1769a29ceSTzu-En Huang /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2769a29ceSTzu-En Huang /* Copyright(c) 2018-2019 Realtek Corporation
3769a29ceSTzu-En Huang */
4769a29ceSTzu-En Huang
5769a29ceSTzu-En Huang #ifndef __RTW8821C_H__
6769a29ceSTzu-En Huang #define __RTW8821C_H__
7769a29ceSTzu-En Huang
8769a29ceSTzu-En Huang #include <asm/byteorder.h>
9769a29ceSTzu-En Huang
10769a29ceSTzu-En Huang #define RCR_VHT_ACK BIT(26)
11769a29ceSTzu-En Huang
12aff5ffd7SSascha Hauer struct rtw8821cu_efuse {
13aff5ffd7SSascha Hauer u8 res4[4]; /* 0xd0 */
14aff5ffd7SSascha Hauer u8 usb_optional_function;
15aff5ffd7SSascha Hauer u8 res5[0x1e];
16aff5ffd7SSascha Hauer u8 res6[2];
17aff5ffd7SSascha Hauer u8 serial[0x0b]; /* 0xf5 */
18aff5ffd7SSascha Hauer u8 vid; /* 0x100 */
19aff5ffd7SSascha Hauer u8 res7;
20aff5ffd7SSascha Hauer u8 pid;
21aff5ffd7SSascha Hauer u8 res8[4];
22aff5ffd7SSascha Hauer u8 mac_addr[ETH_ALEN]; /* 0x107 */
23aff5ffd7SSascha Hauer u8 res9[2];
24aff5ffd7SSascha Hauer u8 vendor_name[0x07];
25aff5ffd7SSascha Hauer u8 res10[2];
26aff5ffd7SSascha Hauer u8 device_name[0x14];
27aff5ffd7SSascha Hauer u8 res11[0xcf];
28aff5ffd7SSascha Hauer u8 package_type; /* 0x1fb */
29aff5ffd7SSascha Hauer u8 res12[0x4];
30aff5ffd7SSascha Hauer };
31aff5ffd7SSascha Hauer
32769a29ceSTzu-En Huang struct rtw8821ce_efuse {
33769a29ceSTzu-En Huang u8 mac_addr[ETH_ALEN]; /* 0xd0 */
34769a29ceSTzu-En Huang u8 vender_id[2];
35769a29ceSTzu-En Huang u8 device_id[2];
36769a29ceSTzu-En Huang u8 sub_vender_id[2];
37769a29ceSTzu-En Huang u8 sub_device_id[2];
38769a29ceSTzu-En Huang u8 pmc[2];
39769a29ceSTzu-En Huang u8 exp_device_cap[2];
40769a29ceSTzu-En Huang u8 msi_cap;
41769a29ceSTzu-En Huang u8 ltr_cap; /* 0xe3 */
42769a29ceSTzu-En Huang u8 exp_link_control[2];
43769a29ceSTzu-En Huang u8 link_cap[4];
44769a29ceSTzu-En Huang u8 link_control[2];
45769a29ceSTzu-En Huang u8 serial_number[8];
46769a29ceSTzu-En Huang u8 res0:2; /* 0xf4 */
47769a29ceSTzu-En Huang u8 ltr_en:1;
48769a29ceSTzu-En Huang u8 res1:2;
49769a29ceSTzu-En Huang u8 obff:2;
50769a29ceSTzu-En Huang u8 res2:3;
51769a29ceSTzu-En Huang u8 obff_cap:2;
52769a29ceSTzu-En Huang u8 res3:4;
53769a29ceSTzu-En Huang u8 res4[3];
54769a29ceSTzu-En Huang u8 class_code[3];
55769a29ceSTzu-En Huang u8 pci_pm_L1_2_supp:1;
56769a29ceSTzu-En Huang u8 pci_pm_L1_1_supp:1;
57769a29ceSTzu-En Huang u8 aspm_pm_L1_2_supp:1;
58769a29ceSTzu-En Huang u8 aspm_pm_L1_1_supp:1;
59769a29ceSTzu-En Huang u8 L1_pm_substates_supp:1;
60769a29ceSTzu-En Huang u8 res5:3;
61769a29ceSTzu-En Huang u8 port_common_mode_restore_time;
62769a29ceSTzu-En Huang u8 port_t_power_on_scale:2;
63769a29ceSTzu-En Huang u8 res6:1;
64769a29ceSTzu-En Huang u8 port_t_power_on_value:5;
65769a29ceSTzu-En Huang u8 res7;
66769a29ceSTzu-En Huang };
67769a29ceSTzu-En Huang
6864e9d564SMartin Blumenstingl struct rtw8821cs_efuse {
6964e9d564SMartin Blumenstingl u8 res4[0x4a]; /* 0xd0 */
7064e9d564SMartin Blumenstingl u8 mac_addr[ETH_ALEN]; /* 0x11a */
7164e9d564SMartin Blumenstingl } __packed;
7264e9d564SMartin Blumenstingl
73769a29ceSTzu-En Huang struct rtw8821c_efuse {
74769a29ceSTzu-En Huang __le16 rtl_id;
75769a29ceSTzu-En Huang u8 res0[0x0e];
76769a29ceSTzu-En Huang
77769a29ceSTzu-En Huang /* power index for four RF paths */
78769a29ceSTzu-En Huang struct rtw_txpwr_idx txpwr_idx_table[4];
79769a29ceSTzu-En Huang
80769a29ceSTzu-En Huang u8 channel_plan; /* 0xb8 */
81769a29ceSTzu-En Huang u8 xtal_k;
82769a29ceSTzu-En Huang u8 thermal_meter;
83769a29ceSTzu-En Huang u8 iqk_lck;
84769a29ceSTzu-En Huang u8 pa_type; /* 0xbc */
85769a29ceSTzu-En Huang u8 lna_type_2g[2]; /* 0xbd */
86769a29ceSTzu-En Huang u8 lna_type_5g[2];
87769a29ceSTzu-En Huang u8 rf_board_option;
88769a29ceSTzu-En Huang u8 rf_feature_option;
89769a29ceSTzu-En Huang u8 rf_bt_setting;
90769a29ceSTzu-En Huang u8 eeprom_version;
91769a29ceSTzu-En Huang u8 eeprom_customer_id;
92769a29ceSTzu-En Huang u8 tx_bb_swing_setting_2g;
93769a29ceSTzu-En Huang u8 tx_bb_swing_setting_5g;
94769a29ceSTzu-En Huang u8 tx_pwr_calibrate_rate;
95769a29ceSTzu-En Huang u8 rf_antenna_option; /* 0xc9 */
96769a29ceSTzu-En Huang u8 rfe_option;
97769a29ceSTzu-En Huang u8 country_code[2];
98769a29ceSTzu-En Huang u8 res[3];
99769a29ceSTzu-En Huang union {
100769a29ceSTzu-En Huang struct rtw8821ce_efuse e;
101aff5ffd7SSascha Hauer struct rtw8821cu_efuse u;
10264e9d564SMartin Blumenstingl struct rtw8821cs_efuse s;
103769a29ceSTzu-En Huang };
104769a29ceSTzu-En Huang };
105769a29ceSTzu-En Huang
106769a29ceSTzu-En Huang static inline void
_rtw_write32s_mask(struct rtw_dev * rtwdev,u32 addr,u32 mask,u32 data)107769a29ceSTzu-En Huang _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
108769a29ceSTzu-En Huang {
109769a29ceSTzu-En Huang /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
110769a29ceSTzu-En Huang rtw_write32_mask(rtwdev, addr, mask, data);
111769a29ceSTzu-En Huang rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
112769a29ceSTzu-En Huang }
113769a29ceSTzu-En Huang
11489d8f53fSLarry Finger extern const struct rtw_chip_info rtw8821c_hw_spec;
11589d8f53fSLarry Finger
116769a29ceSTzu-En Huang #define rtw_write32s_mask(rtwdev, addr, mask, data) \
117769a29ceSTzu-En Huang do { \
118769a29ceSTzu-En Huang BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
119769a29ceSTzu-En Huang \
120769a29ceSTzu-En Huang _rtw_write32s_mask(rtwdev, addr, mask, data); \
121769a29ceSTzu-En Huang } while (0)
122769a29ceSTzu-En Huang
123769a29ceSTzu-En Huang #define BIT_FEN_PCIEA BIT(6)
124769a29ceSTzu-En Huang #define WLAN_SLOT_TIME 0x09
125769a29ceSTzu-En Huang #define WLAN_PIFS_TIME 0x19
126769a29ceSTzu-En Huang #define WLAN_SIFS_CCK_CONT_TX 0xA
127769a29ceSTzu-En Huang #define WLAN_SIFS_OFDM_CONT_TX 0xE
128769a29ceSTzu-En Huang #define WLAN_SIFS_CCK_TRX 0x10
129769a29ceSTzu-En Huang #define WLAN_SIFS_OFDM_TRX 0x10
130769a29ceSTzu-En Huang #define WLAN_VO_TXOP_LIMIT 0x186
131769a29ceSTzu-En Huang #define WLAN_VI_TXOP_LIMIT 0x3BC
132769a29ceSTzu-En Huang #define WLAN_RDG_NAV 0x05
133769a29ceSTzu-En Huang #define WLAN_TXOP_NAV 0x1B
134769a29ceSTzu-En Huang #define WLAN_CCK_RX_TSF 0x30
135769a29ceSTzu-En Huang #define WLAN_OFDM_RX_TSF 0x30
136769a29ceSTzu-En Huang #define WLAN_TBTT_PROHIBIT 0x04
137769a29ceSTzu-En Huang #define WLAN_TBTT_HOLD_TIME 0x064
138769a29ceSTzu-En Huang #define WLAN_DRV_EARLY_INT 0x04
139769a29ceSTzu-En Huang #define WLAN_BCN_DMA_TIME 0x02
140769a29ceSTzu-En Huang
141769a29ceSTzu-En Huang #define WLAN_RX_FILTER0 0x0FFFFFFF
142769a29ceSTzu-En Huang #define WLAN_RX_FILTER2 0xFFFF
143769a29ceSTzu-En Huang #define WLAN_RCR_CFG 0xE400220E
144769a29ceSTzu-En Huang #define WLAN_RXPKT_MAX_SZ 12288
145769a29ceSTzu-En Huang #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
146769a29ceSTzu-En Huang
147769a29ceSTzu-En Huang #define WLAN_AMPDU_MAX_TIME 0x70
148769a29ceSTzu-En Huang #define WLAN_RTS_LEN_TH 0xFF
149769a29ceSTzu-En Huang #define WLAN_RTS_TX_TIME_TH 0x08
150769a29ceSTzu-En Huang #define WLAN_MAX_AGG_PKT_LIMIT 0x20
151769a29ceSTzu-En Huang #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
152769a29ceSTzu-En Huang #define FAST_EDCA_VO_TH 0x06
153769a29ceSTzu-En Huang #define FAST_EDCA_VI_TH 0x06
154769a29ceSTzu-En Huang #define FAST_EDCA_BE_TH 0x06
155769a29ceSTzu-En Huang #define FAST_EDCA_BK_TH 0x06
156769a29ceSTzu-En Huang #define WLAN_BAR_RETRY_LIMIT 0x01
157769a29ceSTzu-En Huang #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
158769a29ceSTzu-En Huang
159769a29ceSTzu-En Huang #define WLAN_TX_FUNC_CFG1 0x30
160769a29ceSTzu-En Huang #define WLAN_TX_FUNC_CFG2 0x30
161769a29ceSTzu-En Huang #define WLAN_MAC_OPT_NORM_FUNC1 0x98
162769a29ceSTzu-En Huang #define WLAN_MAC_OPT_LB_FUNC1 0x80
163c1afb267SPo-Hao Huang #define WLAN_MAC_OPT_FUNC2 0xb0810041
164769a29ceSTzu-En Huang
165769a29ceSTzu-En Huang #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
166769a29ceSTzu-En Huang (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
167769a29ceSTzu-En Huang (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
168769a29ceSTzu-En Huang (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
169769a29ceSTzu-En Huang
170769a29ceSTzu-En Huang #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
171769a29ceSTzu-En Huang (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
172769a29ceSTzu-En Huang
173769a29ceSTzu-En Huang #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
174769a29ceSTzu-En Huang #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
175769a29ceSTzu-En Huang #define WLAN_PRE_TXCNT_TIME_TH 0x1E4
176769a29ceSTzu-En Huang
177d1904061STzu-En Huang /* phy status page0 */
178d1904061STzu-En Huang #define GET_PHY_STAT_P0_PWDB(phy_stat) \
179d1904061STzu-En Huang le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
180b0d3016fSGuo-Feng Fan #define GET_PHY_STAT_P0_VGA(phy_stat) \
181b0d3016fSGuo-Feng Fan le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8))
182b0d3016fSGuo-Feng Fan #define GET_PHY_STAT_P0_LNA_L(phy_stat) \
183b0d3016fSGuo-Feng Fan le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13))
184b0d3016fSGuo-Feng Fan #define GET_PHY_STAT_P0_LNA_H(phy_stat) \
185b0d3016fSGuo-Feng Fan le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23))
186b0d3016fSGuo-Feng Fan #define BIT_LNA_H_MASK BIT(3)
187b0d3016fSGuo-Feng Fan #define BIT_LNA_L_MASK GENMASK(2, 0)
188d1904061STzu-En Huang
189d1904061STzu-En Huang /* phy status page1 */
190d1904061STzu-En Huang #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
191d1904061STzu-En Huang le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
192d1904061STzu-En Huang #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
193d1904061STzu-En Huang le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
194d1904061STzu-En Huang #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
195d1904061STzu-En Huang le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
196d1904061STzu-En Huang #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
197d1904061STzu-En Huang le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
198d1904061STzu-En Huang #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
199d1904061STzu-En Huang le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
2007b080e08SPing-Cheng Chen #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
2017b080e08SPing-Cheng Chen le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
2027b080e08SPing-Cheng Chen #define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
2037b080e08SPing-Cheng Chen le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
2047b080e08SPing-Cheng Chen #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
2057b080e08SPing-Cheng Chen le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
2067b080e08SPing-Cheng Chen #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
2077b080e08SPing-Cheng Chen le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
2087b080e08SPing-Cheng Chen #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
2097b080e08SPing-Cheng Chen le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
2107b080e08SPing-Cheng Chen #define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
2117b080e08SPing-Cheng Chen le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
212d1904061STzu-En Huang
2135d6651feSGuo-Feng Fan #define REG_SYS_CTRL 0x000
2145d6651feSGuo-Feng Fan #define BIT_FEN_EN BIT(26)
215769a29ceSTzu-En Huang #define REG_INIRTS_RATE_SEL 0x0480
216769a29ceSTzu-En Huang #define REG_HTSTFWT 0x800
217769a29ceSTzu-En Huang #define REG_RXPSEL 0x808
218769a29ceSTzu-En Huang #define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
219769a29ceSTzu-En Huang #define REG_TXPSEL 0x80c
220769a29ceSTzu-En Huang #define REG_RXCCAMSK 0x814
221769a29ceSTzu-En Huang #define REG_CCASEL 0x82c
222769a29ceSTzu-En Huang #define REG_PDMFTH 0x830
223769a29ceSTzu-En Huang #define REG_CCA2ND 0x838
224769a29ceSTzu-En Huang #define REG_L1WT 0x83c
225769a29ceSTzu-En Huang #define REG_L1PKWT 0x840
226769a29ceSTzu-En Huang #define REG_MRC 0x850
227769a29ceSTzu-En Huang #define REG_CLKTRK 0x860
228769a29ceSTzu-En Huang #define REG_ADCCLK 0x8ac
229769a29ceSTzu-En Huang #define REG_ADC160 0x8c4
230769a29ceSTzu-En Huang #define REG_ADC40 0x8c8
23158eb40c9STzu-En Huang #define REG_CHFIR 0x8f0
232769a29ceSTzu-En Huang #define REG_CDDTXP 0x93c
233769a29ceSTzu-En Huang #define REG_TXPSEL1 0x940
234769a29ceSTzu-En Huang #define REG_ACBB0 0x948
235769a29ceSTzu-En Huang #define REG_ACBBRXFIR 0x94c
236769a29ceSTzu-En Huang #define REG_ACGG2TBL 0x958
23796036123STzu-En Huang #define REG_FAS 0x9a4
238769a29ceSTzu-En Huang #define REG_RXSB 0xa00
239769a29ceSTzu-En Huang #define REG_ADCINI 0xa04
24011fcb119STzu-En Huang #define REG_PWRTH 0xa08
241*14a5b115SZong-Zhe Yang #define REG_CCA_FLTR 0xa20
242769a29ceSTzu-En Huang #define REG_TXSF2 0xa24
243769a29ceSTzu-En Huang #define REG_TXSF6 0xa28
24496036123STzu-En Huang #define REG_FA_CCK 0xa5c
245769a29ceSTzu-En Huang #define REG_RXDESC 0xa2c
246769a29ceSTzu-En Huang #define REG_ENTXCCK 0xa80
2475d6651feSGuo-Feng Fan #define BTG_LNA 0xfc84
2485d6651feSGuo-Feng Fan #define WLG_LNA 0x7532
2495d6651feSGuo-Feng Fan #define REG_ENRXCCA 0xa84
2505d6651feSGuo-Feng Fan #define BTG_CCA 0x0e
2515d6651feSGuo-Feng Fan #define WLG_CCA 0x12
25211fcb119STzu-En Huang #define REG_PWRTH2 0xaa8
25311fcb119STzu-En Huang #define REG_CSRATIO 0xaaa
25458eb40c9STzu-En Huang #define REG_TXFILTER 0xaac
25596036123STzu-En Huang #define REG_CNTRST 0xb58
256769a29ceSTzu-En Huang #define REG_AGCTR_A 0xc08
25758eb40c9STzu-En Huang #define REG_TXSCALE_A 0xc1c
258769a29ceSTzu-En Huang #define REG_TXDFIR 0xc20
259769a29ceSTzu-En Huang #define REG_RXIGI_A 0xc50
2603a431282STzu-En Huang #define REG_TXAGCIDX 0xc94
261769a29ceSTzu-En Huang #define REG_TRSW 0xca0
262769a29ceSTzu-En Huang #define REG_RFESEL0 0xcb0
263769a29ceSTzu-En Huang #define REG_RFESEL8 0xcb4
264769a29ceSTzu-En Huang #define REG_RFECTL 0xcb8
2655d6651feSGuo-Feng Fan #define B_BTG_SWITCH BIT(16)
2665d6651feSGuo-Feng Fan #define B_CTRL_SWITCH BIT(18)
2675d6651feSGuo-Feng Fan #define B_WL_SWITCH (BIT(20) | BIT(22))
2685d6651feSGuo-Feng Fan #define B_WLG_SWITCH BIT(21)
2695d6651feSGuo-Feng Fan #define B_WLA_SWITCH BIT(23)
270769a29ceSTzu-En Huang #define REG_RFEINV 0xcbc
271769a29ceSTzu-En Huang #define REG_AGCTR_B 0xe08
272769a29ceSTzu-En Huang #define REG_RXIGI_B 0xe50
27396036123STzu-En Huang #define REG_CRC_CCK 0xf04
27496036123STzu-En Huang #define REG_CRC_OFDM 0xf14
27596036123STzu-En Huang #define REG_CRC_HT 0xf10
27696036123STzu-En Huang #define REG_CRC_VHT 0xf0c
27796036123STzu-En Huang #define REG_CCA_OFDM 0xf08
27896036123STzu-En Huang #define REG_FA_OFDM 0xf48
27996036123STzu-En Huang #define REG_CCA_CCK 0xfcc
2805d6651feSGuo-Feng Fan #define REG_DMEM_CTRL 0x1080
2815d6651feSGuo-Feng Fan #define BIT_WL_RST BIT(16)
282769a29ceSTzu-En Huang #define REG_ANTWT 0x1904
283769a29ceSTzu-En Huang #define REG_IQKFAILMSK 0x1bf0
2847b080e08SPing-Cheng Chen #define BIT_MASK_R_RFE_SEL_15 GENMASK(31, 28)
2857b080e08SPing-Cheng Chen #define BIT_SDIO_INT BIT(18)
2867b080e08SPing-Cheng Chen #define BT_CNT_ENABLE 0x1
2877b080e08SPing-Cheng Chen #define BIT_BCN_QUEUE BIT(3)
2887b080e08SPing-Cheng Chen #define BCN_PRI_EN 0x1
2897b080e08SPing-Cheng Chen #define PTA_CTRL_PIN 0x66
2907b080e08SPing-Cheng Chen #define DPDT_CTRL_PIN 0x77
2917b080e08SPing-Cheng Chen #define ANTDIC_CTRL_PIN 0x88
2927b080e08SPing-Cheng Chen #define REG_CTRL_TYPE 0x67
2937b080e08SPing-Cheng Chen #define BIT_CTRL_TYPE1 BIT(5)
2947b080e08SPing-Cheng Chen #define BIT_CTRL_TYPE2 BIT(4)
2957b080e08SPing-Cheng Chen #define CTRL_TYPE_MASK GENMASK(15, 8)
296769a29ceSTzu-En Huang
29758eb40c9STzu-En Huang #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
29858eb40c9STzu-En Huang #define RF18_BAND_2G (0)
29958eb40c9STzu-En Huang #define RF18_BAND_5G (BIT(16) | BIT(8))
30058eb40c9STzu-En Huang #define RF18_CHANNEL_MASK (MASKBYTE0)
30158eb40c9STzu-En Huang #define RF18_RFSI_MASK (BIT(18) | BIT(17))
30258eb40c9STzu-En Huang #define RF18_RFSI_GE (BIT(17))
30358eb40c9STzu-En Huang #define RF18_RFSI_GT (BIT(18))
30458eb40c9STzu-En Huang #define RF18_BW_MASK (BIT(11) | BIT(10))
30558eb40c9STzu-En Huang #define RF18_BW_20M (BIT(11) | BIT(10))
30658eb40c9STzu-En Huang #define RF18_BW_40M (BIT(11))
30758eb40c9STzu-En Huang #define RF18_BW_80M (BIT(10))
30858eb40c9STzu-En Huang
309769a29ceSTzu-En Huang #endif
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