1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 #include "regd.h" 18 19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; 20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, 21 -20, -24, -28, -31, -34, -37, -40, -44}; 22 23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8821c_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse, 30 struct rtw8821c_efuse *map) 31 { 32 ether_addr_copy(efuse->addr, map->u.mac_addr); 33 } 34 35 static void rtw8821cs_efuse_parsing(struct rtw_efuse *efuse, 36 struct rtw8821c_efuse *map) 37 { 38 ether_addr_copy(efuse->addr, map->s.mac_addr); 39 } 40 41 enum rtw8821ce_rf_set { 42 SWITCH_TO_BTG, 43 SWITCH_TO_WLG, 44 SWITCH_TO_WLA, 45 SWITCH_TO_BT, 46 }; 47 48 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 49 { 50 struct rtw_hal *hal = &rtwdev->hal; 51 struct rtw_efuse *efuse = &rtwdev->efuse; 52 struct rtw8821c_efuse *map; 53 int i; 54 55 map = (struct rtw8821c_efuse *)log_map; 56 57 efuse->rfe_option = map->rfe_option & 0x1f; 58 efuse->rf_board_option = map->rf_board_option; 59 efuse->crystal_cap = map->xtal_k; 60 efuse->pa_type_2g = map->pa_type; 61 efuse->pa_type_5g = map->pa_type; 62 efuse->lna_type_2g = map->lna_type_2g[0]; 63 efuse->lna_type_5g = map->lna_type_5g[0]; 64 efuse->channel_plan = map->channel_plan; 65 efuse->country_code[0] = map->country_code[0]; 66 efuse->country_code[1] = map->country_code[1]; 67 efuse->bt_setting = map->rf_bt_setting; 68 efuse->regd = map->rf_board_option & 0x7; 69 efuse->thermal_meter[0] = map->thermal_meter; 70 efuse->thermal_meter_k = map->thermal_meter; 71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 73 74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; 75 76 switch (efuse->rfe_option) { 77 case 0x2: 78 case 0x4: 79 case 0x7: 80 case 0xa: 81 case 0xc: 82 case 0xf: 83 hal->rfe_btg = true; 84 break; 85 } 86 87 for (i = 0; i < 4; i++) 88 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 89 90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) 91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; 92 93 switch (rtw_hci_type(rtwdev)) { 94 case RTW_HCI_TYPE_PCIE: 95 rtw8821ce_efuse_parsing(efuse, map); 96 break; 97 case RTW_HCI_TYPE_USB: 98 rtw8821cu_efuse_parsing(efuse, map); 99 break; 100 case RTW_HCI_TYPE_SDIO: 101 rtw8821cs_efuse_parsing(efuse, map); 102 break; 103 default: 104 /* unsupported now */ 105 return -ENOTSUPP; 106 } 107 108 return 0; 109 } 110 111 static const u32 rtw8821c_txscale_tbl[] = { 112 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 113 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 114 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 115 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 116 }; 117 118 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 119 { 120 u8 i = 0; 121 u32 swing, table_value; 122 123 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 124 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 125 table_value = rtw8821c_txscale_tbl[i]; 126 if (swing == table_value) 127 break; 128 } 129 130 return i; 131 } 132 133 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 134 { 135 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 136 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 137 138 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 139 dm_info->default_ofdm_index = 24; 140 else 141 dm_info->default_ofdm_index = swing_idx; 142 143 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 144 dm_info->delta_power_index[RF_PATH_A] = 0; 145 dm_info->delta_power_index_last[RF_PATH_A] = 0; 146 dm_info->pwr_trk_triggered = false; 147 dm_info->pwr_trk_init_trigger = true; 148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 149 } 150 151 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 152 { 153 rtw_bf_phy_init(rtwdev); 154 /* Grouping bitmap parameters */ 155 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 156 } 157 158 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 159 { 160 struct rtw_hal *hal = &rtwdev->hal; 161 u8 crystal_cap, val; 162 163 /* power on BB/RF domain */ 164 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 165 val |= BIT_FEN_PCIEA; 166 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 167 168 /* toggle BB reset */ 169 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 170 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 171 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 172 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 173 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 174 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 175 176 rtw_write8(rtwdev, REG_RF_CTRL, 177 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 178 usleep_range(10, 11); 179 rtw_write8(rtwdev, REG_WLRF1 + 3, 180 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 181 usleep_range(10, 11); 182 183 /* pre init before header files config */ 184 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 185 186 rtw_phy_load_tables(rtwdev); 187 188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 192 193 /* post init after header files config */ 194 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 198 199 rtw_phy_init(rtwdev); 200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 201 202 rtw8821c_pwrtrack_init(rtwdev); 203 204 rtw8821c_phy_bf_init(rtwdev); 205 } 206 207 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 208 { 209 u32 value32; 210 u16 pre_txcnt; 211 212 /* protocol configuration */ 213 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 214 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 215 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 216 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 217 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 218 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 219 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 220 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 221 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 222 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 223 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 224 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 225 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 226 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 227 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 229 230 /* EDCA configuration */ 231 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 232 rtw_write16(rtwdev, REG_TXPAUSE, 0); 233 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 234 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 235 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 236 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 237 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 238 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 239 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 240 241 /* Set beacon cotnrol - enable TSF and other related functions */ 242 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 243 244 /* Set send beacon related registers */ 245 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 246 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 247 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 248 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 249 250 /* WMAC configuration */ 251 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 252 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 253 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 254 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 255 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 256 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 257 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 259 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 260 BIT_DIS_CHK_VHTSIGB_CRC); 261 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 262 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 263 264 return 0; 265 } 266 267 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 268 { 269 u8 ldo_pwr; 270 271 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 273 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 274 } 275 276 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) 277 { 278 u32 reg; 279 280 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST); 281 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN); 282 283 reg = rtw_read32(rtwdev, REG_RFECTL); 284 switch (rf_set) { 285 case SWITCH_TO_BTG: 286 reg |= B_BTG_SWITCH; 287 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH | 288 B_WLA_SWITCH); 289 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); 290 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); 291 break; 292 case SWITCH_TO_WLG: 293 reg |= B_WL_SWITCH | B_WLG_SWITCH; 294 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH); 295 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); 296 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); 297 break; 298 case SWITCH_TO_WLA: 299 reg |= B_WL_SWITCH | B_WLA_SWITCH; 300 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH); 301 break; 302 case SWITCH_TO_BT: 303 default: 304 break; 305 } 306 307 rtw_write32(rtwdev, REG_RFECTL, reg); 308 } 309 310 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 311 { 312 struct rtw_hal *hal = &rtwdev->hal; 313 u32 rf_reg18; 314 315 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 316 317 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 318 RF18_BW_MASK); 319 320 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 321 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 322 323 if (channel >= 100 && channel <= 140) 324 rf_reg18 |= RF18_RFSI_GE; 325 else if (channel > 140) 326 rf_reg18 |= RF18_RFSI_GT; 327 328 switch (bw) { 329 case RTW_CHANNEL_WIDTH_5: 330 case RTW_CHANNEL_WIDTH_10: 331 case RTW_CHANNEL_WIDTH_20: 332 default: 333 rf_reg18 |= RF18_BW_20M; 334 break; 335 case RTW_CHANNEL_WIDTH_40: 336 rf_reg18 |= RF18_BW_40M; 337 break; 338 case RTW_CHANNEL_WIDTH_80: 339 rf_reg18 |= RF18_BW_80M; 340 break; 341 } 342 343 if (channel <= 14) { 344 if (hal->rfe_btg) 345 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG); 346 else 347 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG); 348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 349 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 350 } else { 351 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA); 352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 353 } 354 355 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 356 357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 359 } 360 361 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 362 { 363 if (bw == RTW_CHANNEL_WIDTH_40) { 364 /* RX DFIR for BW40 */ 365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 369 } else if (bw == RTW_CHANNEL_WIDTH_80) { 370 /* RX DFIR for BW80 */ 371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 375 } else { 376 /* RX DFIR for BW20, BW10 and BW5 */ 377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 381 } 382 } 383 384 static void rtw8821c_cck_tx_filter_srrc(struct rtw_dev *rtwdev, u8 channel, u8 bw) 385 { 386 struct rtw_hal *hal = &rtwdev->hal; 387 388 if (channel == 14) { 389 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); 390 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 391 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 392 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 393 394 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); 395 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); 396 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 397 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); 398 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 399 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); 400 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 401 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); 402 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 403 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); 404 } else if (channel == 13 || 405 (channel == 11 && bw == RTW_CHANNEL_WIDTH_40)) { 406 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe); 407 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c); 408 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810); 409 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667); 410 411 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); 412 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); 413 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); 414 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); 415 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); 416 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); 417 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029); 418 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); 419 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026); 420 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); 421 } else { 422 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); 423 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 424 hal->ch_param[0]); 425 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 426 hal->ch_param[1] & MASKLWORD); 427 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 428 hal->ch_param[2]); 429 430 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); 431 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); 432 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 433 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); 434 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 435 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); 436 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 437 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); 438 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); 439 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); 440 } 441 } 442 443 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 444 u8 primary_ch_idx) 445 { 446 struct rtw_hal *hal = &rtwdev->hal; 447 u32 val32; 448 449 if (channel <= 14) { 450 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 451 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 452 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 453 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 454 455 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 456 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 457 458 if (rtw_regd_srrc(rtwdev)) { 459 rtw8821c_cck_tx_filter_srrc(rtwdev, channel, bw); 460 goto set_bw; 461 } 462 463 /* CCK TX filter parameters for default case */ 464 if (channel == 14) { 465 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 466 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 467 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 468 } else { 469 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 470 hal->ch_param[0]); 471 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 472 hal->ch_param[1] & MASKLWORD); 473 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 474 hal->ch_param[2]); 475 } 476 } else if (channel > 35) { 477 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 478 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 479 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 480 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 481 482 if (channel >= 36 && channel <= 64) 483 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 484 else if (channel >= 100 && channel <= 144) 485 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 486 else if (channel >= 149) 487 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 488 489 if (channel >= 36 && channel <= 48) 490 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 491 else if (channel >= 52 && channel <= 64) 492 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 493 else if (channel >= 100 && channel <= 116) 494 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 495 else if (channel >= 118 && channel <= 177) 496 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 497 } 498 499 set_bw: 500 switch (bw) { 501 case RTW_CHANNEL_WIDTH_20: 502 default: 503 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 504 val32 &= 0xffcffc00; 505 val32 |= 0x10010000; 506 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 507 508 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 509 break; 510 case RTW_CHANNEL_WIDTH_40: 511 if (primary_ch_idx == 1) 512 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 513 else 514 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 515 516 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 517 val32 &= 0xff3ff300; 518 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 519 RTW_CHANNEL_WIDTH_40; 520 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 521 522 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 523 break; 524 case RTW_CHANNEL_WIDTH_80: 525 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 526 val32 &= 0xfcffcf00; 527 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 528 RTW_CHANNEL_WIDTH_80; 529 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 530 531 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 532 break; 533 case RTW_CHANNEL_WIDTH_5: 534 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 535 val32 &= 0xefcefc00; 536 val32 |= 0x200240; 537 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 538 539 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 540 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 541 break; 542 case RTW_CHANNEL_WIDTH_10: 543 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 544 val32 &= 0xefcefc00; 545 val32 |= 0x300380; 546 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 547 548 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 549 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 550 break; 551 } 552 } 553 554 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 555 { 556 struct rtw_efuse efuse = rtwdev->efuse; 557 u8 tx_bb_swing; 558 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 559 560 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 561 efuse.tx_bb_swing_setting_5g; 562 if (tx_bb_swing > 9) 563 tx_bb_swing = 0; 564 565 return swing2setting[(tx_bb_swing / 3)]; 566 } 567 568 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 569 u8 bw, u8 primary_ch_idx) 570 { 571 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 572 rtw8821c_get_bb_swing(rtwdev, channel)); 573 rtw8821c_pwrtrack_init(rtwdev); 574 } 575 576 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 577 u8 primary_chan_idx) 578 { 579 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 580 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 581 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 582 rtw8821c_set_channel_rf(rtwdev, channel, bw); 583 rtw8821c_set_channel_rxdfir(rtwdev, bw); 584 } 585 586 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 587 { 588 struct rtw_efuse *efuse = &rtwdev->efuse; 589 const s8 *lna_gain_table; 590 int lna_gain_table_size; 591 s8 rx_pwr_all = 0; 592 s8 lna_gain = 0; 593 594 if (efuse->rfe_option == 0) { 595 lna_gain_table = lna_gain_table_0; 596 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0); 597 } else { 598 lna_gain_table = lna_gain_table_1; 599 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1); 600 } 601 602 if (lna_idx >= lna_gain_table_size) { 603 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 604 return -120; 605 } 606 607 lna_gain = lna_gain_table[lna_idx]; 608 rx_pwr_all = lna_gain - 2 * vga_idx; 609 610 return rx_pwr_all; 611 } 612 613 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 614 struct rtw_rx_pkt_stat *pkt_stat) 615 { 616 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 617 s8 rx_power; 618 u8 lna_idx = 0; 619 u8 vga_idx = 0; 620 621 vga_idx = GET_PHY_STAT_P0_VGA(phy_status); 622 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) | 623 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status)); 624 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 625 626 pkt_stat->rx_power[RF_PATH_A] = rx_power; 627 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 628 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 629 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 630 pkt_stat->signal_power = rx_power; 631 } 632 633 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 634 struct rtw_rx_pkt_stat *pkt_stat) 635 { 636 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 637 u8 rxsc, bw; 638 s8 min_rx_power = -120; 639 640 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 641 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 642 else 643 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 644 645 if (rxsc >= 1 && rxsc <= 8) 646 bw = RTW_CHANNEL_WIDTH_20; 647 else if (rxsc >= 9 && rxsc <= 12) 648 bw = RTW_CHANNEL_WIDTH_40; 649 else if (rxsc >= 13) 650 bw = RTW_CHANNEL_WIDTH_80; 651 else 652 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 653 654 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 655 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 656 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 657 pkt_stat->bw = bw; 658 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 659 min_rx_power); 660 } 661 662 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 663 struct rtw_rx_pkt_stat *pkt_stat) 664 { 665 u8 page; 666 667 page = *phy_status & 0xf; 668 669 switch (page) { 670 case 0: 671 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 672 break; 673 case 1: 674 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 675 break; 676 default: 677 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 678 return; 679 } 680 } 681 682 static void 683 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 684 { 685 struct rtw_hal *hal = &rtwdev->hal; 686 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 687 static u32 phy_pwr_idx; 688 u8 rate, rate_idx, pwr_index, shift; 689 int j; 690 691 for (j = 0; j < rtw_rate_size[rs]; j++) { 692 rate = rtw_rate_section[rs][j]; 693 pwr_index = hal->tx_pwr_tbl[path][rate]; 694 shift = rate & 0x3; 695 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 696 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 697 rate_idx = rate & 0xfc; 698 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 699 phy_pwr_idx); 700 phy_pwr_idx = 0; 701 } 702 } 703 } 704 705 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 706 { 707 struct rtw_hal *hal = &rtwdev->hal; 708 int rs, path; 709 710 for (path = 0; path < hal->rf_path_num; path++) { 711 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 712 if (rs == RTW_RATE_SECTION_HT_2S || 713 rs == RTW_RATE_SECTION_VHT_2S) 714 continue; 715 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 716 } 717 } 718 } 719 720 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 721 { 722 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 723 u32 cck_enable; 724 u32 cck_fa_cnt; 725 u32 ofdm_fa_cnt; 726 u32 crc32_cnt; 727 u32 cca32_cnt; 728 729 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 730 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 731 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 732 733 dm_info->cck_fa_cnt = cck_fa_cnt; 734 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 735 dm_info->total_fa_cnt = ofdm_fa_cnt; 736 if (cck_enable) 737 dm_info->total_fa_cnt += cck_fa_cnt; 738 739 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 740 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 741 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 742 743 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 744 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 745 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 746 747 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 748 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 749 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 750 751 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 752 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 753 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 754 755 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 756 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 757 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 758 if (cck_enable) { 759 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 760 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 761 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 762 } 763 764 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 765 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 766 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 767 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 768 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 769 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 770 } 771 772 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 773 { 774 static int do_iqk_cnt; 775 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 776 u32 rf_reg, iqk_fail_mask; 777 int counter; 778 bool reload; 779 780 if (rtw_is_assoc(rtwdev)) 781 para.segment_iqk = 1; 782 783 rtw_fw_do_iqk(rtwdev, ¶); 784 785 for (counter = 0; counter < 300; counter++) { 786 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 787 if (rf_reg == 0xabcde) 788 break; 789 msleep(20); 790 } 791 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 792 793 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 794 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 795 rtw_dbg(rtwdev, RTW_DBG_PHY, 796 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 797 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 798 } 799 800 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 801 { 802 rtw8821c_do_iqk(rtwdev); 803 } 804 805 /* for coex */ 806 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 807 { 808 /* enable TBTT nterrupt */ 809 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 810 811 /* BT report packet sample rate */ 812 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 813 814 /* enable BT counter statistics */ 815 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 816 817 /* enable PTA (3-wire function form BT side) */ 818 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 819 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 820 821 /* enable PTA (tx/rx signal form WiFi side) */ 822 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 823 /* wl tx signal to PTA not case EDCCA */ 824 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 825 /* GNT_BT=1 while select both */ 826 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 827 828 /* beacon queue always hi-pri */ 829 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 830 BCN_PRI_EN); 831 } 832 833 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 834 u8 pos_type) 835 { 836 struct rtw_coex *coex = &rtwdev->coex; 837 struct rtw_coex_dm *coex_dm = &coex->dm; 838 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 839 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 840 bool polarity_inverse; 841 u8 regval = 0; 842 843 if (switch_status == coex_dm->cur_switch_status) 844 return; 845 846 if (coex_rfe->wlg_at_btg) { 847 ctrl_type = COEX_SWITCH_CTRL_BY_BBSW; 848 849 if (coex_rfe->ant_switch_polarity) 850 pos_type = COEX_SWITCH_TO_WLA; 851 else 852 pos_type = COEX_SWITCH_TO_WLG_BT; 853 } 854 855 coex_dm->cur_switch_status = switch_status; 856 857 if (coex_rfe->ant_switch_diversity && 858 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 859 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 860 861 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 862 863 switch (ctrl_type) { 864 default: 865 case COEX_SWITCH_CTRL_BY_BBSW: 866 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 867 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 868 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 869 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 870 DPDT_CTRL_PIN); 871 872 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 873 if (coex_rfe->rfe_module_type != 0x4 && 874 coex_rfe->rfe_module_type != 0x2) 875 regval = 0x3; 876 else 877 regval = (!polarity_inverse ? 0x2 : 0x1); 878 } else if (pos_type == COEX_SWITCH_TO_WLG) { 879 regval = (!polarity_inverse ? 0x2 : 0x1); 880 } else { 881 regval = (!polarity_inverse ? 0x1 : 0x2); 882 } 883 884 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 885 regval); 886 break; 887 case COEX_SWITCH_CTRL_BY_PTA: 888 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 889 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 890 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 891 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 892 PTA_CTRL_PIN); 893 894 regval = (!polarity_inverse ? 0x2 : 0x1); 895 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 896 regval); 897 break; 898 case COEX_SWITCH_CTRL_BY_ANTDIV: 899 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 900 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 901 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 902 ANTDIC_CTRL_PIN); 903 break; 904 case COEX_SWITCH_CTRL_BY_MAC: 905 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 906 907 regval = (!polarity_inverse ? 0x0 : 0x1); 908 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 909 regval); 910 break; 911 case COEX_SWITCH_CTRL_BY_FW: 912 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 913 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 914 break; 915 case COEX_SWITCH_CTRL_BY_BT: 916 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 917 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 918 break; 919 } 920 921 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 922 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 923 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 924 } else { 925 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 926 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 927 } 928 } 929 930 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 931 {} 932 933 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 934 { 935 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 936 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 937 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 938 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 939 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 940 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 941 } 942 943 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 944 { 945 struct rtw_coex *coex = &rtwdev->coex; 946 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 947 struct rtw_efuse *efuse = &rtwdev->efuse; 948 949 coex_rfe->rfe_module_type = efuse->rfe_option; 950 coex_rfe->ant_switch_polarity = 0; 951 coex_rfe->ant_switch_exist = true; 952 coex_rfe->wlg_at_btg = false; 953 954 switch (coex_rfe->rfe_module_type) { 955 case 0: 956 case 8: 957 case 1: 958 case 9: /* 1-Ant, Main, WLG */ 959 default: /* 2-Ant, DPDT, WLG */ 960 break; 961 case 2: 962 case 10: /* 1-Ant, Main, BTG */ 963 case 7: 964 case 15: /* 2-Ant, DPDT, BTG */ 965 coex_rfe->wlg_at_btg = true; 966 break; 967 case 3: 968 case 11: /* 1-Ant, Aux, WLG */ 969 coex_rfe->ant_switch_polarity = 1; 970 break; 971 case 4: 972 case 12: /* 1-Ant, Aux, BTG */ 973 coex_rfe->wlg_at_btg = true; 974 coex_rfe->ant_switch_polarity = 1; 975 break; 976 case 5: 977 case 13: /* 2-Ant, no switch, WLG */ 978 case 6: 979 case 14: /* 2-Ant, no antenna switch, WLG */ 980 coex_rfe->ant_switch_exist = false; 981 break; 982 } 983 } 984 985 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 986 { 987 struct rtw_coex *coex = &rtwdev->coex; 988 struct rtw_coex_dm *coex_dm = &coex->dm; 989 struct rtw_efuse *efuse = &rtwdev->efuse; 990 bool share_ant = efuse->share_ant; 991 992 if (share_ant) 993 return; 994 995 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 996 return; 997 998 coex_dm->cur_wl_pwr_lvl = wl_pwr; 999 } 1000 1001 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1002 {} 1003 1004 static void 1005 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 1006 s8 pwr_idx_offset_lower, 1007 s8 *txagc_idx, u8 *swing_idx) 1008 { 1009 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1010 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 1011 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 1012 u8 swing_lower_bound = 0; 1013 u8 max_pwr_idx_offset = 0xf; 1014 s8 agc_index = 0; 1015 u8 swing_index = dm_info->default_ofdm_index; 1016 1017 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 1018 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 1019 1020 if (delta_pwr_idx >= 0) { 1021 if (delta_pwr_idx <= pwr_idx_offset) { 1022 agc_index = delta_pwr_idx; 1023 swing_index = dm_info->default_ofdm_index; 1024 } else if (delta_pwr_idx > pwr_idx_offset) { 1025 agc_index = pwr_idx_offset; 1026 swing_index = dm_info->default_ofdm_index + 1027 delta_pwr_idx - pwr_idx_offset; 1028 swing_index = min_t(u8, swing_index, swing_upper_bound); 1029 } 1030 } else if (delta_pwr_idx < 0) { 1031 if (delta_pwr_idx >= pwr_idx_offset_lower) { 1032 agc_index = delta_pwr_idx; 1033 swing_index = dm_info->default_ofdm_index; 1034 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 1035 if (dm_info->default_ofdm_index > 1036 (pwr_idx_offset_lower - delta_pwr_idx)) 1037 swing_index = dm_info->default_ofdm_index + 1038 delta_pwr_idx - pwr_idx_offset_lower; 1039 else 1040 swing_index = swing_lower_bound; 1041 1042 agc_index = pwr_idx_offset_lower; 1043 } 1044 } 1045 1046 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 1047 rtw_warn(rtwdev, "swing index overflow\n"); 1048 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 1049 } 1050 1051 *txagc_idx = agc_index; 1052 *swing_idx = swing_index; 1053 } 1054 1055 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 1056 s8 pwr_idx_offset_lower) 1057 { 1058 s8 txagc_idx; 1059 u8 swing_idx; 1060 1061 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 1062 &txagc_idx, &swing_idx); 1063 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 1064 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 1065 rtw8821c_txscale_tbl[swing_idx]); 1066 } 1067 1068 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 1069 { 1070 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1071 u8 pwr_idx_offset, tx_pwr_idx; 1072 s8 pwr_idx_offset_lower; 1073 u8 channel = rtwdev->hal.current_channel; 1074 u8 band_width = rtwdev->hal.current_band_width; 1075 u8 regd = rtw_regd_get(rtwdev); 1076 u8 tx_rate = dm_info->tx_rate; 1077 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1078 1079 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 1080 band_width, channel, regd); 1081 1082 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1083 1084 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1085 pwr_idx_offset_lower = 0 - tx_pwr_idx; 1086 1087 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 1088 } 1089 1090 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 1091 { 1092 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1093 struct rtw_swing_table swing_table; 1094 u8 thermal_value, delta; 1095 1096 rtw_phy_config_swing_table(rtwdev, &swing_table); 1097 1098 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1099 return; 1100 1101 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1102 1103 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1104 1105 if (dm_info->pwr_trk_init_trigger) 1106 dm_info->pwr_trk_init_trigger = false; 1107 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1108 RF_PATH_A)) 1109 goto iqk; 1110 1111 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1112 1113 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1114 1115 dm_info->delta_power_index[RF_PATH_A] = 1116 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 1117 RF_PATH_A, delta); 1118 if (dm_info->delta_power_index[RF_PATH_A] == 1119 dm_info->delta_power_index_last[RF_PATH_A]) 1120 goto iqk; 1121 else 1122 dm_info->delta_power_index_last[RF_PATH_A] = 1123 dm_info->delta_power_index[RF_PATH_A]; 1124 rtw8821c_pwrtrack_set(rtwdev); 1125 1126 iqk: 1127 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1128 rtw8821c_do_iqk(rtwdev); 1129 } 1130 1131 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 1132 { 1133 struct rtw_efuse *efuse = &rtwdev->efuse; 1134 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1135 1136 if (efuse->power_track_type != 0) 1137 return; 1138 1139 if (!dm_info->pwr_trk_triggered) { 1140 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1141 GENMASK(17, 16), 0x03); 1142 dm_info->pwr_trk_triggered = true; 1143 return; 1144 } 1145 1146 rtw8821c_phy_pwrtrack(rtwdev); 1147 dm_info->pwr_trk_triggered = false; 1148 } 1149 1150 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 1151 struct rtw_vif *vif, 1152 struct rtw_bfee *bfee, bool enable) 1153 { 1154 if (enable) 1155 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1156 else 1157 rtw_bf_remove_bfee_su(rtwdev, bfee); 1158 } 1159 1160 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1161 struct rtw_vif *vif, 1162 struct rtw_bfee *bfee, bool enable) 1163 { 1164 if (enable) 1165 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1166 else 1167 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1168 } 1169 1170 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1171 struct rtw_bfee *bfee, bool enable) 1172 { 1173 if (bfee->role == RTW_BFEE_SU) 1174 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1175 else if (bfee->role == RTW_BFEE_MU) 1176 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1177 else 1178 rtw_warn(rtwdev, "wrong bfee role\n"); 1179 } 1180 1181 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1182 { 1183 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1184 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1185 u8 cck_n_rx; 1186 1187 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1188 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1189 1190 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1191 return; 1192 1193 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1194 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1195 rtw_dbg(rtwdev, RTW_DBG_PHY, 1196 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1197 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1198 dm_info->cck_pd_default + new_lvl * 2, 1199 pd[new_lvl], dm_info->cck_fa_avg); 1200 1201 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1202 1203 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1204 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1205 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1206 dm_info->cck_pd_default + new_lvl * 2); 1207 } 1208 1209 static void rtw8821c_led_set(struct led_classdev *led, 1210 enum led_brightness brightness) 1211 { 1212 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev); 1213 u32 ledcfg; 1214 1215 ledcfg = rtw_read32(rtwdev, REG_LED_CFG); 1216 u32p_replace_bits(&ledcfg, BIT_LED_MODE_SW_CTRL, BIT_LED2_CM); 1217 ledcfg &= ~BIT_GPIO13_14_WL_CTRL_EN; 1218 1219 if (brightness == LED_OFF) 1220 ledcfg |= BIT_LED2_SV; 1221 else 1222 ledcfg &= ~BIT_LED2_SV; 1223 1224 rtw_write32(rtwdev, REG_LED_CFG, ledcfg); 1225 } 1226 1227 static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev, 1228 struct rtw_tx_pkt_info *pkt_info, 1229 u8 *txdesc) 1230 { 1231 fill_txdesc_checksum_common(txdesc, 16); 1232 } 1233 1234 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1235 {0x0086, 1236 RTW_PWR_CUT_ALL_MSK, 1237 RTW_PWR_INTF_SDIO_MSK, 1238 RTW_PWR_ADDR_SDIO, 1239 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1240 {0x0086, 1241 RTW_PWR_CUT_ALL_MSK, 1242 RTW_PWR_INTF_SDIO_MSK, 1243 RTW_PWR_ADDR_SDIO, 1244 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1245 {0x004A, 1246 RTW_PWR_CUT_ALL_MSK, 1247 RTW_PWR_INTF_USB_MSK, 1248 RTW_PWR_ADDR_MAC, 1249 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1250 {0x0005, 1251 RTW_PWR_CUT_ALL_MSK, 1252 RTW_PWR_INTF_ALL_MSK, 1253 RTW_PWR_ADDR_MAC, 1254 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1255 {0x0300, 1256 RTW_PWR_CUT_ALL_MSK, 1257 RTW_PWR_INTF_PCI_MSK, 1258 RTW_PWR_ADDR_MAC, 1259 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1260 {0x0301, 1261 RTW_PWR_CUT_ALL_MSK, 1262 RTW_PWR_INTF_PCI_MSK, 1263 RTW_PWR_ADDR_MAC, 1264 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1265 {0xFFFF, 1266 RTW_PWR_CUT_ALL_MSK, 1267 RTW_PWR_INTF_ALL_MSK, 1268 0, 1269 RTW_PWR_CMD_END, 0, 0}, 1270 }; 1271 1272 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1273 {0x0020, 1274 RTW_PWR_CUT_ALL_MSK, 1275 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1276 RTW_PWR_ADDR_MAC, 1277 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1278 {0x0001, 1279 RTW_PWR_CUT_ALL_MSK, 1280 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1281 RTW_PWR_ADDR_MAC, 1282 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1283 {0x0000, 1284 RTW_PWR_CUT_ALL_MSK, 1285 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1286 RTW_PWR_ADDR_MAC, 1287 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1288 {0x0005, 1289 RTW_PWR_CUT_ALL_MSK, 1290 RTW_PWR_INTF_ALL_MSK, 1291 RTW_PWR_ADDR_MAC, 1292 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1293 {0x0075, 1294 RTW_PWR_CUT_ALL_MSK, 1295 RTW_PWR_INTF_PCI_MSK, 1296 RTW_PWR_ADDR_MAC, 1297 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1298 {0x0006, 1299 RTW_PWR_CUT_ALL_MSK, 1300 RTW_PWR_INTF_ALL_MSK, 1301 RTW_PWR_ADDR_MAC, 1302 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1303 {0x0075, 1304 RTW_PWR_CUT_ALL_MSK, 1305 RTW_PWR_INTF_PCI_MSK, 1306 RTW_PWR_ADDR_MAC, 1307 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1308 {0x0006, 1309 RTW_PWR_CUT_ALL_MSK, 1310 RTW_PWR_INTF_ALL_MSK, 1311 RTW_PWR_ADDR_MAC, 1312 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1313 {0x0005, 1314 RTW_PWR_CUT_ALL_MSK, 1315 RTW_PWR_INTF_ALL_MSK, 1316 RTW_PWR_ADDR_MAC, 1317 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1318 {0x0005, 1319 RTW_PWR_CUT_ALL_MSK, 1320 RTW_PWR_INTF_ALL_MSK, 1321 RTW_PWR_ADDR_MAC, 1322 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1323 {0x10C3, 1324 RTW_PWR_CUT_ALL_MSK, 1325 RTW_PWR_INTF_USB_MSK, 1326 RTW_PWR_ADDR_MAC, 1327 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1328 {0x0005, 1329 RTW_PWR_CUT_ALL_MSK, 1330 RTW_PWR_INTF_ALL_MSK, 1331 RTW_PWR_ADDR_MAC, 1332 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1333 {0x0005, 1334 RTW_PWR_CUT_ALL_MSK, 1335 RTW_PWR_INTF_ALL_MSK, 1336 RTW_PWR_ADDR_MAC, 1337 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1338 {0x0020, 1339 RTW_PWR_CUT_ALL_MSK, 1340 RTW_PWR_INTF_ALL_MSK, 1341 RTW_PWR_ADDR_MAC, 1342 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1343 {0x0074, 1344 RTW_PWR_CUT_ALL_MSK, 1345 RTW_PWR_INTF_PCI_MSK, 1346 RTW_PWR_ADDR_MAC, 1347 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1348 {0x0022, 1349 RTW_PWR_CUT_ALL_MSK, 1350 RTW_PWR_INTF_PCI_MSK, 1351 RTW_PWR_ADDR_MAC, 1352 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1353 {0x0062, 1354 RTW_PWR_CUT_ALL_MSK, 1355 RTW_PWR_INTF_PCI_MSK, 1356 RTW_PWR_ADDR_MAC, 1357 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1358 (BIT(7) | BIT(6) | BIT(5))}, 1359 {0x0061, 1360 RTW_PWR_CUT_ALL_MSK, 1361 RTW_PWR_INTF_PCI_MSK, 1362 RTW_PWR_ADDR_MAC, 1363 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1364 {0x007C, 1365 RTW_PWR_CUT_ALL_MSK, 1366 RTW_PWR_INTF_ALL_MSK, 1367 RTW_PWR_ADDR_MAC, 1368 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1369 {0xFFFF, 1370 RTW_PWR_CUT_ALL_MSK, 1371 RTW_PWR_INTF_ALL_MSK, 1372 0, 1373 RTW_PWR_CMD_END, 0, 0}, 1374 }; 1375 1376 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1377 {0x0093, 1378 RTW_PWR_CUT_ALL_MSK, 1379 RTW_PWR_INTF_ALL_MSK, 1380 RTW_PWR_ADDR_MAC, 1381 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1382 {0x001F, 1383 RTW_PWR_CUT_ALL_MSK, 1384 RTW_PWR_INTF_ALL_MSK, 1385 RTW_PWR_ADDR_MAC, 1386 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1387 {0x0049, 1388 RTW_PWR_CUT_ALL_MSK, 1389 RTW_PWR_INTF_ALL_MSK, 1390 RTW_PWR_ADDR_MAC, 1391 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1392 {0x0006, 1393 RTW_PWR_CUT_ALL_MSK, 1394 RTW_PWR_INTF_ALL_MSK, 1395 RTW_PWR_ADDR_MAC, 1396 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1397 {0x0002, 1398 RTW_PWR_CUT_ALL_MSK, 1399 RTW_PWR_INTF_ALL_MSK, 1400 RTW_PWR_ADDR_MAC, 1401 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1402 {0x10C3, 1403 RTW_PWR_CUT_ALL_MSK, 1404 RTW_PWR_INTF_USB_MSK, 1405 RTW_PWR_ADDR_MAC, 1406 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1407 {0x0005, 1408 RTW_PWR_CUT_ALL_MSK, 1409 RTW_PWR_INTF_ALL_MSK, 1410 RTW_PWR_ADDR_MAC, 1411 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1412 {0x0005, 1413 RTW_PWR_CUT_ALL_MSK, 1414 RTW_PWR_INTF_ALL_MSK, 1415 RTW_PWR_ADDR_MAC, 1416 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1417 {0x0020, 1418 RTW_PWR_CUT_ALL_MSK, 1419 RTW_PWR_INTF_ALL_MSK, 1420 RTW_PWR_ADDR_MAC, 1421 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1422 {0x0000, 1423 RTW_PWR_CUT_ALL_MSK, 1424 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1425 RTW_PWR_ADDR_MAC, 1426 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1427 {0xFFFF, 1428 RTW_PWR_CUT_ALL_MSK, 1429 RTW_PWR_INTF_ALL_MSK, 1430 0, 1431 RTW_PWR_CMD_END, 0, 0}, 1432 }; 1433 1434 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1435 {0x0007, 1436 RTW_PWR_CUT_ALL_MSK, 1437 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1438 RTW_PWR_ADDR_MAC, 1439 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1440 {0x0067, 1441 RTW_PWR_CUT_ALL_MSK, 1442 RTW_PWR_INTF_ALL_MSK, 1443 RTW_PWR_ADDR_MAC, 1444 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1445 {0x0005, 1446 RTW_PWR_CUT_ALL_MSK, 1447 RTW_PWR_INTF_PCI_MSK, 1448 RTW_PWR_ADDR_MAC, 1449 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1450 {0x004A, 1451 RTW_PWR_CUT_ALL_MSK, 1452 RTW_PWR_INTF_USB_MSK, 1453 RTW_PWR_ADDR_MAC, 1454 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1455 {0x0067, 1456 RTW_PWR_CUT_ALL_MSK, 1457 RTW_PWR_INTF_SDIO_MSK, 1458 RTW_PWR_ADDR_MAC, 1459 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1460 {0x0067, 1461 RTW_PWR_CUT_ALL_MSK, 1462 RTW_PWR_INTF_SDIO_MSK, 1463 RTW_PWR_ADDR_MAC, 1464 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1465 {0x004F, 1466 RTW_PWR_CUT_ALL_MSK, 1467 RTW_PWR_INTF_SDIO_MSK, 1468 RTW_PWR_ADDR_MAC, 1469 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1470 {0x0067, 1471 RTW_PWR_CUT_ALL_MSK, 1472 RTW_PWR_INTF_SDIO_MSK, 1473 RTW_PWR_ADDR_MAC, 1474 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1475 {0x0046, 1476 RTW_PWR_CUT_ALL_MSK, 1477 RTW_PWR_INTF_SDIO_MSK, 1478 RTW_PWR_ADDR_MAC, 1479 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1480 {0x0067, 1481 RTW_PWR_CUT_ALL_MSK, 1482 RTW_PWR_INTF_SDIO_MSK, 1483 RTW_PWR_ADDR_MAC, 1484 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1485 {0x0046, 1486 RTW_PWR_CUT_ALL_MSK, 1487 RTW_PWR_INTF_SDIO_MSK, 1488 RTW_PWR_ADDR_MAC, 1489 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1490 {0x0062, 1491 RTW_PWR_CUT_ALL_MSK, 1492 RTW_PWR_INTF_SDIO_MSK, 1493 RTW_PWR_ADDR_MAC, 1494 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1495 {0x0081, 1496 RTW_PWR_CUT_ALL_MSK, 1497 RTW_PWR_INTF_ALL_MSK, 1498 RTW_PWR_ADDR_MAC, 1499 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1500 {0x0005, 1501 RTW_PWR_CUT_ALL_MSK, 1502 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1503 RTW_PWR_ADDR_MAC, 1504 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1505 {0x0086, 1506 RTW_PWR_CUT_ALL_MSK, 1507 RTW_PWR_INTF_SDIO_MSK, 1508 RTW_PWR_ADDR_SDIO, 1509 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1510 {0x0086, 1511 RTW_PWR_CUT_ALL_MSK, 1512 RTW_PWR_INTF_SDIO_MSK, 1513 RTW_PWR_ADDR_SDIO, 1514 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1515 {0x0090, 1516 RTW_PWR_CUT_ALL_MSK, 1517 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1518 RTW_PWR_ADDR_MAC, 1519 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1520 {0x0044, 1521 RTW_PWR_CUT_ALL_MSK, 1522 RTW_PWR_INTF_SDIO_MSK, 1523 RTW_PWR_ADDR_SDIO, 1524 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1525 {0x0040, 1526 RTW_PWR_CUT_ALL_MSK, 1527 RTW_PWR_INTF_SDIO_MSK, 1528 RTW_PWR_ADDR_SDIO, 1529 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1530 {0x0041, 1531 RTW_PWR_CUT_ALL_MSK, 1532 RTW_PWR_INTF_SDIO_MSK, 1533 RTW_PWR_ADDR_SDIO, 1534 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1535 {0x0042, 1536 RTW_PWR_CUT_ALL_MSK, 1537 RTW_PWR_INTF_SDIO_MSK, 1538 RTW_PWR_ADDR_SDIO, 1539 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1540 {0xFFFF, 1541 RTW_PWR_CUT_ALL_MSK, 1542 RTW_PWR_INTF_ALL_MSK, 1543 0, 1544 RTW_PWR_CMD_END, 0, 0}, 1545 }; 1546 1547 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8821c[] = { 1548 trans_carddis_to_cardemu_8821c, 1549 trans_cardemu_to_act_8821c, 1550 NULL 1551 }; 1552 1553 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8821c[] = { 1554 trans_act_to_cardemu_8821c, 1555 trans_cardemu_to_carddis_8821c, 1556 NULL 1557 }; 1558 1559 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1560 {0xFFFF, 0x00, 1561 RTW_IP_SEL_PHY, 1562 RTW_INTF_PHY_CUT_ALL, 1563 RTW_INTF_PHY_PLATFORM_ALL}, 1564 }; 1565 1566 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1567 {0xFFFF, 0x0000, 1568 RTW_IP_SEL_PHY, 1569 RTW_INTF_PHY_CUT_ALL, 1570 RTW_INTF_PHY_PLATFORM_ALL}, 1571 }; 1572 1573 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1574 {0x0009, 0x6380, 1575 RTW_IP_SEL_PHY, 1576 RTW_INTF_PHY_CUT_ALL, 1577 RTW_INTF_PHY_PLATFORM_ALL}, 1578 {0xFFFF, 0x0000, 1579 RTW_IP_SEL_PHY, 1580 RTW_INTF_PHY_CUT_ALL, 1581 RTW_INTF_PHY_PLATFORM_ALL}, 1582 }; 1583 1584 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1585 {0xFFFF, 0x0000, 1586 RTW_IP_SEL_PHY, 1587 RTW_INTF_PHY_CUT_ALL, 1588 RTW_INTF_PHY_PLATFORM_ALL}, 1589 }; 1590 1591 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1592 .usb2_para = usb2_param_8821c, 1593 .usb3_para = usb3_param_8821c, 1594 .gen1_para = pcie_gen1_param_8821c, 1595 .gen2_para = pcie_gen2_param_8821c, 1596 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1597 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1598 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1599 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1600 }; 1601 1602 static const struct rtw_hw_reg rtw8821c_dig[] = { 1603 [0] = { .addr = 0xc50, .mask = 0x7f }, 1604 }; 1605 1606 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1607 .ctrl = LTECOEX_ACCESS_CTRL, 1608 .wdata = LTECOEX_WRITE_DATA, 1609 .rdata = LTECOEX_READ_DATA, 1610 }; 1611 1612 static const struct rtw_page_table page_table_8821c[] = { 1613 /* not sure what [0] stands for */ 1614 {16, 16, 16, 14, 1}, 1615 {16, 16, 16, 14, 1}, 1616 {16, 16, 0, 0, 1}, 1617 {16, 16, 16, 0, 1}, 1618 {16, 16, 16, 14, 1}, 1619 }; 1620 1621 static const struct rtw_rqpn rqpn_table_8821c[] = { 1622 /* not sure what [0] stands for */ 1623 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1624 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1625 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1626 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1627 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1628 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1629 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1630 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1631 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1632 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1633 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1634 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1635 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1636 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1637 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1638 }; 1639 1640 static const struct rtw_prioq_addrs prioq_addrs_8821c = { 1641 .prio[RTW_DMA_MAPPING_EXTRA] = { 1642 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1643 }, 1644 .prio[RTW_DMA_MAPPING_LOW] = { 1645 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1646 }, 1647 .prio[RTW_DMA_MAPPING_NORMAL] = { 1648 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1649 }, 1650 .prio[RTW_DMA_MAPPING_HIGH] = { 1651 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1652 }, 1653 .wsize = true, 1654 }; 1655 1656 static const struct rtw_chip_ops rtw8821c_ops = { 1657 .power_on = rtw_power_on, 1658 .power_off = rtw_power_off, 1659 .phy_set_param = rtw8821c_phy_set_param, 1660 .read_efuse = rtw8821c_read_efuse, 1661 .query_phy_status = query_phy_status, 1662 .set_channel = rtw8821c_set_channel, 1663 .mac_init = rtw8821c_mac_init, 1664 .read_rf = rtw_phy_read_rf, 1665 .write_rf = rtw_phy_write_rf_reg_sipi, 1666 .set_antenna = NULL, 1667 .set_tx_power_index = rtw8821c_set_tx_power_index, 1668 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1669 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1670 .phy_calibration = rtw8821c_phy_calibration, 1671 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1672 .pwr_track = rtw8821c_pwr_track, 1673 .config_bfee = rtw8821c_bf_config_bfee, 1674 .set_gid_table = rtw_bf_set_gid_table, 1675 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1676 .led_set = rtw8821c_led_set, 1677 .fill_txdesc_checksum = rtw8821c_fill_txdesc_checksum, 1678 1679 .coex_set_init = rtw8821c_coex_cfg_init, 1680 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1681 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1682 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1683 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1684 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1685 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1686 }; 1687 1688 /* rssi in percentage % (dbm = % - 100) */ 1689 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1690 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1691 1692 /* Shared-Antenna Coex Table */ 1693 static const struct coex_table_para table_sant_8821c[] = { 1694 {0x55555555, 0x55555555}, /* case-0 */ 1695 {0x55555555, 0x55555555}, 1696 {0x66555555, 0x66555555}, 1697 {0xaaaaaaaa, 0xaaaaaaaa}, 1698 {0x5a5a5a5a, 0x5a5a5a5a}, 1699 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1700 {0x6a5a5555, 0xaaaaaaaa}, 1701 {0x6a5a56aa, 0x6a5a56aa}, 1702 {0x6a5a5a5a, 0x6a5a5a5a}, 1703 {0x66555555, 0x5a5a5a5a}, 1704 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1705 {0x66555555, 0xaaaaaaaa}, 1706 {0x66555555, 0x6a5a5aaa}, 1707 {0x66555555, 0x6aaa6aaa}, 1708 {0x66555555, 0x6a5a5aaa}, 1709 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1710 {0xffff55ff, 0xfafafafa}, 1711 {0xffff55ff, 0x6afa5afa}, 1712 {0xaaffffaa, 0xfafafafa}, 1713 {0xaa5555aa, 0x5a5a5a5a}, 1714 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1715 {0xaa5555aa, 0xaaaaaaaa}, 1716 {0xffffffff, 0x55555555}, 1717 {0xffffffff, 0x5a5a5a5a}, 1718 {0xffffffff, 0x5a5a5a5a}, 1719 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1720 {0x55555555, 0x5a5a5a5a}, 1721 {0x55555555, 0xaaaaaaaa}, 1722 {0x66555555, 0x6a5a6a5a}, 1723 {0x66556655, 0x66556655}, 1724 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1725 {0xffffffff, 0x5aaa5aaa}, 1726 {0x56555555, 0x5a5a5aaa} 1727 }; 1728 1729 /* Non-Shared-Antenna Coex Table */ 1730 static const struct coex_table_para table_nsant_8821c[] = { 1731 {0xffffffff, 0xffffffff}, /* case-100 */ 1732 {0xffff55ff, 0xfafafafa}, 1733 {0x66555555, 0x66555555}, 1734 {0xaaaaaaaa, 0xaaaaaaaa}, 1735 {0x5a5a5a5a, 0x5a5a5a5a}, 1736 {0xffffffff, 0xffffffff}, /* case-105 */ 1737 {0x5afa5afa, 0x5afa5afa}, 1738 {0x55555555, 0xfafafafa}, 1739 {0x66555555, 0xfafafafa}, 1740 {0x66555555, 0x5a5a5a5a}, 1741 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1742 {0x66555555, 0xaaaaaaaa}, 1743 {0xffff55ff, 0xfafafafa}, 1744 {0xffff55ff, 0x5afa5afa}, 1745 {0xffff55ff, 0xaaaaaaaa}, 1746 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1747 {0xaaffffaa, 0x5afa5afa}, 1748 {0xaaffffaa, 0xaaaaaaaa}, 1749 {0xffffffff, 0xfafafafa}, 1750 {0xffff55ff, 0xfafafafa}, 1751 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1752 {0xffff55ff, 0x5afa5afa}, 1753 {0xffff55ff, 0x5afa5afa}, 1754 {0x55ff55ff, 0x55ff55ff} 1755 }; 1756 1757 /* Shared-Antenna TDMA */ 1758 static const struct coex_tdma_para tdma_sant_8821c[] = { 1759 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1760 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1761 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1762 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1763 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1764 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1765 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1766 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1767 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1768 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1769 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1770 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1771 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1772 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1773 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1774 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1775 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1776 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1777 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1778 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1779 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1780 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1781 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1782 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1783 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1784 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1785 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1786 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1787 }; 1788 1789 /* Non-Shared-Antenna TDMA */ 1790 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1791 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1792 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1793 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1794 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1795 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1796 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1797 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1798 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1799 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1800 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1801 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1802 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1803 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1804 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1805 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1806 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1807 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1808 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1809 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1810 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1811 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1812 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1813 }; 1814 1815 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1816 1817 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1818 static const struct coex_rf_para rf_para_tx_8821c[] = { 1819 {0, 0, false, 7}, /* for normal */ 1820 {0, 20, false, 7}, /* for WL-CPT */ 1821 {8, 17, true, 4}, 1822 {7, 18, true, 4}, 1823 {6, 19, true, 4}, 1824 {5, 20, true, 4} 1825 }; 1826 1827 static const struct coex_rf_para rf_para_rx_8821c[] = { 1828 {0, 0, false, 7}, /* for normal */ 1829 {0, 20, false, 7}, /* for WL-CPT */ 1830 {3, 24, true, 5}, 1831 {2, 26, true, 5}, 1832 {1, 27, true, 5}, 1833 {0, 28, true, 5} 1834 }; 1835 1836 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1837 1838 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1839 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1840 11, 11, 12, 12, 12, 12, 12}, 1841 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1842 11, 12, 12, 12, 12, 12, 12, 12}, 1843 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1844 11, 12, 12, 12, 12, 12, 12}, 1845 }; 1846 1847 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1848 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1849 12, 12, 12, 12, 12, 12, 12}, 1850 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1851 12, 12, 12, 12, 12, 12, 12, 12}, 1852 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1853 11, 12, 12, 12, 12, 12, 12, 12}, 1854 }; 1855 1856 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1857 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1858 11, 11, 12, 12, 12, 12, 12}, 1859 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1860 11, 12, 12, 12, 12, 12, 12, 12}, 1861 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1862 11, 12, 12, 12, 12, 12, 12}, 1863 }; 1864 1865 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1866 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1867 12, 12, 12, 12, 12, 12, 12}, 1868 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1869 12, 12, 12, 12, 12, 12, 12, 12}, 1870 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1871 11, 12, 12, 12, 12, 12, 12, 12}, 1872 }; 1873 1874 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1875 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1876 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1877 }; 1878 1879 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1880 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1881 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1882 }; 1883 1884 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1885 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1886 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1887 }; 1888 1889 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1890 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1891 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1892 }; 1893 1894 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1895 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1896 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1897 }; 1898 1899 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1900 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1901 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1902 }; 1903 1904 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1905 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1906 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1907 }; 1908 1909 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1910 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1911 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1912 }; 1913 1914 static const struct rtw_pwr_track_tbl rtw8821c_pwr_track_type0_tbl = { 1915 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1916 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1917 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1918 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1919 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1920 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1921 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1922 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1923 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1924 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1925 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1926 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1927 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1928 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1929 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1930 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1931 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1932 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1933 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1934 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1935 }; 1936 1937 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1938 [0] = RTW_DEF_RFE(8821c, 0, 0, 0), 1939 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 0, 2), 1940 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 0, 2), 1941 [6] = RTW_DEF_RFE(8821c, 0, 0, 0), 1942 }; 1943 1944 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1945 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1946 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1947 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1948 {0, 0, RTW_REG_DOMAIN_NL}, 1949 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1950 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1951 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1952 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1953 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1954 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1955 {0, 0, RTW_REG_DOMAIN_NL}, 1956 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1957 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1958 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1959 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1960 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1961 {0, 0, RTW_REG_DOMAIN_NL}, 1962 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1963 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1964 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1965 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1966 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1967 }; 1968 1969 const struct rtw_chip_info rtw8821c_hw_spec = { 1970 .ops = &rtw8821c_ops, 1971 .id = RTW_CHIP_TYPE_8821C, 1972 .fw_name = "rtw88/rtw8821c_fw.bin", 1973 .wlan_cpu = RTW_WCPU_11AC, 1974 .tx_pkt_desc_sz = 48, 1975 .tx_buf_desc_sz = 16, 1976 .rx_pkt_desc_sz = 24, 1977 .rx_buf_desc_sz = 8, 1978 .phy_efuse_size = 512, 1979 .log_efuse_size = 512, 1980 .ptct_efuse_size = 96, 1981 .txff_size = 65536, 1982 .rxff_size = 16384, 1983 .rsvd_drv_pg_num = 8, 1984 .txgi_factor = 1, 1985 .is_pwr_by_rate_dec = true, 1986 .max_power_index = 0x3f, 1987 .csi_buf_pg_num = 0, 1988 .band = RTW_BAND_2G | RTW_BAND_5G, 1989 .page_size = TX_PAGE_SIZE, 1990 .dig_min = 0x1c, 1991 .usb_tx_agg_desc_num = 3, 1992 .hw_feature_report = true, 1993 .c2h_ra_report_size = 7, 1994 .old_datarate_fb_limit = false, 1995 .ht_supported = true, 1996 .vht_supported = true, 1997 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1998 .sys_func_en = 0xD8, 1999 .pwr_on_seq = card_enable_flow_8821c, 2000 .pwr_off_seq = card_disable_flow_8821c, 2001 .page_table = page_table_8821c, 2002 .rqpn_table = rqpn_table_8821c, 2003 .prioq_addrs = &prioq_addrs_8821c, 2004 .intf_table = &phy_para_table_8821c, 2005 .dig = rtw8821c_dig, 2006 .rf_base_addr = {0x2800, 0x2c00}, 2007 .rf_sipi_addr = {0xc90, 0xe90}, 2008 .ltecoex_addr = &rtw8821c_ltecoex_addr, 2009 .mac_tbl = &rtw8821c_mac_tbl, 2010 .agc_tbl = &rtw8821c_agc_tbl, 2011 .bb_tbl = &rtw8821c_bb_tbl, 2012 .rf_tbl = {&rtw8821c_rf_a_tbl}, 2013 .rfe_defs = rtw8821c_rfe_defs, 2014 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 2015 .rx_ldpc = false, 2016 .iqk_threshold = 8, 2017 .bfer_su_max_num = 2, 2018 .bfer_mu_max_num = 1, 2019 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 2020 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2021 2022 .coex_para_ver = 0x19092746, 2023 .bt_desired_ver = 0x46, 2024 .scbd_support = true, 2025 .new_scbd10_def = false, 2026 .ble_hid_profile_support = false, 2027 .wl_mimo_ps_support = false, 2028 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2029 .bt_rssi_type = COEX_BTRSSI_RATIO, 2030 .ant_isolation = 15, 2031 .rssi_tolerance = 2, 2032 .wl_rssi_step = wl_rssi_step_8821c, 2033 .bt_rssi_step = bt_rssi_step_8821c, 2034 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 2035 .table_sant = table_sant_8821c, 2036 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 2037 .table_nsant = table_nsant_8821c, 2038 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 2039 .tdma_sant = tdma_sant_8821c, 2040 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 2041 .tdma_nsant = tdma_nsant_8821c, 2042 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 2043 .wl_rf_para_tx = rf_para_tx_8821c, 2044 .wl_rf_para_rx = rf_para_rx_8821c, 2045 .bt_afh_span_bw20 = 0x24, 2046 .bt_afh_span_bw40 = 0x36, 2047 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 2048 .afh_5g = afh_5g_8821c, 2049 2050 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 2051 .coex_info_hw_regs = coex_info_hw_regs_8821c, 2052 }; 2053 EXPORT_SYMBOL(rtw8821c_hw_spec); 2054 2055 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 2056 2057 MODULE_AUTHOR("Realtek Corporation"); 2058 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 2059 MODULE_LICENSE("Dual BSD/GPL"); 2060