1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2024 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "phy.h" 8 #include "reg.h" 9 #include "rtw88xxa.h" 10 #include "rtw8821a.h" 11 #include "rtw8821a_table.h" 12 #include "tx.h" 13 14 static void rtw8821a_power_off(struct rtw_dev *rtwdev) 15 { 16 rtw88xxa_power_off(rtwdev, enter_lps_flow_8821a); 17 } 18 19 static s8 rtw8821a_cck_rx_pwr(u8 lna_idx, u8 vga_idx) 20 { 21 static const s8 lna_gain_table[] = {15, -1, -17, 0, -30, -38}; 22 s8 rx_pwr_all = 0; 23 s8 lna_gain; 24 25 switch (lna_idx) { 26 case 5: 27 case 4: 28 case 2: 29 case 1: 30 case 0: 31 lna_gain = lna_gain_table[lna_idx]; 32 rx_pwr_all = lna_gain - 2 * vga_idx; 33 break; 34 default: 35 break; 36 } 37 38 return rx_pwr_all; 39 } 40 41 static void rtw8821a_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 42 struct rtw_rx_pkt_stat *pkt_stat) 43 { 44 rtw88xxa_query_phy_status(rtwdev, phy_status, pkt_stat, 45 rtw8821a_cck_rx_pwr); 46 } 47 48 static void rtw8821a_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 49 { 50 } 51 52 #define CAL_NUM_8821A 3 53 #define MACBB_REG_NUM_8821A 8 54 #define AFE_REG_NUM_8821A 4 55 #define RF_REG_NUM_8821A 3 56 57 static void rtw8821a_iqk_backup_rf(struct rtw_dev *rtwdev, u32 *rfa_backup, 58 const u32 *backup_rf_reg, u32 rf_num) 59 { 60 u32 i; 61 62 /* [31] = 0 --> Page C */ 63 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 64 65 /* Save RF Parameters */ 66 for (i = 0; i < rf_num; i++) 67 rfa_backup[i] = rtw_read_rf(rtwdev, RF_PATH_A, 68 backup_rf_reg[i], MASKDWORD); 69 } 70 71 static void rtw8821a_iqk_restore_rf(struct rtw_dev *rtwdev, 72 const u32 *backup_rf_reg, 73 u32 *RF_backup, u32 rf_reg_num) 74 { 75 u32 i; 76 77 /* [31] = 0 --> Page C */ 78 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 79 80 for (i = 0; i < rf_reg_num; i++) 81 rtw_write_rf(rtwdev, RF_PATH_A, backup_rf_reg[i], 82 RFREG_MASK, RF_backup[i]); 83 } 84 85 static void rtw8821a_iqk_restore_afe(struct rtw_dev *rtwdev, u32 *afe_backup, 86 const u32 *backup_afe_reg, u32 afe_num) 87 { 88 u32 i; 89 90 /* [31] = 0 --> Page C */ 91 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 92 93 /* Reload AFE Parameters */ 94 for (i = 0; i < afe_num; i++) 95 rtw_write32(rtwdev, backup_afe_reg[i], afe_backup[i]); 96 97 /* [31] = 1 --> Page C1 */ 98 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1); 99 100 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x0); 101 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x0); 102 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x0); 103 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x3c000000); 104 rtw_write32(rtwdev, REG_LSSI_WRITE_A, 0x00000080); 105 rtw_write32(rtwdev, REG_TXAGCIDX, 0x00000000); 106 rtw_write32(rtwdev, REG_IQK_DPD_CFG, 0x20040000); 107 rtw_write32(rtwdev, REG_CFG_PMPD, 0x20000000); 108 rtw_write32(rtwdev, REG_RFECTL_A, 0x0); 109 } 110 111 static void rtw8821a_iqk_rx_fill(struct rtw_dev *rtwdev, 112 unsigned int rx_x, unsigned int rx_y) 113 { 114 /* [31] = 0 --> Page C */ 115 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 116 117 rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A, 118 0x000003ff, rx_x >> 1); 119 rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A, 120 0x03ff0000, (rx_y >> 1) & 0x3ff); 121 } 122 123 static void rtw8821a_iqk_tx_fill(struct rtw_dev *rtwdev, 124 unsigned int tx_x, unsigned int tx_y) 125 { 126 /* [31] = 1 --> Page C1 */ 127 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1); 128 129 rtw_write32(rtwdev, REG_LSSI_WRITE_A, 0x00000080); 130 rtw_write32(rtwdev, REG_IQK_DPD_CFG, 0x20040000); 131 rtw_write32(rtwdev, REG_CFG_PMPD, 0x20000000); 132 rtw_write32_mask(rtwdev, REG_IQC_Y, 0x000007ff, tx_y); 133 rtw_write32_mask(rtwdev, REG_IQC_X, 0x000007ff, tx_x); 134 } 135 136 static void rtw8821a_iqk_tx_vdf_true(struct rtw_dev *rtwdev, u32 cal, 137 bool *tx0iqkok, 138 int tx_x0[CAL_NUM_8821A], 139 int tx_y0[CAL_NUM_8821A]) 140 { 141 u32 cal_retry, delay_count, iqk_ready, tx_fail; 142 int tx_dt[3], vdf_y[3], vdf_x[3]; 143 int k; 144 145 for (k = 0; k < 3; k++) { 146 switch (k) { 147 case 0: 148 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 149 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 150 0x18008c38); 151 /* RX_Tone_idx[9:0], RxK_Mask[29] */ 152 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c38); 153 rtw_write32_mask(rtwdev, REG_INTPO_SETA, BIT(31), 0x0); 154 break; 155 case 1: 156 rtw_write32_mask(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 157 BIT(28), 0x0); 158 rtw_write32_mask(rtwdev, REG_OFDM0_A_TX_AFE, 159 BIT(28), 0x0); 160 rtw_write32_mask(rtwdev, REG_INTPO_SETA, BIT(31), 0x0); 161 break; 162 case 2: 163 rtw_dbg(rtwdev, RTW_DBG_RFK, 164 "vdf_y[1] = %x vdf_y[0] = %x\n", 165 vdf_y[1] >> 21 & 0x00007ff, 166 vdf_y[0] >> 21 & 0x00007ff); 167 168 rtw_dbg(rtwdev, RTW_DBG_RFK, 169 "vdf_x[1] = %x vdf_x[0] = %x\n", 170 vdf_x[1] >> 21 & 0x00007ff, 171 vdf_x[0] >> 21 & 0x00007ff); 172 173 tx_dt[cal] = (vdf_y[1] >> 20) - (vdf_y[0] >> 20); 174 tx_dt[cal] = (16 * tx_dt[cal]) * 10000 / 15708; 175 tx_dt[cal] = (tx_dt[cal] >> 1) + (tx_dt[cal] & BIT(0)); 176 177 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 178 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 179 0x18008c20); 180 /* RX_Tone_idx[9:0], RxK_Mask[29] */ 181 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c20); 182 rtw_write32_mask(rtwdev, REG_INTPO_SETA, BIT(31), 0x1); 183 rtw_write32_mask(rtwdev, REG_INTPO_SETA, 0x3fff0000, 184 tx_dt[cal] & 0x00003fff); 185 break; 186 } 187 188 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000); 189 190 for (cal_retry = 0; cal_retry < 10; cal_retry++) { 191 /* one shot */ 192 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000); 193 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000); 194 195 mdelay(10); 196 197 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000); 198 199 for (delay_count = 0; delay_count < 20; delay_count++) { 200 iqk_ready = rtw_read32_mask(rtwdev, 201 REG_IQKA_END, 202 BIT(10)); 203 204 /* Originally: if (~iqk_ready || delay_count > 20) 205 * that looks like a typo so make it more explicit 206 */ 207 iqk_ready = true; 208 209 if (iqk_ready) 210 break; 211 212 mdelay(1); 213 } 214 215 if (delay_count < 20) { 216 /* ============TXIQK Check============== */ 217 tx_fail = rtw_read32_mask(rtwdev, 218 REG_IQKA_END, 219 BIT(12)); 220 221 /* Originally: if (~tx_fail) { 222 * It looks like a typo, so make it more explicit. 223 */ 224 tx_fail = false; 225 226 if (!tx_fail) { 227 rtw_write32(rtwdev, REG_RFECTL_A, 228 0x02000000); 229 vdf_x[k] = rtw_read32_mask(rtwdev, 230 REG_IQKA_END, 231 0x07ff0000); 232 vdf_x[k] <<= 21; 233 234 rtw_write32(rtwdev, REG_RFECTL_A, 235 0x04000000); 236 vdf_y[k] = rtw_read32_mask(rtwdev, 237 REG_IQKA_END, 238 0x07ff0000); 239 vdf_y[k] <<= 21; 240 241 *tx0iqkok = true; 242 break; 243 } 244 245 rtw_write32_mask(rtwdev, REG_IQC_Y, 246 0x000007ff, 0x0); 247 rtw_write32_mask(rtwdev, REG_IQC_X, 248 0x000007ff, 0x200); 249 } 250 251 *tx0iqkok = false; 252 } 253 } 254 255 if (k == 3) { 256 tx_x0[cal] = vdf_x[k - 1]; 257 tx_y0[cal] = vdf_y[k - 1]; 258 } 259 } 260 261 static void rtw8821a_iqk_tx_vdf_false(struct rtw_dev *rtwdev, u32 cal, 262 bool *tx0iqkok, 263 int tx_x0[CAL_NUM_8821A], 264 int tx_y0[CAL_NUM_8821A]) 265 { 266 u32 cal_retry, delay_count, iqk_ready, tx_fail; 267 268 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 269 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x18008c10); 270 /* RX_Tone_idx[9:0], RxK_Mask[29] */ 271 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c10); 272 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000); 273 274 for (cal_retry = 0; cal_retry < 10; cal_retry++) { 275 /* one shot */ 276 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000); 277 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000); 278 279 mdelay(10); 280 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000); 281 282 for (delay_count = 0; delay_count < 20; delay_count++) { 283 iqk_ready = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(10)); 284 285 /* Originally: if (~iqk_ready || delay_count > 20) 286 * that looks like a typo so make it more explicit 287 */ 288 iqk_ready = true; 289 290 if (iqk_ready) 291 break; 292 293 mdelay(1); 294 } 295 296 if (delay_count < 20) { 297 /* ============TXIQK Check============== */ 298 tx_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(12)); 299 300 /* Originally: if (~tx_fail) { 301 * It looks like a typo, so make it more explicit. 302 */ 303 tx_fail = false; 304 305 if (!tx_fail) { 306 rtw_write32(rtwdev, REG_RFECTL_A, 0x02000000); 307 tx_x0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END, 308 0x07ff0000); 309 tx_x0[cal] <<= 21; 310 311 rtw_write32(rtwdev, REG_RFECTL_A, 0x04000000); 312 tx_y0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END, 313 0x07ff0000); 314 tx_y0[cal] <<= 21; 315 316 *tx0iqkok = true; 317 break; 318 } 319 320 rtw_write32_mask(rtwdev, REG_IQC_Y, 0x000007ff, 0x0); 321 rtw_write32_mask(rtwdev, REG_IQC_X, 0x000007ff, 0x200); 322 } 323 324 *tx0iqkok = false; 325 } 326 } 327 328 static void rtw8821a_iqk_rx(struct rtw_dev *rtwdev, u32 cal, bool *rx0iqkok, 329 int rx_x0[CAL_NUM_8821A], 330 int rx_y0[CAL_NUM_8821A]) 331 { 332 u32 cal_retry, delay_count, iqk_ready, rx_fail; 333 334 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000); 335 336 for (cal_retry = 0; cal_retry < 10; cal_retry++) { 337 /* one shot */ 338 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000); 339 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000); 340 341 mdelay(10); 342 343 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000); 344 345 for (delay_count = 0; delay_count < 20; delay_count++) { 346 iqk_ready = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(10)); 347 348 /* Originally: if (~iqk_ready || delay_count > 20) 349 * that looks like a typo so make it more explicit 350 */ 351 iqk_ready = true; 352 353 if (iqk_ready) 354 break; 355 356 mdelay(1); 357 } 358 359 if (delay_count < 20) { 360 /* ============RXIQK Check============== */ 361 rx_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(11)); 362 if (!rx_fail) { 363 rtw_write32(rtwdev, REG_RFECTL_A, 0x06000000); 364 rx_x0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END, 365 0x07ff0000); 366 rx_x0[cal] <<= 21; 367 368 rtw_write32(rtwdev, REG_RFECTL_A, 0x08000000); 369 rx_y0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END, 370 0x07ff0000); 371 rx_y0[cal] <<= 21; 372 373 *rx0iqkok = true; 374 break; 375 } 376 377 rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A, 378 0x000003ff, 0x200 >> 1); 379 rtw_write32_mask(rtwdev, REG_RX_IQC_AB_A, 380 0x03ff0000, 0x0 >> 1); 381 } 382 383 *rx0iqkok = false; 384 } 385 } 386 387 static void rtw8821a_iqk(struct rtw_dev *rtwdev) 388 { 389 int tx_average = 0, rx_average = 0, rx_iqk_loop = 0; 390 const struct rtw_efuse *efuse = &rtwdev->efuse; 391 int tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0; 392 const struct rtw_hal *hal = &rtwdev->hal; 393 bool tx0iqkok = false, rx0iqkok = false; 394 int rx_x_temp = 0, rx_y_temp = 0; 395 int rx_x0[2][CAL_NUM_8821A]; 396 int rx_y0[2][CAL_NUM_8821A]; 397 int tx_x0[CAL_NUM_8821A]; 398 int tx_y0[CAL_NUM_8821A]; 399 bool rx_finish1 = false; 400 bool rx_finish2 = false; 401 bool vdf_enable; 402 u32 cal; 403 int i; 404 405 rtw_dbg(rtwdev, RTW_DBG_RFK, 406 "band_width = %d, ext_pa = %d, ext_pa_5g = %d\n", 407 hal->current_band_width, efuse->ext_pa_2g, efuse->ext_pa_5g); 408 409 vdf_enable = hal->current_band_width == RTW_CHANNEL_WIDTH_80; 410 411 for (cal = 0; cal < CAL_NUM_8821A; cal++) { 412 /* path-A LOK */ 413 414 /* [31] = 0 --> Page C */ 415 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 416 417 /* ========path-A AFE all on======== */ 418 /* Port 0 DAC/ADC on */ 419 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x77777777); 420 rtw_write32(rtwdev, REG_AFE_PWR2_A, 0x77777777); 421 422 rtw_write32(rtwdev, REG_RX_WAIT_CCA_TX_CCK_RFON_A, 0x19791979); 423 424 /* hardware 3-wire off */ 425 rtw_write32_mask(rtwdev, REG_3WIRE_SWA, 0xf, 0x4); 426 427 /* LOK setting */ 428 429 /* 1. DAC/ADC sampling rate (160 MHz) */ 430 rtw_write32_mask(rtwdev, REG_CK_MONHA, GENMASK(26, 24), 0x7); 431 432 /* 2. LoK RF setting (at BW = 20M) */ 433 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80002); 434 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x00c00, 0x3); 435 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_ADDR, RFREG_MASK, 436 0x20000); 437 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA0, RFREG_MASK, 438 0x0003f); 439 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA1, RFREG_MASK, 440 0xf3fc3); 441 442 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXA_PREPAD, RFREG_MASK, 443 0x931d5); 444 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x8a001); 445 rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000); 446 rtw_write32_mask(rtwdev, REG_TXAGCIDX, BIT(0), 0x1); 447 /* TX (X,Y) */ 448 rtw_write32(rtwdev, REG_IQK_COM00, 0x29002000); 449 /* RX (X,Y) */ 450 rtw_write32(rtwdev, REG_IQK_COM32, 0xa9002000); 451 /* [0]:AGC_en, [15]:idac_K_Mask */ 452 rtw_write32(rtwdev, REG_IQK_COM96, 0x00462910); 453 454 /* [31] = 1 --> Page C1 */ 455 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1); 456 457 if (efuse->ext_pa_5g) 458 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 459 0x821403f7); 460 else 461 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 462 0x821403f4); 463 464 if (hal->current_band_type == RTW_BAND_5G) 465 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x68163e96); 466 else 467 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28163e96); 468 469 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 470 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x18008c10); 471 /* RX_Tone_idx[9:0], RxK_Mask[29] */ 472 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c10); 473 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000); 474 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000); 475 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000); 476 477 mdelay(10); 478 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000); 479 480 /* [31] = 0 --> Page C */ 481 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 482 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXMOD, 0x7fe00, 483 rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, 0xffc00)); 484 485 if (hal->current_band_width == RTW_CHANNEL_WIDTH_40) 486 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, 487 RF18_BW_MASK, 0x1); 488 else if (hal->current_band_width == RTW_CHANNEL_WIDTH_80) 489 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, 490 RF18_BW_MASK, 0x0); 491 492 /* [31] = 1 --> Page C1 */ 493 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1); 494 495 /* 3. TX RF setting */ 496 /* [31] = 0 --> Page C */ 497 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 498 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 499 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_ADDR, RFREG_MASK, 500 0x20000); 501 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA0, RFREG_MASK, 502 0x0003f); 503 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA1, RFREG_MASK, 504 0xf3fc3); 505 506 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXA_PREPAD, RFREG_MASK, 0x931d5); 507 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x8a001); 508 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 509 rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000); 510 rtw_write32_mask(rtwdev, REG_TXAGCIDX, BIT(0), 0x1); 511 /* TX (X,Y) */ 512 rtw_write32(rtwdev, REG_IQK_COM00, 0x29002000); 513 /* RX (X,Y) */ 514 rtw_write32(rtwdev, REG_IQK_COM32, 0xa9002000); 515 /* [0]:AGC_en, [15]:idac_K_Mask */ 516 rtw_write32(rtwdev, REG_IQK_COM96, 0x0046a910); 517 518 /* [31] = 1 --> Page C1 */ 519 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1); 520 521 if (efuse->ext_pa_5g) 522 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 523 0x821403f7); 524 else 525 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 526 0x821403e3); 527 528 if (hal->current_band_type == RTW_BAND_5G) 529 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x40163e96); 530 else 531 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x00163e96); 532 533 if (vdf_enable) 534 rtw8821a_iqk_tx_vdf_true(rtwdev, cal, &tx0iqkok, 535 tx_x0, tx_y0); 536 else 537 rtw8821a_iqk_tx_vdf_false(rtwdev, cal, &tx0iqkok, 538 tx_x0, tx_y0); 539 540 if (!tx0iqkok) 541 break; /* TXK fail, Don't do RXK */ 542 543 /* ====== RX IQK ====== */ 544 /* [31] = 0 --> Page C */ 545 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); 546 /* 1. RX RF setting */ 547 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 548 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_ADDR, RFREG_MASK, 549 0x30000); 550 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA0, RFREG_MASK, 551 0x0002f); 552 rtw_write_rf(rtwdev, RF_PATH_A, RF_MODE_TABLE_DATA1, RFREG_MASK, 553 0xfffbb); 554 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x88001); 555 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXA_PREPAD, RFREG_MASK, 0x931d8); 556 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 557 558 rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x03FF8000, 559 (tx_x0[cal] >> 21) & 0x000007ff); 560 rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x000007FF, 561 (tx_y0[cal] >> 21) & 0x000007ff); 562 rtw_write32_mask(rtwdev, REG_IQK_COM00, BIT(31), 0x1); 563 rtw_write32_mask(rtwdev, REG_IQK_COM00, BIT(31), 0x0); 564 rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000); 565 rtw_write32(rtwdev, REG_IQK_COM96, 0x0046a911); 566 567 /* [31] = 1 --> Page C1 */ 568 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1); 569 570 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 571 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x38008c10); 572 /* RX_Tone_idx[9:0], RxK_Mask[29] */ 573 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x18008c10); 574 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x02140119); 575 576 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) 577 rx_iqk_loop = 2; /* for 2% fail; */ 578 else 579 rx_iqk_loop = 1; 580 581 for (i = 0; i < rx_iqk_loop; i++) { 582 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE && i == 0) 583 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28161100); /* Good */ 584 else 585 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28160d00); 586 587 rtw8821a_iqk_rx(rtwdev, cal, &rx0iqkok, 588 rx_x0[i], rx_y0[i]); 589 } 590 591 if (tx0iqkok) 592 tx_average++; 593 if (rx0iqkok) 594 rx_average++; 595 } 596 597 /* FillIQK Result */ 598 599 if (tx_average == 0) 600 return; 601 602 for (i = 0; i < tx_average; i++) 603 rtw_dbg(rtwdev, RTW_DBG_RFK, 604 "tx_x0[%d] = %x ;; tx_y0[%d] = %x\n", 605 i, (tx_x0[i] >> 21) & 0x000007ff, 606 i, (tx_y0[i] >> 21) & 0x000007ff); 607 608 if (rtw88xxa_iqk_finish(tx_average, 3, tx_x0, tx_y0, 609 &tx_x, &tx_y, true, true)) 610 rtw8821a_iqk_tx_fill(rtwdev, tx_x, tx_y); 611 else 612 rtw8821a_iqk_tx_fill(rtwdev, 0x200, 0x0); 613 614 if (rx_average == 0) 615 return; 616 617 for (i = 0; i < rx_average; i++) { 618 rtw_dbg(rtwdev, RTW_DBG_RFK, 619 "rx_x0[0][%d] = %x ;; rx_y0[0][%d] = %x\n", 620 i, (rx_x0[0][i] >> 21) & 0x000007ff, 621 i, (rx_y0[0][i] >> 21) & 0x000007ff); 622 623 if (rx_iqk_loop == 2) 624 rtw_dbg(rtwdev, RTW_DBG_RFK, 625 "rx_x0[1][%d] = %x ;; rx_y0[1][%d] = %x\n", 626 i, (rx_x0[1][i] >> 21) & 0x000007ff, 627 i, (rx_y0[1][i] >> 21) & 0x000007ff); 628 } 629 630 rx_finish1 = rtw88xxa_iqk_finish(rx_average, 4, rx_x0[0], rx_y0[0], 631 &rx_x_temp, &rx_y_temp, true, true); 632 633 if (rx_finish1) { 634 rx_x = rx_x_temp; 635 rx_y = rx_y_temp; 636 } 637 638 if (rx_iqk_loop == 2) { 639 rx_finish2 = rtw88xxa_iqk_finish(rx_average, 4, 640 rx_x0[1], rx_y0[1], 641 &rx_x, &rx_y, true, true); 642 643 if (rx_finish1 && rx_finish2) { 644 rx_x = (rx_x + rx_x_temp) / 2; 645 rx_y = (rx_y + rx_y_temp) / 2; 646 } 647 } 648 649 if (rx_finish1 || rx_finish2) 650 rtw8821a_iqk_rx_fill(rtwdev, rx_x, rx_y); 651 else 652 rtw8821a_iqk_rx_fill(rtwdev, 0x200, 0x0); 653 } 654 655 static void rtw8821a_do_iqk(struct rtw_dev *rtwdev) 656 { 657 static const u32 backup_macbb_reg[MACBB_REG_NUM_8821A] = { 658 0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c 659 }; 660 static const u32 backup_afe_reg[AFE_REG_NUM_8821A] = { 661 0xc5c, 0xc60, 0xc64, 0xc68 662 }; 663 static const u32 backup_rf_reg[RF_REG_NUM_8821A] = { 664 0x65, 0x8f, 0x0 665 }; 666 u32 macbb_backup[MACBB_REG_NUM_8821A]; 667 u32 afe_backup[AFE_REG_NUM_8821A]; 668 u32 rfa_backup[RF_REG_NUM_8821A]; 669 670 rtw88xxa_iqk_backup_mac_bb(rtwdev, macbb_backup, 671 backup_macbb_reg, MACBB_REG_NUM_8821A); 672 rtw88xxa_iqk_backup_afe(rtwdev, afe_backup, 673 backup_afe_reg, AFE_REG_NUM_8821A); 674 rtw8821a_iqk_backup_rf(rtwdev, rfa_backup, 675 backup_rf_reg, RF_REG_NUM_8821A); 676 677 rtw88xxa_iqk_configure_mac(rtwdev); 678 679 rtw8821a_iqk(rtwdev); 680 681 rtw8821a_iqk_restore_rf(rtwdev, backup_rf_reg, 682 rfa_backup, RF_REG_NUM_8821A); 683 rtw8821a_iqk_restore_afe(rtwdev, afe_backup, 684 backup_afe_reg, AFE_REG_NUM_8821A); 685 rtw88xxa_iqk_restore_mac_bb(rtwdev, macbb_backup, 686 backup_macbb_reg, MACBB_REG_NUM_8821A); 687 } 688 689 static void rtw8821a_phy_calibration(struct rtw_dev *rtwdev) 690 { 691 rtw8821a_do_iqk(rtwdev); 692 } 693 694 static void rtw8821a_pwr_track(struct rtw_dev *rtwdev) 695 { 696 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 697 698 if (!dm_info->pwr_trk_triggered) { 699 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 700 GENMASK(17, 16), 0x03); 701 dm_info->pwr_trk_triggered = true; 702 return; 703 } 704 705 rtw88xxa_phy_pwrtrack(rtwdev, NULL, rtw8821a_do_iqk); 706 dm_info->pwr_trk_triggered = false; 707 } 708 709 static void rtw8821a_fill_txdesc_checksum(struct rtw_dev *rtwdev, 710 struct rtw_tx_pkt_info *pkt_info, 711 u8 *txdesc) 712 { 713 fill_txdesc_checksum_common(txdesc, 16); 714 } 715 716 static void rtw8821a_coex_cfg_init(struct rtw_dev *rtwdev) 717 { 718 u8 val8; 719 720 /* BT report packet sample rate */ 721 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 722 723 val8 = BIT_STATIS_BT_EN; 724 if (rtwdev->efuse.share_ant) 725 val8 |= BIT_R_GRANTALL_WLMASK; 726 rtw_write8(rtwdev, REG_BT_COEX_ENH_INTR_CTRL, val8); 727 728 /* enable BT counter statistics */ 729 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x3); 730 731 /* enable PTA */ 732 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 733 } 734 735 static void rtw8821a_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 736 u8 pos_type) 737 { 738 bool share_ant = rtwdev->efuse.share_ant; 739 struct rtw_coex *coex = &rtwdev->coex; 740 struct rtw_coex_dm *coex_dm = &coex->dm; 741 u32 phase = coex_dm->cur_ant_pos_type; 742 743 if (!rtwdev->efuse.btcoex) 744 return; 745 746 switch (phase) { 747 case COEX_SET_ANT_POWERON: 748 case COEX_SET_ANT_INIT: 749 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 750 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 751 rtw_write8_set(rtwdev, REG_GNT_BT, BIT_PTA_SW_CTL); 752 753 rtw_write8(rtwdev, REG_RFE_CTRL8, 754 share_ant ? PTA_CTRL_PIN : DPDT_CTRL_PIN); 755 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 0x1); 756 break; 757 case COEX_SET_ANT_WONLY: 758 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 759 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 760 rtw_write8_clr(rtwdev, REG_GNT_BT, BIT_PTA_SW_CTL); 761 762 rtw_write8(rtwdev, REG_RFE_CTRL8, DPDT_CTRL_PIN); 763 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 0x1); 764 break; 765 case COEX_SET_ANT_2G: 766 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 767 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 768 rtw_write8_clr(rtwdev, REG_GNT_BT, BIT_PTA_SW_CTL); 769 770 rtw_write8(rtwdev, REG_RFE_CTRL8, 771 share_ant ? PTA_CTRL_PIN : DPDT_CTRL_PIN); 772 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 0x1); 773 break; 774 case COEX_SET_ANT_5G: 775 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 776 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 777 rtw_write8_set(rtwdev, REG_GNT_BT, BIT_PTA_SW_CTL); 778 779 rtw_write8(rtwdev, REG_RFE_CTRL8, DPDT_CTRL_PIN); 780 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 781 share_ant ? 0x2 : 0x1); 782 break; 783 case COEX_SET_ANT_WOFF: 784 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 785 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 786 rtw_write8_set(rtwdev, REG_GNT_BT, BIT_PTA_SW_CTL); 787 788 rtw_write8(rtwdev, REG_RFE_CTRL8, DPDT_CTRL_PIN); 789 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 790 share_ant ? 0x2 : 0x1); 791 break; 792 default: 793 rtw_warn(rtwdev, "%s: not handling phase %d\n", 794 __func__, phase); 795 break; 796 } 797 } 798 799 static void rtw8821a_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 800 { 801 } 802 803 static void rtw8821a_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 804 { 805 } 806 807 static void rtw8821a_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 808 { 809 struct rtw_coex *coex = &rtwdev->coex; 810 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 811 812 coex_rfe->ant_switch_exist = true; 813 } 814 815 static void rtw8821a_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 816 { 817 struct rtw_coex *coex = &rtwdev->coex; 818 struct rtw_coex_dm *coex_dm = &coex->dm; 819 struct rtw_efuse *efuse = &rtwdev->efuse; 820 bool share_ant = efuse->share_ant; 821 822 if (share_ant) 823 return; 824 825 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 826 return; 827 828 coex_dm->cur_wl_pwr_lvl = wl_pwr; 829 } 830 831 static void rtw8821a_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 832 { 833 } 834 835 static const struct rtw_chip_ops rtw8821a_ops = { 836 .power_on = rtw88xxa_power_on, 837 .power_off = rtw8821a_power_off, 838 .phy_set_param = NULL, 839 .read_efuse = rtw88xxa_read_efuse, 840 .query_phy_status = rtw8821a_query_phy_status, 841 .set_channel = rtw88xxa_set_channel, 842 .mac_init = NULL, 843 .read_rf = rtw88xxa_phy_read_rf, 844 .write_rf = rtw_phy_write_rf_reg_sipi, 845 .set_antenna = NULL, 846 .set_tx_power_index = rtw88xxa_set_tx_power_index, 847 .cfg_ldo25 = rtw8821a_cfg_ldo25, 848 .efuse_grant = rtw88xxa_efuse_grant, 849 .false_alarm_statistics = rtw88xxa_false_alarm_statistics, 850 .phy_calibration = rtw8821a_phy_calibration, 851 .cck_pd_set = rtw88xxa_phy_cck_pd_set, 852 .pwr_track = rtw8821a_pwr_track, 853 .config_bfee = NULL, 854 .set_gid_table = NULL, 855 .cfg_csi_rate = NULL, 856 .fill_txdesc_checksum = rtw8821a_fill_txdesc_checksum, 857 .coex_set_init = rtw8821a_coex_cfg_init, 858 .coex_set_ant_switch = rtw8821a_coex_cfg_ant_switch, 859 .coex_set_gnt_fix = rtw8821a_coex_cfg_gnt_fix, 860 .coex_set_gnt_debug = rtw8821a_coex_cfg_gnt_debug, 861 .coex_set_rfe_type = rtw8821a_coex_cfg_rfe_type, 862 .coex_set_wl_tx_power = rtw8821a_coex_cfg_wl_tx_power, 863 .coex_set_wl_rx_gain = rtw8821a_coex_cfg_wl_rx_gain, 864 }; 865 866 static const struct rtw_page_table page_table_8821a[] = { 867 /* hq_num, nq_num, lq_num, exq_num, gapq_num */ 868 {0, 0, 0, 0, 0}, /* SDIO */ 869 {0, 0, 0, 0, 0}, /* PCI */ 870 {8, 0, 0, 0, 1}, /* 2 bulk out endpoints */ 871 {8, 0, 8, 0, 1}, /* 3 bulk out endpoints */ 872 {8, 0, 8, 4, 1}, /* 4 bulk out endpoints */ 873 }; 874 875 static const struct rtw_rqpn rqpn_table_8821a[] = { 876 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 877 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 878 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 879 880 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 881 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 882 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 883 884 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH, 885 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 886 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 887 888 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL, 889 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 890 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 891 892 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 893 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 894 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 895 }; 896 897 static const struct rtw_prioq_addrs prioq_addrs_8821a = { 898 .prio[RTW_DMA_MAPPING_EXTRA] = { 899 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, 900 }, 901 .prio[RTW_DMA_MAPPING_LOW] = { 902 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, 903 }, 904 .prio[RTW_DMA_MAPPING_NORMAL] = { 905 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, 906 }, 907 .prio[RTW_DMA_MAPPING_HIGH] = { 908 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, 909 }, 910 .wsize = false, 911 }; 912 913 static const struct rtw_hw_reg rtw8821a_dig[] = { 914 [0] = { .addr = REG_RXIGI_A, .mask = 0x7f }, 915 }; 916 917 static const struct rtw_rfe_def rtw8821a_rfe_defs[] = { 918 [0] = { .phy_pg_tbl = &rtw8821a_bb_pg_tbl, 919 .txpwr_lmt_tbl = &rtw8821a_txpwr_lmt_tbl, 920 .pwr_track_tbl = &rtw8821a_rtw_pwr_track_tbl, }, 921 }; 922 923 /* TODO */ 924 /* rssi in percentage % (dbm = % - 100) */ 925 static const u8 wl_rssi_step_8821a[] = {101, 45, 101, 40}; 926 static const u8 bt_rssi_step_8821a[] = {101, 101, 101, 101}; 927 928 /* table_sant_8821a, table_nsant_8821a, tdma_sant_8821a, and tdma_nsant_8821a 929 * are copied from rtw8821c.c because the 8821au driver's tables are not 930 * compatible with the coex code in rtw88. 931 * 932 * tdma case 112 (A2DP) byte 0 had to be modified from 0x61 to 0x51, 933 * otherwise the firmware gets confused after pausing the music: 934 * rtw_8821au 1-2:1.2: [BTCoex], Bt_info[1], len=7, data=[81 00 0a 01 00 00] 935 * - 81 means PAN (personal area network) when it should be 4x (A2DP) 936 * The music is not smooth with the PAN algorithm. 937 */ 938 939 /* Shared-Antenna Coex Table */ 940 static const struct coex_table_para table_sant_8821a[] = { 941 {0x55555555, 0x55555555}, /* case-0 */ 942 {0x55555555, 0x55555555}, 943 {0x66555555, 0x66555555}, 944 {0xaaaaaaaa, 0xaaaaaaaa}, 945 {0x5a5a5a5a, 0x5a5a5a5a}, 946 {0xfafafafa, 0xfafafafa}, /* case-5 */ 947 {0x6a5a5555, 0xaaaaaaaa}, 948 {0x6a5a56aa, 0x6a5a56aa}, 949 {0x6a5a5a5a, 0x6a5a5a5a}, 950 {0x66555555, 0x5a5a5a5a}, 951 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 952 {0x66555555, 0xaaaaaaaa}, 953 {0x66555555, 0x6a5a5aaa}, 954 {0x66555555, 0x6aaa6aaa}, 955 {0x66555555, 0x6a5a5aaa}, 956 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 957 {0xffff55ff, 0xfafafafa}, 958 {0xffff55ff, 0x6afa5afa}, 959 {0xaaffffaa, 0xfafafafa}, 960 {0xaa5555aa, 0x5a5a5a5a}, 961 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 962 {0xaa5555aa, 0xaaaaaaaa}, 963 {0xffffffff, 0x55555555}, 964 {0xffffffff, 0x5a5a5a5a}, 965 {0xffffffff, 0x5a5a5a5a}, 966 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 967 {0x55555555, 0x5a5a5a5a}, 968 {0x55555555, 0xaaaaaaaa}, 969 {0x66555555, 0x6a5a6a5a}, 970 {0x66556655, 0x66556655}, 971 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 972 {0xffffffff, 0x5aaa5aaa}, 973 {0x56555555, 0x5a5a5aaa} 974 }; 975 976 /* Non-Shared-Antenna Coex Table */ 977 static const struct coex_table_para table_nsant_8821a[] = { 978 {0xffffffff, 0xffffffff}, /* case-100 */ 979 {0xffff55ff, 0xfafafafa}, 980 {0x66555555, 0x66555555}, 981 {0xaaaaaaaa, 0xaaaaaaaa}, 982 {0x5a5a5a5a, 0x5a5a5a5a}, 983 {0xffffffff, 0xffffffff}, /* case-105 */ 984 {0x5afa5afa, 0x5afa5afa}, 985 {0x55555555, 0xfafafafa}, 986 {0x66555555, 0xfafafafa}, 987 {0x66555555, 0x5a5a5a5a}, 988 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 989 {0x66555555, 0xaaaaaaaa}, 990 {0xffff55ff, 0xfafafafa}, 991 {0xffff55ff, 0x5afa5afa}, 992 {0xffff55ff, 0xaaaaaaaa}, 993 {0xffff55ff, 0xffff55ff}, /* case-115 */ 994 {0xaaffffaa, 0x5afa5afa}, 995 {0xaaffffaa, 0xaaaaaaaa}, 996 {0xffffffff, 0xfafafafa}, 997 {0xffff55ff, 0xfafafafa}, 998 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 999 {0xffff55ff, 0x5afa5afa}, 1000 {0xffff55ff, 0x5afa5afa}, 1001 {0x55ff55ff, 0x55ff55ff} 1002 }; 1003 1004 /* Shared-Antenna TDMA */ 1005 static const struct coex_tdma_para tdma_sant_8821a[] = { 1006 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1007 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1008 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1009 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1010 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1011 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1012 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1013 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1014 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1015 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1016 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1017 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1018 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1019 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1020 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1021 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1022 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1023 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1024 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1025 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1026 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1027 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1028 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1029 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1030 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1031 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1032 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1033 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1034 }; 1035 1036 /* Non-Shared-Antenna TDMA */ 1037 static const struct coex_tdma_para tdma_nsant_8821a[] = { 1038 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1039 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1040 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1041 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1042 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1043 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1044 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1045 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1046 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1047 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1048 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1049 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1050 { {0x51, 0x08, 0x03, 0x10, 0x14} }, /* a2dp high rssi */ 1051 { {0x51, 0x08, 0x03, 0x10, 0x54} }, /* a2dp not high rssi */ 1052 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1053 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1054 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1055 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1056 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1057 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1058 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1059 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1060 }; 1061 1062 /* TODO */ 1063 static const struct coex_rf_para rf_para_tx_8821a[] = { 1064 {0, 0, false, 7}, /* for normal */ 1065 {0, 20, false, 7}, /* for WL-CPT */ 1066 {8, 17, true, 4}, 1067 {7, 18, true, 4}, 1068 {6, 19, true, 4}, 1069 {5, 20, true, 4} 1070 }; 1071 1072 static const struct coex_rf_para rf_para_rx_8821a[] = { 1073 {0, 0, false, 7}, /* for normal */ 1074 {0, 20, false, 7}, /* for WL-CPT */ 1075 {3, 24, true, 5}, 1076 {2, 26, true, 5}, 1077 {1, 27, true, 5}, 1078 {0, 28, true, 5} 1079 }; 1080 1081 static_assert(ARRAY_SIZE(rf_para_tx_8821a) == ARRAY_SIZE(rf_para_rx_8821a)); 1082 1083 static const struct coex_5g_afh_map afh_5g_8821a[] = { {0, 0, 0} }; 1084 1085 static const struct rtw_reg_domain coex_info_hw_regs_8821a[] = { 1086 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1087 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1088 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1089 {0, 0, RTW_REG_DOMAIN_NL}, 1090 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1091 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1092 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1093 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1094 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1095 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1096 {0, 0, RTW_REG_DOMAIN_NL}, 1097 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1098 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1099 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1100 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1101 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1102 {0, 0, RTW_REG_DOMAIN_NL}, 1103 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1104 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1105 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1106 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1107 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1108 }; 1109 1110 const struct rtw_chip_info rtw8821a_hw_spec = { 1111 .ops = &rtw8821a_ops, 1112 .id = RTW_CHIP_TYPE_8821A, 1113 .fw_name = "rtw88/rtw8821a_fw.bin", 1114 .wlan_cpu = RTW_WCPU_11N, 1115 .tx_pkt_desc_sz = 40, 1116 .tx_buf_desc_sz = 16, 1117 .rx_pkt_desc_sz = 24, 1118 .rx_buf_desc_sz = 8, 1119 .phy_efuse_size = 512, 1120 .log_efuse_size = 512, 1121 .ptct_efuse_size = 96 + 1, /* TODO or just 18? */ 1122 .txff_size = 65536, 1123 .rxff_size = 16128, 1124 .rsvd_drv_pg_num = 8, 1125 .txgi_factor = 1, 1126 .is_pwr_by_rate_dec = true, 1127 .max_power_index = 0x3f, 1128 .csi_buf_pg_num = 0, 1129 .band = RTW_BAND_2G | RTW_BAND_5G, 1130 .page_size = 256, 1131 .dig_min = 0x20, 1132 .ht_supported = true, 1133 .vht_supported = true, 1134 .lps_deep_mode_supported = 0, 1135 .sys_func_en = 0xFD, 1136 .pwr_on_seq = card_enable_flow_8821a, 1137 .pwr_off_seq = card_disable_flow_8821a, 1138 .page_table = page_table_8821a, 1139 .rqpn_table = rqpn_table_8821a, 1140 .prioq_addrs = &prioq_addrs_8821a, 1141 .intf_table = NULL, 1142 .dig = rtw8821a_dig, 1143 .rf_sipi_addr = {REG_LSSI_WRITE_A, REG_LSSI_WRITE_B}, 1144 .ltecoex_addr = NULL, 1145 .mac_tbl = &rtw8821a_mac_tbl, 1146 .agc_tbl = &rtw8821a_agc_tbl, 1147 .bb_tbl = &rtw8821a_bb_tbl, 1148 .rf_tbl = {&rtw8821a_rf_a_tbl}, 1149 .rfe_defs = rtw8821a_rfe_defs, 1150 .rfe_defs_size = ARRAY_SIZE(rtw8821a_rfe_defs), 1151 .rx_ldpc = false, 1152 .hw_feature_report = false, 1153 .c2h_ra_report_size = 4, 1154 .old_datarate_fb_limit = true, 1155 .usb_tx_agg_desc_num = 6, 1156 .iqk_threshold = 8, 1157 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1158 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 1159 1160 .coex_para_ver = 20190509, /* glcoex_ver_date_8821a_1ant */ 1161 .bt_desired_ver = 0x62, /* But for 2 ant it's 0x5c */ 1162 .scbd_support = false, 1163 .new_scbd10_def = false, 1164 .ble_hid_profile_support = false, 1165 .wl_mimo_ps_support = false, 1166 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1167 .bt_rssi_type = COEX_BTRSSI_RATIO, 1168 .ant_isolation = 10, 1169 .rssi_tolerance = 2, 1170 .wl_rssi_step = wl_rssi_step_8821a, 1171 .bt_rssi_step = bt_rssi_step_8821a, 1172 .table_sant_num = ARRAY_SIZE(table_sant_8821a), 1173 .table_sant = table_sant_8821a, 1174 .table_nsant_num = ARRAY_SIZE(table_nsant_8821a), 1175 .table_nsant = table_nsant_8821a, 1176 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821a), 1177 .tdma_sant = tdma_sant_8821a, 1178 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821a), 1179 .tdma_nsant = tdma_nsant_8821a, 1180 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821a), 1181 .wl_rf_para_tx = rf_para_tx_8821a, 1182 .wl_rf_para_rx = rf_para_rx_8821a, 1183 .bt_afh_span_bw20 = 0x20, 1184 .bt_afh_span_bw40 = 0x30, 1185 .afh_5g_num = ARRAY_SIZE(afh_5g_8821a), 1186 .afh_5g = afh_5g_8821a, 1187 1188 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821a), 1189 .coex_info_hw_regs = coex_info_hw_regs_8821a, 1190 }; 1191 EXPORT_SYMBOL(rtw8821a_hw_spec); 1192 1193 MODULE_FIRMWARE("rtw88/rtw8821a_fw.bin"); 1194 1195 MODULE_AUTHOR("Realtek Corporation"); 1196 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821a/8811a driver"); 1197 MODULE_LICENSE("Dual BSD/GPL"); 1198