1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW8723D_H__ 6 #define __RTW8723D_H__ 7 8 struct rtw8723de_efuse { 9 u8 mac_addr[ETH_ALEN]; /* 0xd0 */ 10 u8 vender_id[2]; 11 u8 device_id[2]; 12 u8 sub_vender_id[2]; 13 u8 sub_device_id[2]; 14 }; 15 16 struct rtw8723d_efuse { 17 __le16 rtl_id; 18 u8 rsvd[2]; 19 u8 afe; 20 u8 rsvd1[11]; 21 22 /* power index for four RF paths */ 23 struct rtw_txpwr_idx txpwr_idx_table[4]; 24 25 u8 channel_plan; /* 0xb8 */ 26 u8 xtal_k; 27 u8 thermal_meter; 28 u8 iqk_lck; 29 u8 pa_type; /* 0xbc */ 30 u8 lna_type_2g[2]; /* 0xbd */ 31 u8 lna_type_5g[2]; 32 u8 rf_board_option; 33 u8 rf_feature_option; 34 u8 rf_bt_setting; 35 u8 eeprom_version; 36 u8 eeprom_customer_id; 37 u8 tx_bb_swing_setting_2g; 38 u8 res_c7; 39 u8 tx_pwr_calibrate_rate; 40 u8 rf_antenna_option; /* 0xc9 */ 41 u8 rfe_option; 42 u8 country_code[2]; 43 u8 res[3]; 44 struct rtw8723de_efuse e; 45 }; 46 47 /* phy status page0 */ 48 #define GET_PHY_STAT_P0_PWDB(phy_stat) \ 49 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 50 51 /* phy status page1 */ 52 #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \ 53 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 54 #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \ 55 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16)) 56 #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \ 57 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28)) 58 #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \ 59 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8)) 60 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \ 61 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12)) 62 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \ 63 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) 64 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \ 65 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0)) 66 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ 67 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) 68 69 #define SPUR_THRES 0x16 70 #define CCK_DFIR_NR 3 71 #define DIS_3WIRE 0xccf000c0 72 #define EN_3WIRE 0xccc000c0 73 #define START_PSD 0x400000 74 #define FREQ_CH13 0xfccd 75 #define FREQ_CH14 0xff9a 76 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) 77 #define RFCFGCH_BW_MASK (BIT(11) | BIT(10)) 78 #define RFCFGCH_BW_20M (BIT(11) | BIT(10)) 79 #define RFCFGCH_BW_40M BIT(10) 80 #define BIT_MASK_RFMOD BIT(0) 81 82 #define REG_PSDFN 0x0808 83 #define REG_ANALOG_P4 0x088c 84 #define REG_PSDRPT 0x08b4 85 #define REG_FPGA1_RFMOD 0x0900 86 #define REG_BBRX_DFIR 0x0954 87 #define BIT_MASK_RXBB_DFIR GENMASK(27, 24) 88 #define BIT_RXBB_DFIR_EN BIT(19) 89 #define REG_CCK0_SYS 0x0a00 90 #define BIT_CCK_SIDE_BAND BIT(4) 91 #define REG_CCK_FA_RST_11N 0x0a2c 92 #define BIT_MASK_CCK_CNT_KEEP BIT(12) 93 #define BIT_MASK_CCK_CNT_EN BIT(13) 94 #define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN) 95 #define BIT_MASK_CCK_FA_KEEP BIT(14) 96 #define BIT_MASK_CCK_FA_EN BIT(15) 97 #define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN) 98 #define REG_CCK_FA_LSB_11N 0x0a5c 99 #define REG_CCK_FA_MSB_11N 0x0a58 100 #define REG_CCK_CCA_CNT_11N 0x0a60 101 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0) 102 #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8) 103 #define REG_OFDM_FA_HOLDC_11N 0x0c00 104 #define BIT_MASK_OFDM_FA_KEEP BIT(31) 105 #define REG_OFDM_FA_RSTC_11N 0x0c0c 106 #define BIT_MASK_OFDM_FA_RST BIT(31) 107 #define REG_OFDM0_RXDSP 0x0c40 108 #define BIT_MASK_RXDSP GENMASK(28, 24) 109 #define BIT_EN_RXDSP BIT(9) 110 #define REG_OFDM0_XAAGC1 0x0c50 111 #define REG_OFDM0_XBAGC1 0x0c58 112 #define REG_OFDM_FA_TYPE1_11N 0x0cf0 113 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0) 114 #define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16) 115 #define REG_OFDM_FA_RSTD_11N 0x0d00 116 #define BIT_MASK_OFDM_FA_RST1 BIT(27) 117 #define BIT_MASK_OFDM_FA_KEEP1 BIT(31) 118 #define REG_OFDM1_CFOTRK 0x0d2c 119 #define BIT_EN_CFOTRK BIT(28) 120 #define REG_OFDM1_CSI1 0x0d40 121 #define REG_OFDM1_CSI2 0x0d44 122 #define REG_OFDM1_CSI3 0x0d48 123 #define REG_OFDM1_CSI4 0x0d4c 124 #define REG_OFDM_FA_TYPE2_11N 0x0da0 125 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0) 126 #define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16) 127 #define REG_OFDM_FA_TYPE3_11N 0x0da4 128 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0) 129 #define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16) 130 #define REG_OFDM_FA_TYPE4_11N 0x0da8 131 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0) 132 #define REG_PAGE_F_RST_11N 0x0f14 133 #define BIT_MASK_F_RST_ALL BIT(16) 134 #define REG_IGI_C_11N 0x0f84 135 #define REG_IGI_D_11N 0x0f88 136 #define REG_HT_CRC32_CNT_11N 0x0f90 137 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0) 138 #define BIT_MASK_HT_CRC_ERR GENMASK(31, 16) 139 #define REG_OFDM_CRC32_CNT_11N 0x0f94 140 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0) 141 #define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16) 142 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8 143 144 #endif 145