1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8723d.h" 12 #include "rtw8723d_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 17 static const struct rtw_hw_reg rtw8723d_txagc[] = { 18 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, 19 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, 20 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, 21 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, 22 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, 23 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, 24 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, 25 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, 26 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, 27 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, 28 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, 29 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, 30 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, 31 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, 32 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, 33 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, 34 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, 35 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, 36 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, 37 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, 38 }; 39 40 #define WLAN_TXQ_RPT_EN 0x1F 41 #define WLAN_SLOT_TIME 0x09 42 #define WLAN_RL_VAL 0x3030 43 #define WLAN_BAR_VAL 0x0201ffff 44 #define BIT_MASK_TBTT_HOLD 0x00000fff 45 #define BIT_SHIFT_TBTT_HOLD 8 46 #define BIT_MASK_TBTT_SETUP 0x000000ff 47 #define BIT_SHIFT_TBTT_SETUP 0 48 #define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \ 49 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP)) 50 #define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\ 51 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD)) 52 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80) 53 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64) 54 #define WLAN_PIFS_VAL 0 55 #define WLAN_AGG_BRK_TIME 0x16 56 #define WLAN_NAV_PROT_LEN 0x0040 57 #define WLAN_SPEC_SIFS 0x100a 58 #define WLAN_RX_PKT_LIMIT 0x17 59 #define WLAN_MAX_AGG_NR 0x0A 60 #define WLAN_AMPDU_MAX_TIME 0x1C 61 #define WLAN_ANT_SEL 0x82 62 #define WLAN_LTR_IDLE_LAT 0x883C883C 63 #define WLAN_LTR_ACT_LAT 0x880B880B 64 #define WLAN_LTR_CTRL1 0xCB004010 65 #define WLAN_LTR_CTRL2 0x01233425 66 67 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) 68 { 69 u8 xtal_cap; 70 u32 val32; 71 72 /* power on BB/RF domain */ 73 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 74 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 75 rtw_write8_set(rtwdev, REG_RF_CTRL, 76 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 77 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 78 79 rtw_phy_load_tables(rtwdev); 80 81 /* post init after header files config */ 82 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 83 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT); 84 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 85 86 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 87 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 88 xtal_cap | (xtal_cap << 6)); 89 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 90 if ((rtwdev->efuse.afe >> 4) == 14) { 91 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4); 92 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL); 93 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1); 94 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0); 95 } 96 97 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 98 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 99 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 100 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 101 rtw_write8(rtwdev, REG_ATIMWND, 0x2); 102 rtw_write8(rtwdev, REG_BCN_CTRL, 103 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 104 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT); 105 val32 &= ~BIT_MASK_TBTT_MASK; 106 val32 |= WLAN_TBTT_TIME_STOP_BCN; 107 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32); 108 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 109 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME); 110 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN); 111 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 112 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); 113 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); 114 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 115 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 116 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 117 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 118 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL); 119 120 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT); 121 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT); 122 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1); 123 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2); 124 125 rtw_phy_init(rtwdev); 126 127 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); 128 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 129 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 130 } 131 132 static void rtw8723de_efuse_parsing(struct rtw_efuse *efuse, 133 struct rtw8723d_efuse *map) 134 { 135 ether_addr_copy(efuse->addr, map->e.mac_addr); 136 } 137 138 static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 139 { 140 struct rtw_efuse *efuse = &rtwdev->efuse; 141 struct rtw8723d_efuse *map; 142 int i; 143 144 map = (struct rtw8723d_efuse *)log_map; 145 146 efuse->rfe_option = 0; 147 efuse->rf_board_option = map->rf_board_option; 148 efuse->crystal_cap = map->xtal_k; 149 efuse->pa_type_2g = map->pa_type; 150 efuse->lna_type_2g = map->lna_type_2g[0]; 151 efuse->channel_plan = map->channel_plan; 152 efuse->country_code[0] = map->country_code[0]; 153 efuse->country_code[1] = map->country_code[1]; 154 efuse->bt_setting = map->rf_bt_setting; 155 efuse->regd = map->rf_board_option & 0x7; 156 efuse->thermal_meter[0] = map->thermal_meter; 157 efuse->thermal_meter_k = map->thermal_meter; 158 efuse->afe = map->afe; 159 160 for (i = 0; i < 4; i++) 161 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 162 163 switch (rtw_hci_type(rtwdev)) { 164 case RTW_HCI_TYPE_PCIE: 165 rtw8723de_efuse_parsing(efuse, map); 166 break; 167 default: 168 /* unsupported now */ 169 return -ENOTSUPP; 170 } 171 172 return 0; 173 } 174 175 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 176 struct rtw_rx_pkt_stat *pkt_stat) 177 { 178 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 179 s8 min_rx_power = -120; 180 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 181 182 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97; 183 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 184 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 185 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 186 min_rx_power); 187 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 188 } 189 190 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 191 struct rtw_rx_pkt_stat *pkt_stat) 192 { 193 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 194 u8 rxsc, bw; 195 s8 min_rx_power = -120; 196 s8 rx_evm; 197 198 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 199 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 200 else 201 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 202 203 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0) 204 bw = RTW_CHANNEL_WIDTH_20; 205 else if ((rxsc == 1) || (rxsc == 2)) 206 bw = RTW_CHANNEL_WIDTH_20; 207 else 208 bw = RTW_CHANNEL_WIDTH_40; 209 210 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 211 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 212 pkt_stat->bw = bw; 213 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 214 min_rx_power); 215 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 216 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 217 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 218 219 dm_info->curr_rx_rate = pkt_stat->rate; 220 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 221 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 222 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 223 224 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64); 225 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 226 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm; 227 } 228 229 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 230 struct rtw_rx_pkt_stat *pkt_stat) 231 { 232 u8 page; 233 234 page = *phy_status & 0xf; 235 236 switch (page) { 237 case 0: 238 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 239 break; 240 case 1: 241 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 242 break; 243 default: 244 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 245 return; 246 } 247 } 248 249 static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 250 struct rtw_rx_pkt_stat *pkt_stat, 251 struct ieee80211_rx_status *rx_status) 252 { 253 struct ieee80211_hdr *hdr; 254 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 255 u8 *phy_status = NULL; 256 257 memset(pkt_stat, 0, sizeof(*pkt_stat)); 258 259 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 260 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 261 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 262 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 263 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 264 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 265 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 266 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 267 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 268 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 269 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 270 pkt_stat->ppdu_cnt = 0; 271 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 272 273 /* drv_info_sz is in unit of 8-bytes */ 274 pkt_stat->drv_info_sz *= 8; 275 276 /* c2h cmd pkt's rx/phy status is not interested */ 277 if (pkt_stat->is_c2h) 278 return; 279 280 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 281 pkt_stat->drv_info_sz); 282 if (pkt_stat->phy_status) { 283 phy_status = rx_desc + desc_sz + pkt_stat->shift; 284 query_phy_status(rtwdev, phy_status, pkt_stat); 285 } 286 287 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 288 } 289 290 static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev, 291 u8 channel, u32 thres) 292 { 293 u32 freq; 294 bool ret = false; 295 296 if (channel == 13) 297 freq = FREQ_CH13; 298 else if (channel == 14) 299 freq = FREQ_CH14; 300 else 301 return false; 302 303 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 304 rtw_write32(rtwdev, REG_PSDFN, freq); 305 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 306 307 msleep(30); 308 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 309 ret = true; 310 311 rtw_write32(rtwdev, REG_PSDFN, freq); 312 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 313 314 return ret; 315 } 316 317 static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 318 { 319 if (!notch) { 320 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 321 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 322 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 323 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 324 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 325 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 326 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 327 return; 328 } 329 330 switch (channel) { 331 case 13: 332 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 333 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 334 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000); 335 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 336 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 337 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 338 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 339 break; 340 case 14: 341 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 342 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 343 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 344 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 345 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 346 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000); 347 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 348 break; 349 default: 350 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 351 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 352 break; 353 } 354 } 355 356 static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel) 357 { 358 bool notch; 359 360 if (channel < 13) { 361 rtw8723d_cfg_notch(rtwdev, channel, false); 362 return; 363 } 364 365 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES); 366 rtw8723d_cfg_notch(rtwdev, channel, notch); 367 } 368 369 static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 370 { 371 u32 rf_cfgch_a, rf_cfgch_b; 372 373 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 374 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 375 376 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 377 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 378 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 379 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 380 381 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 382 switch (bw) { 383 case RTW_CHANNEL_WIDTH_20: 384 rf_cfgch_a |= RFCFGCH_BW_20M; 385 break; 386 case RTW_CHANNEL_WIDTH_40: 387 rf_cfgch_a |= RFCFGCH_BW_40M; 388 break; 389 default: 390 break; 391 } 392 393 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 394 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 395 396 rtw8723d_spur_cal(rtwdev, channel); 397 } 398 399 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = { 400 [0] = { 401 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C }, 402 { .len = 4, .reg = 0xA28, .val = 0x00008810 }, 403 { .len = 4, .reg = 0xAAC, .val = 0x01235667 }, 404 }, 405 [1] = { 406 { .len = 4, .reg = 0xA24, .val = 0x0000B81C }, 407 { .len = 4, .reg = 0xA28, .val = 0x00000000 }, 408 { .len = 4, .reg = 0xAAC, .val = 0x00003667 }, 409 }, 410 }; 411 412 static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 413 u8 primary_ch_idx) 414 { 415 const struct rtw_backup_info *cck_dfir; 416 int i; 417 418 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 419 420 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++) 421 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 422 423 switch (bw) { 424 case RTW_CHANNEL_WIDTH_20: 425 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 426 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 427 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1); 428 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); 429 break; 430 case RTW_CHANNEL_WIDTH_40: 431 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 432 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 433 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); 434 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 435 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 436 break; 437 default: 438 break; 439 } 440 } 441 442 static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 443 u8 primary_chan_idx) 444 { 445 rtw8723d_set_channel_rf(rtwdev, channel, bw); 446 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 447 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 448 } 449 450 #define BIT_CFENDFORM BIT(9) 451 #define BIT_WMAC_TCR_ERR0 BIT(12) 452 #define BIT_WMAC_TCR_ERR1 BIT(13) 453 #define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ 454 BIT_WMAC_TCR_ERR1) 455 #define WLAN_RX_FILTER0 0xFFFF 456 #define WLAN_RX_FILTER1 0x400 457 #define WLAN_RX_FILTER2 0xFFFF 458 #define WLAN_RCR_CFG 0x700060CE 459 460 static int rtw8723d_mac_init(struct rtw_dev *rtwdev) 461 { 462 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 463 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); 464 465 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 466 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); 467 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 468 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 469 470 rtw_write32(rtwdev, REG_INT_MIG, 0); 471 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); 472 473 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 474 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); 475 476 return 0; 477 } 478 479 static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 480 { 481 u8 ldo_pwr; 482 483 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 484 if (enable) { 485 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; 486 ldo_pwr = (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; 487 } else { 488 ldo_pwr &= ~BIT_LDO25_EN; 489 } 490 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 491 } 492 493 static void 494 rtw8723d_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 495 { 496 struct rtw_hal *hal = &rtwdev->hal; 497 const struct rtw_hw_reg *txagc; 498 u8 rate, pwr_index; 499 int j; 500 501 for (j = 0; j < rtw_rate_size[rs]; j++) { 502 rate = rtw_rate_section[rs][j]; 503 pwr_index = hal->tx_pwr_tbl[path][rate]; 504 505 if (rate >= ARRAY_SIZE(rtw8723d_txagc)) { 506 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); 507 continue; 508 } 509 txagc = &rtw8723d_txagc[rate]; 510 if (!txagc->addr) { 511 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); 512 continue; 513 } 514 515 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); 516 } 517 } 518 519 static void rtw8723d_set_tx_power_index(struct rtw_dev *rtwdev) 520 { 521 struct rtw_hal *hal = &rtwdev->hal; 522 int rs, path; 523 524 for (path = 0; path < hal->rf_path_num; path++) { 525 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) 526 rtw8723d_set_tx_power_index_by_rate(rtwdev, path, rs); 527 } 528 } 529 530 static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on) 531 { 532 if (on) { 533 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 534 535 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 536 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); 537 } else { 538 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 539 } 540 } 541 542 static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev) 543 { 544 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 545 u32 cck_fa_cnt; 546 u32 ofdm_fa_cnt; 547 u32 crc32_cnt; 548 u32 val32; 549 550 /* hold counter */ 551 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); 552 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); 553 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); 554 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); 555 556 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); 557 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; 558 559 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); 560 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); 561 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); 562 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); 563 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); 564 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); 565 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); 566 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); 567 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); 568 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); 569 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); 570 571 dm_info->cck_fa_cnt = cck_fa_cnt; 572 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 573 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; 574 575 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); 576 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); 577 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); 578 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); 579 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); 580 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); 581 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); 582 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); 583 dm_info->vht_err_cnt = 0; 584 dm_info->vht_ok_cnt = 0; 585 586 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); 587 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | 588 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); 589 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; 590 591 /* reset counter */ 592 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); 593 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); 594 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); 595 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); 596 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); 597 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); 598 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); 599 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); 600 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); 601 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); 602 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); 603 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); 604 } 605 606 static struct rtw_chip_ops rtw8723d_ops = { 607 .phy_set_param = rtw8723d_phy_set_param, 608 .read_efuse = rtw8723d_read_efuse, 609 .query_rx_desc = rtw8723d_query_rx_desc, 610 .set_channel = rtw8723d_set_channel, 611 .mac_init = rtw8723d_mac_init, 612 .read_rf = rtw_phy_read_rf_sipi, 613 .write_rf = rtw_phy_write_rf_reg_sipi, 614 .set_tx_power_index = rtw8723d_set_tx_power_index, 615 .set_antenna = NULL, 616 .cfg_ldo25 = rtw8723d_cfg_ldo25, 617 .efuse_grant = rtw8723d_efuse_grant, 618 .false_alarm_statistics = rtw8723d_false_alarm_statistics, 619 .config_bfee = NULL, 620 .set_gid_table = NULL, 621 .cfg_csi_rate = NULL, 622 }; 623 624 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = { 625 {0x0005, 626 RTW_PWR_CUT_ALL_MSK, 627 RTW_PWR_INTF_ALL_MSK, 628 RTW_PWR_ADDR_MAC, 629 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, 630 {0x0086, 631 RTW_PWR_CUT_ALL_MSK, 632 RTW_PWR_INTF_SDIO_MSK, 633 RTW_PWR_ADDR_SDIO, 634 RTW_PWR_CMD_WRITE, BIT(0), 0}, 635 {0x0086, 636 RTW_PWR_CUT_ALL_MSK, 637 RTW_PWR_INTF_SDIO_MSK, 638 RTW_PWR_ADDR_SDIO, 639 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 640 {0x004A, 641 RTW_PWR_CUT_ALL_MSK, 642 RTW_PWR_INTF_USB_MSK, 643 RTW_PWR_ADDR_MAC, 644 RTW_PWR_CMD_WRITE, BIT(0), 0}, 645 {0x0005, 646 RTW_PWR_CUT_ALL_MSK, 647 RTW_PWR_INTF_ALL_MSK, 648 RTW_PWR_ADDR_MAC, 649 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, 650 {0x0023, 651 RTW_PWR_CUT_ALL_MSK, 652 RTW_PWR_INTF_SDIO_MSK, 653 RTW_PWR_ADDR_MAC, 654 RTW_PWR_CMD_WRITE, BIT(4), 0}, 655 {0x0301, 656 RTW_PWR_CUT_ALL_MSK, 657 RTW_PWR_INTF_PCI_MSK, 658 RTW_PWR_ADDR_MAC, 659 RTW_PWR_CMD_WRITE, 0xFF, 0}, 660 {0xFFFF, 661 RTW_PWR_CUT_ALL_MSK, 662 RTW_PWR_INTF_ALL_MSK, 663 0, 664 RTW_PWR_CMD_END, 0, 0}, 665 }; 666 667 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = { 668 {0x0020, 669 RTW_PWR_CUT_ALL_MSK, 670 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 671 RTW_PWR_ADDR_MAC, 672 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 673 {0x0001, 674 RTW_PWR_CUT_ALL_MSK, 675 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 676 RTW_PWR_ADDR_MAC, 677 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 678 {0x0000, 679 RTW_PWR_CUT_ALL_MSK, 680 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 681 RTW_PWR_ADDR_MAC, 682 RTW_PWR_CMD_WRITE, BIT(5), 0}, 683 {0x0005, 684 RTW_PWR_CUT_ALL_MSK, 685 RTW_PWR_INTF_ALL_MSK, 686 RTW_PWR_ADDR_MAC, 687 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 688 {0x0075, 689 RTW_PWR_CUT_ALL_MSK, 690 RTW_PWR_INTF_PCI_MSK, 691 RTW_PWR_ADDR_MAC, 692 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 693 {0x0006, 694 RTW_PWR_CUT_ALL_MSK, 695 RTW_PWR_INTF_ALL_MSK, 696 RTW_PWR_ADDR_MAC, 697 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 698 {0x0075, 699 RTW_PWR_CUT_ALL_MSK, 700 RTW_PWR_INTF_PCI_MSK, 701 RTW_PWR_ADDR_MAC, 702 RTW_PWR_CMD_WRITE, BIT(0), 0}, 703 {0x0006, 704 RTW_PWR_CUT_ALL_MSK, 705 RTW_PWR_INTF_ALL_MSK, 706 RTW_PWR_ADDR_MAC, 707 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 708 {0x0005, 709 RTW_PWR_CUT_ALL_MSK, 710 RTW_PWR_INTF_ALL_MSK, 711 RTW_PWR_ADDR_MAC, 712 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, 713 {0x0005, 714 RTW_PWR_CUT_ALL_MSK, 715 RTW_PWR_INTF_ALL_MSK, 716 RTW_PWR_ADDR_MAC, 717 RTW_PWR_CMD_WRITE, BIT(7), 0}, 718 {0x0005, 719 RTW_PWR_CUT_ALL_MSK, 720 RTW_PWR_INTF_ALL_MSK, 721 RTW_PWR_ADDR_MAC, 722 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 723 {0x0005, 724 RTW_PWR_CUT_ALL_MSK, 725 RTW_PWR_INTF_ALL_MSK, 726 RTW_PWR_ADDR_MAC, 727 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 728 {0x0005, 729 RTW_PWR_CUT_ALL_MSK, 730 RTW_PWR_INTF_ALL_MSK, 731 RTW_PWR_ADDR_MAC, 732 RTW_PWR_CMD_POLLING, BIT(0), 0}, 733 {0x0010, 734 RTW_PWR_CUT_ALL_MSK, 735 RTW_PWR_INTF_ALL_MSK, 736 RTW_PWR_ADDR_MAC, 737 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 738 {0x0049, 739 RTW_PWR_CUT_ALL_MSK, 740 RTW_PWR_INTF_ALL_MSK, 741 RTW_PWR_ADDR_MAC, 742 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 743 {0x0063, 744 RTW_PWR_CUT_ALL_MSK, 745 RTW_PWR_INTF_ALL_MSK, 746 RTW_PWR_ADDR_MAC, 747 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 748 {0x0062, 749 RTW_PWR_CUT_ALL_MSK, 750 RTW_PWR_INTF_ALL_MSK, 751 RTW_PWR_ADDR_MAC, 752 RTW_PWR_CMD_WRITE, BIT(1), 0}, 753 {0x0058, 754 RTW_PWR_CUT_ALL_MSK, 755 RTW_PWR_INTF_ALL_MSK, 756 RTW_PWR_ADDR_MAC, 757 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 758 {0x005A, 759 RTW_PWR_CUT_ALL_MSK, 760 RTW_PWR_INTF_ALL_MSK, 761 RTW_PWR_ADDR_MAC, 762 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 763 {0x0068, 764 RTW_PWR_CUT_TEST_MSK, 765 RTW_PWR_INTF_ALL_MSK, 766 RTW_PWR_ADDR_MAC, 767 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 768 {0x0069, 769 RTW_PWR_CUT_ALL_MSK, 770 RTW_PWR_INTF_ALL_MSK, 771 RTW_PWR_ADDR_MAC, 772 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 773 {0x001f, 774 RTW_PWR_CUT_ALL_MSK, 775 RTW_PWR_INTF_ALL_MSK, 776 RTW_PWR_ADDR_MAC, 777 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 778 {0x0077, 779 RTW_PWR_CUT_ALL_MSK, 780 RTW_PWR_INTF_ALL_MSK, 781 RTW_PWR_ADDR_MAC, 782 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 783 {0x001f, 784 RTW_PWR_CUT_ALL_MSK, 785 RTW_PWR_INTF_ALL_MSK, 786 RTW_PWR_ADDR_MAC, 787 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 788 {0x0077, 789 RTW_PWR_CUT_ALL_MSK, 790 RTW_PWR_INTF_ALL_MSK, 791 RTW_PWR_ADDR_MAC, 792 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 793 {0xFFFF, 794 RTW_PWR_CUT_ALL_MSK, 795 RTW_PWR_INTF_ALL_MSK, 796 0, 797 RTW_PWR_CMD_END, 0, 0}, 798 }; 799 800 static const struct rtw_pwr_seq_cmd *card_enable_flow_8723d[] = { 801 trans_carddis_to_cardemu_8723d, 802 trans_cardemu_to_act_8723d, 803 NULL 804 }; 805 806 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = { 807 {0x0301, 808 RTW_PWR_CUT_ALL_MSK, 809 RTW_PWR_INTF_PCI_MSK, 810 RTW_PWR_ADDR_MAC, 811 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 812 {0x0522, 813 RTW_PWR_CUT_ALL_MSK, 814 RTW_PWR_INTF_ALL_MSK, 815 RTW_PWR_ADDR_MAC, 816 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 817 {0x05F8, 818 RTW_PWR_CUT_ALL_MSK, 819 RTW_PWR_INTF_ALL_MSK, 820 RTW_PWR_ADDR_MAC, 821 RTW_PWR_CMD_POLLING, 0xFF, 0}, 822 {0x05F9, 823 RTW_PWR_CUT_ALL_MSK, 824 RTW_PWR_INTF_ALL_MSK, 825 RTW_PWR_ADDR_MAC, 826 RTW_PWR_CMD_POLLING, 0xFF, 0}, 827 {0x05FA, 828 RTW_PWR_CUT_ALL_MSK, 829 RTW_PWR_INTF_ALL_MSK, 830 RTW_PWR_ADDR_MAC, 831 RTW_PWR_CMD_POLLING, 0xFF, 0}, 832 {0x05FB, 833 RTW_PWR_CUT_ALL_MSK, 834 RTW_PWR_INTF_ALL_MSK, 835 RTW_PWR_ADDR_MAC, 836 RTW_PWR_CMD_POLLING, 0xFF, 0}, 837 {0x0002, 838 RTW_PWR_CUT_ALL_MSK, 839 RTW_PWR_INTF_ALL_MSK, 840 RTW_PWR_ADDR_MAC, 841 RTW_PWR_CMD_WRITE, BIT(0), 0}, 842 {0x0002, 843 RTW_PWR_CUT_ALL_MSK, 844 RTW_PWR_INTF_ALL_MSK, 845 RTW_PWR_ADDR_MAC, 846 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 847 {0x0002, 848 RTW_PWR_CUT_ALL_MSK, 849 RTW_PWR_INTF_ALL_MSK, 850 RTW_PWR_ADDR_MAC, 851 RTW_PWR_CMD_WRITE, BIT(1), 0}, 852 {0x0100, 853 RTW_PWR_CUT_ALL_MSK, 854 RTW_PWR_INTF_ALL_MSK, 855 RTW_PWR_ADDR_MAC, 856 RTW_PWR_CMD_WRITE, 0xFF, 0x03}, 857 {0x0101, 858 RTW_PWR_CUT_ALL_MSK, 859 RTW_PWR_INTF_ALL_MSK, 860 RTW_PWR_ADDR_MAC, 861 RTW_PWR_CMD_WRITE, BIT(1), 0}, 862 {0x0093, 863 RTW_PWR_CUT_ALL_MSK, 864 RTW_PWR_INTF_SDIO_MSK, 865 RTW_PWR_ADDR_MAC, 866 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 867 {0x0553, 868 RTW_PWR_CUT_ALL_MSK, 869 RTW_PWR_INTF_ALL_MSK, 870 RTW_PWR_ADDR_MAC, 871 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 872 {0xFFFF, 873 RTW_PWR_CUT_ALL_MSK, 874 RTW_PWR_INTF_ALL_MSK, 875 0, 876 RTW_PWR_CMD_END, 0, 0}, 877 }; 878 879 static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = { 880 {0x0003, 881 RTW_PWR_CUT_ALL_MSK, 882 RTW_PWR_INTF_ALL_MSK, 883 RTW_PWR_ADDR_MAC, 884 RTW_PWR_CMD_WRITE, BIT(2), 0}, 885 {0x0080, 886 RTW_PWR_CUT_ALL_MSK, 887 RTW_PWR_INTF_ALL_MSK, 888 RTW_PWR_ADDR_MAC, 889 RTW_PWR_CMD_WRITE, 0xFF, 0}, 890 {0xFFFF, 891 RTW_PWR_CUT_ALL_MSK, 892 RTW_PWR_INTF_ALL_MSK, 893 0, 894 RTW_PWR_CMD_END, 0, 0}, 895 }; 896 897 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = { 898 {0x0002, 899 RTW_PWR_CUT_ALL_MSK, 900 RTW_PWR_INTF_ALL_MSK, 901 RTW_PWR_ADDR_MAC, 902 RTW_PWR_CMD_WRITE, BIT(0), 0}, 903 {0x0049, 904 RTW_PWR_CUT_ALL_MSK, 905 RTW_PWR_INTF_ALL_MSK, 906 RTW_PWR_ADDR_MAC, 907 RTW_PWR_CMD_WRITE, BIT(1), 0}, 908 {0x0006, 909 RTW_PWR_CUT_ALL_MSK, 910 RTW_PWR_INTF_ALL_MSK, 911 RTW_PWR_ADDR_MAC, 912 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 913 {0x0005, 914 RTW_PWR_CUT_ALL_MSK, 915 RTW_PWR_INTF_ALL_MSK, 916 RTW_PWR_ADDR_MAC, 917 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 918 {0x0005, 919 RTW_PWR_CUT_ALL_MSK, 920 RTW_PWR_INTF_ALL_MSK, 921 RTW_PWR_ADDR_MAC, 922 RTW_PWR_CMD_POLLING, BIT(1), 0}, 923 {0x0010, 924 RTW_PWR_CUT_ALL_MSK, 925 RTW_PWR_INTF_ALL_MSK, 926 RTW_PWR_ADDR_MAC, 927 RTW_PWR_CMD_WRITE, BIT(6), 0}, 928 {0x0000, 929 RTW_PWR_CUT_ALL_MSK, 930 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 931 RTW_PWR_ADDR_MAC, 932 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 933 {0x0020, 934 RTW_PWR_CUT_ALL_MSK, 935 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 936 RTW_PWR_ADDR_MAC, 937 RTW_PWR_CMD_WRITE, BIT(0), 0}, 938 {0xFFFF, 939 RTW_PWR_CUT_ALL_MSK, 940 RTW_PWR_INTF_ALL_MSK, 941 0, 942 RTW_PWR_CMD_END, 0, 0}, 943 }; 944 945 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = { 946 {0x0007, 947 RTW_PWR_CUT_ALL_MSK, 948 RTW_PWR_INTF_SDIO_MSK, 949 RTW_PWR_ADDR_MAC, 950 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 951 {0x0005, 952 RTW_PWR_CUT_ALL_MSK, 953 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 954 RTW_PWR_ADDR_MAC, 955 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 956 {0x0005, 957 RTW_PWR_CUT_ALL_MSK, 958 RTW_PWR_INTF_PCI_MSK, 959 RTW_PWR_ADDR_MAC, 960 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 961 {0x0005, 962 RTW_PWR_CUT_ALL_MSK, 963 RTW_PWR_INTF_PCI_MSK, 964 RTW_PWR_ADDR_MAC, 965 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, 966 {0x004A, 967 RTW_PWR_CUT_ALL_MSK, 968 RTW_PWR_INTF_USB_MSK, 969 RTW_PWR_ADDR_MAC, 970 RTW_PWR_CMD_WRITE, BIT(0), 1}, 971 {0x0023, 972 RTW_PWR_CUT_ALL_MSK, 973 RTW_PWR_INTF_SDIO_MSK, 974 RTW_PWR_ADDR_MAC, 975 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 976 {0x0086, 977 RTW_PWR_CUT_ALL_MSK, 978 RTW_PWR_INTF_SDIO_MSK, 979 RTW_PWR_ADDR_SDIO, 980 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 981 {0x0086, 982 RTW_PWR_CUT_ALL_MSK, 983 RTW_PWR_INTF_SDIO_MSK, 984 RTW_PWR_ADDR_SDIO, 985 RTW_PWR_CMD_POLLING, BIT(1), 0}, 986 {0xFFFF, 987 RTW_PWR_CUT_ALL_MSK, 988 RTW_PWR_INTF_ALL_MSK, 989 0, 990 RTW_PWR_CMD_END, 0, 0}, 991 }; 992 993 static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = { 994 {0x001D, 995 RTW_PWR_CUT_ALL_MSK, 996 RTW_PWR_INTF_ALL_MSK, 997 RTW_PWR_ADDR_MAC, 998 RTW_PWR_CMD_WRITE, BIT(0), 0}, 999 {0x001D, 1000 RTW_PWR_CUT_ALL_MSK, 1001 RTW_PWR_INTF_ALL_MSK, 1002 RTW_PWR_ADDR_MAC, 1003 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1004 {0x001C, 1005 RTW_PWR_CUT_ALL_MSK, 1006 RTW_PWR_INTF_ALL_MSK, 1007 RTW_PWR_ADDR_MAC, 1008 RTW_PWR_CMD_WRITE, 0xFF, 0x0E}, 1009 {0xFFFF, 1010 RTW_PWR_CUT_ALL_MSK, 1011 RTW_PWR_INTF_ALL_MSK, 1012 0, 1013 RTW_PWR_CMD_END, 0, 0}, 1014 }; 1015 1016 static const struct rtw_pwr_seq_cmd *card_disable_flow_8723d[] = { 1017 trans_act_to_lps_8723d, 1018 trans_act_to_pre_carddis_8723d, 1019 trans_act_to_cardemu_8723d, 1020 trans_cardemu_to_carddis_8723d, 1021 trans_act_to_post_carddis_8723d, 1022 NULL 1023 }; 1024 1025 static const struct rtw_page_table page_table_8723d[] = { 1026 {12, 2, 2, 0, 1}, 1027 {12, 2, 2, 0, 1}, 1028 {12, 2, 2, 0, 1}, 1029 {12, 2, 2, 0, 1}, 1030 {12, 2, 2, 0, 1}, 1031 }; 1032 1033 static const struct rtw_rqpn rqpn_table_8723d[] = { 1034 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1035 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1036 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1037 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1038 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1039 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1040 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1041 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1042 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1043 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1044 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1045 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1046 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1047 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1048 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1049 }; 1050 1051 static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = { 1052 {0x0008, 0x4a22, 1053 RTW_IP_SEL_PHY, 1054 RTW_INTF_PHY_CUT_ALL, 1055 RTW_INTF_PHY_PLATFORM_ALL}, 1056 {0x0009, 0x1000, 1057 RTW_IP_SEL_PHY, 1058 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B), 1059 RTW_INTF_PHY_PLATFORM_ALL}, 1060 {0xFFFF, 0x0000, 1061 RTW_IP_SEL_PHY, 1062 RTW_INTF_PHY_CUT_ALL, 1063 RTW_INTF_PHY_PLATFORM_ALL}, 1064 }; 1065 1066 static const struct rtw_intf_phy_para_table phy_para_table_8723d = { 1067 .gen1_para = pcie_gen1_param_8723d, 1068 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d), 1069 }; 1070 1071 static const struct rtw_hw_reg rtw8723d_dig[] = { 1072 [0] = { .addr = 0xc50, .mask = 0x7f }, 1073 [1] = { .addr = 0xc50, .mask = 0x7f }, 1074 }; 1075 1076 static const struct rtw_hw_reg rtw8723d_dig_cck[] = { 1077 [0] = { .addr = 0xa0c, .mask = 0x3f00 }, 1078 }; 1079 1080 static const struct rtw_rf_sipi_addr rtw8723d_rf_sipi_addr[] = { 1081 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, 1082 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, 1083 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, 1084 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, 1085 }; 1086 1087 static const struct rtw_rfe_def rtw8723d_rfe_defs[] = { 1088 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl, 1089 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,}, 1090 }; 1091 1092 struct rtw_chip_info rtw8723d_hw_spec = { 1093 .ops = &rtw8723d_ops, 1094 .id = RTW_CHIP_TYPE_8723D, 1095 .fw_name = "rtw88/rtw8723d_fw.bin", 1096 .wlan_cpu = RTW_WCPU_11N, 1097 .tx_pkt_desc_sz = 40, 1098 .tx_buf_desc_sz = 16, 1099 .rx_pkt_desc_sz = 24, 1100 .rx_buf_desc_sz = 8, 1101 .phy_efuse_size = 512, 1102 .log_efuse_size = 512, 1103 .ptct_efuse_size = 96 + 1, 1104 .txff_size = 32768, 1105 .rxff_size = 16384, 1106 .txgi_factor = 1, 1107 .is_pwr_by_rate_dec = true, 1108 .max_power_index = 0x3f, 1109 .csi_buf_pg_num = 0, 1110 .band = RTW_BAND_2G, 1111 .page_size = 128, 1112 .dig_min = 0x20, 1113 .ht_supported = true, 1114 .vht_supported = false, 1115 .lps_deep_mode_supported = 0, 1116 .sys_func_en = 0xFD, 1117 .pwr_on_seq = card_enable_flow_8723d, 1118 .pwr_off_seq = card_disable_flow_8723d, 1119 .page_table = page_table_8723d, 1120 .rqpn_table = rqpn_table_8723d, 1121 .intf_table = &phy_para_table_8723d, 1122 .dig = rtw8723d_dig, 1123 .dig_cck = rtw8723d_dig_cck, 1124 .rf_sipi_addr = {0x840, 0x844}, 1125 .rf_sipi_read_addr = rtw8723d_rf_sipi_addr, 1126 .fix_rf_phy_num = 2, 1127 .mac_tbl = &rtw8723d_mac_tbl, 1128 .agc_tbl = &rtw8723d_agc_tbl, 1129 .bb_tbl = &rtw8723d_bb_tbl, 1130 .rf_tbl = {&rtw8723d_rf_a_tbl}, 1131 .rfe_defs = rtw8723d_rfe_defs, 1132 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs), 1133 .rx_ldpc = false, 1134 }; 1135 EXPORT_SYMBOL(rtw8723d_hw_spec); 1136 1137 MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin"); 1138