1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright Fiona Klute <fiona.klute@gmx.de> */ 3 4 #include <linux/of_net.h> 5 #include "main.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rx.h" 12 #include "rtw8703b.h" 13 #include "rtw8703b_tables.h" 14 #include "rtw8723x.h" 15 16 #define BIT_MASK_TXQ_INIT (BIT(7)) 17 #define WLAN_RL_VAL 0x3030 18 /* disable BAR */ 19 #define WLAN_BAR_VAL 0x0201ffff 20 #define WLAN_PIFS_VAL 0 21 #define WLAN_RX_PKT_LIMIT 0x18 22 #define WLAN_SLOT_TIME 0x09 23 #define WLAN_SPEC_SIFS 0x100a 24 #define WLAN_MAX_AGG_NR 0x1f 25 #define WLAN_AMPDU_MAX_TIME 0x70 26 27 /* unit is 32us */ 28 #define TBTT_PROHIBIT_SETUP_TIME 0x04 29 #define TBTT_PROHIBIT_HOLD_TIME 0x80 30 #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 31 32 #define TRANS_SEQ_END \ 33 0xFFFF, \ 34 RTW_PWR_CUT_ALL_MSK, \ 35 RTW_PWR_INTF_ALL_MSK, \ 36 0, \ 37 RTW_PWR_CMD_END, 0, 0 38 39 /* rssi in percentage % (dbm = % - 100) */ 40 /* These are used to select simple signal quality levels, might need 41 * tweaking. Same for rf_para tables below. 42 */ 43 static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30}; 44 static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30}; 45 static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} }; 46 47 /* Actually decreasing wifi TX power/RX gain isn't implemented in 48 * rtw8703b, but hopefully adjusting the BT side helps. 49 */ 50 static const struct coex_rf_para rf_para_tx_8703b[] = { 51 {0, 0, false, 7}, /* for normal */ 52 {0, 10, false, 7}, /* for WL-CPT */ 53 {1, 0, true, 4}, 54 {1, 2, true, 4}, 55 {1, 10, true, 4}, 56 {1, 15, true, 4} 57 }; 58 59 static const struct coex_rf_para rf_para_rx_8703b[] = { 60 {0, 0, false, 7}, /* for normal */ 61 {0, 10, false, 7}, /* for WL-CPT */ 62 {1, 0, true, 5}, 63 {1, 2, true, 5}, 64 {1, 10, true, 5}, 65 {1, 15, true, 5} 66 }; 67 68 static const u32 rtw8703b_ofdm_swing_table[] = { 69 0x0b40002d, /* 0, -15.0dB */ 70 0x0c000030, /* 1, -14.5dB */ 71 0x0cc00033, /* 2, -14.0dB */ 72 0x0d800036, /* 3, -13.5dB */ 73 0x0e400039, /* 4, -13.0dB */ 74 0x0f00003c, /* 5, -12.5dB */ 75 0x10000040, /* 6, -12.0dB */ 76 0x11000044, /* 7, -11.5dB */ 77 0x12000048, /* 8, -11.0dB */ 78 0x1300004c, /* 9, -10.5dB */ 79 0x14400051, /* 10, -10.0dB */ 80 0x15800056, /* 11, -9.5dB */ 81 0x16c0005b, /* 12, -9.0dB */ 82 0x18000060, /* 13, -8.5dB */ 83 0x19800066, /* 14, -8.0dB */ 84 0x1b00006c, /* 15, -7.5dB */ 85 0x1c800072, /* 16, -7.0dB */ 86 0x1e400079, /* 17, -6.5dB */ 87 0x20000080, /* 18, -6.0dB */ 88 0x22000088, /* 19, -5.5dB */ 89 0x24000090, /* 20, -5.0dB */ 90 0x26000098, /* 21, -4.5dB */ 91 0x288000a2, /* 22, -4.0dB */ 92 0x2ac000ab, /* 23, -3.5dB */ 93 0x2d4000b5, /* 24, -3.0dB */ 94 0x300000c0, /* 25, -2.5dB */ 95 0x32c000cb, /* 26, -2.0dB */ 96 0x35c000d7, /* 27, -1.5dB */ 97 0x390000e4, /* 28, -1.0dB */ 98 0x3c8000f2, /* 29, -0.5dB */ 99 0x40000100, /* 30, +0dB */ 100 0x43c0010f, /* 31, +0.5dB */ 101 0x47c0011f, /* 32, +1.0dB */ 102 0x4c000130, /* 33, +1.5dB */ 103 0x50800142, /* 34, +2.0dB */ 104 0x55400155, /* 35, +2.5dB */ 105 0x5a400169, /* 36, +3.0dB */ 106 0x5fc0017f, /* 37, +3.5dB */ 107 0x65400195, /* 38, +4.0dB */ 108 0x6b8001ae, /* 39, +4.5dB */ 109 0x71c001c7, /* 40, +5.0dB */ 110 0x788001e2, /* 41, +5.5dB */ 111 0x7f8001fe /* 42, +6.0dB */ 112 }; 113 114 static const u32 rtw8703b_cck_pwr_regs[] = { 115 0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29, 116 0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3, 117 }; 118 119 static const u8 rtw8703b_cck_swing_table[][16] = { 120 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ 122 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ 124 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ 126 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ 128 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ 130 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ 132 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ 134 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ 136 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ 138 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ 140 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ 142 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ 144 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ 146 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ 148 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ 150 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ 152 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ 154 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ 156 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ 158 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ 160 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ 162 }; 163 164 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table) 165 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table) 166 167 static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = { 168 /* set up external crystal (XTAL) */ 169 {REG_PAD_CTRL1 + 2, 170 RTW_PWR_CUT_ALL_MSK, 171 RTW_PWR_INTF_ALL_MSK, 172 RTW_PWR_ADDR_MAC, 173 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 174 /* set CLK_REQ to high active */ 175 {0x0069, 176 RTW_PWR_CUT_ALL_MSK, 177 RTW_PWR_INTF_ALL_MSK, 178 RTW_PWR_ADDR_MAC, 179 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 180 /* unlock ISO/CLK/power control register */ 181 {REG_RSV_CTRL, 182 RTW_PWR_CUT_ALL_MSK, 183 RTW_PWR_INTF_ALL_MSK, 184 RTW_PWR_ADDR_MAC, 185 RTW_PWR_CMD_WRITE, 0xff, 0}, 186 {TRANS_SEQ_END}, 187 }; 188 189 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = { 190 {0x0005, 191 RTW_PWR_CUT_ALL_MSK, 192 RTW_PWR_INTF_ALL_MSK, 193 RTW_PWR_ADDR_MAC, 194 RTW_PWR_CMD_WRITE, BIT(7), 0}, 195 {TRANS_SEQ_END}, 196 }; 197 198 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = { 199 {0x0023, 200 RTW_PWR_CUT_ALL_MSK, 201 RTW_PWR_INTF_SDIO_MSK, 202 RTW_PWR_ADDR_MAC, 203 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 204 {0x0007, 205 RTW_PWR_CUT_ALL_MSK, 206 RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK, 207 RTW_PWR_ADDR_MAC, 208 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 209 {0x0006, 210 RTW_PWR_CUT_ALL_MSK, 211 RTW_PWR_INTF_ALL_MSK, 212 RTW_PWR_ADDR_MAC, 213 RTW_PWR_CMD_WRITE, BIT(0), 0}, 214 {0x0005, 215 RTW_PWR_CUT_ALL_MSK, 216 RTW_PWR_INTF_ALL_MSK, 217 RTW_PWR_ADDR_MAC, 218 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 219 {TRANS_SEQ_END}, 220 }; 221 222 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = { 223 {0x0020, 224 RTW_PWR_CUT_ALL_MSK, 225 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 226 RTW_PWR_ADDR_MAC, 227 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 228 {0x0067, 229 RTW_PWR_CUT_ALL_MSK, 230 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 231 RTW_PWR_ADDR_MAC, 232 RTW_PWR_CMD_WRITE, BIT(4), 0}, 233 {0x0001, 234 RTW_PWR_CUT_ALL_MSK, 235 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 236 RTW_PWR_ADDR_MAC, 237 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 238 {0x0000, 239 RTW_PWR_CUT_ALL_MSK, 240 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 241 RTW_PWR_ADDR_MAC, 242 RTW_PWR_CMD_WRITE, BIT(5), 0}, 243 {0x0005, 244 RTW_PWR_CUT_ALL_MSK, 245 RTW_PWR_INTF_ALL_MSK, 246 RTW_PWR_ADDR_MAC, 247 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 248 {0x0075, 249 RTW_PWR_CUT_ALL_MSK, 250 RTW_PWR_INTF_PCI_MSK, 251 RTW_PWR_ADDR_MAC, 252 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 253 {0x0004, 254 RTW_PWR_CUT_ALL_MSK, 255 RTW_PWR_INTF_PCI_MSK, 256 RTW_PWR_ADDR_MAC, 257 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 258 {0x0004, 259 RTW_PWR_CUT_ALL_MSK, 260 RTW_PWR_INTF_PCI_MSK, 261 RTW_PWR_ADDR_MAC, 262 RTW_PWR_CMD_WRITE, BIT(3), 0}, 263 /* wait for power ready */ 264 {0x0006, 265 RTW_PWR_CUT_ALL_MSK, 266 RTW_PWR_INTF_ALL_MSK, 267 RTW_PWR_ADDR_MAC, 268 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 269 {0x0075, 270 RTW_PWR_CUT_ALL_MSK, 271 RTW_PWR_INTF_PCI_MSK, 272 RTW_PWR_ADDR_MAC, 273 RTW_PWR_CMD_WRITE, BIT(0), 0}, 274 {0x0006, 275 RTW_PWR_CUT_ALL_MSK, 276 RTW_PWR_INTF_ALL_MSK, 277 RTW_PWR_ADDR_MAC, 278 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 279 {0x0005, 280 RTW_PWR_CUT_ALL_MSK, 281 RTW_PWR_INTF_ALL_MSK, 282 RTW_PWR_ADDR_MAC, 283 RTW_PWR_CMD_WRITE, BIT(7), 0}, 284 {0x0005, 285 RTW_PWR_CUT_ALL_MSK, 286 RTW_PWR_INTF_ALL_MSK, 287 RTW_PWR_ADDR_MAC, 288 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 289 {0x0005, 290 RTW_PWR_CUT_ALL_MSK, 291 RTW_PWR_INTF_ALL_MSK, 292 RTW_PWR_ADDR_MAC, 293 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 294 {0x0005, 295 RTW_PWR_CUT_ALL_MSK, 296 RTW_PWR_INTF_ALL_MSK, 297 RTW_PWR_ADDR_MAC, 298 RTW_PWR_CMD_POLLING, BIT(0), 0}, 299 {0x0010, 300 RTW_PWR_CUT_ALL_MSK, 301 RTW_PWR_INTF_ALL_MSK, 302 RTW_PWR_ADDR_MAC, 303 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 304 {0x0049, 305 RTW_PWR_CUT_ALL_MSK, 306 RTW_PWR_INTF_ALL_MSK, 307 RTW_PWR_ADDR_MAC, 308 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 309 {0x0063, 310 RTW_PWR_CUT_ALL_MSK, 311 RTW_PWR_INTF_ALL_MSK, 312 RTW_PWR_ADDR_MAC, 313 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 314 {0x0062, 315 RTW_PWR_CUT_ALL_MSK, 316 RTW_PWR_INTF_ALL_MSK, 317 RTW_PWR_ADDR_MAC, 318 RTW_PWR_CMD_WRITE, BIT(1), 0}, 319 {0x0058, 320 RTW_PWR_CUT_ALL_MSK, 321 RTW_PWR_INTF_ALL_MSK, 322 RTW_PWR_ADDR_MAC, 323 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 324 {0x005A, 325 RTW_PWR_CUT_ALL_MSK, 326 RTW_PWR_INTF_ALL_MSK, 327 RTW_PWR_ADDR_MAC, 328 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 329 {0x0068, 330 RTW_PWR_CUT_TEST_MSK, 331 RTW_PWR_INTF_ALL_MSK, 332 RTW_PWR_ADDR_MAC, 333 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 334 {0x0069, 335 RTW_PWR_CUT_ALL_MSK, 336 RTW_PWR_INTF_ALL_MSK, 337 RTW_PWR_ADDR_MAC, 338 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 339 {TRANS_SEQ_END}, 340 }; 341 342 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = { 343 {0x001f, 344 RTW_PWR_CUT_ALL_MSK, 345 RTW_PWR_INTF_ALL_MSK, 346 RTW_PWR_ADDR_MAC, 347 RTW_PWR_CMD_WRITE, 0xff, 0}, 348 {0x0049, 349 RTW_PWR_CUT_ALL_MSK, 350 RTW_PWR_INTF_ALL_MSK, 351 RTW_PWR_ADDR_MAC, 352 RTW_PWR_CMD_WRITE, BIT(1), 0}, 353 {0x0006, 354 RTW_PWR_CUT_ALL_MSK, 355 RTW_PWR_INTF_ALL_MSK, 356 RTW_PWR_ADDR_MAC, 357 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 358 {0x0005, 359 RTW_PWR_CUT_ALL_MSK, 360 RTW_PWR_INTF_ALL_MSK, 361 RTW_PWR_ADDR_MAC, 362 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 363 {0x0005, 364 RTW_PWR_CUT_ALL_MSK, 365 RTW_PWR_INTF_ALL_MSK, 366 RTW_PWR_ADDR_MAC, 367 RTW_PWR_CMD_POLLING, BIT(1), 0}, 368 {0x0010, 369 RTW_PWR_CUT_ALL_MSK, 370 RTW_PWR_INTF_ALL_MSK, 371 RTW_PWR_ADDR_MAC, 372 RTW_PWR_CMD_WRITE, BIT(6), 0}, 373 {0x0000, 374 RTW_PWR_CUT_ALL_MSK, 375 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 376 RTW_PWR_ADDR_MAC, 377 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 378 {0x0020, 379 RTW_PWR_CUT_ALL_MSK, 380 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 381 RTW_PWR_ADDR_MAC, 382 RTW_PWR_CMD_WRITE, BIT(0), 0}, 383 {TRANS_SEQ_END}, 384 }; 385 386 static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = { 387 {REG_SYS_FUNC_EN + 1, 388 RTW_PWR_CUT_ALL_MSK, 389 RTW_PWR_INTF_SDIO_MSK, 390 RTW_PWR_ADDR_MAC, 391 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0}, 392 /* reset MCU ready */ 393 {REG_MCUFW_CTRL, 394 RTW_PWR_CUT_ALL_MSK, 395 RTW_PWR_INTF_SDIO_MSK, 396 RTW_PWR_ADDR_MAC, 397 RTW_PWR_CMD_WRITE, 0xff, 0}, 398 /* reset MCU IO wrapper */ 399 {REG_RSV_CTRL + 1, 400 RTW_PWR_CUT_ALL_MSK, 401 RTW_PWR_INTF_SDIO_MSK, 402 RTW_PWR_ADDR_MAC, 403 RTW_PWR_CMD_WRITE, BIT(0), 0}, 404 {REG_RSV_CTRL + 1, 405 RTW_PWR_CUT_ALL_MSK, 406 RTW_PWR_INTF_SDIO_MSK, 407 RTW_PWR_ADDR_MAC, 408 RTW_PWR_CMD_WRITE, BIT(0), 1}, 409 {TRANS_SEQ_END}, 410 }; 411 412 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = { 413 {0x0301, 414 RTW_PWR_CUT_ALL_MSK, 415 RTW_PWR_INTF_ALL_MSK, 416 RTW_PWR_ADDR_MAC, 417 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 418 {0x0522, 419 RTW_PWR_CUT_ALL_MSK, 420 RTW_PWR_INTF_ALL_MSK, 421 RTW_PWR_ADDR_MAC, 422 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 423 {0x05f8, 424 RTW_PWR_CUT_ALL_MSK, 425 RTW_PWR_INTF_ALL_MSK, 426 RTW_PWR_ADDR_MAC, 427 RTW_PWR_CMD_POLLING, 0xff, 0}, 428 {0x05f9, 429 RTW_PWR_CUT_ALL_MSK, 430 RTW_PWR_INTF_ALL_MSK, 431 RTW_PWR_ADDR_MAC, 432 RTW_PWR_CMD_POLLING, 0xff, 0}, 433 {0x05fa, 434 RTW_PWR_CUT_ALL_MSK, 435 RTW_PWR_INTF_ALL_MSK, 436 RTW_PWR_ADDR_MAC, 437 RTW_PWR_CMD_POLLING, 0xff, 0}, 438 {0x05fb, 439 RTW_PWR_CUT_ALL_MSK, 440 RTW_PWR_INTF_ALL_MSK, 441 RTW_PWR_ADDR_MAC, 442 RTW_PWR_CMD_POLLING, 0xff, 0}, 443 {0x0002, 444 RTW_PWR_CUT_ALL_MSK, 445 RTW_PWR_INTF_ALL_MSK, 446 RTW_PWR_ADDR_MAC, 447 RTW_PWR_CMD_WRITE, BIT(0), 0}, 448 {0x0002, 449 RTW_PWR_CUT_ALL_MSK, 450 RTW_PWR_INTF_ALL_MSK, 451 RTW_PWR_ADDR_MAC, 452 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 453 {0x0002, 454 RTW_PWR_CUT_ALL_MSK, 455 RTW_PWR_INTF_ALL_MSK, 456 RTW_PWR_ADDR_MAC, 457 RTW_PWR_CMD_WRITE, BIT(1), 0}, 458 {0x0100, 459 RTW_PWR_CUT_ALL_MSK, 460 RTW_PWR_INTF_ALL_MSK, 461 RTW_PWR_ADDR_MAC, 462 RTW_PWR_CMD_WRITE, 0xff, 0x03}, 463 {0x0101, 464 RTW_PWR_CUT_ALL_MSK, 465 RTW_PWR_INTF_ALL_MSK, 466 RTW_PWR_ADDR_MAC, 467 RTW_PWR_CMD_WRITE, BIT(1), 0}, 468 {0x0093, 469 RTW_PWR_CUT_ALL_MSK, 470 RTW_PWR_INTF_SDIO_MSK, 471 RTW_PWR_ADDR_MAC, 472 RTW_PWR_CMD_WRITE, 0xff, 0}, 473 {0x0553, 474 RTW_PWR_CUT_ALL_MSK, 475 RTW_PWR_INTF_ALL_MSK, 476 RTW_PWR_ADDR_MAC, 477 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 478 {TRANS_SEQ_END}, 479 }; 480 481 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8703b[] = { 482 trans_pre_enable_8703b, 483 trans_carddis_to_cardemu_8703b, 484 trans_cardemu_to_act_8703b, 485 NULL 486 }; 487 488 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8703b[] = { 489 trans_act_to_lps_8703b, 490 trans_act_to_reset_mcu_8703b, 491 trans_act_to_cardemu_8703b, 492 trans_cardemu_to_carddis_8703b, 493 NULL 494 }; 495 496 static const struct rtw_rfe_def rtw8703b_rfe_defs[] = { 497 [0] = { .phy_pg_tbl = &rtw8703b_bb_pg_tbl, 498 .txpwr_lmt_tbl = &rtw8703b_txpwr_lmt_tbl,}, 499 }; 500 501 static const struct rtw_page_table page_table_8703b[] = { 502 {12, 2, 2, 0, 1}, 503 {12, 2, 2, 0, 1}, 504 {12, 2, 2, 0, 1}, 505 {12, 2, 2, 0, 1}, 506 {12, 2, 2, 0, 1}, 507 }; 508 509 static const struct rtw_rqpn rqpn_table_8703b[] = { 510 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 511 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 512 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 513 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 514 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 515 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 516 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 517 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 518 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 519 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 520 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 521 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 522 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 523 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 524 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 525 }; 526 527 /* Default power index table for RTL8703B, used if EFUSE does not 528 * contain valid data. Replaces EFUSE data from offset 0x10 (start of 529 * txpwr_idx_table). 530 */ 531 static const u8 rtw8703b_txpwr_idx_table[] = { 532 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 533 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02 534 }; 535 536 static void try_mac_from_devicetree(struct rtw_dev *rtwdev) 537 { 538 struct device_node *node = rtwdev->dev->of_node; 539 struct rtw_efuse *efuse = &rtwdev->efuse; 540 int ret; 541 542 if (node) { 543 ret = of_get_mac_address(node, efuse->addr); 544 if (ret == 0) { 545 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 546 "got wifi mac address from DT: %pM\n", 547 efuse->addr); 548 } 549 } 550 } 551 552 #define DBG_EFUSE_FIX(rtwdev, name) \ 553 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \ 554 # name "=0x%x\n", rtwdev->efuse.name) 555 556 static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 557 { 558 struct rtw_efuse *efuse = &rtwdev->efuse; 559 u8 *pwr = (u8 *)efuse->txpwr_idx_table; 560 bool valid = false; 561 int ret; 562 563 ret = rtw8723x_read_efuse(rtwdev, log_map); 564 if (ret != 0) 565 return ret; 566 567 if (!is_valid_ether_addr(efuse->addr)) 568 try_mac_from_devicetree(rtwdev); 569 570 /* If TX power index table in EFUSE is invalid, fall back to 571 * built-in table. 572 */ 573 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) 574 if (pwr[i] != 0xff) { 575 valid = true; 576 break; 577 } 578 if (!valid) { 579 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) 580 pwr[i] = rtw8703b_txpwr_idx_table[i]; 581 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 582 "Replaced invalid EFUSE TX power index table."); 583 rtw8723x_debug_txpwr_limit(rtwdev, 584 efuse->txpwr_idx_table, 2); 585 } 586 587 /* Override invalid antenna settings. */ 588 if (efuse->bt_setting == 0xff) { 589 /* shared antenna */ 590 efuse->bt_setting |= BIT(0); 591 /* RF path A */ 592 efuse->bt_setting &= ~BIT(6); 593 DBG_EFUSE_FIX(rtwdev, bt_setting); 594 } 595 596 /* Override invalid board options: The coex code incorrectly 597 * assumes that if bits 6 & 7 are set the board doesn't 598 * support coex. Regd is also derived from rf_board_option and 599 * should be 0 if there's no valid data. 600 */ 601 if (efuse->rf_board_option == 0xff) { 602 efuse->regd = 0; 603 efuse->rf_board_option &= GENMASK(5, 0); 604 DBG_EFUSE_FIX(rtwdev, rf_board_option); 605 } 606 607 /* Override invalid crystal cap setting, default comes from 608 * vendor driver. Chip specific. 609 */ 610 if (efuse->crystal_cap == 0xff) { 611 efuse->crystal_cap = 0x20; 612 DBG_EFUSE_FIX(rtwdev, crystal_cap); 613 } 614 615 return 0; 616 } 617 618 static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev) 619 { 620 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 621 u8 path; 622 623 /* TODO: The vendor driver selects these using tables in 624 * halrf_powertracking_ce.c, functions are called 625 * get_swing_index and get_cck_swing_index. There the current 626 * fixed values are only the defaults in case no match is 627 * found. 628 */ 629 dm_info->default_ofdm_index = 30; 630 dm_info->default_cck_index = 20; 631 632 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 633 ewma_thermal_init(&dm_info->avg_thermal[path]); 634 dm_info->delta_power_index[path] = 0; 635 } 636 dm_info->pwr_trk_triggered = false; 637 dm_info->pwr_trk_init_trigger = true; 638 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 639 dm_info->txagc_remnant_cck = 0; 640 dm_info->txagc_remnant_ofdm = 0; 641 } 642 643 static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev) 644 { 645 u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 646 647 /* power on BB/RF domain */ 648 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 649 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 650 rtw_write8_set(rtwdev, REG_RF_CTRL, 651 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 652 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780); 653 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 654 655 rtw_phy_load_tables(rtwdev); 656 657 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 658 /* 0xff is from vendor driver, rtw8723d uses 659 * BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet 660 * in Hi Queue Tx immediately". I wonder if setting all bits 661 * is really necessary. 662 */ 663 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff); 664 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 665 666 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 667 xtal_cap | (xtal_cap << 6)); 668 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 669 670 /* Init EDCA */ 671 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS); 672 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 673 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */ 674 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */ 675 /* TXOP */ 676 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); 677 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); 678 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); 679 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); 680 681 /* Init retry */ 682 rtw_write8(rtwdev, REG_ACKTO, 0x40); 683 684 /* Set up RX aggregation. sdio.c also sets DMA mode, but not 685 * the burst parameters. 686 */ 687 rtw_write8(rtwdev, REG_RXDMA_MODE, 688 BIT_DMA_MODE | 689 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) | 690 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE)); 691 692 /* Init beacon parameters */ 693 rtw_write8(rtwdev, REG_BCN_CTRL, 694 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 695 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME); 696 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1, 697 TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); 698 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2, 699 (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0) 700 | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); 701 702 /* configure packet burst */ 703 rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 704 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 705 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 706 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 707 rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT); 708 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 709 710 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 711 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 712 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 713 rtw_write16(rtwdev, REG_ATIMWND, 0x2); 714 715 rtw_phy_init(rtwdev); 716 717 if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) { 718 rtwdev->dm_info.rx_cck_agc_report_type = 1; 719 } else { 720 rtwdev->dm_info.rx_cck_agc_report_type = 0; 721 rtw_warn(rtwdev, "unexpected cck agc report type"); 722 } 723 724 rtw8723x_lck(rtwdev); 725 726 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 727 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 728 729 rtw8703b_pwrtrack_init(rtwdev); 730 } 731 732 static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev, 733 u32 freq, u32 thres) 734 { 735 bool ret = false; 736 737 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 738 rtw_write32(rtwdev, REG_PSDFN, freq); 739 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 740 741 msleep(30); 742 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 743 ret = true; 744 745 rtw_write32(rtwdev, REG_PSDFN, freq); 746 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 747 748 return ret; 749 } 750 751 static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 752 { 753 if (!notch) { 754 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 755 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 756 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 757 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 758 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 759 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 760 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 761 return; 762 } 763 764 switch (channel) { 765 case 5: 766 fallthrough; 767 case 13: 768 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 769 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 770 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000); 771 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 772 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 773 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 774 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 775 break; 776 case 6: 777 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4); 778 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 779 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600); 780 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 781 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 782 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 783 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 784 break; 785 case 7: 786 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3); 787 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 788 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 789 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 790 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 791 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000); 792 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 793 break; 794 case 8: 795 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa); 796 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 797 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 798 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 799 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 800 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380); 801 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 802 break; 803 case 14: 804 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 805 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 806 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 807 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 808 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 809 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000); 810 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 811 break; 812 default: 813 rtw_warn(rtwdev, 814 "Bug: Notch filter enable called for channel %u!", 815 channel); 816 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 817 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 818 break; 819 } 820 } 821 822 static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel) 823 { 824 bool notch; 825 u32 freq; 826 827 if (channel == 5) { 828 freq = FREQ_CH5; 829 } else if (channel == 6) { 830 freq = FREQ_CH6; 831 } else if (channel == 7) { 832 freq = FREQ_CH7; 833 } else if (channel == 8) { 834 freq = FREQ_CH8; 835 } else if (channel == 13) { 836 freq = FREQ_CH13; 837 } else if (channel == 14) { 838 freq = FREQ_CH14; 839 } else { 840 rtw8703b_cfg_notch(rtwdev, channel, false); 841 return; 842 } 843 844 notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES); 845 rtw8703b_cfg_notch(rtwdev, channel, notch); 846 } 847 848 static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 849 { 850 u32 rf_cfgch_a; 851 u32 rf_cfgch_b; 852 /* default value for 20M */ 853 u32 rf_rck = 0x00000C08; 854 855 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 856 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 857 858 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 859 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 860 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 861 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 862 863 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 864 switch (bw) { 865 case RTW_CHANNEL_WIDTH_20: 866 rf_cfgch_a |= RFCFGCH_BW_20M; 867 break; 868 case RTW_CHANNEL_WIDTH_40: 869 rf_cfgch_a |= RFCFGCH_BW_40M; 870 rf_rck = 0x00000C4C; 871 break; 872 default: 873 break; 874 } 875 876 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 877 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 878 879 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck); 880 rtw8703b_spur_cal(rtwdev, channel); 881 } 882 883 #define CCK_DFIR_NR_8703B 2 884 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = { 885 [0] = { 886 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD }, 887 { .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B }, 888 }, 889 [1] = { 890 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 }, 891 { .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 }, 892 }, 893 }; 894 895 static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 896 u8 primary_ch_idx) 897 { 898 const struct rtw_backup_info *cck_dfir; 899 int i; 900 901 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 902 903 for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++) 904 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 905 906 switch (bw) { 907 case RTW_CHANNEL_WIDTH_20: 908 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 909 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 910 rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE, 911 GENMASK(31, 20), 0x0); 912 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000); 913 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000); 914 break; 915 case RTW_CHANNEL_WIDTH_40: 916 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 917 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 918 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000); 919 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000); 920 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 921 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0); 922 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00, 923 primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1); 924 925 rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26), 926 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2); 927 break; 928 default: 929 break; 930 } 931 } 932 933 static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel, 934 u8 bw, u8 primary_chan_idx) 935 { 936 rtw8703b_set_channel_rf(rtwdev, channel, bw); 937 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 938 rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 939 } 940 941 /* Not all indices are valid, based on available data. None of the 942 * known valid values are positive, so use 0x7f as "invalid". 943 */ 944 #define LNA_IDX_INVALID 0x7f 945 static const s8 lna_gain_table[16] = { 946 -2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, 947 -6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19, 948 -32, LNA_IDX_INVALID, -36, -42, 949 LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48, 950 }; 951 952 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 953 { 954 s8 lna_gain = 0; 955 956 if (lna_idx < ARRAY_SIZE(lna_gain_table)) 957 lna_gain = lna_gain_table[lna_idx]; 958 959 if (lna_gain >= 0) { 960 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 961 return -120; 962 } 963 964 return lna_gain - 2 * vga_idx; 965 } 966 967 static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw, 968 struct rtw_rx_pkt_stat *pkt_stat) 969 { 970 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 971 u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS; 972 u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS; 973 s8 rx_power; 974 975 if (rtwdev->dm_info.rx_cck_agc_report_type == 1) 976 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, 977 phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT) 978 | FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 979 else 980 lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 981 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 982 983 pkt_stat->rx_power[RF_PATH_A] = rx_power; 984 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 985 rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi; 986 pkt_stat->signal_power = rx_power; 987 } 988 989 static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw, 990 struct rtw_rx_pkt_stat *pkt_stat) 991 { 992 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 993 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 994 s8 val_s8; 995 996 val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F; 997 pkt_stat->rx_power[RF_PATH_A] = (val_s8 * 2) - 110; 998 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 999 pkt_stat->rx_snr[RF_PATH_A] = (s8)(phy_status->path_rxsnr[RF_PATH_A] / 2); 1000 1001 /* signal power reported by HW */ 1002 val_s8 = phy_status->cck_sig_qual_ofdm_pwdb_all >> 1; 1003 pkt_stat->signal_power = (val_s8 & 0x7f) - 110; 1004 1005 pkt_stat->rx_evm[RF_PATH_A] = phy_status->stream_rxevm[RF_PATH_A]; 1006 pkt_stat->cfo_tail[RF_PATH_A] = phy_status->path_cfotail[RF_PATH_A]; 1007 1008 dm_info->curr_rx_rate = pkt_stat->rate; 1009 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 1010 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 1011 /* convert to KHz (used only for debugfs) */ 1012 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 1013 1014 /* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0 1015 * range. rx_evm_dbm needs the absolute (positive) value. 1016 */ 1017 val_s8 = (s8)pkt_stat->rx_evm[RF_PATH_A]; 1018 val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64); 1019 val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 1020 dm_info->rx_evm_dbm[RF_PATH_A] = val_s8; 1021 } 1022 1023 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1024 struct rtw_rx_pkt_stat *pkt_stat) 1025 { 1026 if (pkt_stat->rate <= DESC_RATE11M) 1027 query_phy_status_cck(rtwdev, phy_status, pkt_stat); 1028 else 1029 query_phy_status_ofdm(rtwdev, phy_status, pkt_stat); 1030 } 1031 1032 #define ADDA_ON_VAL_8703B 0x03c00014 1033 1034 static 1035 void rtw8703b_iqk_config_mac(struct rtw_dev *rtwdev, 1036 const struct rtw8723x_iqk_backup_regs *backup) 1037 { 1038 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F); 1039 for (int i = 1; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 1040 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], 1041 backup->mac8[i] & (~BIT(3))); 1042 } 1043 1044 #define IQK_LTE_WRITE_VAL_8703B 0x00007700 1045 #define IQK_DELAY_TIME_8703B 4 1046 1047 static void rtw8703b_iqk_one_shot(struct rtw_dev *rtwdev, bool tx) 1048 { 1049 u32 regval; 1050 ktime_t t; 1051 s64 dur; 1052 int ret; 1053 1054 /* enter IQK mode */ 1055 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1056 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 1057 1058 /* One shot, LOK & IQK */ 1059 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000); 1060 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 1061 1062 t = ktime_get(); 1063 msleep(IQK_DELAY_TIME_8703B); 1064 ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000, 1065 100000, false, rtwdev, 1066 REG_IQK_RDY); 1067 dur = ktime_us_delta(ktime_get(), t); 1068 1069 if (ret) 1070 rtw_warn(rtwdev, "[IQK] %s timed out after %lldus!\n", 1071 tx ? "TX" : "RX", dur); 1072 else 1073 rtw_dbg(rtwdev, RTW_DBG_RFK, 1074 "[IQK] %s done after %lldus\n", 1075 tx ? "TX" : "RX", dur); 1076 } 1077 1078 static void rtw8703b_iqk_txrx_path_post(struct rtw_dev *rtwdev, 1079 const struct rtw8723x_iqk_backup_regs *backup) 1080 { 1081 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup); 1082 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 1083 1084 /* leave IQK mode */ 1085 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1086 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0); 1087 } 1088 1089 static u8 rtw8703b_iqk_check_tx_failed(struct rtw_dev *rtwdev) 1090 { 1091 s32 tx_x, tx_y; 1092 u32 tx_fail; 1093 1094 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 1095 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1096 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 1097 rtw_read32(rtwdev, REG_IQK_RES_TX), 1098 rtw_read32(rtwdev, REG_IQK_RES_TY)); 1099 rtw_dbg(rtwdev, RTW_DBG_RFK, 1100 "[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n", 1101 rtw_read32(rtwdev, REG_IQK_RDY), 1102 rtw_read32(rtwdev, 0xe98)); 1103 1104 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 1105 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1106 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1107 1108 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 1109 return IQK_TX_OK; 1110 1111 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A TX IQK failed\n"); 1112 1113 return 0; 1114 } 1115 1116 static u8 rtw8703b_iqk_check_rx_failed(struct rtw_dev *rtwdev) 1117 { 1118 s32 rx_x, rx_y; 1119 u32 rx_fail; 1120 1121 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 1122 rtw_read32(rtwdev, REG_IQK_RES_RX), 1123 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1124 1125 rtw_dbg(rtwdev, RTW_DBG_RFK, 1126 "[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n", 1127 rtw_read32(rtwdev, 0xea0), 1128 rtw_read32(rtwdev, 0xea8)); 1129 1130 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 1131 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1132 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1133 rx_y = abs(iqkxy_to_s32(rx_y)); 1134 1135 if (!rx_fail && rx_x != IQK_RX_X_ERR && rx_y != IQK_RX_Y_ERR && 1136 rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 1137 rx_y < IQK_RX_Y_LMT) 1138 return IQK_RX_OK; 1139 1140 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A RX IQK failed\n"); 1141 1142 return 0; 1143 } 1144 1145 static u8 rtw8703b_iqk_tx_path(struct rtw_dev *rtwdev, 1146 const struct rtw8723x_iqk_backup_regs *backup) 1147 { 1148 u8 status; 1149 1150 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK!\n"); 1151 1152 /* IQK setting */ 1153 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1154 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1155 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1156 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1157 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1158 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1159 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f); 1160 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1161 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1162 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1163 1164 /* LO calibration setting */ 1165 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 1166 1167 /* leave IQK mode */ 1168 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1169 1170 /* PA, PAD setting */ 1171 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1172 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7); 1173 rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400); 1174 1175 rtw8703b_iqk_one_shot(rtwdev, true); 1176 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1177 1178 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1179 1180 return status; 1181 } 1182 1183 static u8 rtw8703b_iqk_rx_path(struct rtw_dev *rtwdev, 1184 const struct rtw8723x_iqk_backup_regs *backup) 1185 { 1186 u8 status; 1187 u32 tx_x, tx_y; 1188 1189 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 1!\n"); 1190 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n", 1191 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1192 rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000); 1193 1194 /* disable IQC mode */ 1195 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1196 1197 /* IQK setting */ 1198 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1199 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1200 1201 /* path IQK setting */ 1202 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1203 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1204 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1205 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1206 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8216000f); 1207 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1208 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x28110000); 1209 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1210 1211 /* LOK setting */ 1212 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 1213 1214 /* RX IQK mode */ 1215 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1216 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1217 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1218 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7); 1219 1220 rtw8703b_iqk_one_shot(rtwdev, true); 1221 /* leave IQK mode */ 1222 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1223 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1224 1225 if (!status) 1226 goto restore; 1227 1228 /* second round */ 1229 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1230 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1231 1232 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 1233 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 1234 rtw_read32(rtwdev, REG_TXIQK_11N), 1235 BIT_SET_TXIQK_11N(tx_x, tx_y)); 1236 1237 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 2!\n"); 1238 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n", 1239 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1240 1241 /* IQK setting */ 1242 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1243 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 1244 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 1245 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1246 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1247 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000); 1248 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f); 1249 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1250 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1251 1252 /* LO calibration setting */ 1253 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 1254 1255 /* leave IQK mode */ 1256 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1257 /* modify RX IQK mode table */ 1258 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1259 /* RF_RCK_OS, RF_TXPA_G1, RF_TXPA_G2 */ 1260 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1261 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1262 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77); 1263 1264 /* PA, PAD setting */ 1265 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1266 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5); 1267 1268 rtw8703b_iqk_one_shot(rtwdev, false); 1269 status |= rtw8703b_iqk_check_rx_failed(rtwdev); 1270 1271 restore: 1272 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1273 1274 return status; 1275 } 1276 1277 static 1278 void rtw8703b_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 1279 const struct rtw8723x_iqk_backup_regs *backup) 1280 { 1281 u32 i; 1282 u8 a_ok; 1283 1284 rtw_dbg(rtwdev, RTW_DBG_RFK, 1285 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 1286 1287 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8703B); 1288 rtw8703b_iqk_config_mac(rtwdev, backup); 1289 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 1290 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600); 1291 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 1292 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000); 1293 1294 for (i = 0; i < PATH_IQK_RETRY; i++) { 1295 a_ok = rtw8703b_iqk_tx_path(rtwdev, backup); 1296 if (a_ok == IQK_TX_OK) { 1297 rtw_dbg(rtwdev, RTW_DBG_RFK, 1298 "[IQK] path A TX IQK success!\n"); 1299 result[t][IQK_S1_TX_X] = 1300 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, 1301 BIT_MASK_RES_TX); 1302 result[t][IQK_S1_TX_Y] = 1303 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, 1304 BIT_MASK_RES_TY); 1305 break; 1306 } 1307 1308 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK fail!\n"); 1309 result[t][IQK_S1_TX_X] = 0x100; 1310 result[t][IQK_S1_TX_Y] = 0x0; 1311 } 1312 1313 for (i = 0; i < PATH_IQK_RETRY; i++) { 1314 a_ok = rtw8703b_iqk_rx_path(rtwdev, backup); 1315 if (a_ok == (IQK_TX_OK | IQK_RX_OK)) { 1316 rtw_dbg(rtwdev, RTW_DBG_RFK, 1317 "[IQK] path A RX IQK success!\n"); 1318 result[t][IQK_S1_RX_X] = 1319 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, 1320 BIT_MASK_RES_RX); 1321 result[t][IQK_S1_RX_Y] = 1322 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, 1323 BIT_MASK_RES_RY); 1324 break; 1325 } 1326 1327 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK fail!\n"); 1328 result[t][IQK_S1_RX_X] = 0x100; 1329 result[t][IQK_S1_RX_Y] = 0x0; 1330 } 1331 1332 if (a_ok == 0x0) 1333 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A IQK fail!\n"); 1334 1335 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1336 mdelay(1); 1337 } 1338 1339 static 1340 void rtw8703b_iqk_fill_a_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1341 { 1342 u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16); 1343 s32 tx1_a, tx1_a_ext; 1344 s32 tx1_c, tx1_c_ext; 1345 s32 oldval_1; 1346 s32 x, y; 1347 1348 if (result[IQK_S1_TX_X] == 0) 1349 return; 1350 1351 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1352 BIT_MASK_TXIQ_ELM_D); 1353 1354 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 1355 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 1356 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1357 BIT_MASK_TXIQ_ELM_A, tx1_a); 1358 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1359 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 1360 1361 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 1362 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 1363 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1364 BIT_SET_TXIQ_ELM_C1(tx1_c)); 1365 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1366 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 1367 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1368 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 1369 1370 rtw_dbg(rtwdev, RTW_DBG_RFK, 1371 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 1372 x, tx1_a, oldval_1); 1373 rtw_dbg(rtwdev, RTW_DBG_RFK, 1374 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 1375 1376 if (result[IQK_S1_RX_X] == 0) 1377 return; 1378 1379 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_X, result[IQK_S1_RX_X]); 1380 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_Y1, result[IQK_S1_RX_X]); 1381 rtw_write32(rtwdev, REG_A_RXIQI, tmp_rx_iqi); 1382 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 1383 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 1384 } 1385 1386 static void rtw8703b_phy_calibration(struct rtw_dev *rtwdev) 1387 { 1388 /* For some reason path A is called S1 and B S0 in shared 1389 * rtw88 calibration data. 1390 */ 1391 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1392 struct rtw8723x_iqk_backup_regs backup; 1393 u8 final_candidate = IQK_ROUND_INVALID; 1394 s32 result[IQK_ROUND_SIZE][IQK_NR]; 1395 bool good; 1396 u8 i, j; 1397 1398 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!\n"); 1399 1400 memset(result, 0, sizeof(result)); 1401 1402 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup); 1403 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup); 1404 rtw8723x_iqk_backup_regs(rtwdev, &backup); 1405 1406 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 1407 rtw8723x_iqk_config_path_ctrl(rtwdev); 1408 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 1409 1410 rtw8703b_iqk_one_round(rtwdev, result, i, &backup); 1411 1412 rtw_dbg(rtwdev, RTW_DBG_RFK, 1413 "[IQK] back to BB mode, load original values!\n"); 1414 if (i > IQK_ROUND_0) 1415 rtw8723x_iqk_restore_regs(rtwdev, &backup); 1416 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup); 1417 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup); 1418 1419 for (j = IQK_ROUND_0; j < i; j++) { 1420 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i); 1421 1422 if (good) { 1423 final_candidate = j; 1424 rtw_dbg(rtwdev, RTW_DBG_RFK, 1425 "[IQK] cmp %d:%d final_candidate is %x\n", 1426 j, i, final_candidate); 1427 goto iqk_done; 1428 } 1429 } 1430 } 1431 1432 if (final_candidate == IQK_ROUND_INVALID) { 1433 s32 reg_tmp = 0; 1434 1435 for (i = 0; i < IQK_NR; i++) 1436 reg_tmp += result[IQK_ROUND_HYBRID][i]; 1437 1438 if (reg_tmp != 0) { 1439 final_candidate = IQK_ROUND_HYBRID; 1440 } else { 1441 WARN(1, "IQK failed\n"); 1442 goto out; 1443 } 1444 } 1445 1446 iqk_done: 1447 /* only path A is calibrated in rtl8703b */ 1448 rtw8703b_iqk_fill_a_matrix(rtwdev, result[final_candidate]); 1449 1450 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 1451 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 1452 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 1453 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 1454 dm_info->iqk.done = true; 1455 1456 out: 1457 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 1458 1459 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 1460 final_candidate); 1461 1462 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 1463 rtw_dbg(rtwdev, RTW_DBG_RFK, 1464 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 1465 i, 1466 result[i][0], result[i][1], result[i][2], result[i][3], 1467 result[i][4], result[i][5], result[i][6], result[i][7], 1468 final_candidate == i ? "(final candidate)" : ""); 1469 1470 rtw_dbg(rtwdev, RTW_DBG_RFK, 1471 "[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1472 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1473 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1474 rtw_read32(rtwdev, REG_A_RXIQI), 1475 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1476 rtw_dbg(rtwdev, RTW_DBG_RFK, 1477 "[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1478 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1479 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1480 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1481 1482 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Finished.\n"); 1483 } 1484 1485 static void rtw8703b_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1486 u32 ofdm_swing, u8 rf_path) 1487 { 1488 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1489 s32 ele_A, ele_D, ele_C; 1490 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1491 s32 iqk_result_x; 1492 s32 iqk_result_y; 1493 s32 value32; 1494 1495 switch (rf_path) { 1496 default: 1497 case RF_PATH_A: 1498 iqk_result_x = dm_info->iqk.result.s1_x; 1499 iqk_result_y = dm_info->iqk.result.s1_y; 1500 break; 1501 case RF_PATH_B: 1502 iqk_result_x = dm_info->iqk.result.s0_x; 1503 iqk_result_y = dm_info->iqk.result.s0_y; 1504 break; 1505 } 1506 1507 /* new element D */ 1508 ele_D = OFDM_SWING_D(ofdm_swing); 1509 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1510 /* new element A */ 1511 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1512 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1513 /* new element C */ 1514 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1515 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1516 1517 switch (rf_path) { 1518 case RF_PATH_A: 1519 default: 1520 /* write new elements A, C, D, and element B is always 0 */ 1521 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1522 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1523 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1524 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1525 value32); 1526 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1527 value32 &= ~BIT_MASK_OFDM0_EXTS; 1528 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1529 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1530 break; 1531 1532 case RF_PATH_B: 1533 /* write new elements A, C, D, and element B is always 0 */ 1534 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1535 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, value32); 1536 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1537 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1538 value32); 1539 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1540 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1541 value32 |= BIT_SET_OFDM0_EXTS_B(ele_A_ext, ele_C_ext, ele_D_ext); 1542 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1543 break; 1544 } 1545 } 1546 1547 static void rtw8703b_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1548 u8 rf_path) 1549 { 1550 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1551 s32 value32; 1552 u32 ofdm_swing; 1553 1554 ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1); 1555 1556 ofdm_swing = rtw8703b_ofdm_swing_table[ofdm_index]; 1557 1558 if (dm_info->iqk.done) { 1559 rtw8703b_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1560 return; 1561 } 1562 1563 switch (rf_path) { 1564 case RF_PATH_A: 1565 default: 1566 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1567 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1568 0x00); 1569 1570 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1571 value32 &= ~BIT_MASK_OFDM0_EXTS; 1572 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1573 break; 1574 1575 case RF_PATH_B: 1576 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, ofdm_swing); 1577 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1578 0x00); 1579 1580 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1581 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1582 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1583 break; 1584 } 1585 } 1586 1587 static void rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1588 s8 txagc_idx) 1589 { 1590 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1591 1592 dm_info->txagc_remnant_ofdm = txagc_idx; 1593 1594 /* Only path A is calibrated for rtl8703b */ 1595 rtw8703b_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1596 } 1597 1598 static void rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1599 s8 txagc_idx) 1600 { 1601 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1602 1603 dm_info->txagc_remnant_cck = txagc_idx; 1604 1605 swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1); 1606 1607 BUILD_BUG_ON(ARRAY_SIZE(rtw8703b_cck_pwr_regs) 1608 != ARRAY_SIZE(rtw8703b_cck_swing_table[0])); 1609 1610 for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++) 1611 rtw_write8(rtwdev, rtw8703b_cck_pwr_regs[i], 1612 rtw8703b_cck_swing_table[swing_idx][i]); 1613 } 1614 1615 static void rtw8703b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1616 { 1617 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1618 struct rtw_hal *hal = &rtwdev->hal; 1619 u8 limit_ofdm; 1620 u8 limit_cck = 21; 1621 s8 final_ofdm_swing_index; 1622 s8 final_cck_swing_index; 1623 1624 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev); 1625 1626 final_ofdm_swing_index = dm_info->default_ofdm_index + 1627 dm_info->delta_power_index[path]; 1628 final_cck_swing_index = dm_info->default_cck_index + 1629 dm_info->delta_power_index[path]; 1630 1631 if (final_ofdm_swing_index > limit_ofdm) 1632 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1633 final_ofdm_swing_index - limit_ofdm); 1634 else if (final_ofdm_swing_index < 0) 1635 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1636 final_ofdm_swing_index); 1637 else 1638 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1639 1640 if (final_cck_swing_index > limit_cck) 1641 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1642 final_cck_swing_index - limit_cck); 1643 else if (final_cck_swing_index < 0) 1644 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0, 1645 final_cck_swing_index); 1646 else 1647 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1648 1649 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1650 } 1651 1652 static void rtw8703b_phy_pwrtrack(struct rtw_dev *rtwdev) 1653 { 1654 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1655 struct rtw_swing_table swing_table; 1656 u8 thermal_value, delta, path; 1657 bool do_iqk = false; 1658 1659 rtw_phy_config_swing_table(rtwdev, &swing_table); 1660 1661 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1662 return; 1663 1664 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1665 1666 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1667 1668 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1669 1670 if (do_iqk) 1671 rtw8723x_lck(rtwdev); 1672 1673 if (dm_info->pwr_trk_init_trigger) 1674 dm_info->pwr_trk_init_trigger = false; 1675 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1676 RF_PATH_A)) 1677 goto iqk; 1678 1679 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1680 1681 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1682 1683 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1684 s8 delta_cur, delta_last; 1685 1686 delta_last = dm_info->delta_power_index[path]; 1687 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1688 path, RF_PATH_A, delta); 1689 if (delta_last == delta_cur) 1690 continue; 1691 1692 dm_info->delta_power_index[path] = delta_cur; 1693 rtw8703b_pwrtrack_set(rtwdev, path); 1694 } 1695 1696 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1697 1698 iqk: 1699 if (do_iqk) 1700 rtw8703b_phy_calibration(rtwdev); 1701 } 1702 1703 static void rtw8703b_pwr_track(struct rtw_dev *rtwdev) 1704 { 1705 struct rtw_efuse *efuse = &rtwdev->efuse; 1706 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1707 1708 if (efuse->power_track_type != 0) { 1709 rtw_warn(rtwdev, "unsupported power track type"); 1710 return; 1711 } 1712 1713 if (!dm_info->pwr_trk_triggered) { 1714 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1715 GENMASK(17, 16), 0x03); 1716 dm_info->pwr_trk_triggered = true; 1717 return; 1718 } 1719 1720 rtw8703b_phy_pwrtrack(rtwdev); 1721 dm_info->pwr_trk_triggered = false; 1722 } 1723 1724 static void rtw8703b_coex_set_gnt_fix(struct rtw_dev *rtwdev) 1725 { 1726 } 1727 1728 static void rtw8703b_coex_set_gnt_debug(struct rtw_dev *rtwdev) 1729 { 1730 } 1731 1732 static void rtw8703b_coex_set_rfe_type(struct rtw_dev *rtwdev) 1733 { 1734 struct rtw_coex *coex = &rtwdev->coex; 1735 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1736 1737 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1738 coex_rfe->ant_switch_polarity = 0; 1739 coex_rfe->ant_switch_exist = false; 1740 coex_rfe->ant_switch_with_bt = false; 1741 coex_rfe->ant_switch_diversity = false; 1742 coex_rfe->wlg_at_btg = true; 1743 1744 /* disable LTE coex on wifi side */ 1745 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1746 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1747 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1748 } 1749 1750 static void rtw8703b_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1751 { 1752 } 1753 1754 static void rtw8703b_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1755 { 1756 } 1757 1758 static const u8 rtw8703b_pwrtrk_2gb_n[] = { 1759 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1760 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1761 }; 1762 1763 static const u8 rtw8703b_pwrtrk_2gb_p[] = { 1764 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1765 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1766 }; 1767 1768 static const u8 rtw8703b_pwrtrk_2ga_n[] = { 1769 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1770 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1771 }; 1772 1773 static const u8 rtw8703b_pwrtrk_2ga_p[] = { 1774 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1775 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1776 }; 1777 1778 static const u8 rtw8703b_pwrtrk_2g_cck_b_n[] = { 1779 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1780 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1781 }; 1782 1783 static const u8 rtw8703b_pwrtrk_2g_cck_b_p[] = { 1784 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1785 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1786 }; 1787 1788 static const u8 rtw8703b_pwrtrk_2g_cck_a_n[] = { 1789 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1790 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1791 }; 1792 1793 static const u8 rtw8703b_pwrtrk_2g_cck_a_p[] = { 1794 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1795 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1796 }; 1797 1798 static const s8 rtw8703b_pwrtrk_xtal_n[] = { 1799 0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3, 1800 -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1 1801 }; 1802 1803 static const s8 rtw8703b_pwrtrk_xtal_p[] = { 1804 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1, 1805 -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30 1806 }; 1807 1808 static const struct rtw_pwr_track_tbl rtw8703b_rtw_pwr_track_tbl = { 1809 .pwrtrk_2gb_n = rtw8703b_pwrtrk_2gb_n, 1810 .pwrtrk_2gb_p = rtw8703b_pwrtrk_2gb_p, 1811 .pwrtrk_2ga_n = rtw8703b_pwrtrk_2ga_n, 1812 .pwrtrk_2ga_p = rtw8703b_pwrtrk_2ga_p, 1813 .pwrtrk_2g_cckb_n = rtw8703b_pwrtrk_2g_cck_b_n, 1814 .pwrtrk_2g_cckb_p = rtw8703b_pwrtrk_2g_cck_b_p, 1815 .pwrtrk_2g_ccka_n = rtw8703b_pwrtrk_2g_cck_a_n, 1816 .pwrtrk_2g_ccka_p = rtw8703b_pwrtrk_2g_cck_a_p, 1817 .pwrtrk_xtal_n = rtw8703b_pwrtrk_xtal_n, 1818 .pwrtrk_xtal_p = rtw8703b_pwrtrk_xtal_p, 1819 }; 1820 1821 /* Shared-Antenna Coex Table */ 1822 static const struct coex_table_para table_sant_8703b[] = { 1823 {0xffffffff, 0xffffffff}, /* case-0 */ 1824 {0x55555555, 0x55555555}, 1825 {0x66555555, 0x66555555}, 1826 {0xaaaaaaaa, 0xaaaaaaaa}, 1827 {0x5a5a5a5a, 0x5a5a5a5a}, 1828 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1829 {0x6a5a5555, 0xaaaaaaaa}, 1830 {0x6a5a56aa, 0x6a5a56aa}, 1831 {0x6a5a5a5a, 0x6a5a5a5a}, 1832 {0x66555555, 0x5a5a5a5a}, 1833 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1834 {0x66555555, 0x6a5a5aaa}, 1835 {0x66555555, 0x5a5a5aaa}, 1836 {0x66555555, 0x6aaa5aaa}, 1837 {0x66555555, 0xaaaa5aaa}, 1838 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1839 {0xffff55ff, 0xfafafafa}, 1840 {0xffff55ff, 0x6afa5afa}, 1841 {0xaaffffaa, 0xfafafafa}, 1842 {0xaa5555aa, 0x5a5a5a5a}, 1843 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1844 {0xaa5555aa, 0xaaaaaaaa}, 1845 {0xffffffff, 0x5a5a5a5a}, 1846 {0xffffffff, 0x5a5a5a5a}, 1847 {0xffffffff, 0x55555555}, 1848 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1849 {0x55555555, 0x5a5a5a5a}, 1850 {0x55555555, 0xaaaaaaaa}, 1851 {0x55555555, 0x6a5a6a5a}, 1852 {0x66556655, 0x66556655}, 1853 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1854 {0xffffffff, 0x5aaa5aaa}, 1855 {0x56555555, 0x5a5a5aaa}, 1856 }; 1857 1858 /* Shared-Antenna TDMA */ 1859 static const struct coex_tdma_para tdma_sant_8703b[] = { 1860 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1861 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1862 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1863 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1864 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1865 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 1866 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1867 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1868 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1869 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1870 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1871 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1872 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1873 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1874 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1875 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1876 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1877 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1878 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1879 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1880 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1881 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1882 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 1883 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1884 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1885 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1886 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 1887 { {0x61, 0x08, 0x03, 0x11, 0x11} }, 1888 }; 1889 1890 static const struct rtw_chip_ops rtw8703b_ops = { 1891 .mac_init = rtw8723x_mac_init, 1892 .dump_fw_crash = NULL, 1893 .shutdown = NULL, 1894 .read_efuse = rtw8703b_read_efuse, 1895 .phy_set_param = rtw8703b_phy_set_param, 1896 .set_channel = rtw8703b_set_channel, 1897 .query_phy_status = query_phy_status, 1898 .read_rf = rtw_phy_read_rf_sipi, 1899 .write_rf = rtw_phy_write_rf_reg_sipi, 1900 .set_tx_power_index = rtw8723x_set_tx_power_index, 1901 .set_antenna = NULL, 1902 .cfg_ldo25 = rtw8723x_cfg_ldo25, 1903 .efuse_grant = rtw8723x_efuse_grant, 1904 .false_alarm_statistics = rtw8723x_false_alarm_statistics, 1905 .phy_calibration = rtw8703b_phy_calibration, 1906 .dpk_track = NULL, 1907 /* 8723d uses REG_CSRATIO to set dm_info.cck_pd_default, which 1908 * is used in its cck_pd_set function. According to comments 1909 * in the vendor driver code it doesn't exist in this chip 1910 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only 1911 * *written* to). 1912 */ 1913 .cck_pd_set = NULL, 1914 .pwr_track = rtw8703b_pwr_track, 1915 .config_bfee = NULL, 1916 .set_gid_table = NULL, 1917 .cfg_csi_rate = NULL, 1918 .adaptivity_init = NULL, 1919 .adaptivity = NULL, 1920 .cfo_init = NULL, 1921 .cfo_track = NULL, 1922 .config_tx_path = NULL, 1923 .config_txrx_mode = NULL, 1924 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum, 1925 1926 /* for coex */ 1927 .coex_set_init = rtw8723x_coex_cfg_init, 1928 .coex_set_ant_switch = NULL, 1929 .coex_set_gnt_fix = rtw8703b_coex_set_gnt_fix, 1930 .coex_set_gnt_debug = rtw8703b_coex_set_gnt_debug, 1931 .coex_set_rfe_type = rtw8703b_coex_set_rfe_type, 1932 .coex_set_wl_tx_power = rtw8703b_coex_set_wl_tx_power, 1933 .coex_set_wl_rx_gain = rtw8703b_coex_set_wl_rx_gain, 1934 }; 1935 1936 const struct rtw_chip_info rtw8703b_hw_spec = { 1937 .ops = &rtw8703b_ops, 1938 .id = RTW_CHIP_TYPE_8703B, 1939 1940 .fw_name = "rtw88/rtw8703b_fw.bin", 1941 .wlan_cpu = RTW_WCPU_11N, 1942 .tx_pkt_desc_sz = 40, 1943 .tx_buf_desc_sz = 16, 1944 .rx_pkt_desc_sz = 24, 1945 .rx_buf_desc_sz = 8, 1946 .phy_efuse_size = 256, 1947 .log_efuse_size = 512, 1948 .ptct_efuse_size = 15, 1949 .txff_size = 32768, 1950 .rxff_size = 16384, 1951 .rsvd_drv_pg_num = 8, 1952 .band = RTW_BAND_2G, 1953 .page_size = TX_PAGE_SIZE, 1954 .csi_buf_pg_num = 0, 1955 .dig_min = 0x20, 1956 .txgi_factor = 1, 1957 .is_pwr_by_rate_dec = true, 1958 .rx_ldpc = false, 1959 .tx_stbc = false, 1960 .max_power_index = 0x3f, 1961 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1962 .usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */ 1963 1964 .path_div_supported = false, 1965 .ht_supported = true, 1966 .vht_supported = false, 1967 .lps_deep_mode_supported = 0, 1968 1969 .sys_func_en = 0xFD, 1970 .pwr_on_seq = card_enable_flow_8703b, 1971 .pwr_off_seq = card_disable_flow_8703b, 1972 .rqpn_table = rqpn_table_8703b, 1973 .prioq_addrs = &rtw8723x_common.prioq_addrs, 1974 .page_table = page_table_8703b, 1975 /* used only in pci.c, not needed for SDIO devices */ 1976 .intf_table = NULL, 1977 1978 .dig = rtw8723x_common.dig, 1979 .dig_cck = rtw8723x_common.dig_cck, 1980 1981 .rf_sipi_addr = {0x840, 0x844}, 1982 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr, 1983 .fix_rf_phy_num = 2, 1984 .ltecoex_addr = &rtw8723x_common.ltecoex_addr, 1985 1986 .mac_tbl = &rtw8703b_mac_tbl, 1987 .agc_tbl = &rtw8703b_agc_tbl, 1988 .bb_tbl = &rtw8703b_bb_tbl, 1989 .rf_tbl = {&rtw8703b_rf_a_tbl}, 1990 1991 .rfe_defs = rtw8703b_rfe_defs, 1992 .rfe_defs_size = ARRAY_SIZE(rtw8703b_rfe_defs), 1993 1994 .iqk_threshold = 8, 1995 .pwr_track_tbl = &rtw8703b_rtw_pwr_track_tbl, 1996 1997 /* WOWLAN firmware exists, but not implemented yet */ 1998 .wow_fw_name = "rtw88/rtw8703b_wow_fw.bin", 1999 .wowlan_stub = NULL, 2000 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2001 2002 /* Vendor driver has a time-based format, converted from 2003 * 20180330 2004 */ 2005 .coex_para_ver = 0x0133ed6a, 2006 .bt_desired_ver = 0x1c, 2007 .scbd_support = true, 2008 .new_scbd10_def = true, 2009 .ble_hid_profile_support = false, 2010 .wl_mimo_ps_support = false, 2011 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2012 .bt_rssi_type = COEX_BTRSSI_RATIO, 2013 .ant_isolation = 15, 2014 .rssi_tolerance = 2, 2015 .bt_rssi_step = bt_rssi_step_8703b, 2016 .wl_rssi_step = wl_rssi_step_8703b, 2017 /* sant -> shared antenna, nsant -> non-shared antenna 2018 * Not sure if 8703b versions with non-shard antenna even exist. 2019 */ 2020 .table_sant_num = ARRAY_SIZE(table_sant_8703b), 2021 .table_sant = table_sant_8703b, 2022 .table_nsant_num = 0, 2023 .table_nsant = NULL, 2024 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8703b), 2025 .tdma_sant = tdma_sant_8703b, 2026 .tdma_nsant_num = 0, 2027 .tdma_nsant = NULL, 2028 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8703b), 2029 .wl_rf_para_tx = rf_para_tx_8703b, 2030 .wl_rf_para_rx = rf_para_rx_8703b, 2031 .bt_afh_span_bw20 = 0x20, 2032 .bt_afh_span_bw40 = 0x30, 2033 .afh_5g_num = ARRAY_SIZE(afh_5g_8703b), 2034 .afh_5g = afh_5g_8703b, 2035 /* REG_BTG_SEL doesn't seem to have a counterpart in the 2036 * vendor driver. Mathematically it's REG_PAD_CTRL1 + 3. 2037 * 2038 * It is used in the cardemu_to_act power sequence by though 2039 * (by address, 0x0067), comment: "0x67[0] = 0 to disable 2040 * BT_GPS_SEL pins" That seems to fit. 2041 */ 2042 .btg_reg = NULL, 2043 /* These registers are used to read (and print) from if 2044 * CONFIG_RTW88_DEBUGFS is enabled. 2045 */ 2046 .coex_info_hw_regs_num = 0, 2047 .coex_info_hw_regs = NULL, 2048 }; 2049 EXPORT_SYMBOL(rtw8703b_hw_spec); 2050 2051 MODULE_FIRMWARE("rtw88/rtw8703b_fw.bin"); 2052 MODULE_FIRMWARE("rtw88/rtw8703b_wow_fw.bin"); 2053 2054 MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>"); 2055 MODULE_DESCRIPTION("Realtek 802.11n wireless 8703b driver"); 2056 MODULE_LICENSE("Dual BSD/GPL"); 2057