1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_PCI_H_ 6 #define __RTK_PCI_H_ 7 8 #define RTK_PCI_DEVICE(vend, dev, hw_config) \ 9 PCI_DEVICE(vend, dev), \ 10 .driver_data = (kernel_ulong_t)&(hw_config), 11 12 #define RTK_DEFAULT_TX_DESC_NUM 128 13 #define RTK_BEQ_TX_DESC_NUM 256 14 15 #define RTK_MAX_RX_DESC_NUM 512 16 /* 8K + rx desc size */ 17 #define RTK_PCI_RX_BUF_SIZE (8192 + 24) 18 19 #define RTK_PCI_CTRL 0x300 20 #define BIT_RST_TRXDMA_INTF BIT(20) 21 #define BIT_RX_TAG_EN BIT(15) 22 #define REG_DBI_WDATA_V1 0x03E8 23 #define REG_DBI_FLAG_V1 0x03F0 24 #define REG_MDIO_V1 0x03F4 25 #define REG_PCIE_MIX_CFG 0x03F8 26 #define BIT_MDIO_WFLAG_V1 BIT(5) 27 28 #define BIT_PCI_BCNQ_FLAG BIT(4) 29 #define RTK_PCI_TXBD_DESA_BCNQ 0x308 30 #define RTK_PCI_TXBD_DESA_H2CQ 0x1320 31 #define RTK_PCI_TXBD_DESA_MGMTQ 0x310 32 #define RTK_PCI_TXBD_DESA_BKQ 0x330 33 #define RTK_PCI_TXBD_DESA_BEQ 0x328 34 #define RTK_PCI_TXBD_DESA_VIQ 0x320 35 #define RTK_PCI_TXBD_DESA_VOQ 0x318 36 #define RTK_PCI_TXBD_DESA_HI0Q 0x340 37 #define RTK_PCI_RXBD_DESA_MPDUQ 0x338 38 39 /* BCNQ is specialized for rsvd page, does not need to specify a number */ 40 #define RTK_PCI_TXBD_NUM_H2CQ 0x1328 41 #define RTK_PCI_TXBD_NUM_MGMTQ 0x380 42 #define RTK_PCI_TXBD_NUM_BKQ 0x38A 43 #define RTK_PCI_TXBD_NUM_BEQ 0x388 44 #define RTK_PCI_TXBD_NUM_VIQ 0x386 45 #define RTK_PCI_TXBD_NUM_VOQ 0x384 46 #define RTK_PCI_TXBD_NUM_HI0Q 0x38C 47 #define RTK_PCI_RXBD_NUM_MPDUQ 0x382 48 #define RTK_PCI_TXBD_IDX_H2CQ 0x132C 49 #define RTK_PCI_TXBD_IDX_MGMTQ 0x3B0 50 #define RTK_PCI_TXBD_IDX_BKQ 0x3AC 51 #define RTK_PCI_TXBD_IDX_BEQ 0x3A8 52 #define RTK_PCI_TXBD_IDX_VIQ 0x3A4 53 #define RTK_PCI_TXBD_IDX_VOQ 0x3A0 54 #define RTK_PCI_TXBD_IDX_HI0Q 0x3B8 55 #define RTK_PCI_RXBD_IDX_MPDUQ 0x3B4 56 57 #define RTK_PCI_TXBD_RWPTR_CLR 0x39C 58 #define RTK_PCI_TXBD_H2CQ_CSR 0x1330 59 60 #define BIT_CLR_H2CQ_HOST_IDX BIT(16) 61 #define BIT_CLR_H2CQ_HW_IDX BIT(8) 62 63 #define RTK_PCI_HIMR0 0x0B0 64 #define RTK_PCI_HISR0 0x0B4 65 #define RTK_PCI_HIMR1 0x0B8 66 #define RTK_PCI_HISR1 0x0BC 67 #define RTK_PCI_HIMR2 0x10B0 68 #define RTK_PCI_HISR2 0x10B4 69 #define RTK_PCI_HIMR3 0x10B8 70 #define RTK_PCI_HISR3 0x10BC 71 /* IMR 0 */ 72 #define IMR_TIMER2 BIT(31) 73 #define IMR_TIMER1 BIT(30) 74 #define IMR_PSTIMEOUT BIT(29) 75 #define IMR_GTINT4 BIT(28) 76 #define IMR_GTINT3 BIT(27) 77 #define IMR_TBDER BIT(26) 78 #define IMR_TBDOK BIT(25) 79 #define IMR_TSF_BIT32_TOGGLE BIT(24) 80 #define IMR_BCNDMAINT0 BIT(20) 81 #define IMR_BCNDOK0 BIT(16) 82 #define IMR_HSISR_IND_ON_INT BIT(15) 83 #define IMR_BCNDMAINT_E BIT(14) 84 #define IMR_ATIMEND BIT(12) 85 #define IMR_HISR1_IND_INT BIT(11) 86 #define IMR_C2HCMD BIT(10) 87 #define IMR_CPWM2 BIT(9) 88 #define IMR_CPWM BIT(8) 89 #define IMR_HIGHDOK BIT(7) 90 #define IMR_MGNTDOK BIT(6) 91 #define IMR_BKDOK BIT(5) 92 #define IMR_BEDOK BIT(4) 93 #define IMR_VIDOK BIT(3) 94 #define IMR_VODOK BIT(2) 95 #define IMR_RDU BIT(1) 96 #define IMR_ROK BIT(0) 97 /* IMR 1 */ 98 #define IMR_TXFIFO_TH_INT BIT(30) 99 #define IMR_BTON_STS_UPDATE BIT(29) 100 #define IMR_MCUERR BIT(28) 101 #define IMR_BCNDMAINT7 BIT(27) 102 #define IMR_BCNDMAINT6 BIT(26) 103 #define IMR_BCNDMAINT5 BIT(25) 104 #define IMR_BCNDMAINT4 BIT(24) 105 #define IMR_BCNDMAINT3 BIT(23) 106 #define IMR_BCNDMAINT2 BIT(22) 107 #define IMR_BCNDMAINT1 BIT(21) 108 #define IMR_BCNDOK7 BIT(20) 109 #define IMR_BCNDOK6 BIT(19) 110 #define IMR_BCNDOK5 BIT(18) 111 #define IMR_BCNDOK4 BIT(17) 112 #define IMR_BCNDOK3 BIT(16) 113 #define IMR_BCNDOK2 BIT(15) 114 #define IMR_BCNDOK1 BIT(14) 115 #define IMR_ATIMEND_E BIT(13) 116 #define IMR_ATIMEND BIT(12) 117 #define IMR_TXERR BIT(11) 118 #define IMR_RXERR BIT(10) 119 #define IMR_TXFOVW BIT(9) 120 #define IMR_RXFOVW BIT(8) 121 #define IMR_CPU_MGQ_TXDONE BIT(5) 122 #define IMR_PS_TIMER_C BIT(4) 123 #define IMR_PS_TIMER_B BIT(3) 124 #define IMR_PS_TIMER_A BIT(2) 125 #define IMR_CPUMGQ_TX_TIMER BIT(1) 126 /* IMR 3 */ 127 #define IMR_H2CDOK BIT(16) 128 129 /* one element is reserved to know if the ring is closed */ 130 static inline int avail_desc(u32 wp, u32 rp, u32 len) 131 { 132 if (rp > wp) 133 return rp - wp - 1; 134 else 135 return len - wp + rp - 1; 136 } 137 138 #define RTK_PCI_TXBD_OWN_OFFSET 15 139 #define RTK_PCI_TXBD_BCN_WORK 0x383 140 141 struct rtw_pci_tx_buffer_desc { 142 __le16 buf_size; 143 __le16 psb_len; 144 __le32 dma; 145 }; 146 147 struct rtw_pci_tx_data { 148 dma_addr_t dma; 149 u8 sn; 150 }; 151 152 struct rtw_pci_ring { 153 u8 *head; 154 dma_addr_t dma; 155 156 u8 desc_size; 157 158 u32 len; 159 u32 wp; 160 u32 rp; 161 }; 162 163 struct rtw_pci_tx_ring { 164 struct rtw_pci_ring r; 165 struct sk_buff_head queue; 166 bool queue_stopped; 167 }; 168 169 struct rtw_pci_rx_buffer_desc { 170 __le16 buf_size; 171 __le16 total_pkt_size; 172 __le32 dma; 173 }; 174 175 struct rtw_pci_rx_ring { 176 struct rtw_pci_ring r; 177 struct sk_buff *buf[RTK_MAX_RX_DESC_NUM]; 178 }; 179 180 #define RX_TAG_MAX 8192 181 182 struct rtw_pci { 183 struct pci_dev *pdev; 184 185 /* used for pci interrupt */ 186 spinlock_t irq_lock; 187 u32 irq_mask[4]; 188 bool irq_enabled; 189 190 u16 rx_tag; 191 struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM]; 192 struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM]; 193 194 void __iomem *mmap; 195 }; 196 197 static u32 max_num_of_tx_queue(u8 queue) 198 { 199 u32 max_num; 200 201 switch (queue) { 202 case RTW_TX_QUEUE_BE: 203 max_num = RTK_BEQ_TX_DESC_NUM; 204 break; 205 case RTW_TX_QUEUE_BCN: 206 max_num = 1; 207 break; 208 default: 209 max_num = RTK_DEFAULT_TX_DESC_NUM; 210 break; 211 } 212 213 return max_num; 214 } 215 216 static inline struct 217 rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb) 218 { 219 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 220 221 BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) > 222 sizeof(info->status.status_driver_data)); 223 224 return (struct rtw_pci_tx_data *)info->status.status_driver_data; 225 } 226 227 static inline 228 struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring, 229 u32 size) 230 { 231 u8 *buf_desc; 232 233 buf_desc = ring->r.head + ring->r.wp * size; 234 return (struct rtw_pci_tx_buffer_desc *)buf_desc; 235 } 236 237 #endif 238