1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include "main.h" 8 #include "pci.h" 9 #include "reg.h" 10 #include "tx.h" 11 #include "rx.h" 12 #include "fw.h" 13 #include "ps.h" 14 #include "debug.h" 15 16 static bool rtw_disable_msi; 17 static bool rtw_pci_disable_aspm; 18 module_param_named(disable_msi, rtw_disable_msi, bool, 0644); 19 module_param_named(disable_aspm, rtw_pci_disable_aspm, bool, 0644); 20 MODULE_PARM_DESC(disable_msi, "Set Y to disable MSI interrupt support"); 21 MODULE_PARM_DESC(disable_aspm, "Set Y to disable PCI ASPM support"); 22 23 static u32 rtw_pci_tx_queue_idx_addr[] = { 24 [RTW_TX_QUEUE_BK] = RTK_PCI_TXBD_IDX_BKQ, 25 [RTW_TX_QUEUE_BE] = RTK_PCI_TXBD_IDX_BEQ, 26 [RTW_TX_QUEUE_VI] = RTK_PCI_TXBD_IDX_VIQ, 27 [RTW_TX_QUEUE_VO] = RTK_PCI_TXBD_IDX_VOQ, 28 [RTW_TX_QUEUE_MGMT] = RTK_PCI_TXBD_IDX_MGMTQ, 29 [RTW_TX_QUEUE_HI0] = RTK_PCI_TXBD_IDX_HI0Q, 30 [RTW_TX_QUEUE_H2C] = RTK_PCI_TXBD_IDX_H2CQ, 31 }; 32 33 static u8 rtw_pci_get_tx_qsel(struct sk_buff *skb, 34 enum rtw_tx_queue_type queue) 35 { 36 switch (queue) { 37 case RTW_TX_QUEUE_BCN: 38 return TX_DESC_QSEL_BEACON; 39 case RTW_TX_QUEUE_H2C: 40 return TX_DESC_QSEL_H2C; 41 case RTW_TX_QUEUE_MGMT: 42 return TX_DESC_QSEL_MGMT; 43 case RTW_TX_QUEUE_HI0: 44 return TX_DESC_QSEL_HIGH; 45 default: 46 return skb->priority; 47 } 48 }; 49 50 static u8 rtw_pci_read8(struct rtw_dev *rtwdev, u32 addr) 51 { 52 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 53 54 return readb(rtwpci->mmap + addr); 55 } 56 57 static u16 rtw_pci_read16(struct rtw_dev *rtwdev, u32 addr) 58 { 59 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 60 61 return readw(rtwpci->mmap + addr); 62 } 63 64 static u32 rtw_pci_read32(struct rtw_dev *rtwdev, u32 addr) 65 { 66 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 67 68 return readl(rtwpci->mmap + addr); 69 } 70 71 static void rtw_pci_write8(struct rtw_dev *rtwdev, u32 addr, u8 val) 72 { 73 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 74 75 writeb(val, rtwpci->mmap + addr); 76 } 77 78 static void rtw_pci_write16(struct rtw_dev *rtwdev, u32 addr, u16 val) 79 { 80 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 81 82 writew(val, rtwpci->mmap + addr); 83 } 84 85 static void rtw_pci_write32(struct rtw_dev *rtwdev, u32 addr, u32 val) 86 { 87 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 88 89 writel(val, rtwpci->mmap + addr); 90 } 91 92 static void rtw_pci_free_tx_ring_skbs(struct rtw_dev *rtwdev, 93 struct rtw_pci_tx_ring *tx_ring) 94 { 95 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 96 struct rtw_pci_tx_data *tx_data; 97 struct sk_buff *skb, *tmp; 98 dma_addr_t dma; 99 100 /* free every skb remained in tx list */ 101 skb_queue_walk_safe(&tx_ring->queue, skb, tmp) { 102 __skb_unlink(skb, &tx_ring->queue); 103 tx_data = rtw_pci_get_tx_data(skb); 104 dma = tx_data->dma; 105 106 dma_unmap_single(&pdev->dev, dma, skb->len, DMA_TO_DEVICE); 107 dev_kfree_skb_any(skb); 108 } 109 } 110 111 static void rtw_pci_free_tx_ring(struct rtw_dev *rtwdev, 112 struct rtw_pci_tx_ring *tx_ring) 113 { 114 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 115 u8 *head = tx_ring->r.head; 116 u32 len = tx_ring->r.len; 117 int ring_sz = len * tx_ring->r.desc_size; 118 119 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 120 121 /* free the ring itself */ 122 dma_free_coherent(&pdev->dev, ring_sz, head, tx_ring->r.dma); 123 tx_ring->r.head = NULL; 124 } 125 126 static void rtw_pci_free_rx_ring_skbs(struct rtw_dev *rtwdev, 127 struct rtw_pci_rx_ring *rx_ring) 128 { 129 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 130 struct sk_buff *skb; 131 int buf_sz = RTK_PCI_RX_BUF_SIZE; 132 dma_addr_t dma; 133 int i; 134 135 for (i = 0; i < rx_ring->r.len; i++) { 136 skb = rx_ring->buf[i]; 137 if (!skb) 138 continue; 139 140 dma = *((dma_addr_t *)skb->cb); 141 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 142 dev_kfree_skb(skb); 143 rx_ring->buf[i] = NULL; 144 } 145 } 146 147 static void rtw_pci_free_rx_ring(struct rtw_dev *rtwdev, 148 struct rtw_pci_rx_ring *rx_ring) 149 { 150 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 151 u8 *head = rx_ring->r.head; 152 int ring_sz = rx_ring->r.desc_size * rx_ring->r.len; 153 154 rtw_pci_free_rx_ring_skbs(rtwdev, rx_ring); 155 156 dma_free_coherent(&pdev->dev, ring_sz, head, rx_ring->r.dma); 157 } 158 159 static void rtw_pci_free_trx_ring(struct rtw_dev *rtwdev) 160 { 161 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 162 struct rtw_pci_tx_ring *tx_ring; 163 struct rtw_pci_rx_ring *rx_ring; 164 int i; 165 166 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 167 tx_ring = &rtwpci->tx_rings[i]; 168 rtw_pci_free_tx_ring(rtwdev, tx_ring); 169 } 170 171 for (i = 0; i < RTK_MAX_RX_QUEUE_NUM; i++) { 172 rx_ring = &rtwpci->rx_rings[i]; 173 rtw_pci_free_rx_ring(rtwdev, rx_ring); 174 } 175 } 176 177 static int rtw_pci_init_tx_ring(struct rtw_dev *rtwdev, 178 struct rtw_pci_tx_ring *tx_ring, 179 u8 desc_size, u32 len) 180 { 181 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 182 int ring_sz = desc_size * len; 183 dma_addr_t dma; 184 u8 *head; 185 186 if (len > TRX_BD_IDX_MASK) { 187 rtw_err(rtwdev, "len %d exceeds maximum TX entries\n", len); 188 return -EINVAL; 189 } 190 191 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 192 if (!head) { 193 rtw_err(rtwdev, "failed to allocate tx ring\n"); 194 return -ENOMEM; 195 } 196 197 skb_queue_head_init(&tx_ring->queue); 198 tx_ring->r.head = head; 199 tx_ring->r.dma = dma; 200 tx_ring->r.len = len; 201 tx_ring->r.desc_size = desc_size; 202 tx_ring->r.wp = 0; 203 tx_ring->r.rp = 0; 204 205 return 0; 206 } 207 208 static int rtw_pci_reset_rx_desc(struct rtw_dev *rtwdev, struct sk_buff *skb, 209 struct rtw_pci_rx_ring *rx_ring, 210 u32 idx, u32 desc_sz) 211 { 212 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 213 struct rtw_pci_rx_buffer_desc *buf_desc; 214 int buf_sz = RTK_PCI_RX_BUF_SIZE; 215 dma_addr_t dma; 216 217 if (!skb) 218 return -EINVAL; 219 220 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); 221 if (dma_mapping_error(&pdev->dev, dma)) 222 return -EBUSY; 223 224 *((dma_addr_t *)skb->cb) = dma; 225 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 226 idx * desc_sz); 227 memset(buf_desc, 0, sizeof(*buf_desc)); 228 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 229 buf_desc->dma = cpu_to_le32(dma); 230 231 return 0; 232 } 233 234 static void rtw_pci_sync_rx_desc_device(struct rtw_dev *rtwdev, dma_addr_t dma, 235 struct rtw_pci_rx_ring *rx_ring, 236 u32 idx, u32 desc_sz) 237 { 238 struct device *dev = rtwdev->dev; 239 struct rtw_pci_rx_buffer_desc *buf_desc; 240 int buf_sz = RTK_PCI_RX_BUF_SIZE; 241 242 dma_sync_single_for_device(dev, dma, buf_sz, DMA_FROM_DEVICE); 243 244 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 245 idx * desc_sz); 246 memset(buf_desc, 0, sizeof(*buf_desc)); 247 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 248 buf_desc->dma = cpu_to_le32(dma); 249 } 250 251 static int rtw_pci_init_rx_ring(struct rtw_dev *rtwdev, 252 struct rtw_pci_rx_ring *rx_ring, 253 u8 desc_size, u32 len) 254 { 255 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 256 struct sk_buff *skb = NULL; 257 dma_addr_t dma; 258 u8 *head; 259 int ring_sz = desc_size * len; 260 int buf_sz = RTK_PCI_RX_BUF_SIZE; 261 int i, allocated; 262 int ret = 0; 263 264 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 265 if (!head) { 266 rtw_err(rtwdev, "failed to allocate rx ring\n"); 267 return -ENOMEM; 268 } 269 rx_ring->r.head = head; 270 271 for (i = 0; i < len; i++) { 272 skb = dev_alloc_skb(buf_sz); 273 if (!skb) { 274 allocated = i; 275 ret = -ENOMEM; 276 goto err_out; 277 } 278 279 memset(skb->data, 0, buf_sz); 280 rx_ring->buf[i] = skb; 281 ret = rtw_pci_reset_rx_desc(rtwdev, skb, rx_ring, i, desc_size); 282 if (ret) { 283 allocated = i; 284 dev_kfree_skb_any(skb); 285 goto err_out; 286 } 287 } 288 289 rx_ring->r.dma = dma; 290 rx_ring->r.len = len; 291 rx_ring->r.desc_size = desc_size; 292 rx_ring->r.wp = 0; 293 rx_ring->r.rp = 0; 294 295 return 0; 296 297 err_out: 298 for (i = 0; i < allocated; i++) { 299 skb = rx_ring->buf[i]; 300 if (!skb) 301 continue; 302 dma = *((dma_addr_t *)skb->cb); 303 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 304 dev_kfree_skb_any(skb); 305 rx_ring->buf[i] = NULL; 306 } 307 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 308 309 rtw_err(rtwdev, "failed to init rx buffer\n"); 310 311 return ret; 312 } 313 314 static int rtw_pci_init_trx_ring(struct rtw_dev *rtwdev) 315 { 316 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 317 struct rtw_pci_tx_ring *tx_ring; 318 struct rtw_pci_rx_ring *rx_ring; 319 const struct rtw_chip_info *chip = rtwdev->chip; 320 int i = 0, j = 0, tx_alloced = 0, rx_alloced = 0; 321 int tx_desc_size, rx_desc_size; 322 u32 len; 323 int ret; 324 325 tx_desc_size = chip->tx_buf_desc_sz; 326 327 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 328 tx_ring = &rtwpci->tx_rings[i]; 329 len = max_num_of_tx_queue(i); 330 ret = rtw_pci_init_tx_ring(rtwdev, tx_ring, tx_desc_size, len); 331 if (ret) 332 goto out; 333 } 334 335 rx_desc_size = chip->rx_buf_desc_sz; 336 337 for (j = 0; j < RTK_MAX_RX_QUEUE_NUM; j++) { 338 rx_ring = &rtwpci->rx_rings[j]; 339 ret = rtw_pci_init_rx_ring(rtwdev, rx_ring, rx_desc_size, 340 RTK_MAX_RX_DESC_NUM); 341 if (ret) 342 goto out; 343 } 344 345 return 0; 346 347 out: 348 tx_alloced = i; 349 for (i = 0; i < tx_alloced; i++) { 350 tx_ring = &rtwpci->tx_rings[i]; 351 rtw_pci_free_tx_ring(rtwdev, tx_ring); 352 } 353 354 rx_alloced = j; 355 for (j = 0; j < rx_alloced; j++) { 356 rx_ring = &rtwpci->rx_rings[j]; 357 rtw_pci_free_rx_ring(rtwdev, rx_ring); 358 } 359 360 return ret; 361 } 362 363 static void rtw_pci_deinit(struct rtw_dev *rtwdev) 364 { 365 rtw_pci_free_trx_ring(rtwdev); 366 } 367 368 static int rtw_pci_init(struct rtw_dev *rtwdev) 369 { 370 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 371 int ret = 0; 372 373 rtwpci->irq_mask[0] = IMR_HIGHDOK | 374 IMR_MGNTDOK | 375 IMR_BKDOK | 376 IMR_BEDOK | 377 IMR_VIDOK | 378 IMR_VODOK | 379 IMR_ROK | 380 IMR_BCNDMAINT_E | 381 IMR_C2HCMD | 382 0; 383 rtwpci->irq_mask[1] = IMR_TXFOVW | 384 0; 385 rtwpci->irq_mask[3] = IMR_H2CDOK | 386 0; 387 spin_lock_init(&rtwpci->irq_lock); 388 spin_lock_init(&rtwpci->hwirq_lock); 389 ret = rtw_pci_init_trx_ring(rtwdev); 390 391 return ret; 392 } 393 394 static void rtw_pci_reset_buf_desc(struct rtw_dev *rtwdev) 395 { 396 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 397 u32 len; 398 u8 tmp; 399 dma_addr_t dma; 400 401 tmp = rtw_read8(rtwdev, RTK_PCI_CTRL + 3); 402 rtw_write8(rtwdev, RTK_PCI_CTRL + 3, tmp | 0xf7); 403 404 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BCN].r.dma; 405 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BCNQ, dma); 406 407 if (!rtw_chip_wcpu_11n(rtwdev)) { 408 len = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.len; 409 dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma; 410 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0; 411 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; 412 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK); 413 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma); 414 } 415 416 len = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.len; 417 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.dma; 418 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.rp = 0; 419 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; 420 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BKQ, len & TRX_BD_IDX_MASK); 421 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BKQ, dma); 422 423 len = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.len; 424 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.dma; 425 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.rp = 0; 426 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; 427 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BEQ, len & TRX_BD_IDX_MASK); 428 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BEQ, dma); 429 430 len = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.len; 431 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.dma; 432 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.rp = 0; 433 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; 434 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VOQ, len & TRX_BD_IDX_MASK); 435 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VOQ, dma); 436 437 len = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.len; 438 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.dma; 439 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.rp = 0; 440 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; 441 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VIQ, len & TRX_BD_IDX_MASK); 442 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VIQ, dma); 443 444 len = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.len; 445 dma = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.dma; 446 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.rp = 0; 447 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; 448 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_MGMTQ, len & TRX_BD_IDX_MASK); 449 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_MGMTQ, dma); 450 451 len = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.len; 452 dma = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.dma; 453 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.rp = 0; 454 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; 455 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_HI0Q, len & TRX_BD_IDX_MASK); 456 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_HI0Q, dma); 457 458 len = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.len; 459 dma = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.dma; 460 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.rp = 0; 461 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0; 462 rtw_write16(rtwdev, RTK_PCI_RXBD_NUM_MPDUQ, len & TRX_BD_IDX_MASK); 463 rtw_write32(rtwdev, RTK_PCI_RXBD_DESA_MPDUQ, dma); 464 465 /* reset read/write point */ 466 rtw_write32(rtwdev, RTK_PCI_TXBD_RWPTR_CLR, 0xffffffff); 467 468 /* reset H2C Queue index in a single write */ 469 if (rtw_chip_wcpu_11ac(rtwdev)) 470 rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR, 471 BIT_CLR_H2CQ_HOST_IDX | BIT_CLR_H2CQ_HW_IDX); 472 } 473 474 static void rtw_pci_reset_trx_ring(struct rtw_dev *rtwdev) 475 { 476 rtw_pci_reset_buf_desc(rtwdev); 477 } 478 479 static void rtw_pci_enable_interrupt(struct rtw_dev *rtwdev, 480 struct rtw_pci *rtwpci, bool exclude_rx) 481 { 482 unsigned long flags; 483 u32 imr0_unmask = exclude_rx ? IMR_ROK : 0; 484 485 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 486 487 rtw_write32(rtwdev, RTK_PCI_HIMR0, rtwpci->irq_mask[0] & ~imr0_unmask); 488 rtw_write32(rtwdev, RTK_PCI_HIMR1, rtwpci->irq_mask[1]); 489 if (rtw_chip_wcpu_11ac(rtwdev)) 490 rtw_write32(rtwdev, RTK_PCI_HIMR3, rtwpci->irq_mask[3]); 491 492 rtwpci->irq_enabled = true; 493 494 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 495 } 496 497 static void rtw_pci_disable_interrupt(struct rtw_dev *rtwdev, 498 struct rtw_pci *rtwpci) 499 { 500 unsigned long flags; 501 502 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 503 504 if (!rtwpci->irq_enabled) 505 goto out; 506 507 rtw_write32(rtwdev, RTK_PCI_HIMR0, 0); 508 rtw_write32(rtwdev, RTK_PCI_HIMR1, 0); 509 if (rtw_chip_wcpu_11ac(rtwdev)) 510 rtw_write32(rtwdev, RTK_PCI_HIMR3, 0); 511 512 rtwpci->irq_enabled = false; 513 514 out: 515 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 516 } 517 518 static void rtw_pci_dma_reset(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 519 { 520 /* reset dma and rx tag */ 521 rtw_write32_set(rtwdev, RTK_PCI_CTRL, 522 BIT_RST_TRXDMA_INTF | BIT_RX_TAG_EN); 523 rtwpci->rx_tag = 0; 524 } 525 526 static int rtw_pci_setup(struct rtw_dev *rtwdev) 527 { 528 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 529 530 rtw_pci_reset_trx_ring(rtwdev); 531 rtw_pci_dma_reset(rtwdev, rtwpci); 532 533 return 0; 534 } 535 536 static void rtw_pci_dma_release(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 537 { 538 struct rtw_pci_tx_ring *tx_ring; 539 enum rtw_tx_queue_type queue; 540 541 rtw_pci_reset_trx_ring(rtwdev); 542 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 543 tx_ring = &rtwpci->tx_rings[queue]; 544 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 545 } 546 } 547 548 static void rtw_pci_napi_start(struct rtw_dev *rtwdev) 549 { 550 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 551 552 if (test_and_set_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 553 return; 554 555 napi_enable(&rtwpci->napi); 556 } 557 558 static void rtw_pci_napi_stop(struct rtw_dev *rtwdev) 559 { 560 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 561 562 if (!test_and_clear_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 563 return; 564 565 napi_synchronize(&rtwpci->napi); 566 napi_disable(&rtwpci->napi); 567 } 568 569 static int rtw_pci_start(struct rtw_dev *rtwdev) 570 { 571 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 572 573 rtw_pci_napi_start(rtwdev); 574 575 spin_lock_bh(&rtwpci->irq_lock); 576 rtwpci->running = true; 577 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 578 spin_unlock_bh(&rtwpci->irq_lock); 579 580 return 0; 581 } 582 583 static void rtw_pci_stop(struct rtw_dev *rtwdev) 584 { 585 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 586 struct pci_dev *pdev = rtwpci->pdev; 587 588 spin_lock_bh(&rtwpci->irq_lock); 589 rtwpci->running = false; 590 rtw_pci_disable_interrupt(rtwdev, rtwpci); 591 spin_unlock_bh(&rtwpci->irq_lock); 592 593 synchronize_irq(pdev->irq); 594 rtw_pci_napi_stop(rtwdev); 595 596 spin_lock_bh(&rtwpci->irq_lock); 597 rtw_pci_dma_release(rtwdev, rtwpci); 598 spin_unlock_bh(&rtwpci->irq_lock); 599 } 600 601 static void rtw_pci_deep_ps_enter(struct rtw_dev *rtwdev) 602 { 603 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 604 struct rtw_pci_tx_ring *tx_ring; 605 enum rtw_tx_queue_type queue; 606 bool tx_empty = true; 607 608 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE)) 609 goto enter_deep_ps; 610 611 lockdep_assert_held(&rtwpci->irq_lock); 612 613 /* Deep PS state is not allowed to TX-DMA */ 614 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 615 /* BCN queue is rsvd page, does not have DMA interrupt 616 * H2C queue is managed by firmware 617 */ 618 if (queue == RTW_TX_QUEUE_BCN || 619 queue == RTW_TX_QUEUE_H2C) 620 continue; 621 622 tx_ring = &rtwpci->tx_rings[queue]; 623 624 /* check if there is any skb DMAing */ 625 if (skb_queue_len(&tx_ring->queue)) { 626 tx_empty = false; 627 break; 628 } 629 } 630 631 if (!tx_empty) { 632 rtw_dbg(rtwdev, RTW_DBG_PS, 633 "TX path not empty, cannot enter deep power save state\n"); 634 return; 635 } 636 enter_deep_ps: 637 set_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags); 638 rtw_power_mode_change(rtwdev, true); 639 } 640 641 static void rtw_pci_deep_ps_leave(struct rtw_dev *rtwdev) 642 { 643 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 644 645 lockdep_assert_held(&rtwpci->irq_lock); 646 647 if (test_and_clear_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 648 rtw_power_mode_change(rtwdev, false); 649 } 650 651 static void rtw_pci_deep_ps(struct rtw_dev *rtwdev, bool enter) 652 { 653 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 654 655 spin_lock_bh(&rtwpci->irq_lock); 656 657 if (enter && !test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 658 rtw_pci_deep_ps_enter(rtwdev); 659 660 if (!enter && test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 661 rtw_pci_deep_ps_leave(rtwdev); 662 663 spin_unlock_bh(&rtwpci->irq_lock); 664 } 665 666 static void rtw_pci_release_rsvd_page(struct rtw_pci *rtwpci, 667 struct rtw_pci_tx_ring *ring) 668 { 669 struct sk_buff *prev = skb_dequeue(&ring->queue); 670 struct rtw_pci_tx_data *tx_data; 671 dma_addr_t dma; 672 673 if (!prev) 674 return; 675 676 tx_data = rtw_pci_get_tx_data(prev); 677 dma = tx_data->dma; 678 dma_unmap_single(&rtwpci->pdev->dev, dma, prev->len, DMA_TO_DEVICE); 679 dev_kfree_skb_any(prev); 680 } 681 682 static void rtw_pci_dma_check(struct rtw_dev *rtwdev, 683 struct rtw_pci_rx_ring *rx_ring, 684 u32 idx) 685 { 686 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 687 const struct rtw_chip_info *chip = rtwdev->chip; 688 struct rtw_pci_rx_buffer_desc *buf_desc; 689 u32 desc_sz = chip->rx_buf_desc_sz; 690 u16 total_pkt_size; 691 692 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 693 idx * desc_sz); 694 total_pkt_size = le16_to_cpu(buf_desc->total_pkt_size); 695 696 /* rx tag mismatch, throw a warning */ 697 if (total_pkt_size != rtwpci->rx_tag) 698 rtw_warn(rtwdev, "pci bus timeout, check dma status\n"); 699 700 rtwpci->rx_tag = (rtwpci->rx_tag + 1) % RX_TAG_MAX; 701 } 702 703 static u32 __pci_get_hw_tx_ring_rp(struct rtw_dev *rtwdev, u8 pci_q) 704 { 705 u32 bd_idx_addr = rtw_pci_tx_queue_idx_addr[pci_q]; 706 u32 bd_idx = rtw_read16(rtwdev, bd_idx_addr + 2); 707 708 return FIELD_GET(TRX_BD_IDX_MASK, bd_idx); 709 } 710 711 static void __pci_flush_queue(struct rtw_dev *rtwdev, u8 pci_q, bool drop) 712 { 713 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 714 struct rtw_pci_tx_ring *ring = &rtwpci->tx_rings[pci_q]; 715 u32 cur_rp; 716 u8 i; 717 718 /* Because the time taked by the I/O in __pci_get_hw_tx_ring_rp is a 719 * bit dynamic, it's hard to define a reasonable fixed total timeout to 720 * use read_poll_timeout* helper. Instead, we can ensure a reasonable 721 * polling times, so we just use for loop with udelay here. 722 */ 723 for (i = 0; i < 30; i++) { 724 cur_rp = __pci_get_hw_tx_ring_rp(rtwdev, pci_q); 725 if (cur_rp == ring->r.wp) 726 return; 727 728 udelay(1); 729 } 730 731 if (!drop) 732 rtw_warn(rtwdev, "timed out to flush pci tx ring[%d]\n", pci_q); 733 } 734 735 static void __rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 pci_queues, 736 bool drop) 737 { 738 u8 q; 739 740 for (q = 0; q < RTK_MAX_TX_QUEUE_NUM; q++) { 741 /* It may be not necessary to flush BCN and H2C tx queues. */ 742 if (q == RTW_TX_QUEUE_BCN || q == RTW_TX_QUEUE_H2C) 743 continue; 744 745 if (pci_queues & BIT(q)) 746 __pci_flush_queue(rtwdev, q, drop); 747 } 748 } 749 750 static void rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 751 { 752 u32 pci_queues = 0; 753 u8 i; 754 755 /* If all of the hardware queues are requested to flush, 756 * flush all of the pci queues. 757 */ 758 if (queues == BIT(rtwdev->hw->queues) - 1) { 759 pci_queues = BIT(RTK_MAX_TX_QUEUE_NUM) - 1; 760 } else { 761 for (i = 0; i < rtwdev->hw->queues; i++) 762 if (queues & BIT(i)) 763 pci_queues |= BIT(rtw_tx_ac_to_hwq(i)); 764 } 765 766 __rtw_pci_flush_queues(rtwdev, pci_queues, drop); 767 } 768 769 static void rtw_pci_tx_kick_off_queue(struct rtw_dev *rtwdev, 770 enum rtw_tx_queue_type queue) 771 { 772 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 773 struct rtw_pci_tx_ring *ring; 774 u32 bd_idx; 775 776 ring = &rtwpci->tx_rings[queue]; 777 bd_idx = rtw_pci_tx_queue_idx_addr[queue]; 778 779 spin_lock_bh(&rtwpci->irq_lock); 780 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE)) 781 rtw_pci_deep_ps_leave(rtwdev); 782 rtw_write16(rtwdev, bd_idx, ring->r.wp & TRX_BD_IDX_MASK); 783 spin_unlock_bh(&rtwpci->irq_lock); 784 } 785 786 static void rtw_pci_tx_kick_off(struct rtw_dev *rtwdev) 787 { 788 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 789 enum rtw_tx_queue_type queue; 790 791 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) 792 if (test_and_clear_bit(queue, rtwpci->tx_queued)) 793 rtw_pci_tx_kick_off_queue(rtwdev, queue); 794 } 795 796 static int rtw_pci_tx_write_data(struct rtw_dev *rtwdev, 797 struct rtw_tx_pkt_info *pkt_info, 798 struct sk_buff *skb, 799 enum rtw_tx_queue_type queue) 800 { 801 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 802 const struct rtw_chip_info *chip = rtwdev->chip; 803 struct rtw_pci_tx_ring *ring; 804 struct rtw_pci_tx_data *tx_data; 805 dma_addr_t dma; 806 u32 tx_pkt_desc_sz = chip->tx_pkt_desc_sz; 807 u32 tx_buf_desc_sz = chip->tx_buf_desc_sz; 808 u32 size; 809 u32 psb_len; 810 u8 *pkt_desc; 811 struct rtw_pci_tx_buffer_desc *buf_desc; 812 813 ring = &rtwpci->tx_rings[queue]; 814 815 size = skb->len; 816 817 if (queue == RTW_TX_QUEUE_BCN) 818 rtw_pci_release_rsvd_page(rtwpci, ring); 819 else if (!avail_desc(ring->r.wp, ring->r.rp, ring->r.len)) 820 return -ENOSPC; 821 822 pkt_desc = skb_push(skb, chip->tx_pkt_desc_sz); 823 memset(pkt_desc, 0, tx_pkt_desc_sz); 824 pkt_info->qsel = rtw_pci_get_tx_qsel(skb, queue); 825 rtw_tx_fill_tx_desc(pkt_info, skb); 826 dma = dma_map_single(&rtwpci->pdev->dev, skb->data, skb->len, 827 DMA_TO_DEVICE); 828 if (dma_mapping_error(&rtwpci->pdev->dev, dma)) 829 return -EBUSY; 830 831 /* after this we got dma mapped, there is no way back */ 832 buf_desc = get_tx_buffer_desc(ring, tx_buf_desc_sz); 833 memset(buf_desc, 0, tx_buf_desc_sz); 834 psb_len = (skb->len - 1) / 128 + 1; 835 if (queue == RTW_TX_QUEUE_BCN) 836 psb_len |= 1 << RTK_PCI_TXBD_OWN_OFFSET; 837 838 buf_desc[0].psb_len = cpu_to_le16(psb_len); 839 buf_desc[0].buf_size = cpu_to_le16(tx_pkt_desc_sz); 840 buf_desc[0].dma = cpu_to_le32(dma); 841 buf_desc[1].buf_size = cpu_to_le16(size); 842 buf_desc[1].dma = cpu_to_le32(dma + tx_pkt_desc_sz); 843 844 tx_data = rtw_pci_get_tx_data(skb); 845 tx_data->dma = dma; 846 tx_data->sn = pkt_info->sn; 847 848 spin_lock_bh(&rtwpci->irq_lock); 849 850 skb_queue_tail(&ring->queue, skb); 851 852 if (queue == RTW_TX_QUEUE_BCN) 853 goto out_unlock; 854 855 /* update write-index, and kick it off later */ 856 set_bit(queue, rtwpci->tx_queued); 857 if (++ring->r.wp >= ring->r.len) 858 ring->r.wp = 0; 859 860 out_unlock: 861 spin_unlock_bh(&rtwpci->irq_lock); 862 863 return 0; 864 } 865 866 static int rtw_pci_write_data_rsvd_page(struct rtw_dev *rtwdev, u8 *buf, 867 u32 size) 868 { 869 struct sk_buff *skb; 870 struct rtw_tx_pkt_info pkt_info = {0}; 871 u8 reg_bcn_work; 872 int ret; 873 874 skb = rtw_tx_write_data_rsvd_page_get(rtwdev, &pkt_info, buf, size); 875 if (!skb) 876 return -ENOMEM; 877 878 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_BCN); 879 if (ret) { 880 rtw_err(rtwdev, "failed to write rsvd page data\n"); 881 return ret; 882 } 883 884 /* reserved pages go through beacon queue */ 885 reg_bcn_work = rtw_read8(rtwdev, RTK_PCI_TXBD_BCN_WORK); 886 reg_bcn_work |= BIT_PCI_BCNQ_FLAG; 887 rtw_write8(rtwdev, RTK_PCI_TXBD_BCN_WORK, reg_bcn_work); 888 889 return 0; 890 } 891 892 static int rtw_pci_write_data_h2c(struct rtw_dev *rtwdev, u8 *buf, u32 size) 893 { 894 struct sk_buff *skb; 895 struct rtw_tx_pkt_info pkt_info = {0}; 896 int ret; 897 898 skb = rtw_tx_write_data_h2c_get(rtwdev, &pkt_info, buf, size); 899 if (!skb) 900 return -ENOMEM; 901 902 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_H2C); 903 if (ret) { 904 rtw_err(rtwdev, "failed to write h2c data\n"); 905 return ret; 906 } 907 908 rtw_pci_tx_kick_off_queue(rtwdev, RTW_TX_QUEUE_H2C); 909 910 return 0; 911 } 912 913 static int rtw_pci_tx_write(struct rtw_dev *rtwdev, 914 struct rtw_tx_pkt_info *pkt_info, 915 struct sk_buff *skb) 916 { 917 enum rtw_tx_queue_type queue = rtw_tx_queue_mapping(skb); 918 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 919 struct rtw_pci_tx_ring *ring; 920 int ret; 921 922 ret = rtw_pci_tx_write_data(rtwdev, pkt_info, skb, queue); 923 if (ret) 924 return ret; 925 926 ring = &rtwpci->tx_rings[queue]; 927 spin_lock_bh(&rtwpci->irq_lock); 928 if (avail_desc(ring->r.wp, ring->r.rp, ring->r.len) < 2) { 929 ieee80211_stop_queue(rtwdev->hw, skb_get_queue_mapping(skb)); 930 ring->queue_stopped = true; 931 } 932 spin_unlock_bh(&rtwpci->irq_lock); 933 934 return 0; 935 } 936 937 static void rtw_pci_tx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 938 u8 hw_queue) 939 { 940 struct ieee80211_hw *hw = rtwdev->hw; 941 struct ieee80211_tx_info *info; 942 struct rtw_pci_tx_ring *ring; 943 struct rtw_pci_tx_data *tx_data; 944 struct sk_buff *skb; 945 u32 count; 946 u32 bd_idx_addr; 947 u32 bd_idx, cur_rp, rp_idx; 948 u16 q_map; 949 950 ring = &rtwpci->tx_rings[hw_queue]; 951 952 bd_idx_addr = rtw_pci_tx_queue_idx_addr[hw_queue]; 953 bd_idx = rtw_read32(rtwdev, bd_idx_addr); 954 cur_rp = bd_idx >> 16; 955 cur_rp &= TRX_BD_IDX_MASK; 956 rp_idx = ring->r.rp; 957 if (cur_rp >= ring->r.rp) 958 count = cur_rp - ring->r.rp; 959 else 960 count = ring->r.len - (ring->r.rp - cur_rp); 961 962 while (count--) { 963 skb = skb_dequeue(&ring->queue); 964 if (!skb) { 965 rtw_err(rtwdev, "failed to dequeue %d skb TX queue %d, BD=0x%08x, rp %d -> %d\n", 966 count, hw_queue, bd_idx, ring->r.rp, cur_rp); 967 break; 968 } 969 tx_data = rtw_pci_get_tx_data(skb); 970 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 971 DMA_TO_DEVICE); 972 973 /* just free command packets from host to card */ 974 if (hw_queue == RTW_TX_QUEUE_H2C) { 975 dev_kfree_skb_irq(skb); 976 continue; 977 } 978 979 if (ring->queue_stopped && 980 avail_desc(ring->r.wp, rp_idx, ring->r.len) > 4) { 981 q_map = skb_get_queue_mapping(skb); 982 ieee80211_wake_queue(hw, q_map); 983 ring->queue_stopped = false; 984 } 985 986 if (++rp_idx >= ring->r.len) 987 rp_idx = 0; 988 989 skb_pull(skb, rtwdev->chip->tx_pkt_desc_sz); 990 991 info = IEEE80211_SKB_CB(skb); 992 993 /* enqueue to wait for tx report */ 994 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 995 rtw_tx_report_enqueue(rtwdev, skb, tx_data->sn); 996 continue; 997 } 998 999 /* always ACK for others, then they won't be marked as drop */ 1000 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1001 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 1002 else 1003 info->flags |= IEEE80211_TX_STAT_ACK; 1004 1005 ieee80211_tx_info_clear_status(info); 1006 ieee80211_tx_status_irqsafe(hw, skb); 1007 } 1008 1009 ring->r.rp = cur_rp; 1010 } 1011 1012 static void rtw_pci_rx_isr(struct rtw_dev *rtwdev) 1013 { 1014 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1015 struct napi_struct *napi = &rtwpci->napi; 1016 1017 napi_schedule(napi); 1018 } 1019 1020 static int rtw_pci_get_hw_rx_ring_nr(struct rtw_dev *rtwdev, 1021 struct rtw_pci *rtwpci) 1022 { 1023 struct rtw_pci_rx_ring *ring; 1024 int count = 0; 1025 u32 tmp, cur_wp; 1026 1027 ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 1028 tmp = rtw_read32(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ); 1029 cur_wp = u32_get_bits(tmp, TRX_BD_HW_IDX_MASK); 1030 if (cur_wp >= ring->r.wp) 1031 count = cur_wp - ring->r.wp; 1032 else 1033 count = ring->r.len - (ring->r.wp - cur_wp); 1034 1035 return count; 1036 } 1037 1038 static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 1039 u8 hw_queue, u32 limit) 1040 { 1041 const struct rtw_chip_info *chip = rtwdev->chip; 1042 struct napi_struct *napi = &rtwpci->napi; 1043 struct rtw_pci_rx_ring *ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 1044 struct rtw_rx_pkt_stat pkt_stat; 1045 struct ieee80211_rx_status rx_status; 1046 struct sk_buff *skb, *new; 1047 u32 cur_rp = ring->r.rp; 1048 u32 count, rx_done = 0; 1049 u32 pkt_offset; 1050 u32 pkt_desc_sz = chip->rx_pkt_desc_sz; 1051 u32 buf_desc_sz = chip->rx_buf_desc_sz; 1052 u32 new_len; 1053 u8 *rx_desc; 1054 dma_addr_t dma; 1055 1056 count = rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci); 1057 count = min(count, limit); 1058 1059 while (count--) { 1060 rtw_pci_dma_check(rtwdev, ring, cur_rp); 1061 skb = ring->buf[cur_rp]; 1062 dma = *((dma_addr_t *)skb->cb); 1063 dma_sync_single_for_cpu(rtwdev->dev, dma, RTK_PCI_RX_BUF_SIZE, 1064 DMA_FROM_DEVICE); 1065 rx_desc = skb->data; 1066 chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status); 1067 1068 /* offset from rx_desc to payload */ 1069 pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz + 1070 pkt_stat.shift; 1071 1072 /* allocate a new skb for this frame, 1073 * discard the frame if none available 1074 */ 1075 new_len = pkt_stat.pkt_len + pkt_offset; 1076 new = dev_alloc_skb(new_len); 1077 if (WARN_ONCE(!new, "rx routine starvation\n")) 1078 goto next_rp; 1079 1080 /* put the DMA data including rx_desc from phy to new skb */ 1081 skb_put_data(new, skb->data, new_len); 1082 1083 if (pkt_stat.is_c2h) { 1084 rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, new); 1085 } else { 1086 /* remove rx_desc */ 1087 skb_pull(new, pkt_offset); 1088 1089 rtw_rx_stats(rtwdev, pkt_stat.vif, new); 1090 memcpy(new->cb, &rx_status, sizeof(rx_status)); 1091 ieee80211_rx_napi(rtwdev->hw, NULL, new, napi); 1092 rx_done++; 1093 } 1094 1095 next_rp: 1096 /* new skb delivered to mac80211, re-enable original skb DMA */ 1097 rtw_pci_sync_rx_desc_device(rtwdev, dma, ring, cur_rp, 1098 buf_desc_sz); 1099 1100 /* host read next element in ring */ 1101 if (++cur_rp >= ring->r.len) 1102 cur_rp = 0; 1103 } 1104 1105 ring->r.rp = cur_rp; 1106 /* 'rp', the last position we have read, is seen as previous posistion 1107 * of 'wp' that is used to calculate 'count' next time. 1108 */ 1109 ring->r.wp = cur_rp; 1110 rtw_write16(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ, ring->r.rp); 1111 1112 return rx_done; 1113 } 1114 1115 static void rtw_pci_irq_recognized(struct rtw_dev *rtwdev, 1116 struct rtw_pci *rtwpci, u32 *irq_status) 1117 { 1118 unsigned long flags; 1119 1120 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 1121 1122 irq_status[0] = rtw_read32(rtwdev, RTK_PCI_HISR0); 1123 irq_status[1] = rtw_read32(rtwdev, RTK_PCI_HISR1); 1124 if (rtw_chip_wcpu_11ac(rtwdev)) 1125 irq_status[3] = rtw_read32(rtwdev, RTK_PCI_HISR3); 1126 else 1127 irq_status[3] = 0; 1128 irq_status[0] &= rtwpci->irq_mask[0]; 1129 irq_status[1] &= rtwpci->irq_mask[1]; 1130 irq_status[3] &= rtwpci->irq_mask[3]; 1131 rtw_write32(rtwdev, RTK_PCI_HISR0, irq_status[0]); 1132 rtw_write32(rtwdev, RTK_PCI_HISR1, irq_status[1]); 1133 if (rtw_chip_wcpu_11ac(rtwdev)) 1134 rtw_write32(rtwdev, RTK_PCI_HISR3, irq_status[3]); 1135 1136 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 1137 } 1138 1139 static irqreturn_t rtw_pci_interrupt_handler(int irq, void *dev) 1140 { 1141 struct rtw_dev *rtwdev = dev; 1142 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1143 1144 /* disable RTW PCI interrupt to avoid more interrupts before the end of 1145 * thread function 1146 * 1147 * disable HIMR here to also avoid new HISR flag being raised before 1148 * the HISRs have been Write-1-cleared for MSI. If not all of the HISRs 1149 * are cleared, the edge-triggered interrupt will not be generated when 1150 * a new HISR flag is set. 1151 */ 1152 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1153 1154 return IRQ_WAKE_THREAD; 1155 } 1156 1157 static irqreturn_t rtw_pci_interrupt_threadfn(int irq, void *dev) 1158 { 1159 struct rtw_dev *rtwdev = dev; 1160 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1161 u32 irq_status[4]; 1162 bool rx = false; 1163 1164 spin_lock_bh(&rtwpci->irq_lock); 1165 rtw_pci_irq_recognized(rtwdev, rtwpci, irq_status); 1166 1167 if (irq_status[0] & IMR_MGNTDOK) 1168 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_MGMT); 1169 if (irq_status[0] & IMR_HIGHDOK) 1170 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_HI0); 1171 if (irq_status[0] & IMR_BEDOK) 1172 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BE); 1173 if (irq_status[0] & IMR_BKDOK) 1174 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BK); 1175 if (irq_status[0] & IMR_VODOK) 1176 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VO); 1177 if (irq_status[0] & IMR_VIDOK) 1178 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VI); 1179 if (irq_status[3] & IMR_H2CDOK) 1180 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_H2C); 1181 if (irq_status[0] & IMR_ROK) { 1182 rtw_pci_rx_isr(rtwdev); 1183 rx = true; 1184 } 1185 if (unlikely(irq_status[0] & IMR_C2HCMD)) 1186 rtw_fw_c2h_cmd_isr(rtwdev); 1187 1188 /* all of the jobs for this interrupt have been done */ 1189 if (rtwpci->running) 1190 rtw_pci_enable_interrupt(rtwdev, rtwpci, rx); 1191 spin_unlock_bh(&rtwpci->irq_lock); 1192 1193 return IRQ_HANDLED; 1194 } 1195 1196 static int rtw_pci_io_mapping(struct rtw_dev *rtwdev, 1197 struct pci_dev *pdev) 1198 { 1199 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1200 unsigned long len; 1201 u8 bar_id = 2; 1202 int ret; 1203 1204 ret = pci_request_regions(pdev, KBUILD_MODNAME); 1205 if (ret) { 1206 rtw_err(rtwdev, "failed to request pci regions\n"); 1207 return ret; 1208 } 1209 1210 len = pci_resource_len(pdev, bar_id); 1211 rtwpci->mmap = pci_iomap(pdev, bar_id, len); 1212 if (!rtwpci->mmap) { 1213 pci_release_regions(pdev); 1214 rtw_err(rtwdev, "failed to map pci memory\n"); 1215 return -ENOMEM; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev, 1222 struct pci_dev *pdev) 1223 { 1224 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1225 1226 if (rtwpci->mmap) { 1227 pci_iounmap(pdev, rtwpci->mmap); 1228 pci_release_regions(pdev); 1229 } 1230 } 1231 1232 static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data) 1233 { 1234 u16 write_addr; 1235 u16 remainder = addr & ~(BITS_DBI_WREN | BITS_DBI_ADDR_MASK); 1236 u8 flag; 1237 u8 cnt; 1238 1239 write_addr = addr & BITS_DBI_ADDR_MASK; 1240 write_addr |= u16_encode_bits(BIT(remainder), BITS_DBI_WREN); 1241 rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data); 1242 rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr); 1243 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_WFLAG >> 16); 1244 1245 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1246 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1247 if (flag == 0) 1248 return; 1249 1250 udelay(10); 1251 } 1252 1253 WARN(flag, "failed to write to DBI register, addr=0x%04x\n", addr); 1254 } 1255 1256 static int rtw_dbi_read8(struct rtw_dev *rtwdev, u16 addr, u8 *value) 1257 { 1258 u16 read_addr = addr & BITS_DBI_ADDR_MASK; 1259 u8 flag; 1260 u8 cnt; 1261 1262 rtw_write16(rtwdev, REG_DBI_FLAG_V1, read_addr); 1263 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_RFLAG >> 16); 1264 1265 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1266 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1267 if (flag == 0) { 1268 read_addr = REG_DBI_RDATA_V1 + (addr & 3); 1269 *value = rtw_read8(rtwdev, read_addr); 1270 return 0; 1271 } 1272 1273 udelay(10); 1274 } 1275 1276 WARN(1, "failed to read DBI register, addr=0x%04x\n", addr); 1277 return -EIO; 1278 } 1279 1280 static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1) 1281 { 1282 u8 page; 1283 u8 wflag; 1284 u8 cnt; 1285 1286 rtw_write16(rtwdev, REG_MDIO_V1, data); 1287 1288 page = addr < RTW_PCI_MDIO_PG_SZ ? 0 : 1; 1289 page += g1 ? RTW_PCI_MDIO_PG_OFFS_G1 : RTW_PCI_MDIO_PG_OFFS_G2; 1290 rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & BITS_MDIO_ADDR_MASK); 1291 rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page); 1292 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1); 1293 1294 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1295 wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, 1296 BIT_MDIO_WFLAG_V1); 1297 if (wflag == 0) 1298 return; 1299 1300 udelay(10); 1301 } 1302 1303 WARN(wflag, "failed to write to MDIO register, addr=0x%02x\n", addr); 1304 } 1305 1306 static void rtw_pci_clkreq_set(struct rtw_dev *rtwdev, bool enable) 1307 { 1308 u8 value; 1309 int ret; 1310 1311 if (rtw_pci_disable_aspm) 1312 return; 1313 1314 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1315 if (ret) { 1316 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret); 1317 return; 1318 } 1319 1320 if (enable) 1321 value |= BIT_CLKREQ_SW_EN; 1322 else 1323 value &= ~BIT_CLKREQ_SW_EN; 1324 1325 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1326 } 1327 1328 static void rtw_pci_clkreq_pad_low(struct rtw_dev *rtwdev, bool enable) 1329 { 1330 u8 value; 1331 int ret; 1332 1333 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1334 if (ret) { 1335 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret); 1336 return; 1337 } 1338 1339 if (enable) 1340 value &= ~BIT_CLKREQ_N_PAD; 1341 else 1342 value |= BIT_CLKREQ_N_PAD; 1343 1344 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1345 } 1346 1347 static void rtw_pci_aspm_set(struct rtw_dev *rtwdev, bool enable) 1348 { 1349 u8 value; 1350 int ret; 1351 1352 if (rtw_pci_disable_aspm) 1353 return; 1354 1355 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1356 if (ret) { 1357 rtw_err(rtwdev, "failed to read ASPM, ret=%d", ret); 1358 return; 1359 } 1360 1361 if (enable) 1362 value |= BIT_L1_SW_EN; 1363 else 1364 value &= ~BIT_L1_SW_EN; 1365 1366 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1367 } 1368 1369 static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter) 1370 { 1371 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1372 1373 /* Like CLKREQ, ASPM is also implemented by two HW modules, and can 1374 * only be enabled when host supports it. 1375 * 1376 * And ASPM mechanism should be enabled when driver/firmware enters 1377 * power save mode, without having heavy traffic. Because we've 1378 * experienced some inter-operability issues that the link tends 1379 * to enter L1 state on the fly even when driver is having high 1380 * throughput. This is probably because the ASPM behavior slightly 1381 * varies from different SOC. 1382 */ 1383 if (!(rtwpci->link_ctrl & PCI_EXP_LNKCTL_ASPM_L1)) 1384 return; 1385 1386 if ((enter && atomic_dec_if_positive(&rtwpci->link_usage) == 0) || 1387 (!enter && atomic_inc_return(&rtwpci->link_usage) == 1)) 1388 rtw_pci_aspm_set(rtwdev, enter); 1389 } 1390 1391 static void rtw_pci_link_cfg(struct rtw_dev *rtwdev) 1392 { 1393 const struct rtw_chip_info *chip = rtwdev->chip; 1394 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1395 struct pci_dev *pdev = rtwpci->pdev; 1396 u16 link_ctrl; 1397 int ret; 1398 1399 /* RTL8822CE has enabled REFCLK auto calibration, it does not need 1400 * to add clock delay to cover the REFCLK timing gap. 1401 */ 1402 if (chip->id == RTW_CHIP_TYPE_8822C) 1403 rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0); 1404 1405 /* Though there is standard PCIE configuration space to set the 1406 * link control register, but by Realtek's design, driver should 1407 * check if host supports CLKREQ/ASPM to enable the HW module. 1408 * 1409 * These functions are implemented by two HW modules associated, 1410 * one is responsible to access PCIE configuration space to 1411 * follow the host settings, and another is in charge of doing 1412 * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes 1413 * the host does not support it, and due to some reasons or wrong 1414 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device 1415 * loss if HW misbehaves on the link. 1416 * 1417 * Hence it's designed that driver should first check the PCIE 1418 * configuration space is sync'ed and enabled, then driver can turn 1419 * on the other module that is actually working on the mechanism. 1420 */ 1421 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); 1422 if (ret) { 1423 rtw_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); 1424 return; 1425 } 1426 1427 if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) 1428 rtw_pci_clkreq_set(rtwdev, true); 1429 1430 rtwpci->link_ctrl = link_ctrl; 1431 } 1432 1433 static void rtw_pci_interface_cfg(struct rtw_dev *rtwdev) 1434 { 1435 const struct rtw_chip_info *chip = rtwdev->chip; 1436 1437 switch (chip->id) { 1438 case RTW_CHIP_TYPE_8822C: 1439 if (rtwdev->hal.cut_version >= RTW_CHIP_VER_CUT_D) 1440 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG, 1441 BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK, 1); 1442 break; 1443 default: 1444 break; 1445 } 1446 } 1447 1448 static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev) 1449 { 1450 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1451 const struct rtw_chip_info *chip = rtwdev->chip; 1452 struct pci_dev *pdev = rtwpci->pdev; 1453 const struct rtw_intf_phy_para *para; 1454 u16 cut; 1455 u16 value; 1456 u16 offset; 1457 int i; 1458 int ret; 1459 1460 cut = BIT(0) << rtwdev->hal.cut_version; 1461 1462 for (i = 0; i < chip->intf_table->n_gen1_para; i++) { 1463 para = &chip->intf_table->gen1_para[i]; 1464 if (!(para->cut_mask & cut)) 1465 continue; 1466 if (para->offset == 0xffff) 1467 break; 1468 offset = para->offset; 1469 value = para->value; 1470 if (para->ip_sel == RTW_IP_SEL_PHY) 1471 rtw_mdio_write(rtwdev, offset, value, true); 1472 else 1473 rtw_dbi_write8(rtwdev, offset, value); 1474 } 1475 1476 for (i = 0; i < chip->intf_table->n_gen2_para; i++) { 1477 para = &chip->intf_table->gen2_para[i]; 1478 if (!(para->cut_mask & cut)) 1479 continue; 1480 if (para->offset == 0xffff) 1481 break; 1482 offset = para->offset; 1483 value = para->value; 1484 if (para->ip_sel == RTW_IP_SEL_PHY) 1485 rtw_mdio_write(rtwdev, offset, value, false); 1486 else 1487 rtw_dbi_write8(rtwdev, offset, value); 1488 } 1489 1490 rtw_pci_link_cfg(rtwdev); 1491 1492 /* Disable 8821ce completion timeout by default */ 1493 if (chip->id == RTW_CHIP_TYPE_8821C) { 1494 ret = pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 1495 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 1496 if (ret) 1497 rtw_err(rtwdev, "failed to set PCI cap, ret = %d\n", 1498 ret); 1499 } 1500 } 1501 1502 static int __maybe_unused rtw_pci_suspend(struct device *dev) 1503 { 1504 struct ieee80211_hw *hw = dev_get_drvdata(dev); 1505 struct rtw_dev *rtwdev = hw->priv; 1506 const struct rtw_chip_info *chip = rtwdev->chip; 1507 struct rtw_efuse *efuse = &rtwdev->efuse; 1508 1509 if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6) 1510 rtw_pci_clkreq_pad_low(rtwdev, true); 1511 return 0; 1512 } 1513 1514 static int __maybe_unused rtw_pci_resume(struct device *dev) 1515 { 1516 struct ieee80211_hw *hw = dev_get_drvdata(dev); 1517 struct rtw_dev *rtwdev = hw->priv; 1518 const struct rtw_chip_info *chip = rtwdev->chip; 1519 struct rtw_efuse *efuse = &rtwdev->efuse; 1520 1521 if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6) 1522 rtw_pci_clkreq_pad_low(rtwdev, false); 1523 return 0; 1524 } 1525 1526 SIMPLE_DEV_PM_OPS(rtw_pm_ops, rtw_pci_suspend, rtw_pci_resume); 1527 EXPORT_SYMBOL(rtw_pm_ops); 1528 1529 static int rtw_pci_claim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1530 { 1531 int ret; 1532 1533 ret = pci_enable_device(pdev); 1534 if (ret) { 1535 rtw_err(rtwdev, "failed to enable pci device\n"); 1536 return ret; 1537 } 1538 1539 pci_set_master(pdev); 1540 pci_set_drvdata(pdev, rtwdev->hw); 1541 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); 1542 1543 return 0; 1544 } 1545 1546 static void rtw_pci_declaim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1547 { 1548 pci_disable_device(pdev); 1549 } 1550 1551 static int rtw_pci_setup_resource(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1552 { 1553 struct rtw_pci *rtwpci; 1554 int ret; 1555 1556 rtwpci = (struct rtw_pci *)rtwdev->priv; 1557 rtwpci->pdev = pdev; 1558 1559 /* after this driver can access to hw registers */ 1560 ret = rtw_pci_io_mapping(rtwdev, pdev); 1561 if (ret) { 1562 rtw_err(rtwdev, "failed to request pci io region\n"); 1563 goto err_out; 1564 } 1565 1566 ret = rtw_pci_init(rtwdev); 1567 if (ret) { 1568 rtw_err(rtwdev, "failed to allocate pci resources\n"); 1569 goto err_io_unmap; 1570 } 1571 1572 return 0; 1573 1574 err_io_unmap: 1575 rtw_pci_io_unmapping(rtwdev, pdev); 1576 1577 err_out: 1578 return ret; 1579 } 1580 1581 static void rtw_pci_destroy(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1582 { 1583 rtw_pci_deinit(rtwdev); 1584 rtw_pci_io_unmapping(rtwdev, pdev); 1585 } 1586 1587 static struct rtw_hci_ops rtw_pci_ops = { 1588 .tx_write = rtw_pci_tx_write, 1589 .tx_kick_off = rtw_pci_tx_kick_off, 1590 .flush_queues = rtw_pci_flush_queues, 1591 .setup = rtw_pci_setup, 1592 .start = rtw_pci_start, 1593 .stop = rtw_pci_stop, 1594 .deep_ps = rtw_pci_deep_ps, 1595 .link_ps = rtw_pci_link_ps, 1596 .interface_cfg = rtw_pci_interface_cfg, 1597 1598 .read8 = rtw_pci_read8, 1599 .read16 = rtw_pci_read16, 1600 .read32 = rtw_pci_read32, 1601 .write8 = rtw_pci_write8, 1602 .write16 = rtw_pci_write16, 1603 .write32 = rtw_pci_write32, 1604 .write_data_rsvd_page = rtw_pci_write_data_rsvd_page, 1605 .write_data_h2c = rtw_pci_write_data_h2c, 1606 }; 1607 1608 static int rtw_pci_request_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1609 { 1610 unsigned int flags = PCI_IRQ_LEGACY; 1611 int ret; 1612 1613 if (!rtw_disable_msi) 1614 flags |= PCI_IRQ_MSI; 1615 1616 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); 1617 if (ret < 0) { 1618 rtw_err(rtwdev, "failed to alloc PCI irq vectors\n"); 1619 return ret; 1620 } 1621 1622 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, 1623 rtw_pci_interrupt_handler, 1624 rtw_pci_interrupt_threadfn, 1625 IRQF_SHARED, KBUILD_MODNAME, rtwdev); 1626 if (ret) { 1627 rtw_err(rtwdev, "failed to request irq %d\n", ret); 1628 pci_free_irq_vectors(pdev); 1629 } 1630 1631 return ret; 1632 } 1633 1634 static void rtw_pci_free_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1635 { 1636 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); 1637 pci_free_irq_vectors(pdev); 1638 } 1639 1640 static int rtw_pci_napi_poll(struct napi_struct *napi, int budget) 1641 { 1642 struct rtw_pci *rtwpci = container_of(napi, struct rtw_pci, napi); 1643 struct rtw_dev *rtwdev = container_of((void *)rtwpci, struct rtw_dev, 1644 priv); 1645 int work_done = 0; 1646 1647 if (rtwpci->rx_no_aspm) 1648 rtw_pci_link_ps(rtwdev, false); 1649 1650 while (work_done < budget) { 1651 u32 work_done_once; 1652 1653 work_done_once = rtw_pci_rx_napi(rtwdev, rtwpci, RTW_RX_QUEUE_MPDU, 1654 budget - work_done); 1655 if (work_done_once == 0) 1656 break; 1657 work_done += work_done_once; 1658 } 1659 if (work_done < budget) { 1660 napi_complete_done(napi, work_done); 1661 spin_lock_bh(&rtwpci->irq_lock); 1662 if (rtwpci->running) 1663 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 1664 spin_unlock_bh(&rtwpci->irq_lock); 1665 /* When ISR happens during polling and before napi_complete 1666 * while no further data is received. Data on the dma_ring will 1667 * not be processed immediately. Check whether dma ring is 1668 * empty and perform napi_schedule accordingly. 1669 */ 1670 if (rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci)) 1671 napi_schedule(napi); 1672 } 1673 if (rtwpci->rx_no_aspm) 1674 rtw_pci_link_ps(rtwdev, true); 1675 1676 return work_done; 1677 } 1678 1679 static void rtw_pci_napi_init(struct rtw_dev *rtwdev) 1680 { 1681 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1682 1683 init_dummy_netdev(&rtwpci->netdev); 1684 netif_napi_add(&rtwpci->netdev, &rtwpci->napi, rtw_pci_napi_poll); 1685 } 1686 1687 static void rtw_pci_napi_deinit(struct rtw_dev *rtwdev) 1688 { 1689 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1690 1691 rtw_pci_napi_stop(rtwdev); 1692 netif_napi_del(&rtwpci->napi); 1693 } 1694 1695 int rtw_pci_probe(struct pci_dev *pdev, 1696 const struct pci_device_id *id) 1697 { 1698 struct pci_dev *bridge = pci_upstream_bridge(pdev); 1699 struct ieee80211_hw *hw; 1700 struct rtw_dev *rtwdev; 1701 struct rtw_pci *rtwpci; 1702 int drv_data_size; 1703 int ret; 1704 1705 drv_data_size = sizeof(struct rtw_dev) + sizeof(struct rtw_pci); 1706 hw = ieee80211_alloc_hw(drv_data_size, &rtw_ops); 1707 if (!hw) { 1708 dev_err(&pdev->dev, "failed to allocate hw\n"); 1709 return -ENOMEM; 1710 } 1711 1712 rtwdev = hw->priv; 1713 rtwdev->hw = hw; 1714 rtwdev->dev = &pdev->dev; 1715 rtwdev->chip = (struct rtw_chip_info *)id->driver_data; 1716 rtwdev->hci.ops = &rtw_pci_ops; 1717 rtwdev->hci.type = RTW_HCI_TYPE_PCIE; 1718 1719 rtwpci = (struct rtw_pci *)rtwdev->priv; 1720 atomic_set(&rtwpci->link_usage, 1); 1721 1722 ret = rtw_core_init(rtwdev); 1723 if (ret) 1724 goto err_release_hw; 1725 1726 rtw_dbg(rtwdev, RTW_DBG_PCI, 1727 "rtw88 pci probe: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 1728 pdev->vendor, pdev->device, pdev->revision); 1729 1730 ret = rtw_pci_claim(rtwdev, pdev); 1731 if (ret) { 1732 rtw_err(rtwdev, "failed to claim pci device\n"); 1733 goto err_deinit_core; 1734 } 1735 1736 ret = rtw_pci_setup_resource(rtwdev, pdev); 1737 if (ret) { 1738 rtw_err(rtwdev, "failed to setup pci resources\n"); 1739 goto err_pci_declaim; 1740 } 1741 1742 rtw_pci_napi_init(rtwdev); 1743 1744 ret = rtw_chip_info_setup(rtwdev); 1745 if (ret) { 1746 rtw_err(rtwdev, "failed to setup chip information\n"); 1747 goto err_destroy_pci; 1748 } 1749 1750 /* Disable PCIe ASPM L1 while doing NAPI poll for 8821CE */ 1751 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821C && bridge->vendor == PCI_VENDOR_ID_INTEL) 1752 rtwpci->rx_no_aspm = true; 1753 1754 rtw_pci_phy_cfg(rtwdev); 1755 1756 ret = rtw_register_hw(rtwdev, hw); 1757 if (ret) { 1758 rtw_err(rtwdev, "failed to register hw\n"); 1759 goto err_destroy_pci; 1760 } 1761 1762 ret = rtw_pci_request_irq(rtwdev, pdev); 1763 if (ret) { 1764 ieee80211_unregister_hw(hw); 1765 goto err_destroy_pci; 1766 } 1767 1768 return 0; 1769 1770 err_destroy_pci: 1771 rtw_pci_napi_deinit(rtwdev); 1772 rtw_pci_destroy(rtwdev, pdev); 1773 1774 err_pci_declaim: 1775 rtw_pci_declaim(rtwdev, pdev); 1776 1777 err_deinit_core: 1778 rtw_core_deinit(rtwdev); 1779 1780 err_release_hw: 1781 ieee80211_free_hw(hw); 1782 1783 return ret; 1784 } 1785 EXPORT_SYMBOL(rtw_pci_probe); 1786 1787 void rtw_pci_remove(struct pci_dev *pdev) 1788 { 1789 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1790 struct rtw_dev *rtwdev; 1791 struct rtw_pci *rtwpci; 1792 1793 if (!hw) 1794 return; 1795 1796 rtwdev = hw->priv; 1797 rtwpci = (struct rtw_pci *)rtwdev->priv; 1798 1799 rtw_unregister_hw(rtwdev, hw); 1800 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1801 rtw_pci_napi_deinit(rtwdev); 1802 rtw_pci_destroy(rtwdev, pdev); 1803 rtw_pci_declaim(rtwdev, pdev); 1804 rtw_pci_free_irq(rtwdev, pdev); 1805 rtw_core_deinit(rtwdev); 1806 ieee80211_free_hw(hw); 1807 } 1808 EXPORT_SYMBOL(rtw_pci_remove); 1809 1810 void rtw_pci_shutdown(struct pci_dev *pdev) 1811 { 1812 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1813 struct rtw_dev *rtwdev; 1814 const struct rtw_chip_info *chip; 1815 1816 if (!hw) 1817 return; 1818 1819 rtwdev = hw->priv; 1820 chip = rtwdev->chip; 1821 1822 if (chip->ops->shutdown) 1823 chip->ops->shutdown(rtwdev); 1824 1825 pci_set_power_state(pdev, PCI_D3hot); 1826 } 1827 EXPORT_SYMBOL(rtw_pci_shutdown); 1828 1829 MODULE_AUTHOR("Realtek Corporation"); 1830 MODULE_DESCRIPTION("Realtek 802.11ac wireless PCI driver"); 1831 MODULE_LICENSE("Dual BSD/GPL"); 1832