1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 15 #include "util.h" 16 17 #define RTW_MAX_MAC_ID_NUM 32 18 #define RTW_MAX_SEC_CAM_NUM 32 19 20 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 21 22 #define RFREG_MASK 0xfffff 23 #define INV_RF_DATA 0xffffffff 24 #define TX_PAGE_SIZE_SHIFT 7 25 26 #define RTW_CHANNEL_WIDTH_MAX 3 27 #define RTW_RF_PATH_MAX 4 28 #define HW_FEATURE_LEN 13 29 30 extern unsigned int rtw_debug_mask; 31 extern const struct ieee80211_ops rtw_ops; 32 extern struct rtw_chip_info rtw8822b_hw_spec; 33 extern struct rtw_chip_info rtw8822c_hw_spec; 34 35 #define RTW_MAX_CHANNEL_NUM_2G 14 36 #define RTW_MAX_CHANNEL_NUM_5G 49 37 38 struct rtw_dev; 39 40 enum rtw_hci_type { 41 RTW_HCI_TYPE_PCIE, 42 RTW_HCI_TYPE_USB, 43 RTW_HCI_TYPE_SDIO, 44 45 RTW_HCI_TYPE_UNDEFINE, 46 }; 47 48 struct rtw_hci { 49 struct rtw_hci_ops *ops; 50 enum rtw_hci_type type; 51 52 u32 rpwm_addr; 53 54 u8 bulkout_num; 55 }; 56 57 enum rtw_supported_band { 58 RTW_BAND_2G = 1 << 0, 59 RTW_BAND_5G = 1 << 1, 60 RTW_BAND_60G = 1 << 2, 61 62 RTW_BAND_MAX, 63 }; 64 65 enum rtw_bandwidth { 66 RTW_CHANNEL_WIDTH_20 = 0, 67 RTW_CHANNEL_WIDTH_40 = 1, 68 RTW_CHANNEL_WIDTH_80 = 2, 69 RTW_CHANNEL_WIDTH_160 = 3, 70 RTW_CHANNEL_WIDTH_80_80 = 4, 71 RTW_CHANNEL_WIDTH_5 = 5, 72 RTW_CHANNEL_WIDTH_10 = 6, 73 }; 74 75 enum rtw_net_type { 76 RTW_NET_NO_LINK = 0, 77 RTW_NET_AD_HOC = 1, 78 RTW_NET_MGD_LINKED = 2, 79 RTW_NET_AP_MODE = 3, 80 }; 81 82 enum rtw_rf_type { 83 RF_1T1R = 0, 84 RF_1T2R = 1, 85 RF_2T2R = 2, 86 RF_2T3R = 3, 87 RF_2T4R = 4, 88 RF_3T3R = 5, 89 RF_3T4R = 6, 90 RF_4T4R = 7, 91 RF_TYPE_MAX, 92 }; 93 94 enum rtw_rf_path { 95 RF_PATH_A = 0, 96 RF_PATH_B = 1, 97 RF_PATH_C = 2, 98 RF_PATH_D = 3, 99 }; 100 101 enum rtw_bb_path { 102 BB_PATH_A = BIT(0), 103 BB_PATH_B = BIT(1), 104 BB_PATH_C = BIT(2), 105 BB_PATH_D = BIT(3), 106 107 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 108 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 109 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 110 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 111 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 112 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 113 114 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 115 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 116 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 117 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 118 119 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 120 }; 121 122 enum rtw_rate_section { 123 RTW_RATE_SECTION_CCK = 0, 124 RTW_RATE_SECTION_OFDM, 125 RTW_RATE_SECTION_HT_1S, 126 RTW_RATE_SECTION_HT_2S, 127 RTW_RATE_SECTION_VHT_1S, 128 RTW_RATE_SECTION_VHT_2S, 129 130 /* keep last */ 131 RTW_RATE_SECTION_MAX, 132 }; 133 134 enum rtw_wireless_set { 135 WIRELESS_CCK = 0x00000001, 136 WIRELESS_OFDM = 0x00000002, 137 WIRELESS_HT = 0x00000004, 138 WIRELESS_VHT = 0x00000008, 139 }; 140 141 #define HT_STBC_EN BIT(0) 142 #define VHT_STBC_EN BIT(1) 143 #define HT_LDPC_EN BIT(0) 144 #define VHT_LDPC_EN BIT(1) 145 146 enum rtw_chip_type { 147 RTW_CHIP_TYPE_8822B, 148 RTW_CHIP_TYPE_8822C, 149 }; 150 151 enum rtw_tx_queue_type { 152 /* the order of AC queues matters */ 153 RTW_TX_QUEUE_BK = 0x0, 154 RTW_TX_QUEUE_BE = 0x1, 155 RTW_TX_QUEUE_VI = 0x2, 156 RTW_TX_QUEUE_VO = 0x3, 157 158 RTW_TX_QUEUE_BCN = 0x4, 159 RTW_TX_QUEUE_MGMT = 0x5, 160 RTW_TX_QUEUE_HI0 = 0x6, 161 RTW_TX_QUEUE_H2C = 0x7, 162 /* keep it last */ 163 RTK_MAX_TX_QUEUE_NUM 164 }; 165 166 enum rtw_rx_queue_type { 167 RTW_RX_QUEUE_MPDU = 0x0, 168 RTW_RX_QUEUE_C2H = 0x1, 169 /* keep it last */ 170 RTK_MAX_RX_QUEUE_NUM 171 }; 172 173 enum rtw_rate_index { 174 RTW_RATEID_BGN_40M_2SS = 0, 175 RTW_RATEID_BGN_40M_1SS = 1, 176 RTW_RATEID_BGN_20M_2SS = 2, 177 RTW_RATEID_BGN_20M_1SS = 3, 178 RTW_RATEID_GN_N2SS = 4, 179 RTW_RATEID_GN_N1SS = 5, 180 RTW_RATEID_BG = 6, 181 RTW_RATEID_G = 7, 182 RTW_RATEID_B_20M = 8, 183 RTW_RATEID_ARFR0_AC_2SS = 9, 184 RTW_RATEID_ARFR1_AC_1SS = 10, 185 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 186 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 187 RTW_RATEID_ARFR4_AC_3SS = 13, 188 RTW_RATEID_ARFR5_N_3SS = 14, 189 RTW_RATEID_ARFR7_N_4SS = 15, 190 RTW_RATEID_ARFR6_AC_4SS = 16 191 }; 192 193 enum rtw_trx_desc_rate { 194 DESC_RATE1M = 0x00, 195 DESC_RATE2M = 0x01, 196 DESC_RATE5_5M = 0x02, 197 DESC_RATE11M = 0x03, 198 199 DESC_RATE6M = 0x04, 200 DESC_RATE9M = 0x05, 201 DESC_RATE12M = 0x06, 202 DESC_RATE18M = 0x07, 203 DESC_RATE24M = 0x08, 204 DESC_RATE36M = 0x09, 205 DESC_RATE48M = 0x0a, 206 DESC_RATE54M = 0x0b, 207 208 DESC_RATEMCS0 = 0x0c, 209 DESC_RATEMCS1 = 0x0d, 210 DESC_RATEMCS2 = 0x0e, 211 DESC_RATEMCS3 = 0x0f, 212 DESC_RATEMCS4 = 0x10, 213 DESC_RATEMCS5 = 0x11, 214 DESC_RATEMCS6 = 0x12, 215 DESC_RATEMCS7 = 0x13, 216 DESC_RATEMCS8 = 0x14, 217 DESC_RATEMCS9 = 0x15, 218 DESC_RATEMCS10 = 0x16, 219 DESC_RATEMCS11 = 0x17, 220 DESC_RATEMCS12 = 0x18, 221 DESC_RATEMCS13 = 0x19, 222 DESC_RATEMCS14 = 0x1a, 223 DESC_RATEMCS15 = 0x1b, 224 DESC_RATEMCS16 = 0x1c, 225 DESC_RATEMCS17 = 0x1d, 226 DESC_RATEMCS18 = 0x1e, 227 DESC_RATEMCS19 = 0x1f, 228 DESC_RATEMCS20 = 0x20, 229 DESC_RATEMCS21 = 0x21, 230 DESC_RATEMCS22 = 0x22, 231 DESC_RATEMCS23 = 0x23, 232 DESC_RATEMCS24 = 0x24, 233 DESC_RATEMCS25 = 0x25, 234 DESC_RATEMCS26 = 0x26, 235 DESC_RATEMCS27 = 0x27, 236 DESC_RATEMCS28 = 0x28, 237 DESC_RATEMCS29 = 0x29, 238 DESC_RATEMCS30 = 0x2a, 239 DESC_RATEMCS31 = 0x2b, 240 241 DESC_RATEVHT1SS_MCS0 = 0x2c, 242 DESC_RATEVHT1SS_MCS1 = 0x2d, 243 DESC_RATEVHT1SS_MCS2 = 0x2e, 244 DESC_RATEVHT1SS_MCS3 = 0x2f, 245 DESC_RATEVHT1SS_MCS4 = 0x30, 246 DESC_RATEVHT1SS_MCS5 = 0x31, 247 DESC_RATEVHT1SS_MCS6 = 0x32, 248 DESC_RATEVHT1SS_MCS7 = 0x33, 249 DESC_RATEVHT1SS_MCS8 = 0x34, 250 DESC_RATEVHT1SS_MCS9 = 0x35, 251 252 DESC_RATEVHT2SS_MCS0 = 0x36, 253 DESC_RATEVHT2SS_MCS1 = 0x37, 254 DESC_RATEVHT2SS_MCS2 = 0x38, 255 DESC_RATEVHT2SS_MCS3 = 0x39, 256 DESC_RATEVHT2SS_MCS4 = 0x3a, 257 DESC_RATEVHT2SS_MCS5 = 0x3b, 258 DESC_RATEVHT2SS_MCS6 = 0x3c, 259 DESC_RATEVHT2SS_MCS7 = 0x3d, 260 DESC_RATEVHT2SS_MCS8 = 0x3e, 261 DESC_RATEVHT2SS_MCS9 = 0x3f, 262 263 DESC_RATEVHT3SS_MCS0 = 0x40, 264 DESC_RATEVHT3SS_MCS1 = 0x41, 265 DESC_RATEVHT3SS_MCS2 = 0x42, 266 DESC_RATEVHT3SS_MCS3 = 0x43, 267 DESC_RATEVHT3SS_MCS4 = 0x44, 268 DESC_RATEVHT3SS_MCS5 = 0x45, 269 DESC_RATEVHT3SS_MCS6 = 0x46, 270 DESC_RATEVHT3SS_MCS7 = 0x47, 271 DESC_RATEVHT3SS_MCS8 = 0x48, 272 DESC_RATEVHT3SS_MCS9 = 0x49, 273 274 DESC_RATEVHT4SS_MCS0 = 0x4a, 275 DESC_RATEVHT4SS_MCS1 = 0x4b, 276 DESC_RATEVHT4SS_MCS2 = 0x4c, 277 DESC_RATEVHT4SS_MCS3 = 0x4d, 278 DESC_RATEVHT4SS_MCS4 = 0x4e, 279 DESC_RATEVHT4SS_MCS5 = 0x4f, 280 DESC_RATEVHT4SS_MCS6 = 0x50, 281 DESC_RATEVHT4SS_MCS7 = 0x51, 282 DESC_RATEVHT4SS_MCS8 = 0x52, 283 DESC_RATEVHT4SS_MCS9 = 0x53, 284 285 DESC_RATE_MAX, 286 }; 287 288 enum rtw_regulatory_domains { 289 RTW_REGD_FCC = 0, 290 RTW_REGD_MKK = 1, 291 RTW_REGD_ETSI = 2, 292 RTW_REGD_WW = 3, 293 294 RTW_REGD_MAX 295 }; 296 297 enum rtw_flags { 298 RTW_FLAG_RUNNING, 299 RTW_FLAG_FW_RUNNING, 300 RTW_FLAG_SCANNING, 301 RTW_FLAG_INACTIVE_PS, 302 RTW_FLAG_LEISURE_PS, 303 RTW_FLAG_DIG_DISABLE, 304 305 NUM_OF_RTW_FLAGS, 306 }; 307 308 /* the power index is represented by differences, which cck-1s & ht40-1s are 309 * the base values, so for 1s's differences, there are only ht20 & ofdm 310 */ 311 struct rtw_2g_1s_pwr_idx_diff { 312 #ifdef __LITTLE_ENDIAN 313 s8 ofdm:4; 314 s8 bw20:4; 315 #else 316 s8 bw20:4; 317 s8 ofdm:4; 318 #endif 319 } __packed; 320 321 struct rtw_2g_ns_pwr_idx_diff { 322 #ifdef __LITTLE_ENDIAN 323 s8 bw20:4; 324 s8 bw40:4; 325 s8 cck:4; 326 s8 ofdm:4; 327 #else 328 s8 ofdm:4; 329 s8 cck:4; 330 s8 bw40:4; 331 s8 bw20:4; 332 #endif 333 } __packed; 334 335 struct rtw_2g_txpwr_idx { 336 u8 cck_base[6]; 337 u8 bw40_base[5]; 338 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 339 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 340 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 341 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 342 }; 343 344 struct rtw_5g_ht_1s_pwr_idx_diff { 345 #ifdef __LITTLE_ENDIAN 346 s8 ofdm:4; 347 s8 bw20:4; 348 #else 349 s8 bw20:4; 350 s8 ofdm:4; 351 #endif 352 } __packed; 353 354 struct rtw_5g_ht_ns_pwr_idx_diff { 355 #ifdef __LITTLE_ENDIAN 356 s8 bw20:4; 357 s8 bw40:4; 358 #else 359 s8 bw40:4; 360 s8 bw20:4; 361 #endif 362 } __packed; 363 364 struct rtw_5g_ofdm_ns_pwr_idx_diff { 365 #ifdef __LITTLE_ENDIAN 366 s8 ofdm_3s:4; 367 s8 ofdm_2s:4; 368 s8 ofdm_4s:4; 369 s8 res:4; 370 #else 371 s8 res:4; 372 s8 ofdm_4s:4; 373 s8 ofdm_2s:4; 374 s8 ofdm_3s:4; 375 #endif 376 } __packed; 377 378 struct rtw_5g_vht_ns_pwr_idx_diff { 379 #ifdef __LITTLE_ENDIAN 380 s8 bw160:4; 381 s8 bw80:4; 382 #else 383 s8 bw80:4; 384 s8 bw160:4; 385 #endif 386 } __packed; 387 388 struct rtw_5g_txpwr_idx { 389 u8 bw40_base[14]; 390 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 391 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 392 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 393 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 394 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 395 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 396 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 397 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 398 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 399 }; 400 401 struct rtw_txpwr_idx { 402 struct rtw_2g_txpwr_idx pwr_idx_2g; 403 struct rtw_5g_txpwr_idx pwr_idx_5g; 404 }; 405 406 struct rtw_timer_list { 407 struct timer_list timer; 408 void (*function)(void *data); 409 void *args; 410 }; 411 412 struct rtw_channel_params { 413 u8 center_chan; 414 u8 bandwidth; 415 u8 primary_chan_idx; 416 }; 417 418 struct rtw_hw_reg { 419 u32 addr; 420 u32 mask; 421 }; 422 423 struct rtw_backup_info { 424 u8 len; 425 u32 reg; 426 u32 val; 427 }; 428 429 enum rtw_vif_port_set { 430 PORT_SET_MAC_ADDR = BIT(0), 431 PORT_SET_BSSID = BIT(1), 432 PORT_SET_NET_TYPE = BIT(2), 433 PORT_SET_AID = BIT(3), 434 PORT_SET_BCN_CTRL = BIT(4), 435 }; 436 437 struct rtw_vif_port { 438 struct rtw_hw_reg mac_addr; 439 struct rtw_hw_reg bssid; 440 struct rtw_hw_reg net_type; 441 struct rtw_hw_reg aid; 442 struct rtw_hw_reg bcn_ctrl; 443 }; 444 445 struct rtw_tx_pkt_info { 446 u32 tx_pkt_size; 447 u8 offset; 448 u8 pkt_offset; 449 u8 mac_id; 450 u8 rate_id; 451 u8 rate; 452 u8 qsel; 453 u8 bw; 454 u8 sec_type; 455 u8 sn; 456 bool ampdu_en; 457 u8 ampdu_factor; 458 u8 ampdu_density; 459 u16 seq; 460 bool stbc; 461 bool ldpc; 462 bool dis_rate_fallback; 463 bool bmc; 464 bool use_rate; 465 bool ls; 466 bool fs; 467 bool short_gi; 468 bool report; 469 }; 470 471 struct rtw_rx_pkt_stat { 472 bool phy_status; 473 bool icv_err; 474 bool crc_err; 475 bool decrypted; 476 bool is_c2h; 477 478 s32 signal_power; 479 u16 pkt_len; 480 u8 bw; 481 u8 drv_info_sz; 482 u8 shift; 483 u8 rate; 484 u8 mac_id; 485 u8 cam_id; 486 u8 ppdu_cnt; 487 u32 tsf_low; 488 s8 rx_power[RTW_RF_PATH_MAX]; 489 u8 rssi; 490 u8 rxsc; 491 struct rtw_sta_info *si; 492 struct ieee80211_vif *vif; 493 }; 494 495 struct rtw_traffic_stats { 496 /* units in bytes */ 497 u64 tx_unicast; 498 u64 rx_unicast; 499 500 /* count for packets */ 501 u64 tx_cnt; 502 u64 rx_cnt; 503 504 /* units in Mbps */ 505 u32 tx_throughput; 506 u32 rx_throughput; 507 }; 508 509 enum rtw_lps_mode { 510 RTW_MODE_ACTIVE = 0, 511 RTW_MODE_LPS = 1, 512 RTW_MODE_WMM_PS = 2, 513 }; 514 515 enum rtw_pwr_state { 516 RTW_RF_OFF = 0x0, 517 RTW_RF_ON = 0x4, 518 RTW_ALL_ON = 0xc, 519 }; 520 521 struct rtw_lps_conf { 522 /* the interface to enter lps */ 523 struct rtw_vif *rtwvif; 524 enum rtw_lps_mode mode; 525 enum rtw_pwr_state state; 526 u8 awake_interval; 527 u8 rlbm; 528 u8 smart_ps; 529 u8 port_id; 530 }; 531 532 enum rtw_hw_key_type { 533 RTW_CAM_NONE = 0, 534 RTW_CAM_WEP40 = 1, 535 RTW_CAM_TKIP = 2, 536 RTW_CAM_AES = 4, 537 RTW_CAM_WEP104 = 5, 538 }; 539 540 struct rtw_cam_entry { 541 bool valid; 542 bool group; 543 u8 addr[ETH_ALEN]; 544 u8 hw_key_type; 545 struct ieee80211_key_conf *key; 546 }; 547 548 struct rtw_sec_desc { 549 /* search strategy */ 550 bool default_key_search; 551 552 u32 total_cam_num; 553 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 554 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 555 }; 556 557 struct rtw_tx_report { 558 /* protect the tx report queue */ 559 spinlock_t q_lock; 560 struct sk_buff_head queue; 561 atomic_t sn; 562 struct timer_list purge_timer; 563 }; 564 565 #define RTW_BC_MC_MACID 1 566 DECLARE_EWMA(rssi, 10, 16); 567 568 struct rtw_sta_info { 569 struct ieee80211_sta *sta; 570 struct ieee80211_vif *vif; 571 572 struct ewma_rssi avg_rssi; 573 u8 rssi_level; 574 575 u8 mac_id; 576 u8 rate_id; 577 enum rtw_bandwidth bw_mode; 578 enum rtw_rf_type rf_type; 579 enum rtw_wireless_set wireless_set; 580 u8 stbc_en:2; 581 u8 ldpc_en:2; 582 bool sgi_enable; 583 bool vht_enable; 584 bool updated; 585 u8 init_ra_lv; 586 u64 ra_mask; 587 }; 588 589 struct rtw_vif { 590 struct ieee80211_vif *vif; 591 enum rtw_net_type net_type; 592 u16 aid; 593 u8 mac_addr[ETH_ALEN]; 594 u8 bssid[ETH_ALEN]; 595 u8 port; 596 u8 bcn_ctrl; 597 const struct rtw_vif_port *conf; 598 599 struct rtw_traffic_stats stats; 600 bool in_lps; 601 }; 602 603 struct rtw_regulatory { 604 char alpha2[2]; 605 u8 chplan; 606 u8 txpwr_regd; 607 }; 608 609 struct rtw_chip_ops { 610 int (*mac_init)(struct rtw_dev *rtwdev); 611 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 612 void (*phy_set_param)(struct rtw_dev *rtwdev); 613 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 614 u8 bandwidth, u8 primary_chan_idx); 615 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 616 struct rtw_rx_pkt_stat *pkt_stat, 617 struct ieee80211_rx_status *rx_status); 618 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 619 u32 addr, u32 mask); 620 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 621 u32 addr, u32 mask, u32 data); 622 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 623 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 624 u32 size); 625 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx, 626 u8 antenna_rx); 627 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 628 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 629 void (*do_iqk)(struct rtw_dev *rtwdev); 630 }; 631 632 #define RTW_PWR_POLLING_CNT 20000 633 634 #define RTW_PWR_CMD_READ 0x00 635 #define RTW_PWR_CMD_WRITE 0x01 636 #define RTW_PWR_CMD_POLLING 0x02 637 #define RTW_PWR_CMD_DELAY 0x03 638 #define RTW_PWR_CMD_END 0x04 639 640 /* define the base address of each block */ 641 #define RTW_PWR_ADDR_MAC 0x00 642 #define RTW_PWR_ADDR_USB 0x01 643 #define RTW_PWR_ADDR_PCIE 0x02 644 #define RTW_PWR_ADDR_SDIO 0x03 645 646 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 647 #define RTW_PWR_INTF_USB_MSK BIT(1) 648 #define RTW_PWR_INTF_PCI_MSK BIT(2) 649 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 650 651 #define RTW_PWR_CUT_A_MSK BIT(1) 652 #define RTW_PWR_CUT_B_MSK BIT(2) 653 #define RTW_PWR_CUT_C_MSK BIT(3) 654 #define RTW_PWR_CUT_D_MSK BIT(4) 655 #define RTW_PWR_CUT_E_MSK BIT(5) 656 #define RTW_PWR_CUT_F_MSK BIT(6) 657 #define RTW_PWR_CUT_G_MSK BIT(7) 658 #define RTW_PWR_CUT_ALL_MSK 0xFF 659 660 enum rtw_pwr_seq_cmd_delay_unit { 661 RTW_PWR_DELAY_US, 662 RTW_PWR_DELAY_MS, 663 }; 664 665 struct rtw_pwr_seq_cmd { 666 u16 offset; 667 u8 cut_mask; 668 u8 intf_mask; 669 u8 base:4; 670 u8 cmd:4; 671 u8 mask; 672 u8 value; 673 }; 674 675 enum rtw_chip_ver { 676 RTW_CHIP_VER_CUT_A = 0x00, 677 RTW_CHIP_VER_CUT_B = 0x01, 678 RTW_CHIP_VER_CUT_C = 0x02, 679 RTW_CHIP_VER_CUT_D = 0x03, 680 RTW_CHIP_VER_CUT_E = 0x04, 681 RTW_CHIP_VER_CUT_F = 0x05, 682 RTW_CHIP_VER_CUT_G = 0x06, 683 }; 684 685 #define RTW_INTF_PHY_PLATFORM_ALL 0 686 687 enum rtw_intf_phy_cut { 688 RTW_INTF_PHY_CUT_A = BIT(0), 689 RTW_INTF_PHY_CUT_B = BIT(1), 690 RTW_INTF_PHY_CUT_C = BIT(2), 691 RTW_INTF_PHY_CUT_D = BIT(3), 692 RTW_INTF_PHY_CUT_E = BIT(4), 693 RTW_INTF_PHY_CUT_F = BIT(5), 694 RTW_INTF_PHY_CUT_G = BIT(6), 695 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 696 }; 697 698 enum rtw_ip_sel { 699 RTW_IP_SEL_PHY = 0, 700 RTW_IP_SEL_MAC = 1, 701 RTW_IP_SEL_DBI = 2, 702 703 RTW_IP_SEL_UNDEF = 0xFFFF 704 }; 705 706 enum rtw_pq_map_id { 707 RTW_PQ_MAP_VO = 0x0, 708 RTW_PQ_MAP_VI = 0x1, 709 RTW_PQ_MAP_BE = 0x2, 710 RTW_PQ_MAP_BK = 0x3, 711 RTW_PQ_MAP_MG = 0x4, 712 RTW_PQ_MAP_HI = 0x5, 713 RTW_PQ_MAP_NUM = 0x6, 714 715 RTW_PQ_MAP_UNDEF, 716 }; 717 718 enum rtw_dma_mapping { 719 RTW_DMA_MAPPING_EXTRA = 0, 720 RTW_DMA_MAPPING_LOW = 1, 721 RTW_DMA_MAPPING_NORMAL = 2, 722 RTW_DMA_MAPPING_HIGH = 3, 723 724 RTW_DMA_MAPPING_UNDEF, 725 }; 726 727 struct rtw_rqpn { 728 enum rtw_dma_mapping dma_map_vo; 729 enum rtw_dma_mapping dma_map_vi; 730 enum rtw_dma_mapping dma_map_be; 731 enum rtw_dma_mapping dma_map_bk; 732 enum rtw_dma_mapping dma_map_mg; 733 enum rtw_dma_mapping dma_map_hi; 734 }; 735 736 struct rtw_page_table { 737 u16 hq_num; 738 u16 nq_num; 739 u16 lq_num; 740 u16 exq_num; 741 u16 gapq_num; 742 }; 743 744 struct rtw_intf_phy_para { 745 u16 offset; 746 u16 value; 747 u16 ip_sel; 748 u16 cut_mask; 749 u16 platform; 750 }; 751 752 struct rtw_intf_phy_para_table { 753 struct rtw_intf_phy_para *usb2_para; 754 struct rtw_intf_phy_para *usb3_para; 755 struct rtw_intf_phy_para *gen1_para; 756 struct rtw_intf_phy_para *gen2_para; 757 u8 n_usb2_para; 758 u8 n_usb3_para; 759 u8 n_gen1_para; 760 u8 n_gen2_para; 761 }; 762 763 struct rtw_table { 764 const void *data; 765 const u32 size; 766 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 767 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 768 u32 addr, u32 data); 769 enum rtw_rf_path rf_path; 770 }; 771 772 static inline void rtw_load_table(struct rtw_dev *rtwdev, 773 const struct rtw_table *tbl) 774 { 775 (*tbl->parse)(rtwdev, tbl); 776 } 777 778 enum rtw_rfe_fem { 779 RTW_RFE_IFEM, 780 RTW_RFE_EFEM, 781 RTW_RFE_IFEM2G_EFEM5G, 782 RTW_RFE_NUM, 783 }; 784 785 struct rtw_rfe_def { 786 const struct rtw_table *phy_pg_tbl; 787 const struct rtw_table *txpwr_lmt_tbl; 788 }; 789 790 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 791 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 792 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 793 } 794 795 /* hardware configuration for each IC */ 796 struct rtw_chip_info { 797 struct rtw_chip_ops *ops; 798 u8 id; 799 800 const char *fw_name; 801 u8 tx_pkt_desc_sz; 802 u8 tx_buf_desc_sz; 803 u8 rx_pkt_desc_sz; 804 u8 rx_buf_desc_sz; 805 u32 phy_efuse_size; 806 u32 log_efuse_size; 807 u32 ptct_efuse_size; 808 u32 txff_size; 809 u32 rxff_size; 810 u8 band; 811 u8 page_size; 812 u8 csi_buf_pg_num; 813 u8 dig_max; 814 u8 dig_min; 815 u8 txgi_factor; 816 bool is_pwr_by_rate_dec; 817 u8 max_power_index; 818 819 bool ht_supported; 820 bool vht_supported; 821 822 /* init values */ 823 u8 sys_func_en; 824 struct rtw_pwr_seq_cmd **pwr_on_seq; 825 struct rtw_pwr_seq_cmd **pwr_off_seq; 826 struct rtw_rqpn *rqpn_table; 827 struct rtw_page_table *page_table; 828 struct rtw_intf_phy_para_table *intf_table; 829 830 struct rtw_hw_reg *dig; 831 u32 rf_base_addr[2]; 832 u32 rf_sipi_addr[2]; 833 834 const struct rtw_table *mac_tbl; 835 const struct rtw_table *agc_tbl; 836 const struct rtw_table *bb_tbl; 837 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 838 const struct rtw_table *rfk_init_tbl; 839 840 const struct rtw_rfe_def *rfe_defs; 841 u32 rfe_defs_size; 842 }; 843 844 #define DACK_MSBK_BACKUP_NUM 0xf 845 #define DACK_DCK_BACKUP_NUM 0x2 846 847 struct rtw_dm_info { 848 u32 cck_fa_cnt; 849 u32 ofdm_fa_cnt; 850 u32 total_fa_cnt; 851 u8 min_rssi; 852 u8 pre_min_rssi; 853 u16 fa_history[4]; 854 u8 igi_history[4]; 855 u8 igi_bitmap; 856 bool damping; 857 u8 damping_cnt; 858 u8 damping_rssi; 859 860 u8 cck_gi_u_bnd; 861 u8 cck_gi_l_bnd; 862 863 /* backup dack results for each path and I/Q */ 864 u32 dack_adck[RTW_RF_PATH_MAX]; 865 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 866 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 867 }; 868 869 struct rtw_efuse { 870 u32 size; 871 u32 physical_size; 872 u32 logical_size; 873 u32 protect_size; 874 875 u8 addr[ETH_ALEN]; 876 u8 channel_plan; 877 u8 country_code[2]; 878 u8 rfe_option; 879 u8 thermal_meter; 880 u8 crystal_cap; 881 u8 ant_div_cfg; 882 u8 ant_div_type; 883 u8 regd; 884 885 u8 lna_type_2g; 886 u8 lna_type_5g; 887 u8 glna_type; 888 u8 alna_type; 889 bool ext_lna_2g; 890 bool ext_lna_5g; 891 u8 pa_type_2g; 892 u8 pa_type_5g; 893 u8 gpa_type; 894 u8 apa_type; 895 bool ext_pa_2g; 896 bool ext_pa_5g; 897 898 bool btcoex; 899 /* bt share antenna with wifi */ 900 bool share_ant; 901 u8 bt_setting; 902 903 struct { 904 u8 hci; 905 u8 bw; 906 u8 ptcl; 907 u8 nss; 908 u8 ant_num; 909 } hw_cap; 910 911 struct rtw_txpwr_idx txpwr_idx_table[4]; 912 }; 913 914 struct rtw_phy_cond { 915 #ifdef __LITTLE_ENDIAN 916 u32 rfe:8; 917 u32 intf:4; 918 u32 pkg:4; 919 u32 plat:4; 920 u32 intf_rsvd:4; 921 u32 cut:4; 922 u32 branch:2; 923 u32 neg:1; 924 u32 pos:1; 925 #else 926 u32 pos:1; 927 u32 neg:1; 928 u32 branch:2; 929 u32 cut:4; 930 u32 intf_rsvd:4; 931 u32 plat:4; 932 u32 pkg:4; 933 u32 intf:4; 934 u32 rfe:8; 935 #endif 936 /* for intf:4 */ 937 #define INTF_PCIE BIT(0) 938 #define INTF_USB BIT(1) 939 #define INTF_SDIO BIT(2) 940 /* for branch:2 */ 941 #define BRANCH_IF 0 942 #define BRANCH_ELIF 1 943 #define BRANCH_ELSE 2 944 #define BRANCH_ENDIF 3 945 }; 946 947 struct rtw_fifo_conf { 948 /* tx fifo information */ 949 u16 rsvd_boundary; 950 u16 rsvd_pg_num; 951 u16 rsvd_drv_pg_num; 952 u16 txff_pg_num; 953 u16 acq_pg_num; 954 u16 rsvd_drv_addr; 955 u16 rsvd_h2c_info_addr; 956 u16 rsvd_h2c_sta_info_addr; 957 u16 rsvd_h2cq_addr; 958 u16 rsvd_cpu_instr_addr; 959 u16 rsvd_fw_txbuf_addr; 960 u16 rsvd_csibuf_addr; 961 enum rtw_dma_mapping pq_map[RTW_PQ_MAP_NUM]; 962 }; 963 964 struct rtw_fw_state { 965 const struct firmware *firmware; 966 struct completion completion; 967 u16 version; 968 u8 sub_version; 969 u8 sub_index; 970 u16 h2c_version; 971 }; 972 973 struct rtw_hal { 974 u32 rcr; 975 976 u32 chip_version; 977 u8 fab_version; 978 u8 cut_version; 979 u8 mp_chip; 980 u8 oem_id; 981 struct rtw_phy_cond phy_cond; 982 983 u8 ps_mode; 984 u8 current_channel; 985 u8 current_band_width; 986 u8 current_band_type; 987 u8 sec_ch_offset; 988 u8 rf_type; 989 u8 rf_path_num; 990 u8 antenna_tx; 991 u8 antenna_rx; 992 993 /* protect tx power section */ 994 struct mutex tx_power_mutex; 995 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 996 [DESC_RATE_MAX]; 997 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 998 [DESC_RATE_MAX]; 999 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1000 [RTW_RATE_SECTION_MAX]; 1001 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1002 [RTW_RATE_SECTION_MAX]; 1003 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1004 [RTW_CHANNEL_WIDTH_MAX] 1005 [RTW_RATE_SECTION_MAX] 1006 [RTW_MAX_CHANNEL_NUM_2G]; 1007 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1008 [RTW_CHANNEL_WIDTH_MAX] 1009 [RTW_RATE_SECTION_MAX] 1010 [RTW_MAX_CHANNEL_NUM_5G]; 1011 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1012 [DESC_RATE_MAX]; 1013 }; 1014 1015 struct rtw_dev { 1016 struct ieee80211_hw *hw; 1017 struct device *dev; 1018 1019 struct rtw_hci hci; 1020 1021 struct rtw_chip_info *chip; 1022 struct rtw_hal hal; 1023 struct rtw_fifo_conf fifo; 1024 struct rtw_fw_state fw; 1025 struct rtw_efuse efuse; 1026 struct rtw_sec_desc sec; 1027 struct rtw_traffic_stats stats; 1028 struct rtw_regulatory regd; 1029 1030 struct rtw_dm_info dm_info; 1031 1032 /* ensures exclusive access from mac80211 callbacks */ 1033 struct mutex mutex; 1034 1035 /* lock for dm to use */ 1036 spinlock_t dm_lock; 1037 1038 /* read/write rf register */ 1039 spinlock_t rf_lock; 1040 1041 /* watch dog every 2 sec */ 1042 struct delayed_work watch_dog_work; 1043 u32 watch_dog_cnt; 1044 1045 struct list_head rsvd_page_list; 1046 1047 /* c2h cmd queue & handler work */ 1048 struct sk_buff_head c2h_queue; 1049 struct work_struct c2h_work; 1050 1051 struct rtw_tx_report tx_report; 1052 1053 struct { 1054 /* incicate the mail box to use with fw */ 1055 u8 last_box_num; 1056 /* protect to send h2c to fw */ 1057 spinlock_t lock; 1058 u32 seq; 1059 } h2c; 1060 1061 /* lps power state & handler work */ 1062 struct rtw_lps_conf lps_conf; 1063 struct delayed_work lps_work; 1064 1065 struct dentry *debugfs; 1066 1067 u8 sta_cnt; 1068 1069 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1070 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1071 1072 u8 mp_mode; 1073 1074 /* hci related data, must be last */ 1075 u8 priv[0] __aligned(sizeof(void *)); 1076 }; 1077 1078 #include "hci.h" 1079 1080 static inline bool rtw_flag_check(struct rtw_dev *rtwdev, enum rtw_flags flag) 1081 { 1082 return test_bit(flag, rtwdev->flags); 1083 } 1084 1085 static inline void rtw_flag_clear(struct rtw_dev *rtwdev, enum rtw_flags flag) 1086 { 1087 clear_bit(flag, rtwdev->flags); 1088 } 1089 1090 static inline void rtw_flag_set(struct rtw_dev *rtwdev, enum rtw_flags flag) 1091 { 1092 set_bit(flag, rtwdev->flags); 1093 } 1094 1095 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1096 struct rtw_channel_params *ch_param); 1097 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1098 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1099 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1100 void rtw_restore_reg(struct rtw_dev *rtwdev, 1101 struct rtw_backup_info *bckp, u32 num); 1102 void rtw_set_channel(struct rtw_dev *rtwdev); 1103 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1104 u32 config); 1105 void rtw_tx_report_purge_timer(struct timer_list *t); 1106 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1107 int rtw_core_start(struct rtw_dev *rtwdev); 1108 void rtw_core_stop(struct rtw_dev *rtwdev); 1109 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1110 int rtw_core_init(struct rtw_dev *rtwdev); 1111 void rtw_core_deinit(struct rtw_dev *rtwdev); 1112 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1113 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1114 1115 #endif 1116