1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 17 #include "util.h" 18 19 #define RTW_MAX_MAC_ID_NUM 32 20 #define RTW_MAX_SEC_CAM_NUM 32 21 #define MAX_PG_CAM_BACKUP_NUM 8 22 23 #define RTW_MAX_PATTERN_NUM 12 24 #define RTW_MAX_PATTERN_MASK_SIZE 16 25 #define RTW_MAX_PATTERN_SIZE 128 26 27 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 28 29 #define RFREG_MASK 0xfffff 30 #define INV_RF_DATA 0xffffffff 31 #define TX_PAGE_SIZE_SHIFT 7 32 33 #define RTW_CHANNEL_WIDTH_MAX 3 34 #define RTW_RF_PATH_MAX 4 35 #define HW_FEATURE_LEN 13 36 37 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 38 39 extern bool rtw_bf_support; 40 extern unsigned int rtw_fw_lps_deep_mode; 41 extern unsigned int rtw_debug_mask; 42 extern const struct ieee80211_ops rtw_ops; 43 extern struct rtw_chip_info rtw8822b_hw_spec; 44 extern struct rtw_chip_info rtw8723d_hw_spec; 45 46 #define RTW_MAX_CHANNEL_NUM_2G 14 47 #define RTW_MAX_CHANNEL_NUM_5G 49 48 49 struct rtw_dev; 50 51 enum rtw_hci_type { 52 RTW_HCI_TYPE_PCIE, 53 RTW_HCI_TYPE_USB, 54 RTW_HCI_TYPE_SDIO, 55 56 RTW_HCI_TYPE_UNDEFINE, 57 }; 58 59 struct rtw_hci { 60 struct rtw_hci_ops *ops; 61 enum rtw_hci_type type; 62 63 u32 rpwm_addr; 64 u32 cpwm_addr; 65 66 u8 bulkout_num; 67 }; 68 69 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 70 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 71 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 72 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 73 74 #define IS_CH_5G_BAND_MID(channel) \ 75 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 76 77 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 78 #define IS_CH_5G_BAND(channel) \ 79 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 80 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 81 82 enum rtw_supported_band { 83 RTW_BAND_2G = 1 << 0, 84 RTW_BAND_5G = 1 << 1, 85 RTW_BAND_60G = 1 << 2, 86 87 RTW_BAND_MAX, 88 }; 89 90 /* now, support upto 80M bw */ 91 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 92 93 enum rtw_bandwidth { 94 RTW_CHANNEL_WIDTH_20 = 0, 95 RTW_CHANNEL_WIDTH_40 = 1, 96 RTW_CHANNEL_WIDTH_80 = 2, 97 RTW_CHANNEL_WIDTH_160 = 3, 98 RTW_CHANNEL_WIDTH_80_80 = 4, 99 RTW_CHANNEL_WIDTH_5 = 5, 100 RTW_CHANNEL_WIDTH_10 = 6, 101 }; 102 103 enum rtw_sc_offset { 104 RTW_SC_DONT_CARE = 0, 105 RTW_SC_20_UPPER = 1, 106 RTW_SC_20_LOWER = 2, 107 RTW_SC_20_UPMOST = 3, 108 RTW_SC_20_LOWEST = 4, 109 RTW_SC_40_UPPER = 9, 110 RTW_SC_40_LOWER = 10, 111 }; 112 113 enum rtw_net_type { 114 RTW_NET_NO_LINK = 0, 115 RTW_NET_AD_HOC = 1, 116 RTW_NET_MGD_LINKED = 2, 117 RTW_NET_AP_MODE = 3, 118 }; 119 120 enum rtw_rf_type { 121 RF_1T1R = 0, 122 RF_1T2R = 1, 123 RF_2T2R = 2, 124 RF_2T3R = 3, 125 RF_2T4R = 4, 126 RF_3T3R = 5, 127 RF_3T4R = 6, 128 RF_4T4R = 7, 129 RF_TYPE_MAX, 130 }; 131 132 enum rtw_rf_path { 133 RF_PATH_A = 0, 134 RF_PATH_B = 1, 135 RF_PATH_C = 2, 136 RF_PATH_D = 3, 137 }; 138 139 enum rtw_bb_path { 140 BB_PATH_A = BIT(0), 141 BB_PATH_B = BIT(1), 142 BB_PATH_C = BIT(2), 143 BB_PATH_D = BIT(3), 144 145 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 146 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 147 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 148 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 149 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 150 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 151 152 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 153 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 154 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 155 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 156 157 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 158 }; 159 160 enum rtw_rate_section { 161 RTW_RATE_SECTION_CCK = 0, 162 RTW_RATE_SECTION_OFDM, 163 RTW_RATE_SECTION_HT_1S, 164 RTW_RATE_SECTION_HT_2S, 165 RTW_RATE_SECTION_VHT_1S, 166 RTW_RATE_SECTION_VHT_2S, 167 168 /* keep last */ 169 RTW_RATE_SECTION_MAX, 170 }; 171 172 enum rtw_wireless_set { 173 WIRELESS_CCK = 0x00000001, 174 WIRELESS_OFDM = 0x00000002, 175 WIRELESS_HT = 0x00000004, 176 WIRELESS_VHT = 0x00000008, 177 }; 178 179 #define HT_STBC_EN BIT(0) 180 #define VHT_STBC_EN BIT(1) 181 #define HT_LDPC_EN BIT(0) 182 #define VHT_LDPC_EN BIT(1) 183 184 enum rtw_chip_type { 185 RTW_CHIP_TYPE_8822B, 186 RTW_CHIP_TYPE_8822C, 187 RTW_CHIP_TYPE_8723D, 188 }; 189 190 enum rtw_tx_queue_type { 191 /* the order of AC queues matters */ 192 RTW_TX_QUEUE_BK = 0x0, 193 RTW_TX_QUEUE_BE = 0x1, 194 RTW_TX_QUEUE_VI = 0x2, 195 RTW_TX_QUEUE_VO = 0x3, 196 197 RTW_TX_QUEUE_BCN = 0x4, 198 RTW_TX_QUEUE_MGMT = 0x5, 199 RTW_TX_QUEUE_HI0 = 0x6, 200 RTW_TX_QUEUE_H2C = 0x7, 201 /* keep it last */ 202 RTK_MAX_TX_QUEUE_NUM 203 }; 204 205 enum rtw_rx_queue_type { 206 RTW_RX_QUEUE_MPDU = 0x0, 207 RTW_RX_QUEUE_C2H = 0x1, 208 /* keep it last */ 209 RTK_MAX_RX_QUEUE_NUM 210 }; 211 212 enum rtw_fw_type { 213 RTW_NORMAL_FW = 0x0, 214 RTW_WOWLAN_FW = 0x1, 215 }; 216 217 enum rtw_rate_index { 218 RTW_RATEID_BGN_40M_2SS = 0, 219 RTW_RATEID_BGN_40M_1SS = 1, 220 RTW_RATEID_BGN_20M_2SS = 2, 221 RTW_RATEID_BGN_20M_1SS = 3, 222 RTW_RATEID_GN_N2SS = 4, 223 RTW_RATEID_GN_N1SS = 5, 224 RTW_RATEID_BG = 6, 225 RTW_RATEID_G = 7, 226 RTW_RATEID_B_20M = 8, 227 RTW_RATEID_ARFR0_AC_2SS = 9, 228 RTW_RATEID_ARFR1_AC_1SS = 10, 229 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 230 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 231 RTW_RATEID_ARFR4_AC_3SS = 13, 232 RTW_RATEID_ARFR5_N_3SS = 14, 233 RTW_RATEID_ARFR7_N_4SS = 15, 234 RTW_RATEID_ARFR6_AC_4SS = 16 235 }; 236 237 enum rtw_trx_desc_rate { 238 DESC_RATE1M = 0x00, 239 DESC_RATE2M = 0x01, 240 DESC_RATE5_5M = 0x02, 241 DESC_RATE11M = 0x03, 242 243 DESC_RATE6M = 0x04, 244 DESC_RATE9M = 0x05, 245 DESC_RATE12M = 0x06, 246 DESC_RATE18M = 0x07, 247 DESC_RATE24M = 0x08, 248 DESC_RATE36M = 0x09, 249 DESC_RATE48M = 0x0a, 250 DESC_RATE54M = 0x0b, 251 252 DESC_RATEMCS0 = 0x0c, 253 DESC_RATEMCS1 = 0x0d, 254 DESC_RATEMCS2 = 0x0e, 255 DESC_RATEMCS3 = 0x0f, 256 DESC_RATEMCS4 = 0x10, 257 DESC_RATEMCS5 = 0x11, 258 DESC_RATEMCS6 = 0x12, 259 DESC_RATEMCS7 = 0x13, 260 DESC_RATEMCS8 = 0x14, 261 DESC_RATEMCS9 = 0x15, 262 DESC_RATEMCS10 = 0x16, 263 DESC_RATEMCS11 = 0x17, 264 DESC_RATEMCS12 = 0x18, 265 DESC_RATEMCS13 = 0x19, 266 DESC_RATEMCS14 = 0x1a, 267 DESC_RATEMCS15 = 0x1b, 268 DESC_RATEMCS16 = 0x1c, 269 DESC_RATEMCS17 = 0x1d, 270 DESC_RATEMCS18 = 0x1e, 271 DESC_RATEMCS19 = 0x1f, 272 DESC_RATEMCS20 = 0x20, 273 DESC_RATEMCS21 = 0x21, 274 DESC_RATEMCS22 = 0x22, 275 DESC_RATEMCS23 = 0x23, 276 DESC_RATEMCS24 = 0x24, 277 DESC_RATEMCS25 = 0x25, 278 DESC_RATEMCS26 = 0x26, 279 DESC_RATEMCS27 = 0x27, 280 DESC_RATEMCS28 = 0x28, 281 DESC_RATEMCS29 = 0x29, 282 DESC_RATEMCS30 = 0x2a, 283 DESC_RATEMCS31 = 0x2b, 284 285 DESC_RATEVHT1SS_MCS0 = 0x2c, 286 DESC_RATEVHT1SS_MCS1 = 0x2d, 287 DESC_RATEVHT1SS_MCS2 = 0x2e, 288 DESC_RATEVHT1SS_MCS3 = 0x2f, 289 DESC_RATEVHT1SS_MCS4 = 0x30, 290 DESC_RATEVHT1SS_MCS5 = 0x31, 291 DESC_RATEVHT1SS_MCS6 = 0x32, 292 DESC_RATEVHT1SS_MCS7 = 0x33, 293 DESC_RATEVHT1SS_MCS8 = 0x34, 294 DESC_RATEVHT1SS_MCS9 = 0x35, 295 296 DESC_RATEVHT2SS_MCS0 = 0x36, 297 DESC_RATEVHT2SS_MCS1 = 0x37, 298 DESC_RATEVHT2SS_MCS2 = 0x38, 299 DESC_RATEVHT2SS_MCS3 = 0x39, 300 DESC_RATEVHT2SS_MCS4 = 0x3a, 301 DESC_RATEVHT2SS_MCS5 = 0x3b, 302 DESC_RATEVHT2SS_MCS6 = 0x3c, 303 DESC_RATEVHT2SS_MCS7 = 0x3d, 304 DESC_RATEVHT2SS_MCS8 = 0x3e, 305 DESC_RATEVHT2SS_MCS9 = 0x3f, 306 307 DESC_RATEVHT3SS_MCS0 = 0x40, 308 DESC_RATEVHT3SS_MCS1 = 0x41, 309 DESC_RATEVHT3SS_MCS2 = 0x42, 310 DESC_RATEVHT3SS_MCS3 = 0x43, 311 DESC_RATEVHT3SS_MCS4 = 0x44, 312 DESC_RATEVHT3SS_MCS5 = 0x45, 313 DESC_RATEVHT3SS_MCS6 = 0x46, 314 DESC_RATEVHT3SS_MCS7 = 0x47, 315 DESC_RATEVHT3SS_MCS8 = 0x48, 316 DESC_RATEVHT3SS_MCS9 = 0x49, 317 318 DESC_RATEVHT4SS_MCS0 = 0x4a, 319 DESC_RATEVHT4SS_MCS1 = 0x4b, 320 DESC_RATEVHT4SS_MCS2 = 0x4c, 321 DESC_RATEVHT4SS_MCS3 = 0x4d, 322 DESC_RATEVHT4SS_MCS4 = 0x4e, 323 DESC_RATEVHT4SS_MCS5 = 0x4f, 324 DESC_RATEVHT4SS_MCS6 = 0x50, 325 DESC_RATEVHT4SS_MCS7 = 0x51, 326 DESC_RATEVHT4SS_MCS8 = 0x52, 327 DESC_RATEVHT4SS_MCS9 = 0x53, 328 329 DESC_RATE_MAX, 330 }; 331 332 enum rtw_regulatory_domains { 333 RTW_REGD_FCC = 0, 334 RTW_REGD_MKK = 1, 335 RTW_REGD_ETSI = 2, 336 RTW_REGD_IC = 3, 337 RTW_REGD_KCC = 4, 338 RTW_REGD_ACMA = 5, 339 RTW_REGD_CHILE = 6, 340 RTW_REGD_UKRAINE = 7, 341 RTW_REGD_MEXICO = 8, 342 RTW_REGD_CN = 9, 343 RTW_REGD_WW, 344 345 RTW_REGD_MAX 346 }; 347 348 enum rtw_txq_flags { 349 RTW_TXQ_AMPDU, 350 RTW_TXQ_BLOCK_BA, 351 }; 352 353 enum rtw_flags { 354 RTW_FLAG_RUNNING, 355 RTW_FLAG_FW_RUNNING, 356 RTW_FLAG_SCANNING, 357 RTW_FLAG_INACTIVE_PS, 358 RTW_FLAG_LEISURE_PS, 359 RTW_FLAG_LEISURE_PS_DEEP, 360 RTW_FLAG_DIG_DISABLE, 361 RTW_FLAG_BUSY_TRAFFIC, 362 RTW_FLAG_WOWLAN, 363 364 NUM_OF_RTW_FLAGS, 365 }; 366 367 enum rtw_evm { 368 RTW_EVM_OFDM = 0, 369 RTW_EVM_1SS, 370 RTW_EVM_2SS_A, 371 RTW_EVM_2SS_B, 372 /* keep it last */ 373 RTW_EVM_NUM 374 }; 375 376 enum rtw_snr { 377 RTW_SNR_OFDM_A = 0, 378 RTW_SNR_OFDM_B, 379 RTW_SNR_OFDM_C, 380 RTW_SNR_OFDM_D, 381 RTW_SNR_1SS_A, 382 RTW_SNR_1SS_B, 383 RTW_SNR_1SS_C, 384 RTW_SNR_1SS_D, 385 RTW_SNR_2SS_A, 386 RTW_SNR_2SS_B, 387 RTW_SNR_2SS_C, 388 RTW_SNR_2SS_D, 389 /* keep it last */ 390 RTW_SNR_NUM 391 }; 392 393 enum rtw_wow_flags { 394 RTW_WOW_FLAG_EN_MAGIC_PKT, 395 RTW_WOW_FLAG_EN_REKEY_PKT, 396 RTW_WOW_FLAG_EN_DISCONNECT, 397 398 /* keep it last */ 399 RTW_WOW_FLAG_MAX, 400 }; 401 402 /* the power index is represented by differences, which cck-1s & ht40-1s are 403 * the base values, so for 1s's differences, there are only ht20 & ofdm 404 */ 405 struct rtw_2g_1s_pwr_idx_diff { 406 #ifdef __LITTLE_ENDIAN 407 s8 ofdm:4; 408 s8 bw20:4; 409 #else 410 s8 bw20:4; 411 s8 ofdm:4; 412 #endif 413 } __packed; 414 415 struct rtw_2g_ns_pwr_idx_diff { 416 #ifdef __LITTLE_ENDIAN 417 s8 bw20:4; 418 s8 bw40:4; 419 s8 cck:4; 420 s8 ofdm:4; 421 #else 422 s8 ofdm:4; 423 s8 cck:4; 424 s8 bw40:4; 425 s8 bw20:4; 426 #endif 427 } __packed; 428 429 struct rtw_2g_txpwr_idx { 430 u8 cck_base[6]; 431 u8 bw40_base[5]; 432 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 433 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 434 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 435 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 436 }; 437 438 struct rtw_5g_ht_1s_pwr_idx_diff { 439 #ifdef __LITTLE_ENDIAN 440 s8 ofdm:4; 441 s8 bw20:4; 442 #else 443 s8 bw20:4; 444 s8 ofdm:4; 445 #endif 446 } __packed; 447 448 struct rtw_5g_ht_ns_pwr_idx_diff { 449 #ifdef __LITTLE_ENDIAN 450 s8 bw20:4; 451 s8 bw40:4; 452 #else 453 s8 bw40:4; 454 s8 bw20:4; 455 #endif 456 } __packed; 457 458 struct rtw_5g_ofdm_ns_pwr_idx_diff { 459 #ifdef __LITTLE_ENDIAN 460 s8 ofdm_3s:4; 461 s8 ofdm_2s:4; 462 s8 ofdm_4s:4; 463 s8 res:4; 464 #else 465 s8 res:4; 466 s8 ofdm_4s:4; 467 s8 ofdm_2s:4; 468 s8 ofdm_3s:4; 469 #endif 470 } __packed; 471 472 struct rtw_5g_vht_ns_pwr_idx_diff { 473 #ifdef __LITTLE_ENDIAN 474 s8 bw160:4; 475 s8 bw80:4; 476 #else 477 s8 bw80:4; 478 s8 bw160:4; 479 #endif 480 } __packed; 481 482 struct rtw_5g_txpwr_idx { 483 u8 bw40_base[14]; 484 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 485 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 486 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 487 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 488 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 489 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 490 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 491 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 492 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 493 }; 494 495 struct rtw_txpwr_idx { 496 struct rtw_2g_txpwr_idx pwr_idx_2g; 497 struct rtw_5g_txpwr_idx pwr_idx_5g; 498 }; 499 500 struct rtw_timer_list { 501 struct timer_list timer; 502 void (*function)(void *data); 503 void *args; 504 }; 505 506 struct rtw_channel_params { 507 u8 center_chan; 508 u8 bandwidth; 509 u8 primary_chan_idx; 510 /* center channel by different available bandwidth, 511 * val of (bw > current bandwidth) is invalid 512 */ 513 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 514 }; 515 516 struct rtw_hw_reg { 517 u32 addr; 518 u32 mask; 519 }; 520 521 struct rtw_ltecoex_addr { 522 u32 ctrl; 523 u32 wdata; 524 u32 rdata; 525 }; 526 527 struct rtw_reg_domain { 528 u32 addr; 529 u32 mask; 530 #define RTW_REG_DOMAIN_MAC32 0 531 #define RTW_REG_DOMAIN_MAC16 1 532 #define RTW_REG_DOMAIN_MAC8 2 533 #define RTW_REG_DOMAIN_RF_A 3 534 #define RTW_REG_DOMAIN_RF_B 4 535 #define RTW_REG_DOMAIN_NL 0xFF 536 u8 domain; 537 }; 538 539 struct rtw_rf_sipi_addr { 540 u32 hssi_1; 541 u32 hssi_2; 542 u32 lssi_read; 543 u32 lssi_read_pi; 544 }; 545 546 struct rtw_backup_info { 547 u8 len; 548 u32 reg; 549 u32 val; 550 }; 551 552 enum rtw_vif_port_set { 553 PORT_SET_MAC_ADDR = BIT(0), 554 PORT_SET_BSSID = BIT(1), 555 PORT_SET_NET_TYPE = BIT(2), 556 PORT_SET_AID = BIT(3), 557 PORT_SET_BCN_CTRL = BIT(4), 558 }; 559 560 struct rtw_vif_port { 561 struct rtw_hw_reg mac_addr; 562 struct rtw_hw_reg bssid; 563 struct rtw_hw_reg net_type; 564 struct rtw_hw_reg aid; 565 struct rtw_hw_reg bcn_ctrl; 566 }; 567 568 struct rtw_tx_pkt_info { 569 u32 tx_pkt_size; 570 u8 offset; 571 u8 pkt_offset; 572 u8 mac_id; 573 u8 rate_id; 574 u8 rate; 575 u8 qsel; 576 u8 bw; 577 u8 sec_type; 578 u8 sn; 579 bool ampdu_en; 580 u8 ampdu_factor; 581 u8 ampdu_density; 582 u16 seq; 583 bool stbc; 584 bool ldpc; 585 bool dis_rate_fallback; 586 bool bmc; 587 bool use_rate; 588 bool ls; 589 bool fs; 590 bool short_gi; 591 bool report; 592 bool rts; 593 bool dis_qselseq; 594 bool en_hwseq; 595 u8 hw_ssn_sel; 596 }; 597 598 struct rtw_rx_pkt_stat { 599 bool phy_status; 600 bool icv_err; 601 bool crc_err; 602 bool decrypted; 603 bool is_c2h; 604 605 s32 signal_power; 606 u16 pkt_len; 607 u8 bw; 608 u8 drv_info_sz; 609 u8 shift; 610 u8 rate; 611 u8 mac_id; 612 u8 cam_id; 613 u8 ppdu_cnt; 614 u32 tsf_low; 615 s8 rx_power[RTW_RF_PATH_MAX]; 616 u8 rssi; 617 u8 rxsc; 618 s8 rx_snr[RTW_RF_PATH_MAX]; 619 u8 rx_evm[RTW_RF_PATH_MAX]; 620 s8 cfo_tail[RTW_RF_PATH_MAX]; 621 622 struct rtw_sta_info *si; 623 struct ieee80211_vif *vif; 624 }; 625 626 DECLARE_EWMA(tp, 10, 2); 627 628 struct rtw_traffic_stats { 629 /* units in bytes */ 630 u64 tx_unicast; 631 u64 rx_unicast; 632 633 /* count for packets */ 634 u64 tx_cnt; 635 u64 rx_cnt; 636 637 /* units in Mbps */ 638 u32 tx_throughput; 639 u32 rx_throughput; 640 struct ewma_tp tx_ewma_tp; 641 struct ewma_tp rx_ewma_tp; 642 }; 643 644 enum rtw_lps_mode { 645 RTW_MODE_ACTIVE = 0, 646 RTW_MODE_LPS = 1, 647 RTW_MODE_WMM_PS = 2, 648 }; 649 650 enum rtw_lps_deep_mode { 651 LPS_DEEP_MODE_NONE = 0, 652 LPS_DEEP_MODE_LCLK = 1, 653 LPS_DEEP_MODE_PG = 2, 654 }; 655 656 enum rtw_pwr_state { 657 RTW_RF_OFF = 0x0, 658 RTW_RF_ON = 0x4, 659 RTW_ALL_ON = 0xc, 660 }; 661 662 struct rtw_lps_conf { 663 enum rtw_lps_mode mode; 664 enum rtw_lps_deep_mode deep_mode; 665 enum rtw_pwr_state state; 666 u8 awake_interval; 667 u8 rlbm; 668 u8 smart_ps; 669 u8 port_id; 670 bool sec_cam_backup; 671 bool pattern_cam_backup; 672 }; 673 674 enum rtw_hw_key_type { 675 RTW_CAM_NONE = 0, 676 RTW_CAM_WEP40 = 1, 677 RTW_CAM_TKIP = 2, 678 RTW_CAM_AES = 4, 679 RTW_CAM_WEP104 = 5, 680 }; 681 682 struct rtw_cam_entry { 683 bool valid; 684 bool group; 685 u8 addr[ETH_ALEN]; 686 u8 hw_key_type; 687 struct ieee80211_key_conf *key; 688 }; 689 690 struct rtw_sec_desc { 691 /* search strategy */ 692 bool default_key_search; 693 694 u32 total_cam_num; 695 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 696 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 697 }; 698 699 struct rtw_tx_report { 700 /* protect the tx report queue */ 701 spinlock_t q_lock; 702 struct sk_buff_head queue; 703 atomic_t sn; 704 struct timer_list purge_timer; 705 }; 706 707 struct rtw_ra_report { 708 struct rate_info txrate; 709 u32 bit_rate; 710 u8 desc_rate; 711 }; 712 713 struct rtw_txq { 714 struct list_head list; 715 716 unsigned long flags; 717 unsigned long last_push; 718 }; 719 720 #define RTW_BC_MC_MACID 1 721 DECLARE_EWMA(rssi, 10, 16); 722 723 struct rtw_sta_info { 724 struct ieee80211_sta *sta; 725 struct ieee80211_vif *vif; 726 727 struct ewma_rssi avg_rssi; 728 u8 rssi_level; 729 730 u8 mac_id; 731 u8 rate_id; 732 enum rtw_bandwidth bw_mode; 733 enum rtw_rf_type rf_type; 734 enum rtw_wireless_set wireless_set; 735 u8 stbc_en:2; 736 u8 ldpc_en:2; 737 bool sgi_enable; 738 bool vht_enable; 739 bool updated; 740 u8 init_ra_lv; 741 u64 ra_mask; 742 743 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 744 745 struct rtw_ra_report ra_report; 746 747 bool use_cfg_mask; 748 struct cfg80211_bitrate_mask *mask; 749 }; 750 751 enum rtw_bfee_role { 752 RTW_BFEE_NONE, 753 RTW_BFEE_SU, 754 RTW_BFEE_MU 755 }; 756 757 struct rtw_bfee { 758 enum rtw_bfee_role role; 759 760 u16 p_aid; 761 u8 g_id; 762 u8 mac_addr[ETH_ALEN]; 763 u8 sound_dim; 764 765 /* SU-MIMO */ 766 u8 su_reg_index; 767 768 /* MU-MIMO */ 769 u16 aid; 770 }; 771 772 struct rtw_bf_info { 773 u8 bfer_mu_cnt; 774 u8 bfer_su_cnt; 775 DECLARE_BITMAP(bfer_su_reg_maping, 2); 776 u8 cur_csi_rpt_rate; 777 }; 778 779 struct rtw_vif { 780 enum rtw_net_type net_type; 781 u16 aid; 782 u8 mac_addr[ETH_ALEN]; 783 u8 bssid[ETH_ALEN]; 784 u8 port; 785 u8 bcn_ctrl; 786 struct list_head rsvd_page_list; 787 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 788 const struct rtw_vif_port *conf; 789 790 struct rtw_traffic_stats stats; 791 792 struct rtw_bfee bfee; 793 }; 794 795 struct rtw_regulatory { 796 char alpha2[2]; 797 u8 chplan; 798 u8 txpwr_regd; 799 }; 800 801 struct rtw_chip_ops { 802 int (*mac_init)(struct rtw_dev *rtwdev); 803 void (*shutdown)(struct rtw_dev *rtwdev); 804 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 805 void (*phy_set_param)(struct rtw_dev *rtwdev); 806 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 807 u8 bandwidth, u8 primary_chan_idx); 808 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 809 struct rtw_rx_pkt_stat *pkt_stat, 810 struct ieee80211_rx_status *rx_status); 811 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 812 u32 addr, u32 mask); 813 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 814 u32 addr, u32 mask, u32 data); 815 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 816 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 817 u32 size); 818 int (*set_antenna)(struct rtw_dev *rtwdev, 819 u32 antenna_tx, 820 u32 antenna_rx); 821 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 822 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 823 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 824 void (*phy_calibration)(struct rtw_dev *rtwdev); 825 void (*dpk_track)(struct rtw_dev *rtwdev); 826 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 827 void (*pwr_track)(struct rtw_dev *rtwdev); 828 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 829 struct rtw_bfee *bfee, bool enable); 830 void (*set_gid_table)(struct rtw_dev *rtwdev, 831 struct ieee80211_vif *vif, 832 struct ieee80211_bss_conf *conf); 833 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 834 u8 fixrate_en, u8 *new_rate); 835 836 /* for coex */ 837 void (*coex_set_init)(struct rtw_dev *rtwdev); 838 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 839 u8 ctrl_type, u8 pos_type); 840 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 841 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 842 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 843 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 844 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 845 }; 846 847 #define RTW_PWR_POLLING_CNT 20000 848 849 #define RTW_PWR_CMD_READ 0x00 850 #define RTW_PWR_CMD_WRITE 0x01 851 #define RTW_PWR_CMD_POLLING 0x02 852 #define RTW_PWR_CMD_DELAY 0x03 853 #define RTW_PWR_CMD_END 0x04 854 855 /* define the base address of each block */ 856 #define RTW_PWR_ADDR_MAC 0x00 857 #define RTW_PWR_ADDR_USB 0x01 858 #define RTW_PWR_ADDR_PCIE 0x02 859 #define RTW_PWR_ADDR_SDIO 0x03 860 861 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 862 #define RTW_PWR_INTF_USB_MSK BIT(1) 863 #define RTW_PWR_INTF_PCI_MSK BIT(2) 864 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 865 866 #define RTW_PWR_CUT_TEST_MSK BIT(0) 867 #define RTW_PWR_CUT_A_MSK BIT(1) 868 #define RTW_PWR_CUT_B_MSK BIT(2) 869 #define RTW_PWR_CUT_C_MSK BIT(3) 870 #define RTW_PWR_CUT_D_MSK BIT(4) 871 #define RTW_PWR_CUT_E_MSK BIT(5) 872 #define RTW_PWR_CUT_F_MSK BIT(6) 873 #define RTW_PWR_CUT_G_MSK BIT(7) 874 #define RTW_PWR_CUT_ALL_MSK 0xFF 875 876 enum rtw_pwr_seq_cmd_delay_unit { 877 RTW_PWR_DELAY_US, 878 RTW_PWR_DELAY_MS, 879 }; 880 881 struct rtw_pwr_seq_cmd { 882 u16 offset; 883 u8 cut_mask; 884 u8 intf_mask; 885 u8 base:4; 886 u8 cmd:4; 887 u8 mask; 888 u8 value; 889 }; 890 891 enum rtw_chip_ver { 892 RTW_CHIP_VER_CUT_A = 0x00, 893 RTW_CHIP_VER_CUT_B = 0x01, 894 RTW_CHIP_VER_CUT_C = 0x02, 895 RTW_CHIP_VER_CUT_D = 0x03, 896 RTW_CHIP_VER_CUT_E = 0x04, 897 RTW_CHIP_VER_CUT_F = 0x05, 898 RTW_CHIP_VER_CUT_G = 0x06, 899 }; 900 901 #define RTW_INTF_PHY_PLATFORM_ALL 0 902 903 enum rtw_intf_phy_cut { 904 RTW_INTF_PHY_CUT_A = BIT(0), 905 RTW_INTF_PHY_CUT_B = BIT(1), 906 RTW_INTF_PHY_CUT_C = BIT(2), 907 RTW_INTF_PHY_CUT_D = BIT(3), 908 RTW_INTF_PHY_CUT_E = BIT(4), 909 RTW_INTF_PHY_CUT_F = BIT(5), 910 RTW_INTF_PHY_CUT_G = BIT(6), 911 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 912 }; 913 914 enum rtw_ip_sel { 915 RTW_IP_SEL_PHY = 0, 916 RTW_IP_SEL_MAC = 1, 917 RTW_IP_SEL_DBI = 2, 918 919 RTW_IP_SEL_UNDEF = 0xFFFF 920 }; 921 922 enum rtw_pq_map_id { 923 RTW_PQ_MAP_VO = 0x0, 924 RTW_PQ_MAP_VI = 0x1, 925 RTW_PQ_MAP_BE = 0x2, 926 RTW_PQ_MAP_BK = 0x3, 927 RTW_PQ_MAP_MG = 0x4, 928 RTW_PQ_MAP_HI = 0x5, 929 RTW_PQ_MAP_NUM = 0x6, 930 931 RTW_PQ_MAP_UNDEF, 932 }; 933 934 enum rtw_dma_mapping { 935 RTW_DMA_MAPPING_EXTRA = 0, 936 RTW_DMA_MAPPING_LOW = 1, 937 RTW_DMA_MAPPING_NORMAL = 2, 938 RTW_DMA_MAPPING_HIGH = 3, 939 940 RTW_DMA_MAPPING_MAX, 941 RTW_DMA_MAPPING_UNDEF, 942 }; 943 944 struct rtw_rqpn { 945 enum rtw_dma_mapping dma_map_vo; 946 enum rtw_dma_mapping dma_map_vi; 947 enum rtw_dma_mapping dma_map_be; 948 enum rtw_dma_mapping dma_map_bk; 949 enum rtw_dma_mapping dma_map_mg; 950 enum rtw_dma_mapping dma_map_hi; 951 }; 952 953 struct rtw_prioq_addr { 954 u32 rsvd; 955 u32 avail; 956 }; 957 958 struct rtw_prioq_addrs { 959 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 960 bool wsize; 961 }; 962 963 struct rtw_page_table { 964 u16 hq_num; 965 u16 nq_num; 966 u16 lq_num; 967 u16 exq_num; 968 u16 gapq_num; 969 }; 970 971 struct rtw_intf_phy_para { 972 u16 offset; 973 u16 value; 974 u16 ip_sel; 975 u16 cut_mask; 976 u16 platform; 977 }; 978 979 struct rtw_wow_pattern { 980 u16 crc; 981 u8 type; 982 u8 valid; 983 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 984 }; 985 986 struct rtw_pno_request { 987 bool inited; 988 u32 match_set_cnt; 989 struct cfg80211_match_set *match_sets; 990 u8 channel_cnt; 991 struct ieee80211_channel *channels; 992 struct cfg80211_sched_scan_plan scan_plan; 993 }; 994 995 struct rtw_wow_param { 996 struct ieee80211_vif *wow_vif; 997 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 998 u8 txpause; 999 u8 pattern_cnt; 1000 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1001 1002 bool ips_enabled; 1003 struct rtw_pno_request pno_req; 1004 }; 1005 1006 struct rtw_intf_phy_para_table { 1007 const struct rtw_intf_phy_para *usb2_para; 1008 const struct rtw_intf_phy_para *usb3_para; 1009 const struct rtw_intf_phy_para *gen1_para; 1010 const struct rtw_intf_phy_para *gen2_para; 1011 u8 n_usb2_para; 1012 u8 n_usb3_para; 1013 u8 n_gen1_para; 1014 u8 n_gen2_para; 1015 }; 1016 1017 struct rtw_table { 1018 const void *data; 1019 const u32 size; 1020 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1021 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1022 u32 addr, u32 data); 1023 enum rtw_rf_path rf_path; 1024 }; 1025 1026 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1027 const struct rtw_table *tbl) 1028 { 1029 (*tbl->parse)(rtwdev, tbl); 1030 } 1031 1032 enum rtw_rfe_fem { 1033 RTW_RFE_IFEM, 1034 RTW_RFE_EFEM, 1035 RTW_RFE_IFEM2G_EFEM5G, 1036 RTW_RFE_NUM, 1037 }; 1038 1039 struct rtw_rfe_def { 1040 const struct rtw_table *phy_pg_tbl; 1041 const struct rtw_table *txpwr_lmt_tbl; 1042 }; 1043 1044 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1045 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1046 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1047 } 1048 1049 #define RTW_PWR_TRK_5G_1 0 1050 #define RTW_PWR_TRK_5G_2 1 1051 #define RTW_PWR_TRK_5G_3 2 1052 #define RTW_PWR_TRK_5G_NUM 3 1053 1054 #define RTW_PWR_TRK_TBL_SZ 30 1055 1056 /* This table stores the values of TX power that will be adjusted by power 1057 * tracking. 1058 * 1059 * For 5G bands, there are 3 different settings. 1060 * For 2G there are cck rate and ofdm rate with different settings. 1061 */ 1062 struct rtw_pwr_track_tbl { 1063 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1064 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1065 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1066 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1067 const u8 *pwrtrk_2gb_n; 1068 const u8 *pwrtrk_2gb_p; 1069 const u8 *pwrtrk_2ga_n; 1070 const u8 *pwrtrk_2ga_p; 1071 const u8 *pwrtrk_2g_cckb_n; 1072 const u8 *pwrtrk_2g_cckb_p; 1073 const u8 *pwrtrk_2g_ccka_n; 1074 const u8 *pwrtrk_2g_ccka_p; 1075 const s8 *pwrtrk_xtal_n; 1076 const s8 *pwrtrk_xtal_p; 1077 }; 1078 1079 enum rtw_wlan_cpu { 1080 RTW_WCPU_11AC, 1081 RTW_WCPU_11N, 1082 }; 1083 1084 /* hardware configuration for each IC */ 1085 struct rtw_chip_info { 1086 struct rtw_chip_ops *ops; 1087 u8 id; 1088 1089 const char *fw_name; 1090 enum rtw_wlan_cpu wlan_cpu; 1091 u8 tx_pkt_desc_sz; 1092 u8 tx_buf_desc_sz; 1093 u8 rx_pkt_desc_sz; 1094 u8 rx_buf_desc_sz; 1095 u32 phy_efuse_size; 1096 u32 log_efuse_size; 1097 u32 ptct_efuse_size; 1098 u32 txff_size; 1099 u32 rxff_size; 1100 u8 band; 1101 u8 page_size; 1102 u8 csi_buf_pg_num; 1103 u8 dig_max; 1104 u8 dig_min; 1105 u8 txgi_factor; 1106 bool is_pwr_by_rate_dec; 1107 bool rx_ldpc; 1108 u8 max_power_index; 1109 1110 bool ht_supported; 1111 bool vht_supported; 1112 u8 lps_deep_mode_supported; 1113 1114 /* init values */ 1115 u8 sys_func_en; 1116 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1117 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1118 const struct rtw_rqpn *rqpn_table; 1119 const struct rtw_prioq_addrs *prioq_addrs; 1120 const struct rtw_page_table *page_table; 1121 const struct rtw_intf_phy_para_table *intf_table; 1122 1123 const struct rtw_hw_reg *dig; 1124 const struct rtw_hw_reg *dig_cck; 1125 u32 rf_base_addr[2]; 1126 u32 rf_sipi_addr[2]; 1127 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1128 u8 fix_rf_phy_num; 1129 const struct rtw_ltecoex_addr *ltecoex_addr; 1130 1131 const struct rtw_table *mac_tbl; 1132 const struct rtw_table *agc_tbl; 1133 const struct rtw_table *bb_tbl; 1134 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1135 const struct rtw_table *rfk_init_tbl; 1136 1137 const struct rtw_rfe_def *rfe_defs; 1138 u32 rfe_defs_size; 1139 1140 bool en_dis_dpd; 1141 u16 dpd_ratemask; 1142 u8 iqk_threshold; 1143 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1144 1145 u8 bfer_su_max_num; 1146 u8 bfer_mu_max_num; 1147 1148 const char *wow_fw_name; 1149 const struct wiphy_wowlan_support *wowlan_stub; 1150 const u8 max_sched_scan_ssids; 1151 1152 /* coex paras */ 1153 u32 coex_para_ver; 1154 u8 bt_desired_ver; 1155 bool scbd_support; 1156 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1157 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1158 u8 bt_rssi_type; 1159 u8 ant_isolation; 1160 u8 rssi_tolerance; 1161 u8 table_sant_num; 1162 u8 table_nsant_num; 1163 u8 tdma_sant_num; 1164 u8 tdma_nsant_num; 1165 u8 bt_afh_span_bw20; 1166 u8 bt_afh_span_bw40; 1167 u8 afh_5g_num; 1168 u8 wl_rf_para_num; 1169 u8 coex_info_hw_regs_num; 1170 const u8 *bt_rssi_step; 1171 const u8 *wl_rssi_step; 1172 const struct coex_table_para *table_nsant; 1173 const struct coex_table_para *table_sant; 1174 const struct coex_tdma_para *tdma_sant; 1175 const struct coex_tdma_para *tdma_nsant; 1176 const struct coex_rf_para *wl_rf_para_tx; 1177 const struct coex_rf_para *wl_rf_para_rx; 1178 const struct coex_5g_afh_map *afh_5g; 1179 const struct rtw_reg_domain *coex_info_hw_regs; 1180 }; 1181 1182 enum rtw_coex_bt_state_cnt { 1183 COEX_CNT_BT_RETRY, 1184 COEX_CNT_BT_REINIT, 1185 COEX_CNT_BT_REENABLE, 1186 COEX_CNT_BT_POPEVENT, 1187 COEX_CNT_BT_SETUPLINK, 1188 COEX_CNT_BT_IGNWLANACT, 1189 COEX_CNT_BT_INQ, 1190 COEX_CNT_BT_PAGE, 1191 COEX_CNT_BT_ROLESWITCH, 1192 COEX_CNT_BT_AFHUPDATE, 1193 COEX_CNT_BT_INFOUPDATE, 1194 COEX_CNT_BT_IQK, 1195 COEX_CNT_BT_IQKFAIL, 1196 1197 COEX_CNT_BT_MAX 1198 }; 1199 1200 enum rtw_coex_wl_state_cnt { 1201 COEX_CNT_WL_CONNPKT, 1202 COEX_CNT_WL_COEXRUN, 1203 COEX_CNT_WL_NOISY0, 1204 COEX_CNT_WL_NOISY1, 1205 COEX_CNT_WL_NOISY2, 1206 COEX_CNT_WL_5MS_NOEXTEND, 1207 COEX_CNT_WL_FW_NOTIFY, 1208 1209 COEX_CNT_WL_MAX 1210 }; 1211 1212 struct rtw_coex_rfe { 1213 bool ant_switch_exist; 1214 bool ant_switch_diversity; 1215 bool ant_switch_with_bt; 1216 u8 rfe_module_type; 1217 u8 ant_switch_polarity; 1218 1219 /* true if WLG at BTG, else at WLAG */ 1220 bool wlg_at_btg; 1221 }; 1222 1223 struct rtw_coex_dm { 1224 bool cur_ps_tdma_on; 1225 bool cur_wl_rx_low_gain_en; 1226 bool ignore_wl_act; 1227 1228 u8 reason; 1229 u8 bt_rssi_state[4]; 1230 u8 wl_rssi_state[4]; 1231 u8 wl_ch_info[3]; 1232 u8 cur_ps_tdma; 1233 u8 cur_table; 1234 u8 ps_tdma_para[5]; 1235 u8 cur_bt_pwr_lvl; 1236 u8 cur_bt_lna_lvl; 1237 u8 cur_wl_pwr_lvl; 1238 u8 bt_status; 1239 u32 cur_ant_pos_type; 1240 u32 cur_switch_status; 1241 u32 setting_tdma; 1242 }; 1243 1244 #define COEX_BTINFO_SRC_WL_FW 0x0 1245 #define COEX_BTINFO_SRC_BT_RSP 0x1 1246 #define COEX_BTINFO_SRC_BT_ACT 0x2 1247 #define COEX_BTINFO_SRC_BT_IQK 0x3 1248 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1249 #define COEX_BTINFO_SRC_MAX 0x5 1250 1251 #define COEX_INFO_FTP BIT(7) 1252 #define COEX_INFO_A2DP BIT(6) 1253 #define COEX_INFO_HID BIT(5) 1254 #define COEX_INFO_SCO_BUSY BIT(4) 1255 #define COEX_INFO_ACL_BUSY BIT(3) 1256 #define COEX_INFO_INQ_PAGE BIT(2) 1257 #define COEX_INFO_SCO_ESCO BIT(1) 1258 #define COEX_INFO_CONNECTION BIT(0) 1259 #define COEX_BTINFO_LENGTH_MAX 10 1260 1261 struct rtw_coex_stat { 1262 bool bt_disabled; 1263 bool bt_disabled_pre; 1264 bool bt_link_exist; 1265 bool bt_whck_test; 1266 bool bt_inq_page; 1267 bool bt_inq; 1268 bool bt_page; 1269 bool bt_ble_voice; 1270 bool bt_ble_exist; 1271 bool bt_hfp_exist; 1272 bool bt_a2dp_exist; 1273 bool bt_hid_exist; 1274 bool bt_pan_exist; /* PAN or OPP */ 1275 bool bt_opp_exist; /* OPP only */ 1276 bool bt_acl_busy; 1277 bool bt_fix_2M; 1278 bool bt_setup_link; 1279 bool bt_multi_link; 1280 bool bt_a2dp_sink; 1281 bool bt_a2dp_active; 1282 bool bt_reenable; 1283 bool bt_ble_scan_en; 1284 bool bt_init_scan; 1285 bool bt_slave; 1286 bool bt_418_hid_exist; 1287 bool bt_mailbox_reply; 1288 1289 bool wl_under_lps; 1290 bool wl_under_ips; 1291 bool wl_hi_pri_task1; 1292 bool wl_hi_pri_task2; 1293 bool wl_force_lps_ctrl; 1294 bool wl_gl_busy; 1295 bool wl_linkscan_proc; 1296 bool wl_ps_state_fail; 1297 bool wl_tx_limit_en; 1298 bool wl_ampdu_limit_en; 1299 bool wl_connected; 1300 bool wl_slot_extend; 1301 bool wl_cck_lock; 1302 bool wl_cck_lock_pre; 1303 bool wl_cck_lock_ever; 1304 1305 u32 bt_supported_version; 1306 u32 bt_supported_feature; 1307 u32 patch_ver; 1308 u16 bt_reg_vendor_ae; 1309 u16 bt_reg_vendor_ac; 1310 s8 bt_rssi; 1311 u8 kt_ver; 1312 u8 gnt_workaround_state; 1313 u8 tdma_timer_base; 1314 u8 bt_profile_num; 1315 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1316 u8 bt_info_lb2; 1317 u8 bt_info_lb3; 1318 u8 bt_info_hb0; 1319 u8 bt_info_hb1; 1320 u8 bt_info_hb2; 1321 u8 bt_info_hb3; 1322 u8 bt_ble_scan_type; 1323 u8 bt_hid_pair_num; 1324 u8 bt_hid_slot; 1325 u8 bt_a2dp_bitpool; 1326 u8 bt_iqk_state; 1327 1328 u8 wl_noisy_level; 1329 u8 wl_fw_dbg_info[10]; 1330 u8 wl_fw_dbg_info_pre[10]; 1331 u8 wl_coex_mode; 1332 u8 ampdu_max_time; 1333 u8 wl_tput_dir; 1334 1335 u16 score_board; 1336 u16 retry_limit; 1337 1338 /* counters to record bt states */ 1339 u32 cnt_bt[COEX_CNT_BT_MAX]; 1340 1341 /* counters to record wifi states */ 1342 u32 cnt_wl[COEX_CNT_WL_MAX]; 1343 1344 u32 darfrc; 1345 u32 darfrch; 1346 }; 1347 1348 struct rtw_coex { 1349 /* protects coex info request section */ 1350 struct mutex mutex; 1351 struct sk_buff_head queue; 1352 wait_queue_head_t wait; 1353 1354 bool under_5g; 1355 bool stop_dm; 1356 bool freeze; 1357 bool freerun; 1358 bool wl_rf_off; 1359 1360 struct rtw_coex_stat stat; 1361 struct rtw_coex_dm dm; 1362 struct rtw_coex_rfe rfe; 1363 1364 struct delayed_work bt_relink_work; 1365 struct delayed_work bt_reenable_work; 1366 struct delayed_work defreeze_work; 1367 }; 1368 1369 #define DPK_RF_REG_NUM 7 1370 #define DPK_RF_PATH_NUM 2 1371 #define DPK_BB_REG_NUM 18 1372 #define DPK_CHANNEL_WIDTH_80 1 1373 1374 DECLARE_EWMA(thermal, 10, 4); 1375 1376 struct rtw_dpk_info { 1377 bool is_dpk_pwr_on; 1378 bool is_reload; 1379 1380 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1381 1382 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1383 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1384 1385 u32 gnt_control; 1386 u32 gnt_value; 1387 1388 u8 result[RTW_RF_PATH_MAX]; 1389 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1390 u32 coef[RTW_RF_PATH_MAX][20]; 1391 u16 dpk_gs[RTW_RF_PATH_MAX]; 1392 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1393 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1394 1395 u8 dpk_band; 1396 u8 dpk_ch; 1397 u8 dpk_bw; 1398 }; 1399 1400 struct rtw_phy_cck_pd_reg { 1401 u32 reg_pd; 1402 u32 mask_pd; 1403 u32 reg_cs; 1404 u32 mask_cs; 1405 }; 1406 1407 #define DACK_MSBK_BACKUP_NUM 0xf 1408 #define DACK_DCK_BACKUP_NUM 0x2 1409 1410 struct rtw_swing_table { 1411 const u8 *p[RTW_RF_PATH_MAX]; 1412 const u8 *n[RTW_RF_PATH_MAX]; 1413 }; 1414 1415 struct rtw_pkt_count { 1416 u16 num_bcn_pkt; 1417 u16 num_qry_pkt[DESC_RATE_MAX]; 1418 }; 1419 1420 DECLARE_EWMA(evm, 10, 4); 1421 DECLARE_EWMA(snr, 10, 4); 1422 1423 struct rtw_iqk_info { 1424 bool done; 1425 struct { 1426 u32 s1_x; 1427 u32 s1_y; 1428 u32 s0_x; 1429 u32 s0_y; 1430 } result; 1431 }; 1432 1433 struct rtw_dm_info { 1434 u32 cck_fa_cnt; 1435 u32 ofdm_fa_cnt; 1436 u32 total_fa_cnt; 1437 u32 cck_cca_cnt; 1438 u32 ofdm_cca_cnt; 1439 u32 total_cca_cnt; 1440 1441 u32 cck_ok_cnt; 1442 u32 cck_err_cnt; 1443 u32 ofdm_ok_cnt; 1444 u32 ofdm_err_cnt; 1445 u32 ht_ok_cnt; 1446 u32 ht_err_cnt; 1447 u32 vht_ok_cnt; 1448 u32 vht_err_cnt; 1449 1450 u8 min_rssi; 1451 u8 pre_min_rssi; 1452 u16 fa_history[4]; 1453 u8 igi_history[4]; 1454 u8 igi_bitmap; 1455 bool damping; 1456 u8 damping_cnt; 1457 u8 damping_rssi; 1458 1459 u8 cck_gi_u_bnd; 1460 u8 cck_gi_l_bnd; 1461 1462 u8 tx_rate; 1463 u8 thermal_avg[RTW_RF_PATH_MAX]; 1464 u8 thermal_meter_k; 1465 s8 delta_power_index[RTW_RF_PATH_MAX]; 1466 u8 default_ofdm_index; 1467 bool pwr_trk_triggered; 1468 bool pwr_trk_init_trigger; 1469 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1470 s8 txagc_remnant_cck; 1471 s8 txagc_remnant_ofdm; 1472 1473 /* backup dack results for each path and I/Q */ 1474 u32 dack_adck[RTW_RF_PATH_MAX]; 1475 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1476 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1477 1478 struct rtw_dpk_info dpk_info; 1479 1480 /* [bandwidth 0:20M/1:40M][number of path] */ 1481 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1482 u32 cck_fa_avg; 1483 1484 /* save the last rx phy status for debug */ 1485 s8 rx_snr[RTW_RF_PATH_MAX]; 1486 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1487 s16 cfo_tail[RTW_RF_PATH_MAX]; 1488 u8 rssi[RTW_RF_PATH_MAX]; 1489 u8 curr_rx_rate; 1490 struct rtw_pkt_count cur_pkt_count; 1491 struct rtw_pkt_count last_pkt_count; 1492 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1493 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1494 1495 struct rtw_iqk_info iqk; 1496 }; 1497 1498 struct rtw_efuse { 1499 u32 size; 1500 u32 physical_size; 1501 u32 logical_size; 1502 u32 protect_size; 1503 1504 u8 addr[ETH_ALEN]; 1505 u8 channel_plan; 1506 u8 country_code[2]; 1507 u8 rf_board_option; 1508 u8 rfe_option; 1509 u8 power_track_type; 1510 u8 thermal_meter[RTW_RF_PATH_MAX]; 1511 u8 thermal_meter_k; 1512 u8 crystal_cap; 1513 u8 ant_div_cfg; 1514 u8 ant_div_type; 1515 u8 regd; 1516 u8 afe; 1517 1518 u8 lna_type_2g; 1519 u8 lna_type_5g; 1520 u8 glna_type; 1521 u8 alna_type; 1522 bool ext_lna_2g; 1523 bool ext_lna_5g; 1524 u8 pa_type_2g; 1525 u8 pa_type_5g; 1526 u8 gpa_type; 1527 u8 apa_type; 1528 bool ext_pa_2g; 1529 bool ext_pa_5g; 1530 1531 bool btcoex; 1532 /* bt share antenna with wifi */ 1533 bool share_ant; 1534 u8 bt_setting; 1535 1536 struct { 1537 u8 hci; 1538 u8 bw; 1539 u8 ptcl; 1540 u8 nss; 1541 u8 ant_num; 1542 } hw_cap; 1543 1544 struct rtw_txpwr_idx txpwr_idx_table[4]; 1545 }; 1546 1547 struct rtw_phy_cond { 1548 #ifdef __LITTLE_ENDIAN 1549 u32 rfe:8; 1550 u32 intf:4; 1551 u32 pkg:4; 1552 u32 plat:4; 1553 u32 intf_rsvd:4; 1554 u32 cut:4; 1555 u32 branch:2; 1556 u32 neg:1; 1557 u32 pos:1; 1558 #else 1559 u32 pos:1; 1560 u32 neg:1; 1561 u32 branch:2; 1562 u32 cut:4; 1563 u32 intf_rsvd:4; 1564 u32 plat:4; 1565 u32 pkg:4; 1566 u32 intf:4; 1567 u32 rfe:8; 1568 #endif 1569 /* for intf:4 */ 1570 #define INTF_PCIE BIT(0) 1571 #define INTF_USB BIT(1) 1572 #define INTF_SDIO BIT(2) 1573 /* for branch:2 */ 1574 #define BRANCH_IF 0 1575 #define BRANCH_ELIF 1 1576 #define BRANCH_ELSE 2 1577 #define BRANCH_ENDIF 3 1578 }; 1579 1580 struct rtw_fifo_conf { 1581 /* tx fifo information */ 1582 u16 rsvd_boundary; 1583 u16 rsvd_pg_num; 1584 u16 rsvd_drv_pg_num; 1585 u16 txff_pg_num; 1586 u16 acq_pg_num; 1587 u16 rsvd_drv_addr; 1588 u16 rsvd_h2c_info_addr; 1589 u16 rsvd_h2c_sta_info_addr; 1590 u16 rsvd_h2cq_addr; 1591 u16 rsvd_cpu_instr_addr; 1592 u16 rsvd_fw_txbuf_addr; 1593 u16 rsvd_csibuf_addr; 1594 const struct rtw_rqpn *rqpn; 1595 }; 1596 1597 struct rtw_fw_state { 1598 const struct firmware *firmware; 1599 struct rtw_dev *rtwdev; 1600 struct completion completion; 1601 u16 version; 1602 u8 sub_version; 1603 u8 sub_index; 1604 u16 h2c_version; 1605 }; 1606 1607 struct rtw_hal { 1608 u32 rcr; 1609 1610 u32 chip_version; 1611 u8 cut_version; 1612 u8 mp_chip; 1613 u8 oem_id; 1614 struct rtw_phy_cond phy_cond; 1615 1616 u8 ps_mode; 1617 u8 current_channel; 1618 u8 current_band_width; 1619 u8 current_band_type; 1620 1621 /* center channel for different available bandwidth, 1622 * val of (bw > current_band_width) is invalid 1623 */ 1624 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1625 1626 u8 sec_ch_offset; 1627 u8 rf_type; 1628 u8 rf_path_num; 1629 u8 rf_phy_num; 1630 u32 antenna_tx; 1631 u32 antenna_rx; 1632 u8 bfee_sts_cap; 1633 1634 /* protect tx power section */ 1635 struct mutex tx_power_mutex; 1636 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1637 [DESC_RATE_MAX]; 1638 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1639 [DESC_RATE_MAX]; 1640 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1641 [RTW_RATE_SECTION_MAX]; 1642 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1643 [RTW_RATE_SECTION_MAX]; 1644 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1645 [RTW_CHANNEL_WIDTH_MAX] 1646 [RTW_RATE_SECTION_MAX] 1647 [RTW_MAX_CHANNEL_NUM_2G]; 1648 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1649 [RTW_CHANNEL_WIDTH_MAX] 1650 [RTW_RATE_SECTION_MAX] 1651 [RTW_MAX_CHANNEL_NUM_5G]; 1652 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1653 [DESC_RATE_MAX]; 1654 }; 1655 1656 struct rtw_dev { 1657 struct ieee80211_hw *hw; 1658 struct device *dev; 1659 1660 struct rtw_hci hci; 1661 1662 struct rtw_chip_info *chip; 1663 struct rtw_hal hal; 1664 struct rtw_fifo_conf fifo; 1665 struct rtw_fw_state fw; 1666 struct rtw_efuse efuse; 1667 struct rtw_sec_desc sec; 1668 struct rtw_traffic_stats stats; 1669 struct rtw_regulatory regd; 1670 struct rtw_bf_info bf_info; 1671 1672 struct rtw_dm_info dm_info; 1673 struct rtw_coex coex; 1674 1675 /* ensures exclusive access from mac80211 callbacks */ 1676 struct mutex mutex; 1677 1678 /* read/write rf register */ 1679 spinlock_t rf_lock; 1680 1681 /* watch dog every 2 sec */ 1682 struct delayed_work watch_dog_work; 1683 u32 watch_dog_cnt; 1684 1685 struct list_head rsvd_page_list; 1686 1687 /* c2h cmd queue & handler work */ 1688 struct sk_buff_head c2h_queue; 1689 struct work_struct c2h_work; 1690 1691 /* used to protect txqs list */ 1692 spinlock_t txq_lock; 1693 struct list_head txqs; 1694 struct tasklet_struct tx_tasklet; 1695 struct work_struct ba_work; 1696 1697 struct rtw_tx_report tx_report; 1698 1699 struct { 1700 /* incicate the mail box to use with fw */ 1701 u8 last_box_num; 1702 /* protect to send h2c to fw */ 1703 spinlock_t lock; 1704 u32 seq; 1705 } h2c; 1706 1707 /* lps power state & handler work */ 1708 struct rtw_lps_conf lps_conf; 1709 bool ps_enabled; 1710 1711 struct dentry *debugfs; 1712 1713 u8 sta_cnt; 1714 u32 rts_threshold; 1715 1716 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1717 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1718 1719 u8 mp_mode; 1720 1721 struct rtw_fw_state wow_fw; 1722 struct rtw_wow_param wow; 1723 1724 /* hci related data, must be last */ 1725 u8 priv[] __aligned(sizeof(void *)); 1726 }; 1727 1728 #include "hci.h" 1729 1730 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1731 { 1732 return !!rtwdev->sta_cnt; 1733 } 1734 1735 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1736 { 1737 void *p = rtwtxq; 1738 1739 return container_of(p, struct ieee80211_txq, drv_priv); 1740 } 1741 1742 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1743 { 1744 void *p = rtwvif; 1745 1746 return container_of(p, struct ieee80211_vif, drv_priv); 1747 } 1748 1749 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1750 struct cfg80211_ssid *b) 1751 { 1752 if (!a || !b || a->ssid_len != b->ssid_len) 1753 return false; 1754 1755 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1756 return false; 1757 1758 return true; 1759 } 1760 1761 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 1762 { 1763 if (rtwdev->chip->ops->efuse_grant) 1764 rtwdev->chip->ops->efuse_grant(rtwdev, true); 1765 } 1766 1767 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 1768 { 1769 if (rtwdev->chip->ops->efuse_grant) 1770 rtwdev->chip->ops->efuse_grant(rtwdev, false); 1771 } 1772 1773 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 1774 { 1775 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 1776 } 1777 1778 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 1779 { 1780 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 1781 } 1782 1783 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 1784 { 1785 return rtwdev->chip->rx_ldpc; 1786 } 1787 1788 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1789 struct rtw_channel_params *ch_param); 1790 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1791 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1792 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1793 void rtw_restore_reg(struct rtw_dev *rtwdev, 1794 struct rtw_backup_info *bckp, u32 num); 1795 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1796 void rtw_set_channel(struct rtw_dev *rtwdev); 1797 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1798 u32 config); 1799 void rtw_tx_report_purge_timer(struct timer_list *t); 1800 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1801 int rtw_core_start(struct rtw_dev *rtwdev); 1802 void rtw_core_stop(struct rtw_dev *rtwdev); 1803 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1804 int rtw_core_init(struct rtw_dev *rtwdev); 1805 void rtw_core_deinit(struct rtw_dev *rtwdev); 1806 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1807 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1808 u16 rtw_desc_to_bitrate(u8 desc_rate); 1809 1810 #endif 1811