1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 17 #include "util.h" 18 19 #define RTW_MAX_MAC_ID_NUM 32 20 #define RTW_MAX_SEC_CAM_NUM 32 21 #define MAX_PG_CAM_BACKUP_NUM 8 22 23 #define RTW_MAX_PATTERN_NUM 12 24 #define RTW_MAX_PATTERN_MASK_SIZE 16 25 #define RTW_MAX_PATTERN_SIZE 128 26 27 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 28 29 #define RFREG_MASK 0xfffff 30 #define INV_RF_DATA 0xffffffff 31 #define TX_PAGE_SIZE_SHIFT 7 32 33 #define RTW_CHANNEL_WIDTH_MAX 3 34 #define RTW_RF_PATH_MAX 4 35 #define HW_FEATURE_LEN 13 36 37 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 38 39 extern bool rtw_bf_support; 40 extern unsigned int rtw_fw_lps_deep_mode; 41 extern unsigned int rtw_debug_mask; 42 extern const struct ieee80211_ops rtw_ops; 43 44 #define RTW_MAX_CHANNEL_NUM_2G 14 45 #define RTW_MAX_CHANNEL_NUM_5G 49 46 47 struct rtw_dev; 48 49 enum rtw_hci_type { 50 RTW_HCI_TYPE_PCIE, 51 RTW_HCI_TYPE_USB, 52 RTW_HCI_TYPE_SDIO, 53 54 RTW_HCI_TYPE_UNDEFINE, 55 }; 56 57 struct rtw_hci { 58 struct rtw_hci_ops *ops; 59 enum rtw_hci_type type; 60 61 u32 rpwm_addr; 62 u32 cpwm_addr; 63 64 u8 bulkout_num; 65 }; 66 67 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 68 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 69 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 70 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 71 72 #define IS_CH_5G_BAND_MID(channel) \ 73 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 74 75 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 76 #define IS_CH_5G_BAND(channel) \ 77 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 78 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 79 80 enum rtw_supported_band { 81 RTW_BAND_2G = 1 << 0, 82 RTW_BAND_5G = 1 << 1, 83 RTW_BAND_60G = 1 << 2, 84 85 RTW_BAND_MAX, 86 }; 87 88 /* now, support upto 80M bw */ 89 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 90 91 enum rtw_bandwidth { 92 RTW_CHANNEL_WIDTH_20 = 0, 93 RTW_CHANNEL_WIDTH_40 = 1, 94 RTW_CHANNEL_WIDTH_80 = 2, 95 RTW_CHANNEL_WIDTH_160 = 3, 96 RTW_CHANNEL_WIDTH_80_80 = 4, 97 RTW_CHANNEL_WIDTH_5 = 5, 98 RTW_CHANNEL_WIDTH_10 = 6, 99 }; 100 101 enum rtw_sc_offset { 102 RTW_SC_DONT_CARE = 0, 103 RTW_SC_20_UPPER = 1, 104 RTW_SC_20_LOWER = 2, 105 RTW_SC_20_UPMOST = 3, 106 RTW_SC_20_LOWEST = 4, 107 RTW_SC_40_UPPER = 9, 108 RTW_SC_40_LOWER = 10, 109 }; 110 111 enum rtw_net_type { 112 RTW_NET_NO_LINK = 0, 113 RTW_NET_AD_HOC = 1, 114 RTW_NET_MGD_LINKED = 2, 115 RTW_NET_AP_MODE = 3, 116 }; 117 118 enum rtw_rf_type { 119 RF_1T1R = 0, 120 RF_1T2R = 1, 121 RF_2T2R = 2, 122 RF_2T3R = 3, 123 RF_2T4R = 4, 124 RF_3T3R = 5, 125 RF_3T4R = 6, 126 RF_4T4R = 7, 127 RF_TYPE_MAX, 128 }; 129 130 enum rtw_rf_path { 131 RF_PATH_A = 0, 132 RF_PATH_B = 1, 133 RF_PATH_C = 2, 134 RF_PATH_D = 3, 135 }; 136 137 enum rtw_bb_path { 138 BB_PATH_A = BIT(0), 139 BB_PATH_B = BIT(1), 140 BB_PATH_C = BIT(2), 141 BB_PATH_D = BIT(3), 142 143 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 144 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 145 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 146 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 147 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 148 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 149 150 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 151 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 152 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 153 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 154 155 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 156 }; 157 158 enum rtw_rate_section { 159 RTW_RATE_SECTION_CCK = 0, 160 RTW_RATE_SECTION_OFDM, 161 RTW_RATE_SECTION_HT_1S, 162 RTW_RATE_SECTION_HT_2S, 163 RTW_RATE_SECTION_VHT_1S, 164 RTW_RATE_SECTION_VHT_2S, 165 166 /* keep last */ 167 RTW_RATE_SECTION_MAX, 168 }; 169 170 enum rtw_wireless_set { 171 WIRELESS_CCK = 0x00000001, 172 WIRELESS_OFDM = 0x00000002, 173 WIRELESS_HT = 0x00000004, 174 WIRELESS_VHT = 0x00000008, 175 }; 176 177 #define HT_STBC_EN BIT(0) 178 #define VHT_STBC_EN BIT(1) 179 #define HT_LDPC_EN BIT(0) 180 #define VHT_LDPC_EN BIT(1) 181 182 enum rtw_chip_type { 183 RTW_CHIP_TYPE_8822B, 184 RTW_CHIP_TYPE_8822C, 185 RTW_CHIP_TYPE_8723D, 186 }; 187 188 enum rtw_tx_queue_type { 189 /* the order of AC queues matters */ 190 RTW_TX_QUEUE_BK = 0x0, 191 RTW_TX_QUEUE_BE = 0x1, 192 RTW_TX_QUEUE_VI = 0x2, 193 RTW_TX_QUEUE_VO = 0x3, 194 195 RTW_TX_QUEUE_BCN = 0x4, 196 RTW_TX_QUEUE_MGMT = 0x5, 197 RTW_TX_QUEUE_HI0 = 0x6, 198 RTW_TX_QUEUE_H2C = 0x7, 199 /* keep it last */ 200 RTK_MAX_TX_QUEUE_NUM 201 }; 202 203 enum rtw_rx_queue_type { 204 RTW_RX_QUEUE_MPDU = 0x0, 205 RTW_RX_QUEUE_C2H = 0x1, 206 /* keep it last */ 207 RTK_MAX_RX_QUEUE_NUM 208 }; 209 210 enum rtw_fw_type { 211 RTW_NORMAL_FW = 0x0, 212 RTW_WOWLAN_FW = 0x1, 213 }; 214 215 enum rtw_rate_index { 216 RTW_RATEID_BGN_40M_2SS = 0, 217 RTW_RATEID_BGN_40M_1SS = 1, 218 RTW_RATEID_BGN_20M_2SS = 2, 219 RTW_RATEID_BGN_20M_1SS = 3, 220 RTW_RATEID_GN_N2SS = 4, 221 RTW_RATEID_GN_N1SS = 5, 222 RTW_RATEID_BG = 6, 223 RTW_RATEID_G = 7, 224 RTW_RATEID_B_20M = 8, 225 RTW_RATEID_ARFR0_AC_2SS = 9, 226 RTW_RATEID_ARFR1_AC_1SS = 10, 227 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 228 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 229 RTW_RATEID_ARFR4_AC_3SS = 13, 230 RTW_RATEID_ARFR5_N_3SS = 14, 231 RTW_RATEID_ARFR7_N_4SS = 15, 232 RTW_RATEID_ARFR6_AC_4SS = 16 233 }; 234 235 enum rtw_trx_desc_rate { 236 DESC_RATE1M = 0x00, 237 DESC_RATE2M = 0x01, 238 DESC_RATE5_5M = 0x02, 239 DESC_RATE11M = 0x03, 240 241 DESC_RATE6M = 0x04, 242 DESC_RATE9M = 0x05, 243 DESC_RATE12M = 0x06, 244 DESC_RATE18M = 0x07, 245 DESC_RATE24M = 0x08, 246 DESC_RATE36M = 0x09, 247 DESC_RATE48M = 0x0a, 248 DESC_RATE54M = 0x0b, 249 250 DESC_RATEMCS0 = 0x0c, 251 DESC_RATEMCS1 = 0x0d, 252 DESC_RATEMCS2 = 0x0e, 253 DESC_RATEMCS3 = 0x0f, 254 DESC_RATEMCS4 = 0x10, 255 DESC_RATEMCS5 = 0x11, 256 DESC_RATEMCS6 = 0x12, 257 DESC_RATEMCS7 = 0x13, 258 DESC_RATEMCS8 = 0x14, 259 DESC_RATEMCS9 = 0x15, 260 DESC_RATEMCS10 = 0x16, 261 DESC_RATEMCS11 = 0x17, 262 DESC_RATEMCS12 = 0x18, 263 DESC_RATEMCS13 = 0x19, 264 DESC_RATEMCS14 = 0x1a, 265 DESC_RATEMCS15 = 0x1b, 266 DESC_RATEMCS16 = 0x1c, 267 DESC_RATEMCS17 = 0x1d, 268 DESC_RATEMCS18 = 0x1e, 269 DESC_RATEMCS19 = 0x1f, 270 DESC_RATEMCS20 = 0x20, 271 DESC_RATEMCS21 = 0x21, 272 DESC_RATEMCS22 = 0x22, 273 DESC_RATEMCS23 = 0x23, 274 DESC_RATEMCS24 = 0x24, 275 DESC_RATEMCS25 = 0x25, 276 DESC_RATEMCS26 = 0x26, 277 DESC_RATEMCS27 = 0x27, 278 DESC_RATEMCS28 = 0x28, 279 DESC_RATEMCS29 = 0x29, 280 DESC_RATEMCS30 = 0x2a, 281 DESC_RATEMCS31 = 0x2b, 282 283 DESC_RATEVHT1SS_MCS0 = 0x2c, 284 DESC_RATEVHT1SS_MCS1 = 0x2d, 285 DESC_RATEVHT1SS_MCS2 = 0x2e, 286 DESC_RATEVHT1SS_MCS3 = 0x2f, 287 DESC_RATEVHT1SS_MCS4 = 0x30, 288 DESC_RATEVHT1SS_MCS5 = 0x31, 289 DESC_RATEVHT1SS_MCS6 = 0x32, 290 DESC_RATEVHT1SS_MCS7 = 0x33, 291 DESC_RATEVHT1SS_MCS8 = 0x34, 292 DESC_RATEVHT1SS_MCS9 = 0x35, 293 294 DESC_RATEVHT2SS_MCS0 = 0x36, 295 DESC_RATEVHT2SS_MCS1 = 0x37, 296 DESC_RATEVHT2SS_MCS2 = 0x38, 297 DESC_RATEVHT2SS_MCS3 = 0x39, 298 DESC_RATEVHT2SS_MCS4 = 0x3a, 299 DESC_RATEVHT2SS_MCS5 = 0x3b, 300 DESC_RATEVHT2SS_MCS6 = 0x3c, 301 DESC_RATEVHT2SS_MCS7 = 0x3d, 302 DESC_RATEVHT2SS_MCS8 = 0x3e, 303 DESC_RATEVHT2SS_MCS9 = 0x3f, 304 305 DESC_RATEVHT3SS_MCS0 = 0x40, 306 DESC_RATEVHT3SS_MCS1 = 0x41, 307 DESC_RATEVHT3SS_MCS2 = 0x42, 308 DESC_RATEVHT3SS_MCS3 = 0x43, 309 DESC_RATEVHT3SS_MCS4 = 0x44, 310 DESC_RATEVHT3SS_MCS5 = 0x45, 311 DESC_RATEVHT3SS_MCS6 = 0x46, 312 DESC_RATEVHT3SS_MCS7 = 0x47, 313 DESC_RATEVHT3SS_MCS8 = 0x48, 314 DESC_RATEVHT3SS_MCS9 = 0x49, 315 316 DESC_RATEVHT4SS_MCS0 = 0x4a, 317 DESC_RATEVHT4SS_MCS1 = 0x4b, 318 DESC_RATEVHT4SS_MCS2 = 0x4c, 319 DESC_RATEVHT4SS_MCS3 = 0x4d, 320 DESC_RATEVHT4SS_MCS4 = 0x4e, 321 DESC_RATEVHT4SS_MCS5 = 0x4f, 322 DESC_RATEVHT4SS_MCS6 = 0x50, 323 DESC_RATEVHT4SS_MCS7 = 0x51, 324 DESC_RATEVHT4SS_MCS8 = 0x52, 325 DESC_RATEVHT4SS_MCS9 = 0x53, 326 327 DESC_RATE_MAX, 328 }; 329 330 enum rtw_regulatory_domains { 331 RTW_REGD_FCC = 0, 332 RTW_REGD_MKK = 1, 333 RTW_REGD_ETSI = 2, 334 RTW_REGD_IC = 3, 335 RTW_REGD_KCC = 4, 336 RTW_REGD_ACMA = 5, 337 RTW_REGD_CHILE = 6, 338 RTW_REGD_UKRAINE = 7, 339 RTW_REGD_MEXICO = 8, 340 RTW_REGD_CN = 9, 341 RTW_REGD_WW, 342 343 RTW_REGD_MAX 344 }; 345 346 enum rtw_txq_flags { 347 RTW_TXQ_AMPDU, 348 RTW_TXQ_BLOCK_BA, 349 }; 350 351 enum rtw_flags { 352 RTW_FLAG_RUNNING, 353 RTW_FLAG_FW_RUNNING, 354 RTW_FLAG_SCANNING, 355 RTW_FLAG_INACTIVE_PS, 356 RTW_FLAG_LEISURE_PS, 357 RTW_FLAG_LEISURE_PS_DEEP, 358 RTW_FLAG_DIG_DISABLE, 359 RTW_FLAG_BUSY_TRAFFIC, 360 RTW_FLAG_WOWLAN, 361 362 NUM_OF_RTW_FLAGS, 363 }; 364 365 enum rtw_evm { 366 RTW_EVM_OFDM = 0, 367 RTW_EVM_1SS, 368 RTW_EVM_2SS_A, 369 RTW_EVM_2SS_B, 370 /* keep it last */ 371 RTW_EVM_NUM 372 }; 373 374 enum rtw_snr { 375 RTW_SNR_OFDM_A = 0, 376 RTW_SNR_OFDM_B, 377 RTW_SNR_OFDM_C, 378 RTW_SNR_OFDM_D, 379 RTW_SNR_1SS_A, 380 RTW_SNR_1SS_B, 381 RTW_SNR_1SS_C, 382 RTW_SNR_1SS_D, 383 RTW_SNR_2SS_A, 384 RTW_SNR_2SS_B, 385 RTW_SNR_2SS_C, 386 RTW_SNR_2SS_D, 387 /* keep it last */ 388 RTW_SNR_NUM 389 }; 390 391 enum rtw_wow_flags { 392 RTW_WOW_FLAG_EN_MAGIC_PKT, 393 RTW_WOW_FLAG_EN_REKEY_PKT, 394 RTW_WOW_FLAG_EN_DISCONNECT, 395 396 /* keep it last */ 397 RTW_WOW_FLAG_MAX, 398 }; 399 400 /* the power index is represented by differences, which cck-1s & ht40-1s are 401 * the base values, so for 1s's differences, there are only ht20 & ofdm 402 */ 403 struct rtw_2g_1s_pwr_idx_diff { 404 #ifdef __LITTLE_ENDIAN 405 s8 ofdm:4; 406 s8 bw20:4; 407 #else 408 s8 bw20:4; 409 s8 ofdm:4; 410 #endif 411 } __packed; 412 413 struct rtw_2g_ns_pwr_idx_diff { 414 #ifdef __LITTLE_ENDIAN 415 s8 bw20:4; 416 s8 bw40:4; 417 s8 cck:4; 418 s8 ofdm:4; 419 #else 420 s8 ofdm:4; 421 s8 cck:4; 422 s8 bw40:4; 423 s8 bw20:4; 424 #endif 425 } __packed; 426 427 struct rtw_2g_txpwr_idx { 428 u8 cck_base[6]; 429 u8 bw40_base[5]; 430 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 431 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 432 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 433 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 434 }; 435 436 struct rtw_5g_ht_1s_pwr_idx_diff { 437 #ifdef __LITTLE_ENDIAN 438 s8 ofdm:4; 439 s8 bw20:4; 440 #else 441 s8 bw20:4; 442 s8 ofdm:4; 443 #endif 444 } __packed; 445 446 struct rtw_5g_ht_ns_pwr_idx_diff { 447 #ifdef __LITTLE_ENDIAN 448 s8 bw20:4; 449 s8 bw40:4; 450 #else 451 s8 bw40:4; 452 s8 bw20:4; 453 #endif 454 } __packed; 455 456 struct rtw_5g_ofdm_ns_pwr_idx_diff { 457 #ifdef __LITTLE_ENDIAN 458 s8 ofdm_3s:4; 459 s8 ofdm_2s:4; 460 s8 ofdm_4s:4; 461 s8 res:4; 462 #else 463 s8 res:4; 464 s8 ofdm_4s:4; 465 s8 ofdm_2s:4; 466 s8 ofdm_3s:4; 467 #endif 468 } __packed; 469 470 struct rtw_5g_vht_ns_pwr_idx_diff { 471 #ifdef __LITTLE_ENDIAN 472 s8 bw160:4; 473 s8 bw80:4; 474 #else 475 s8 bw80:4; 476 s8 bw160:4; 477 #endif 478 } __packed; 479 480 struct rtw_5g_txpwr_idx { 481 u8 bw40_base[14]; 482 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 483 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 484 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 485 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 486 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 487 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 488 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 489 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 490 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 491 }; 492 493 struct rtw_txpwr_idx { 494 struct rtw_2g_txpwr_idx pwr_idx_2g; 495 struct rtw_5g_txpwr_idx pwr_idx_5g; 496 }; 497 498 struct rtw_timer_list { 499 struct timer_list timer; 500 void (*function)(void *data); 501 void *args; 502 }; 503 504 struct rtw_channel_params { 505 u8 center_chan; 506 u8 bandwidth; 507 u8 primary_chan_idx; 508 /* center channel by different available bandwidth, 509 * val of (bw > current bandwidth) is invalid 510 */ 511 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 512 }; 513 514 struct rtw_hw_reg { 515 u32 addr; 516 u32 mask; 517 }; 518 519 struct rtw_ltecoex_addr { 520 u32 ctrl; 521 u32 wdata; 522 u32 rdata; 523 }; 524 525 struct rtw_reg_domain { 526 u32 addr; 527 u32 mask; 528 #define RTW_REG_DOMAIN_MAC32 0 529 #define RTW_REG_DOMAIN_MAC16 1 530 #define RTW_REG_DOMAIN_MAC8 2 531 #define RTW_REG_DOMAIN_RF_A 3 532 #define RTW_REG_DOMAIN_RF_B 4 533 #define RTW_REG_DOMAIN_NL 0xFF 534 u8 domain; 535 }; 536 537 struct rtw_rf_sipi_addr { 538 u32 hssi_1; 539 u32 hssi_2; 540 u32 lssi_read; 541 u32 lssi_read_pi; 542 }; 543 544 struct rtw_backup_info { 545 u8 len; 546 u32 reg; 547 u32 val; 548 }; 549 550 enum rtw_vif_port_set { 551 PORT_SET_MAC_ADDR = BIT(0), 552 PORT_SET_BSSID = BIT(1), 553 PORT_SET_NET_TYPE = BIT(2), 554 PORT_SET_AID = BIT(3), 555 PORT_SET_BCN_CTRL = BIT(4), 556 }; 557 558 struct rtw_vif_port { 559 struct rtw_hw_reg mac_addr; 560 struct rtw_hw_reg bssid; 561 struct rtw_hw_reg net_type; 562 struct rtw_hw_reg aid; 563 struct rtw_hw_reg bcn_ctrl; 564 }; 565 566 struct rtw_tx_pkt_info { 567 u32 tx_pkt_size; 568 u8 offset; 569 u8 pkt_offset; 570 u8 mac_id; 571 u8 rate_id; 572 u8 rate; 573 u8 qsel; 574 u8 bw; 575 u8 sec_type; 576 u8 sn; 577 bool ampdu_en; 578 u8 ampdu_factor; 579 u8 ampdu_density; 580 u16 seq; 581 bool stbc; 582 bool ldpc; 583 bool dis_rate_fallback; 584 bool bmc; 585 bool use_rate; 586 bool ls; 587 bool fs; 588 bool short_gi; 589 bool report; 590 bool rts; 591 bool dis_qselseq; 592 bool en_hwseq; 593 u8 hw_ssn_sel; 594 }; 595 596 struct rtw_rx_pkt_stat { 597 bool phy_status; 598 bool icv_err; 599 bool crc_err; 600 bool decrypted; 601 bool is_c2h; 602 603 s32 signal_power; 604 u16 pkt_len; 605 u8 bw; 606 u8 drv_info_sz; 607 u8 shift; 608 u8 rate; 609 u8 mac_id; 610 u8 cam_id; 611 u8 ppdu_cnt; 612 u32 tsf_low; 613 s8 rx_power[RTW_RF_PATH_MAX]; 614 u8 rssi; 615 u8 rxsc; 616 s8 rx_snr[RTW_RF_PATH_MAX]; 617 u8 rx_evm[RTW_RF_PATH_MAX]; 618 s8 cfo_tail[RTW_RF_PATH_MAX]; 619 620 struct rtw_sta_info *si; 621 struct ieee80211_vif *vif; 622 }; 623 624 DECLARE_EWMA(tp, 10, 2); 625 626 struct rtw_traffic_stats { 627 /* units in bytes */ 628 u64 tx_unicast; 629 u64 rx_unicast; 630 631 /* count for packets */ 632 u64 tx_cnt; 633 u64 rx_cnt; 634 635 /* units in Mbps */ 636 u32 tx_throughput; 637 u32 rx_throughput; 638 struct ewma_tp tx_ewma_tp; 639 struct ewma_tp rx_ewma_tp; 640 }; 641 642 enum rtw_lps_mode { 643 RTW_MODE_ACTIVE = 0, 644 RTW_MODE_LPS = 1, 645 RTW_MODE_WMM_PS = 2, 646 }; 647 648 enum rtw_lps_deep_mode { 649 LPS_DEEP_MODE_NONE = 0, 650 LPS_DEEP_MODE_LCLK = 1, 651 LPS_DEEP_MODE_PG = 2, 652 }; 653 654 enum rtw_pwr_state { 655 RTW_RF_OFF = 0x0, 656 RTW_RF_ON = 0x4, 657 RTW_ALL_ON = 0xc, 658 }; 659 660 struct rtw_lps_conf { 661 enum rtw_lps_mode mode; 662 enum rtw_lps_deep_mode deep_mode; 663 enum rtw_pwr_state state; 664 u8 awake_interval; 665 u8 rlbm; 666 u8 smart_ps; 667 u8 port_id; 668 bool sec_cam_backup; 669 bool pattern_cam_backup; 670 }; 671 672 enum rtw_hw_key_type { 673 RTW_CAM_NONE = 0, 674 RTW_CAM_WEP40 = 1, 675 RTW_CAM_TKIP = 2, 676 RTW_CAM_AES = 4, 677 RTW_CAM_WEP104 = 5, 678 }; 679 680 struct rtw_cam_entry { 681 bool valid; 682 bool group; 683 u8 addr[ETH_ALEN]; 684 u8 hw_key_type; 685 struct ieee80211_key_conf *key; 686 }; 687 688 struct rtw_sec_desc { 689 /* search strategy */ 690 bool default_key_search; 691 692 u32 total_cam_num; 693 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 694 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 695 }; 696 697 struct rtw_tx_report { 698 /* protect the tx report queue */ 699 spinlock_t q_lock; 700 struct sk_buff_head queue; 701 atomic_t sn; 702 struct timer_list purge_timer; 703 }; 704 705 struct rtw_ra_report { 706 struct rate_info txrate; 707 u32 bit_rate; 708 u8 desc_rate; 709 }; 710 711 struct rtw_txq { 712 struct list_head list; 713 714 unsigned long flags; 715 unsigned long last_push; 716 }; 717 718 #define RTW_BC_MC_MACID 1 719 DECLARE_EWMA(rssi, 10, 16); 720 721 struct rtw_sta_info { 722 struct ieee80211_sta *sta; 723 struct ieee80211_vif *vif; 724 725 struct ewma_rssi avg_rssi; 726 u8 rssi_level; 727 728 u8 mac_id; 729 u8 rate_id; 730 enum rtw_bandwidth bw_mode; 731 enum rtw_rf_type rf_type; 732 enum rtw_wireless_set wireless_set; 733 u8 stbc_en:2; 734 u8 ldpc_en:2; 735 bool sgi_enable; 736 bool vht_enable; 737 bool updated; 738 u8 init_ra_lv; 739 u64 ra_mask; 740 741 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 742 743 struct rtw_ra_report ra_report; 744 745 bool use_cfg_mask; 746 struct cfg80211_bitrate_mask *mask; 747 }; 748 749 enum rtw_bfee_role { 750 RTW_BFEE_NONE, 751 RTW_BFEE_SU, 752 RTW_BFEE_MU 753 }; 754 755 struct rtw_bfee { 756 enum rtw_bfee_role role; 757 758 u16 p_aid; 759 u8 g_id; 760 u8 mac_addr[ETH_ALEN]; 761 u8 sound_dim; 762 763 /* SU-MIMO */ 764 u8 su_reg_index; 765 766 /* MU-MIMO */ 767 u16 aid; 768 }; 769 770 struct rtw_bf_info { 771 u8 bfer_mu_cnt; 772 u8 bfer_su_cnt; 773 DECLARE_BITMAP(bfer_su_reg_maping, 2); 774 u8 cur_csi_rpt_rate; 775 }; 776 777 struct rtw_vif { 778 enum rtw_net_type net_type; 779 u16 aid; 780 u8 mac_addr[ETH_ALEN]; 781 u8 bssid[ETH_ALEN]; 782 u8 port; 783 u8 bcn_ctrl; 784 struct list_head rsvd_page_list; 785 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 786 const struct rtw_vif_port *conf; 787 788 struct rtw_traffic_stats stats; 789 790 struct rtw_bfee bfee; 791 }; 792 793 struct rtw_regulatory { 794 char alpha2[2]; 795 u8 chplan; 796 u8 txpwr_regd; 797 }; 798 799 struct rtw_chip_ops { 800 int (*mac_init)(struct rtw_dev *rtwdev); 801 void (*shutdown)(struct rtw_dev *rtwdev); 802 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 803 void (*phy_set_param)(struct rtw_dev *rtwdev); 804 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 805 u8 bandwidth, u8 primary_chan_idx); 806 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 807 struct rtw_rx_pkt_stat *pkt_stat, 808 struct ieee80211_rx_status *rx_status); 809 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 810 u32 addr, u32 mask); 811 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 812 u32 addr, u32 mask, u32 data); 813 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 814 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 815 u32 size); 816 int (*set_antenna)(struct rtw_dev *rtwdev, 817 u32 antenna_tx, 818 u32 antenna_rx); 819 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 820 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 821 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 822 void (*phy_calibration)(struct rtw_dev *rtwdev); 823 void (*dpk_track)(struct rtw_dev *rtwdev); 824 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 825 void (*pwr_track)(struct rtw_dev *rtwdev); 826 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 827 struct rtw_bfee *bfee, bool enable); 828 void (*set_gid_table)(struct rtw_dev *rtwdev, 829 struct ieee80211_vif *vif, 830 struct ieee80211_bss_conf *conf); 831 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 832 u8 fixrate_en, u8 *new_rate); 833 834 /* for coex */ 835 void (*coex_set_init)(struct rtw_dev *rtwdev); 836 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 837 u8 ctrl_type, u8 pos_type); 838 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 839 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 840 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 841 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 842 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 843 }; 844 845 #define RTW_PWR_POLLING_CNT 20000 846 847 #define RTW_PWR_CMD_READ 0x00 848 #define RTW_PWR_CMD_WRITE 0x01 849 #define RTW_PWR_CMD_POLLING 0x02 850 #define RTW_PWR_CMD_DELAY 0x03 851 #define RTW_PWR_CMD_END 0x04 852 853 /* define the base address of each block */ 854 #define RTW_PWR_ADDR_MAC 0x00 855 #define RTW_PWR_ADDR_USB 0x01 856 #define RTW_PWR_ADDR_PCIE 0x02 857 #define RTW_PWR_ADDR_SDIO 0x03 858 859 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 860 #define RTW_PWR_INTF_USB_MSK BIT(1) 861 #define RTW_PWR_INTF_PCI_MSK BIT(2) 862 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 863 864 #define RTW_PWR_CUT_TEST_MSK BIT(0) 865 #define RTW_PWR_CUT_A_MSK BIT(1) 866 #define RTW_PWR_CUT_B_MSK BIT(2) 867 #define RTW_PWR_CUT_C_MSK BIT(3) 868 #define RTW_PWR_CUT_D_MSK BIT(4) 869 #define RTW_PWR_CUT_E_MSK BIT(5) 870 #define RTW_PWR_CUT_F_MSK BIT(6) 871 #define RTW_PWR_CUT_G_MSK BIT(7) 872 #define RTW_PWR_CUT_ALL_MSK 0xFF 873 874 enum rtw_pwr_seq_cmd_delay_unit { 875 RTW_PWR_DELAY_US, 876 RTW_PWR_DELAY_MS, 877 }; 878 879 struct rtw_pwr_seq_cmd { 880 u16 offset; 881 u8 cut_mask; 882 u8 intf_mask; 883 u8 base:4; 884 u8 cmd:4; 885 u8 mask; 886 u8 value; 887 }; 888 889 enum rtw_chip_ver { 890 RTW_CHIP_VER_CUT_A = 0x00, 891 RTW_CHIP_VER_CUT_B = 0x01, 892 RTW_CHIP_VER_CUT_C = 0x02, 893 RTW_CHIP_VER_CUT_D = 0x03, 894 RTW_CHIP_VER_CUT_E = 0x04, 895 RTW_CHIP_VER_CUT_F = 0x05, 896 RTW_CHIP_VER_CUT_G = 0x06, 897 }; 898 899 #define RTW_INTF_PHY_PLATFORM_ALL 0 900 901 enum rtw_intf_phy_cut { 902 RTW_INTF_PHY_CUT_A = BIT(0), 903 RTW_INTF_PHY_CUT_B = BIT(1), 904 RTW_INTF_PHY_CUT_C = BIT(2), 905 RTW_INTF_PHY_CUT_D = BIT(3), 906 RTW_INTF_PHY_CUT_E = BIT(4), 907 RTW_INTF_PHY_CUT_F = BIT(5), 908 RTW_INTF_PHY_CUT_G = BIT(6), 909 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 910 }; 911 912 enum rtw_ip_sel { 913 RTW_IP_SEL_PHY = 0, 914 RTW_IP_SEL_MAC = 1, 915 RTW_IP_SEL_DBI = 2, 916 917 RTW_IP_SEL_UNDEF = 0xFFFF 918 }; 919 920 enum rtw_pq_map_id { 921 RTW_PQ_MAP_VO = 0x0, 922 RTW_PQ_MAP_VI = 0x1, 923 RTW_PQ_MAP_BE = 0x2, 924 RTW_PQ_MAP_BK = 0x3, 925 RTW_PQ_MAP_MG = 0x4, 926 RTW_PQ_MAP_HI = 0x5, 927 RTW_PQ_MAP_NUM = 0x6, 928 929 RTW_PQ_MAP_UNDEF, 930 }; 931 932 enum rtw_dma_mapping { 933 RTW_DMA_MAPPING_EXTRA = 0, 934 RTW_DMA_MAPPING_LOW = 1, 935 RTW_DMA_MAPPING_NORMAL = 2, 936 RTW_DMA_MAPPING_HIGH = 3, 937 938 RTW_DMA_MAPPING_MAX, 939 RTW_DMA_MAPPING_UNDEF, 940 }; 941 942 struct rtw_rqpn { 943 enum rtw_dma_mapping dma_map_vo; 944 enum rtw_dma_mapping dma_map_vi; 945 enum rtw_dma_mapping dma_map_be; 946 enum rtw_dma_mapping dma_map_bk; 947 enum rtw_dma_mapping dma_map_mg; 948 enum rtw_dma_mapping dma_map_hi; 949 }; 950 951 struct rtw_prioq_addr { 952 u32 rsvd; 953 u32 avail; 954 }; 955 956 struct rtw_prioq_addrs { 957 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 958 bool wsize; 959 }; 960 961 struct rtw_page_table { 962 u16 hq_num; 963 u16 nq_num; 964 u16 lq_num; 965 u16 exq_num; 966 u16 gapq_num; 967 }; 968 969 struct rtw_intf_phy_para { 970 u16 offset; 971 u16 value; 972 u16 ip_sel; 973 u16 cut_mask; 974 u16 platform; 975 }; 976 977 struct rtw_wow_pattern { 978 u16 crc; 979 u8 type; 980 u8 valid; 981 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 982 }; 983 984 struct rtw_pno_request { 985 bool inited; 986 u32 match_set_cnt; 987 struct cfg80211_match_set *match_sets; 988 u8 channel_cnt; 989 struct ieee80211_channel *channels; 990 struct cfg80211_sched_scan_plan scan_plan; 991 }; 992 993 struct rtw_wow_param { 994 struct ieee80211_vif *wow_vif; 995 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 996 u8 txpause; 997 u8 pattern_cnt; 998 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 999 1000 bool ips_enabled; 1001 struct rtw_pno_request pno_req; 1002 }; 1003 1004 struct rtw_intf_phy_para_table { 1005 const struct rtw_intf_phy_para *usb2_para; 1006 const struct rtw_intf_phy_para *usb3_para; 1007 const struct rtw_intf_phy_para *gen1_para; 1008 const struct rtw_intf_phy_para *gen2_para; 1009 u8 n_usb2_para; 1010 u8 n_usb3_para; 1011 u8 n_gen1_para; 1012 u8 n_gen2_para; 1013 }; 1014 1015 struct rtw_table { 1016 const void *data; 1017 const u32 size; 1018 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1019 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1020 u32 addr, u32 data); 1021 enum rtw_rf_path rf_path; 1022 }; 1023 1024 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1025 const struct rtw_table *tbl) 1026 { 1027 (*tbl->parse)(rtwdev, tbl); 1028 } 1029 1030 enum rtw_rfe_fem { 1031 RTW_RFE_IFEM, 1032 RTW_RFE_EFEM, 1033 RTW_RFE_IFEM2G_EFEM5G, 1034 RTW_RFE_NUM, 1035 }; 1036 1037 struct rtw_rfe_def { 1038 const struct rtw_table *phy_pg_tbl; 1039 const struct rtw_table *txpwr_lmt_tbl; 1040 }; 1041 1042 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1043 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1044 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1045 } 1046 1047 #define RTW_PWR_TRK_5G_1 0 1048 #define RTW_PWR_TRK_5G_2 1 1049 #define RTW_PWR_TRK_5G_3 2 1050 #define RTW_PWR_TRK_5G_NUM 3 1051 1052 #define RTW_PWR_TRK_TBL_SZ 30 1053 1054 /* This table stores the values of TX power that will be adjusted by power 1055 * tracking. 1056 * 1057 * For 5G bands, there are 3 different settings. 1058 * For 2G there are cck rate and ofdm rate with different settings. 1059 */ 1060 struct rtw_pwr_track_tbl { 1061 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1062 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1063 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1064 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1065 const u8 *pwrtrk_2gb_n; 1066 const u8 *pwrtrk_2gb_p; 1067 const u8 *pwrtrk_2ga_n; 1068 const u8 *pwrtrk_2ga_p; 1069 const u8 *pwrtrk_2g_cckb_n; 1070 const u8 *pwrtrk_2g_cckb_p; 1071 const u8 *pwrtrk_2g_ccka_n; 1072 const u8 *pwrtrk_2g_ccka_p; 1073 const s8 *pwrtrk_xtal_n; 1074 const s8 *pwrtrk_xtal_p; 1075 }; 1076 1077 enum rtw_wlan_cpu { 1078 RTW_WCPU_11AC, 1079 RTW_WCPU_11N, 1080 }; 1081 1082 /* hardware configuration for each IC */ 1083 struct rtw_chip_info { 1084 struct rtw_chip_ops *ops; 1085 u8 id; 1086 1087 const char *fw_name; 1088 enum rtw_wlan_cpu wlan_cpu; 1089 u8 tx_pkt_desc_sz; 1090 u8 tx_buf_desc_sz; 1091 u8 rx_pkt_desc_sz; 1092 u8 rx_buf_desc_sz; 1093 u32 phy_efuse_size; 1094 u32 log_efuse_size; 1095 u32 ptct_efuse_size; 1096 u32 txff_size; 1097 u32 rxff_size; 1098 u8 band; 1099 u8 page_size; 1100 u8 csi_buf_pg_num; 1101 u8 dig_max; 1102 u8 dig_min; 1103 u8 txgi_factor; 1104 bool is_pwr_by_rate_dec; 1105 bool rx_ldpc; 1106 u8 max_power_index; 1107 1108 bool ht_supported; 1109 bool vht_supported; 1110 u8 lps_deep_mode_supported; 1111 1112 /* init values */ 1113 u8 sys_func_en; 1114 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1115 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1116 const struct rtw_rqpn *rqpn_table; 1117 const struct rtw_prioq_addrs *prioq_addrs; 1118 const struct rtw_page_table *page_table; 1119 const struct rtw_intf_phy_para_table *intf_table; 1120 1121 const struct rtw_hw_reg *dig; 1122 const struct rtw_hw_reg *dig_cck; 1123 u32 rf_base_addr[2]; 1124 u32 rf_sipi_addr[2]; 1125 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1126 u8 fix_rf_phy_num; 1127 const struct rtw_ltecoex_addr *ltecoex_addr; 1128 1129 const struct rtw_table *mac_tbl; 1130 const struct rtw_table *agc_tbl; 1131 const struct rtw_table *bb_tbl; 1132 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1133 const struct rtw_table *rfk_init_tbl; 1134 1135 const struct rtw_rfe_def *rfe_defs; 1136 u32 rfe_defs_size; 1137 1138 bool en_dis_dpd; 1139 u16 dpd_ratemask; 1140 u8 iqk_threshold; 1141 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1142 1143 u8 bfer_su_max_num; 1144 u8 bfer_mu_max_num; 1145 1146 const char *wow_fw_name; 1147 const struct wiphy_wowlan_support *wowlan_stub; 1148 const u8 max_sched_scan_ssids; 1149 1150 /* coex paras */ 1151 u32 coex_para_ver; 1152 u8 bt_desired_ver; 1153 bool scbd_support; 1154 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1155 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1156 u8 bt_rssi_type; 1157 u8 ant_isolation; 1158 u8 rssi_tolerance; 1159 u8 table_sant_num; 1160 u8 table_nsant_num; 1161 u8 tdma_sant_num; 1162 u8 tdma_nsant_num; 1163 u8 bt_afh_span_bw20; 1164 u8 bt_afh_span_bw40; 1165 u8 afh_5g_num; 1166 u8 wl_rf_para_num; 1167 u8 coex_info_hw_regs_num; 1168 const u8 *bt_rssi_step; 1169 const u8 *wl_rssi_step; 1170 const struct coex_table_para *table_nsant; 1171 const struct coex_table_para *table_sant; 1172 const struct coex_tdma_para *tdma_sant; 1173 const struct coex_tdma_para *tdma_nsant; 1174 const struct coex_rf_para *wl_rf_para_tx; 1175 const struct coex_rf_para *wl_rf_para_rx; 1176 const struct coex_5g_afh_map *afh_5g; 1177 const struct rtw_hw_reg *btg_reg; 1178 const struct rtw_reg_domain *coex_info_hw_regs; 1179 }; 1180 1181 enum rtw_coex_bt_state_cnt { 1182 COEX_CNT_BT_RETRY, 1183 COEX_CNT_BT_REINIT, 1184 COEX_CNT_BT_REENABLE, 1185 COEX_CNT_BT_POPEVENT, 1186 COEX_CNT_BT_SETUPLINK, 1187 COEX_CNT_BT_IGNWLANACT, 1188 COEX_CNT_BT_INQ, 1189 COEX_CNT_BT_PAGE, 1190 COEX_CNT_BT_ROLESWITCH, 1191 COEX_CNT_BT_AFHUPDATE, 1192 COEX_CNT_BT_INFOUPDATE, 1193 COEX_CNT_BT_IQK, 1194 COEX_CNT_BT_IQKFAIL, 1195 1196 COEX_CNT_BT_MAX 1197 }; 1198 1199 enum rtw_coex_wl_state_cnt { 1200 COEX_CNT_WL_CONNPKT, 1201 COEX_CNT_WL_COEXRUN, 1202 COEX_CNT_WL_NOISY0, 1203 COEX_CNT_WL_NOISY1, 1204 COEX_CNT_WL_NOISY2, 1205 COEX_CNT_WL_5MS_NOEXTEND, 1206 COEX_CNT_WL_FW_NOTIFY, 1207 1208 COEX_CNT_WL_MAX 1209 }; 1210 1211 struct rtw_coex_rfe { 1212 bool ant_switch_exist; 1213 bool ant_switch_diversity; 1214 bool ant_switch_with_bt; 1215 u8 rfe_module_type; 1216 u8 ant_switch_polarity; 1217 1218 /* true if WLG at BTG, else at WLAG */ 1219 bool wlg_at_btg; 1220 }; 1221 1222 struct rtw_coex_dm { 1223 bool cur_ps_tdma_on; 1224 bool cur_wl_rx_low_gain_en; 1225 bool ignore_wl_act; 1226 1227 u8 reason; 1228 u8 bt_rssi_state[4]; 1229 u8 wl_rssi_state[4]; 1230 u8 wl_ch_info[3]; 1231 u8 cur_ps_tdma; 1232 u8 cur_table; 1233 u8 ps_tdma_para[5]; 1234 u8 cur_bt_pwr_lvl; 1235 u8 cur_bt_lna_lvl; 1236 u8 cur_wl_pwr_lvl; 1237 u8 bt_status; 1238 u32 cur_ant_pos_type; 1239 u32 cur_switch_status; 1240 u32 setting_tdma; 1241 }; 1242 1243 #define COEX_BTINFO_SRC_WL_FW 0x0 1244 #define COEX_BTINFO_SRC_BT_RSP 0x1 1245 #define COEX_BTINFO_SRC_BT_ACT 0x2 1246 #define COEX_BTINFO_SRC_BT_IQK 0x3 1247 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1248 #define COEX_BTINFO_SRC_MAX 0x5 1249 1250 #define COEX_INFO_FTP BIT(7) 1251 #define COEX_INFO_A2DP BIT(6) 1252 #define COEX_INFO_HID BIT(5) 1253 #define COEX_INFO_SCO_BUSY BIT(4) 1254 #define COEX_INFO_ACL_BUSY BIT(3) 1255 #define COEX_INFO_INQ_PAGE BIT(2) 1256 #define COEX_INFO_SCO_ESCO BIT(1) 1257 #define COEX_INFO_CONNECTION BIT(0) 1258 #define COEX_BTINFO_LENGTH_MAX 10 1259 1260 struct rtw_coex_stat { 1261 bool bt_disabled; 1262 bool bt_disabled_pre; 1263 bool bt_link_exist; 1264 bool bt_whck_test; 1265 bool bt_inq_page; 1266 bool bt_inq; 1267 bool bt_page; 1268 bool bt_ble_voice; 1269 bool bt_ble_exist; 1270 bool bt_hfp_exist; 1271 bool bt_a2dp_exist; 1272 bool bt_hid_exist; 1273 bool bt_pan_exist; /* PAN or OPP */ 1274 bool bt_opp_exist; /* OPP only */ 1275 bool bt_acl_busy; 1276 bool bt_fix_2M; 1277 bool bt_setup_link; 1278 bool bt_multi_link; 1279 bool bt_a2dp_sink; 1280 bool bt_a2dp_active; 1281 bool bt_reenable; 1282 bool bt_ble_scan_en; 1283 bool bt_init_scan; 1284 bool bt_slave; 1285 bool bt_418_hid_exist; 1286 bool bt_mailbox_reply; 1287 1288 bool wl_under_lps; 1289 bool wl_under_ips; 1290 bool wl_hi_pri_task1; 1291 bool wl_hi_pri_task2; 1292 bool wl_force_lps_ctrl; 1293 bool wl_gl_busy; 1294 bool wl_linkscan_proc; 1295 bool wl_ps_state_fail; 1296 bool wl_tx_limit_en; 1297 bool wl_ampdu_limit_en; 1298 bool wl_connected; 1299 bool wl_slot_extend; 1300 bool wl_cck_lock; 1301 bool wl_cck_lock_pre; 1302 bool wl_cck_lock_ever; 1303 1304 u32 bt_supported_version; 1305 u32 bt_supported_feature; 1306 u32 patch_ver; 1307 u16 bt_reg_vendor_ae; 1308 u16 bt_reg_vendor_ac; 1309 s8 bt_rssi; 1310 u8 kt_ver; 1311 u8 gnt_workaround_state; 1312 u8 tdma_timer_base; 1313 u8 bt_profile_num; 1314 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1315 u8 bt_info_lb2; 1316 u8 bt_info_lb3; 1317 u8 bt_info_hb0; 1318 u8 bt_info_hb1; 1319 u8 bt_info_hb2; 1320 u8 bt_info_hb3; 1321 u8 bt_ble_scan_type; 1322 u8 bt_hid_pair_num; 1323 u8 bt_hid_slot; 1324 u8 bt_a2dp_bitpool; 1325 u8 bt_iqk_state; 1326 1327 u8 wl_noisy_level; 1328 u8 wl_fw_dbg_info[10]; 1329 u8 wl_fw_dbg_info_pre[10]; 1330 u8 wl_coex_mode; 1331 u8 ampdu_max_time; 1332 u8 wl_tput_dir; 1333 1334 u16 score_board; 1335 u16 retry_limit; 1336 1337 /* counters to record bt states */ 1338 u32 cnt_bt[COEX_CNT_BT_MAX]; 1339 1340 /* counters to record wifi states */ 1341 u32 cnt_wl[COEX_CNT_WL_MAX]; 1342 1343 u32 darfrc; 1344 u32 darfrch; 1345 }; 1346 1347 struct rtw_coex { 1348 /* protects coex info request section */ 1349 struct mutex mutex; 1350 struct sk_buff_head queue; 1351 wait_queue_head_t wait; 1352 1353 bool under_5g; 1354 bool stop_dm; 1355 bool freeze; 1356 bool freerun; 1357 bool wl_rf_off; 1358 1359 struct rtw_coex_stat stat; 1360 struct rtw_coex_dm dm; 1361 struct rtw_coex_rfe rfe; 1362 1363 struct delayed_work bt_relink_work; 1364 struct delayed_work bt_reenable_work; 1365 struct delayed_work defreeze_work; 1366 }; 1367 1368 #define DPK_RF_REG_NUM 7 1369 #define DPK_RF_PATH_NUM 2 1370 #define DPK_BB_REG_NUM 18 1371 #define DPK_CHANNEL_WIDTH_80 1 1372 1373 DECLARE_EWMA(thermal, 10, 4); 1374 1375 struct rtw_dpk_info { 1376 bool is_dpk_pwr_on; 1377 bool is_reload; 1378 1379 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1380 1381 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1382 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1383 1384 u32 gnt_control; 1385 u32 gnt_value; 1386 1387 u8 result[RTW_RF_PATH_MAX]; 1388 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1389 u32 coef[RTW_RF_PATH_MAX][20]; 1390 u16 dpk_gs[RTW_RF_PATH_MAX]; 1391 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1392 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1393 1394 u8 dpk_band; 1395 u8 dpk_ch; 1396 u8 dpk_bw; 1397 }; 1398 1399 struct rtw_phy_cck_pd_reg { 1400 u32 reg_pd; 1401 u32 mask_pd; 1402 u32 reg_cs; 1403 u32 mask_cs; 1404 }; 1405 1406 #define DACK_MSBK_BACKUP_NUM 0xf 1407 #define DACK_DCK_BACKUP_NUM 0x2 1408 1409 struct rtw_swing_table { 1410 const u8 *p[RTW_RF_PATH_MAX]; 1411 const u8 *n[RTW_RF_PATH_MAX]; 1412 }; 1413 1414 struct rtw_pkt_count { 1415 u16 num_bcn_pkt; 1416 u16 num_qry_pkt[DESC_RATE_MAX]; 1417 }; 1418 1419 DECLARE_EWMA(evm, 10, 4); 1420 DECLARE_EWMA(snr, 10, 4); 1421 1422 struct rtw_iqk_info { 1423 bool done; 1424 struct { 1425 u32 s1_x; 1426 u32 s1_y; 1427 u32 s0_x; 1428 u32 s0_y; 1429 } result; 1430 }; 1431 1432 struct rtw_dm_info { 1433 u32 cck_fa_cnt; 1434 u32 ofdm_fa_cnt; 1435 u32 total_fa_cnt; 1436 u32 cck_cca_cnt; 1437 u32 ofdm_cca_cnt; 1438 u32 total_cca_cnt; 1439 1440 u32 cck_ok_cnt; 1441 u32 cck_err_cnt; 1442 u32 ofdm_ok_cnt; 1443 u32 ofdm_err_cnt; 1444 u32 ht_ok_cnt; 1445 u32 ht_err_cnt; 1446 u32 vht_ok_cnt; 1447 u32 vht_err_cnt; 1448 1449 u8 min_rssi; 1450 u8 pre_min_rssi; 1451 u16 fa_history[4]; 1452 u8 igi_history[4]; 1453 u8 igi_bitmap; 1454 bool damping; 1455 u8 damping_cnt; 1456 u8 damping_rssi; 1457 1458 u8 cck_gi_u_bnd; 1459 u8 cck_gi_l_bnd; 1460 1461 u8 tx_rate; 1462 u8 thermal_avg[RTW_RF_PATH_MAX]; 1463 u8 thermal_meter_k; 1464 s8 delta_power_index[RTW_RF_PATH_MAX]; 1465 u8 default_ofdm_index; 1466 bool pwr_trk_triggered; 1467 bool pwr_trk_init_trigger; 1468 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1469 s8 txagc_remnant_cck; 1470 s8 txagc_remnant_ofdm; 1471 1472 /* backup dack results for each path and I/Q */ 1473 u32 dack_adck[RTW_RF_PATH_MAX]; 1474 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1475 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1476 1477 struct rtw_dpk_info dpk_info; 1478 1479 /* [bandwidth 0:20M/1:40M][number of path] */ 1480 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1481 u32 cck_fa_avg; 1482 1483 /* save the last rx phy status for debug */ 1484 s8 rx_snr[RTW_RF_PATH_MAX]; 1485 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1486 s16 cfo_tail[RTW_RF_PATH_MAX]; 1487 u8 rssi[RTW_RF_PATH_MAX]; 1488 u8 curr_rx_rate; 1489 struct rtw_pkt_count cur_pkt_count; 1490 struct rtw_pkt_count last_pkt_count; 1491 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1492 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1493 1494 struct rtw_iqk_info iqk; 1495 }; 1496 1497 struct rtw_efuse { 1498 u32 size; 1499 u32 physical_size; 1500 u32 logical_size; 1501 u32 protect_size; 1502 1503 u8 addr[ETH_ALEN]; 1504 u8 channel_plan; 1505 u8 country_code[2]; 1506 u8 rf_board_option; 1507 u8 rfe_option; 1508 u8 power_track_type; 1509 u8 thermal_meter[RTW_RF_PATH_MAX]; 1510 u8 thermal_meter_k; 1511 u8 crystal_cap; 1512 u8 ant_div_cfg; 1513 u8 ant_div_type; 1514 u8 regd; 1515 u8 afe; 1516 1517 u8 lna_type_2g; 1518 u8 lna_type_5g; 1519 u8 glna_type; 1520 u8 alna_type; 1521 bool ext_lna_2g; 1522 bool ext_lna_5g; 1523 u8 pa_type_2g; 1524 u8 pa_type_5g; 1525 u8 gpa_type; 1526 u8 apa_type; 1527 bool ext_pa_2g; 1528 bool ext_pa_5g; 1529 1530 bool btcoex; 1531 /* bt share antenna with wifi */ 1532 bool share_ant; 1533 u8 bt_setting; 1534 1535 struct { 1536 u8 hci; 1537 u8 bw; 1538 u8 ptcl; 1539 u8 nss; 1540 u8 ant_num; 1541 } hw_cap; 1542 1543 struct rtw_txpwr_idx txpwr_idx_table[4]; 1544 }; 1545 1546 struct rtw_phy_cond { 1547 #ifdef __LITTLE_ENDIAN 1548 u32 rfe:8; 1549 u32 intf:4; 1550 u32 pkg:4; 1551 u32 plat:4; 1552 u32 intf_rsvd:4; 1553 u32 cut:4; 1554 u32 branch:2; 1555 u32 neg:1; 1556 u32 pos:1; 1557 #else 1558 u32 pos:1; 1559 u32 neg:1; 1560 u32 branch:2; 1561 u32 cut:4; 1562 u32 intf_rsvd:4; 1563 u32 plat:4; 1564 u32 pkg:4; 1565 u32 intf:4; 1566 u32 rfe:8; 1567 #endif 1568 /* for intf:4 */ 1569 #define INTF_PCIE BIT(0) 1570 #define INTF_USB BIT(1) 1571 #define INTF_SDIO BIT(2) 1572 /* for branch:2 */ 1573 #define BRANCH_IF 0 1574 #define BRANCH_ELIF 1 1575 #define BRANCH_ELSE 2 1576 #define BRANCH_ENDIF 3 1577 }; 1578 1579 struct rtw_fifo_conf { 1580 /* tx fifo information */ 1581 u16 rsvd_boundary; 1582 u16 rsvd_pg_num; 1583 u16 rsvd_drv_pg_num; 1584 u16 txff_pg_num; 1585 u16 acq_pg_num; 1586 u16 rsvd_drv_addr; 1587 u16 rsvd_h2c_info_addr; 1588 u16 rsvd_h2c_sta_info_addr; 1589 u16 rsvd_h2cq_addr; 1590 u16 rsvd_cpu_instr_addr; 1591 u16 rsvd_fw_txbuf_addr; 1592 u16 rsvd_csibuf_addr; 1593 const struct rtw_rqpn *rqpn; 1594 }; 1595 1596 struct rtw_fw_state { 1597 const struct firmware *firmware; 1598 struct rtw_dev *rtwdev; 1599 struct completion completion; 1600 u16 version; 1601 u8 sub_version; 1602 u8 sub_index; 1603 u16 h2c_version; 1604 }; 1605 1606 struct rtw_hal { 1607 u32 rcr; 1608 1609 u32 chip_version; 1610 u8 cut_version; 1611 u8 mp_chip; 1612 u8 oem_id; 1613 struct rtw_phy_cond phy_cond; 1614 1615 u8 ps_mode; 1616 u8 current_channel; 1617 u8 current_band_width; 1618 u8 current_band_type; 1619 1620 /* center channel for different available bandwidth, 1621 * val of (bw > current_band_width) is invalid 1622 */ 1623 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1624 1625 u8 sec_ch_offset; 1626 u8 rf_type; 1627 u8 rf_path_num; 1628 u8 rf_phy_num; 1629 u32 antenna_tx; 1630 u32 antenna_rx; 1631 u8 bfee_sts_cap; 1632 1633 /* protect tx power section */ 1634 struct mutex tx_power_mutex; 1635 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1636 [DESC_RATE_MAX]; 1637 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1638 [DESC_RATE_MAX]; 1639 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1640 [RTW_RATE_SECTION_MAX]; 1641 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1642 [RTW_RATE_SECTION_MAX]; 1643 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1644 [RTW_CHANNEL_WIDTH_MAX] 1645 [RTW_RATE_SECTION_MAX] 1646 [RTW_MAX_CHANNEL_NUM_2G]; 1647 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1648 [RTW_CHANNEL_WIDTH_MAX] 1649 [RTW_RATE_SECTION_MAX] 1650 [RTW_MAX_CHANNEL_NUM_5G]; 1651 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1652 [DESC_RATE_MAX]; 1653 }; 1654 1655 struct rtw_dev { 1656 struct ieee80211_hw *hw; 1657 struct device *dev; 1658 1659 struct rtw_hci hci; 1660 1661 struct rtw_chip_info *chip; 1662 struct rtw_hal hal; 1663 struct rtw_fifo_conf fifo; 1664 struct rtw_fw_state fw; 1665 struct rtw_efuse efuse; 1666 struct rtw_sec_desc sec; 1667 struct rtw_traffic_stats stats; 1668 struct rtw_regulatory regd; 1669 struct rtw_bf_info bf_info; 1670 1671 struct rtw_dm_info dm_info; 1672 struct rtw_coex coex; 1673 1674 /* ensures exclusive access from mac80211 callbacks */ 1675 struct mutex mutex; 1676 1677 /* read/write rf register */ 1678 spinlock_t rf_lock; 1679 1680 /* watch dog every 2 sec */ 1681 struct delayed_work watch_dog_work; 1682 u32 watch_dog_cnt; 1683 1684 struct list_head rsvd_page_list; 1685 1686 /* c2h cmd queue & handler work */ 1687 struct sk_buff_head c2h_queue; 1688 struct work_struct c2h_work; 1689 1690 /* used to protect txqs list */ 1691 spinlock_t txq_lock; 1692 struct list_head txqs; 1693 struct tasklet_struct tx_tasklet; 1694 struct work_struct ba_work; 1695 1696 struct rtw_tx_report tx_report; 1697 1698 struct { 1699 /* incicate the mail box to use with fw */ 1700 u8 last_box_num; 1701 /* protect to send h2c to fw */ 1702 spinlock_t lock; 1703 u32 seq; 1704 } h2c; 1705 1706 /* lps power state & handler work */ 1707 struct rtw_lps_conf lps_conf; 1708 bool ps_enabled; 1709 1710 struct dentry *debugfs; 1711 1712 u8 sta_cnt; 1713 u32 rts_threshold; 1714 1715 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1716 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1717 1718 u8 mp_mode; 1719 1720 struct rtw_fw_state wow_fw; 1721 struct rtw_wow_param wow; 1722 1723 bool need_rfk; 1724 1725 /* hci related data, must be last */ 1726 u8 priv[] __aligned(sizeof(void *)); 1727 }; 1728 1729 #include "hci.h" 1730 1731 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1732 { 1733 return !!rtwdev->sta_cnt; 1734 } 1735 1736 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1737 { 1738 void *p = rtwtxq; 1739 1740 return container_of(p, struct ieee80211_txq, drv_priv); 1741 } 1742 1743 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1744 { 1745 void *p = rtwvif; 1746 1747 return container_of(p, struct ieee80211_vif, drv_priv); 1748 } 1749 1750 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1751 struct cfg80211_ssid *b) 1752 { 1753 if (!a || !b || a->ssid_len != b->ssid_len) 1754 return false; 1755 1756 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1757 return false; 1758 1759 return true; 1760 } 1761 1762 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 1763 { 1764 if (rtwdev->chip->ops->efuse_grant) 1765 rtwdev->chip->ops->efuse_grant(rtwdev, true); 1766 } 1767 1768 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 1769 { 1770 if (rtwdev->chip->ops->efuse_grant) 1771 rtwdev->chip->ops->efuse_grant(rtwdev, false); 1772 } 1773 1774 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 1775 { 1776 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 1777 } 1778 1779 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 1780 { 1781 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 1782 } 1783 1784 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 1785 { 1786 return rtwdev->chip->rx_ldpc; 1787 } 1788 1789 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1790 struct rtw_channel_params *ch_param); 1791 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1792 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1793 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1794 void rtw_restore_reg(struct rtw_dev *rtwdev, 1795 struct rtw_backup_info *bckp, u32 num); 1796 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1797 void rtw_set_channel(struct rtw_dev *rtwdev); 1798 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 1799 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1800 u32 config); 1801 void rtw_tx_report_purge_timer(struct timer_list *t); 1802 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1803 int rtw_core_start(struct rtw_dev *rtwdev); 1804 void rtw_core_stop(struct rtw_dev *rtwdev); 1805 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1806 int rtw_core_init(struct rtw_dev *rtwdev); 1807 void rtw_core_deinit(struct rtw_dev *rtwdev); 1808 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1809 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1810 u16 rtw_desc_to_bitrate(u8 desc_rate); 1811 1812 #endif 1813