1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/interrupt.h> 15 16 #include "util.h" 17 18 #define RTW_MAX_MAC_ID_NUM 32 19 #define RTW_MAX_SEC_CAM_NUM 32 20 #define MAX_PG_CAM_BACKUP_NUM 8 21 22 #define RTW_MAX_PATTERN_NUM 12 23 #define RTW_MAX_PATTERN_MASK_SIZE 16 24 #define RTW_MAX_PATTERN_SIZE 128 25 26 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 27 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 #define TX_PAGE_SIZE_SHIFT 7 31 32 #define RTW_CHANNEL_WIDTH_MAX 3 33 #define RTW_RF_PATH_MAX 4 34 #define HW_FEATURE_LEN 13 35 36 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 37 38 extern bool rtw_bf_support; 39 extern unsigned int rtw_fw_lps_deep_mode; 40 extern unsigned int rtw_debug_mask; 41 extern const struct ieee80211_ops rtw_ops; 42 extern struct rtw_chip_info rtw8822b_hw_spec; 43 extern struct rtw_chip_info rtw8822c_hw_spec; 44 extern struct rtw_chip_info rtw8723d_hw_spec; 45 46 #define RTW_MAX_CHANNEL_NUM_2G 14 47 #define RTW_MAX_CHANNEL_NUM_5G 49 48 49 struct rtw_dev; 50 51 enum rtw_hci_type { 52 RTW_HCI_TYPE_PCIE, 53 RTW_HCI_TYPE_USB, 54 RTW_HCI_TYPE_SDIO, 55 56 RTW_HCI_TYPE_UNDEFINE, 57 }; 58 59 struct rtw_hci { 60 struct rtw_hci_ops *ops; 61 enum rtw_hci_type type; 62 63 u32 rpwm_addr; 64 u32 cpwm_addr; 65 66 u8 bulkout_num; 67 }; 68 69 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 70 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 71 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 72 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 73 74 #define IS_CH_5G_BAND_MID(channel) \ 75 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 76 77 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 78 #define IS_CH_5G_BAND(channel) \ 79 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 80 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 81 82 enum rtw_supported_band { 83 RTW_BAND_2G = 1 << 0, 84 RTW_BAND_5G = 1 << 1, 85 RTW_BAND_60G = 1 << 2, 86 87 RTW_BAND_MAX, 88 }; 89 90 /* now, support upto 80M bw */ 91 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 92 93 enum rtw_bandwidth { 94 RTW_CHANNEL_WIDTH_20 = 0, 95 RTW_CHANNEL_WIDTH_40 = 1, 96 RTW_CHANNEL_WIDTH_80 = 2, 97 RTW_CHANNEL_WIDTH_160 = 3, 98 RTW_CHANNEL_WIDTH_80_80 = 4, 99 RTW_CHANNEL_WIDTH_5 = 5, 100 RTW_CHANNEL_WIDTH_10 = 6, 101 }; 102 103 enum rtw_sc_offset { 104 RTW_SC_DONT_CARE = 0, 105 RTW_SC_20_UPPER = 1, 106 RTW_SC_20_LOWER = 2, 107 RTW_SC_20_UPMOST = 3, 108 RTW_SC_20_LOWEST = 4, 109 RTW_SC_40_UPPER = 9, 110 RTW_SC_40_LOWER = 10, 111 }; 112 113 enum rtw_net_type { 114 RTW_NET_NO_LINK = 0, 115 RTW_NET_AD_HOC = 1, 116 RTW_NET_MGD_LINKED = 2, 117 RTW_NET_AP_MODE = 3, 118 }; 119 120 enum rtw_rf_type { 121 RF_1T1R = 0, 122 RF_1T2R = 1, 123 RF_2T2R = 2, 124 RF_2T3R = 3, 125 RF_2T4R = 4, 126 RF_3T3R = 5, 127 RF_3T4R = 6, 128 RF_4T4R = 7, 129 RF_TYPE_MAX, 130 }; 131 132 enum rtw_rf_path { 133 RF_PATH_A = 0, 134 RF_PATH_B = 1, 135 RF_PATH_C = 2, 136 RF_PATH_D = 3, 137 }; 138 139 enum rtw_bb_path { 140 BB_PATH_A = BIT(0), 141 BB_PATH_B = BIT(1), 142 BB_PATH_C = BIT(2), 143 BB_PATH_D = BIT(3), 144 145 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 146 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 147 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 148 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 149 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 150 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 151 152 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 153 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 154 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 155 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 156 157 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 158 }; 159 160 enum rtw_rate_section { 161 RTW_RATE_SECTION_CCK = 0, 162 RTW_RATE_SECTION_OFDM, 163 RTW_RATE_SECTION_HT_1S, 164 RTW_RATE_SECTION_HT_2S, 165 RTW_RATE_SECTION_VHT_1S, 166 RTW_RATE_SECTION_VHT_2S, 167 168 /* keep last */ 169 RTW_RATE_SECTION_MAX, 170 }; 171 172 enum rtw_wireless_set { 173 WIRELESS_CCK = 0x00000001, 174 WIRELESS_OFDM = 0x00000002, 175 WIRELESS_HT = 0x00000004, 176 WIRELESS_VHT = 0x00000008, 177 }; 178 179 #define HT_STBC_EN BIT(0) 180 #define VHT_STBC_EN BIT(1) 181 #define HT_LDPC_EN BIT(0) 182 #define VHT_LDPC_EN BIT(1) 183 184 enum rtw_chip_type { 185 RTW_CHIP_TYPE_8822B, 186 RTW_CHIP_TYPE_8822C, 187 RTW_CHIP_TYPE_8723D, 188 }; 189 190 enum rtw_tx_queue_type { 191 /* the order of AC queues matters */ 192 RTW_TX_QUEUE_BK = 0x0, 193 RTW_TX_QUEUE_BE = 0x1, 194 RTW_TX_QUEUE_VI = 0x2, 195 RTW_TX_QUEUE_VO = 0x3, 196 197 RTW_TX_QUEUE_BCN = 0x4, 198 RTW_TX_QUEUE_MGMT = 0x5, 199 RTW_TX_QUEUE_HI0 = 0x6, 200 RTW_TX_QUEUE_H2C = 0x7, 201 /* keep it last */ 202 RTK_MAX_TX_QUEUE_NUM 203 }; 204 205 enum rtw_rx_queue_type { 206 RTW_RX_QUEUE_MPDU = 0x0, 207 RTW_RX_QUEUE_C2H = 0x1, 208 /* keep it last */ 209 RTK_MAX_RX_QUEUE_NUM 210 }; 211 212 enum rtw_fw_type { 213 RTW_NORMAL_FW = 0x0, 214 RTW_WOWLAN_FW = 0x1, 215 }; 216 217 enum rtw_rate_index { 218 RTW_RATEID_BGN_40M_2SS = 0, 219 RTW_RATEID_BGN_40M_1SS = 1, 220 RTW_RATEID_BGN_20M_2SS = 2, 221 RTW_RATEID_BGN_20M_1SS = 3, 222 RTW_RATEID_GN_N2SS = 4, 223 RTW_RATEID_GN_N1SS = 5, 224 RTW_RATEID_BG = 6, 225 RTW_RATEID_G = 7, 226 RTW_RATEID_B_20M = 8, 227 RTW_RATEID_ARFR0_AC_2SS = 9, 228 RTW_RATEID_ARFR1_AC_1SS = 10, 229 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 230 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 231 RTW_RATEID_ARFR4_AC_3SS = 13, 232 RTW_RATEID_ARFR5_N_3SS = 14, 233 RTW_RATEID_ARFR7_N_4SS = 15, 234 RTW_RATEID_ARFR6_AC_4SS = 16 235 }; 236 237 enum rtw_trx_desc_rate { 238 DESC_RATE1M = 0x00, 239 DESC_RATE2M = 0x01, 240 DESC_RATE5_5M = 0x02, 241 DESC_RATE11M = 0x03, 242 243 DESC_RATE6M = 0x04, 244 DESC_RATE9M = 0x05, 245 DESC_RATE12M = 0x06, 246 DESC_RATE18M = 0x07, 247 DESC_RATE24M = 0x08, 248 DESC_RATE36M = 0x09, 249 DESC_RATE48M = 0x0a, 250 DESC_RATE54M = 0x0b, 251 252 DESC_RATEMCS0 = 0x0c, 253 DESC_RATEMCS1 = 0x0d, 254 DESC_RATEMCS2 = 0x0e, 255 DESC_RATEMCS3 = 0x0f, 256 DESC_RATEMCS4 = 0x10, 257 DESC_RATEMCS5 = 0x11, 258 DESC_RATEMCS6 = 0x12, 259 DESC_RATEMCS7 = 0x13, 260 DESC_RATEMCS8 = 0x14, 261 DESC_RATEMCS9 = 0x15, 262 DESC_RATEMCS10 = 0x16, 263 DESC_RATEMCS11 = 0x17, 264 DESC_RATEMCS12 = 0x18, 265 DESC_RATEMCS13 = 0x19, 266 DESC_RATEMCS14 = 0x1a, 267 DESC_RATEMCS15 = 0x1b, 268 DESC_RATEMCS16 = 0x1c, 269 DESC_RATEMCS17 = 0x1d, 270 DESC_RATEMCS18 = 0x1e, 271 DESC_RATEMCS19 = 0x1f, 272 DESC_RATEMCS20 = 0x20, 273 DESC_RATEMCS21 = 0x21, 274 DESC_RATEMCS22 = 0x22, 275 DESC_RATEMCS23 = 0x23, 276 DESC_RATEMCS24 = 0x24, 277 DESC_RATEMCS25 = 0x25, 278 DESC_RATEMCS26 = 0x26, 279 DESC_RATEMCS27 = 0x27, 280 DESC_RATEMCS28 = 0x28, 281 DESC_RATEMCS29 = 0x29, 282 DESC_RATEMCS30 = 0x2a, 283 DESC_RATEMCS31 = 0x2b, 284 285 DESC_RATEVHT1SS_MCS0 = 0x2c, 286 DESC_RATEVHT1SS_MCS1 = 0x2d, 287 DESC_RATEVHT1SS_MCS2 = 0x2e, 288 DESC_RATEVHT1SS_MCS3 = 0x2f, 289 DESC_RATEVHT1SS_MCS4 = 0x30, 290 DESC_RATEVHT1SS_MCS5 = 0x31, 291 DESC_RATEVHT1SS_MCS6 = 0x32, 292 DESC_RATEVHT1SS_MCS7 = 0x33, 293 DESC_RATEVHT1SS_MCS8 = 0x34, 294 DESC_RATEVHT1SS_MCS9 = 0x35, 295 296 DESC_RATEVHT2SS_MCS0 = 0x36, 297 DESC_RATEVHT2SS_MCS1 = 0x37, 298 DESC_RATEVHT2SS_MCS2 = 0x38, 299 DESC_RATEVHT2SS_MCS3 = 0x39, 300 DESC_RATEVHT2SS_MCS4 = 0x3a, 301 DESC_RATEVHT2SS_MCS5 = 0x3b, 302 DESC_RATEVHT2SS_MCS6 = 0x3c, 303 DESC_RATEVHT2SS_MCS7 = 0x3d, 304 DESC_RATEVHT2SS_MCS8 = 0x3e, 305 DESC_RATEVHT2SS_MCS9 = 0x3f, 306 307 DESC_RATEVHT3SS_MCS0 = 0x40, 308 DESC_RATEVHT3SS_MCS1 = 0x41, 309 DESC_RATEVHT3SS_MCS2 = 0x42, 310 DESC_RATEVHT3SS_MCS3 = 0x43, 311 DESC_RATEVHT3SS_MCS4 = 0x44, 312 DESC_RATEVHT3SS_MCS5 = 0x45, 313 DESC_RATEVHT3SS_MCS6 = 0x46, 314 DESC_RATEVHT3SS_MCS7 = 0x47, 315 DESC_RATEVHT3SS_MCS8 = 0x48, 316 DESC_RATEVHT3SS_MCS9 = 0x49, 317 318 DESC_RATEVHT4SS_MCS0 = 0x4a, 319 DESC_RATEVHT4SS_MCS1 = 0x4b, 320 DESC_RATEVHT4SS_MCS2 = 0x4c, 321 DESC_RATEVHT4SS_MCS3 = 0x4d, 322 DESC_RATEVHT4SS_MCS4 = 0x4e, 323 DESC_RATEVHT4SS_MCS5 = 0x4f, 324 DESC_RATEVHT4SS_MCS6 = 0x50, 325 DESC_RATEVHT4SS_MCS7 = 0x51, 326 DESC_RATEVHT4SS_MCS8 = 0x52, 327 DESC_RATEVHT4SS_MCS9 = 0x53, 328 329 DESC_RATE_MAX, 330 }; 331 332 enum rtw_regulatory_domains { 333 RTW_REGD_FCC = 0, 334 RTW_REGD_MKK = 1, 335 RTW_REGD_ETSI = 2, 336 RTW_REGD_IC = 3, 337 RTW_REGD_KCC = 4, 338 RTW_REGD_ACMA = 5, 339 RTW_REGD_CHILE = 6, 340 RTW_REGD_UKRAINE = 7, 341 RTW_REGD_MEXICO = 8, 342 RTW_REGD_CN = 9, 343 RTW_REGD_WW, 344 345 RTW_REGD_MAX 346 }; 347 348 enum rtw_txq_flags { 349 RTW_TXQ_AMPDU, 350 RTW_TXQ_BLOCK_BA, 351 }; 352 353 enum rtw_flags { 354 RTW_FLAG_RUNNING, 355 RTW_FLAG_FW_RUNNING, 356 RTW_FLAG_SCANNING, 357 RTW_FLAG_INACTIVE_PS, 358 RTW_FLAG_LEISURE_PS, 359 RTW_FLAG_LEISURE_PS_DEEP, 360 RTW_FLAG_DIG_DISABLE, 361 RTW_FLAG_BUSY_TRAFFIC, 362 RTW_FLAG_WOWLAN, 363 364 NUM_OF_RTW_FLAGS, 365 }; 366 367 enum rtw_evm { 368 RTW_EVM_OFDM = 0, 369 RTW_EVM_1SS, 370 RTW_EVM_2SS_A, 371 RTW_EVM_2SS_B, 372 /* keep it last */ 373 RTW_EVM_NUM 374 }; 375 376 enum rtw_snr { 377 RTW_SNR_OFDM_A = 0, 378 RTW_SNR_OFDM_B, 379 RTW_SNR_OFDM_C, 380 RTW_SNR_OFDM_D, 381 RTW_SNR_1SS_A, 382 RTW_SNR_1SS_B, 383 RTW_SNR_1SS_C, 384 RTW_SNR_1SS_D, 385 RTW_SNR_2SS_A, 386 RTW_SNR_2SS_B, 387 RTW_SNR_2SS_C, 388 RTW_SNR_2SS_D, 389 /* keep it last */ 390 RTW_SNR_NUM 391 }; 392 393 enum rtw_wow_flags { 394 RTW_WOW_FLAG_EN_MAGIC_PKT, 395 RTW_WOW_FLAG_EN_REKEY_PKT, 396 RTW_WOW_FLAG_EN_DISCONNECT, 397 398 /* keep it last */ 399 RTW_WOW_FLAG_MAX, 400 }; 401 402 /* the power index is represented by differences, which cck-1s & ht40-1s are 403 * the base values, so for 1s's differences, there are only ht20 & ofdm 404 */ 405 struct rtw_2g_1s_pwr_idx_diff { 406 #ifdef __LITTLE_ENDIAN 407 s8 ofdm:4; 408 s8 bw20:4; 409 #else 410 s8 bw20:4; 411 s8 ofdm:4; 412 #endif 413 } __packed; 414 415 struct rtw_2g_ns_pwr_idx_diff { 416 #ifdef __LITTLE_ENDIAN 417 s8 bw20:4; 418 s8 bw40:4; 419 s8 cck:4; 420 s8 ofdm:4; 421 #else 422 s8 ofdm:4; 423 s8 cck:4; 424 s8 bw40:4; 425 s8 bw20:4; 426 #endif 427 } __packed; 428 429 struct rtw_2g_txpwr_idx { 430 u8 cck_base[6]; 431 u8 bw40_base[5]; 432 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 433 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 434 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 435 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 436 }; 437 438 struct rtw_5g_ht_1s_pwr_idx_diff { 439 #ifdef __LITTLE_ENDIAN 440 s8 ofdm:4; 441 s8 bw20:4; 442 #else 443 s8 bw20:4; 444 s8 ofdm:4; 445 #endif 446 } __packed; 447 448 struct rtw_5g_ht_ns_pwr_idx_diff { 449 #ifdef __LITTLE_ENDIAN 450 s8 bw20:4; 451 s8 bw40:4; 452 #else 453 s8 bw40:4; 454 s8 bw20:4; 455 #endif 456 } __packed; 457 458 struct rtw_5g_ofdm_ns_pwr_idx_diff { 459 #ifdef __LITTLE_ENDIAN 460 s8 ofdm_3s:4; 461 s8 ofdm_2s:4; 462 s8 ofdm_4s:4; 463 s8 res:4; 464 #else 465 s8 res:4; 466 s8 ofdm_4s:4; 467 s8 ofdm_2s:4; 468 s8 ofdm_3s:4; 469 #endif 470 } __packed; 471 472 struct rtw_5g_vht_ns_pwr_idx_diff { 473 #ifdef __LITTLE_ENDIAN 474 s8 bw160:4; 475 s8 bw80:4; 476 #else 477 s8 bw80:4; 478 s8 bw160:4; 479 #endif 480 } __packed; 481 482 struct rtw_5g_txpwr_idx { 483 u8 bw40_base[14]; 484 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 485 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 486 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 487 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 488 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 489 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 490 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 491 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 492 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 493 }; 494 495 struct rtw_txpwr_idx { 496 struct rtw_2g_txpwr_idx pwr_idx_2g; 497 struct rtw_5g_txpwr_idx pwr_idx_5g; 498 }; 499 500 struct rtw_timer_list { 501 struct timer_list timer; 502 void (*function)(void *data); 503 void *args; 504 }; 505 506 struct rtw_channel_params { 507 u8 center_chan; 508 u8 bandwidth; 509 u8 primary_chan_idx; 510 /* center channel by different available bandwidth, 511 * val of (bw > current bandwidth) is invalid 512 */ 513 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 514 }; 515 516 struct rtw_hw_reg { 517 u32 addr; 518 u32 mask; 519 }; 520 521 struct rtw_reg_domain { 522 u32 addr; 523 u32 mask; 524 #define RTW_REG_DOMAIN_MAC32 0 525 #define RTW_REG_DOMAIN_MAC16 1 526 #define RTW_REG_DOMAIN_MAC8 2 527 #define RTW_REG_DOMAIN_RF_A 3 528 #define RTW_REG_DOMAIN_RF_B 4 529 #define RTW_REG_DOMAIN_NL 0xFF 530 u8 domain; 531 }; 532 533 struct rtw_rf_sipi_addr { 534 u32 hssi_1; 535 u32 hssi_2; 536 u32 lssi_read; 537 u32 lssi_read_pi; 538 }; 539 540 struct rtw_backup_info { 541 u8 len; 542 u32 reg; 543 u32 val; 544 }; 545 546 enum rtw_vif_port_set { 547 PORT_SET_MAC_ADDR = BIT(0), 548 PORT_SET_BSSID = BIT(1), 549 PORT_SET_NET_TYPE = BIT(2), 550 PORT_SET_AID = BIT(3), 551 PORT_SET_BCN_CTRL = BIT(4), 552 }; 553 554 struct rtw_vif_port { 555 struct rtw_hw_reg mac_addr; 556 struct rtw_hw_reg bssid; 557 struct rtw_hw_reg net_type; 558 struct rtw_hw_reg aid; 559 struct rtw_hw_reg bcn_ctrl; 560 }; 561 562 struct rtw_tx_pkt_info { 563 u32 tx_pkt_size; 564 u8 offset; 565 u8 pkt_offset; 566 u8 mac_id; 567 u8 rate_id; 568 u8 rate; 569 u8 qsel; 570 u8 bw; 571 u8 sec_type; 572 u8 sn; 573 bool ampdu_en; 574 u8 ampdu_factor; 575 u8 ampdu_density; 576 u16 seq; 577 bool stbc; 578 bool ldpc; 579 bool dis_rate_fallback; 580 bool bmc; 581 bool use_rate; 582 bool ls; 583 bool fs; 584 bool short_gi; 585 bool report; 586 bool rts; 587 bool dis_qselseq; 588 bool en_hwseq; 589 u8 hw_ssn_sel; 590 }; 591 592 struct rtw_rx_pkt_stat { 593 bool phy_status; 594 bool icv_err; 595 bool crc_err; 596 bool decrypted; 597 bool is_c2h; 598 599 s32 signal_power; 600 u16 pkt_len; 601 u8 bw; 602 u8 drv_info_sz; 603 u8 shift; 604 u8 rate; 605 u8 mac_id; 606 u8 cam_id; 607 u8 ppdu_cnt; 608 u32 tsf_low; 609 s8 rx_power[RTW_RF_PATH_MAX]; 610 u8 rssi; 611 u8 rxsc; 612 s8 rx_snr[RTW_RF_PATH_MAX]; 613 u8 rx_evm[RTW_RF_PATH_MAX]; 614 s8 cfo_tail[RTW_RF_PATH_MAX]; 615 616 struct rtw_sta_info *si; 617 struct ieee80211_vif *vif; 618 }; 619 620 DECLARE_EWMA(tp, 10, 2); 621 622 struct rtw_traffic_stats { 623 /* units in bytes */ 624 u64 tx_unicast; 625 u64 rx_unicast; 626 627 /* count for packets */ 628 u64 tx_cnt; 629 u64 rx_cnt; 630 631 /* units in Mbps */ 632 u32 tx_throughput; 633 u32 rx_throughput; 634 struct ewma_tp tx_ewma_tp; 635 struct ewma_tp rx_ewma_tp; 636 }; 637 638 enum rtw_lps_mode { 639 RTW_MODE_ACTIVE = 0, 640 RTW_MODE_LPS = 1, 641 RTW_MODE_WMM_PS = 2, 642 }; 643 644 enum rtw_lps_deep_mode { 645 LPS_DEEP_MODE_NONE = 0, 646 LPS_DEEP_MODE_LCLK = 1, 647 LPS_DEEP_MODE_PG = 2, 648 }; 649 650 enum rtw_pwr_state { 651 RTW_RF_OFF = 0x0, 652 RTW_RF_ON = 0x4, 653 RTW_ALL_ON = 0xc, 654 }; 655 656 struct rtw_lps_conf { 657 enum rtw_lps_mode mode; 658 enum rtw_lps_deep_mode deep_mode; 659 enum rtw_pwr_state state; 660 u8 awake_interval; 661 u8 rlbm; 662 u8 smart_ps; 663 u8 port_id; 664 bool sec_cam_backup; 665 bool pattern_cam_backup; 666 }; 667 668 enum rtw_hw_key_type { 669 RTW_CAM_NONE = 0, 670 RTW_CAM_WEP40 = 1, 671 RTW_CAM_TKIP = 2, 672 RTW_CAM_AES = 4, 673 RTW_CAM_WEP104 = 5, 674 }; 675 676 struct rtw_cam_entry { 677 bool valid; 678 bool group; 679 u8 addr[ETH_ALEN]; 680 u8 hw_key_type; 681 struct ieee80211_key_conf *key; 682 }; 683 684 struct rtw_sec_desc { 685 /* search strategy */ 686 bool default_key_search; 687 688 u32 total_cam_num; 689 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 690 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 691 }; 692 693 struct rtw_tx_report { 694 /* protect the tx report queue */ 695 spinlock_t q_lock; 696 struct sk_buff_head queue; 697 atomic_t sn; 698 struct timer_list purge_timer; 699 }; 700 701 struct rtw_ra_report { 702 struct rate_info txrate; 703 u32 bit_rate; 704 u8 desc_rate; 705 }; 706 707 struct rtw_txq { 708 struct list_head list; 709 710 unsigned long flags; 711 unsigned long last_push; 712 }; 713 714 #define RTW_BC_MC_MACID 1 715 DECLARE_EWMA(rssi, 10, 16); 716 717 struct rtw_sta_info { 718 struct ieee80211_sta *sta; 719 struct ieee80211_vif *vif; 720 721 struct ewma_rssi avg_rssi; 722 u8 rssi_level; 723 724 u8 mac_id; 725 u8 rate_id; 726 enum rtw_bandwidth bw_mode; 727 enum rtw_rf_type rf_type; 728 enum rtw_wireless_set wireless_set; 729 u8 stbc_en:2; 730 u8 ldpc_en:2; 731 bool sgi_enable; 732 bool vht_enable; 733 bool updated; 734 u8 init_ra_lv; 735 u64 ra_mask; 736 737 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 738 739 struct rtw_ra_report ra_report; 740 741 bool use_cfg_mask; 742 struct cfg80211_bitrate_mask *mask; 743 }; 744 745 enum rtw_bfee_role { 746 RTW_BFEE_NONE, 747 RTW_BFEE_SU, 748 RTW_BFEE_MU 749 }; 750 751 struct rtw_bfee { 752 enum rtw_bfee_role role; 753 754 u16 p_aid; 755 u8 g_id; 756 u8 mac_addr[ETH_ALEN]; 757 u8 sound_dim; 758 759 /* SU-MIMO */ 760 u8 su_reg_index; 761 762 /* MU-MIMO */ 763 u16 aid; 764 }; 765 766 struct rtw_bf_info { 767 u8 bfer_mu_cnt; 768 u8 bfer_su_cnt; 769 DECLARE_BITMAP(bfer_su_reg_maping, 2); 770 u8 cur_csi_rpt_rate; 771 }; 772 773 struct rtw_vif { 774 enum rtw_net_type net_type; 775 u16 aid; 776 u8 mac_addr[ETH_ALEN]; 777 u8 bssid[ETH_ALEN]; 778 u8 port; 779 u8 bcn_ctrl; 780 struct list_head rsvd_page_list; 781 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 782 const struct rtw_vif_port *conf; 783 784 struct rtw_traffic_stats stats; 785 786 struct rtw_bfee bfee; 787 }; 788 789 struct rtw_regulatory { 790 char alpha2[2]; 791 u8 chplan; 792 u8 txpwr_regd; 793 }; 794 795 struct rtw_chip_ops { 796 int (*mac_init)(struct rtw_dev *rtwdev); 797 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 798 void (*phy_set_param)(struct rtw_dev *rtwdev); 799 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 800 u8 bandwidth, u8 primary_chan_idx); 801 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 802 struct rtw_rx_pkt_stat *pkt_stat, 803 struct ieee80211_rx_status *rx_status); 804 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 805 u32 addr, u32 mask); 806 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 807 u32 addr, u32 mask, u32 data); 808 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 809 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 810 u32 size); 811 int (*set_antenna)(struct rtw_dev *rtwdev, 812 u32 antenna_tx, 813 u32 antenna_rx); 814 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 815 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 816 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 817 void (*phy_calibration)(struct rtw_dev *rtwdev); 818 void (*dpk_track)(struct rtw_dev *rtwdev); 819 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 820 void (*pwr_track)(struct rtw_dev *rtwdev); 821 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 822 struct rtw_bfee *bfee, bool enable); 823 void (*set_gid_table)(struct rtw_dev *rtwdev, 824 struct ieee80211_vif *vif, 825 struct ieee80211_bss_conf *conf); 826 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 827 u8 fixrate_en, u8 *new_rate); 828 829 /* for coex */ 830 void (*coex_set_init)(struct rtw_dev *rtwdev); 831 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 832 u8 ctrl_type, u8 pos_type); 833 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 834 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 835 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 836 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 837 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 838 }; 839 840 #define RTW_PWR_POLLING_CNT 20000 841 842 #define RTW_PWR_CMD_READ 0x00 843 #define RTW_PWR_CMD_WRITE 0x01 844 #define RTW_PWR_CMD_POLLING 0x02 845 #define RTW_PWR_CMD_DELAY 0x03 846 #define RTW_PWR_CMD_END 0x04 847 848 /* define the base address of each block */ 849 #define RTW_PWR_ADDR_MAC 0x00 850 #define RTW_PWR_ADDR_USB 0x01 851 #define RTW_PWR_ADDR_PCIE 0x02 852 #define RTW_PWR_ADDR_SDIO 0x03 853 854 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 855 #define RTW_PWR_INTF_USB_MSK BIT(1) 856 #define RTW_PWR_INTF_PCI_MSK BIT(2) 857 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 858 859 #define RTW_PWR_CUT_TEST_MSK BIT(0) 860 #define RTW_PWR_CUT_A_MSK BIT(1) 861 #define RTW_PWR_CUT_B_MSK BIT(2) 862 #define RTW_PWR_CUT_C_MSK BIT(3) 863 #define RTW_PWR_CUT_D_MSK BIT(4) 864 #define RTW_PWR_CUT_E_MSK BIT(5) 865 #define RTW_PWR_CUT_F_MSK BIT(6) 866 #define RTW_PWR_CUT_G_MSK BIT(7) 867 #define RTW_PWR_CUT_ALL_MSK 0xFF 868 869 enum rtw_pwr_seq_cmd_delay_unit { 870 RTW_PWR_DELAY_US, 871 RTW_PWR_DELAY_MS, 872 }; 873 874 struct rtw_pwr_seq_cmd { 875 u16 offset; 876 u8 cut_mask; 877 u8 intf_mask; 878 u8 base:4; 879 u8 cmd:4; 880 u8 mask; 881 u8 value; 882 }; 883 884 enum rtw_chip_ver { 885 RTW_CHIP_VER_CUT_A = 0x00, 886 RTW_CHIP_VER_CUT_B = 0x01, 887 RTW_CHIP_VER_CUT_C = 0x02, 888 RTW_CHIP_VER_CUT_D = 0x03, 889 RTW_CHIP_VER_CUT_E = 0x04, 890 RTW_CHIP_VER_CUT_F = 0x05, 891 RTW_CHIP_VER_CUT_G = 0x06, 892 }; 893 894 #define RTW_INTF_PHY_PLATFORM_ALL 0 895 896 enum rtw_intf_phy_cut { 897 RTW_INTF_PHY_CUT_A = BIT(0), 898 RTW_INTF_PHY_CUT_B = BIT(1), 899 RTW_INTF_PHY_CUT_C = BIT(2), 900 RTW_INTF_PHY_CUT_D = BIT(3), 901 RTW_INTF_PHY_CUT_E = BIT(4), 902 RTW_INTF_PHY_CUT_F = BIT(5), 903 RTW_INTF_PHY_CUT_G = BIT(6), 904 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 905 }; 906 907 enum rtw_ip_sel { 908 RTW_IP_SEL_PHY = 0, 909 RTW_IP_SEL_MAC = 1, 910 RTW_IP_SEL_DBI = 2, 911 912 RTW_IP_SEL_UNDEF = 0xFFFF 913 }; 914 915 enum rtw_pq_map_id { 916 RTW_PQ_MAP_VO = 0x0, 917 RTW_PQ_MAP_VI = 0x1, 918 RTW_PQ_MAP_BE = 0x2, 919 RTW_PQ_MAP_BK = 0x3, 920 RTW_PQ_MAP_MG = 0x4, 921 RTW_PQ_MAP_HI = 0x5, 922 RTW_PQ_MAP_NUM = 0x6, 923 924 RTW_PQ_MAP_UNDEF, 925 }; 926 927 enum rtw_dma_mapping { 928 RTW_DMA_MAPPING_EXTRA = 0, 929 RTW_DMA_MAPPING_LOW = 1, 930 RTW_DMA_MAPPING_NORMAL = 2, 931 RTW_DMA_MAPPING_HIGH = 3, 932 933 RTW_DMA_MAPPING_MAX, 934 RTW_DMA_MAPPING_UNDEF, 935 }; 936 937 struct rtw_rqpn { 938 enum rtw_dma_mapping dma_map_vo; 939 enum rtw_dma_mapping dma_map_vi; 940 enum rtw_dma_mapping dma_map_be; 941 enum rtw_dma_mapping dma_map_bk; 942 enum rtw_dma_mapping dma_map_mg; 943 enum rtw_dma_mapping dma_map_hi; 944 }; 945 946 struct rtw_page_table { 947 u16 hq_num; 948 u16 nq_num; 949 u16 lq_num; 950 u16 exq_num; 951 u16 gapq_num; 952 }; 953 954 struct rtw_intf_phy_para { 955 u16 offset; 956 u16 value; 957 u16 ip_sel; 958 u16 cut_mask; 959 u16 platform; 960 }; 961 962 struct rtw_wow_pattern { 963 u16 crc; 964 u8 type; 965 u8 valid; 966 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 967 }; 968 969 struct rtw_pno_request { 970 bool inited; 971 u32 match_set_cnt; 972 struct cfg80211_match_set *match_sets; 973 u8 channel_cnt; 974 struct ieee80211_channel *channels; 975 struct cfg80211_sched_scan_plan scan_plan; 976 }; 977 978 struct rtw_wow_param { 979 struct ieee80211_vif *wow_vif; 980 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 981 u8 txpause; 982 u8 pattern_cnt; 983 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 984 985 bool ips_enabled; 986 struct rtw_pno_request pno_req; 987 }; 988 989 struct rtw_intf_phy_para_table { 990 const struct rtw_intf_phy_para *usb2_para; 991 const struct rtw_intf_phy_para *usb3_para; 992 const struct rtw_intf_phy_para *gen1_para; 993 const struct rtw_intf_phy_para *gen2_para; 994 u8 n_usb2_para; 995 u8 n_usb3_para; 996 u8 n_gen1_para; 997 u8 n_gen2_para; 998 }; 999 1000 struct rtw_table { 1001 const void *data; 1002 const u32 size; 1003 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1004 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1005 u32 addr, u32 data); 1006 enum rtw_rf_path rf_path; 1007 }; 1008 1009 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1010 const struct rtw_table *tbl) 1011 { 1012 (*tbl->parse)(rtwdev, tbl); 1013 } 1014 1015 enum rtw_rfe_fem { 1016 RTW_RFE_IFEM, 1017 RTW_RFE_EFEM, 1018 RTW_RFE_IFEM2G_EFEM5G, 1019 RTW_RFE_NUM, 1020 }; 1021 1022 struct rtw_rfe_def { 1023 const struct rtw_table *phy_pg_tbl; 1024 const struct rtw_table *txpwr_lmt_tbl; 1025 }; 1026 1027 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1028 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1029 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1030 } 1031 1032 #define RTW_PWR_TRK_5G_1 0 1033 #define RTW_PWR_TRK_5G_2 1 1034 #define RTW_PWR_TRK_5G_3 2 1035 #define RTW_PWR_TRK_5G_NUM 3 1036 1037 #define RTW_PWR_TRK_TBL_SZ 30 1038 1039 /* This table stores the values of TX power that will be adjusted by power 1040 * tracking. 1041 * 1042 * For 5G bands, there are 3 different settings. 1043 * For 2G there are cck rate and ofdm rate with different settings. 1044 */ 1045 struct rtw_pwr_track_tbl { 1046 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1047 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1048 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1049 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1050 const u8 *pwrtrk_2gb_n; 1051 const u8 *pwrtrk_2gb_p; 1052 const u8 *pwrtrk_2ga_n; 1053 const u8 *pwrtrk_2ga_p; 1054 const u8 *pwrtrk_2g_cckb_n; 1055 const u8 *pwrtrk_2g_cckb_p; 1056 const u8 *pwrtrk_2g_ccka_n; 1057 const u8 *pwrtrk_2g_ccka_p; 1058 }; 1059 1060 enum rtw_wlan_cpu { 1061 RTW_WCPU_11AC, 1062 RTW_WCPU_11N, 1063 }; 1064 1065 /* hardware configuration for each IC */ 1066 struct rtw_chip_info { 1067 struct rtw_chip_ops *ops; 1068 u8 id; 1069 1070 const char *fw_name; 1071 enum rtw_wlan_cpu wlan_cpu; 1072 u8 tx_pkt_desc_sz; 1073 u8 tx_buf_desc_sz; 1074 u8 rx_pkt_desc_sz; 1075 u8 rx_buf_desc_sz; 1076 u32 phy_efuse_size; 1077 u32 log_efuse_size; 1078 u32 ptct_efuse_size; 1079 u32 txff_size; 1080 u32 rxff_size; 1081 u8 band; 1082 u8 page_size; 1083 u8 csi_buf_pg_num; 1084 u8 dig_max; 1085 u8 dig_min; 1086 u8 txgi_factor; 1087 bool is_pwr_by_rate_dec; 1088 bool rx_ldpc; 1089 u8 max_power_index; 1090 1091 bool ht_supported; 1092 bool vht_supported; 1093 u8 lps_deep_mode_supported; 1094 1095 /* init values */ 1096 u8 sys_func_en; 1097 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1098 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1099 const struct rtw_rqpn *rqpn_table; 1100 const struct rtw_page_table *page_table; 1101 const struct rtw_intf_phy_para_table *intf_table; 1102 1103 const struct rtw_hw_reg *dig; 1104 const struct rtw_hw_reg *dig_cck; 1105 u32 rf_base_addr[2]; 1106 u32 rf_sipi_addr[2]; 1107 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1108 u8 fix_rf_phy_num; 1109 1110 const struct rtw_table *mac_tbl; 1111 const struct rtw_table *agc_tbl; 1112 const struct rtw_table *bb_tbl; 1113 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1114 const struct rtw_table *rfk_init_tbl; 1115 1116 const struct rtw_rfe_def *rfe_defs; 1117 u32 rfe_defs_size; 1118 1119 bool en_dis_dpd; 1120 u16 dpd_ratemask; 1121 u8 iqk_threshold; 1122 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1123 1124 u8 bfer_su_max_num; 1125 u8 bfer_mu_max_num; 1126 1127 const char *wow_fw_name; 1128 const struct wiphy_wowlan_support *wowlan_stub; 1129 const u8 max_sched_scan_ssids; 1130 1131 /* coex paras */ 1132 u32 coex_para_ver; 1133 u8 bt_desired_ver; 1134 bool scbd_support; 1135 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1136 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1137 u8 bt_rssi_type; 1138 u8 ant_isolation; 1139 u8 rssi_tolerance; 1140 u8 table_sant_num; 1141 u8 table_nsant_num; 1142 u8 tdma_sant_num; 1143 u8 tdma_nsant_num; 1144 u8 bt_afh_span_bw20; 1145 u8 bt_afh_span_bw40; 1146 u8 afh_5g_num; 1147 u8 wl_rf_para_num; 1148 u8 coex_info_hw_regs_num; 1149 const u8 *bt_rssi_step; 1150 const u8 *wl_rssi_step; 1151 const struct coex_table_para *table_nsant; 1152 const struct coex_table_para *table_sant; 1153 const struct coex_tdma_para *tdma_sant; 1154 const struct coex_tdma_para *tdma_nsant; 1155 const struct coex_rf_para *wl_rf_para_tx; 1156 const struct coex_rf_para *wl_rf_para_rx; 1157 const struct coex_5g_afh_map *afh_5g; 1158 const struct rtw_reg_domain *coex_info_hw_regs; 1159 }; 1160 1161 enum rtw_coex_bt_state_cnt { 1162 COEX_CNT_BT_RETRY, 1163 COEX_CNT_BT_REINIT, 1164 COEX_CNT_BT_REENABLE, 1165 COEX_CNT_BT_POPEVENT, 1166 COEX_CNT_BT_SETUPLINK, 1167 COEX_CNT_BT_IGNWLANACT, 1168 COEX_CNT_BT_INQ, 1169 COEX_CNT_BT_PAGE, 1170 COEX_CNT_BT_ROLESWITCH, 1171 COEX_CNT_BT_AFHUPDATE, 1172 COEX_CNT_BT_INFOUPDATE, 1173 COEX_CNT_BT_IQK, 1174 COEX_CNT_BT_IQKFAIL, 1175 1176 COEX_CNT_BT_MAX 1177 }; 1178 1179 enum rtw_coex_wl_state_cnt { 1180 COEX_CNT_WL_CONNPKT, 1181 COEX_CNT_WL_COEXRUN, 1182 COEX_CNT_WL_NOISY0, 1183 COEX_CNT_WL_NOISY1, 1184 COEX_CNT_WL_NOISY2, 1185 COEX_CNT_WL_5MS_NOEXTEND, 1186 COEX_CNT_WL_FW_NOTIFY, 1187 1188 COEX_CNT_WL_MAX 1189 }; 1190 1191 struct rtw_coex_rfe { 1192 bool ant_switch_exist; 1193 bool ant_switch_diversity; 1194 bool ant_switch_with_bt; 1195 u8 rfe_module_type; 1196 u8 ant_switch_polarity; 1197 1198 /* true if WLG at BTG, else at WLAG */ 1199 bool wlg_at_btg; 1200 }; 1201 1202 struct rtw_coex_dm { 1203 bool cur_ps_tdma_on; 1204 bool cur_wl_rx_low_gain_en; 1205 bool ignore_wl_act; 1206 1207 u8 reason; 1208 u8 bt_rssi_state[4]; 1209 u8 wl_rssi_state[4]; 1210 u8 wl_ch_info[3]; 1211 u8 cur_ps_tdma; 1212 u8 cur_table; 1213 u8 ps_tdma_para[5]; 1214 u8 cur_bt_pwr_lvl; 1215 u8 cur_bt_lna_lvl; 1216 u8 cur_wl_pwr_lvl; 1217 u8 bt_status; 1218 u32 cur_ant_pos_type; 1219 u32 cur_switch_status; 1220 u32 setting_tdma; 1221 }; 1222 1223 #define COEX_BTINFO_SRC_WL_FW 0x0 1224 #define COEX_BTINFO_SRC_BT_RSP 0x1 1225 #define COEX_BTINFO_SRC_BT_ACT 0x2 1226 #define COEX_BTINFO_SRC_BT_IQK 0x3 1227 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1228 #define COEX_BTINFO_SRC_MAX 0x5 1229 1230 #define COEX_INFO_FTP BIT(7) 1231 #define COEX_INFO_A2DP BIT(6) 1232 #define COEX_INFO_HID BIT(5) 1233 #define COEX_INFO_SCO_BUSY BIT(4) 1234 #define COEX_INFO_ACL_BUSY BIT(3) 1235 #define COEX_INFO_INQ_PAGE BIT(2) 1236 #define COEX_INFO_SCO_ESCO BIT(1) 1237 #define COEX_INFO_CONNECTION BIT(0) 1238 #define COEX_BTINFO_LENGTH_MAX 10 1239 1240 struct rtw_coex_stat { 1241 bool bt_disabled; 1242 bool bt_disabled_pre; 1243 bool bt_link_exist; 1244 bool bt_whck_test; 1245 bool bt_inq_page; 1246 bool bt_inq; 1247 bool bt_page; 1248 bool bt_ble_voice; 1249 bool bt_ble_exist; 1250 bool bt_hfp_exist; 1251 bool bt_a2dp_exist; 1252 bool bt_hid_exist; 1253 bool bt_pan_exist; /* PAN or OPP */ 1254 bool bt_opp_exist; /* OPP only */ 1255 bool bt_acl_busy; 1256 bool bt_fix_2M; 1257 bool bt_setup_link; 1258 bool bt_multi_link; 1259 bool bt_a2dp_sink; 1260 bool bt_a2dp_active; 1261 bool bt_reenable; 1262 bool bt_ble_scan_en; 1263 bool bt_init_scan; 1264 bool bt_slave; 1265 bool bt_418_hid_exist; 1266 bool bt_mailbox_reply; 1267 1268 bool wl_under_lps; 1269 bool wl_under_ips; 1270 bool wl_hi_pri_task1; 1271 bool wl_hi_pri_task2; 1272 bool wl_force_lps_ctrl; 1273 bool wl_gl_busy; 1274 bool wl_linkscan_proc; 1275 bool wl_ps_state_fail; 1276 bool wl_tx_limit_en; 1277 bool wl_ampdu_limit_en; 1278 bool wl_connected; 1279 bool wl_slot_extend; 1280 bool wl_cck_lock; 1281 bool wl_cck_lock_pre; 1282 bool wl_cck_lock_ever; 1283 1284 u32 bt_supported_version; 1285 u32 bt_supported_feature; 1286 u32 patch_ver; 1287 u16 bt_reg_vendor_ae; 1288 u16 bt_reg_vendor_ac; 1289 s8 bt_rssi; 1290 u8 kt_ver; 1291 u8 gnt_workaround_state; 1292 u8 tdma_timer_base; 1293 u8 bt_profile_num; 1294 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1295 u8 bt_info_lb2; 1296 u8 bt_info_lb3; 1297 u8 bt_info_hb0; 1298 u8 bt_info_hb1; 1299 u8 bt_info_hb2; 1300 u8 bt_info_hb3; 1301 u8 bt_ble_scan_type; 1302 u8 bt_hid_pair_num; 1303 u8 bt_hid_slot; 1304 u8 bt_a2dp_bitpool; 1305 u8 bt_iqk_state; 1306 1307 u8 wl_noisy_level; 1308 u8 wl_fw_dbg_info[10]; 1309 u8 wl_fw_dbg_info_pre[10]; 1310 u8 wl_coex_mode; 1311 u8 ampdu_max_time; 1312 u8 wl_tput_dir; 1313 1314 u16 score_board; 1315 u16 retry_limit; 1316 1317 /* counters to record bt states */ 1318 u32 cnt_bt[COEX_CNT_BT_MAX]; 1319 1320 /* counters to record wifi states */ 1321 u32 cnt_wl[COEX_CNT_WL_MAX]; 1322 1323 u32 darfrc; 1324 u32 darfrch; 1325 }; 1326 1327 struct rtw_coex { 1328 /* protects coex info request section */ 1329 struct mutex mutex; 1330 struct sk_buff_head queue; 1331 wait_queue_head_t wait; 1332 1333 bool under_5g; 1334 bool stop_dm; 1335 bool freeze; 1336 bool freerun; 1337 bool wl_rf_off; 1338 1339 struct rtw_coex_stat stat; 1340 struct rtw_coex_dm dm; 1341 struct rtw_coex_rfe rfe; 1342 1343 struct delayed_work bt_relink_work; 1344 struct delayed_work bt_reenable_work; 1345 struct delayed_work defreeze_work; 1346 }; 1347 1348 #define DPK_RF_REG_NUM 7 1349 #define DPK_RF_PATH_NUM 2 1350 #define DPK_BB_REG_NUM 18 1351 #define DPK_CHANNEL_WIDTH_80 1 1352 1353 DECLARE_EWMA(thermal, 10, 4); 1354 1355 struct rtw_dpk_info { 1356 bool is_dpk_pwr_on; 1357 bool is_reload; 1358 1359 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1360 1361 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1362 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1363 1364 u32 gnt_control; 1365 u32 gnt_value; 1366 1367 u8 result[RTW_RF_PATH_MAX]; 1368 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1369 u32 coef[RTW_RF_PATH_MAX][20]; 1370 u16 dpk_gs[RTW_RF_PATH_MAX]; 1371 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1372 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1373 1374 u8 dpk_band; 1375 u8 dpk_ch; 1376 u8 dpk_bw; 1377 }; 1378 1379 struct rtw_phy_cck_pd_reg { 1380 u32 reg_pd; 1381 u32 mask_pd; 1382 u32 reg_cs; 1383 u32 mask_cs; 1384 }; 1385 1386 #define DACK_MSBK_BACKUP_NUM 0xf 1387 #define DACK_DCK_BACKUP_NUM 0x2 1388 1389 struct rtw_swing_table { 1390 const u8 *p[RTW_RF_PATH_MAX]; 1391 const u8 *n[RTW_RF_PATH_MAX]; 1392 }; 1393 1394 struct rtw_pkt_count { 1395 u16 num_bcn_pkt; 1396 u16 num_qry_pkt[DESC_RATE_MAX]; 1397 }; 1398 1399 DECLARE_EWMA(evm, 10, 4); 1400 DECLARE_EWMA(snr, 10, 4); 1401 1402 struct rtw_dm_info { 1403 u32 cck_fa_cnt; 1404 u32 ofdm_fa_cnt; 1405 u32 total_fa_cnt; 1406 u32 cck_cca_cnt; 1407 u32 ofdm_cca_cnt; 1408 u32 total_cca_cnt; 1409 1410 u32 cck_ok_cnt; 1411 u32 cck_err_cnt; 1412 u32 ofdm_ok_cnt; 1413 u32 ofdm_err_cnt; 1414 u32 ht_ok_cnt; 1415 u32 ht_err_cnt; 1416 u32 vht_ok_cnt; 1417 u32 vht_err_cnt; 1418 1419 u8 min_rssi; 1420 u8 pre_min_rssi; 1421 u16 fa_history[4]; 1422 u8 igi_history[4]; 1423 u8 igi_bitmap; 1424 bool damping; 1425 u8 damping_cnt; 1426 u8 damping_rssi; 1427 1428 u8 cck_gi_u_bnd; 1429 u8 cck_gi_l_bnd; 1430 1431 u8 tx_rate; 1432 u8 thermal_avg[RTW_RF_PATH_MAX]; 1433 u8 thermal_meter_k; 1434 s8 delta_power_index[RTW_RF_PATH_MAX]; 1435 u8 default_ofdm_index; 1436 bool pwr_trk_triggered; 1437 bool pwr_trk_init_trigger; 1438 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1439 1440 /* backup dack results for each path and I/Q */ 1441 u32 dack_adck[RTW_RF_PATH_MAX]; 1442 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1443 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1444 1445 struct rtw_dpk_info dpk_info; 1446 1447 /* [bandwidth 0:20M/1:40M][number of path] */ 1448 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1449 u32 cck_fa_avg; 1450 1451 /* save the last rx phy status for debug */ 1452 s8 rx_snr[RTW_RF_PATH_MAX]; 1453 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1454 s16 cfo_tail[RTW_RF_PATH_MAX]; 1455 u8 rssi[RTW_RF_PATH_MAX]; 1456 u8 curr_rx_rate; 1457 struct rtw_pkt_count cur_pkt_count; 1458 struct rtw_pkt_count last_pkt_count; 1459 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1460 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1461 }; 1462 1463 struct rtw_efuse { 1464 u32 size; 1465 u32 physical_size; 1466 u32 logical_size; 1467 u32 protect_size; 1468 1469 u8 addr[ETH_ALEN]; 1470 u8 channel_plan; 1471 u8 country_code[2]; 1472 u8 rf_board_option; 1473 u8 rfe_option; 1474 u8 power_track_type; 1475 u8 thermal_meter[RTW_RF_PATH_MAX]; 1476 u8 thermal_meter_k; 1477 u8 crystal_cap; 1478 u8 ant_div_cfg; 1479 u8 ant_div_type; 1480 u8 regd; 1481 u8 afe; 1482 1483 u8 lna_type_2g; 1484 u8 lna_type_5g; 1485 u8 glna_type; 1486 u8 alna_type; 1487 bool ext_lna_2g; 1488 bool ext_lna_5g; 1489 u8 pa_type_2g; 1490 u8 pa_type_5g; 1491 u8 gpa_type; 1492 u8 apa_type; 1493 bool ext_pa_2g; 1494 bool ext_pa_5g; 1495 1496 bool btcoex; 1497 /* bt share antenna with wifi */ 1498 bool share_ant; 1499 u8 bt_setting; 1500 1501 struct { 1502 u8 hci; 1503 u8 bw; 1504 u8 ptcl; 1505 u8 nss; 1506 u8 ant_num; 1507 } hw_cap; 1508 1509 struct rtw_txpwr_idx txpwr_idx_table[4]; 1510 }; 1511 1512 struct rtw_phy_cond { 1513 #ifdef __LITTLE_ENDIAN 1514 u32 rfe:8; 1515 u32 intf:4; 1516 u32 pkg:4; 1517 u32 plat:4; 1518 u32 intf_rsvd:4; 1519 u32 cut:4; 1520 u32 branch:2; 1521 u32 neg:1; 1522 u32 pos:1; 1523 #else 1524 u32 pos:1; 1525 u32 neg:1; 1526 u32 branch:2; 1527 u32 cut:4; 1528 u32 intf_rsvd:4; 1529 u32 plat:4; 1530 u32 pkg:4; 1531 u32 intf:4; 1532 u32 rfe:8; 1533 #endif 1534 /* for intf:4 */ 1535 #define INTF_PCIE BIT(0) 1536 #define INTF_USB BIT(1) 1537 #define INTF_SDIO BIT(2) 1538 /* for branch:2 */ 1539 #define BRANCH_IF 0 1540 #define BRANCH_ELIF 1 1541 #define BRANCH_ELSE 2 1542 #define BRANCH_ENDIF 3 1543 }; 1544 1545 struct rtw_fifo_conf { 1546 /* tx fifo information */ 1547 u16 rsvd_boundary; 1548 u16 rsvd_pg_num; 1549 u16 rsvd_drv_pg_num; 1550 u16 txff_pg_num; 1551 u16 acq_pg_num; 1552 u16 rsvd_drv_addr; 1553 u16 rsvd_h2c_info_addr; 1554 u16 rsvd_h2c_sta_info_addr; 1555 u16 rsvd_h2cq_addr; 1556 u16 rsvd_cpu_instr_addr; 1557 u16 rsvd_fw_txbuf_addr; 1558 u16 rsvd_csibuf_addr; 1559 const struct rtw_rqpn *rqpn; 1560 }; 1561 1562 struct rtw_fw_state { 1563 const struct firmware *firmware; 1564 struct rtw_dev *rtwdev; 1565 struct completion completion; 1566 u16 version; 1567 u8 sub_version; 1568 u8 sub_index; 1569 u16 h2c_version; 1570 }; 1571 1572 struct rtw_hal { 1573 u32 rcr; 1574 1575 u32 chip_version; 1576 u8 cut_version; 1577 u8 mp_chip; 1578 u8 oem_id; 1579 struct rtw_phy_cond phy_cond; 1580 1581 u8 ps_mode; 1582 u8 current_channel; 1583 u8 current_band_width; 1584 u8 current_band_type; 1585 1586 /* center channel for different available bandwidth, 1587 * val of (bw > current_band_width) is invalid 1588 */ 1589 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1590 1591 u8 sec_ch_offset; 1592 u8 rf_type; 1593 u8 rf_path_num; 1594 u8 rf_phy_num; 1595 u32 antenna_tx; 1596 u32 antenna_rx; 1597 u8 bfee_sts_cap; 1598 1599 /* protect tx power section */ 1600 struct mutex tx_power_mutex; 1601 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1602 [DESC_RATE_MAX]; 1603 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1604 [DESC_RATE_MAX]; 1605 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1606 [RTW_RATE_SECTION_MAX]; 1607 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1608 [RTW_RATE_SECTION_MAX]; 1609 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1610 [RTW_CHANNEL_WIDTH_MAX] 1611 [RTW_RATE_SECTION_MAX] 1612 [RTW_MAX_CHANNEL_NUM_2G]; 1613 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1614 [RTW_CHANNEL_WIDTH_MAX] 1615 [RTW_RATE_SECTION_MAX] 1616 [RTW_MAX_CHANNEL_NUM_5G]; 1617 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1618 [DESC_RATE_MAX]; 1619 }; 1620 1621 struct rtw_dev { 1622 struct ieee80211_hw *hw; 1623 struct device *dev; 1624 1625 struct rtw_hci hci; 1626 1627 struct rtw_chip_info *chip; 1628 struct rtw_hal hal; 1629 struct rtw_fifo_conf fifo; 1630 struct rtw_fw_state fw; 1631 struct rtw_efuse efuse; 1632 struct rtw_sec_desc sec; 1633 struct rtw_traffic_stats stats; 1634 struct rtw_regulatory regd; 1635 struct rtw_bf_info bf_info; 1636 1637 struct rtw_dm_info dm_info; 1638 struct rtw_coex coex; 1639 1640 /* ensures exclusive access from mac80211 callbacks */ 1641 struct mutex mutex; 1642 1643 /* read/write rf register */ 1644 spinlock_t rf_lock; 1645 1646 /* watch dog every 2 sec */ 1647 struct delayed_work watch_dog_work; 1648 u32 watch_dog_cnt; 1649 1650 struct list_head rsvd_page_list; 1651 1652 /* c2h cmd queue & handler work */ 1653 struct sk_buff_head c2h_queue; 1654 struct work_struct c2h_work; 1655 1656 /* used to protect txqs list */ 1657 spinlock_t txq_lock; 1658 struct list_head txqs; 1659 struct tasklet_struct tx_tasklet; 1660 struct work_struct ba_work; 1661 1662 struct rtw_tx_report tx_report; 1663 1664 struct { 1665 /* incicate the mail box to use with fw */ 1666 u8 last_box_num; 1667 /* protect to send h2c to fw */ 1668 spinlock_t lock; 1669 u32 seq; 1670 } h2c; 1671 1672 /* lps power state & handler work */ 1673 struct rtw_lps_conf lps_conf; 1674 bool ps_enabled; 1675 1676 struct dentry *debugfs; 1677 1678 u8 sta_cnt; 1679 u32 rts_threshold; 1680 1681 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1682 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1683 1684 u8 mp_mode; 1685 1686 struct rtw_fw_state wow_fw; 1687 struct rtw_wow_param wow; 1688 1689 /* hci related data, must be last */ 1690 u8 priv[] __aligned(sizeof(void *)); 1691 }; 1692 1693 #include "hci.h" 1694 1695 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1696 { 1697 return !!rtwdev->sta_cnt; 1698 } 1699 1700 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1701 { 1702 void *p = rtwtxq; 1703 1704 return container_of(p, struct ieee80211_txq, drv_priv); 1705 } 1706 1707 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1708 { 1709 void *p = rtwvif; 1710 1711 return container_of(p, struct ieee80211_vif, drv_priv); 1712 } 1713 1714 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1715 struct cfg80211_ssid *b) 1716 { 1717 if (!a || !b || a->ssid_len != b->ssid_len) 1718 return false; 1719 1720 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1721 return false; 1722 1723 return true; 1724 } 1725 1726 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 1727 { 1728 if (rtwdev->chip->ops->efuse_grant) 1729 rtwdev->chip->ops->efuse_grant(rtwdev, true); 1730 } 1731 1732 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 1733 { 1734 if (rtwdev->chip->ops->efuse_grant) 1735 rtwdev->chip->ops->efuse_grant(rtwdev, false); 1736 } 1737 1738 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 1739 { 1740 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 1741 } 1742 1743 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 1744 { 1745 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 1746 } 1747 1748 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 1749 { 1750 return rtwdev->chip->rx_ldpc; 1751 } 1752 1753 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1754 struct rtw_channel_params *ch_param); 1755 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1756 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1757 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1758 void rtw_restore_reg(struct rtw_dev *rtwdev, 1759 struct rtw_backup_info *bckp, u32 num); 1760 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1761 void rtw_set_channel(struct rtw_dev *rtwdev); 1762 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1763 u32 config); 1764 void rtw_tx_report_purge_timer(struct timer_list *t); 1765 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1766 int rtw_core_start(struct rtw_dev *rtwdev); 1767 void rtw_core_stop(struct rtw_dev *rtwdev); 1768 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1769 int rtw_core_init(struct rtw_dev *rtwdev); 1770 void rtw_core_deinit(struct rtw_dev *rtwdev); 1771 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1772 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1773 u16 rtw_desc_to_bitrate(u8 desc_rate); 1774 1775 #endif 1776