1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 18 #include "util.h" 19 20 #define RTW_NAPI_WEIGHT_NUM 64 21 #define RTW_MAX_MAC_ID_NUM 32 22 #define RTW_MAX_SEC_CAM_NUM 32 23 #define MAX_PG_CAM_BACKUP_NUM 8 24 25 #define RTW_MAX_PATTERN_NUM 12 26 #define RTW_MAX_PATTERN_MASK_SIZE 16 27 #define RTW_MAX_PATTERN_SIZE 128 28 29 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 30 31 #define RFREG_MASK 0xfffff 32 #define INV_RF_DATA 0xffffffff 33 #define TX_PAGE_SIZE_SHIFT 7 34 35 #define RTW_CHANNEL_WIDTH_MAX 3 36 #define RTW_RF_PATH_MAX 4 37 #define HW_FEATURE_LEN 13 38 39 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 40 41 extern bool rtw_bf_support; 42 extern bool rtw_disable_lps_deep_mode; 43 extern unsigned int rtw_debug_mask; 44 extern bool rtw_edcca_enabled; 45 extern const struct ieee80211_ops rtw_ops; 46 47 #define RTW_MAX_CHANNEL_NUM_2G 14 48 #define RTW_MAX_CHANNEL_NUM_5G 49 49 50 struct rtw_dev; 51 52 enum rtw_hci_type { 53 RTW_HCI_TYPE_PCIE, 54 RTW_HCI_TYPE_USB, 55 RTW_HCI_TYPE_SDIO, 56 57 RTW_HCI_TYPE_UNDEFINE, 58 }; 59 60 struct rtw_hci { 61 struct rtw_hci_ops *ops; 62 enum rtw_hci_type type; 63 64 u32 rpwm_addr; 65 u32 cpwm_addr; 66 67 u8 bulkout_num; 68 }; 69 70 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 71 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 72 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 73 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 74 75 #define IS_CH_5G_BAND_MID(channel) \ 76 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 77 78 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 79 #define IS_CH_5G_BAND(channel) \ 80 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 81 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 82 83 enum rtw_supported_band { 84 RTW_BAND_2G = 1 << 0, 85 RTW_BAND_5G = 1 << 1, 86 RTW_BAND_60G = 1 << 2, 87 88 RTW_BAND_MAX, 89 }; 90 91 /* now, support upto 80M bw */ 92 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 93 94 enum rtw_bandwidth { 95 RTW_CHANNEL_WIDTH_20 = 0, 96 RTW_CHANNEL_WIDTH_40 = 1, 97 RTW_CHANNEL_WIDTH_80 = 2, 98 RTW_CHANNEL_WIDTH_160 = 3, 99 RTW_CHANNEL_WIDTH_80_80 = 4, 100 RTW_CHANNEL_WIDTH_5 = 5, 101 RTW_CHANNEL_WIDTH_10 = 6, 102 }; 103 104 enum rtw_sc_offset { 105 RTW_SC_DONT_CARE = 0, 106 RTW_SC_20_UPPER = 1, 107 RTW_SC_20_LOWER = 2, 108 RTW_SC_20_UPMOST = 3, 109 RTW_SC_20_LOWEST = 4, 110 RTW_SC_40_UPPER = 9, 111 RTW_SC_40_LOWER = 10, 112 }; 113 114 enum rtw_net_type { 115 RTW_NET_NO_LINK = 0, 116 RTW_NET_AD_HOC = 1, 117 RTW_NET_MGD_LINKED = 2, 118 RTW_NET_AP_MODE = 3, 119 }; 120 121 enum rtw_rf_type { 122 RF_1T1R = 0, 123 RF_1T2R = 1, 124 RF_2T2R = 2, 125 RF_2T3R = 3, 126 RF_2T4R = 4, 127 RF_3T3R = 5, 128 RF_3T4R = 6, 129 RF_4T4R = 7, 130 RF_TYPE_MAX, 131 }; 132 133 enum rtw_rf_path { 134 RF_PATH_A = 0, 135 RF_PATH_B = 1, 136 RF_PATH_C = 2, 137 RF_PATH_D = 3, 138 }; 139 140 enum rtw_bb_path { 141 BB_PATH_A = BIT(0), 142 BB_PATH_B = BIT(1), 143 BB_PATH_C = BIT(2), 144 BB_PATH_D = BIT(3), 145 146 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 147 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 148 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 149 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 150 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 151 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 152 153 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 154 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 155 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 156 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 157 158 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 159 }; 160 161 enum rtw_rate_section { 162 RTW_RATE_SECTION_CCK = 0, 163 RTW_RATE_SECTION_OFDM, 164 RTW_RATE_SECTION_HT_1S, 165 RTW_RATE_SECTION_HT_2S, 166 RTW_RATE_SECTION_VHT_1S, 167 RTW_RATE_SECTION_VHT_2S, 168 169 /* keep last */ 170 RTW_RATE_SECTION_MAX, 171 }; 172 173 enum rtw_wireless_set { 174 WIRELESS_CCK = 0x00000001, 175 WIRELESS_OFDM = 0x00000002, 176 WIRELESS_HT = 0x00000004, 177 WIRELESS_VHT = 0x00000008, 178 }; 179 180 #define HT_STBC_EN BIT(0) 181 #define VHT_STBC_EN BIT(1) 182 #define HT_LDPC_EN BIT(0) 183 #define VHT_LDPC_EN BIT(1) 184 185 enum rtw_chip_type { 186 RTW_CHIP_TYPE_8822B, 187 RTW_CHIP_TYPE_8822C, 188 RTW_CHIP_TYPE_8723D, 189 RTW_CHIP_TYPE_8821C, 190 }; 191 192 enum rtw_tx_queue_type { 193 /* the order of AC queues matters */ 194 RTW_TX_QUEUE_BK = 0x0, 195 RTW_TX_QUEUE_BE = 0x1, 196 RTW_TX_QUEUE_VI = 0x2, 197 RTW_TX_QUEUE_VO = 0x3, 198 199 RTW_TX_QUEUE_BCN = 0x4, 200 RTW_TX_QUEUE_MGMT = 0x5, 201 RTW_TX_QUEUE_HI0 = 0x6, 202 RTW_TX_QUEUE_H2C = 0x7, 203 /* keep it last */ 204 RTK_MAX_TX_QUEUE_NUM 205 }; 206 207 enum rtw_rx_queue_type { 208 RTW_RX_QUEUE_MPDU = 0x0, 209 RTW_RX_QUEUE_C2H = 0x1, 210 /* keep it last */ 211 RTK_MAX_RX_QUEUE_NUM 212 }; 213 214 enum rtw_fw_type { 215 RTW_NORMAL_FW = 0x0, 216 RTW_WOWLAN_FW = 0x1, 217 }; 218 219 enum rtw_rate_index { 220 RTW_RATEID_BGN_40M_2SS = 0, 221 RTW_RATEID_BGN_40M_1SS = 1, 222 RTW_RATEID_BGN_20M_2SS = 2, 223 RTW_RATEID_BGN_20M_1SS = 3, 224 RTW_RATEID_GN_N2SS = 4, 225 RTW_RATEID_GN_N1SS = 5, 226 RTW_RATEID_BG = 6, 227 RTW_RATEID_G = 7, 228 RTW_RATEID_B_20M = 8, 229 RTW_RATEID_ARFR0_AC_2SS = 9, 230 RTW_RATEID_ARFR1_AC_1SS = 10, 231 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 232 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 233 RTW_RATEID_ARFR4_AC_3SS = 13, 234 RTW_RATEID_ARFR5_N_3SS = 14, 235 RTW_RATEID_ARFR7_N_4SS = 15, 236 RTW_RATEID_ARFR6_AC_4SS = 16 237 }; 238 239 enum rtw_trx_desc_rate { 240 DESC_RATE1M = 0x00, 241 DESC_RATE2M = 0x01, 242 DESC_RATE5_5M = 0x02, 243 DESC_RATE11M = 0x03, 244 245 DESC_RATE6M = 0x04, 246 DESC_RATE9M = 0x05, 247 DESC_RATE12M = 0x06, 248 DESC_RATE18M = 0x07, 249 DESC_RATE24M = 0x08, 250 DESC_RATE36M = 0x09, 251 DESC_RATE48M = 0x0a, 252 DESC_RATE54M = 0x0b, 253 254 DESC_RATEMCS0 = 0x0c, 255 DESC_RATEMCS1 = 0x0d, 256 DESC_RATEMCS2 = 0x0e, 257 DESC_RATEMCS3 = 0x0f, 258 DESC_RATEMCS4 = 0x10, 259 DESC_RATEMCS5 = 0x11, 260 DESC_RATEMCS6 = 0x12, 261 DESC_RATEMCS7 = 0x13, 262 DESC_RATEMCS8 = 0x14, 263 DESC_RATEMCS9 = 0x15, 264 DESC_RATEMCS10 = 0x16, 265 DESC_RATEMCS11 = 0x17, 266 DESC_RATEMCS12 = 0x18, 267 DESC_RATEMCS13 = 0x19, 268 DESC_RATEMCS14 = 0x1a, 269 DESC_RATEMCS15 = 0x1b, 270 DESC_RATEMCS16 = 0x1c, 271 DESC_RATEMCS17 = 0x1d, 272 DESC_RATEMCS18 = 0x1e, 273 DESC_RATEMCS19 = 0x1f, 274 DESC_RATEMCS20 = 0x20, 275 DESC_RATEMCS21 = 0x21, 276 DESC_RATEMCS22 = 0x22, 277 DESC_RATEMCS23 = 0x23, 278 DESC_RATEMCS24 = 0x24, 279 DESC_RATEMCS25 = 0x25, 280 DESC_RATEMCS26 = 0x26, 281 DESC_RATEMCS27 = 0x27, 282 DESC_RATEMCS28 = 0x28, 283 DESC_RATEMCS29 = 0x29, 284 DESC_RATEMCS30 = 0x2a, 285 DESC_RATEMCS31 = 0x2b, 286 287 DESC_RATEVHT1SS_MCS0 = 0x2c, 288 DESC_RATEVHT1SS_MCS1 = 0x2d, 289 DESC_RATEVHT1SS_MCS2 = 0x2e, 290 DESC_RATEVHT1SS_MCS3 = 0x2f, 291 DESC_RATEVHT1SS_MCS4 = 0x30, 292 DESC_RATEVHT1SS_MCS5 = 0x31, 293 DESC_RATEVHT1SS_MCS6 = 0x32, 294 DESC_RATEVHT1SS_MCS7 = 0x33, 295 DESC_RATEVHT1SS_MCS8 = 0x34, 296 DESC_RATEVHT1SS_MCS9 = 0x35, 297 298 DESC_RATEVHT2SS_MCS0 = 0x36, 299 DESC_RATEVHT2SS_MCS1 = 0x37, 300 DESC_RATEVHT2SS_MCS2 = 0x38, 301 DESC_RATEVHT2SS_MCS3 = 0x39, 302 DESC_RATEVHT2SS_MCS4 = 0x3a, 303 DESC_RATEVHT2SS_MCS5 = 0x3b, 304 DESC_RATEVHT2SS_MCS6 = 0x3c, 305 DESC_RATEVHT2SS_MCS7 = 0x3d, 306 DESC_RATEVHT2SS_MCS8 = 0x3e, 307 DESC_RATEVHT2SS_MCS9 = 0x3f, 308 309 DESC_RATEVHT3SS_MCS0 = 0x40, 310 DESC_RATEVHT3SS_MCS1 = 0x41, 311 DESC_RATEVHT3SS_MCS2 = 0x42, 312 DESC_RATEVHT3SS_MCS3 = 0x43, 313 DESC_RATEVHT3SS_MCS4 = 0x44, 314 DESC_RATEVHT3SS_MCS5 = 0x45, 315 DESC_RATEVHT3SS_MCS6 = 0x46, 316 DESC_RATEVHT3SS_MCS7 = 0x47, 317 DESC_RATEVHT3SS_MCS8 = 0x48, 318 DESC_RATEVHT3SS_MCS9 = 0x49, 319 320 DESC_RATEVHT4SS_MCS0 = 0x4a, 321 DESC_RATEVHT4SS_MCS1 = 0x4b, 322 DESC_RATEVHT4SS_MCS2 = 0x4c, 323 DESC_RATEVHT4SS_MCS3 = 0x4d, 324 DESC_RATEVHT4SS_MCS4 = 0x4e, 325 DESC_RATEVHT4SS_MCS5 = 0x4f, 326 DESC_RATEVHT4SS_MCS6 = 0x50, 327 DESC_RATEVHT4SS_MCS7 = 0x51, 328 DESC_RATEVHT4SS_MCS8 = 0x52, 329 DESC_RATEVHT4SS_MCS9 = 0x53, 330 331 DESC_RATE_MAX, 332 }; 333 334 enum rtw_regulatory_domains { 335 RTW_REGD_FCC = 0, 336 RTW_REGD_MKK = 1, 337 RTW_REGD_ETSI = 2, 338 RTW_REGD_IC = 3, 339 RTW_REGD_KCC = 4, 340 RTW_REGD_ACMA = 5, 341 RTW_REGD_CHILE = 6, 342 RTW_REGD_UKRAINE = 7, 343 RTW_REGD_MEXICO = 8, 344 RTW_REGD_CN = 9, 345 RTW_REGD_WW, 346 347 RTW_REGD_MAX 348 }; 349 350 enum rtw_txq_flags { 351 RTW_TXQ_AMPDU, 352 RTW_TXQ_BLOCK_BA, 353 }; 354 355 enum rtw_flags { 356 RTW_FLAG_RUNNING, 357 RTW_FLAG_FW_RUNNING, 358 RTW_FLAG_SCANNING, 359 RTW_FLAG_INACTIVE_PS, 360 RTW_FLAG_LEISURE_PS, 361 RTW_FLAG_LEISURE_PS_DEEP, 362 RTW_FLAG_DIG_DISABLE, 363 RTW_FLAG_BUSY_TRAFFIC, 364 RTW_FLAG_WOWLAN, 365 RTW_FLAG_RESTARTING, 366 RTW_FLAG_RESTART_TRIGGERING, 367 RTW_FLAG_FORCE_LOWEST_RATE, 368 369 NUM_OF_RTW_FLAGS, 370 }; 371 372 enum rtw_evm { 373 RTW_EVM_OFDM = 0, 374 RTW_EVM_1SS, 375 RTW_EVM_2SS_A, 376 RTW_EVM_2SS_B, 377 /* keep it last */ 378 RTW_EVM_NUM 379 }; 380 381 enum rtw_snr { 382 RTW_SNR_OFDM_A = 0, 383 RTW_SNR_OFDM_B, 384 RTW_SNR_OFDM_C, 385 RTW_SNR_OFDM_D, 386 RTW_SNR_1SS_A, 387 RTW_SNR_1SS_B, 388 RTW_SNR_1SS_C, 389 RTW_SNR_1SS_D, 390 RTW_SNR_2SS_A, 391 RTW_SNR_2SS_B, 392 RTW_SNR_2SS_C, 393 RTW_SNR_2SS_D, 394 /* keep it last */ 395 RTW_SNR_NUM 396 }; 397 398 enum rtw_wow_flags { 399 RTW_WOW_FLAG_EN_MAGIC_PKT, 400 RTW_WOW_FLAG_EN_REKEY_PKT, 401 RTW_WOW_FLAG_EN_DISCONNECT, 402 403 /* keep it last */ 404 RTW_WOW_FLAG_MAX, 405 }; 406 407 /* the power index is represented by differences, which cck-1s & ht40-1s are 408 * the base values, so for 1s's differences, there are only ht20 & ofdm 409 */ 410 struct rtw_2g_1s_pwr_idx_diff { 411 #ifdef __LITTLE_ENDIAN 412 s8 ofdm:4; 413 s8 bw20:4; 414 #else 415 s8 bw20:4; 416 s8 ofdm:4; 417 #endif 418 } __packed; 419 420 struct rtw_2g_ns_pwr_idx_diff { 421 #ifdef __LITTLE_ENDIAN 422 s8 bw20:4; 423 s8 bw40:4; 424 s8 cck:4; 425 s8 ofdm:4; 426 #else 427 s8 ofdm:4; 428 s8 cck:4; 429 s8 bw40:4; 430 s8 bw20:4; 431 #endif 432 } __packed; 433 434 struct rtw_2g_txpwr_idx { 435 u8 cck_base[6]; 436 u8 bw40_base[5]; 437 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 438 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 439 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 440 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 441 }; 442 443 struct rtw_5g_ht_1s_pwr_idx_diff { 444 #ifdef __LITTLE_ENDIAN 445 s8 ofdm:4; 446 s8 bw20:4; 447 #else 448 s8 bw20:4; 449 s8 ofdm:4; 450 #endif 451 } __packed; 452 453 struct rtw_5g_ht_ns_pwr_idx_diff { 454 #ifdef __LITTLE_ENDIAN 455 s8 bw20:4; 456 s8 bw40:4; 457 #else 458 s8 bw40:4; 459 s8 bw20:4; 460 #endif 461 } __packed; 462 463 struct rtw_5g_ofdm_ns_pwr_idx_diff { 464 #ifdef __LITTLE_ENDIAN 465 s8 ofdm_3s:4; 466 s8 ofdm_2s:4; 467 s8 ofdm_4s:4; 468 s8 res:4; 469 #else 470 s8 res:4; 471 s8 ofdm_4s:4; 472 s8 ofdm_2s:4; 473 s8 ofdm_3s:4; 474 #endif 475 } __packed; 476 477 struct rtw_5g_vht_ns_pwr_idx_diff { 478 #ifdef __LITTLE_ENDIAN 479 s8 bw160:4; 480 s8 bw80:4; 481 #else 482 s8 bw80:4; 483 s8 bw160:4; 484 #endif 485 } __packed; 486 487 struct rtw_5g_txpwr_idx { 488 u8 bw40_base[14]; 489 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 490 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 491 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 492 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 493 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 494 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 495 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 496 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 497 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 498 }; 499 500 struct rtw_txpwr_idx { 501 struct rtw_2g_txpwr_idx pwr_idx_2g; 502 struct rtw_5g_txpwr_idx pwr_idx_5g; 503 }; 504 505 struct rtw_timer_list { 506 struct timer_list timer; 507 void (*function)(void *data); 508 void *args; 509 }; 510 511 struct rtw_channel_params { 512 u8 center_chan; 513 u8 bandwidth; 514 u8 primary_chan_idx; 515 /* center channel by different available bandwidth, 516 * val of (bw > current bandwidth) is invalid 517 */ 518 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 519 }; 520 521 struct rtw_hw_reg { 522 u32 addr; 523 u32 mask; 524 }; 525 526 struct rtw_ltecoex_addr { 527 u32 ctrl; 528 u32 wdata; 529 u32 rdata; 530 }; 531 532 struct rtw_reg_domain { 533 u32 addr; 534 u32 mask; 535 #define RTW_REG_DOMAIN_MAC32 0 536 #define RTW_REG_DOMAIN_MAC16 1 537 #define RTW_REG_DOMAIN_MAC8 2 538 #define RTW_REG_DOMAIN_RF_A 3 539 #define RTW_REG_DOMAIN_RF_B 4 540 #define RTW_REG_DOMAIN_NL 0xFF 541 u8 domain; 542 }; 543 544 struct rtw_rf_sipi_addr { 545 u32 hssi_1; 546 u32 hssi_2; 547 u32 lssi_read; 548 u32 lssi_read_pi; 549 }; 550 551 struct rtw_hw_reg_offset { 552 struct rtw_hw_reg hw_reg; 553 u8 offset; 554 }; 555 556 struct rtw_backup_info { 557 u8 len; 558 u32 reg; 559 u32 val; 560 }; 561 562 enum rtw_vif_port_set { 563 PORT_SET_MAC_ADDR = BIT(0), 564 PORT_SET_BSSID = BIT(1), 565 PORT_SET_NET_TYPE = BIT(2), 566 PORT_SET_AID = BIT(3), 567 PORT_SET_BCN_CTRL = BIT(4), 568 }; 569 570 struct rtw_vif_port { 571 struct rtw_hw_reg mac_addr; 572 struct rtw_hw_reg bssid; 573 struct rtw_hw_reg net_type; 574 struct rtw_hw_reg aid; 575 struct rtw_hw_reg bcn_ctrl; 576 }; 577 578 struct rtw_tx_pkt_info { 579 u32 tx_pkt_size; 580 u8 offset; 581 u8 pkt_offset; 582 u8 mac_id; 583 u8 rate_id; 584 u8 rate; 585 u8 qsel; 586 u8 bw; 587 u8 sec_type; 588 u8 sn; 589 bool ampdu_en; 590 u8 ampdu_factor; 591 u8 ampdu_density; 592 u16 seq; 593 bool stbc; 594 bool ldpc; 595 bool dis_rate_fallback; 596 bool bmc; 597 bool use_rate; 598 bool ls; 599 bool fs; 600 bool short_gi; 601 bool report; 602 bool rts; 603 bool dis_qselseq; 604 bool en_hwseq; 605 u8 hw_ssn_sel; 606 bool nav_use_hdr; 607 bool bt_null; 608 }; 609 610 struct rtw_rx_pkt_stat { 611 bool phy_status; 612 bool icv_err; 613 bool crc_err; 614 bool decrypted; 615 bool is_c2h; 616 617 s32 signal_power; 618 u16 pkt_len; 619 u8 bw; 620 u8 drv_info_sz; 621 u8 shift; 622 u8 rate; 623 u8 mac_id; 624 u8 cam_id; 625 u8 ppdu_cnt; 626 u32 tsf_low; 627 s8 rx_power[RTW_RF_PATH_MAX]; 628 u8 rssi; 629 u8 rxsc; 630 s8 rx_snr[RTW_RF_PATH_MAX]; 631 u8 rx_evm[RTW_RF_PATH_MAX]; 632 s8 cfo_tail[RTW_RF_PATH_MAX]; 633 634 struct rtw_sta_info *si; 635 struct ieee80211_vif *vif; 636 struct ieee80211_hdr *hdr; 637 }; 638 639 DECLARE_EWMA(tp, 10, 2); 640 641 struct rtw_traffic_stats { 642 /* units in bytes */ 643 u64 tx_unicast; 644 u64 rx_unicast; 645 646 /* count for packets */ 647 u64 tx_cnt; 648 u64 rx_cnt; 649 650 /* units in Mbps */ 651 u32 tx_throughput; 652 u32 rx_throughput; 653 struct ewma_tp tx_ewma_tp; 654 struct ewma_tp rx_ewma_tp; 655 }; 656 657 enum rtw_lps_mode { 658 RTW_MODE_ACTIVE = 0, 659 RTW_MODE_LPS = 1, 660 RTW_MODE_WMM_PS = 2, 661 }; 662 663 enum rtw_lps_deep_mode { 664 LPS_DEEP_MODE_NONE = 0, 665 LPS_DEEP_MODE_LCLK = 1, 666 LPS_DEEP_MODE_PG = 2, 667 }; 668 669 enum rtw_pwr_state { 670 RTW_RF_OFF = 0x0, 671 RTW_RF_ON = 0x4, 672 RTW_ALL_ON = 0xc, 673 }; 674 675 struct rtw_lps_conf { 676 enum rtw_lps_mode mode; 677 enum rtw_lps_deep_mode deep_mode; 678 enum rtw_lps_deep_mode wow_deep_mode; 679 enum rtw_pwr_state state; 680 u8 awake_interval; 681 u8 rlbm; 682 u8 smart_ps; 683 u8 port_id; 684 bool sec_cam_backup; 685 bool pattern_cam_backup; 686 }; 687 688 enum rtw_hw_key_type { 689 RTW_CAM_NONE = 0, 690 RTW_CAM_WEP40 = 1, 691 RTW_CAM_TKIP = 2, 692 RTW_CAM_AES = 4, 693 RTW_CAM_WEP104 = 5, 694 }; 695 696 struct rtw_cam_entry { 697 bool valid; 698 bool group; 699 u8 addr[ETH_ALEN]; 700 u8 hw_key_type; 701 struct ieee80211_key_conf *key; 702 }; 703 704 struct rtw_sec_desc { 705 /* search strategy */ 706 bool default_key_search; 707 708 u32 total_cam_num; 709 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 710 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 711 }; 712 713 struct rtw_tx_report { 714 /* protect the tx report queue */ 715 spinlock_t q_lock; 716 struct sk_buff_head queue; 717 atomic_t sn; 718 struct timer_list purge_timer; 719 }; 720 721 struct rtw_ra_report { 722 struct rate_info txrate; 723 u32 bit_rate; 724 u8 desc_rate; 725 }; 726 727 struct rtw_txq { 728 struct list_head list; 729 730 unsigned long flags; 731 unsigned long last_push; 732 }; 733 734 #define RTW_BC_MC_MACID 1 735 DECLARE_EWMA(rssi, 10, 16); 736 737 struct rtw_sta_info { 738 struct ieee80211_sta *sta; 739 struct ieee80211_vif *vif; 740 741 struct ewma_rssi avg_rssi; 742 u8 rssi_level; 743 744 u8 mac_id; 745 u8 rate_id; 746 enum rtw_bandwidth bw_mode; 747 enum rtw_rf_type rf_type; 748 enum rtw_wireless_set wireless_set; 749 u8 stbc_en:2; 750 u8 ldpc_en:2; 751 bool sgi_enable; 752 bool vht_enable; 753 bool updated; 754 u8 init_ra_lv; 755 u64 ra_mask; 756 757 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 758 759 struct rtw_ra_report ra_report; 760 761 bool use_cfg_mask; 762 struct cfg80211_bitrate_mask *mask; 763 }; 764 765 enum rtw_bfee_role { 766 RTW_BFEE_NONE, 767 RTW_BFEE_SU, 768 RTW_BFEE_MU 769 }; 770 771 struct rtw_bfee { 772 enum rtw_bfee_role role; 773 774 u16 p_aid; 775 u8 g_id; 776 u8 mac_addr[ETH_ALEN]; 777 u8 sound_dim; 778 779 /* SU-MIMO */ 780 u8 su_reg_index; 781 782 /* MU-MIMO */ 783 u16 aid; 784 }; 785 786 struct rtw_bf_info { 787 u8 bfer_mu_cnt; 788 u8 bfer_su_cnt; 789 DECLARE_BITMAP(bfer_su_reg_maping, 2); 790 u8 cur_csi_rpt_rate; 791 }; 792 793 struct rtw_vif { 794 enum rtw_net_type net_type; 795 u16 aid; 796 u8 mac_addr[ETH_ALEN]; 797 u8 bssid[ETH_ALEN]; 798 u8 port; 799 u8 bcn_ctrl; 800 struct list_head rsvd_page_list; 801 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 802 const struct rtw_vif_port *conf; 803 804 struct rtw_traffic_stats stats; 805 806 struct rtw_bfee bfee; 807 }; 808 809 struct rtw_regulatory { 810 char alpha2[2]; 811 u8 txpwr_regd_2g; 812 u8 txpwr_regd_5g; 813 }; 814 815 enum rtw_regd_state { 816 RTW_REGD_STATE_WORLDWIDE, 817 RTW_REGD_STATE_PROGRAMMED, 818 RTW_REGD_STATE_SETTING, 819 820 RTW_REGD_STATE_NR, 821 }; 822 823 struct rtw_regd { 824 enum rtw_regd_state state; 825 const struct rtw_regulatory *regulatory; 826 enum nl80211_dfs_regions dfs_region; 827 }; 828 829 struct rtw_chip_ops { 830 int (*mac_init)(struct rtw_dev *rtwdev); 831 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 832 void (*shutdown)(struct rtw_dev *rtwdev); 833 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 834 void (*phy_set_param)(struct rtw_dev *rtwdev); 835 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 836 u8 bandwidth, u8 primary_chan_idx); 837 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 838 struct rtw_rx_pkt_stat *pkt_stat, 839 struct ieee80211_rx_status *rx_status); 840 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 841 u32 addr, u32 mask); 842 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 843 u32 addr, u32 mask, u32 data); 844 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 845 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 846 u32 size); 847 int (*set_antenna)(struct rtw_dev *rtwdev, 848 u32 antenna_tx, 849 u32 antenna_rx); 850 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 851 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 852 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 853 void (*phy_calibration)(struct rtw_dev *rtwdev); 854 void (*dpk_track)(struct rtw_dev *rtwdev); 855 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 856 void (*pwr_track)(struct rtw_dev *rtwdev); 857 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 858 struct rtw_bfee *bfee, bool enable); 859 void (*set_gid_table)(struct rtw_dev *rtwdev, 860 struct ieee80211_vif *vif, 861 struct ieee80211_bss_conf *conf); 862 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 863 u8 fixrate_en, u8 *new_rate); 864 void (*adaptivity_init)(struct rtw_dev *rtwdev); 865 void (*adaptivity)(struct rtw_dev *rtwdev); 866 void (*cfo_init)(struct rtw_dev *rtwdev); 867 void (*cfo_track)(struct rtw_dev *rtwdev); 868 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 869 enum rtw_bb_path tx_path_1ss, 870 enum rtw_bb_path tx_path_cck, 871 bool is_tx2_path); 872 873 /* for coex */ 874 void (*coex_set_init)(struct rtw_dev *rtwdev); 875 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 876 u8 ctrl_type, u8 pos_type); 877 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 878 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 879 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 880 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 881 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 882 }; 883 884 #define RTW_PWR_POLLING_CNT 20000 885 886 #define RTW_PWR_CMD_READ 0x00 887 #define RTW_PWR_CMD_WRITE 0x01 888 #define RTW_PWR_CMD_POLLING 0x02 889 #define RTW_PWR_CMD_DELAY 0x03 890 #define RTW_PWR_CMD_END 0x04 891 892 /* define the base address of each block */ 893 #define RTW_PWR_ADDR_MAC 0x00 894 #define RTW_PWR_ADDR_USB 0x01 895 #define RTW_PWR_ADDR_PCIE 0x02 896 #define RTW_PWR_ADDR_SDIO 0x03 897 898 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 899 #define RTW_PWR_INTF_USB_MSK BIT(1) 900 #define RTW_PWR_INTF_PCI_MSK BIT(2) 901 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 902 903 #define RTW_PWR_CUT_TEST_MSK BIT(0) 904 #define RTW_PWR_CUT_A_MSK BIT(1) 905 #define RTW_PWR_CUT_B_MSK BIT(2) 906 #define RTW_PWR_CUT_C_MSK BIT(3) 907 #define RTW_PWR_CUT_D_MSK BIT(4) 908 #define RTW_PWR_CUT_E_MSK BIT(5) 909 #define RTW_PWR_CUT_F_MSK BIT(6) 910 #define RTW_PWR_CUT_G_MSK BIT(7) 911 #define RTW_PWR_CUT_ALL_MSK 0xFF 912 913 enum rtw_pwr_seq_cmd_delay_unit { 914 RTW_PWR_DELAY_US, 915 RTW_PWR_DELAY_MS, 916 }; 917 918 struct rtw_pwr_seq_cmd { 919 u16 offset; 920 u8 cut_mask; 921 u8 intf_mask; 922 u8 base:4; 923 u8 cmd:4; 924 u8 mask; 925 u8 value; 926 }; 927 928 enum rtw_chip_ver { 929 RTW_CHIP_VER_CUT_A = 0x00, 930 RTW_CHIP_VER_CUT_B = 0x01, 931 RTW_CHIP_VER_CUT_C = 0x02, 932 RTW_CHIP_VER_CUT_D = 0x03, 933 RTW_CHIP_VER_CUT_E = 0x04, 934 RTW_CHIP_VER_CUT_F = 0x05, 935 RTW_CHIP_VER_CUT_G = 0x06, 936 }; 937 938 #define RTW_INTF_PHY_PLATFORM_ALL 0 939 940 enum rtw_intf_phy_cut { 941 RTW_INTF_PHY_CUT_A = BIT(0), 942 RTW_INTF_PHY_CUT_B = BIT(1), 943 RTW_INTF_PHY_CUT_C = BIT(2), 944 RTW_INTF_PHY_CUT_D = BIT(3), 945 RTW_INTF_PHY_CUT_E = BIT(4), 946 RTW_INTF_PHY_CUT_F = BIT(5), 947 RTW_INTF_PHY_CUT_G = BIT(6), 948 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 949 }; 950 951 enum rtw_ip_sel { 952 RTW_IP_SEL_PHY = 0, 953 RTW_IP_SEL_MAC = 1, 954 RTW_IP_SEL_DBI = 2, 955 956 RTW_IP_SEL_UNDEF = 0xFFFF 957 }; 958 959 enum rtw_pq_map_id { 960 RTW_PQ_MAP_VO = 0x0, 961 RTW_PQ_MAP_VI = 0x1, 962 RTW_PQ_MAP_BE = 0x2, 963 RTW_PQ_MAP_BK = 0x3, 964 RTW_PQ_MAP_MG = 0x4, 965 RTW_PQ_MAP_HI = 0x5, 966 RTW_PQ_MAP_NUM = 0x6, 967 968 RTW_PQ_MAP_UNDEF, 969 }; 970 971 enum rtw_dma_mapping { 972 RTW_DMA_MAPPING_EXTRA = 0, 973 RTW_DMA_MAPPING_LOW = 1, 974 RTW_DMA_MAPPING_NORMAL = 2, 975 RTW_DMA_MAPPING_HIGH = 3, 976 977 RTW_DMA_MAPPING_MAX, 978 RTW_DMA_MAPPING_UNDEF, 979 }; 980 981 struct rtw_rqpn { 982 enum rtw_dma_mapping dma_map_vo; 983 enum rtw_dma_mapping dma_map_vi; 984 enum rtw_dma_mapping dma_map_be; 985 enum rtw_dma_mapping dma_map_bk; 986 enum rtw_dma_mapping dma_map_mg; 987 enum rtw_dma_mapping dma_map_hi; 988 }; 989 990 struct rtw_prioq_addr { 991 u32 rsvd; 992 u32 avail; 993 }; 994 995 struct rtw_prioq_addrs { 996 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 997 bool wsize; 998 }; 999 1000 struct rtw_page_table { 1001 u16 hq_num; 1002 u16 nq_num; 1003 u16 lq_num; 1004 u16 exq_num; 1005 u16 gapq_num; 1006 }; 1007 1008 struct rtw_intf_phy_para { 1009 u16 offset; 1010 u16 value; 1011 u16 ip_sel; 1012 u16 cut_mask; 1013 u16 platform; 1014 }; 1015 1016 struct rtw_wow_pattern { 1017 u16 crc; 1018 u8 type; 1019 u8 valid; 1020 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1021 }; 1022 1023 struct rtw_pno_request { 1024 bool inited; 1025 u32 match_set_cnt; 1026 struct cfg80211_match_set *match_sets; 1027 u8 channel_cnt; 1028 struct ieee80211_channel *channels; 1029 struct cfg80211_sched_scan_plan scan_plan; 1030 }; 1031 1032 struct rtw_wow_param { 1033 struct ieee80211_vif *wow_vif; 1034 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1035 u8 txpause; 1036 u8 pattern_cnt; 1037 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1038 1039 bool ips_enabled; 1040 struct rtw_pno_request pno_req; 1041 }; 1042 1043 struct rtw_intf_phy_para_table { 1044 const struct rtw_intf_phy_para *usb2_para; 1045 const struct rtw_intf_phy_para *usb3_para; 1046 const struct rtw_intf_phy_para *gen1_para; 1047 const struct rtw_intf_phy_para *gen2_para; 1048 u8 n_usb2_para; 1049 u8 n_usb3_para; 1050 u8 n_gen1_para; 1051 u8 n_gen2_para; 1052 }; 1053 1054 struct rtw_table { 1055 const void *data; 1056 const u32 size; 1057 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1058 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1059 u32 addr, u32 data); 1060 enum rtw_rf_path rf_path; 1061 }; 1062 1063 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1064 const struct rtw_table *tbl) 1065 { 1066 (*tbl->parse)(rtwdev, tbl); 1067 } 1068 1069 enum rtw_rfe_fem { 1070 RTW_RFE_IFEM, 1071 RTW_RFE_EFEM, 1072 RTW_RFE_IFEM2G_EFEM5G, 1073 RTW_RFE_NUM, 1074 }; 1075 1076 struct rtw_rfe_def { 1077 const struct rtw_table *phy_pg_tbl; 1078 const struct rtw_table *txpwr_lmt_tbl; 1079 const struct rtw_table *agc_btg_tbl; 1080 }; 1081 1082 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1083 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1084 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1085 } 1086 1087 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1088 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1089 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1090 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1091 } 1092 1093 #define RTW_PWR_TRK_5G_1 0 1094 #define RTW_PWR_TRK_5G_2 1 1095 #define RTW_PWR_TRK_5G_3 2 1096 #define RTW_PWR_TRK_5G_NUM 3 1097 1098 #define RTW_PWR_TRK_TBL_SZ 30 1099 1100 /* This table stores the values of TX power that will be adjusted by power 1101 * tracking. 1102 * 1103 * For 5G bands, there are 3 different settings. 1104 * For 2G there are cck rate and ofdm rate with different settings. 1105 */ 1106 struct rtw_pwr_track_tbl { 1107 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1108 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1109 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1110 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1111 const u8 *pwrtrk_2gb_n; 1112 const u8 *pwrtrk_2gb_p; 1113 const u8 *pwrtrk_2ga_n; 1114 const u8 *pwrtrk_2ga_p; 1115 const u8 *pwrtrk_2g_cckb_n; 1116 const u8 *pwrtrk_2g_cckb_p; 1117 const u8 *pwrtrk_2g_ccka_n; 1118 const u8 *pwrtrk_2g_ccka_p; 1119 const s8 *pwrtrk_xtal_n; 1120 const s8 *pwrtrk_xtal_p; 1121 }; 1122 1123 enum rtw_wlan_cpu { 1124 RTW_WCPU_11AC, 1125 RTW_WCPU_11N, 1126 }; 1127 1128 enum rtw_fw_fifo_sel { 1129 RTW_FW_FIFO_SEL_TX, 1130 RTW_FW_FIFO_SEL_RX, 1131 RTW_FW_FIFO_SEL_RSVD_PAGE, 1132 RTW_FW_FIFO_SEL_REPORT, 1133 RTW_FW_FIFO_SEL_LLT, 1134 RTW_FW_FIFO_SEL_RXBUF_FW, 1135 1136 RTW_FW_FIFO_MAX, 1137 }; 1138 1139 enum rtw_fwcd_item { 1140 RTW_FWCD_TLV, 1141 RTW_FWCD_REG, 1142 RTW_FWCD_ROM, 1143 RTW_FWCD_IMEM, 1144 RTW_FWCD_DMEM, 1145 RTW_FWCD_EMEM, 1146 }; 1147 1148 /* hardware configuration for each IC */ 1149 struct rtw_chip_info { 1150 struct rtw_chip_ops *ops; 1151 u8 id; 1152 1153 const char *fw_name; 1154 enum rtw_wlan_cpu wlan_cpu; 1155 u8 tx_pkt_desc_sz; 1156 u8 tx_buf_desc_sz; 1157 u8 rx_pkt_desc_sz; 1158 u8 rx_buf_desc_sz; 1159 u32 phy_efuse_size; 1160 u32 log_efuse_size; 1161 u32 ptct_efuse_size; 1162 u32 txff_size; 1163 u32 rxff_size; 1164 u32 fw_rxff_size; 1165 u8 band; 1166 u8 page_size; 1167 u8 csi_buf_pg_num; 1168 u8 dig_max; 1169 u8 dig_min; 1170 u8 txgi_factor; 1171 bool is_pwr_by_rate_dec; 1172 bool rx_ldpc; 1173 bool tx_stbc; 1174 u8 max_power_index; 1175 1176 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1177 const struct rtw_fwcd_segs *fwcd_segs; 1178 1179 u8 default_1ss_tx_path; 1180 1181 bool path_div_supported; 1182 bool ht_supported; 1183 bool vht_supported; 1184 u8 lps_deep_mode_supported; 1185 1186 /* init values */ 1187 u8 sys_func_en; 1188 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1189 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1190 const struct rtw_rqpn *rqpn_table; 1191 const struct rtw_prioq_addrs *prioq_addrs; 1192 const struct rtw_page_table *page_table; 1193 const struct rtw_intf_phy_para_table *intf_table; 1194 1195 const struct rtw_hw_reg *dig; 1196 const struct rtw_hw_reg *dig_cck; 1197 u32 rf_base_addr[2]; 1198 u32 rf_sipi_addr[2]; 1199 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1200 u8 fix_rf_phy_num; 1201 const struct rtw_ltecoex_addr *ltecoex_addr; 1202 1203 const struct rtw_table *mac_tbl; 1204 const struct rtw_table *agc_tbl; 1205 const struct rtw_table *bb_tbl; 1206 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1207 const struct rtw_table *rfk_init_tbl; 1208 1209 const struct rtw_rfe_def *rfe_defs; 1210 u32 rfe_defs_size; 1211 1212 bool en_dis_dpd; 1213 u16 dpd_ratemask; 1214 u8 iqk_threshold; 1215 u8 lck_threshold; 1216 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1217 1218 u8 bfer_su_max_num; 1219 u8 bfer_mu_max_num; 1220 1221 struct rtw_hw_reg_offset *edcca_th; 1222 s8 l2h_th_ini_cs; 1223 s8 l2h_th_ini_ad; 1224 1225 const char *wow_fw_name; 1226 const struct wiphy_wowlan_support *wowlan_stub; 1227 const u8 max_sched_scan_ssids; 1228 1229 /* for 8821c set channel */ 1230 u32 ch_param[3]; 1231 1232 /* coex paras */ 1233 u32 coex_para_ver; 1234 u8 bt_desired_ver; 1235 bool scbd_support; 1236 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1237 bool ble_hid_profile_support; 1238 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1239 u8 bt_rssi_type; 1240 u8 ant_isolation; 1241 u8 rssi_tolerance; 1242 u8 table_sant_num; 1243 u8 table_nsant_num; 1244 u8 tdma_sant_num; 1245 u8 tdma_nsant_num; 1246 u8 bt_afh_span_bw20; 1247 u8 bt_afh_span_bw40; 1248 u8 afh_5g_num; 1249 u8 wl_rf_para_num; 1250 u8 coex_info_hw_regs_num; 1251 const u8 *bt_rssi_step; 1252 const u8 *wl_rssi_step; 1253 const struct coex_table_para *table_nsant; 1254 const struct coex_table_para *table_sant; 1255 const struct coex_tdma_para *tdma_sant; 1256 const struct coex_tdma_para *tdma_nsant; 1257 const struct coex_rf_para *wl_rf_para_tx; 1258 const struct coex_rf_para *wl_rf_para_rx; 1259 const struct coex_5g_afh_map *afh_5g; 1260 const struct rtw_hw_reg *btg_reg; 1261 const struct rtw_reg_domain *coex_info_hw_regs; 1262 u32 wl_fw_desired_ver; 1263 }; 1264 1265 enum rtw_coex_bt_state_cnt { 1266 COEX_CNT_BT_RETRY, 1267 COEX_CNT_BT_REINIT, 1268 COEX_CNT_BT_REENABLE, 1269 COEX_CNT_BT_POPEVENT, 1270 COEX_CNT_BT_SETUPLINK, 1271 COEX_CNT_BT_IGNWLANACT, 1272 COEX_CNT_BT_INQ, 1273 COEX_CNT_BT_PAGE, 1274 COEX_CNT_BT_ROLESWITCH, 1275 COEX_CNT_BT_AFHUPDATE, 1276 COEX_CNT_BT_INFOUPDATE, 1277 COEX_CNT_BT_IQK, 1278 COEX_CNT_BT_IQKFAIL, 1279 1280 COEX_CNT_BT_MAX 1281 }; 1282 1283 enum rtw_coex_wl_state_cnt { 1284 COEX_CNT_WL_SCANAP, 1285 COEX_CNT_WL_CONNPKT, 1286 COEX_CNT_WL_COEXRUN, 1287 COEX_CNT_WL_NOISY0, 1288 COEX_CNT_WL_NOISY1, 1289 COEX_CNT_WL_NOISY2, 1290 COEX_CNT_WL_5MS_NOEXTEND, 1291 COEX_CNT_WL_FW_NOTIFY, 1292 1293 COEX_CNT_WL_MAX 1294 }; 1295 1296 struct rtw_coex_rfe { 1297 bool ant_switch_exist; 1298 bool ant_switch_diversity; 1299 bool ant_switch_with_bt; 1300 u8 rfe_module_type; 1301 u8 ant_switch_polarity; 1302 1303 /* true if WLG at BTG, else at WLAG */ 1304 bool wlg_at_btg; 1305 }; 1306 1307 #define COEX_WL_TDMA_PARA_LENGTH 5 1308 1309 struct rtw_coex_dm { 1310 bool cur_ps_tdma_on; 1311 bool cur_wl_rx_low_gain_en; 1312 bool ignore_wl_act; 1313 1314 u8 reason; 1315 u8 bt_rssi_state[4]; 1316 u8 wl_rssi_state[4]; 1317 u8 wl_ch_info[3]; 1318 u8 cur_ps_tdma; 1319 u8 cur_table; 1320 u8 ps_tdma_para[5]; 1321 u8 cur_bt_pwr_lvl; 1322 u8 cur_bt_lna_lvl; 1323 u8 cur_wl_pwr_lvl; 1324 u8 bt_status; 1325 u32 cur_ant_pos_type; 1326 u32 cur_switch_status; 1327 u32 setting_tdma; 1328 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1329 }; 1330 1331 #define COEX_BTINFO_SRC_WL_FW 0x0 1332 #define COEX_BTINFO_SRC_BT_RSP 0x1 1333 #define COEX_BTINFO_SRC_BT_ACT 0x2 1334 #define COEX_BTINFO_SRC_BT_IQK 0x3 1335 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1336 #define COEX_BTINFO_SRC_H2C60 0x5 1337 #define COEX_BTINFO_SRC_MAX 0x6 1338 1339 #define COEX_INFO_FTP BIT(7) 1340 #define COEX_INFO_A2DP BIT(6) 1341 #define COEX_INFO_HID BIT(5) 1342 #define COEX_INFO_SCO_BUSY BIT(4) 1343 #define COEX_INFO_ACL_BUSY BIT(3) 1344 #define COEX_INFO_INQ_PAGE BIT(2) 1345 #define COEX_INFO_SCO_ESCO BIT(1) 1346 #define COEX_INFO_CONNECTION BIT(0) 1347 #define COEX_BTINFO_LENGTH_MAX 10 1348 #define COEX_BTINFO_LENGTH 7 1349 1350 struct rtw_coex_stat { 1351 bool bt_disabled; 1352 bool bt_disabled_pre; 1353 bool bt_link_exist; 1354 bool bt_whck_test; 1355 bool bt_inq_page; 1356 bool bt_inq_remain; 1357 bool bt_inq; 1358 bool bt_page; 1359 bool bt_ble_voice; 1360 bool bt_ble_exist; 1361 bool bt_hfp_exist; 1362 bool bt_a2dp_exist; 1363 bool bt_hid_exist; 1364 bool bt_pan_exist; /* PAN or OPP */ 1365 bool bt_opp_exist; /* OPP only */ 1366 bool bt_acl_busy; 1367 bool bt_fix_2M; 1368 bool bt_setup_link; 1369 bool bt_multi_link; 1370 bool bt_multi_link_pre; 1371 bool bt_multi_link_remain; 1372 bool bt_a2dp_sink; 1373 bool bt_a2dp_active; 1374 bool bt_reenable; 1375 bool bt_ble_scan_en; 1376 bool bt_init_scan; 1377 bool bt_slave; 1378 bool bt_418_hid_exist; 1379 bool bt_ble_hid_exist; 1380 bool bt_mailbox_reply; 1381 1382 bool wl_under_lps; 1383 bool wl_under_ips; 1384 bool wl_hi_pri_task1; 1385 bool wl_hi_pri_task2; 1386 bool wl_force_lps_ctrl; 1387 bool wl_gl_busy; 1388 bool wl_linkscan_proc; 1389 bool wl_ps_state_fail; 1390 bool wl_tx_limit_en; 1391 bool wl_ampdu_limit_en; 1392 bool wl_connected; 1393 bool wl_slot_extend; 1394 bool wl_cck_lock; 1395 bool wl_cck_lock_pre; 1396 bool wl_cck_lock_ever; 1397 bool wl_connecting; 1398 bool wl_slot_toggle; 1399 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1400 1401 u32 bt_supported_version; 1402 u32 bt_supported_feature; 1403 u32 hi_pri_tx; 1404 u32 hi_pri_rx; 1405 u32 lo_pri_tx; 1406 u32 lo_pri_rx; 1407 u32 patch_ver; 1408 u16 bt_reg_vendor_ae; 1409 u16 bt_reg_vendor_ac; 1410 s8 bt_rssi; 1411 u8 kt_ver; 1412 u8 gnt_workaround_state; 1413 u8 tdma_timer_base; 1414 u8 bt_profile_num; 1415 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1416 u8 bt_info_lb2; 1417 u8 bt_info_lb3; 1418 u8 bt_info_hb0; 1419 u8 bt_info_hb1; 1420 u8 bt_info_hb2; 1421 u8 bt_info_hb3; 1422 u8 bt_ble_scan_type; 1423 u8 bt_hid_pair_num; 1424 u8 bt_hid_slot; 1425 u8 bt_a2dp_bitpool; 1426 u8 bt_iqk_state; 1427 1428 u16 wl_beacon_interval; 1429 u8 wl_noisy_level; 1430 u8 wl_fw_dbg_info[10]; 1431 u8 wl_fw_dbg_info_pre[10]; 1432 u8 wl_rx_rate; 1433 u8 wl_tx_rate; 1434 u8 wl_rts_rx_rate; 1435 u8 wl_coex_mode; 1436 u8 wl_iot_peer; 1437 u8 ampdu_max_time; 1438 u8 wl_tput_dir; 1439 1440 u8 wl_toggle_para[6]; 1441 u8 wl_toggle_interval; 1442 1443 u16 score_board; 1444 u16 retry_limit; 1445 1446 /* counters to record bt states */ 1447 u32 cnt_bt[COEX_CNT_BT_MAX]; 1448 1449 /* counters to record wifi states */ 1450 u32 cnt_wl[COEX_CNT_WL_MAX]; 1451 1452 /* counters to record bt c2h data */ 1453 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1454 1455 u32 darfrc; 1456 u32 darfrch; 1457 }; 1458 1459 struct rtw_coex { 1460 /* protects coex info request section */ 1461 struct mutex mutex; 1462 struct sk_buff_head queue; 1463 wait_queue_head_t wait; 1464 1465 bool under_5g; 1466 bool stop_dm; 1467 bool freeze; 1468 bool freerun; 1469 bool wl_rf_off; 1470 bool manual_control; 1471 1472 struct rtw_coex_stat stat; 1473 struct rtw_coex_dm dm; 1474 struct rtw_coex_rfe rfe; 1475 1476 struct delayed_work bt_relink_work; 1477 struct delayed_work bt_reenable_work; 1478 struct delayed_work defreeze_work; 1479 struct delayed_work wl_remain_work; 1480 struct delayed_work bt_remain_work; 1481 struct delayed_work wl_connecting_work; 1482 struct delayed_work bt_multi_link_remain_work; 1483 struct delayed_work wl_ccklock_work; 1484 1485 }; 1486 1487 #define DPK_RF_REG_NUM 7 1488 #define DPK_RF_PATH_NUM 2 1489 #define DPK_BB_REG_NUM 18 1490 #define DPK_CHANNEL_WIDTH_80 1 1491 1492 DECLARE_EWMA(thermal, 10, 4); 1493 1494 struct rtw_dpk_info { 1495 bool is_dpk_pwr_on; 1496 bool is_reload; 1497 1498 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1499 1500 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1501 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1502 1503 u32 gnt_control; 1504 u32 gnt_value; 1505 1506 u8 result[RTW_RF_PATH_MAX]; 1507 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1508 u32 coef[RTW_RF_PATH_MAX][20]; 1509 u16 dpk_gs[RTW_RF_PATH_MAX]; 1510 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1511 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1512 1513 u8 dpk_band; 1514 u8 dpk_ch; 1515 u8 dpk_bw; 1516 }; 1517 1518 struct rtw_phy_cck_pd_reg { 1519 u32 reg_pd; 1520 u32 mask_pd; 1521 u32 reg_cs; 1522 u32 mask_cs; 1523 }; 1524 1525 #define DACK_MSBK_BACKUP_NUM 0xf 1526 #define DACK_DCK_BACKUP_NUM 0x2 1527 1528 struct rtw_swing_table { 1529 const u8 *p[RTW_RF_PATH_MAX]; 1530 const u8 *n[RTW_RF_PATH_MAX]; 1531 }; 1532 1533 struct rtw_pkt_count { 1534 u16 num_bcn_pkt; 1535 u16 num_qry_pkt[DESC_RATE_MAX]; 1536 }; 1537 1538 DECLARE_EWMA(evm, 10, 4); 1539 DECLARE_EWMA(snr, 10, 4); 1540 1541 struct rtw_iqk_info { 1542 bool done; 1543 struct { 1544 u32 s1_x; 1545 u32 s1_y; 1546 u32 s0_x; 1547 u32 s0_y; 1548 } result; 1549 }; 1550 1551 enum rtw_rf_band { 1552 RF_BAND_2G_CCK, 1553 RF_BAND_2G_OFDM, 1554 RF_BAND_5G_L, 1555 RF_BAND_5G_M, 1556 RF_BAND_5G_H, 1557 RF_BAND_MAX 1558 }; 1559 1560 #define RF_GAIN_NUM 11 1561 #define RF_HW_OFFSET_NUM 10 1562 1563 struct rtw_gapk_info { 1564 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1565 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1566 bool txgapk_bp_done; 1567 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1568 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1569 u8 read_txgain; 1570 u8 channel; 1571 }; 1572 1573 #define EDCCA_TH_L2H_IDX 0 1574 #define EDCCA_TH_H2L_IDX 1 1575 #define EDCCA_TH_L2H_LB 48 1576 #define EDCCA_ADC_BACKOFF 12 1577 #define EDCCA_IGI_BASE 50 1578 #define EDCCA_IGI_L2H_DIFF 8 1579 #define EDCCA_L2H_H2L_DIFF 7 1580 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1581 1582 enum rtw_edcca_mode { 1583 RTW_EDCCA_NORMAL = 0, 1584 RTW_EDCCA_ADAPTIVITY = 1, 1585 }; 1586 1587 struct rtw_cfo_track { 1588 bool is_adjust; 1589 u8 crystal_cap; 1590 s32 cfo_tail[RTW_RF_PATH_MAX]; 1591 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1592 u32 packet_count; 1593 u32 packet_count_pre; 1594 }; 1595 1596 #define RRSR_INIT_2G 0x15f 1597 #define RRSR_INIT_5G 0x150 1598 1599 enum rtw_dm_cap { 1600 RTW_DM_CAP_NA, 1601 RTW_DM_CAP_TXGAPK, 1602 RTW_DM_CAP_NUM 1603 }; 1604 1605 struct rtw_dm_info { 1606 u32 cck_fa_cnt; 1607 u32 ofdm_fa_cnt; 1608 u32 total_fa_cnt; 1609 u32 cck_cca_cnt; 1610 u32 ofdm_cca_cnt; 1611 u32 total_cca_cnt; 1612 1613 u32 cck_ok_cnt; 1614 u32 cck_err_cnt; 1615 u32 ofdm_ok_cnt; 1616 u32 ofdm_err_cnt; 1617 u32 ht_ok_cnt; 1618 u32 ht_err_cnt; 1619 u32 vht_ok_cnt; 1620 u32 vht_err_cnt; 1621 1622 u8 min_rssi; 1623 u8 pre_min_rssi; 1624 u16 fa_history[4]; 1625 u8 igi_history[4]; 1626 u8 igi_bitmap; 1627 bool damping; 1628 u8 damping_cnt; 1629 u8 damping_rssi; 1630 1631 u8 cck_gi_u_bnd; 1632 u8 cck_gi_l_bnd; 1633 1634 u8 tx_rate; 1635 u32 rrsr_val_init; 1636 u32 rrsr_mask_min; 1637 u8 thermal_avg[RTW_RF_PATH_MAX]; 1638 u8 thermal_meter_k; 1639 u8 thermal_meter_lck; 1640 s8 delta_power_index[RTW_RF_PATH_MAX]; 1641 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1642 u8 default_ofdm_index; 1643 bool pwr_trk_triggered; 1644 bool pwr_trk_init_trigger; 1645 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1646 s8 txagc_remnant_cck; 1647 s8 txagc_remnant_ofdm; 1648 1649 /* backup dack results for each path and I/Q */ 1650 u32 dack_adck[RTW_RF_PATH_MAX]; 1651 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1652 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1653 1654 struct rtw_dpk_info dpk_info; 1655 struct rtw_cfo_track cfo_track; 1656 1657 /* [bandwidth 0:20M/1:40M][number of path] */ 1658 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1659 u32 cck_fa_avg; 1660 u8 cck_pd_default; 1661 1662 /* save the last rx phy status for debug */ 1663 s8 rx_snr[RTW_RF_PATH_MAX]; 1664 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1665 s16 cfo_tail[RTW_RF_PATH_MAX]; 1666 u8 rssi[RTW_RF_PATH_MAX]; 1667 u8 curr_rx_rate; 1668 struct rtw_pkt_count cur_pkt_count; 1669 struct rtw_pkt_count last_pkt_count; 1670 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1671 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1672 1673 u32 dm_flags; /* enum rtw_dm_cap */ 1674 struct rtw_iqk_info iqk; 1675 struct rtw_gapk_info gapk; 1676 bool is_bt_iqk_timeout; 1677 1678 s8 l2h_th_ini; 1679 enum rtw_edcca_mode edcca_mode; 1680 u8 scan_density; 1681 }; 1682 1683 struct rtw_efuse { 1684 u32 size; 1685 u32 physical_size; 1686 u32 logical_size; 1687 u32 protect_size; 1688 1689 u8 addr[ETH_ALEN]; 1690 u8 channel_plan; 1691 u8 country_code[2]; 1692 u8 rf_board_option; 1693 u8 rfe_option; 1694 u8 power_track_type; 1695 u8 thermal_meter[RTW_RF_PATH_MAX]; 1696 u8 thermal_meter_k; 1697 u8 crystal_cap; 1698 u8 ant_div_cfg; 1699 u8 ant_div_type; 1700 u8 regd; 1701 u8 afe; 1702 1703 u8 lna_type_2g; 1704 u8 lna_type_5g; 1705 u8 glna_type; 1706 u8 alna_type; 1707 bool ext_lna_2g; 1708 bool ext_lna_5g; 1709 u8 pa_type_2g; 1710 u8 pa_type_5g; 1711 u8 gpa_type; 1712 u8 apa_type; 1713 bool ext_pa_2g; 1714 bool ext_pa_5g; 1715 u8 tx_bb_swing_setting_2g; 1716 u8 tx_bb_swing_setting_5g; 1717 1718 bool btcoex; 1719 /* bt share antenna with wifi */ 1720 bool share_ant; 1721 u8 bt_setting; 1722 1723 struct { 1724 u8 hci; 1725 u8 bw; 1726 u8 ptcl; 1727 u8 nss; 1728 u8 ant_num; 1729 } hw_cap; 1730 1731 struct rtw_txpwr_idx txpwr_idx_table[4]; 1732 }; 1733 1734 struct rtw_phy_cond { 1735 #ifdef __LITTLE_ENDIAN 1736 u32 rfe:8; 1737 u32 intf:4; 1738 u32 pkg:4; 1739 u32 plat:4; 1740 u32 intf_rsvd:4; 1741 u32 cut:4; 1742 u32 branch:2; 1743 u32 neg:1; 1744 u32 pos:1; 1745 #else 1746 u32 pos:1; 1747 u32 neg:1; 1748 u32 branch:2; 1749 u32 cut:4; 1750 u32 intf_rsvd:4; 1751 u32 plat:4; 1752 u32 pkg:4; 1753 u32 intf:4; 1754 u32 rfe:8; 1755 #endif 1756 /* for intf:4 */ 1757 #define INTF_PCIE BIT(0) 1758 #define INTF_USB BIT(1) 1759 #define INTF_SDIO BIT(2) 1760 /* for branch:2 */ 1761 #define BRANCH_IF 0 1762 #define BRANCH_ELIF 1 1763 #define BRANCH_ELSE 2 1764 #define BRANCH_ENDIF 3 1765 }; 1766 1767 struct rtw_fifo_conf { 1768 /* tx fifo information */ 1769 u16 rsvd_boundary; 1770 u16 rsvd_pg_num; 1771 u16 rsvd_drv_pg_num; 1772 u16 txff_pg_num; 1773 u16 acq_pg_num; 1774 u16 rsvd_drv_addr; 1775 u16 rsvd_h2c_info_addr; 1776 u16 rsvd_h2c_sta_info_addr; 1777 u16 rsvd_h2cq_addr; 1778 u16 rsvd_cpu_instr_addr; 1779 u16 rsvd_fw_txbuf_addr; 1780 u16 rsvd_csibuf_addr; 1781 const struct rtw_rqpn *rqpn; 1782 }; 1783 1784 struct rtw_fwcd_desc { 1785 u32 size; 1786 u8 *next; 1787 u8 *data; 1788 }; 1789 1790 struct rtw_fwcd_segs { 1791 const u32 *segs; 1792 u8 num; 1793 }; 1794 1795 #define FW_CD_TYPE 0xffff 1796 #define FW_CD_LEN 4 1797 #define FW_CD_VAL 0xaabbccdd 1798 struct rtw_fw_state { 1799 const struct firmware *firmware; 1800 struct rtw_dev *rtwdev; 1801 struct completion completion; 1802 struct rtw_fwcd_desc fwcd_desc; 1803 u16 version; 1804 u8 sub_version; 1805 u8 sub_index; 1806 u16 h2c_version; 1807 u32 feature; 1808 }; 1809 1810 struct rtw_hal { 1811 u32 rcr; 1812 1813 u32 chip_version; 1814 u8 cut_version; 1815 u8 mp_chip; 1816 u8 oem_id; 1817 struct rtw_phy_cond phy_cond; 1818 1819 u8 ps_mode; 1820 u8 current_channel; 1821 u8 current_band_width; 1822 u8 current_band_type; 1823 1824 /* center channel for different available bandwidth, 1825 * val of (bw > current_band_width) is invalid 1826 */ 1827 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1828 1829 u8 sec_ch_offset; 1830 u8 rf_type; 1831 u8 rf_path_num; 1832 u8 rf_phy_num; 1833 u32 antenna_tx; 1834 u32 antenna_rx; 1835 u8 bfee_sts_cap; 1836 1837 /* protect tx power section */ 1838 struct mutex tx_power_mutex; 1839 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1840 [DESC_RATE_MAX]; 1841 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1842 [DESC_RATE_MAX]; 1843 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1844 [RTW_RATE_SECTION_MAX]; 1845 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1846 [RTW_RATE_SECTION_MAX]; 1847 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1848 [RTW_CHANNEL_WIDTH_MAX] 1849 [RTW_RATE_SECTION_MAX] 1850 [RTW_MAX_CHANNEL_NUM_2G]; 1851 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1852 [RTW_CHANNEL_WIDTH_MAX] 1853 [RTW_RATE_SECTION_MAX] 1854 [RTW_MAX_CHANNEL_NUM_5G]; 1855 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1856 [DESC_RATE_MAX]; 1857 }; 1858 1859 struct rtw_path_div { 1860 enum rtw_bb_path current_tx_path; 1861 u32 path_a_sum; 1862 u32 path_b_sum; 1863 u16 path_a_cnt; 1864 u16 path_b_cnt; 1865 }; 1866 1867 struct rtw_dev { 1868 struct ieee80211_hw *hw; 1869 struct device *dev; 1870 1871 struct rtw_hci hci; 1872 1873 struct rtw_chip_info *chip; 1874 struct rtw_hal hal; 1875 struct rtw_fifo_conf fifo; 1876 struct rtw_fw_state fw; 1877 struct rtw_efuse efuse; 1878 struct rtw_sec_desc sec; 1879 struct rtw_traffic_stats stats; 1880 struct rtw_regd regd; 1881 struct rtw_bf_info bf_info; 1882 1883 struct rtw_dm_info dm_info; 1884 struct rtw_coex coex; 1885 1886 /* ensures exclusive access from mac80211 callbacks */ 1887 struct mutex mutex; 1888 1889 /* read/write rf register */ 1890 spinlock_t rf_lock; 1891 1892 /* watch dog every 2 sec */ 1893 struct delayed_work watch_dog_work; 1894 u32 watch_dog_cnt; 1895 1896 struct list_head rsvd_page_list; 1897 1898 /* c2h cmd queue & handler work */ 1899 struct sk_buff_head c2h_queue; 1900 struct work_struct c2h_work; 1901 struct work_struct fw_recovery_work; 1902 1903 /* used to protect txqs list */ 1904 spinlock_t txq_lock; 1905 struct list_head txqs; 1906 struct workqueue_struct *tx_wq; 1907 struct work_struct tx_work; 1908 struct work_struct ba_work; 1909 1910 struct rtw_tx_report tx_report; 1911 1912 struct { 1913 /* incicate the mail box to use with fw */ 1914 u8 last_box_num; 1915 /* protect to send h2c to fw */ 1916 spinlock_t lock; 1917 u32 seq; 1918 } h2c; 1919 1920 /* lps power state & handler work */ 1921 struct rtw_lps_conf lps_conf; 1922 bool ps_enabled; 1923 bool beacon_loss; 1924 struct completion lps_leave_check; 1925 1926 struct dentry *debugfs; 1927 1928 u8 sta_cnt; 1929 u32 rts_threshold; 1930 1931 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1932 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1933 1934 u8 mp_mode; 1935 struct rtw_path_div dm_path_div; 1936 1937 struct rtw_fw_state wow_fw; 1938 struct rtw_wow_param wow; 1939 1940 bool need_rfk; 1941 struct completion fw_scan_density; 1942 1943 /* hci related data, must be last */ 1944 u8 priv[] __aligned(sizeof(void *)); 1945 }; 1946 1947 #include "hci.h" 1948 1949 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1950 { 1951 return !!rtwdev->sta_cnt; 1952 } 1953 1954 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1955 { 1956 void *p = rtwtxq; 1957 1958 return container_of(p, struct ieee80211_txq, drv_priv); 1959 } 1960 1961 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1962 { 1963 void *p = rtwvif; 1964 1965 return container_of(p, struct ieee80211_vif, drv_priv); 1966 } 1967 1968 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1969 struct cfg80211_ssid *b) 1970 { 1971 if (!a || !b || a->ssid_len != b->ssid_len) 1972 return false; 1973 1974 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1975 return false; 1976 1977 return true; 1978 } 1979 1980 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 1981 { 1982 if (rtwdev->chip->ops->efuse_grant) 1983 rtwdev->chip->ops->efuse_grant(rtwdev, true); 1984 } 1985 1986 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 1987 { 1988 if (rtwdev->chip->ops->efuse_grant) 1989 rtwdev->chip->ops->efuse_grant(rtwdev, false); 1990 } 1991 1992 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 1993 { 1994 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 1995 } 1996 1997 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 1998 { 1999 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2000 } 2001 2002 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2003 { 2004 return rtwdev->chip->rx_ldpc; 2005 } 2006 2007 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2008 { 2009 return rtwdev->chip->tx_stbc; 2010 } 2011 2012 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2013 { 2014 clear_bit(mac_id, rtwdev->mac_id_map); 2015 } 2016 2017 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2018 { 2019 if (rtwdev->chip->ops->dump_fw_crash) 2020 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2021 2022 return 0; 2023 } 2024 2025 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2026 struct rtw_channel_params *ch_param); 2027 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2028 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2029 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2030 void rtw_restore_reg(struct rtw_dev *rtwdev, 2031 struct rtw_backup_info *bckp, u32 num); 2032 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2033 void rtw_set_channel(struct rtw_dev *rtwdev); 2034 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2035 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2036 u32 config); 2037 void rtw_tx_report_purge_timer(struct timer_list *t); 2038 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 2039 int rtw_core_start(struct rtw_dev *rtwdev); 2040 void rtw_core_stop(struct rtw_dev *rtwdev); 2041 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2042 int rtw_core_init(struct rtw_dev *rtwdev); 2043 void rtw_core_deinit(struct rtw_dev *rtwdev); 2044 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2045 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2046 u16 rtw_desc_to_bitrate(u8 desc_rate); 2047 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2048 struct ieee80211_bss_conf *conf); 2049 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2050 struct ieee80211_vif *vif); 2051 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2052 bool fw_exist); 2053 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2054 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2055 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2056 u32 fwcd_item); 2057 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2058 2059 #endif 2060