1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 18 #include "util.h" 19 20 #define RTW_MAX_MAC_ID_NUM 32 21 #define RTW_MAX_SEC_CAM_NUM 32 22 #define MAX_PG_CAM_BACKUP_NUM 8 23 24 #define RTW_SCAN_MAX_SSIDS 4 25 26 #define RTW_MAX_PATTERN_NUM 12 27 #define RTW_MAX_PATTERN_MASK_SIZE 16 28 #define RTW_MAX_PATTERN_SIZE 128 29 30 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 31 32 #define RFREG_MASK 0xfffff 33 #define INV_RF_DATA 0xffffffff 34 #define TX_PAGE_SIZE_SHIFT 7 35 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT) 36 37 #define RTW_CHANNEL_WIDTH_MAX 3 38 #define RTW_RF_PATH_MAX 4 39 #define HW_FEATURE_LEN 13 40 41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 42 43 extern bool rtw_bf_support; 44 extern bool rtw_disable_lps_deep_mode; 45 extern unsigned int rtw_debug_mask; 46 extern bool rtw_edcca_enabled; 47 extern const struct ieee80211_ops rtw_ops; 48 49 #define RTW_MAX_CHANNEL_NUM_2G 14 50 #define RTW_MAX_CHANNEL_NUM_5G 49 51 52 struct rtw_dev; 53 struct rtw_debugfs; 54 55 enum rtw_hci_type { 56 RTW_HCI_TYPE_PCIE, 57 RTW_HCI_TYPE_USB, 58 RTW_HCI_TYPE_SDIO, 59 60 RTW_HCI_TYPE_UNDEFINE, 61 }; 62 63 struct rtw_hci { 64 const struct rtw_hci_ops *ops; 65 enum rtw_hci_type type; 66 67 u32 rpwm_addr; 68 u32 cpwm_addr; 69 70 u8 bulkout_num; 71 }; 72 73 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 74 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 75 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 76 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 77 78 #define IS_CH_5G_BAND_MID(channel) \ 79 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 80 81 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 82 #define IS_CH_5G_BAND(channel) \ 83 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 84 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 85 86 enum rtw_supported_band { 87 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 88 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 89 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 90 }; 91 92 /* now, support up to 80M bw */ 93 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 94 95 enum rtw_bandwidth { 96 RTW_CHANNEL_WIDTH_20 = 0, 97 RTW_CHANNEL_WIDTH_40 = 1, 98 RTW_CHANNEL_WIDTH_80 = 2, 99 RTW_CHANNEL_WIDTH_160 = 3, 100 RTW_CHANNEL_WIDTH_80_80 = 4, 101 RTW_CHANNEL_WIDTH_5 = 5, 102 RTW_CHANNEL_WIDTH_10 = 6, 103 }; 104 105 enum rtw_sc_offset { 106 RTW_SC_DONT_CARE = 0, 107 RTW_SC_20_UPPER = 1, 108 RTW_SC_20_LOWER = 2, 109 RTW_SC_20_UPMOST = 3, 110 RTW_SC_20_LOWEST = 4, 111 RTW_SC_40_UPPER = 9, 112 RTW_SC_40_LOWER = 10, 113 }; 114 115 enum rtw_net_type { 116 RTW_NET_NO_LINK = 0, 117 RTW_NET_AD_HOC = 1, 118 RTW_NET_MGD_LINKED = 2, 119 RTW_NET_AP_MODE = 3, 120 }; 121 122 enum rtw_rf_type { 123 RF_1T1R = 0, 124 RF_1T2R = 1, 125 RF_2T2R = 2, 126 RF_2T3R = 3, 127 RF_2T4R = 4, 128 RF_3T3R = 5, 129 RF_3T4R = 6, 130 RF_4T4R = 7, 131 RF_TYPE_MAX, 132 }; 133 134 enum rtw_rf_path { 135 RF_PATH_A = 0, 136 RF_PATH_B = 1, 137 RF_PATH_C = 2, 138 RF_PATH_D = 3, 139 }; 140 141 enum rtw_bb_path { 142 BB_PATH_A = BIT(0), 143 BB_PATH_B = BIT(1), 144 BB_PATH_C = BIT(2), 145 BB_PATH_D = BIT(3), 146 147 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 148 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 149 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 150 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 151 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 152 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 153 154 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 155 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 156 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 157 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 158 159 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 160 }; 161 162 enum rtw_rate_section { 163 RTW_RATE_SECTION_CCK = 0, 164 RTW_RATE_SECTION_OFDM, 165 RTW_RATE_SECTION_HT_1S, 166 RTW_RATE_SECTION_HT_2S, 167 RTW_RATE_SECTION_VHT_1S, 168 RTW_RATE_SECTION_VHT_2S, 169 __RTW_RATE_SECTION_2SS_MAX = RTW_RATE_SECTION_VHT_2S, 170 RTW_RATE_SECTION_HT_3S, 171 RTW_RATE_SECTION_HT_4S, 172 RTW_RATE_SECTION_VHT_3S, 173 RTW_RATE_SECTION_VHT_4S, 174 175 /* keep last */ 176 RTW_RATE_SECTION_NUM, 177 }; 178 179 enum rtw_wireless_set { 180 WIRELESS_CCK = 0x00000001, 181 WIRELESS_OFDM = 0x00000002, 182 WIRELESS_HT = 0x00000004, 183 WIRELESS_VHT = 0x00000008, 184 }; 185 186 #define HT_STBC_EN BIT(0) 187 #define VHT_STBC_EN BIT(1) 188 #define HT_LDPC_EN BIT(0) 189 #define VHT_LDPC_EN BIT(1) 190 191 enum rtw_chip_type { 192 RTW_CHIP_TYPE_8822B, 193 RTW_CHIP_TYPE_8822C, 194 RTW_CHIP_TYPE_8723D, 195 RTW_CHIP_TYPE_8821C, 196 RTW_CHIP_TYPE_8703B, 197 RTW_CHIP_TYPE_8821A, 198 RTW_CHIP_TYPE_8812A, 199 RTW_CHIP_TYPE_8814A, 200 }; 201 202 enum rtw_tx_queue_type { 203 /* the order of AC queues matters */ 204 RTW_TX_QUEUE_BK = 0x0, 205 RTW_TX_QUEUE_BE = 0x1, 206 RTW_TX_QUEUE_VI = 0x2, 207 RTW_TX_QUEUE_VO = 0x3, 208 209 RTW_TX_QUEUE_BCN = 0x4, 210 RTW_TX_QUEUE_MGMT = 0x5, 211 RTW_TX_QUEUE_HI0 = 0x6, 212 RTW_TX_QUEUE_H2C = 0x7, 213 /* keep it last */ 214 RTK_MAX_TX_QUEUE_NUM 215 }; 216 217 enum rtw_rx_queue_type { 218 RTW_RX_QUEUE_MPDU = 0x0, 219 RTW_RX_QUEUE_C2H = 0x1, 220 /* keep it last */ 221 RTK_MAX_RX_QUEUE_NUM 222 }; 223 224 enum rtw_fw_type { 225 RTW_NORMAL_FW = 0x0, 226 RTW_WOWLAN_FW = 0x1, 227 }; 228 229 enum rtw_rate_index { 230 RTW_RATEID_BGN_40M_2SS = 0, 231 RTW_RATEID_BGN_40M_1SS = 1, 232 RTW_RATEID_BGN_20M_2SS = 2, 233 RTW_RATEID_BGN_20M_1SS = 3, 234 RTW_RATEID_GN_N2SS = 4, 235 RTW_RATEID_GN_N1SS = 5, 236 RTW_RATEID_BG = 6, 237 RTW_RATEID_G = 7, 238 RTW_RATEID_B_20M = 8, 239 RTW_RATEID_ARFR0_AC_2SS = 9, 240 RTW_RATEID_ARFR1_AC_1SS = 10, 241 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 242 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 243 RTW_RATEID_ARFR4_AC_3SS = 13, 244 RTW_RATEID_ARFR5_N_3SS = 14, 245 RTW_RATEID_ARFR7_N_4SS = 15, 246 RTW_RATEID_ARFR6_AC_4SS = 16 247 }; 248 249 enum rtw_trx_desc_rate { 250 DESC_RATE1M = 0x00, 251 DESC_RATE2M = 0x01, 252 DESC_RATE5_5M = 0x02, 253 DESC_RATE11M = 0x03, 254 255 DESC_RATE6M = 0x04, 256 DESC_RATE9M = 0x05, 257 DESC_RATE12M = 0x06, 258 DESC_RATE18M = 0x07, 259 DESC_RATE24M = 0x08, 260 DESC_RATE36M = 0x09, 261 DESC_RATE48M = 0x0a, 262 DESC_RATE54M = 0x0b, 263 264 DESC_RATEMCS0 = 0x0c, 265 DESC_RATEMCS1 = 0x0d, 266 DESC_RATEMCS2 = 0x0e, 267 DESC_RATEMCS3 = 0x0f, 268 DESC_RATEMCS4 = 0x10, 269 DESC_RATEMCS5 = 0x11, 270 DESC_RATEMCS6 = 0x12, 271 DESC_RATEMCS7 = 0x13, 272 DESC_RATEMCS8 = 0x14, 273 DESC_RATEMCS9 = 0x15, 274 DESC_RATEMCS10 = 0x16, 275 DESC_RATEMCS11 = 0x17, 276 DESC_RATEMCS12 = 0x18, 277 DESC_RATEMCS13 = 0x19, 278 DESC_RATEMCS14 = 0x1a, 279 DESC_RATEMCS15 = 0x1b, 280 DESC_RATEMCS16 = 0x1c, 281 DESC_RATEMCS17 = 0x1d, 282 DESC_RATEMCS18 = 0x1e, 283 DESC_RATEMCS19 = 0x1f, 284 DESC_RATEMCS20 = 0x20, 285 DESC_RATEMCS21 = 0x21, 286 DESC_RATEMCS22 = 0x22, 287 DESC_RATEMCS23 = 0x23, 288 DESC_RATEMCS24 = 0x24, 289 DESC_RATEMCS25 = 0x25, 290 DESC_RATEMCS26 = 0x26, 291 DESC_RATEMCS27 = 0x27, 292 DESC_RATEMCS28 = 0x28, 293 DESC_RATEMCS29 = 0x29, 294 DESC_RATEMCS30 = 0x2a, 295 DESC_RATEMCS31 = 0x2b, 296 297 DESC_RATEVHT1SS_MCS0 = 0x2c, 298 DESC_RATEVHT1SS_MCS1 = 0x2d, 299 DESC_RATEVHT1SS_MCS2 = 0x2e, 300 DESC_RATEVHT1SS_MCS3 = 0x2f, 301 DESC_RATEVHT1SS_MCS4 = 0x30, 302 DESC_RATEVHT1SS_MCS5 = 0x31, 303 DESC_RATEVHT1SS_MCS6 = 0x32, 304 DESC_RATEVHT1SS_MCS7 = 0x33, 305 DESC_RATEVHT1SS_MCS8 = 0x34, 306 DESC_RATEVHT1SS_MCS9 = 0x35, 307 308 DESC_RATEVHT2SS_MCS0 = 0x36, 309 DESC_RATEVHT2SS_MCS1 = 0x37, 310 DESC_RATEVHT2SS_MCS2 = 0x38, 311 DESC_RATEVHT2SS_MCS3 = 0x39, 312 DESC_RATEVHT2SS_MCS4 = 0x3a, 313 DESC_RATEVHT2SS_MCS5 = 0x3b, 314 DESC_RATEVHT2SS_MCS6 = 0x3c, 315 DESC_RATEVHT2SS_MCS7 = 0x3d, 316 DESC_RATEVHT2SS_MCS8 = 0x3e, 317 DESC_RATEVHT2SS_MCS9 = 0x3f, 318 319 DESC_RATEVHT3SS_MCS0 = 0x40, 320 DESC_RATEVHT3SS_MCS1 = 0x41, 321 DESC_RATEVHT3SS_MCS2 = 0x42, 322 DESC_RATEVHT3SS_MCS3 = 0x43, 323 DESC_RATEVHT3SS_MCS4 = 0x44, 324 DESC_RATEVHT3SS_MCS5 = 0x45, 325 DESC_RATEVHT3SS_MCS6 = 0x46, 326 DESC_RATEVHT3SS_MCS7 = 0x47, 327 DESC_RATEVHT3SS_MCS8 = 0x48, 328 DESC_RATEVHT3SS_MCS9 = 0x49, 329 330 DESC_RATEVHT4SS_MCS0 = 0x4a, 331 DESC_RATEVHT4SS_MCS1 = 0x4b, 332 DESC_RATEVHT4SS_MCS2 = 0x4c, 333 DESC_RATEVHT4SS_MCS3 = 0x4d, 334 DESC_RATEVHT4SS_MCS4 = 0x4e, 335 DESC_RATEVHT4SS_MCS5 = 0x4f, 336 DESC_RATEVHT4SS_MCS6 = 0x50, 337 DESC_RATEVHT4SS_MCS7 = 0x51, 338 DESC_RATEVHT4SS_MCS8 = 0x52, 339 DESC_RATEVHT4SS_MCS9 = 0x53, 340 341 DESC_RATE_MAX, 342 }; 343 344 enum rtw_regulatory_domains { 345 RTW_REGD_FCC = 0, 346 RTW_REGD_MKK = 1, 347 RTW_REGD_ETSI = 2, 348 RTW_REGD_IC = 3, 349 RTW_REGD_KCC = 4, 350 RTW_REGD_ACMA = 5, 351 RTW_REGD_CHILE = 6, 352 RTW_REGD_UKRAINE = 7, 353 RTW_REGD_MEXICO = 8, 354 RTW_REGD_CN = 9, 355 RTW_REGD_QATAR = 10, 356 RTW_REGD_UK = 11, 357 358 RTW_REGD_WW, 359 RTW_REGD_MAX 360 }; 361 362 enum rtw_txq_flags { 363 RTW_TXQ_AMPDU, 364 RTW_TXQ_BLOCK_BA, 365 }; 366 367 enum rtw_flags { 368 RTW_FLAG_RUNNING, 369 RTW_FLAG_FW_RUNNING, 370 RTW_FLAG_SCANNING, 371 RTW_FLAG_POWERON, 372 RTW_FLAG_LEISURE_PS, 373 RTW_FLAG_LEISURE_PS_DEEP, 374 RTW_FLAG_DIG_DISABLE, 375 RTW_FLAG_BUSY_TRAFFIC, 376 RTW_FLAG_WOWLAN, 377 RTW_FLAG_RESTARTING, 378 RTW_FLAG_RESTART_TRIGGERING, 379 RTW_FLAG_FORCE_LOWEST_RATE, 380 381 NUM_OF_RTW_FLAGS, 382 }; 383 384 enum rtw_evm { 385 RTW_EVM_OFDM = 0, 386 RTW_EVM_1SS, 387 RTW_EVM_2SS_A, 388 RTW_EVM_2SS_B, 389 /* keep it last */ 390 RTW_EVM_NUM 391 }; 392 393 enum rtw_snr { 394 RTW_SNR_OFDM_A = 0, 395 RTW_SNR_OFDM_B, 396 RTW_SNR_OFDM_C, 397 RTW_SNR_OFDM_D, 398 RTW_SNR_1SS_A, 399 RTW_SNR_1SS_B, 400 RTW_SNR_1SS_C, 401 RTW_SNR_1SS_D, 402 RTW_SNR_2SS_A, 403 RTW_SNR_2SS_B, 404 RTW_SNR_2SS_C, 405 RTW_SNR_2SS_D, 406 /* keep it last */ 407 RTW_SNR_NUM 408 }; 409 410 enum rtw_port { 411 RTW_PORT_0 = 0, 412 RTW_PORT_1 = 1, 413 RTW_PORT_2 = 2, 414 RTW_PORT_3 = 3, 415 RTW_PORT_4 = 4, 416 RTW_PORT_NUM 417 }; 418 419 enum rtw_wow_flags { 420 RTW_WOW_FLAG_EN_MAGIC_PKT, 421 RTW_WOW_FLAG_EN_REKEY_PKT, 422 RTW_WOW_FLAG_EN_DISCONNECT, 423 424 /* keep it last */ 425 RTW_WOW_FLAG_MAX, 426 }; 427 428 /* the power index is represented by differences, which cck-1s & ht40-1s are 429 * the base values, so for 1s's differences, there are only ht20 & ofdm 430 */ 431 struct rtw_2g_1s_pwr_idx_diff { 432 #ifdef __LITTLE_ENDIAN 433 s8 ofdm:4; 434 s8 bw20:4; 435 #else 436 s8 bw20:4; 437 s8 ofdm:4; 438 #endif 439 } __packed; 440 441 struct rtw_2g_ns_pwr_idx_diff { 442 #ifdef __LITTLE_ENDIAN 443 s8 bw20:4; 444 s8 bw40:4; 445 s8 cck:4; 446 s8 ofdm:4; 447 #else 448 s8 ofdm:4; 449 s8 cck:4; 450 s8 bw40:4; 451 s8 bw20:4; 452 #endif 453 } __packed; 454 455 struct rtw_2g_txpwr_idx { 456 u8 cck_base[6]; 457 u8 bw40_base[5]; 458 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 459 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 460 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 461 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 462 }; 463 464 struct rtw_5g_ht_1s_pwr_idx_diff { 465 #ifdef __LITTLE_ENDIAN 466 s8 ofdm:4; 467 s8 bw20:4; 468 #else 469 s8 bw20:4; 470 s8 ofdm:4; 471 #endif 472 } __packed; 473 474 struct rtw_5g_ht_ns_pwr_idx_diff { 475 #ifdef __LITTLE_ENDIAN 476 s8 bw20:4; 477 s8 bw40:4; 478 #else 479 s8 bw40:4; 480 s8 bw20:4; 481 #endif 482 } __packed; 483 484 struct rtw_5g_ofdm_ns_pwr_idx_diff { 485 #ifdef __LITTLE_ENDIAN 486 s8 ofdm_3s:4; 487 s8 ofdm_2s:4; 488 s8 ofdm_4s:4; 489 s8 res:4; 490 #else 491 s8 res:4; 492 s8 ofdm_4s:4; 493 s8 ofdm_2s:4; 494 s8 ofdm_3s:4; 495 #endif 496 } __packed; 497 498 struct rtw_5g_vht_ns_pwr_idx_diff { 499 #ifdef __LITTLE_ENDIAN 500 s8 bw160:4; 501 s8 bw80:4; 502 #else 503 s8 bw80:4; 504 s8 bw160:4; 505 #endif 506 } __packed; 507 508 struct rtw_5g_txpwr_idx { 509 u8 bw40_base[14]; 510 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 511 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 512 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 513 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 514 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 515 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 516 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 517 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 518 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 519 } __packed; 520 521 struct rtw_txpwr_idx { 522 struct rtw_2g_txpwr_idx pwr_idx_2g; 523 struct rtw_5g_txpwr_idx pwr_idx_5g; 524 } __packed; 525 526 struct rtw_channel_params { 527 u8 center_chan; 528 u8 primary_chan; 529 u8 bandwidth; 530 }; 531 532 struct rtw_hw_reg { 533 u32 addr; 534 u32 mask; 535 }; 536 537 struct rtw_hw_reg_desc { 538 u32 addr; 539 u32 mask; 540 const char *desc; 541 }; 542 543 struct rtw_ltecoex_addr { 544 u32 ctrl; 545 u32 wdata; 546 u32 rdata; 547 }; 548 549 struct rtw_reg_domain { 550 u32 addr; 551 u32 mask; 552 #define RTW_REG_DOMAIN_MAC32 0 553 #define RTW_REG_DOMAIN_MAC16 1 554 #define RTW_REG_DOMAIN_MAC8 2 555 #define RTW_REG_DOMAIN_RF_A 3 556 #define RTW_REG_DOMAIN_RF_B 4 557 #define RTW_REG_DOMAIN_NL 0xFF 558 u8 domain; 559 }; 560 561 struct rtw_rf_sipi_addr { 562 u32 hssi_1; 563 u32 hssi_2; 564 u32 lssi_read; 565 u32 lssi_read_pi; 566 }; 567 568 struct rtw_hw_reg_offset { 569 struct rtw_hw_reg hw_reg; 570 u8 offset; 571 }; 572 573 struct rtw_backup_info { 574 u8 len; 575 u32 reg; 576 u32 val; 577 }; 578 579 enum rtw_vif_port_set { 580 PORT_SET_MAC_ADDR = BIT(0), 581 PORT_SET_BSSID = BIT(1), 582 PORT_SET_NET_TYPE = BIT(2), 583 PORT_SET_AID = BIT(3), 584 PORT_SET_BCN_CTRL = BIT(4), 585 }; 586 587 struct rtw_vif_port { 588 struct rtw_hw_reg mac_addr; 589 struct rtw_hw_reg bssid; 590 struct rtw_hw_reg net_type; 591 struct rtw_hw_reg aid; 592 struct rtw_hw_reg bcn_ctrl; 593 }; 594 595 struct rtw_tx_pkt_info { 596 u32 tx_pkt_size; 597 u8 offset; 598 u8 pkt_offset; 599 u8 tim_offset; 600 u8 mac_id; 601 u8 rate_id; 602 u8 rate; 603 u8 qsel; 604 u8 bw; 605 u8 sec_type; 606 u8 sn; 607 bool ampdu_en; 608 u8 ampdu_factor; 609 u8 ampdu_density; 610 u16 seq; 611 bool stbc; 612 bool ldpc; 613 bool dis_rate_fallback; 614 bool bmc; 615 bool use_rate; 616 bool ls; 617 bool fs; 618 bool short_gi; 619 bool report; 620 bool rts; 621 bool dis_qselseq; 622 bool en_hwseq; 623 u8 hw_ssn_sel; 624 bool nav_use_hdr; 625 bool bt_null; 626 }; 627 628 struct rtw_rx_pkt_stat { 629 bool phy_status; 630 bool icv_err; 631 bool crc_err; 632 bool decrypted; 633 bool is_c2h; 634 bool channel_invalid; 635 636 s32 signal_power; 637 u16 pkt_len; 638 u8 bw; 639 u8 drv_info_sz; 640 u8 shift; 641 u8 rate; 642 u8 mac_id; 643 u8 cam_id; 644 u8 ppdu_cnt; 645 u32 tsf_low; 646 s8 rx_power[RTW_RF_PATH_MAX]; 647 u8 rssi; 648 u8 rxsc; 649 s8 rx_snr[RTW_RF_PATH_MAX]; 650 u8 rx_evm[RTW_RF_PATH_MAX]; 651 s8 cfo_tail[RTW_RF_PATH_MAX]; 652 u16 freq; 653 u8 band; 654 655 struct rtw_sta_info *si; 656 struct ieee80211_vif *vif; 657 struct ieee80211_hdr *hdr; 658 }; 659 660 DECLARE_EWMA(tp, 10, 2); 661 662 struct rtw_traffic_stats { 663 /* units in bytes */ 664 u64 tx_unicast; 665 u64 rx_unicast; 666 667 /* count for packets */ 668 u64 tx_cnt; 669 u64 rx_cnt; 670 671 /* units in Mbps */ 672 u32 tx_throughput; 673 u32 rx_throughput; 674 struct ewma_tp tx_ewma_tp; 675 struct ewma_tp rx_ewma_tp; 676 }; 677 678 enum rtw_lps_mode { 679 RTW_MODE_ACTIVE = 0, 680 RTW_MODE_LPS = 1, 681 RTW_MODE_WMM_PS = 2, 682 }; 683 684 enum rtw_lps_deep_mode { 685 LPS_DEEP_MODE_NONE = 0, 686 LPS_DEEP_MODE_LCLK = 1, 687 LPS_DEEP_MODE_PG = 2, 688 }; 689 690 enum rtw_pwr_state { 691 RTW_RF_OFF = 0x0, 692 RTW_RF_ON = 0x4, 693 RTW_ALL_ON = 0xc, 694 }; 695 696 struct rtw_lps_conf { 697 enum rtw_lps_mode mode; 698 enum rtw_lps_deep_mode deep_mode; 699 enum rtw_lps_deep_mode wow_deep_mode; 700 enum rtw_pwr_state state; 701 u8 awake_interval; 702 u8 rlbm; 703 u8 smart_ps; 704 u8 port_id; 705 bool sec_cam_backup; 706 bool pattern_cam_backup; 707 }; 708 709 enum rtw_hw_key_type { 710 RTW_CAM_NONE = 0, 711 RTW_CAM_WEP40 = 1, 712 RTW_CAM_TKIP = 2, 713 RTW_CAM_AES = 4, 714 RTW_CAM_WEP104 = 5, 715 }; 716 717 struct rtw_cam_entry { 718 bool valid; 719 bool group; 720 u8 addr[ETH_ALEN]; 721 u8 hw_key_type; 722 struct ieee80211_key_conf *key; 723 }; 724 725 struct rtw_sec_desc { 726 /* search strategy */ 727 bool default_key_search; 728 729 u32 total_cam_num; 730 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 731 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 732 }; 733 734 struct rtw_tx_report { 735 /* protect the tx report queue */ 736 spinlock_t q_lock; 737 struct sk_buff_head queue; 738 atomic_t sn; 739 struct timer_list purge_timer; 740 }; 741 742 struct rtw_ra_report { 743 struct rate_info txrate; 744 u32 bit_rate; 745 u8 desc_rate; 746 }; 747 748 struct rtw_txq { 749 struct list_head list; 750 unsigned long flags; 751 }; 752 753 DECLARE_EWMA(rssi, 10, 16); 754 755 struct rtw_sta_info { 756 struct rtw_dev *rtwdev; 757 struct ieee80211_sta *sta; 758 struct ieee80211_vif *vif; 759 760 struct ewma_rssi avg_rssi; 761 u8 rssi_level; 762 763 u8 mac_id; 764 u8 rate_id; 765 enum rtw_bandwidth bw_mode; 766 u8 stbc_en:2; 767 u8 ldpc_en:2; 768 bool sgi_enable; 769 bool vht_enable; 770 u8 init_ra_lv; 771 u64 ra_mask; 772 773 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 774 775 struct rtw_ra_report ra_report; 776 777 bool use_cfg_mask; 778 struct cfg80211_bitrate_mask *mask; 779 780 struct work_struct rc_work; 781 }; 782 783 enum rtw_bfee_role { 784 RTW_BFEE_NONE, 785 RTW_BFEE_SU, 786 RTW_BFEE_MU 787 }; 788 789 struct rtw_bfee { 790 enum rtw_bfee_role role; 791 792 u16 p_aid; 793 u8 g_id; 794 u8 mac_addr[ETH_ALEN]; 795 u8 sound_dim; 796 797 /* SU-MIMO */ 798 u8 su_reg_index; 799 800 /* MU-MIMO */ 801 u16 aid; 802 }; 803 804 struct rtw_bf_info { 805 u8 bfer_mu_cnt; 806 u8 bfer_su_cnt; 807 DECLARE_BITMAP(bfer_su_reg_maping, 2); 808 u8 cur_csi_rpt_rate; 809 }; 810 811 struct rtw_vif { 812 enum rtw_net_type net_type; 813 u16 aid; 814 u8 mac_id; 815 u8 mac_addr[ETH_ALEN]; 816 u8 bssid[ETH_ALEN]; 817 u8 port; 818 u8 bcn_ctrl; 819 struct list_head rsvd_page_list; 820 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 821 const struct rtw_vif_port *conf; 822 struct cfg80211_scan_request *scan_req; 823 struct ieee80211_scan_ies *scan_ies; 824 825 struct rtw_traffic_stats stats; 826 827 struct rtw_bfee bfee; 828 }; 829 830 struct rtw_regulatory { 831 char alpha2[2]; 832 u8 txpwr_regd_2g; 833 u8 txpwr_regd_5g; 834 }; 835 836 enum rtw_regd_state { 837 RTW_REGD_STATE_WORLDWIDE, 838 RTW_REGD_STATE_PROGRAMMED, 839 RTW_REGD_STATE_SETTING, 840 841 RTW_REGD_STATE_NR, 842 }; 843 844 struct rtw_regd { 845 enum rtw_regd_state state; 846 const struct rtw_regulatory *regulatory; 847 enum nl80211_dfs_regions dfs_region; 848 }; 849 850 struct rtw_chip_ops { 851 int (*power_on)(struct rtw_dev *rtwdev); 852 void (*power_off)(struct rtw_dev *rtwdev); 853 int (*mac_init)(struct rtw_dev *rtwdev); 854 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 855 void (*shutdown)(struct rtw_dev *rtwdev); 856 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 857 void (*phy_set_param)(struct rtw_dev *rtwdev); 858 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 859 u8 bandwidth, u8 primary_chan_idx); 860 void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status, 861 struct rtw_rx_pkt_stat *pkt_stat); 862 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 863 u32 addr, u32 mask); 864 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 865 u32 addr, u32 mask, u32 data); 866 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 867 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 868 u32 size); 869 int (*set_antenna)(struct rtw_dev *rtwdev, 870 u32 antenna_tx, 871 u32 antenna_rx); 872 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 873 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 874 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 875 void (*phy_calibration)(struct rtw_dev *rtwdev); 876 void (*dpk_track)(struct rtw_dev *rtwdev); 877 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 878 void (*pwr_track)(struct rtw_dev *rtwdev); 879 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 880 struct rtw_bfee *bfee, bool enable); 881 void (*set_gid_table)(struct rtw_dev *rtwdev, 882 struct ieee80211_vif *vif, 883 struct ieee80211_bss_conf *conf); 884 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 885 u8 fixrate_en, u8 *new_rate); 886 void (*adaptivity_init)(struct rtw_dev *rtwdev); 887 void (*adaptivity)(struct rtw_dev *rtwdev); 888 void (*cfo_init)(struct rtw_dev *rtwdev); 889 void (*cfo_track)(struct rtw_dev *rtwdev); 890 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 891 enum rtw_bb_path tx_path_1ss, 892 enum rtw_bb_path tx_path_cck, 893 bool is_tx2_path); 894 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 895 u8 rx_path, bool is_tx2_path); 896 void (*led_set)(struct led_classdev *led, enum led_brightness brightness); 897 /* for USB/SDIO only */ 898 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, 899 struct rtw_tx_pkt_info *pkt_info, 900 u8 *txdesc); 901 902 /* for coex */ 903 void (*coex_set_init)(struct rtw_dev *rtwdev); 904 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 905 u8 ctrl_type, u8 pos_type); 906 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 907 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 908 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 909 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 910 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 911 }; 912 913 #define RTW_PWR_POLLING_CNT 20000 914 915 #define RTW_PWR_CMD_READ 0x00 916 #define RTW_PWR_CMD_WRITE 0x01 917 #define RTW_PWR_CMD_POLLING 0x02 918 #define RTW_PWR_CMD_DELAY 0x03 919 #define RTW_PWR_CMD_END 0x04 920 921 /* define the base address of each block */ 922 #define RTW_PWR_ADDR_MAC 0x00 923 #define RTW_PWR_ADDR_USB 0x01 924 #define RTW_PWR_ADDR_PCIE 0x02 925 #define RTW_PWR_ADDR_SDIO 0x03 926 927 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 928 #define RTW_PWR_INTF_USB_MSK BIT(1) 929 #define RTW_PWR_INTF_PCI_MSK BIT(2) 930 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 931 932 #define RTW_PWR_CUT_TEST_MSK BIT(0) 933 #define RTW_PWR_CUT_A_MSK BIT(1) 934 #define RTW_PWR_CUT_B_MSK BIT(2) 935 #define RTW_PWR_CUT_C_MSK BIT(3) 936 #define RTW_PWR_CUT_D_MSK BIT(4) 937 #define RTW_PWR_CUT_E_MSK BIT(5) 938 #define RTW_PWR_CUT_F_MSK BIT(6) 939 #define RTW_PWR_CUT_G_MSK BIT(7) 940 #define RTW_PWR_CUT_ALL_MSK 0xFF 941 942 enum rtw_pwr_seq_cmd_delay_unit { 943 RTW_PWR_DELAY_US, 944 RTW_PWR_DELAY_MS, 945 }; 946 947 struct rtw_pwr_seq_cmd { 948 u16 offset; 949 u8 cut_mask; 950 u8 intf_mask; 951 u8 base:4; 952 u8 cmd:4; 953 u8 mask; 954 u8 value; 955 }; 956 957 enum rtw_chip_ver { 958 RTW_CHIP_VER_CUT_A = 0x00, 959 RTW_CHIP_VER_CUT_B = 0x01, 960 RTW_CHIP_VER_CUT_C = 0x02, 961 RTW_CHIP_VER_CUT_D = 0x03, 962 RTW_CHIP_VER_CUT_E = 0x04, 963 RTW_CHIP_VER_CUT_F = 0x05, 964 RTW_CHIP_VER_CUT_G = 0x06, 965 }; 966 967 #define RTW_INTF_PHY_PLATFORM_ALL 0 968 969 enum rtw_intf_phy_cut { 970 RTW_INTF_PHY_CUT_A = BIT(0), 971 RTW_INTF_PHY_CUT_B = BIT(1), 972 RTW_INTF_PHY_CUT_C = BIT(2), 973 RTW_INTF_PHY_CUT_D = BIT(3), 974 RTW_INTF_PHY_CUT_E = BIT(4), 975 RTW_INTF_PHY_CUT_F = BIT(5), 976 RTW_INTF_PHY_CUT_G = BIT(6), 977 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 978 }; 979 980 enum rtw_ip_sel { 981 RTW_IP_SEL_PHY = 0, 982 RTW_IP_SEL_MAC = 1, 983 RTW_IP_SEL_DBI = 2, 984 985 RTW_IP_SEL_UNDEF = 0xFFFF 986 }; 987 988 enum rtw_pq_map_id { 989 RTW_PQ_MAP_VO = 0x0, 990 RTW_PQ_MAP_VI = 0x1, 991 RTW_PQ_MAP_BE = 0x2, 992 RTW_PQ_MAP_BK = 0x3, 993 RTW_PQ_MAP_MG = 0x4, 994 RTW_PQ_MAP_HI = 0x5, 995 RTW_PQ_MAP_NUM = 0x6, 996 997 RTW_PQ_MAP_UNDEF, 998 }; 999 1000 enum rtw_dma_mapping { 1001 RTW_DMA_MAPPING_EXTRA = 0, 1002 RTW_DMA_MAPPING_LOW = 1, 1003 RTW_DMA_MAPPING_NORMAL = 2, 1004 RTW_DMA_MAPPING_HIGH = 3, 1005 1006 RTW_DMA_MAPPING_MAX, 1007 RTW_DMA_MAPPING_UNDEF, 1008 }; 1009 1010 struct rtw_rqpn { 1011 enum rtw_dma_mapping dma_map_vo; 1012 enum rtw_dma_mapping dma_map_vi; 1013 enum rtw_dma_mapping dma_map_be; 1014 enum rtw_dma_mapping dma_map_bk; 1015 enum rtw_dma_mapping dma_map_mg; 1016 enum rtw_dma_mapping dma_map_hi; 1017 }; 1018 1019 struct rtw_prioq_addr { 1020 u32 rsvd; 1021 u32 avail; 1022 }; 1023 1024 struct rtw_prioq_addrs { 1025 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1026 bool wsize; 1027 }; 1028 1029 struct rtw_page_table { 1030 u16 hq_num; 1031 u16 nq_num; 1032 u16 lq_num; 1033 u16 exq_num; 1034 u16 gapq_num; 1035 }; 1036 1037 struct rtw_intf_phy_para { 1038 u16 offset; 1039 u16 value; 1040 u16 ip_sel; 1041 u16 cut_mask; 1042 u16 platform; 1043 }; 1044 1045 struct rtw_wow_pattern { 1046 u16 crc; 1047 u8 type; 1048 u8 valid; 1049 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1050 }; 1051 1052 struct rtw_pno_request { 1053 bool inited; 1054 u32 match_set_cnt; 1055 struct cfg80211_match_set *match_sets; 1056 u8 channel_cnt; 1057 struct ieee80211_channel *channels; 1058 struct cfg80211_sched_scan_plan scan_plan; 1059 }; 1060 1061 struct rtw_wow_param { 1062 struct ieee80211_vif *wow_vif; 1063 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1064 u8 txpause; 1065 u8 pattern_cnt; 1066 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1067 1068 bool ips_enabled; 1069 struct rtw_pno_request pno_req; 1070 }; 1071 1072 struct rtw_intf_phy_para_table { 1073 const struct rtw_intf_phy_para *usb2_para; 1074 const struct rtw_intf_phy_para *usb3_para; 1075 const struct rtw_intf_phy_para *gen1_para; 1076 const struct rtw_intf_phy_para *gen2_para; 1077 u8 n_usb2_para; 1078 u8 n_usb3_para; 1079 u8 n_gen1_para; 1080 u8 n_gen2_para; 1081 }; 1082 1083 struct rtw_table { 1084 const void *data; 1085 const u32 size; 1086 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1087 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1088 u32 addr, u32 data); 1089 enum rtw_rf_path rf_path; 1090 }; 1091 1092 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1093 const struct rtw_table *tbl) 1094 { 1095 (*tbl->parse)(rtwdev, tbl); 1096 } 1097 1098 enum rtw_rfe_fem { 1099 RTW_RFE_IFEM, 1100 RTW_RFE_EFEM, 1101 RTW_RFE_IFEM2G_EFEM5G, 1102 RTW_RFE_NUM, 1103 }; 1104 1105 struct rtw_rfe_def { 1106 const struct rtw_table *phy_pg_tbl; 1107 const struct rtw_table *txpwr_lmt_tbl; 1108 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1109 const struct rtw_table *agc_btg_tbl; 1110 }; 1111 1112 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt, track) { \ 1113 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1114 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1115 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \ 1116 } 1117 1118 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, track, btg) { \ 1119 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1120 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1121 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \ 1122 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1123 } 1124 1125 #define RTW_PWR_TRK_5G_1 0 1126 #define RTW_PWR_TRK_5G_2 1 1127 #define RTW_PWR_TRK_5G_3 2 1128 #define RTW_PWR_TRK_5G_NUM 3 1129 1130 #define RTW_PWR_TRK_TBL_SZ 30 1131 1132 /* This table stores the values of TX power that will be adjusted by power 1133 * tracking. 1134 * 1135 * For 5G bands, there are 3 different settings. 1136 * For 2G there are cck rate and ofdm rate with different settings. 1137 */ 1138 struct rtw_pwr_track_tbl { 1139 const u8 *pwrtrk_5gd_n[RTW_PWR_TRK_5G_NUM]; 1140 const u8 *pwrtrk_5gd_p[RTW_PWR_TRK_5G_NUM]; 1141 const u8 *pwrtrk_5gc_n[RTW_PWR_TRK_5G_NUM]; 1142 const u8 *pwrtrk_5gc_p[RTW_PWR_TRK_5G_NUM]; 1143 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1144 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1145 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1146 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1147 const u8 *pwrtrk_2gd_n; 1148 const u8 *pwrtrk_2gd_p; 1149 const u8 *pwrtrk_2gc_n; 1150 const u8 *pwrtrk_2gc_p; 1151 const u8 *pwrtrk_2gb_n; 1152 const u8 *pwrtrk_2gb_p; 1153 const u8 *pwrtrk_2ga_n; 1154 const u8 *pwrtrk_2ga_p; 1155 const u8 *pwrtrk_2g_cckd_n; 1156 const u8 *pwrtrk_2g_cckd_p; 1157 const u8 *pwrtrk_2g_cckc_n; 1158 const u8 *pwrtrk_2g_cckc_p; 1159 const u8 *pwrtrk_2g_cckb_n; 1160 const u8 *pwrtrk_2g_cckb_p; 1161 const u8 *pwrtrk_2g_ccka_n; 1162 const u8 *pwrtrk_2g_ccka_p; 1163 const s8 *pwrtrk_xtal_n; 1164 const s8 *pwrtrk_xtal_p; 1165 }; 1166 1167 enum rtw_wlan_cpu { 1168 RTW_WCPU_11AC, 1169 RTW_WCPU_11N, 1170 }; 1171 1172 enum rtw_fw_fifo_sel { 1173 RTW_FW_FIFO_SEL_TX, 1174 RTW_FW_FIFO_SEL_RX, 1175 RTW_FW_FIFO_SEL_RSVD_PAGE, 1176 RTW_FW_FIFO_SEL_REPORT, 1177 RTW_FW_FIFO_SEL_LLT, 1178 RTW_FW_FIFO_SEL_RXBUF_FW, 1179 1180 RTW_FW_FIFO_MAX, 1181 }; 1182 1183 enum rtw_fwcd_item { 1184 RTW_FWCD_TLV, 1185 RTW_FWCD_REG, 1186 RTW_FWCD_ROM, 1187 RTW_FWCD_IMEM, 1188 RTW_FWCD_DMEM, 1189 RTW_FWCD_EMEM, 1190 }; 1191 1192 /* hardware configuration for each IC */ 1193 struct rtw_chip_info { 1194 const struct rtw_chip_ops *ops; 1195 u8 id; 1196 1197 const char *fw_name; 1198 enum rtw_wlan_cpu wlan_cpu; 1199 u8 tx_pkt_desc_sz; 1200 u8 tx_buf_desc_sz; 1201 u8 rx_pkt_desc_sz; 1202 u8 rx_buf_desc_sz; 1203 u32 phy_efuse_size; 1204 u32 log_efuse_size; 1205 u32 ptct_efuse_size; 1206 u32 txff_size; 1207 u32 rxff_size; 1208 u32 fw_rxff_size; 1209 u16 rsvd_drv_pg_num; 1210 u8 band; 1211 u16 page_size; 1212 u8 csi_buf_pg_num; 1213 u8 dig_max; 1214 u8 dig_min; 1215 u8 txgi_factor; 1216 bool is_pwr_by_rate_dec; 1217 bool rx_ldpc; 1218 bool tx_stbc; 1219 u8 max_power_index; 1220 u8 ampdu_density; 1221 1222 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1223 const struct rtw_fwcd_segs *fwcd_segs; 1224 1225 u8 usb_tx_agg_desc_num; 1226 bool hw_feature_report; 1227 u8 c2h_ra_report_size; 1228 bool old_datarate_fb_limit; 1229 1230 u8 default_1ss_tx_path; 1231 1232 bool path_div_supported; 1233 bool ht_supported; 1234 bool vht_supported; 1235 u8 lps_deep_mode_supported; 1236 1237 /* init values */ 1238 u8 sys_func_en; 1239 const struct rtw_pwr_seq_cmd * const *pwr_on_seq; 1240 const struct rtw_pwr_seq_cmd * const *pwr_off_seq; 1241 const struct rtw_rqpn *rqpn_table; 1242 const struct rtw_prioq_addrs *prioq_addrs; 1243 const struct rtw_page_table *page_table; 1244 const struct rtw_intf_phy_para_table *intf_table; 1245 1246 const struct rtw_hw_reg *dig; 1247 const struct rtw_hw_reg *dig_cck; 1248 u32 rf_base_addr[RTW_RF_PATH_MAX]; 1249 u32 rf_sipi_addr[RTW_RF_PATH_MAX]; 1250 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1251 u8 fix_rf_phy_num; 1252 const struct rtw_ltecoex_addr *ltecoex_addr; 1253 1254 const struct rtw_table *mac_tbl; 1255 const struct rtw_table *agc_tbl; 1256 const struct rtw_table *bb_tbl; 1257 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1258 const struct rtw_table *rfk_init_tbl; 1259 1260 const struct rtw_rfe_def *rfe_defs; 1261 u32 rfe_defs_size; 1262 1263 bool en_dis_dpd; 1264 u16 dpd_ratemask; 1265 u8 iqk_threshold; 1266 u8 lck_threshold; 1267 1268 u8 bfer_su_max_num; 1269 u8 bfer_mu_max_num; 1270 1271 const struct rtw_hw_reg_offset *edcca_th; 1272 s8 l2h_th_ini_cs; 1273 s8 l2h_th_ini_ad; 1274 1275 const char *wow_fw_name; 1276 const struct wiphy_wowlan_support *wowlan_stub; 1277 const u8 max_sched_scan_ssids; 1278 const u16 max_scan_ie_len; 1279 1280 /* coex paras */ 1281 u32 coex_para_ver; 1282 u8 bt_desired_ver; 1283 bool scbd_support; 1284 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1285 bool ble_hid_profile_support; 1286 bool wl_mimo_ps_support; 1287 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1288 u8 bt_rssi_type; 1289 u8 ant_isolation; 1290 u8 rssi_tolerance; 1291 u8 table_sant_num; 1292 u8 table_nsant_num; 1293 u8 tdma_sant_num; 1294 u8 tdma_nsant_num; 1295 u8 bt_afh_span_bw20; 1296 u8 bt_afh_span_bw40; 1297 u8 afh_5g_num; 1298 u8 wl_rf_para_num; 1299 u8 coex_info_hw_regs_num; 1300 const u8 *bt_rssi_step; 1301 const u8 *wl_rssi_step; 1302 const struct coex_table_para *table_nsant; 1303 const struct coex_table_para *table_sant; 1304 const struct coex_tdma_para *tdma_sant; 1305 const struct coex_tdma_para *tdma_nsant; 1306 const struct coex_rf_para *wl_rf_para_tx; 1307 const struct coex_rf_para *wl_rf_para_rx; 1308 const struct coex_5g_afh_map *afh_5g; 1309 const struct rtw_hw_reg *btg_reg; 1310 const struct rtw_reg_domain *coex_info_hw_regs; 1311 u32 wl_fw_desired_ver; 1312 }; 1313 1314 enum rtw_coex_bt_state_cnt { 1315 COEX_CNT_BT_RETRY, 1316 COEX_CNT_BT_REINIT, 1317 COEX_CNT_BT_REENABLE, 1318 COEX_CNT_BT_POPEVENT, 1319 COEX_CNT_BT_SETUPLINK, 1320 COEX_CNT_BT_IGNWLANACT, 1321 COEX_CNT_BT_INQ, 1322 COEX_CNT_BT_PAGE, 1323 COEX_CNT_BT_ROLESWITCH, 1324 COEX_CNT_BT_AFHUPDATE, 1325 COEX_CNT_BT_INFOUPDATE, 1326 COEX_CNT_BT_IQK, 1327 COEX_CNT_BT_IQKFAIL, 1328 1329 COEX_CNT_BT_MAX 1330 }; 1331 1332 enum rtw_coex_wl_state_cnt { 1333 COEX_CNT_WL_SCANAP, 1334 COEX_CNT_WL_CONNPKT, 1335 COEX_CNT_WL_COEXRUN, 1336 COEX_CNT_WL_NOISY0, 1337 COEX_CNT_WL_NOISY1, 1338 COEX_CNT_WL_NOISY2, 1339 COEX_CNT_WL_5MS_NOEXTEND, 1340 COEX_CNT_WL_FW_NOTIFY, 1341 1342 COEX_CNT_WL_MAX 1343 }; 1344 1345 struct rtw_coex_rfe { 1346 bool ant_switch_exist; 1347 bool ant_switch_diversity; 1348 bool ant_switch_with_bt; 1349 u8 rfe_module_type; 1350 u8 ant_switch_polarity; 1351 1352 /* true if WLG at BTG, else at WLAG */ 1353 bool wlg_at_btg; 1354 }; 1355 1356 #define COEX_WL_TDMA_PARA_LENGTH 5 1357 1358 struct rtw_coex_dm { 1359 bool cur_ps_tdma_on; 1360 bool cur_wl_rx_low_gain_en; 1361 bool ignore_wl_act; 1362 1363 u8 reason; 1364 u8 bt_rssi_state[4]; 1365 u8 wl_rssi_state[4]; 1366 u8 wl_ch_info[3]; 1367 u8 cur_ps_tdma; 1368 u8 cur_table; 1369 u8 ps_tdma_para[5]; 1370 u8 cur_bt_pwr_lvl; 1371 u8 cur_bt_lna_lvl; 1372 u8 cur_wl_pwr_lvl; 1373 u8 bt_status; 1374 u32 cur_ant_pos_type; 1375 u32 cur_switch_status; 1376 u32 setting_tdma; 1377 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1378 }; 1379 1380 #define COEX_BTINFO_SRC_WL_FW 0x0 1381 #define COEX_BTINFO_SRC_BT_RSP 0x1 1382 #define COEX_BTINFO_SRC_BT_ACT 0x2 1383 #define COEX_BTINFO_SRC_BT_IQK 0x3 1384 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1385 #define COEX_BTINFO_SRC_H2C60 0x5 1386 #define COEX_BTINFO_SRC_MAX 0x6 1387 1388 #define COEX_INFO_FTP BIT(7) 1389 #define COEX_INFO_A2DP BIT(6) 1390 #define COEX_INFO_HID BIT(5) 1391 #define COEX_INFO_SCO_BUSY BIT(4) 1392 #define COEX_INFO_ACL_BUSY BIT(3) 1393 #define COEX_INFO_INQ_PAGE BIT(2) 1394 #define COEX_INFO_SCO_ESCO BIT(1) 1395 #define COEX_INFO_CONNECTION BIT(0) 1396 #define COEX_BTINFO_LENGTH_MAX 10 1397 #define COEX_BTINFO_LENGTH 7 1398 1399 #define COEX_BT_HIDINFO_LIST 0x0 1400 #define COEX_BT_HIDINFO_A 0x1 1401 #define COEX_BT_HIDINFO_NAME 3 1402 1403 #define COEX_BT_HIDINFO_LENGTH 6 1404 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1405 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1406 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1407 #define COEX_BT_BLE_HANDLE_THRS 0x10 1408 #define COEX_BT_HIDINFO_NOTCON 0xff 1409 1410 struct rtw_coex_hid { 1411 u8 hid_handle; 1412 u8 hid_vendor; 1413 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1414 bool hid_info_completed; 1415 bool is_game_hid; 1416 }; 1417 1418 struct rtw_coex_hid_handle_list { 1419 u8 cmd_id; 1420 u8 len; 1421 u8 subid; 1422 u8 handle_cnt; 1423 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1424 } __packed; 1425 1426 struct rtw_coex_hid_info_a { 1427 u8 cmd_id; 1428 u8 len; 1429 u8 subid; 1430 u8 handle; 1431 u8 vendor; 1432 u8 name[COEX_BT_HIDINFO_NAME]; 1433 } __packed; 1434 1435 struct rtw_coex_stat { 1436 bool bt_disabled; 1437 bool bt_disabled_pre; 1438 bool bt_link_exist; 1439 bool bt_whck_test; 1440 bool bt_inq_page; 1441 bool bt_inq_remain; 1442 bool bt_inq; 1443 bool bt_page; 1444 bool bt_ble_voice; 1445 bool bt_ble_exist; 1446 bool bt_hfp_exist; 1447 bool bt_a2dp_exist; 1448 bool bt_hid_exist; 1449 bool bt_pan_exist; /* PAN or OPP */ 1450 bool bt_opp_exist; /* OPP only */ 1451 bool bt_acl_busy; 1452 bool bt_fix_2M; 1453 bool bt_setup_link; 1454 bool bt_multi_link; 1455 bool bt_multi_link_pre; 1456 bool bt_multi_link_remain; 1457 bool bt_a2dp_sink; 1458 bool bt_a2dp_active; 1459 bool bt_reenable; 1460 bool bt_ble_scan_en; 1461 bool bt_init_scan; 1462 bool bt_slave; 1463 bool bt_418_hid_exist; 1464 bool bt_ble_hid_exist; 1465 bool bt_game_hid_exist; 1466 bool bt_hid_handle_cnt; 1467 bool bt_mailbox_reply; 1468 1469 bool wl_under_lps; 1470 bool wl_under_ips; 1471 bool wl_hi_pri_task1; 1472 bool wl_hi_pri_task2; 1473 bool wl_force_lps_ctrl; 1474 bool wl_gl_busy; 1475 bool wl_linkscan_proc; 1476 bool wl_ps_state_fail; 1477 bool wl_tx_limit_en; 1478 bool wl_ampdu_limit_en; 1479 bool wl_connected; 1480 bool wl_slot_extend; 1481 bool wl_cck_lock; 1482 bool wl_cck_lock_pre; 1483 bool wl_cck_lock_ever; 1484 bool wl_connecting; 1485 bool wl_slot_toggle; 1486 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1487 bool wl_mimo_ps; 1488 1489 u32 bt_supported_version; 1490 u32 bt_supported_feature; 1491 u32 hi_pri_tx; 1492 u32 hi_pri_rx; 1493 u32 lo_pri_tx; 1494 u32 lo_pri_rx; 1495 u32 patch_ver; 1496 u16 bt_reg_vendor_ae; 1497 u16 bt_reg_vendor_ac; 1498 s8 bt_rssi; 1499 u8 kt_ver; 1500 u8 gnt_workaround_state; 1501 u8 tdma_timer_base; 1502 u8 bt_profile_num; 1503 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1504 u8 bt_info_lb2; 1505 u8 bt_info_lb3; 1506 u8 bt_info_hb0; 1507 u8 bt_info_hb1; 1508 u8 bt_info_hb2; 1509 u8 bt_info_hb3; 1510 u8 bt_ble_scan_type; 1511 u8 bt_hid_pair_num; 1512 u8 bt_hid_slot; 1513 u8 bt_a2dp_bitpool; 1514 u8 bt_iqk_state; 1515 u8 bt_disable_cnt; 1516 1517 u16 wl_beacon_interval; 1518 u8 wl_noisy_level; 1519 u8 wl_fw_dbg_info[10]; 1520 u8 wl_fw_dbg_info_pre[10]; 1521 u8 wl_rx_rate; 1522 u8 wl_tx_rate; 1523 u8 wl_rts_rx_rate; 1524 u8 wl_coex_mode; 1525 u8 wl_iot_peer; 1526 u8 ampdu_max_time; 1527 u8 wl_tput_dir; 1528 1529 u8 wl_toggle_para[6]; 1530 u8 wl_toggle_interval; 1531 1532 u16 score_board; 1533 u16 retry_limit; 1534 1535 /* counters to record bt states */ 1536 u32 cnt_bt[COEX_CNT_BT_MAX]; 1537 1538 /* counters to record wifi states */ 1539 u32 cnt_wl[COEX_CNT_WL_MAX]; 1540 1541 /* counters to record bt c2h data */ 1542 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1543 1544 u32 darfrc; 1545 u32 darfrch; 1546 1547 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1548 struct rtw_coex_hid_handle_list hid_handle_list; 1549 }; 1550 1551 struct rtw_coex { 1552 struct sk_buff_head queue; 1553 wait_queue_head_t wait; 1554 1555 bool under_5g; 1556 bool stop_dm; 1557 bool freeze; 1558 bool freerun; 1559 bool wl_rf_off; 1560 bool manual_control; 1561 1562 struct rtw_coex_stat stat; 1563 struct rtw_coex_dm dm; 1564 struct rtw_coex_rfe rfe; 1565 1566 struct delayed_work bt_relink_work; 1567 struct delayed_work bt_reenable_work; 1568 struct delayed_work defreeze_work; 1569 struct delayed_work wl_remain_work; 1570 struct delayed_work bt_remain_work; 1571 struct delayed_work wl_connecting_work; 1572 struct delayed_work bt_multi_link_remain_work; 1573 struct delayed_work wl_ccklock_work; 1574 1575 }; 1576 1577 #define DPK_RF_REG_NUM 7 1578 #define DPK_RF_PATH_NUM 2 1579 #define DPK_BB_REG_NUM 18 1580 #define DPK_CHANNEL_WIDTH_80 1 1581 1582 DECLARE_EWMA(thermal, 10, 4); 1583 1584 struct rtw_dpk_info { 1585 bool is_dpk_pwr_on; 1586 bool is_reload; 1587 1588 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1589 1590 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1591 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1592 1593 u32 gnt_control; 1594 u32 gnt_value; 1595 1596 u8 result[RTW_RF_PATH_MAX]; 1597 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1598 u32 coef[RTW_RF_PATH_MAX][20]; 1599 u16 dpk_gs[RTW_RF_PATH_MAX]; 1600 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1601 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1602 1603 u8 dpk_band; 1604 u8 dpk_ch; 1605 u8 dpk_bw; 1606 }; 1607 1608 struct rtw_phy_cck_pd_reg { 1609 u32 reg_pd; 1610 u32 mask_pd; 1611 u32 reg_cs; 1612 u32 mask_cs; 1613 }; 1614 1615 #define DACK_MSBK_BACKUP_NUM 0xf 1616 #define DACK_DCK_BACKUP_NUM 0x2 1617 1618 struct rtw_swing_table { 1619 const u8 *p[RTW_RF_PATH_MAX]; 1620 const u8 *n[RTW_RF_PATH_MAX]; 1621 }; 1622 1623 struct rtw_pkt_count { 1624 u16 num_bcn_pkt; 1625 u16 num_qry_pkt[DESC_RATE_MAX]; 1626 }; 1627 1628 DECLARE_EWMA(evm, 10, 4); 1629 DECLARE_EWMA(snr, 10, 4); 1630 1631 struct rtw_iqk_info { 1632 bool done; 1633 struct { 1634 u32 s1_x; 1635 u32 s1_y; 1636 u32 s0_x; 1637 u32 s0_y; 1638 } result; 1639 }; 1640 1641 enum rtw_rf_band { 1642 RF_BAND_2G_CCK, 1643 RF_BAND_2G_OFDM, 1644 RF_BAND_5G_L, 1645 RF_BAND_5G_M, 1646 RF_BAND_5G_H, 1647 RF_BAND_MAX 1648 }; 1649 1650 #define RF_GAIN_NUM 11 1651 #define RF_HW_OFFSET_NUM 10 1652 1653 struct rtw_gapk_info { 1654 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1655 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1656 bool txgapk_bp_done; 1657 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1658 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1659 u8 read_txgain; 1660 u8 channel; 1661 }; 1662 1663 #define EDCCA_TH_L2H_IDX 0 1664 #define EDCCA_TH_H2L_IDX 1 1665 #define EDCCA_TH_L2H_LB 48 1666 #define EDCCA_ADC_BACKOFF 12 1667 #define EDCCA_IGI_BASE 50 1668 #define EDCCA_IGI_L2H_DIFF 8 1669 #define EDCCA_L2H_H2L_DIFF 7 1670 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1671 1672 enum rtw_edcca_mode { 1673 RTW_EDCCA_NORMAL = 0, 1674 RTW_EDCCA_ADAPTIVITY = 1, 1675 }; 1676 1677 struct rtw_cfo_track { 1678 bool is_adjust; 1679 u8 crystal_cap; 1680 s32 cfo_tail[RTW_RF_PATH_MAX]; 1681 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1682 u32 packet_count; 1683 u32 packet_count_pre; 1684 }; 1685 1686 #define RRSR_INIT_2G 0x15f 1687 #define RRSR_INIT_5G 0x150 1688 1689 enum rtw_dm_cap { 1690 RTW_DM_CAP_NA, 1691 RTW_DM_CAP_TXGAPK, 1692 RTW_DM_CAP_NUM 1693 }; 1694 1695 struct rtw_dm_info { 1696 u32 cck_fa_cnt; 1697 u32 ofdm_fa_cnt; 1698 u32 total_fa_cnt; 1699 u32 cck_cca_cnt; 1700 u32 ofdm_cca_cnt; 1701 u32 total_cca_cnt; 1702 1703 u32 cck_ok_cnt; 1704 u32 cck_err_cnt; 1705 u32 ofdm_ok_cnt; 1706 u32 ofdm_err_cnt; 1707 u32 ht_ok_cnt; 1708 u32 ht_err_cnt; 1709 u32 vht_ok_cnt; 1710 u32 vht_err_cnt; 1711 1712 u8 min_rssi; 1713 u8 pre_min_rssi; 1714 u16 fa_history[4]; 1715 u8 igi_history[4]; 1716 u8 igi_bitmap; 1717 bool damping; 1718 u8 damping_cnt; 1719 u8 damping_rssi; 1720 1721 u8 cck_gi_u_bnd; 1722 u8 cck_gi_l_bnd; 1723 1724 u8 fix_rate; 1725 u8 tx_rate; 1726 u32 rrsr_val_init; 1727 u32 rrsr_mask_min; 1728 u8 thermal_avg[RTW_RF_PATH_MAX]; 1729 u8 thermal_meter_k; 1730 u8 thermal_meter_lck; 1731 s8 delta_power_index[RTW_RF_PATH_MAX]; 1732 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1733 u8 default_ofdm_index; 1734 u8 default_cck_index; 1735 bool pwr_trk_triggered; 1736 bool pwr_trk_init_trigger; 1737 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1738 s8 txagc_remnant_cck; 1739 s8 txagc_remnant_ofdm[RTW_RF_PATH_MAX]; 1740 u8 rx_cck_agc_report_type; 1741 1742 /* backup dack results for each path and I/Q */ 1743 u32 dack_adck[RTW_RF_PATH_MAX]; 1744 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1745 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1746 1747 struct rtw_dpk_info dpk_info; 1748 struct rtw_cfo_track cfo_track; 1749 1750 /* [bandwidth 0:20M/1:40M][number of path] */ 1751 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1752 u32 cck_fa_avg; 1753 u8 cck_pd_default; 1754 1755 /* save the last rx phy status for debug */ 1756 s8 rx_snr[RTW_RF_PATH_MAX]; 1757 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1758 s16 cfo_tail[RTW_RF_PATH_MAX]; 1759 u8 rssi[RTW_RF_PATH_MAX]; 1760 u8 curr_rx_rate; 1761 struct rtw_pkt_count cur_pkt_count; 1762 struct rtw_pkt_count last_pkt_count; 1763 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1764 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1765 1766 u32 dm_flags; /* enum rtw_dm_cap */ 1767 struct rtw_iqk_info iqk; 1768 struct rtw_gapk_info gapk; 1769 bool is_bt_iqk_timeout; 1770 1771 s8 l2h_th_ini; 1772 enum rtw_edcca_mode edcca_mode; 1773 u8 scan_density; 1774 }; 1775 1776 struct rtw_efuse { 1777 u32 size; 1778 u32 physical_size; 1779 u32 logical_size; 1780 u32 protect_size; 1781 1782 u8 addr[ETH_ALEN]; 1783 u8 channel_plan; 1784 u8 country_code[2]; 1785 u8 rf_board_option; 1786 u8 rfe_option; 1787 u8 power_track_type; 1788 u8 thermal_meter[RTW_RF_PATH_MAX]; 1789 u8 thermal_meter_k; 1790 u8 crystal_cap; 1791 u8 ant_div_cfg; 1792 u8 ant_div_type; 1793 u8 regd; 1794 u8 afe; 1795 1796 u8 lna_type_2g; 1797 u8 lna_type_5g; 1798 u8 glna_type; 1799 u8 alna_type; 1800 bool ext_lna_2g; 1801 bool ext_lna_5g; 1802 u8 pa_type_2g; 1803 u8 pa_type_5g; 1804 u8 gpa_type; 1805 u8 apa_type; 1806 bool ext_pa_2g; 1807 bool ext_pa_5g; 1808 u8 tx_bb_swing_setting_2g; 1809 u8 tx_bb_swing_setting_5g; 1810 1811 bool btcoex; 1812 /* bt share antenna with wifi */ 1813 bool share_ant; 1814 u8 bt_setting; 1815 1816 u8 usb_mode_switch; 1817 1818 struct { 1819 u8 hci; 1820 u8 bw; 1821 u8 ptcl; 1822 u8 nss; 1823 u8 ant_num; 1824 } hw_cap; 1825 1826 struct rtw_txpwr_idx txpwr_idx_table[4]; 1827 }; 1828 1829 struct rtw_phy_cond { 1830 #ifdef __LITTLE_ENDIAN 1831 u32 rfe:8; 1832 u32 intf:4; 1833 u32 pkg:4; 1834 u32 plat:4; 1835 u32 intf_rsvd:4; 1836 u32 cut:4; 1837 u32 branch:2; 1838 u32 neg:1; 1839 u32 pos:1; 1840 #else 1841 u32 pos:1; 1842 u32 neg:1; 1843 u32 branch:2; 1844 u32 cut:4; 1845 u32 intf_rsvd:4; 1846 u32 plat:4; 1847 u32 pkg:4; 1848 u32 intf:4; 1849 u32 rfe:8; 1850 #endif 1851 /* for intf:4 */ 1852 #define INTF_PCIE BIT(0) 1853 #define INTF_USB BIT(1) 1854 #define INTF_SDIO BIT(2) 1855 /* for branch:2 */ 1856 #define BRANCH_IF 0 1857 #define BRANCH_ELIF 1 1858 #define BRANCH_ELSE 2 1859 #define BRANCH_ENDIF 3 1860 }; 1861 1862 struct rtw_phy_cond2 { 1863 #ifdef __LITTLE_ENDIAN 1864 u8 type_glna; 1865 u8 type_gpa; 1866 u8 type_alna; 1867 u8 type_apa; 1868 #else 1869 u8 type_apa; 1870 u8 type_alna; 1871 u8 type_gpa; 1872 u8 type_glna; 1873 #endif 1874 }; 1875 1876 struct rtw_fifo_conf { 1877 /* tx fifo information */ 1878 u16 rsvd_boundary; 1879 u16 rsvd_pg_num; 1880 u16 rsvd_drv_pg_num; 1881 u16 txff_pg_num; 1882 u16 acq_pg_num; 1883 u16 rsvd_drv_addr; 1884 u16 rsvd_h2c_info_addr; 1885 u16 rsvd_h2c_sta_info_addr; 1886 u16 rsvd_h2cq_addr; 1887 u16 rsvd_cpu_instr_addr; 1888 u16 rsvd_fw_txbuf_addr; 1889 u16 rsvd_csibuf_addr; 1890 const struct rtw_rqpn *rqpn; 1891 }; 1892 1893 struct rtw_fwcd_desc { 1894 u32 size; 1895 u8 *next; 1896 u8 *data; 1897 }; 1898 1899 struct rtw_fwcd_segs { 1900 const u32 *segs; 1901 u8 num; 1902 }; 1903 1904 #define FW_CD_TYPE 0xffff 1905 #define FW_CD_LEN 4 1906 #define FW_CD_VAL 0xaabbccdd 1907 struct rtw_fw_state { 1908 const struct firmware *firmware; 1909 struct rtw_dev *rtwdev; 1910 struct completion completion; 1911 struct rtw_fwcd_desc fwcd_desc; 1912 u16 version; 1913 u8 sub_version; 1914 u8 sub_index; 1915 u16 h2c_version; 1916 u32 feature; 1917 u32 feature_ext; 1918 enum rtw_fw_type type; 1919 }; 1920 1921 enum rtw_sar_sources { 1922 RTW_SAR_SOURCE_NONE, 1923 RTW_SAR_SOURCE_COMMON, 1924 }; 1925 1926 enum rtw_sar_bands { 1927 RTW_SAR_BAND_0, 1928 RTW_SAR_BAND_1, 1929 /* RTW_SAR_BAND_2, not used now */ 1930 RTW_SAR_BAND_3, 1931 RTW_SAR_BAND_4, 1932 1933 RTW_SAR_BAND_NR, 1934 }; 1935 1936 /* the union is reserved for other kinds of SAR sources 1937 * which might not re-use same format with array common. 1938 */ 1939 union rtw_sar_cfg { 1940 s8 common[RTW_SAR_BAND_NR]; 1941 }; 1942 1943 struct rtw_sar { 1944 enum rtw_sar_sources src; 1945 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_NUM]; 1946 }; 1947 1948 struct rtw_hal { 1949 u32 rcr; 1950 1951 u32 chip_version; 1952 u8 cut_version; 1953 u8 mp_chip; 1954 u8 oem_id; 1955 u8 pkg_type; 1956 struct rtw_phy_cond phy_cond; 1957 struct rtw_phy_cond2 phy_cond2; 1958 bool rfe_btg; 1959 1960 u8 ps_mode; 1961 u8 current_channel; 1962 u8 current_primary_channel_index; 1963 u8 current_band_width; 1964 u8 current_band_type; 1965 u8 primary_channel; 1966 1967 /* center channel for different available bandwidth, 1968 * val of (bw > current_band_width) is invalid 1969 */ 1970 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1971 1972 u8 sec_ch_offset; 1973 u8 rf_type; 1974 u8 rf_path_num; 1975 u8 rf_phy_num; 1976 u32 antenna_tx; 1977 u32 antenna_rx; 1978 u8 bfee_sts_cap; 1979 bool txrx_1ss; 1980 bool cck_high_power; 1981 1982 /* protect tx power section */ 1983 struct mutex tx_power_mutex; 1984 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1985 [DESC_RATE_MAX]; 1986 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1987 [DESC_RATE_MAX]; 1988 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1989 [RTW_RATE_SECTION_NUM]; 1990 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1991 [RTW_RATE_SECTION_NUM]; 1992 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1993 [RTW_CHANNEL_WIDTH_MAX] 1994 [RTW_RATE_SECTION_NUM] 1995 [RTW_MAX_CHANNEL_NUM_2G]; 1996 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1997 [RTW_CHANNEL_WIDTH_MAX] 1998 [RTW_RATE_SECTION_NUM] 1999 [RTW_MAX_CHANNEL_NUM_5G]; 2000 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 2001 [DESC_RATE_MAX]; 2002 2003 enum rtw_sar_bands sar_band; 2004 struct rtw_sar sar; 2005 2006 /* for 8821c set channel */ 2007 u32 ch_param[3]; 2008 }; 2009 2010 struct rtw_path_div { 2011 enum rtw_bb_path current_tx_path; 2012 u32 path_a_sum; 2013 u32 path_b_sum; 2014 u16 path_a_cnt; 2015 u16 path_b_cnt; 2016 }; 2017 2018 struct rtw_chan_info { 2019 int pri_ch_idx; 2020 int action_id; 2021 int bw; 2022 u8 extra_info; 2023 u8 channel; 2024 u16 timeout; 2025 }; 2026 2027 struct rtw_chan_list { 2028 u32 buf_size; 2029 u32 ch_num; 2030 u32 size; 2031 u16 addr; 2032 }; 2033 2034 struct rtw_hw_scan_info { 2035 struct ieee80211_vif *scanning_vif; 2036 u8 probe_pg_size; 2037 u8 op_pri_ch_idx; 2038 u8 op_pri_ch; 2039 u8 op_chan; 2040 u8 op_bw; 2041 }; 2042 2043 struct rtw_dev { 2044 struct ieee80211_hw *hw; 2045 struct device *dev; 2046 2047 struct rtw_hci hci; 2048 2049 struct rtw_hw_scan_info scan_info; 2050 const struct rtw_chip_info *chip; 2051 struct rtw_hal hal; 2052 struct rtw_fifo_conf fifo; 2053 struct rtw_fw_state fw; 2054 struct rtw_efuse efuse; 2055 struct rtw_sec_desc sec; 2056 struct rtw_traffic_stats stats; 2057 struct rtw_regd regd; 2058 struct rtw_bf_info bf_info; 2059 2060 struct rtw_dm_info dm_info; 2061 struct rtw_coex coex; 2062 2063 /* ensures exclusive access from mac80211 callbacks */ 2064 struct mutex mutex; 2065 2066 /* watch dog every 2 sec */ 2067 struct delayed_work watch_dog_work; 2068 u32 watch_dog_cnt; 2069 2070 struct list_head rsvd_page_list; 2071 2072 /* c2h cmd queue & handler work */ 2073 struct sk_buff_head c2h_queue; 2074 struct work_struct c2h_work; 2075 struct work_struct ips_work; 2076 struct work_struct fw_recovery_work; 2077 struct work_struct update_beacon_work; 2078 2079 /* used to protect txqs list */ 2080 spinlock_t txq_lock; 2081 struct list_head txqs; 2082 struct workqueue_struct *tx_wq; 2083 struct work_struct tx_work; 2084 struct work_struct ba_work; 2085 2086 struct rtw_tx_report tx_report; 2087 2088 struct { 2089 /* indicate the mail box to use with fw */ 2090 u8 last_box_num; 2091 u32 seq; 2092 } h2c; 2093 2094 /* lps power state & handler work */ 2095 struct rtw_lps_conf lps_conf; 2096 bool ps_enabled; 2097 bool beacon_loss; 2098 struct completion lps_leave_check; 2099 2100 struct rtw_debugfs *debugfs; 2101 2102 u8 sta_cnt; 2103 u32 rts_threshold; 2104 2105 DECLARE_BITMAP(hw_port, RTW_PORT_NUM); 2106 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2107 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2108 2109 u8 mp_mode; 2110 struct rtw_path_div dm_path_div; 2111 2112 struct rtw_fw_state wow_fw; 2113 struct rtw_wow_param wow; 2114 2115 bool need_rfk; 2116 struct completion fw_scan_density; 2117 bool ap_active; 2118 2119 bool led_registered; 2120 char led_name[32]; 2121 struct led_classdev led_cdev; 2122 2123 /* hci related data, must be last */ 2124 u8 priv[] __aligned(sizeof(void *)); 2125 }; 2126 2127 #include "hci.h" 2128 2129 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2130 { 2131 return !!rtwdev->sta_cnt; 2132 } 2133 2134 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2135 { 2136 void *p = rtwtxq; 2137 2138 return container_of(p, struct ieee80211_txq, drv_priv); 2139 } 2140 2141 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2142 { 2143 void *p = rtwvif; 2144 2145 return container_of(p, struct ieee80211_vif, drv_priv); 2146 } 2147 2148 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2149 { 2150 if (rtwdev->chip->ops->efuse_grant) 2151 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2152 } 2153 2154 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2155 { 2156 if (rtwdev->chip->ops->efuse_grant) 2157 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2158 } 2159 2160 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2161 { 2162 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2163 } 2164 2165 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2166 { 2167 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2168 } 2169 2170 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2171 { 2172 return rtwdev->chip->rx_ldpc; 2173 } 2174 2175 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2176 { 2177 return rtwdev->chip->tx_stbc; 2178 } 2179 2180 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 2181 { 2182 unsigned long mac_id; 2183 2184 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 2185 if (mac_id < RTW_MAX_MAC_ID_NUM) 2186 set_bit(mac_id, rtwdev->mac_id_map); 2187 2188 return mac_id; 2189 } 2190 2191 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2192 { 2193 clear_bit(mac_id, rtwdev->mac_id_map); 2194 } 2195 2196 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2197 { 2198 if (rtwdev->chip->ops->dump_fw_crash) 2199 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2200 2201 return 0; 2202 } 2203 2204 static inline 2205 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band) 2206 { 2207 switch (hw_band) { 2208 default: 2209 case RTW_BAND_2G: 2210 return NL80211_BAND_2GHZ; 2211 case RTW_BAND_5G: 2212 return NL80211_BAND_5GHZ; 2213 case RTW_BAND_60G: 2214 return NL80211_BAND_60GHZ; 2215 } 2216 } 2217 2218 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2219 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period); 2220 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2221 struct rtw_channel_params *ch_param); 2222 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2223 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2224 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2225 void rtw_restore_reg(struct rtw_dev *rtwdev, 2226 struct rtw_backup_info *bckp, u32 num); 2227 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2228 void rtw_set_channel(struct rtw_dev *rtwdev); 2229 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2230 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2231 u32 config); 2232 void rtw_tx_report_purge_timer(struct timer_list *t); 2233 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 2234 bool reset_ra_mask); 2235 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2236 const u8 *mac_addr, bool hw_scan); 2237 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2238 bool hw_scan); 2239 int rtw_core_start(struct rtw_dev *rtwdev); 2240 void rtw_power_off(struct rtw_dev *rtwdev); 2241 void rtw_core_stop(struct rtw_dev *rtwdev); 2242 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2243 int rtw_core_init(struct rtw_dev *rtwdev); 2244 void rtw_core_deinit(struct rtw_dev *rtwdev); 2245 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2246 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2247 u16 rtw_desc_to_bitrate(u8 desc_rate); 2248 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2249 struct ieee80211_bss_conf *conf); 2250 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2251 struct ieee80211_vif *vif); 2252 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2253 bool fw_exist); 2254 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2255 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev); 2256 int rtw_power_on(struct rtw_dev *rtwdev); 2257 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2258 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2259 u32 fwcd_item); 2260 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2261 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2262 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 2263 u8 primary_channel, enum rtw_supported_band band, 2264 enum rtw_bandwidth bandwidth); 2265 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 2266 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev); 2267 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable); 2268 #endif 2269