1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 #include "sdio.h" 22 23 bool rtw_disable_lps_deep_mode; 24 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 25 bool rtw_bf_support = true; 26 unsigned int rtw_debug_mask; 27 EXPORT_SYMBOL(rtw_debug_mask); 28 /* EDCCA is enabled during normal behavior. For debugging purpose in 29 * a noisy environment, it can be disabled via edcca debugfs. Because 30 * all rtw88 devices will probably be affected if environment is noisy, 31 * rtw_edcca_enabled is just declared by driver instead of by device. 32 * So, turning it off will take effect for all rtw88 devices before 33 * there is a tough reason to maintain rtw_edcca_enabled by device. 34 */ 35 bool rtw_edcca_enabled = true; 36 37 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 38 module_param_named(support_bf, rtw_bf_support, bool, 0644); 39 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 40 41 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 42 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 43 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 44 45 static struct ieee80211_channel rtw_channeltable_2g[] = { 46 {.center_freq = 2412, .hw_value = 1,}, 47 {.center_freq = 2417, .hw_value = 2,}, 48 {.center_freq = 2422, .hw_value = 3,}, 49 {.center_freq = 2427, .hw_value = 4,}, 50 {.center_freq = 2432, .hw_value = 5,}, 51 {.center_freq = 2437, .hw_value = 6,}, 52 {.center_freq = 2442, .hw_value = 7,}, 53 {.center_freq = 2447, .hw_value = 8,}, 54 {.center_freq = 2452, .hw_value = 9,}, 55 {.center_freq = 2457, .hw_value = 10,}, 56 {.center_freq = 2462, .hw_value = 11,}, 57 {.center_freq = 2467, .hw_value = 12,}, 58 {.center_freq = 2472, .hw_value = 13,}, 59 {.center_freq = 2484, .hw_value = 14,}, 60 }; 61 62 static struct ieee80211_channel rtw_channeltable_5g[] = { 63 {.center_freq = 5180, .hw_value = 36,}, 64 {.center_freq = 5200, .hw_value = 40,}, 65 {.center_freq = 5220, .hw_value = 44,}, 66 {.center_freq = 5240, .hw_value = 48,}, 67 {.center_freq = 5260, .hw_value = 52,}, 68 {.center_freq = 5280, .hw_value = 56,}, 69 {.center_freq = 5300, .hw_value = 60,}, 70 {.center_freq = 5320, .hw_value = 64,}, 71 {.center_freq = 5500, .hw_value = 100,}, 72 {.center_freq = 5520, .hw_value = 104,}, 73 {.center_freq = 5540, .hw_value = 108,}, 74 {.center_freq = 5560, .hw_value = 112,}, 75 {.center_freq = 5580, .hw_value = 116,}, 76 {.center_freq = 5600, .hw_value = 120,}, 77 {.center_freq = 5620, .hw_value = 124,}, 78 {.center_freq = 5640, .hw_value = 128,}, 79 {.center_freq = 5660, .hw_value = 132,}, 80 {.center_freq = 5680, .hw_value = 136,}, 81 {.center_freq = 5700, .hw_value = 140,}, 82 {.center_freq = 5720, .hw_value = 144,}, 83 {.center_freq = 5745, .hw_value = 149,}, 84 {.center_freq = 5765, .hw_value = 153,}, 85 {.center_freq = 5785, .hw_value = 157,}, 86 {.center_freq = 5805, .hw_value = 161,}, 87 {.center_freq = 5825, .hw_value = 165, 88 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 89 }; 90 91 static struct ieee80211_rate rtw_ratetable[] = { 92 {.bitrate = 10, .hw_value = 0x00,}, 93 {.bitrate = 20, .hw_value = 0x01,}, 94 {.bitrate = 55, .hw_value = 0x02,}, 95 {.bitrate = 110, .hw_value = 0x03,}, 96 {.bitrate = 60, .hw_value = 0x04,}, 97 {.bitrate = 90, .hw_value = 0x05,}, 98 {.bitrate = 120, .hw_value = 0x06,}, 99 {.bitrate = 180, .hw_value = 0x07,}, 100 {.bitrate = 240, .hw_value = 0x08,}, 101 {.bitrate = 360, .hw_value = 0x09,}, 102 {.bitrate = 480, .hw_value = 0x0a,}, 103 {.bitrate = 540, .hw_value = 0x0b,}, 104 }; 105 106 static const struct ieee80211_iface_limit rtw_iface_limits[] = { 107 { 108 .max = 1, 109 .types = BIT(NL80211_IFTYPE_STATION), 110 }, 111 { 112 .max = 1, 113 .types = BIT(NL80211_IFTYPE_AP), 114 } 115 }; 116 117 static const struct ieee80211_iface_combination rtw_iface_combs[] = { 118 { 119 .limits = rtw_iface_limits, 120 .n_limits = ARRAY_SIZE(rtw_iface_limits), 121 .max_interfaces = 2, 122 .num_different_channels = 1, 123 } 124 }; 125 126 u16 rtw_desc_to_bitrate(u8 desc_rate) 127 { 128 struct ieee80211_rate rate; 129 130 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 131 return 0; 132 133 rate = rtw_ratetable[desc_rate]; 134 135 return rate.bitrate; 136 } 137 138 static struct ieee80211_supported_band rtw_band_2ghz = { 139 .band = NL80211_BAND_2GHZ, 140 141 .channels = rtw_channeltable_2g, 142 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 143 144 .bitrates = rtw_ratetable, 145 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 146 147 .ht_cap = {0}, 148 .vht_cap = {0}, 149 }; 150 151 static struct ieee80211_supported_band rtw_band_5ghz = { 152 .band = NL80211_BAND_5GHZ, 153 154 .channels = rtw_channeltable_5g, 155 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 156 157 /* 5G has no CCK rates */ 158 .bitrates = rtw_ratetable + 4, 159 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 160 161 .ht_cap = {0}, 162 .vht_cap = {0}, 163 }; 164 165 struct rtw_watch_dog_iter_data { 166 struct rtw_dev *rtwdev; 167 struct rtw_vif *rtwvif; 168 }; 169 170 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 171 { 172 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 173 u8 fix_rate_enable = 0; 174 u8 new_csi_rate_idx; 175 176 if (rtwvif->bfee.role != RTW_BFEE_SU && 177 rtwvif->bfee.role != RTW_BFEE_MU) 178 return; 179 180 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 181 bf_info->cur_csi_rpt_rate, 182 fix_rate_enable, &new_csi_rate_idx); 183 184 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 185 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 186 } 187 188 static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif) 189 { 190 struct rtw_watch_dog_iter_data *iter_data = data; 191 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 192 193 if (vif->type == NL80211_IFTYPE_STATION) 194 if (vif->cfg.assoc) 195 iter_data->rtwvif = rtwvif; 196 197 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 198 199 rtwvif->stats.tx_unicast = 0; 200 rtwvif->stats.rx_unicast = 0; 201 rtwvif->stats.tx_cnt = 0; 202 rtwvif->stats.rx_cnt = 0; 203 } 204 205 /* process TX/RX statistics periodically for hardware, 206 * the information helps hardware to enhance performance 207 */ 208 static void rtw_watch_dog_work(struct work_struct *work) 209 { 210 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 211 watch_dog_work.work); 212 struct rtw_traffic_stats *stats = &rtwdev->stats; 213 struct rtw_watch_dog_iter_data data = {}; 214 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 215 u32 tx_unicast_mbps, rx_unicast_mbps; 216 bool ps_active; 217 218 mutex_lock(&rtwdev->mutex); 219 220 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 221 goto unlock; 222 223 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 224 RTW_WATCH_DOG_DELAY_TIME); 225 226 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 227 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 228 else 229 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 230 231 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 232 rtw_coex_wl_status_change_notify(rtwdev, 0); 233 234 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 235 stats->rx_cnt > RTW_LPS_THRESHOLD) 236 ps_active = true; 237 else 238 ps_active = false; 239 240 tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT; 241 rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT; 242 243 ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps); 244 ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps); 245 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 246 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 247 248 /* reset tx/rx statictics */ 249 stats->tx_unicast = 0; 250 stats->rx_unicast = 0; 251 stats->tx_cnt = 0; 252 stats->rx_cnt = 0; 253 254 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 255 goto unlock; 256 257 /* make sure BB/RF is working for dynamic mech */ 258 rtw_leave_lps(rtwdev); 259 rtw_coex_wl_status_check(rtwdev); 260 rtw_coex_query_bt_hid_list(rtwdev); 261 262 rtw_phy_dynamic_mechanism(rtwdev); 263 264 rtw_hci_dynamic_rx_agg(rtwdev, 265 tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1); 266 267 data.rtwdev = rtwdev; 268 /* rtw_iterate_vifs internally uses an atomic iterator which is needed 269 * to avoid taking local->iflist_mtx mutex 270 */ 271 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data); 272 273 /* fw supports only one station associated to enter lps, if there are 274 * more than two stations associated to the AP, then we can not enter 275 * lps, because fw does not handle the overlapped beacon interval 276 * 277 * rtw_recalc_lps() iterate vifs and determine if driver can enter 278 * ps by vif->type and vif->cfg.ps, all we need to do here is to 279 * get that vif and check if device is having traffic more than the 280 * threshold. 281 */ 282 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 283 !rtwdev->beacon_loss && !rtwdev->ap_active) 284 rtw_enter_lps(rtwdev, data.rtwvif->port); 285 286 rtwdev->watch_dog_cnt++; 287 288 unlock: 289 mutex_unlock(&rtwdev->mutex); 290 } 291 292 static void rtw_c2h_work(struct work_struct *work) 293 { 294 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 295 struct sk_buff *skb, *tmp; 296 297 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 298 skb_unlink(skb, &rtwdev->c2h_queue); 299 rtw_fw_c2h_cmd_handle(rtwdev, skb); 300 dev_kfree_skb_any(skb); 301 } 302 } 303 304 static void rtw_ips_work(struct work_struct *work) 305 { 306 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 307 308 mutex_lock(&rtwdev->mutex); 309 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 310 rtw_enter_ips(rtwdev); 311 mutex_unlock(&rtwdev->mutex); 312 } 313 314 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 315 { 316 unsigned long mac_id; 317 318 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 319 if (mac_id < RTW_MAX_MAC_ID_NUM) 320 set_bit(mac_id, rtwdev->mac_id_map); 321 322 return mac_id; 323 } 324 325 static void rtw_sta_rc_work(struct work_struct *work) 326 { 327 struct rtw_sta_info *si = container_of(work, struct rtw_sta_info, 328 rc_work); 329 struct rtw_dev *rtwdev = si->rtwdev; 330 331 mutex_lock(&rtwdev->mutex); 332 rtw_update_sta_info(rtwdev, si, true); 333 mutex_unlock(&rtwdev->mutex); 334 } 335 336 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 337 struct ieee80211_vif *vif) 338 { 339 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 340 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 341 int i; 342 343 si->mac_id = rtw_acquire_macid(rtwdev); 344 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 345 return -ENOSPC; 346 347 if (vif->type == NL80211_IFTYPE_STATION && vif->cfg.assoc == 0) 348 rtwvif->mac_id = si->mac_id; 349 si->rtwdev = rtwdev; 350 si->sta = sta; 351 si->vif = vif; 352 si->init_ra_lv = 1; 353 ewma_rssi_init(&si->avg_rssi); 354 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 355 rtw_txq_init(rtwdev, sta->txq[i]); 356 INIT_WORK(&si->rc_work, rtw_sta_rc_work); 357 358 rtw_update_sta_info(rtwdev, si, true); 359 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 360 361 rtwdev->sta_cnt++; 362 rtwdev->beacon_loss = false; 363 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 364 sta->addr, si->mac_id); 365 366 return 0; 367 } 368 369 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 370 bool fw_exist) 371 { 372 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 373 int i; 374 375 cancel_work_sync(&si->rc_work); 376 377 rtw_release_macid(rtwdev, si->mac_id); 378 if (fw_exist) 379 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 380 381 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 382 rtw_txq_cleanup(rtwdev, sta->txq[i]); 383 384 kfree(si->mask); 385 386 rtwdev->sta_cnt--; 387 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 388 sta->addr, si->mac_id); 389 } 390 391 struct rtw_fwcd_hdr { 392 u32 item; 393 u32 size; 394 u32 padding1; 395 u32 padding2; 396 } __packed; 397 398 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 399 { 400 const struct rtw_chip_info *chip = rtwdev->chip; 401 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 402 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 403 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 404 u8 i; 405 406 if (segs) { 407 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 408 409 for (i = 0; i < segs->num; i++) 410 prep_size += segs->segs[i]; 411 } 412 413 desc->data = vmalloc(prep_size); 414 if (!desc->data) 415 return -ENOMEM; 416 417 desc->size = prep_size; 418 desc->next = desc->data; 419 420 return 0; 421 } 422 423 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 424 { 425 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 426 struct rtw_fwcd_hdr *hdr; 427 u8 *next; 428 429 if (!desc->data) { 430 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 431 return NULL; 432 } 433 434 next = desc->next + sizeof(struct rtw_fwcd_hdr); 435 if (next - desc->data + size > desc->size) { 436 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 437 return NULL; 438 } 439 440 hdr = (struct rtw_fwcd_hdr *)(desc->next); 441 hdr->item = item; 442 hdr->size = size; 443 hdr->padding1 = 0x01234567; 444 hdr->padding2 = 0x89abcdef; 445 desc->next = next + size; 446 447 return next; 448 } 449 450 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 451 { 452 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 453 454 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 455 456 /* Data will be freed after lifetime of device coredump. After calling 457 * dev_coredump, data is supposed to be handled by the device coredump 458 * framework. Note that a new dump will be discarded if a previous one 459 * hasn't been released yet. 460 */ 461 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 462 } 463 464 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 465 { 466 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 467 468 if (free_self) { 469 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 470 vfree(desc->data); 471 } 472 473 desc->data = NULL; 474 desc->next = NULL; 475 } 476 477 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 478 { 479 u32 size = rtwdev->chip->fw_rxff_size; 480 u32 *buf; 481 u8 seq; 482 483 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 484 if (!buf) 485 return -ENOMEM; 486 487 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 488 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 489 return -EINVAL; 490 } 491 492 if (GET_FW_DUMP_LEN(buf) == 0) { 493 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 494 return -EINVAL; 495 } 496 497 seq = GET_FW_DUMP_SEQ(buf); 498 if (seq > 0) { 499 rtw_dbg(rtwdev, RTW_DBG_FW, 500 "fw crash dump's seq is wrong: %d\n", seq); 501 return -EINVAL; 502 } 503 504 return 0; 505 } 506 507 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 508 u32 fwcd_item) 509 { 510 u32 rxff = rtwdev->chip->fw_rxff_size; 511 u32 dump_size, done_size = 0; 512 u8 *buf; 513 int ret; 514 515 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 516 if (!buf) 517 return -ENOMEM; 518 519 while (size) { 520 dump_size = size > rxff ? rxff : size; 521 522 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 523 dump_size); 524 if (ret) { 525 rtw_err(rtwdev, 526 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 527 ocp_src, done_size); 528 return ret; 529 } 530 531 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 532 dump_size, (u32 *)(buf + done_size)); 533 if (ret) { 534 rtw_err(rtwdev, 535 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 536 ocp_src, done_size); 537 return ret; 538 } 539 540 size -= dump_size; 541 done_size += dump_size; 542 } 543 544 return 0; 545 } 546 EXPORT_SYMBOL(rtw_dump_fw); 547 548 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 549 { 550 u8 *buf; 551 u32 i; 552 553 if (addr & 0x3) { 554 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 555 return -EINVAL; 556 } 557 558 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 559 if (!buf) 560 return -ENOMEM; 561 562 for (i = 0; i < size; i += 4) 563 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 564 565 return 0; 566 } 567 EXPORT_SYMBOL(rtw_dump_reg); 568 569 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 570 struct ieee80211_bss_conf *conf) 571 { 572 struct ieee80211_vif *vif = NULL; 573 574 if (conf) 575 vif = container_of(conf, struct ieee80211_vif, bss_conf); 576 577 if (conf && vif->cfg.assoc) { 578 rtwvif->aid = vif->cfg.aid; 579 rtwvif->net_type = RTW_NET_MGD_LINKED; 580 } else { 581 rtwvif->aid = 0; 582 rtwvif->net_type = RTW_NET_NO_LINK; 583 } 584 } 585 586 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 587 struct ieee80211_vif *vif, 588 struct ieee80211_sta *sta, 589 struct ieee80211_key_conf *key, 590 void *data) 591 { 592 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 593 struct rtw_sec_desc *sec = &rtwdev->sec; 594 595 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 596 } 597 598 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 599 { 600 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 601 602 if (rtwdev->sta_cnt == 0) { 603 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 604 return; 605 } 606 rtw_sta_remove(rtwdev, sta, false); 607 } 608 609 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 610 { 611 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 612 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 613 614 rtw_bf_disassoc(rtwdev, vif, NULL); 615 rtw_vif_assoc_changed(rtwvif, NULL); 616 rtw_txq_cleanup(rtwdev, vif->txq); 617 } 618 619 void rtw_fw_recovery(struct rtw_dev *rtwdev) 620 { 621 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 622 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 623 } 624 625 static void __fw_recovery_work(struct rtw_dev *rtwdev) 626 { 627 int ret = 0; 628 629 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 630 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 631 632 ret = rtw_fwcd_prep(rtwdev); 633 if (ret) 634 goto free; 635 ret = rtw_fw_dump_crash_log(rtwdev); 636 if (ret) 637 goto free; 638 ret = rtw_chip_dump_fw_crash(rtwdev); 639 if (ret) 640 goto free; 641 642 rtw_fwcd_dump(rtwdev); 643 free: 644 rtw_fwcd_free(rtwdev, !!ret); 645 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 646 647 WARN(1, "firmware crash, start reset and recover\n"); 648 649 rcu_read_lock(); 650 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 651 rcu_read_unlock(); 652 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 653 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 654 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM); 655 rtw_enter_ips(rtwdev); 656 } 657 658 static void rtw_fw_recovery_work(struct work_struct *work) 659 { 660 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 661 fw_recovery_work); 662 663 mutex_lock(&rtwdev->mutex); 664 __fw_recovery_work(rtwdev); 665 mutex_unlock(&rtwdev->mutex); 666 667 ieee80211_restart_hw(rtwdev->hw); 668 } 669 670 struct rtw_txq_ba_iter_data { 671 }; 672 673 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 674 { 675 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 676 int ret; 677 u8 tid; 678 679 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 680 while (tid != IEEE80211_NUM_TIDS) { 681 clear_bit(tid, si->tid_ba); 682 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 683 if (ret == -EINVAL) { 684 struct ieee80211_txq *txq; 685 struct rtw_txq *rtwtxq; 686 687 txq = sta->txq[tid]; 688 rtwtxq = (struct rtw_txq *)txq->drv_priv; 689 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 690 } 691 692 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 693 } 694 } 695 696 static void rtw_txq_ba_work(struct work_struct *work) 697 { 698 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 699 struct rtw_txq_ba_iter_data data; 700 701 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 702 } 703 704 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 705 { 706 if (IS_CH_2G_BAND(channel)) 707 pkt_stat->band = NL80211_BAND_2GHZ; 708 else if (IS_CH_5G_BAND(channel)) 709 pkt_stat->band = NL80211_BAND_5GHZ; 710 else 711 return; 712 713 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 714 } 715 EXPORT_SYMBOL(rtw_set_rx_freq_band); 716 717 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 718 { 719 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 720 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 721 } 722 723 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 724 u8 primary_channel, enum rtw_supported_band band, 725 enum rtw_bandwidth bandwidth) 726 { 727 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band); 728 struct rtw_hal *hal = &rtwdev->hal; 729 u8 *cch_by_bw = hal->cch_by_bw; 730 u32 center_freq, primary_freq; 731 enum rtw_sar_bands sar_band; 732 u8 primary_channel_idx; 733 734 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band); 735 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band); 736 737 /* assign the center channel used while 20M bw is selected */ 738 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel; 739 740 /* assign the center channel used while current bw is selected */ 741 cch_by_bw[bandwidth] = center_channel; 742 743 switch (bandwidth) { 744 case RTW_CHANNEL_WIDTH_20: 745 default: 746 primary_channel_idx = RTW_SC_DONT_CARE; 747 break; 748 case RTW_CHANNEL_WIDTH_40: 749 if (primary_freq > center_freq) 750 primary_channel_idx = RTW_SC_20_UPPER; 751 else 752 primary_channel_idx = RTW_SC_20_LOWER; 753 break; 754 case RTW_CHANNEL_WIDTH_80: 755 if (primary_freq > center_freq) { 756 if (primary_freq - center_freq == 10) 757 primary_channel_idx = RTW_SC_20_UPPER; 758 else 759 primary_channel_idx = RTW_SC_20_UPMOST; 760 761 /* assign the center channel used 762 * while 40M bw is selected 763 */ 764 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4; 765 } else { 766 if (center_freq - primary_freq == 10) 767 primary_channel_idx = RTW_SC_20_LOWER; 768 else 769 primary_channel_idx = RTW_SC_20_LOWEST; 770 771 /* assign the center channel used 772 * while 40M bw is selected 773 */ 774 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4; 775 } 776 break; 777 } 778 779 switch (center_channel) { 780 case 1 ... 14: 781 sar_band = RTW_SAR_BAND_0; 782 break; 783 case 36 ... 64: 784 sar_band = RTW_SAR_BAND_1; 785 break; 786 case 100 ... 144: 787 sar_band = RTW_SAR_BAND_3; 788 break; 789 case 149 ... 177: 790 sar_band = RTW_SAR_BAND_4; 791 break; 792 default: 793 WARN(1, "unknown ch(%u) to SAR band\n", center_channel); 794 sar_band = RTW_SAR_BAND_0; 795 break; 796 } 797 798 hal->current_primary_channel_index = primary_channel_idx; 799 hal->current_band_width = bandwidth; 800 hal->primary_channel = primary_channel; 801 hal->current_channel = center_channel; 802 hal->current_band_type = band; 803 hal->sar_band = sar_band; 804 } 805 806 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 807 struct rtw_channel_params *chan_params) 808 { 809 struct ieee80211_channel *channel = chandef->chan; 810 enum nl80211_chan_width width = chandef->width; 811 u32 primary_freq, center_freq; 812 u8 center_chan; 813 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 814 815 center_chan = channel->hw_value; 816 primary_freq = channel->center_freq; 817 center_freq = chandef->center_freq1; 818 819 switch (width) { 820 case NL80211_CHAN_WIDTH_20_NOHT: 821 case NL80211_CHAN_WIDTH_20: 822 bandwidth = RTW_CHANNEL_WIDTH_20; 823 break; 824 case NL80211_CHAN_WIDTH_40: 825 bandwidth = RTW_CHANNEL_WIDTH_40; 826 if (primary_freq > center_freq) 827 center_chan -= 2; 828 else 829 center_chan += 2; 830 break; 831 case NL80211_CHAN_WIDTH_80: 832 bandwidth = RTW_CHANNEL_WIDTH_80; 833 if (primary_freq > center_freq) { 834 if (primary_freq - center_freq == 10) 835 center_chan -= 2; 836 else 837 center_chan -= 6; 838 } else { 839 if (center_freq - primary_freq == 10) 840 center_chan += 2; 841 else 842 center_chan += 6; 843 } 844 break; 845 default: 846 center_chan = 0; 847 break; 848 } 849 850 chan_params->center_chan = center_chan; 851 chan_params->bandwidth = bandwidth; 852 chan_params->primary_chan = channel->hw_value; 853 } 854 855 void rtw_set_channel(struct rtw_dev *rtwdev) 856 { 857 const struct rtw_chip_info *chip = rtwdev->chip; 858 struct ieee80211_hw *hw = rtwdev->hw; 859 struct rtw_hal *hal = &rtwdev->hal; 860 struct rtw_channel_params ch_param; 861 u8 center_chan, primary_chan, bandwidth, band; 862 863 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 864 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 865 return; 866 867 center_chan = ch_param.center_chan; 868 primary_chan = ch_param.primary_chan; 869 bandwidth = ch_param.bandwidth; 870 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 871 872 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth); 873 874 if (rtwdev->scan_info.op_chan) 875 rtw_store_op_chan(rtwdev, true); 876 877 chip->ops->set_channel(rtwdev, center_chan, bandwidth, 878 hal->current_primary_channel_index); 879 880 if (hal->current_band_type == RTW_BAND_5G) { 881 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 882 } else { 883 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 884 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 885 else 886 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 887 } 888 889 rtw_phy_set_tx_power_level(rtwdev, center_chan); 890 891 /* if the channel isn't set for scanning, we will do RF calibration 892 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 893 * during scanning on each channel takes too long. 894 */ 895 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 896 rtwdev->need_rfk = true; 897 } 898 899 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 900 { 901 const struct rtw_chip_info *chip = rtwdev->chip; 902 903 if (rtwdev->need_rfk) { 904 rtwdev->need_rfk = false; 905 chip->ops->phy_calibration(rtwdev); 906 } 907 } 908 909 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 910 { 911 int i; 912 913 for (i = 0; i < ETH_ALEN; i++) 914 rtw_write8(rtwdev, start + i, addr[i]); 915 } 916 917 void rtw_vif_port_config(struct rtw_dev *rtwdev, 918 struct rtw_vif *rtwvif, 919 u32 config) 920 { 921 u32 addr, mask; 922 923 if (config & PORT_SET_MAC_ADDR) { 924 addr = rtwvif->conf->mac_addr.addr; 925 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 926 } 927 if (config & PORT_SET_BSSID) { 928 addr = rtwvif->conf->bssid.addr; 929 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 930 } 931 if (config & PORT_SET_NET_TYPE) { 932 addr = rtwvif->conf->net_type.addr; 933 mask = rtwvif->conf->net_type.mask; 934 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 935 } 936 if (config & PORT_SET_AID) { 937 addr = rtwvif->conf->aid.addr; 938 mask = rtwvif->conf->aid.mask; 939 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 940 } 941 if (config & PORT_SET_BCN_CTRL) { 942 addr = rtwvif->conf->bcn_ctrl.addr; 943 mask = rtwvif->conf->bcn_ctrl.mask; 944 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 945 } 946 } 947 948 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 949 { 950 u8 bw = 0; 951 952 switch (bw_cap) { 953 case EFUSE_HW_CAP_IGNORE: 954 case EFUSE_HW_CAP_SUPP_BW80: 955 bw |= BIT(RTW_CHANNEL_WIDTH_80); 956 fallthrough; 957 case EFUSE_HW_CAP_SUPP_BW40: 958 bw |= BIT(RTW_CHANNEL_WIDTH_40); 959 fallthrough; 960 default: 961 bw |= BIT(RTW_CHANNEL_WIDTH_20); 962 break; 963 } 964 965 return bw; 966 } 967 968 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 969 { 970 const struct rtw_chip_info *chip = rtwdev->chip; 971 struct rtw_hal *hal = &rtwdev->hal; 972 973 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 974 hw_ant_num >= hal->rf_path_num) 975 return; 976 977 switch (hw_ant_num) { 978 case 1: 979 hal->rf_type = RF_1T1R; 980 hal->rf_path_num = 1; 981 if (!chip->fix_rf_phy_num) 982 hal->rf_phy_num = hal->rf_path_num; 983 hal->antenna_tx = BB_PATH_A; 984 hal->antenna_rx = BB_PATH_A; 985 break; 986 default: 987 WARN(1, "invalid hw configuration from efuse\n"); 988 break; 989 } 990 } 991 992 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 993 { 994 u64 ra_mask = 0; 995 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 996 u8 vht_mcs_cap; 997 int i, nss; 998 999 /* 4SS, every two bits for MCS7/8/9 */ 1000 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 1001 vht_mcs_cap = mcs_map & 0x3; 1002 switch (vht_mcs_cap) { 1003 case 2: /* MCS9 */ 1004 ra_mask |= 0x3ffULL << nss; 1005 break; 1006 case 1: /* MCS8 */ 1007 ra_mask |= 0x1ffULL << nss; 1008 break; 1009 case 0: /* MCS7 */ 1010 ra_mask |= 0x0ffULL << nss; 1011 break; 1012 default: 1013 break; 1014 } 1015 } 1016 1017 return ra_mask; 1018 } 1019 1020 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 1021 { 1022 u8 rate_id = 0; 1023 1024 switch (wireless_set) { 1025 case WIRELESS_CCK: 1026 rate_id = RTW_RATEID_B_20M; 1027 break; 1028 case WIRELESS_OFDM: 1029 rate_id = RTW_RATEID_G; 1030 break; 1031 case WIRELESS_CCK | WIRELESS_OFDM: 1032 rate_id = RTW_RATEID_BG; 1033 break; 1034 case WIRELESS_OFDM | WIRELESS_HT: 1035 if (tx_num == 1) 1036 rate_id = RTW_RATEID_GN_N1SS; 1037 else if (tx_num == 2) 1038 rate_id = RTW_RATEID_GN_N2SS; 1039 else if (tx_num == 3) 1040 rate_id = RTW_RATEID_ARFR5_N_3SS; 1041 break; 1042 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 1043 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 1044 if (tx_num == 1) 1045 rate_id = RTW_RATEID_BGN_40M_1SS; 1046 else if (tx_num == 2) 1047 rate_id = RTW_RATEID_BGN_40M_2SS; 1048 else if (tx_num == 3) 1049 rate_id = RTW_RATEID_ARFR5_N_3SS; 1050 else if (tx_num == 4) 1051 rate_id = RTW_RATEID_ARFR7_N_4SS; 1052 } else { 1053 if (tx_num == 1) 1054 rate_id = RTW_RATEID_BGN_20M_1SS; 1055 else if (tx_num == 2) 1056 rate_id = RTW_RATEID_BGN_20M_2SS; 1057 else if (tx_num == 3) 1058 rate_id = RTW_RATEID_ARFR5_N_3SS; 1059 else if (tx_num == 4) 1060 rate_id = RTW_RATEID_ARFR7_N_4SS; 1061 } 1062 break; 1063 case WIRELESS_OFDM | WIRELESS_VHT: 1064 if (tx_num == 1) 1065 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1066 else if (tx_num == 2) 1067 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1068 else if (tx_num == 3) 1069 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1070 else if (tx_num == 4) 1071 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1072 break; 1073 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 1074 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 1075 if (tx_num == 1) 1076 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1077 else if (tx_num == 2) 1078 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1079 else if (tx_num == 3) 1080 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1081 else if (tx_num == 4) 1082 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1083 } else { 1084 if (tx_num == 1) 1085 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1086 else if (tx_num == 2) 1087 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1088 else if (tx_num == 3) 1089 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1090 else if (tx_num == 4) 1091 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1092 } 1093 break; 1094 default: 1095 break; 1096 } 1097 1098 return rate_id; 1099 } 1100 1101 #define RA_MASK_CCK_RATES 0x0000f 1102 #define RA_MASK_OFDM_RATES 0x00ff0 1103 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1104 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1105 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1106 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1107 RA_MASK_HT_RATES_2SS | \ 1108 RA_MASK_HT_RATES_3SS) 1109 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1110 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1111 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1112 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1113 RA_MASK_VHT_RATES_2SS | \ 1114 RA_MASK_VHT_RATES_3SS) 1115 #define RA_MASK_CCK_IN_BG 0x00005 1116 #define RA_MASK_CCK_IN_HT 0x00005 1117 #define RA_MASK_CCK_IN_VHT 0x00005 1118 #define RA_MASK_OFDM_IN_VHT 0x00010 1119 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1120 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1121 1122 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1123 { 1124 u8 rssi_level = si->rssi_level; 1125 1126 if (wireless_set == WIRELESS_CCK) 1127 return 0xffffffffffffffffULL; 1128 1129 if (rssi_level == 0) 1130 return 0xffffffffffffffffULL; 1131 else if (rssi_level == 1) 1132 return 0xfffffffffffffff0ULL; 1133 else if (rssi_level == 2) 1134 return 0xffffffffffffefe0ULL; 1135 else if (rssi_level == 3) 1136 return 0xffffffffffffcfc0ULL; 1137 else if (rssi_level == 4) 1138 return 0xffffffffffff8f80ULL; 1139 else 1140 return 0xffffffffffff0f00ULL; 1141 } 1142 1143 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1144 { 1145 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1146 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1147 1148 if (ra_mask == 0) 1149 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1150 1151 return ra_mask; 1152 } 1153 1154 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1155 u64 ra_mask, bool is_vht_enable) 1156 { 1157 struct rtw_hal *hal = &rtwdev->hal; 1158 const struct cfg80211_bitrate_mask *mask = si->mask; 1159 u64 cfg_mask = GENMASK_ULL(63, 0); 1160 u8 band; 1161 1162 if (!si->use_cfg_mask) 1163 return ra_mask; 1164 1165 band = hal->current_band_type; 1166 if (band == RTW_BAND_2G) { 1167 band = NL80211_BAND_2GHZ; 1168 cfg_mask = mask->control[band].legacy; 1169 } else if (band == RTW_BAND_5G) { 1170 band = NL80211_BAND_5GHZ; 1171 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1172 RA_MASK_OFDM_RATES); 1173 } 1174 1175 if (!is_vht_enable) { 1176 if (ra_mask & RA_MASK_HT_RATES_1SS) 1177 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1178 RA_MASK_HT_RATES_1SS); 1179 if (ra_mask & RA_MASK_HT_RATES_2SS) 1180 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1181 RA_MASK_HT_RATES_2SS); 1182 } else { 1183 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1184 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1185 RA_MASK_VHT_RATES_1SS); 1186 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1187 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1188 RA_MASK_VHT_RATES_2SS); 1189 } 1190 1191 ra_mask &= cfg_mask; 1192 1193 return ra_mask; 1194 } 1195 1196 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1197 bool reset_ra_mask) 1198 { 1199 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1200 struct ieee80211_sta *sta = si->sta; 1201 struct rtw_efuse *efuse = &rtwdev->efuse; 1202 struct rtw_hal *hal = &rtwdev->hal; 1203 u8 wireless_set; 1204 u8 bw_mode; 1205 u8 rate_id; 1206 u8 rf_type = RF_1T1R; 1207 u8 stbc_en = 0; 1208 u8 ldpc_en = 0; 1209 u8 tx_num = 1; 1210 u64 ra_mask = 0; 1211 u64 ra_mask_bak = 0; 1212 bool is_vht_enable = false; 1213 bool is_support_sgi = false; 1214 1215 if (sta->deflink.vht_cap.vht_supported) { 1216 is_vht_enable = true; 1217 ra_mask |= get_vht_ra_mask(sta); 1218 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1219 stbc_en = VHT_STBC_EN; 1220 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1221 ldpc_en = VHT_LDPC_EN; 1222 } else if (sta->deflink.ht_cap.ht_supported) { 1223 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1224 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1225 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1226 stbc_en = HT_STBC_EN; 1227 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1228 ldpc_en = HT_LDPC_EN; 1229 } 1230 1231 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1232 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1233 1234 if (hal->current_band_type == RTW_BAND_5G) { 1235 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1236 ra_mask_bak = ra_mask; 1237 if (sta->deflink.vht_cap.vht_supported) { 1238 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1239 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1240 } else if (sta->deflink.ht_cap.ht_supported) { 1241 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1242 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1243 } else { 1244 wireless_set = WIRELESS_OFDM; 1245 } 1246 dm_info->rrsr_val_init = RRSR_INIT_5G; 1247 } else if (hal->current_band_type == RTW_BAND_2G) { 1248 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1249 ra_mask_bak = ra_mask; 1250 if (sta->deflink.vht_cap.vht_supported) { 1251 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1252 RA_MASK_OFDM_IN_VHT; 1253 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1254 WIRELESS_HT | WIRELESS_VHT; 1255 } else if (sta->deflink.ht_cap.ht_supported) { 1256 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1257 RA_MASK_OFDM_IN_HT_2G; 1258 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1259 WIRELESS_HT; 1260 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1261 wireless_set = WIRELESS_CCK; 1262 } else { 1263 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1264 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1265 } 1266 dm_info->rrsr_val_init = RRSR_INIT_2G; 1267 } else { 1268 rtw_err(rtwdev, "Unknown band type\n"); 1269 ra_mask_bak = ra_mask; 1270 wireless_set = 0; 1271 } 1272 1273 switch (sta->deflink.bandwidth) { 1274 case IEEE80211_STA_RX_BW_80: 1275 bw_mode = RTW_CHANNEL_WIDTH_80; 1276 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1277 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1278 break; 1279 case IEEE80211_STA_RX_BW_40: 1280 bw_mode = RTW_CHANNEL_WIDTH_40; 1281 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1282 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1283 break; 1284 default: 1285 bw_mode = RTW_CHANNEL_WIDTH_20; 1286 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1287 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1288 break; 1289 } 1290 1291 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { 1292 tx_num = 2; 1293 rf_type = RF_2T2R; 1294 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { 1295 tx_num = 2; 1296 rf_type = RF_2T2R; 1297 } 1298 1299 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1300 1301 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1302 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1303 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1304 1305 si->bw_mode = bw_mode; 1306 si->stbc_en = stbc_en; 1307 si->ldpc_en = ldpc_en; 1308 si->rf_type = rf_type; 1309 si->sgi_enable = is_support_sgi; 1310 si->vht_enable = is_vht_enable; 1311 si->ra_mask = ra_mask; 1312 si->rate_id = rate_id; 1313 1314 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1315 } 1316 1317 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1318 { 1319 const struct rtw_chip_info *chip = rtwdev->chip; 1320 struct rtw_fw_state *fw; 1321 int ret = 0; 1322 1323 fw = &rtwdev->fw; 1324 wait_for_completion(&fw->completion); 1325 if (!fw->firmware) 1326 ret = -EINVAL; 1327 1328 if (chip->wow_fw_name) { 1329 fw = &rtwdev->wow_fw; 1330 wait_for_completion(&fw->completion); 1331 if (!fw->firmware) 1332 ret = -EINVAL; 1333 } 1334 1335 return ret; 1336 } 1337 1338 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1339 struct rtw_fw_state *fw) 1340 { 1341 const struct rtw_chip_info *chip = rtwdev->chip; 1342 1343 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1344 !fw->feature) 1345 return LPS_DEEP_MODE_NONE; 1346 1347 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1348 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1349 return LPS_DEEP_MODE_PG; 1350 1351 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1352 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1353 return LPS_DEEP_MODE_LCLK; 1354 1355 return LPS_DEEP_MODE_NONE; 1356 } 1357 1358 static int rtw_power_on(struct rtw_dev *rtwdev) 1359 { 1360 const struct rtw_chip_info *chip = rtwdev->chip; 1361 struct rtw_fw_state *fw = &rtwdev->fw; 1362 bool wifi_only; 1363 int ret; 1364 1365 ret = rtw_hci_setup(rtwdev); 1366 if (ret) { 1367 rtw_err(rtwdev, "failed to setup hci\n"); 1368 goto err; 1369 } 1370 1371 /* power on MAC before firmware downloaded */ 1372 ret = rtw_mac_power_on(rtwdev); 1373 if (ret) { 1374 rtw_err(rtwdev, "failed to power on mac\n"); 1375 goto err; 1376 } 1377 1378 ret = rtw_wait_firmware_completion(rtwdev); 1379 if (ret) { 1380 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1381 goto err_off; 1382 } 1383 1384 ret = rtw_download_firmware(rtwdev, fw); 1385 if (ret) { 1386 rtw_err(rtwdev, "failed to download firmware\n"); 1387 goto err_off; 1388 } 1389 1390 /* config mac after firmware downloaded */ 1391 ret = rtw_mac_init(rtwdev); 1392 if (ret) { 1393 rtw_err(rtwdev, "failed to configure mac\n"); 1394 goto err_off; 1395 } 1396 1397 chip->ops->phy_set_param(rtwdev); 1398 1399 ret = rtw_hci_start(rtwdev); 1400 if (ret) { 1401 rtw_err(rtwdev, "failed to start hci\n"); 1402 goto err_off; 1403 } 1404 1405 /* send H2C after HCI has started */ 1406 rtw_fw_send_general_info(rtwdev); 1407 rtw_fw_send_phydm_info(rtwdev); 1408 1409 wifi_only = !rtwdev->efuse.btcoex; 1410 rtw_coex_power_on_setting(rtwdev); 1411 rtw_coex_init_hw_config(rtwdev, wifi_only); 1412 1413 return 0; 1414 1415 err_off: 1416 rtw_mac_power_off(rtwdev); 1417 1418 err: 1419 return ret; 1420 } 1421 1422 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1423 { 1424 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1425 return; 1426 1427 if (start) { 1428 rtw_fw_scan_notify(rtwdev, true); 1429 } else { 1430 reinit_completion(&rtwdev->fw_scan_density); 1431 rtw_fw_scan_notify(rtwdev, false); 1432 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1433 SCAN_NOTIFY_TIMEOUT)) 1434 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1435 } 1436 } 1437 1438 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1439 const u8 *mac_addr, bool hw_scan) 1440 { 1441 u32 config = 0; 1442 int ret = 0; 1443 1444 rtw_leave_lps(rtwdev); 1445 1446 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1447 ret = rtw_leave_ips(rtwdev); 1448 if (ret) { 1449 rtw_err(rtwdev, "failed to leave idle state\n"); 1450 return; 1451 } 1452 } 1453 1454 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1455 config |= PORT_SET_MAC_ADDR; 1456 rtw_vif_port_config(rtwdev, rtwvif, config); 1457 1458 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1459 rtw_core_fw_scan_notify(rtwdev, true); 1460 1461 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1462 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1463 } 1464 1465 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1466 bool hw_scan) 1467 { 1468 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1469 u32 config = 0; 1470 1471 if (!rtwvif) 1472 return; 1473 1474 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1475 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1476 1477 rtw_core_fw_scan_notify(rtwdev, false); 1478 1479 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1480 config |= PORT_SET_MAC_ADDR; 1481 rtw_vif_port_config(rtwdev, rtwvif, config); 1482 1483 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1484 1485 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1486 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1487 } 1488 1489 int rtw_core_start(struct rtw_dev *rtwdev) 1490 { 1491 int ret; 1492 1493 ret = rtw_power_on(rtwdev); 1494 if (ret) 1495 return ret; 1496 1497 rtw_sec_enable_sec_engine(rtwdev); 1498 1499 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1500 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1501 1502 /* rcr reset after powered on */ 1503 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1504 1505 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1506 RTW_WATCH_DOG_DELAY_TIME); 1507 1508 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1509 1510 return 0; 1511 } 1512 1513 static void rtw_power_off(struct rtw_dev *rtwdev) 1514 { 1515 rtw_hci_stop(rtwdev); 1516 rtw_coex_power_off_setting(rtwdev); 1517 rtw_mac_power_off(rtwdev); 1518 } 1519 1520 void rtw_core_stop(struct rtw_dev *rtwdev) 1521 { 1522 struct rtw_coex *coex = &rtwdev->coex; 1523 1524 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1525 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1526 1527 mutex_unlock(&rtwdev->mutex); 1528 1529 cancel_work_sync(&rtwdev->c2h_work); 1530 cancel_work_sync(&rtwdev->update_beacon_work); 1531 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1532 cancel_delayed_work_sync(&coex->bt_relink_work); 1533 cancel_delayed_work_sync(&coex->bt_reenable_work); 1534 cancel_delayed_work_sync(&coex->defreeze_work); 1535 cancel_delayed_work_sync(&coex->wl_remain_work); 1536 cancel_delayed_work_sync(&coex->bt_remain_work); 1537 cancel_delayed_work_sync(&coex->wl_connecting_work); 1538 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1539 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1540 1541 mutex_lock(&rtwdev->mutex); 1542 1543 rtw_power_off(rtwdev); 1544 } 1545 1546 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1547 struct ieee80211_sta_ht_cap *ht_cap) 1548 { 1549 const struct rtw_chip_info *chip = rtwdev->chip; 1550 struct rtw_efuse *efuse = &rtwdev->efuse; 1551 1552 ht_cap->ht_supported = true; 1553 ht_cap->cap = 0; 1554 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1555 IEEE80211_HT_CAP_MAX_AMSDU | 1556 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1557 1558 if (rtw_chip_has_rx_ldpc(rtwdev)) 1559 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1560 if (rtw_chip_has_tx_stbc(rtwdev)) 1561 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1562 1563 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1564 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1565 IEEE80211_HT_CAP_DSSSCCK40 | 1566 IEEE80211_HT_CAP_SGI_40; 1567 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1568 ht_cap->ampdu_density = chip->ampdu_density; 1569 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1570 if (efuse->hw_cap.nss > 1) { 1571 ht_cap->mcs.rx_mask[0] = 0xFF; 1572 ht_cap->mcs.rx_mask[1] = 0xFF; 1573 ht_cap->mcs.rx_mask[4] = 0x01; 1574 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1575 } else { 1576 ht_cap->mcs.rx_mask[0] = 0xFF; 1577 ht_cap->mcs.rx_mask[1] = 0x00; 1578 ht_cap->mcs.rx_mask[4] = 0x01; 1579 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1580 } 1581 } 1582 1583 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1584 struct ieee80211_sta_vht_cap *vht_cap) 1585 { 1586 struct rtw_efuse *efuse = &rtwdev->efuse; 1587 u16 mcs_map; 1588 __le16 highest; 1589 1590 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1591 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1592 return; 1593 1594 vht_cap->vht_supported = true; 1595 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1596 IEEE80211_VHT_CAP_SHORT_GI_80 | 1597 IEEE80211_VHT_CAP_RXSTBC_1 | 1598 IEEE80211_VHT_CAP_HTC_VHT | 1599 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1600 0; 1601 if (rtwdev->hal.rf_path_num > 1) 1602 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1603 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1604 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1605 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1606 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1607 1608 if (rtw_chip_has_rx_ldpc(rtwdev)) 1609 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1610 1611 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1612 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1613 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1614 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1615 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1616 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1617 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1618 if (efuse->hw_cap.nss > 1) { 1619 highest = cpu_to_le16(780); 1620 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1621 } else { 1622 highest = cpu_to_le16(390); 1623 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1624 } 1625 1626 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1627 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1628 vht_cap->vht_mcs.rx_highest = highest; 1629 vht_cap->vht_mcs.tx_highest = highest; 1630 } 1631 1632 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev) 1633 { 1634 u16 len; 1635 1636 len = rtwdev->chip->max_scan_ie_len; 1637 1638 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) && 1639 rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 1640 len = IEEE80211_MAX_DATA_LEN; 1641 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM)) 1642 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE; 1643 1644 return len; 1645 } 1646 1647 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1648 const struct rtw_chip_info *chip) 1649 { 1650 struct rtw_dev *rtwdev = hw->priv; 1651 struct ieee80211_supported_band *sband; 1652 1653 if (chip->band & RTW_BAND_2G) { 1654 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1655 if (!sband) 1656 goto err_out; 1657 if (chip->ht_supported) 1658 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1659 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1660 } 1661 1662 if (chip->band & RTW_BAND_5G) { 1663 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1664 if (!sband) 1665 goto err_out; 1666 if (chip->ht_supported) 1667 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1668 if (chip->vht_supported) 1669 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1670 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1671 } 1672 1673 return; 1674 1675 err_out: 1676 rtw_err(rtwdev, "failed to set supported band\n"); 1677 } 1678 1679 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1680 const struct rtw_chip_info *chip) 1681 { 1682 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1683 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1684 } 1685 1686 static void rtw_vif_smps_iter(void *data, u8 *mac, 1687 struct ieee80211_vif *vif) 1688 { 1689 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1690 1691 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 1692 return; 1693 1694 if (rtwdev->hal.txrx_1ss) 1695 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); 1696 else 1697 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); 1698 } 1699 1700 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1701 { 1702 const struct rtw_chip_info *chip = rtwdev->chip; 1703 struct rtw_hal *hal = &rtwdev->hal; 1704 1705 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1706 return; 1707 1708 rtwdev->hal.txrx_1ss = txrx_1ss; 1709 if (txrx_1ss) 1710 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1711 else 1712 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1713 hal->antenna_rx, false); 1714 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1715 } 1716 1717 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1718 struct rtw_fw_state *fw) 1719 { 1720 u32 feature; 1721 const struct rtw_fw_hdr *fw_hdr = 1722 (const struct rtw_fw_hdr *)fw->firmware->data; 1723 1724 feature = le32_to_cpu(fw_hdr->feature); 1725 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1726 1727 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C && 1728 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13)) 1729 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM; 1730 } 1731 1732 static void __update_firmware_info(struct rtw_dev *rtwdev, 1733 struct rtw_fw_state *fw) 1734 { 1735 const struct rtw_fw_hdr *fw_hdr = 1736 (const struct rtw_fw_hdr *)fw->firmware->data; 1737 1738 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1739 fw->version = le16_to_cpu(fw_hdr->version); 1740 fw->sub_version = fw_hdr->subversion; 1741 fw->sub_index = fw_hdr->subindex; 1742 1743 __update_firmware_feature(rtwdev, fw); 1744 } 1745 1746 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1747 struct rtw_fw_state *fw) 1748 { 1749 struct rtw_fw_hdr_legacy *legacy = 1750 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1751 1752 fw->h2c_version = 0; 1753 fw->version = le16_to_cpu(legacy->version); 1754 fw->sub_version = legacy->subversion1; 1755 fw->sub_index = legacy->subversion2; 1756 } 1757 1758 static void update_firmware_info(struct rtw_dev *rtwdev, 1759 struct rtw_fw_state *fw) 1760 { 1761 if (rtw_chip_wcpu_11n(rtwdev)) 1762 __update_firmware_info_legacy(rtwdev, fw); 1763 else 1764 __update_firmware_info(rtwdev, fw); 1765 } 1766 1767 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1768 { 1769 struct rtw_fw_state *fw = context; 1770 struct rtw_dev *rtwdev = fw->rtwdev; 1771 1772 if (!firmware || !firmware->data) { 1773 rtw_err(rtwdev, "failed to request firmware\n"); 1774 complete_all(&fw->completion); 1775 return; 1776 } 1777 1778 fw->firmware = firmware; 1779 update_firmware_info(rtwdev, fw); 1780 complete_all(&fw->completion); 1781 1782 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n", 1783 fw->type == RTW_WOWLAN_FW ? "WOW " : "", 1784 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1785 } 1786 1787 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1788 { 1789 const char *fw_name; 1790 struct rtw_fw_state *fw; 1791 int ret; 1792 1793 switch (type) { 1794 case RTW_WOWLAN_FW: 1795 fw = &rtwdev->wow_fw; 1796 fw_name = rtwdev->chip->wow_fw_name; 1797 break; 1798 1799 case RTW_NORMAL_FW: 1800 fw = &rtwdev->fw; 1801 fw_name = rtwdev->chip->fw_name; 1802 break; 1803 1804 default: 1805 rtw_warn(rtwdev, "unsupported firmware type\n"); 1806 return -ENOENT; 1807 } 1808 1809 fw->type = type; 1810 fw->rtwdev = rtwdev; 1811 init_completion(&fw->completion); 1812 1813 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1814 GFP_KERNEL, fw, rtw_load_firmware_cb); 1815 if (ret) { 1816 rtw_err(rtwdev, "failed to async firmware request\n"); 1817 return ret; 1818 } 1819 1820 return 0; 1821 } 1822 1823 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1824 { 1825 const struct rtw_chip_info *chip = rtwdev->chip; 1826 struct rtw_hal *hal = &rtwdev->hal; 1827 struct rtw_efuse *efuse = &rtwdev->efuse; 1828 1829 switch (rtw_hci_type(rtwdev)) { 1830 case RTW_HCI_TYPE_PCIE: 1831 rtwdev->hci.rpwm_addr = 0x03d9; 1832 rtwdev->hci.cpwm_addr = 0x03da; 1833 break; 1834 case RTW_HCI_TYPE_SDIO: 1835 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1; 1836 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2; 1837 break; 1838 case RTW_HCI_TYPE_USB: 1839 rtwdev->hci.rpwm_addr = 0xfe58; 1840 rtwdev->hci.cpwm_addr = 0xfe57; 1841 break; 1842 default: 1843 rtw_err(rtwdev, "unsupported hci type\n"); 1844 return -EINVAL; 1845 } 1846 1847 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1848 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1849 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1850 if (hal->chip_version & BIT_RF_TYPE_ID) { 1851 hal->rf_type = RF_2T2R; 1852 hal->rf_path_num = 2; 1853 hal->antenna_tx = BB_PATH_AB; 1854 hal->antenna_rx = BB_PATH_AB; 1855 } else { 1856 hal->rf_type = RF_1T1R; 1857 hal->rf_path_num = 1; 1858 hal->antenna_tx = BB_PATH_A; 1859 hal->antenna_rx = BB_PATH_A; 1860 } 1861 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1862 hal->rf_path_num; 1863 1864 efuse->physical_size = chip->phy_efuse_size; 1865 efuse->logical_size = chip->log_efuse_size; 1866 efuse->protect_size = chip->ptct_efuse_size; 1867 1868 /* default use ack */ 1869 rtwdev->hal.rcr |= BIT_VHT_DACK; 1870 1871 hal->bfee_sts_cap = 3; 1872 1873 return 0; 1874 } 1875 1876 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1877 { 1878 struct rtw_fw_state *fw = &rtwdev->fw; 1879 int ret; 1880 1881 ret = rtw_hci_setup(rtwdev); 1882 if (ret) { 1883 rtw_err(rtwdev, "failed to setup hci\n"); 1884 goto err; 1885 } 1886 1887 ret = rtw_mac_power_on(rtwdev); 1888 if (ret) { 1889 rtw_err(rtwdev, "failed to power on mac\n"); 1890 goto err; 1891 } 1892 1893 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1894 1895 wait_for_completion(&fw->completion); 1896 if (!fw->firmware) { 1897 ret = -EINVAL; 1898 rtw_err(rtwdev, "failed to load firmware\n"); 1899 goto err; 1900 } 1901 1902 ret = rtw_download_firmware(rtwdev, fw); 1903 if (ret) { 1904 rtw_err(rtwdev, "failed to download firmware\n"); 1905 goto err_off; 1906 } 1907 1908 return 0; 1909 1910 err_off: 1911 rtw_mac_power_off(rtwdev); 1912 1913 err: 1914 return ret; 1915 } 1916 1917 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1918 { 1919 struct rtw_efuse *efuse = &rtwdev->efuse; 1920 u8 hw_feature[HW_FEATURE_LEN]; 1921 u8 id; 1922 u8 bw; 1923 int i; 1924 1925 id = rtw_read8(rtwdev, REG_C2HEVT); 1926 if (id != C2H_HW_FEATURE_REPORT) { 1927 rtw_err(rtwdev, "failed to read hw feature report\n"); 1928 return -EBUSY; 1929 } 1930 1931 for (i = 0; i < HW_FEATURE_LEN; i++) 1932 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1933 1934 rtw_write8(rtwdev, REG_C2HEVT, 0); 1935 1936 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1937 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1938 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1939 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1940 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1941 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1942 1943 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1944 1945 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1946 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1947 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1948 1949 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1950 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1951 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1952 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1953 1954 return 0; 1955 } 1956 1957 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1958 { 1959 rtw_hci_stop(rtwdev); 1960 rtw_mac_power_off(rtwdev); 1961 } 1962 1963 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1964 { 1965 struct rtw_efuse *efuse = &rtwdev->efuse; 1966 int ret; 1967 1968 mutex_lock(&rtwdev->mutex); 1969 1970 /* power on mac to read efuse */ 1971 ret = rtw_chip_efuse_enable(rtwdev); 1972 if (ret) 1973 goto out_unlock; 1974 1975 ret = rtw_parse_efuse_map(rtwdev); 1976 if (ret) 1977 goto out_disable; 1978 1979 ret = rtw_dump_hw_feature(rtwdev); 1980 if (ret) 1981 goto out_disable; 1982 1983 ret = rtw_check_supported_rfe(rtwdev); 1984 if (ret) 1985 goto out_disable; 1986 1987 if (efuse->crystal_cap == 0xff) 1988 efuse->crystal_cap = 0; 1989 if (efuse->pa_type_2g == 0xff) 1990 efuse->pa_type_2g = 0; 1991 if (efuse->pa_type_5g == 0xff) 1992 efuse->pa_type_5g = 0; 1993 if (efuse->lna_type_2g == 0xff) 1994 efuse->lna_type_2g = 0; 1995 if (efuse->lna_type_5g == 0xff) 1996 efuse->lna_type_5g = 0; 1997 if (efuse->channel_plan == 0xff) 1998 efuse->channel_plan = 0x7f; 1999 if (efuse->rf_board_option == 0xff) 2000 efuse->rf_board_option = 0; 2001 if (efuse->bt_setting & BIT(0)) 2002 efuse->share_ant = true; 2003 if (efuse->regd == 0xff) 2004 efuse->regd = 0; 2005 if (efuse->tx_bb_swing_setting_2g == 0xff) 2006 efuse->tx_bb_swing_setting_2g = 0; 2007 if (efuse->tx_bb_swing_setting_5g == 0xff) 2008 efuse->tx_bb_swing_setting_5g = 0; 2009 2010 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 2011 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 2012 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 2013 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 2014 efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 2015 2016 if (!is_valid_ether_addr(efuse->addr)) { 2017 eth_random_addr(efuse->addr); 2018 dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n"); 2019 } 2020 2021 out_disable: 2022 rtw_chip_efuse_disable(rtwdev); 2023 2024 out_unlock: 2025 mutex_unlock(&rtwdev->mutex); 2026 return ret; 2027 } 2028 2029 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 2030 { 2031 struct rtw_hal *hal = &rtwdev->hal; 2032 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 2033 2034 if (!rfe_def) 2035 return -ENODEV; 2036 2037 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type); 2038 2039 rtw_phy_init_tx_power(rtwdev); 2040 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 2041 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 2042 rtw_phy_tx_power_by_rate_config(hal); 2043 rtw_phy_tx_power_limit_config(hal); 2044 2045 return 0; 2046 } 2047 2048 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 2049 { 2050 int ret; 2051 2052 ret = rtw_chip_parameter_setup(rtwdev); 2053 if (ret) { 2054 rtw_err(rtwdev, "failed to setup chip parameters\n"); 2055 goto err_out; 2056 } 2057 2058 ret = rtw_chip_efuse_info_setup(rtwdev); 2059 if (ret) { 2060 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 2061 goto err_out; 2062 } 2063 2064 ret = rtw_chip_board_info_setup(rtwdev); 2065 if (ret) { 2066 rtw_err(rtwdev, "failed to setup chip board info\n"); 2067 goto err_out; 2068 } 2069 2070 return 0; 2071 2072 err_out: 2073 return ret; 2074 } 2075 EXPORT_SYMBOL(rtw_chip_info_setup); 2076 2077 static void rtw_stats_init(struct rtw_dev *rtwdev) 2078 { 2079 struct rtw_traffic_stats *stats = &rtwdev->stats; 2080 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2081 int i; 2082 2083 ewma_tp_init(&stats->tx_ewma_tp); 2084 ewma_tp_init(&stats->rx_ewma_tp); 2085 2086 for (i = 0; i < RTW_EVM_NUM; i++) 2087 ewma_evm_init(&dm_info->ewma_evm[i]); 2088 for (i = 0; i < RTW_SNR_NUM; i++) 2089 ewma_snr_init(&dm_info->ewma_snr[i]); 2090 } 2091 2092 int rtw_core_init(struct rtw_dev *rtwdev) 2093 { 2094 const struct rtw_chip_info *chip = rtwdev->chip; 2095 struct rtw_coex *coex = &rtwdev->coex; 2096 int ret; 2097 2098 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 2099 INIT_LIST_HEAD(&rtwdev->txqs); 2100 2101 timer_setup(&rtwdev->tx_report.purge_timer, 2102 rtw_tx_report_purge_timer, 0); 2103 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2104 if (!rtwdev->tx_wq) { 2105 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n"); 2106 return -ENOMEM; 2107 } 2108 2109 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 2110 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 2111 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 2112 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 2113 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 2114 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 2115 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 2116 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 2117 rtw_coex_bt_multi_link_remain_work); 2118 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2119 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2120 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2121 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2122 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2123 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2124 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2125 skb_queue_head_init(&rtwdev->c2h_queue); 2126 skb_queue_head_init(&rtwdev->coex.queue); 2127 skb_queue_head_init(&rtwdev->tx_report.queue); 2128 2129 spin_lock_init(&rtwdev->txq_lock); 2130 spin_lock_init(&rtwdev->tx_report.q_lock); 2131 2132 mutex_init(&rtwdev->mutex); 2133 mutex_init(&rtwdev->hal.tx_power_mutex); 2134 2135 init_waitqueue_head(&rtwdev->coex.wait); 2136 init_completion(&rtwdev->lps_leave_check); 2137 init_completion(&rtwdev->fw_scan_density); 2138 2139 rtwdev->sec.total_cam_num = 32; 2140 rtwdev->hal.current_channel = 1; 2141 rtwdev->dm_info.fix_rate = U8_MAX; 2142 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2143 2144 rtw_stats_init(rtwdev); 2145 2146 /* default rx filter setting */ 2147 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2148 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2149 BIT_AB | BIT_AM | BIT_APM; 2150 2151 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2152 if (ret) { 2153 rtw_warn(rtwdev, "no firmware loaded\n"); 2154 goto out; 2155 } 2156 2157 if (chip->wow_fw_name) { 2158 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2159 if (ret) { 2160 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2161 wait_for_completion(&rtwdev->fw.completion); 2162 if (rtwdev->fw.firmware) 2163 release_firmware(rtwdev->fw.firmware); 2164 goto out; 2165 } 2166 } 2167 2168 return 0; 2169 2170 out: 2171 destroy_workqueue(rtwdev->tx_wq); 2172 return ret; 2173 } 2174 EXPORT_SYMBOL(rtw_core_init); 2175 2176 void rtw_core_deinit(struct rtw_dev *rtwdev) 2177 { 2178 struct rtw_fw_state *fw = &rtwdev->fw; 2179 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2180 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2181 unsigned long flags; 2182 2183 rtw_wait_firmware_completion(rtwdev); 2184 2185 if (fw->firmware) 2186 release_firmware(fw->firmware); 2187 2188 if (wow_fw->firmware) 2189 release_firmware(wow_fw->firmware); 2190 2191 destroy_workqueue(rtwdev->tx_wq); 2192 timer_delete_sync(&rtwdev->tx_report.purge_timer); 2193 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2194 skb_queue_purge(&rtwdev->tx_report.queue); 2195 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2196 skb_queue_purge(&rtwdev->coex.queue); 2197 skb_queue_purge(&rtwdev->c2h_queue); 2198 2199 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2200 build_list) { 2201 list_del(&rsvd_pkt->build_list); 2202 kfree(rsvd_pkt); 2203 } 2204 2205 mutex_destroy(&rtwdev->mutex); 2206 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2207 } 2208 EXPORT_SYMBOL(rtw_core_deinit); 2209 2210 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2211 { 2212 bool sta_mode_only = rtwdev->hci.type == RTW_HCI_TYPE_SDIO; 2213 struct rtw_hal *hal = &rtwdev->hal; 2214 int max_tx_headroom = 0; 2215 int ret; 2216 2217 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2218 2219 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 2220 max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN; 2221 2222 hw->extra_tx_headroom = max_tx_headroom; 2223 hw->queues = IEEE80211_NUM_ACS; 2224 hw->txq_data_size = sizeof(struct rtw_txq); 2225 hw->sta_data_size = sizeof(struct rtw_sta_info); 2226 hw->vif_data_size = sizeof(struct rtw_vif); 2227 2228 ieee80211_hw_set(hw, SIGNAL_DBM); 2229 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2230 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2231 ieee80211_hw_set(hw, MFP_CAPABLE); 2232 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2233 ieee80211_hw_set(hw, SUPPORTS_PS); 2234 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2235 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2236 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2237 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2238 ieee80211_hw_set(hw, TX_AMSDU); 2239 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2240 2241 if (sta_mode_only) 2242 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 2243 else 2244 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2245 BIT(NL80211_IFTYPE_AP) | 2246 BIT(NL80211_IFTYPE_ADHOC); 2247 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2248 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2249 2250 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2251 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2252 2253 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2254 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2255 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev); 2256 2257 if (!sta_mode_only && rtwdev->chip->id == RTW_CHIP_TYPE_8822C) { 2258 hw->wiphy->iface_combinations = rtw_iface_combs; 2259 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs); 2260 } 2261 2262 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2263 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2264 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2265 2266 #ifdef CONFIG_PM 2267 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2268 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2269 #endif 2270 rtw_set_supported_band(hw, rtwdev->chip); 2271 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2272 2273 hw->wiphy->sar_capa = &rtw_sar_capa; 2274 2275 ret = rtw_regd_init(rtwdev); 2276 if (ret) { 2277 rtw_err(rtwdev, "failed to init regd\n"); 2278 return ret; 2279 } 2280 2281 ret = ieee80211_register_hw(hw); 2282 if (ret) { 2283 rtw_err(rtwdev, "failed to register hw\n"); 2284 return ret; 2285 } 2286 2287 ret = rtw_regd_hint(rtwdev); 2288 if (ret) { 2289 rtw_err(rtwdev, "failed to hint regd\n"); 2290 return ret; 2291 } 2292 2293 rtw_debugfs_init(rtwdev); 2294 2295 rtwdev->bf_info.bfer_mu_cnt = 0; 2296 rtwdev->bf_info.bfer_su_cnt = 0; 2297 2298 return 0; 2299 } 2300 EXPORT_SYMBOL(rtw_register_hw); 2301 2302 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2303 { 2304 const struct rtw_chip_info *chip = rtwdev->chip; 2305 2306 ieee80211_unregister_hw(hw); 2307 rtw_unset_supported_band(hw, chip); 2308 rtw_debugfs_deinit(rtwdev); 2309 } 2310 EXPORT_SYMBOL(rtw_unregister_hw); 2311 2312 static 2313 void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2314 const struct rtw_hw_reg *reg2, u8 nbytes) 2315 { 2316 u8 i; 2317 2318 for (i = 0; i < nbytes; i++) { 2319 u8 v1 = rtw_read8(rtwdev, reg1->addr + i); 2320 u8 v2 = rtw_read8(rtwdev, reg2->addr + i); 2321 2322 rtw_write8(rtwdev, reg1->addr + i, v2); 2323 rtw_write8(rtwdev, reg2->addr + i, v1); 2324 } 2325 } 2326 2327 static 2328 void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2329 const struct rtw_hw_reg *reg2) 2330 { 2331 u32 v1, v2; 2332 2333 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask); 2334 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask); 2335 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1); 2336 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2); 2337 } 2338 2339 struct rtw_iter_port_switch_data { 2340 struct rtw_dev *rtwdev; 2341 struct rtw_vif *rtwvif_ap; 2342 }; 2343 2344 static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif) 2345 { 2346 struct rtw_iter_port_switch_data *iter_data = data; 2347 struct rtw_dev *rtwdev = iter_data->rtwdev; 2348 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv; 2349 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap; 2350 const struct rtw_hw_reg *reg1, *reg2; 2351 2352 if (rtwvif_target->port != RTW_PORT_0) 2353 return; 2354 2355 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n", 2356 rtwvif_ap->port, rtwvif_target->port); 2357 2358 /* Leave LPS so the value swapped are not in PS mode */ 2359 rtw_leave_lps(rtwdev); 2360 2361 reg1 = &rtwvif_ap->conf->net_type; 2362 reg2 = &rtwvif_target->conf->net_type; 2363 rtw_swap_reg_mask(rtwdev, reg1, reg2); 2364 2365 reg1 = &rtwvif_ap->conf->mac_addr; 2366 reg2 = &rtwvif_target->conf->mac_addr; 2367 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2368 2369 reg1 = &rtwvif_ap->conf->bssid; 2370 reg2 = &rtwvif_target->conf->bssid; 2371 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2372 2373 reg1 = &rtwvif_ap->conf->bcn_ctrl; 2374 reg2 = &rtwvif_target->conf->bcn_ctrl; 2375 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1); 2376 2377 swap(rtwvif_target->port, rtwvif_ap->port); 2378 swap(rtwvif_target->conf, rtwvif_ap->conf); 2379 2380 rtw_fw_default_port(rtwdev, rtwvif_target); 2381 } 2382 2383 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 2384 { 2385 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2386 struct rtw_iter_port_switch_data iter_data; 2387 2388 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0) 2389 return; 2390 2391 iter_data.rtwdev = rtwdev; 2392 iter_data.rtwvif_ap = rtwvif; 2393 rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data); 2394 } 2395 2396 static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif) 2397 { 2398 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2399 bool *active = data; 2400 2401 if (*active) 2402 return; 2403 2404 if (vif->type != NL80211_IFTYPE_STATION) 2405 return; 2406 2407 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid)) 2408 *active = true; 2409 } 2410 2411 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev) 2412 { 2413 bool sta_active = false; 2414 2415 rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active); 2416 2417 return rtwdev->ap_active || sta_active; 2418 } 2419 2420 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable) 2421 { 2422 if (!rtwdev->ap_active) 2423 return; 2424 2425 if (enable) { 2426 rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2427 rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2428 } else { 2429 rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2430 rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2431 } 2432 } 2433 2434 MODULE_AUTHOR("Realtek Corporation"); 2435 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2436 MODULE_LICENSE("Dual BSD/GPL"); 2437