1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 22 bool rtw_disable_lps_deep_mode; 23 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 24 bool rtw_bf_support = true; 25 unsigned int rtw_debug_mask; 26 EXPORT_SYMBOL(rtw_debug_mask); 27 /* EDCCA is enabled during normal behavior. For debugging purpose in 28 * a noisy environment, it can be disabled via edcca debugfs. Because 29 * all rtw88 devices will probably be affected if environment is noisy, 30 * rtw_edcca_enabled is just declared by driver instead of by device. 31 * So, turning it off will take effect for all rtw88 devices before 32 * there is a tough reason to maintain rtw_edcca_enabled by device. 33 */ 34 bool rtw_edcca_enabled = true; 35 36 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 37 module_param_named(support_bf, rtw_bf_support, bool, 0644); 38 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 39 40 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 41 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 42 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 43 44 static struct ieee80211_channel rtw_channeltable_2g[] = { 45 {.center_freq = 2412, .hw_value = 1,}, 46 {.center_freq = 2417, .hw_value = 2,}, 47 {.center_freq = 2422, .hw_value = 3,}, 48 {.center_freq = 2427, .hw_value = 4,}, 49 {.center_freq = 2432, .hw_value = 5,}, 50 {.center_freq = 2437, .hw_value = 6,}, 51 {.center_freq = 2442, .hw_value = 7,}, 52 {.center_freq = 2447, .hw_value = 8,}, 53 {.center_freq = 2452, .hw_value = 9,}, 54 {.center_freq = 2457, .hw_value = 10,}, 55 {.center_freq = 2462, .hw_value = 11,}, 56 {.center_freq = 2467, .hw_value = 12,}, 57 {.center_freq = 2472, .hw_value = 13,}, 58 {.center_freq = 2484, .hw_value = 14,}, 59 }; 60 61 static struct ieee80211_channel rtw_channeltable_5g[] = { 62 {.center_freq = 5180, .hw_value = 36,}, 63 {.center_freq = 5200, .hw_value = 40,}, 64 {.center_freq = 5220, .hw_value = 44,}, 65 {.center_freq = 5240, .hw_value = 48,}, 66 {.center_freq = 5260, .hw_value = 52,}, 67 {.center_freq = 5280, .hw_value = 56,}, 68 {.center_freq = 5300, .hw_value = 60,}, 69 {.center_freq = 5320, .hw_value = 64,}, 70 {.center_freq = 5500, .hw_value = 100,}, 71 {.center_freq = 5520, .hw_value = 104,}, 72 {.center_freq = 5540, .hw_value = 108,}, 73 {.center_freq = 5560, .hw_value = 112,}, 74 {.center_freq = 5580, .hw_value = 116,}, 75 {.center_freq = 5600, .hw_value = 120,}, 76 {.center_freq = 5620, .hw_value = 124,}, 77 {.center_freq = 5640, .hw_value = 128,}, 78 {.center_freq = 5660, .hw_value = 132,}, 79 {.center_freq = 5680, .hw_value = 136,}, 80 {.center_freq = 5700, .hw_value = 140,}, 81 {.center_freq = 5720, .hw_value = 144,}, 82 {.center_freq = 5745, .hw_value = 149,}, 83 {.center_freq = 5765, .hw_value = 153,}, 84 {.center_freq = 5785, .hw_value = 157,}, 85 {.center_freq = 5805, .hw_value = 161,}, 86 {.center_freq = 5825, .hw_value = 165, 87 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 88 }; 89 90 static struct ieee80211_rate rtw_ratetable[] = { 91 {.bitrate = 10, .hw_value = 0x00,}, 92 {.bitrate = 20, .hw_value = 0x01,}, 93 {.bitrate = 55, .hw_value = 0x02,}, 94 {.bitrate = 110, .hw_value = 0x03,}, 95 {.bitrate = 60, .hw_value = 0x04,}, 96 {.bitrate = 90, .hw_value = 0x05,}, 97 {.bitrate = 120, .hw_value = 0x06,}, 98 {.bitrate = 180, .hw_value = 0x07,}, 99 {.bitrate = 240, .hw_value = 0x08,}, 100 {.bitrate = 360, .hw_value = 0x09,}, 101 {.bitrate = 480, .hw_value = 0x0a,}, 102 {.bitrate = 540, .hw_value = 0x0b,}, 103 }; 104 105 u16 rtw_desc_to_bitrate(u8 desc_rate) 106 { 107 struct ieee80211_rate rate; 108 109 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 110 return 0; 111 112 rate = rtw_ratetable[desc_rate]; 113 114 return rate.bitrate; 115 } 116 117 static struct ieee80211_supported_band rtw_band_2ghz = { 118 .band = NL80211_BAND_2GHZ, 119 120 .channels = rtw_channeltable_2g, 121 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 122 123 .bitrates = rtw_ratetable, 124 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 125 126 .ht_cap = {0}, 127 .vht_cap = {0}, 128 }; 129 130 static struct ieee80211_supported_band rtw_band_5ghz = { 131 .band = NL80211_BAND_5GHZ, 132 133 .channels = rtw_channeltable_5g, 134 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 135 136 /* 5G has no CCK rates */ 137 .bitrates = rtw_ratetable + 4, 138 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 139 140 .ht_cap = {0}, 141 .vht_cap = {0}, 142 }; 143 144 struct rtw_watch_dog_iter_data { 145 struct rtw_dev *rtwdev; 146 struct rtw_vif *rtwvif; 147 }; 148 149 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 150 { 151 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 152 u8 fix_rate_enable = 0; 153 u8 new_csi_rate_idx; 154 155 if (rtwvif->bfee.role != RTW_BFEE_SU && 156 rtwvif->bfee.role != RTW_BFEE_MU) 157 return; 158 159 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 160 bf_info->cur_csi_rpt_rate, 161 fix_rate_enable, &new_csi_rate_idx); 162 163 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 164 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 165 } 166 167 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 168 struct ieee80211_vif *vif) 169 { 170 struct rtw_watch_dog_iter_data *iter_data = data; 171 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 172 173 if (vif->type == NL80211_IFTYPE_STATION) 174 if (vif->bss_conf.assoc) 175 iter_data->rtwvif = rtwvif; 176 177 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 178 179 rtwvif->stats.tx_unicast = 0; 180 rtwvif->stats.rx_unicast = 0; 181 rtwvif->stats.tx_cnt = 0; 182 rtwvif->stats.rx_cnt = 0; 183 } 184 185 /* process TX/RX statistics periodically for hardware, 186 * the information helps hardware to enhance performance 187 */ 188 static void rtw_watch_dog_work(struct work_struct *work) 189 { 190 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 191 watch_dog_work.work); 192 struct rtw_traffic_stats *stats = &rtwdev->stats; 193 struct rtw_watch_dog_iter_data data = {}; 194 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 195 bool ps_active; 196 197 mutex_lock(&rtwdev->mutex); 198 199 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 200 goto unlock; 201 202 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 203 RTW_WATCH_DOG_DELAY_TIME); 204 205 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 206 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 207 else 208 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 209 210 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 211 rtw_coex_wl_status_change_notify(rtwdev, 0); 212 213 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 214 stats->rx_cnt > RTW_LPS_THRESHOLD) 215 ps_active = true; 216 else 217 ps_active = false; 218 219 ewma_tp_add(&stats->tx_ewma_tp, 220 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 221 ewma_tp_add(&stats->rx_ewma_tp, 222 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 223 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 224 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 225 226 /* reset tx/rx statictics */ 227 stats->tx_unicast = 0; 228 stats->rx_unicast = 0; 229 stats->tx_cnt = 0; 230 stats->rx_cnt = 0; 231 232 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 233 goto unlock; 234 235 /* make sure BB/RF is working for dynamic mech */ 236 rtw_leave_lps(rtwdev); 237 238 rtw_phy_dynamic_mechanism(rtwdev); 239 240 data.rtwdev = rtwdev; 241 /* use atomic version to avoid taking local->iflist_mtx mutex */ 242 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 243 244 /* fw supports only one station associated to enter lps, if there are 245 * more than two stations associated to the AP, then we can not enter 246 * lps, because fw does not handle the overlapped beacon interval 247 * 248 * mac80211 should iterate vifs and determine if driver can enter 249 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 250 * get that vif and check if device is having traffic more than the 251 * threshold. 252 */ 253 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 254 !rtwdev->beacon_loss) 255 rtw_enter_lps(rtwdev, data.rtwvif->port); 256 257 rtwdev->watch_dog_cnt++; 258 259 unlock: 260 mutex_unlock(&rtwdev->mutex); 261 } 262 263 static void rtw_c2h_work(struct work_struct *work) 264 { 265 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 266 struct sk_buff *skb, *tmp; 267 268 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 269 skb_unlink(skb, &rtwdev->c2h_queue); 270 rtw_fw_c2h_cmd_handle(rtwdev, skb); 271 dev_kfree_skb_any(skb); 272 } 273 } 274 275 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 276 { 277 unsigned long mac_id; 278 279 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 280 if (mac_id < RTW_MAX_MAC_ID_NUM) 281 set_bit(mac_id, rtwdev->mac_id_map); 282 283 return mac_id; 284 } 285 286 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 287 struct ieee80211_vif *vif) 288 { 289 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 290 int i; 291 292 si->mac_id = rtw_acquire_macid(rtwdev); 293 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 294 return -ENOSPC; 295 296 si->sta = sta; 297 si->vif = vif; 298 si->init_ra_lv = 1; 299 ewma_rssi_init(&si->avg_rssi); 300 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 301 rtw_txq_init(rtwdev, sta->txq[i]); 302 303 rtw_update_sta_info(rtwdev, si); 304 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 305 306 rtwdev->sta_cnt++; 307 rtwdev->beacon_loss = false; 308 rtw_info(rtwdev, "sta %pM joined with macid %d\n", 309 sta->addr, si->mac_id); 310 311 return 0; 312 } 313 314 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 315 bool fw_exist) 316 { 317 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 318 int i; 319 320 rtw_release_macid(rtwdev, si->mac_id); 321 if (fw_exist) 322 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 323 324 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 325 rtw_txq_cleanup(rtwdev, sta->txq[i]); 326 327 kfree(si->mask); 328 329 rtwdev->sta_cnt--; 330 rtw_info(rtwdev, "sta %pM with macid %d left\n", 331 sta->addr, si->mac_id); 332 } 333 334 struct rtw_fwcd_hdr { 335 u32 item; 336 u32 size; 337 u32 padding1; 338 u32 padding2; 339 } __packed; 340 341 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 342 { 343 struct rtw_chip_info *chip = rtwdev->chip; 344 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 345 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 346 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 347 u8 i; 348 349 if (segs) { 350 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 351 352 for (i = 0; i < segs->num; i++) 353 prep_size += segs->segs[i]; 354 } 355 356 desc->data = vmalloc(prep_size); 357 if (!desc->data) 358 return -ENOMEM; 359 360 desc->size = prep_size; 361 desc->next = desc->data; 362 363 return 0; 364 } 365 366 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 367 { 368 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 369 struct rtw_fwcd_hdr *hdr; 370 u8 *next; 371 372 if (!desc->data) { 373 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 374 return NULL; 375 } 376 377 next = desc->next + sizeof(struct rtw_fwcd_hdr); 378 if (next - desc->data + size > desc->size) { 379 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 380 return NULL; 381 } 382 383 hdr = (struct rtw_fwcd_hdr *)(desc->next); 384 hdr->item = item; 385 hdr->size = size; 386 hdr->padding1 = 0x01234567; 387 hdr->padding2 = 0x89abcdef; 388 desc->next = next + size; 389 390 return next; 391 } 392 393 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 394 { 395 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 396 397 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 398 399 /* Data will be freed after lifetime of device coredump. After calling 400 * dev_coredump, data is supposed to be handled by the device coredump 401 * framework. Note that a new dump will be discarded if a previous one 402 * hasn't been released yet. 403 */ 404 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 405 } 406 407 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 408 { 409 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 410 411 if (free_self) { 412 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 413 vfree(desc->data); 414 } 415 416 desc->data = NULL; 417 desc->next = NULL; 418 } 419 420 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 421 { 422 u32 size = rtwdev->chip->fw_rxff_size; 423 u32 *buf; 424 u8 seq; 425 426 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 427 if (!buf) 428 return -ENOMEM; 429 430 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 431 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 432 return -EINVAL; 433 } 434 435 if (GET_FW_DUMP_LEN(buf) == 0) { 436 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 437 return -EINVAL; 438 } 439 440 seq = GET_FW_DUMP_SEQ(buf); 441 if (seq > 0) { 442 rtw_dbg(rtwdev, RTW_DBG_FW, 443 "fw crash dump's seq is wrong: %d\n", seq); 444 return -EINVAL; 445 } 446 447 return 0; 448 } 449 450 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 451 u32 fwcd_item) 452 { 453 u32 rxff = rtwdev->chip->fw_rxff_size; 454 u32 dump_size, done_size = 0; 455 u8 *buf; 456 int ret; 457 458 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 459 if (!buf) 460 return -ENOMEM; 461 462 while (size) { 463 dump_size = size > rxff ? rxff : size; 464 465 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 466 dump_size); 467 if (ret) { 468 rtw_err(rtwdev, 469 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 470 ocp_src, done_size); 471 return ret; 472 } 473 474 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 475 dump_size, (u32 *)(buf + done_size)); 476 if (ret) { 477 rtw_err(rtwdev, 478 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 479 ocp_src, done_size); 480 return ret; 481 } 482 483 size -= dump_size; 484 done_size += dump_size; 485 } 486 487 return 0; 488 } 489 EXPORT_SYMBOL(rtw_dump_fw); 490 491 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 492 { 493 u8 *buf; 494 u32 i; 495 496 if (addr & 0x3) { 497 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 498 return -EINVAL; 499 } 500 501 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 502 if (!buf) 503 return -ENOMEM; 504 505 for (i = 0; i < size; i += 4) 506 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 507 508 return 0; 509 } 510 EXPORT_SYMBOL(rtw_dump_reg); 511 512 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 513 struct ieee80211_bss_conf *conf) 514 { 515 if (conf && conf->assoc) { 516 rtwvif->aid = conf->aid; 517 rtwvif->net_type = RTW_NET_MGD_LINKED; 518 } else { 519 rtwvif->aid = 0; 520 rtwvif->net_type = RTW_NET_NO_LINK; 521 } 522 } 523 524 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 525 struct ieee80211_vif *vif, 526 struct ieee80211_sta *sta, 527 struct ieee80211_key_conf *key, 528 void *data) 529 { 530 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 531 struct rtw_sec_desc *sec = &rtwdev->sec; 532 533 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 534 } 535 536 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 537 { 538 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 539 540 if (rtwdev->sta_cnt == 0) { 541 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 542 return; 543 } 544 rtw_sta_remove(rtwdev, sta, false); 545 } 546 547 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 548 { 549 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 550 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 551 552 rtw_bf_disassoc(rtwdev, vif, NULL); 553 rtw_vif_assoc_changed(rtwvif, NULL); 554 rtw_txq_cleanup(rtwdev, vif->txq); 555 } 556 557 void rtw_fw_recovery(struct rtw_dev *rtwdev) 558 { 559 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 560 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 561 } 562 563 static void __fw_recovery_work(struct rtw_dev *rtwdev) 564 { 565 int ret = 0; 566 567 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 568 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 569 570 ret = rtw_fwcd_prep(rtwdev); 571 if (ret) 572 goto free; 573 ret = rtw_fw_dump_crash_log(rtwdev); 574 if (ret) 575 goto free; 576 ret = rtw_chip_dump_fw_crash(rtwdev); 577 if (ret) 578 goto free; 579 580 rtw_fwcd_dump(rtwdev); 581 free: 582 rtw_fwcd_free(rtwdev, !!ret); 583 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 584 585 WARN(1, "firmware crash, start reset and recover\n"); 586 587 rcu_read_lock(); 588 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 589 rcu_read_unlock(); 590 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 591 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 592 rtw_enter_ips(rtwdev); 593 } 594 595 static void rtw_fw_recovery_work(struct work_struct *work) 596 { 597 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 598 fw_recovery_work); 599 600 mutex_lock(&rtwdev->mutex); 601 __fw_recovery_work(rtwdev); 602 mutex_unlock(&rtwdev->mutex); 603 604 ieee80211_restart_hw(rtwdev->hw); 605 } 606 607 struct rtw_txq_ba_iter_data { 608 }; 609 610 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 611 { 612 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 613 int ret; 614 u8 tid; 615 616 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 617 while (tid != IEEE80211_NUM_TIDS) { 618 clear_bit(tid, si->tid_ba); 619 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 620 if (ret == -EINVAL) { 621 struct ieee80211_txq *txq; 622 struct rtw_txq *rtwtxq; 623 624 txq = sta->txq[tid]; 625 rtwtxq = (struct rtw_txq *)txq->drv_priv; 626 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 627 } 628 629 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 630 } 631 } 632 633 static void rtw_txq_ba_work(struct work_struct *work) 634 { 635 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 636 struct rtw_txq_ba_iter_data data; 637 638 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 639 } 640 641 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 642 { 643 if (IS_CH_2G_BAND(channel)) 644 pkt_stat->band = NL80211_BAND_2GHZ; 645 else if (IS_CH_5G_BAND(channel)) 646 pkt_stat->band = NL80211_BAND_5GHZ; 647 else 648 return; 649 650 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 651 } 652 EXPORT_SYMBOL(rtw_set_rx_freq_band); 653 654 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 655 struct rtw_channel_params *chan_params) 656 { 657 struct ieee80211_channel *channel = chandef->chan; 658 enum nl80211_chan_width width = chandef->width; 659 u8 *cch_by_bw = chan_params->cch_by_bw; 660 u32 primary_freq, center_freq; 661 u8 center_chan; 662 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 663 u8 primary_chan_idx = 0; 664 u8 i; 665 666 center_chan = channel->hw_value; 667 primary_freq = channel->center_freq; 668 center_freq = chandef->center_freq1; 669 670 /* assign the center channel used while 20M bw is selected */ 671 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 672 673 switch (width) { 674 case NL80211_CHAN_WIDTH_20_NOHT: 675 case NL80211_CHAN_WIDTH_20: 676 bandwidth = RTW_CHANNEL_WIDTH_20; 677 primary_chan_idx = RTW_SC_DONT_CARE; 678 break; 679 case NL80211_CHAN_WIDTH_40: 680 bandwidth = RTW_CHANNEL_WIDTH_40; 681 if (primary_freq > center_freq) { 682 primary_chan_idx = RTW_SC_20_UPPER; 683 center_chan -= 2; 684 } else { 685 primary_chan_idx = RTW_SC_20_LOWER; 686 center_chan += 2; 687 } 688 break; 689 case NL80211_CHAN_WIDTH_80: 690 bandwidth = RTW_CHANNEL_WIDTH_80; 691 if (primary_freq > center_freq) { 692 if (primary_freq - center_freq == 10) { 693 primary_chan_idx = RTW_SC_20_UPPER; 694 center_chan -= 2; 695 } else { 696 primary_chan_idx = RTW_SC_20_UPMOST; 697 center_chan -= 6; 698 } 699 /* assign the center channel used 700 * while 40M bw is selected 701 */ 702 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 703 } else { 704 if (center_freq - primary_freq == 10) { 705 primary_chan_idx = RTW_SC_20_LOWER; 706 center_chan += 2; 707 } else { 708 primary_chan_idx = RTW_SC_20_LOWEST; 709 center_chan += 6; 710 } 711 /* assign the center channel used 712 * while 40M bw is selected 713 */ 714 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 715 } 716 break; 717 default: 718 center_chan = 0; 719 break; 720 } 721 722 chan_params->center_chan = center_chan; 723 chan_params->bandwidth = bandwidth; 724 chan_params->primary_chan_idx = primary_chan_idx; 725 726 /* assign the center channel used while current bw is selected */ 727 cch_by_bw[bandwidth] = center_chan; 728 729 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 730 cch_by_bw[i] = 0; 731 } 732 733 void rtw_set_channel(struct rtw_dev *rtwdev) 734 { 735 struct ieee80211_hw *hw = rtwdev->hw; 736 struct rtw_hal *hal = &rtwdev->hal; 737 struct rtw_chip_info *chip = rtwdev->chip; 738 struct rtw_channel_params ch_param; 739 u8 center_chan, bandwidth, primary_chan_idx; 740 u8 i; 741 742 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 743 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 744 return; 745 746 center_chan = ch_param.center_chan; 747 bandwidth = ch_param.bandwidth; 748 primary_chan_idx = ch_param.primary_chan_idx; 749 750 hal->current_band_width = bandwidth; 751 hal->current_channel = center_chan; 752 hal->current_primary_channel_index = primary_chan_idx; 753 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 754 755 switch (center_chan) { 756 case 1 ... 14: 757 hal->sar_band = RTW_SAR_BAND_0; 758 break; 759 case 36 ... 64: 760 hal->sar_band = RTW_SAR_BAND_1; 761 break; 762 case 100 ... 144: 763 hal->sar_band = RTW_SAR_BAND_3; 764 break; 765 case 149 ... 177: 766 hal->sar_band = RTW_SAR_BAND_4; 767 break; 768 default: 769 WARN(1, "unknown ch(%u) to SAR band\n", center_chan); 770 hal->sar_band = RTW_SAR_BAND_0; 771 break; 772 } 773 774 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 775 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 776 777 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 778 779 if (hal->current_band_type == RTW_BAND_5G) { 780 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 781 } else { 782 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 783 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 784 else 785 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 786 } 787 788 rtw_phy_set_tx_power_level(rtwdev, center_chan); 789 790 /* if the channel isn't set for scanning, we will do RF calibration 791 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 792 * during scanning on each channel takes too long. 793 */ 794 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 795 rtwdev->need_rfk = true; 796 } 797 798 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 799 { 800 struct rtw_chip_info *chip = rtwdev->chip; 801 802 if (rtwdev->need_rfk) { 803 rtwdev->need_rfk = false; 804 chip->ops->phy_calibration(rtwdev); 805 } 806 } 807 808 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 809 { 810 int i; 811 812 for (i = 0; i < ETH_ALEN; i++) 813 rtw_write8(rtwdev, start + i, addr[i]); 814 } 815 816 void rtw_vif_port_config(struct rtw_dev *rtwdev, 817 struct rtw_vif *rtwvif, 818 u32 config) 819 { 820 u32 addr, mask; 821 822 if (config & PORT_SET_MAC_ADDR) { 823 addr = rtwvif->conf->mac_addr.addr; 824 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 825 } 826 if (config & PORT_SET_BSSID) { 827 addr = rtwvif->conf->bssid.addr; 828 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 829 } 830 if (config & PORT_SET_NET_TYPE) { 831 addr = rtwvif->conf->net_type.addr; 832 mask = rtwvif->conf->net_type.mask; 833 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 834 } 835 if (config & PORT_SET_AID) { 836 addr = rtwvif->conf->aid.addr; 837 mask = rtwvif->conf->aid.mask; 838 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 839 } 840 if (config & PORT_SET_BCN_CTRL) { 841 addr = rtwvif->conf->bcn_ctrl.addr; 842 mask = rtwvif->conf->bcn_ctrl.mask; 843 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 844 } 845 } 846 847 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 848 { 849 u8 bw = 0; 850 851 switch (bw_cap) { 852 case EFUSE_HW_CAP_IGNORE: 853 case EFUSE_HW_CAP_SUPP_BW80: 854 bw |= BIT(RTW_CHANNEL_WIDTH_80); 855 fallthrough; 856 case EFUSE_HW_CAP_SUPP_BW40: 857 bw |= BIT(RTW_CHANNEL_WIDTH_40); 858 fallthrough; 859 default: 860 bw |= BIT(RTW_CHANNEL_WIDTH_20); 861 break; 862 } 863 864 return bw; 865 } 866 867 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 868 { 869 struct rtw_hal *hal = &rtwdev->hal; 870 struct rtw_chip_info *chip = rtwdev->chip; 871 872 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 873 hw_ant_num >= hal->rf_path_num) 874 return; 875 876 switch (hw_ant_num) { 877 case 1: 878 hal->rf_type = RF_1T1R; 879 hal->rf_path_num = 1; 880 if (!chip->fix_rf_phy_num) 881 hal->rf_phy_num = hal->rf_path_num; 882 hal->antenna_tx = BB_PATH_A; 883 hal->antenna_rx = BB_PATH_A; 884 break; 885 default: 886 WARN(1, "invalid hw configuration from efuse\n"); 887 break; 888 } 889 } 890 891 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 892 { 893 u64 ra_mask = 0; 894 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 895 u8 vht_mcs_cap; 896 int i, nss; 897 898 /* 4SS, every two bits for MCS7/8/9 */ 899 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 900 vht_mcs_cap = mcs_map & 0x3; 901 switch (vht_mcs_cap) { 902 case 2: /* MCS9 */ 903 ra_mask |= 0x3ffULL << nss; 904 break; 905 case 1: /* MCS8 */ 906 ra_mask |= 0x1ffULL << nss; 907 break; 908 case 0: /* MCS7 */ 909 ra_mask |= 0x0ffULL << nss; 910 break; 911 default: 912 break; 913 } 914 } 915 916 return ra_mask; 917 } 918 919 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 920 { 921 u8 rate_id = 0; 922 923 switch (wireless_set) { 924 case WIRELESS_CCK: 925 rate_id = RTW_RATEID_B_20M; 926 break; 927 case WIRELESS_OFDM: 928 rate_id = RTW_RATEID_G; 929 break; 930 case WIRELESS_CCK | WIRELESS_OFDM: 931 rate_id = RTW_RATEID_BG; 932 break; 933 case WIRELESS_OFDM | WIRELESS_HT: 934 if (tx_num == 1) 935 rate_id = RTW_RATEID_GN_N1SS; 936 else if (tx_num == 2) 937 rate_id = RTW_RATEID_GN_N2SS; 938 else if (tx_num == 3) 939 rate_id = RTW_RATEID_ARFR5_N_3SS; 940 break; 941 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 942 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 943 if (tx_num == 1) 944 rate_id = RTW_RATEID_BGN_40M_1SS; 945 else if (tx_num == 2) 946 rate_id = RTW_RATEID_BGN_40M_2SS; 947 else if (tx_num == 3) 948 rate_id = RTW_RATEID_ARFR5_N_3SS; 949 else if (tx_num == 4) 950 rate_id = RTW_RATEID_ARFR7_N_4SS; 951 } else { 952 if (tx_num == 1) 953 rate_id = RTW_RATEID_BGN_20M_1SS; 954 else if (tx_num == 2) 955 rate_id = RTW_RATEID_BGN_20M_2SS; 956 else if (tx_num == 3) 957 rate_id = RTW_RATEID_ARFR5_N_3SS; 958 else if (tx_num == 4) 959 rate_id = RTW_RATEID_ARFR7_N_4SS; 960 } 961 break; 962 case WIRELESS_OFDM | WIRELESS_VHT: 963 if (tx_num == 1) 964 rate_id = RTW_RATEID_ARFR1_AC_1SS; 965 else if (tx_num == 2) 966 rate_id = RTW_RATEID_ARFR0_AC_2SS; 967 else if (tx_num == 3) 968 rate_id = RTW_RATEID_ARFR4_AC_3SS; 969 else if (tx_num == 4) 970 rate_id = RTW_RATEID_ARFR6_AC_4SS; 971 break; 972 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 973 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 974 if (tx_num == 1) 975 rate_id = RTW_RATEID_ARFR1_AC_1SS; 976 else if (tx_num == 2) 977 rate_id = RTW_RATEID_ARFR0_AC_2SS; 978 else if (tx_num == 3) 979 rate_id = RTW_RATEID_ARFR4_AC_3SS; 980 else if (tx_num == 4) 981 rate_id = RTW_RATEID_ARFR6_AC_4SS; 982 } else { 983 if (tx_num == 1) 984 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 985 else if (tx_num == 2) 986 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 987 else if (tx_num == 3) 988 rate_id = RTW_RATEID_ARFR4_AC_3SS; 989 else if (tx_num == 4) 990 rate_id = RTW_RATEID_ARFR6_AC_4SS; 991 } 992 break; 993 default: 994 break; 995 } 996 997 return rate_id; 998 } 999 1000 #define RA_MASK_CCK_RATES 0x0000f 1001 #define RA_MASK_OFDM_RATES 0x00ff0 1002 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1003 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1004 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1005 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1006 RA_MASK_HT_RATES_2SS | \ 1007 RA_MASK_HT_RATES_3SS) 1008 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1009 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1010 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1011 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1012 RA_MASK_VHT_RATES_2SS | \ 1013 RA_MASK_VHT_RATES_3SS) 1014 #define RA_MASK_CCK_IN_HT 0x00005 1015 #define RA_MASK_CCK_IN_VHT 0x00005 1016 #define RA_MASK_OFDM_IN_VHT 0x00010 1017 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1018 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1019 1020 static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev, 1021 struct rtw_sta_info *si, 1022 u64 ra_mask, bool is_vht_enable, 1023 u8 wireless_set) 1024 { 1025 struct rtw_hal *hal = &rtwdev->hal; 1026 const struct cfg80211_bitrate_mask *mask = si->mask; 1027 u64 cfg_mask = GENMASK_ULL(63, 0); 1028 u8 rssi_level, band; 1029 1030 if (wireless_set != WIRELESS_CCK) { 1031 rssi_level = si->rssi_level; 1032 if (rssi_level == 0) 1033 ra_mask &= 0xffffffffffffffffULL; 1034 else if (rssi_level == 1) 1035 ra_mask &= 0xfffffffffffffff0ULL; 1036 else if (rssi_level == 2) 1037 ra_mask &= 0xffffffffffffefe0ULL; 1038 else if (rssi_level == 3) 1039 ra_mask &= 0xffffffffffffcfc0ULL; 1040 else if (rssi_level == 4) 1041 ra_mask &= 0xffffffffffff8f80ULL; 1042 else if (rssi_level >= 5) 1043 ra_mask &= 0xffffffffffff0f00ULL; 1044 } 1045 1046 if (!si->use_cfg_mask) 1047 return ra_mask; 1048 1049 band = hal->current_band_type; 1050 if (band == RTW_BAND_2G) { 1051 band = NL80211_BAND_2GHZ; 1052 cfg_mask = mask->control[band].legacy; 1053 } else if (band == RTW_BAND_5G) { 1054 band = NL80211_BAND_5GHZ; 1055 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1056 RA_MASK_OFDM_RATES); 1057 } 1058 1059 if (!is_vht_enable) { 1060 if (ra_mask & RA_MASK_HT_RATES_1SS) 1061 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1062 RA_MASK_HT_RATES_1SS); 1063 if (ra_mask & RA_MASK_HT_RATES_2SS) 1064 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1065 RA_MASK_HT_RATES_2SS); 1066 } else { 1067 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1068 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1069 RA_MASK_VHT_RATES_1SS); 1070 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1071 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1072 RA_MASK_VHT_RATES_2SS); 1073 } 1074 1075 ra_mask &= cfg_mask; 1076 1077 return ra_mask; 1078 } 1079 1080 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 1081 { 1082 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1083 struct ieee80211_sta *sta = si->sta; 1084 struct rtw_efuse *efuse = &rtwdev->efuse; 1085 struct rtw_hal *hal = &rtwdev->hal; 1086 u8 wireless_set; 1087 u8 bw_mode; 1088 u8 rate_id; 1089 u8 rf_type = RF_1T1R; 1090 u8 stbc_en = 0; 1091 u8 ldpc_en = 0; 1092 u8 tx_num = 1; 1093 u64 ra_mask = 0; 1094 bool is_vht_enable = false; 1095 bool is_support_sgi = false; 1096 1097 if (sta->vht_cap.vht_supported) { 1098 is_vht_enable = true; 1099 ra_mask |= get_vht_ra_mask(sta); 1100 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1101 stbc_en = VHT_STBC_EN; 1102 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1103 ldpc_en = VHT_LDPC_EN; 1104 } else if (sta->ht_cap.ht_supported) { 1105 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | 1106 (sta->ht_cap.mcs.rx_mask[0] << 12); 1107 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1108 stbc_en = HT_STBC_EN; 1109 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1110 ldpc_en = HT_LDPC_EN; 1111 } 1112 1113 if (efuse->hw_cap.nss == 1) 1114 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1115 1116 if (hal->current_band_type == RTW_BAND_5G) { 1117 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 1118 if (sta->vht_cap.vht_supported) { 1119 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1120 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1121 } else if (sta->ht_cap.ht_supported) { 1122 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1123 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1124 } else { 1125 wireless_set = WIRELESS_OFDM; 1126 } 1127 dm_info->rrsr_val_init = RRSR_INIT_5G; 1128 } else if (hal->current_band_type == RTW_BAND_2G) { 1129 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 1130 if (sta->vht_cap.vht_supported) { 1131 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1132 RA_MASK_OFDM_IN_VHT; 1133 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1134 WIRELESS_HT | WIRELESS_VHT; 1135 } else if (sta->ht_cap.ht_supported) { 1136 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1137 RA_MASK_OFDM_IN_HT_2G; 1138 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1139 WIRELESS_HT; 1140 } else if (sta->supp_rates[0] <= 0xf) { 1141 wireless_set = WIRELESS_CCK; 1142 } else { 1143 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1144 } 1145 dm_info->rrsr_val_init = RRSR_INIT_2G; 1146 } else { 1147 rtw_err(rtwdev, "Unknown band type\n"); 1148 wireless_set = 0; 1149 } 1150 1151 switch (sta->bandwidth) { 1152 case IEEE80211_STA_RX_BW_80: 1153 bw_mode = RTW_CHANNEL_WIDTH_80; 1154 is_support_sgi = sta->vht_cap.vht_supported && 1155 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1156 break; 1157 case IEEE80211_STA_RX_BW_40: 1158 bw_mode = RTW_CHANNEL_WIDTH_40; 1159 is_support_sgi = sta->ht_cap.ht_supported && 1160 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1161 break; 1162 default: 1163 bw_mode = RTW_CHANNEL_WIDTH_20; 1164 is_support_sgi = sta->ht_cap.ht_supported && 1165 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1166 break; 1167 } 1168 1169 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 1170 tx_num = 2; 1171 rf_type = RF_2T2R; 1172 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 1173 tx_num = 2; 1174 rf_type = RF_2T2R; 1175 } 1176 1177 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1178 1179 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable, 1180 wireless_set); 1181 1182 si->bw_mode = bw_mode; 1183 si->stbc_en = stbc_en; 1184 si->ldpc_en = ldpc_en; 1185 si->rf_type = rf_type; 1186 si->wireless_set = wireless_set; 1187 si->sgi_enable = is_support_sgi; 1188 si->vht_enable = is_vht_enable; 1189 si->ra_mask = ra_mask; 1190 si->rate_id = rate_id; 1191 1192 rtw_fw_send_ra_info(rtwdev, si); 1193 } 1194 1195 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1196 { 1197 struct rtw_chip_info *chip = rtwdev->chip; 1198 struct rtw_fw_state *fw; 1199 1200 fw = &rtwdev->fw; 1201 wait_for_completion(&fw->completion); 1202 if (!fw->firmware) 1203 return -EINVAL; 1204 1205 if (chip->wow_fw_name) { 1206 fw = &rtwdev->wow_fw; 1207 wait_for_completion(&fw->completion); 1208 if (!fw->firmware) 1209 return -EINVAL; 1210 } 1211 1212 return 0; 1213 } 1214 1215 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1216 struct rtw_fw_state *fw) 1217 { 1218 struct rtw_chip_info *chip = rtwdev->chip; 1219 1220 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1221 !fw->feature) 1222 return LPS_DEEP_MODE_NONE; 1223 1224 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1225 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1226 return LPS_DEEP_MODE_PG; 1227 1228 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1229 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1230 return LPS_DEEP_MODE_LCLK; 1231 1232 return LPS_DEEP_MODE_NONE; 1233 } 1234 1235 static int rtw_power_on(struct rtw_dev *rtwdev) 1236 { 1237 struct rtw_chip_info *chip = rtwdev->chip; 1238 struct rtw_fw_state *fw = &rtwdev->fw; 1239 bool wifi_only; 1240 int ret; 1241 1242 ret = rtw_hci_setup(rtwdev); 1243 if (ret) { 1244 rtw_err(rtwdev, "failed to setup hci\n"); 1245 goto err; 1246 } 1247 1248 /* power on MAC before firmware downloaded */ 1249 ret = rtw_mac_power_on(rtwdev); 1250 if (ret) { 1251 rtw_err(rtwdev, "failed to power on mac\n"); 1252 goto err; 1253 } 1254 1255 ret = rtw_wait_firmware_completion(rtwdev); 1256 if (ret) { 1257 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1258 goto err_off; 1259 } 1260 1261 ret = rtw_download_firmware(rtwdev, fw); 1262 if (ret) { 1263 rtw_err(rtwdev, "failed to download firmware\n"); 1264 goto err_off; 1265 } 1266 1267 /* config mac after firmware downloaded */ 1268 ret = rtw_mac_init(rtwdev); 1269 if (ret) { 1270 rtw_err(rtwdev, "failed to configure mac\n"); 1271 goto err_off; 1272 } 1273 1274 chip->ops->phy_set_param(rtwdev); 1275 1276 ret = rtw_hci_start(rtwdev); 1277 if (ret) { 1278 rtw_err(rtwdev, "failed to start hci\n"); 1279 goto err_off; 1280 } 1281 1282 /* send H2C after HCI has started */ 1283 rtw_fw_send_general_info(rtwdev); 1284 rtw_fw_send_phydm_info(rtwdev); 1285 1286 wifi_only = !rtwdev->efuse.btcoex; 1287 rtw_coex_power_on_setting(rtwdev); 1288 rtw_coex_init_hw_config(rtwdev, wifi_only); 1289 1290 return 0; 1291 1292 err_off: 1293 rtw_mac_power_off(rtwdev); 1294 1295 err: 1296 return ret; 1297 } 1298 1299 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1300 { 1301 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1302 return; 1303 1304 if (start) { 1305 rtw_fw_scan_notify(rtwdev, true); 1306 } else { 1307 reinit_completion(&rtwdev->fw_scan_density); 1308 rtw_fw_scan_notify(rtwdev, false); 1309 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1310 SCAN_NOTIFY_TIMEOUT)) 1311 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1312 } 1313 } 1314 1315 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1316 const u8 *mac_addr, bool hw_scan) 1317 { 1318 u32 config = 0; 1319 int ret = 0; 1320 1321 rtw_leave_lps(rtwdev); 1322 1323 if (hw_scan && rtwvif->net_type == RTW_NET_NO_LINK) { 1324 ret = rtw_leave_ips(rtwdev); 1325 if (ret) { 1326 rtw_err(rtwdev, "failed to leave idle state\n"); 1327 return; 1328 } 1329 } 1330 1331 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1332 config |= PORT_SET_MAC_ADDR; 1333 rtw_vif_port_config(rtwdev, rtwvif, config); 1334 1335 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1336 rtw_core_fw_scan_notify(rtwdev, true); 1337 1338 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1339 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1340 } 1341 1342 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 1343 { 1344 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 1345 u32 config = 0; 1346 1347 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1348 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1349 1350 rtw_core_fw_scan_notify(rtwdev, false); 1351 1352 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1353 config |= PORT_SET_MAC_ADDR; 1354 rtw_vif_port_config(rtwdev, rtwvif, config); 1355 1356 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1357 } 1358 1359 int rtw_core_start(struct rtw_dev *rtwdev) 1360 { 1361 int ret; 1362 1363 ret = rtw_power_on(rtwdev); 1364 if (ret) 1365 return ret; 1366 1367 rtw_sec_enable_sec_engine(rtwdev); 1368 1369 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1370 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1371 1372 /* rcr reset after powered on */ 1373 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1374 1375 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1376 RTW_WATCH_DOG_DELAY_TIME); 1377 1378 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1379 1380 return 0; 1381 } 1382 1383 static void rtw_power_off(struct rtw_dev *rtwdev) 1384 { 1385 rtw_hci_stop(rtwdev); 1386 rtw_coex_power_off_setting(rtwdev); 1387 rtw_mac_power_off(rtwdev); 1388 } 1389 1390 void rtw_core_stop(struct rtw_dev *rtwdev) 1391 { 1392 struct rtw_coex *coex = &rtwdev->coex; 1393 1394 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1395 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1396 1397 mutex_unlock(&rtwdev->mutex); 1398 1399 cancel_work_sync(&rtwdev->c2h_work); 1400 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1401 cancel_delayed_work_sync(&coex->bt_relink_work); 1402 cancel_delayed_work_sync(&coex->bt_reenable_work); 1403 cancel_delayed_work_sync(&coex->defreeze_work); 1404 cancel_delayed_work_sync(&coex->wl_remain_work); 1405 cancel_delayed_work_sync(&coex->bt_remain_work); 1406 cancel_delayed_work_sync(&coex->wl_connecting_work); 1407 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1408 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1409 1410 mutex_lock(&rtwdev->mutex); 1411 1412 rtw_power_off(rtwdev); 1413 } 1414 1415 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1416 struct ieee80211_sta_ht_cap *ht_cap) 1417 { 1418 struct rtw_efuse *efuse = &rtwdev->efuse; 1419 1420 ht_cap->ht_supported = true; 1421 ht_cap->cap = 0; 1422 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1423 IEEE80211_HT_CAP_MAX_AMSDU | 1424 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1425 1426 if (rtw_chip_has_rx_ldpc(rtwdev)) 1427 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1428 if (rtw_chip_has_tx_stbc(rtwdev)) 1429 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1430 1431 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1432 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1433 IEEE80211_HT_CAP_DSSSCCK40 | 1434 IEEE80211_HT_CAP_SGI_40; 1435 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1436 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 1437 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1438 if (efuse->hw_cap.nss > 1) { 1439 ht_cap->mcs.rx_mask[0] = 0xFF; 1440 ht_cap->mcs.rx_mask[1] = 0xFF; 1441 ht_cap->mcs.rx_mask[4] = 0x01; 1442 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1443 } else { 1444 ht_cap->mcs.rx_mask[0] = 0xFF; 1445 ht_cap->mcs.rx_mask[1] = 0x00; 1446 ht_cap->mcs.rx_mask[4] = 0x01; 1447 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1448 } 1449 } 1450 1451 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1452 struct ieee80211_sta_vht_cap *vht_cap) 1453 { 1454 struct rtw_efuse *efuse = &rtwdev->efuse; 1455 u16 mcs_map; 1456 __le16 highest; 1457 1458 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1459 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1460 return; 1461 1462 vht_cap->vht_supported = true; 1463 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1464 IEEE80211_VHT_CAP_SHORT_GI_80 | 1465 IEEE80211_VHT_CAP_RXSTBC_1 | 1466 IEEE80211_VHT_CAP_HTC_VHT | 1467 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1468 0; 1469 if (rtwdev->hal.rf_path_num > 1) 1470 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1471 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1472 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1473 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1474 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1475 1476 if (rtw_chip_has_rx_ldpc(rtwdev)) 1477 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1478 1479 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1480 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1481 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1482 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1483 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1484 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1485 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1486 if (efuse->hw_cap.nss > 1) { 1487 highest = cpu_to_le16(780); 1488 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1489 } else { 1490 highest = cpu_to_le16(390); 1491 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1492 } 1493 1494 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1495 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1496 vht_cap->vht_mcs.rx_highest = highest; 1497 vht_cap->vht_mcs.tx_highest = highest; 1498 } 1499 1500 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1501 struct rtw_chip_info *chip) 1502 { 1503 struct rtw_dev *rtwdev = hw->priv; 1504 struct ieee80211_supported_band *sband; 1505 1506 if (chip->band & RTW_BAND_2G) { 1507 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1508 if (!sband) 1509 goto err_out; 1510 if (chip->ht_supported) 1511 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1512 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1513 } 1514 1515 if (chip->band & RTW_BAND_5G) { 1516 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1517 if (!sband) 1518 goto err_out; 1519 if (chip->ht_supported) 1520 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1521 if (chip->vht_supported) 1522 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1523 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1524 } 1525 1526 return; 1527 1528 err_out: 1529 rtw_err(rtwdev, "failed to set supported band\n"); 1530 } 1531 1532 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1533 struct rtw_chip_info *chip) 1534 { 1535 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1536 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1537 } 1538 1539 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1540 struct rtw_fw_state *fw) 1541 { 1542 u32 feature; 1543 const struct rtw_fw_hdr *fw_hdr = 1544 (const struct rtw_fw_hdr *)fw->firmware->data; 1545 1546 feature = le32_to_cpu(fw_hdr->feature); 1547 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1548 } 1549 1550 static void __update_firmware_info(struct rtw_dev *rtwdev, 1551 struct rtw_fw_state *fw) 1552 { 1553 const struct rtw_fw_hdr *fw_hdr = 1554 (const struct rtw_fw_hdr *)fw->firmware->data; 1555 1556 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1557 fw->version = le16_to_cpu(fw_hdr->version); 1558 fw->sub_version = fw_hdr->subversion; 1559 fw->sub_index = fw_hdr->subindex; 1560 1561 __update_firmware_feature(rtwdev, fw); 1562 } 1563 1564 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1565 struct rtw_fw_state *fw) 1566 { 1567 struct rtw_fw_hdr_legacy *legacy = 1568 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1569 1570 fw->h2c_version = 0; 1571 fw->version = le16_to_cpu(legacy->version); 1572 fw->sub_version = legacy->subversion1; 1573 fw->sub_index = legacy->subversion2; 1574 } 1575 1576 static void update_firmware_info(struct rtw_dev *rtwdev, 1577 struct rtw_fw_state *fw) 1578 { 1579 if (rtw_chip_wcpu_11n(rtwdev)) 1580 __update_firmware_info_legacy(rtwdev, fw); 1581 else 1582 __update_firmware_info(rtwdev, fw); 1583 } 1584 1585 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1586 { 1587 struct rtw_fw_state *fw = context; 1588 struct rtw_dev *rtwdev = fw->rtwdev; 1589 1590 if (!firmware || !firmware->data) { 1591 rtw_err(rtwdev, "failed to request firmware\n"); 1592 complete_all(&fw->completion); 1593 return; 1594 } 1595 1596 fw->firmware = firmware; 1597 update_firmware_info(rtwdev, fw); 1598 complete_all(&fw->completion); 1599 1600 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1601 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1602 } 1603 1604 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1605 { 1606 const char *fw_name; 1607 struct rtw_fw_state *fw; 1608 int ret; 1609 1610 switch (type) { 1611 case RTW_WOWLAN_FW: 1612 fw = &rtwdev->wow_fw; 1613 fw_name = rtwdev->chip->wow_fw_name; 1614 break; 1615 1616 case RTW_NORMAL_FW: 1617 fw = &rtwdev->fw; 1618 fw_name = rtwdev->chip->fw_name; 1619 break; 1620 1621 default: 1622 rtw_warn(rtwdev, "unsupported firmware type\n"); 1623 return -ENOENT; 1624 } 1625 1626 fw->rtwdev = rtwdev; 1627 init_completion(&fw->completion); 1628 1629 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1630 GFP_KERNEL, fw, rtw_load_firmware_cb); 1631 if (ret) { 1632 rtw_err(rtwdev, "failed to async firmware request\n"); 1633 return ret; 1634 } 1635 1636 return 0; 1637 } 1638 1639 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1640 { 1641 struct rtw_chip_info *chip = rtwdev->chip; 1642 struct rtw_hal *hal = &rtwdev->hal; 1643 struct rtw_efuse *efuse = &rtwdev->efuse; 1644 1645 switch (rtw_hci_type(rtwdev)) { 1646 case RTW_HCI_TYPE_PCIE: 1647 rtwdev->hci.rpwm_addr = 0x03d9; 1648 rtwdev->hci.cpwm_addr = 0x03da; 1649 break; 1650 default: 1651 rtw_err(rtwdev, "unsupported hci type\n"); 1652 return -EINVAL; 1653 } 1654 1655 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1656 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1657 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1658 if (hal->chip_version & BIT_RF_TYPE_ID) { 1659 hal->rf_type = RF_2T2R; 1660 hal->rf_path_num = 2; 1661 hal->antenna_tx = BB_PATH_AB; 1662 hal->antenna_rx = BB_PATH_AB; 1663 } else { 1664 hal->rf_type = RF_1T1R; 1665 hal->rf_path_num = 1; 1666 hal->antenna_tx = BB_PATH_A; 1667 hal->antenna_rx = BB_PATH_A; 1668 } 1669 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1670 hal->rf_path_num; 1671 1672 efuse->physical_size = chip->phy_efuse_size; 1673 efuse->logical_size = chip->log_efuse_size; 1674 efuse->protect_size = chip->ptct_efuse_size; 1675 1676 /* default use ack */ 1677 rtwdev->hal.rcr |= BIT_VHT_DACK; 1678 1679 hal->bfee_sts_cap = 3; 1680 1681 return 0; 1682 } 1683 1684 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1685 { 1686 struct rtw_fw_state *fw = &rtwdev->fw; 1687 int ret; 1688 1689 ret = rtw_hci_setup(rtwdev); 1690 if (ret) { 1691 rtw_err(rtwdev, "failed to setup hci\n"); 1692 goto err; 1693 } 1694 1695 ret = rtw_mac_power_on(rtwdev); 1696 if (ret) { 1697 rtw_err(rtwdev, "failed to power on mac\n"); 1698 goto err; 1699 } 1700 1701 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1702 1703 wait_for_completion(&fw->completion); 1704 if (!fw->firmware) { 1705 ret = -EINVAL; 1706 rtw_err(rtwdev, "failed to load firmware\n"); 1707 goto err; 1708 } 1709 1710 ret = rtw_download_firmware(rtwdev, fw); 1711 if (ret) { 1712 rtw_err(rtwdev, "failed to download firmware\n"); 1713 goto err_off; 1714 } 1715 1716 return 0; 1717 1718 err_off: 1719 rtw_mac_power_off(rtwdev); 1720 1721 err: 1722 return ret; 1723 } 1724 1725 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1726 { 1727 struct rtw_efuse *efuse = &rtwdev->efuse; 1728 u8 hw_feature[HW_FEATURE_LEN]; 1729 u8 id; 1730 u8 bw; 1731 int i; 1732 1733 id = rtw_read8(rtwdev, REG_C2HEVT); 1734 if (id != C2H_HW_FEATURE_REPORT) { 1735 rtw_err(rtwdev, "failed to read hw feature report\n"); 1736 return -EBUSY; 1737 } 1738 1739 for (i = 0; i < HW_FEATURE_LEN; i++) 1740 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1741 1742 rtw_write8(rtwdev, REG_C2HEVT, 0); 1743 1744 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1745 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1746 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1747 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1748 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1749 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1750 1751 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1752 1753 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1754 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1755 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1756 1757 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1758 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1759 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1760 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1761 1762 return 0; 1763 } 1764 1765 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1766 { 1767 rtw_hci_stop(rtwdev); 1768 rtw_mac_power_off(rtwdev); 1769 } 1770 1771 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1772 { 1773 struct rtw_efuse *efuse = &rtwdev->efuse; 1774 int ret; 1775 1776 mutex_lock(&rtwdev->mutex); 1777 1778 /* power on mac to read efuse */ 1779 ret = rtw_chip_efuse_enable(rtwdev); 1780 if (ret) 1781 goto out_unlock; 1782 1783 ret = rtw_parse_efuse_map(rtwdev); 1784 if (ret) 1785 goto out_disable; 1786 1787 ret = rtw_dump_hw_feature(rtwdev); 1788 if (ret) 1789 goto out_disable; 1790 1791 ret = rtw_check_supported_rfe(rtwdev); 1792 if (ret) 1793 goto out_disable; 1794 1795 if (efuse->crystal_cap == 0xff) 1796 efuse->crystal_cap = 0; 1797 if (efuse->pa_type_2g == 0xff) 1798 efuse->pa_type_2g = 0; 1799 if (efuse->pa_type_5g == 0xff) 1800 efuse->pa_type_5g = 0; 1801 if (efuse->lna_type_2g == 0xff) 1802 efuse->lna_type_2g = 0; 1803 if (efuse->lna_type_5g == 0xff) 1804 efuse->lna_type_5g = 0; 1805 if (efuse->channel_plan == 0xff) 1806 efuse->channel_plan = 0x7f; 1807 if (efuse->rf_board_option == 0xff) 1808 efuse->rf_board_option = 0; 1809 if (efuse->bt_setting & BIT(0)) 1810 efuse->share_ant = true; 1811 if (efuse->regd == 0xff) 1812 efuse->regd = 0; 1813 if (efuse->tx_bb_swing_setting_2g == 0xff) 1814 efuse->tx_bb_swing_setting_2g = 0; 1815 if (efuse->tx_bb_swing_setting_5g == 0xff) 1816 efuse->tx_bb_swing_setting_5g = 0; 1817 1818 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1819 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1820 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1821 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1822 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1823 1824 out_disable: 1825 rtw_chip_efuse_disable(rtwdev); 1826 1827 out_unlock: 1828 mutex_unlock(&rtwdev->mutex); 1829 return ret; 1830 } 1831 1832 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1833 { 1834 struct rtw_hal *hal = &rtwdev->hal; 1835 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1836 1837 if (!rfe_def) 1838 return -ENODEV; 1839 1840 rtw_phy_setup_phy_cond(rtwdev, 0); 1841 1842 rtw_phy_init_tx_power(rtwdev); 1843 if (rfe_def->agc_btg_tbl) 1844 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1845 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1846 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1847 rtw_phy_tx_power_by_rate_config(hal); 1848 rtw_phy_tx_power_limit_config(hal); 1849 1850 return 0; 1851 } 1852 1853 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1854 { 1855 int ret; 1856 1857 ret = rtw_chip_parameter_setup(rtwdev); 1858 if (ret) { 1859 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1860 goto err_out; 1861 } 1862 1863 ret = rtw_chip_efuse_info_setup(rtwdev); 1864 if (ret) { 1865 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1866 goto err_out; 1867 } 1868 1869 ret = rtw_chip_board_info_setup(rtwdev); 1870 if (ret) { 1871 rtw_err(rtwdev, "failed to setup chip board info\n"); 1872 goto err_out; 1873 } 1874 1875 return 0; 1876 1877 err_out: 1878 return ret; 1879 } 1880 EXPORT_SYMBOL(rtw_chip_info_setup); 1881 1882 static void rtw_stats_init(struct rtw_dev *rtwdev) 1883 { 1884 struct rtw_traffic_stats *stats = &rtwdev->stats; 1885 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1886 int i; 1887 1888 ewma_tp_init(&stats->tx_ewma_tp); 1889 ewma_tp_init(&stats->rx_ewma_tp); 1890 1891 for (i = 0; i < RTW_EVM_NUM; i++) 1892 ewma_evm_init(&dm_info->ewma_evm[i]); 1893 for (i = 0; i < RTW_SNR_NUM; i++) 1894 ewma_snr_init(&dm_info->ewma_snr[i]); 1895 } 1896 1897 int rtw_core_init(struct rtw_dev *rtwdev) 1898 { 1899 struct rtw_chip_info *chip = rtwdev->chip; 1900 struct rtw_coex *coex = &rtwdev->coex; 1901 int ret; 1902 1903 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1904 INIT_LIST_HEAD(&rtwdev->txqs); 1905 1906 timer_setup(&rtwdev->tx_report.purge_timer, 1907 rtw_tx_report_purge_timer, 0); 1908 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 1909 1910 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1911 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1912 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1913 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1914 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 1915 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 1916 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 1917 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 1918 rtw_coex_bt_multi_link_remain_work); 1919 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 1920 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 1921 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1922 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 1923 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1924 skb_queue_head_init(&rtwdev->c2h_queue); 1925 skb_queue_head_init(&rtwdev->coex.queue); 1926 skb_queue_head_init(&rtwdev->tx_report.queue); 1927 1928 spin_lock_init(&rtwdev->rf_lock); 1929 spin_lock_init(&rtwdev->h2c.lock); 1930 spin_lock_init(&rtwdev->txq_lock); 1931 spin_lock_init(&rtwdev->tx_report.q_lock); 1932 1933 mutex_init(&rtwdev->mutex); 1934 mutex_init(&rtwdev->coex.mutex); 1935 mutex_init(&rtwdev->hal.tx_power_mutex); 1936 1937 init_waitqueue_head(&rtwdev->coex.wait); 1938 init_completion(&rtwdev->lps_leave_check); 1939 init_completion(&rtwdev->fw_scan_density); 1940 1941 rtwdev->sec.total_cam_num = 32; 1942 rtwdev->hal.current_channel = 1; 1943 rtwdev->dm_info.fix_rate = U8_MAX; 1944 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 1945 1946 rtw_stats_init(rtwdev); 1947 1948 /* default rx filter setting */ 1949 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 1950 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 1951 BIT_AB | BIT_AM | BIT_APM; 1952 1953 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 1954 if (ret) { 1955 rtw_warn(rtwdev, "no firmware loaded\n"); 1956 return ret; 1957 } 1958 1959 if (chip->wow_fw_name) { 1960 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 1961 if (ret) { 1962 rtw_warn(rtwdev, "no wow firmware loaded\n"); 1963 wait_for_completion(&rtwdev->fw.completion); 1964 if (rtwdev->fw.firmware) 1965 release_firmware(rtwdev->fw.firmware); 1966 return ret; 1967 } 1968 } 1969 1970 return 0; 1971 } 1972 EXPORT_SYMBOL(rtw_core_init); 1973 1974 void rtw_core_deinit(struct rtw_dev *rtwdev) 1975 { 1976 struct rtw_fw_state *fw = &rtwdev->fw; 1977 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 1978 struct rtw_rsvd_page *rsvd_pkt, *tmp; 1979 unsigned long flags; 1980 1981 rtw_wait_firmware_completion(rtwdev); 1982 1983 if (fw->firmware) 1984 release_firmware(fw->firmware); 1985 1986 if (wow_fw->firmware) 1987 release_firmware(wow_fw->firmware); 1988 1989 destroy_workqueue(rtwdev->tx_wq); 1990 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 1991 skb_queue_purge(&rtwdev->tx_report.queue); 1992 skb_queue_purge(&rtwdev->coex.queue); 1993 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 1994 1995 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 1996 build_list) { 1997 list_del(&rsvd_pkt->build_list); 1998 kfree(rsvd_pkt); 1999 } 2000 2001 mutex_destroy(&rtwdev->mutex); 2002 mutex_destroy(&rtwdev->coex.mutex); 2003 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2004 } 2005 EXPORT_SYMBOL(rtw_core_deinit); 2006 2007 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2008 { 2009 struct rtw_hal *hal = &rtwdev->hal; 2010 int max_tx_headroom = 0; 2011 int ret; 2012 2013 /* TODO: USB & SDIO may need extra room? */ 2014 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2015 2016 hw->extra_tx_headroom = max_tx_headroom; 2017 hw->queues = IEEE80211_NUM_ACS; 2018 hw->txq_data_size = sizeof(struct rtw_txq); 2019 hw->sta_data_size = sizeof(struct rtw_sta_info); 2020 hw->vif_data_size = sizeof(struct rtw_vif); 2021 2022 ieee80211_hw_set(hw, SIGNAL_DBM); 2023 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2024 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2025 ieee80211_hw_set(hw, MFP_CAPABLE); 2026 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2027 ieee80211_hw_set(hw, SUPPORTS_PS); 2028 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2029 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2030 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2031 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2032 ieee80211_hw_set(hw, TX_AMSDU); 2033 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2034 2035 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2036 BIT(NL80211_IFTYPE_AP) | 2037 BIT(NL80211_IFTYPE_ADHOC) | 2038 BIT(NL80211_IFTYPE_MESH_POINT); 2039 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2040 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2041 2042 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2043 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2044 2045 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2046 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2047 hw->wiphy->max_scan_ie_len = RTW_SCAN_MAX_IE_LEN; 2048 2049 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2050 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2051 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2052 2053 #ifdef CONFIG_PM 2054 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2055 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2056 #endif 2057 rtw_set_supported_band(hw, rtwdev->chip); 2058 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2059 2060 hw->wiphy->sar_capa = &rtw_sar_capa; 2061 2062 ret = rtw_regd_init(rtwdev); 2063 if (ret) { 2064 rtw_err(rtwdev, "failed to init regd\n"); 2065 return ret; 2066 } 2067 2068 ret = ieee80211_register_hw(hw); 2069 if (ret) { 2070 rtw_err(rtwdev, "failed to register hw\n"); 2071 return ret; 2072 } 2073 2074 ret = rtw_regd_hint(rtwdev); 2075 if (ret) { 2076 rtw_err(rtwdev, "failed to hint regd\n"); 2077 return ret; 2078 } 2079 2080 rtw_debugfs_init(rtwdev); 2081 2082 rtwdev->bf_info.bfer_mu_cnt = 0; 2083 rtwdev->bf_info.bfer_su_cnt = 0; 2084 2085 return 0; 2086 } 2087 EXPORT_SYMBOL(rtw_register_hw); 2088 2089 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2090 { 2091 struct rtw_chip_info *chip = rtwdev->chip; 2092 2093 ieee80211_unregister_hw(hw); 2094 rtw_unset_supported_band(hw, chip); 2095 } 2096 EXPORT_SYMBOL(rtw_unregister_hw); 2097 2098 MODULE_AUTHOR("Realtek Corporation"); 2099 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2100 MODULE_LICENSE("Dual BSD/GPL"); 2101