1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 22 bool rtw_disable_lps_deep_mode; 23 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 24 bool rtw_bf_support = true; 25 unsigned int rtw_debug_mask; 26 EXPORT_SYMBOL(rtw_debug_mask); 27 /* EDCCA is enabled during normal behavior. For debugging purpose in 28 * a noisy environment, it can be disabled via edcca debugfs. Because 29 * all rtw88 devices will probably be affected if environment is noisy, 30 * rtw_edcca_enabled is just declared by driver instead of by device. 31 * So, turning it off will take effect for all rtw88 devices before 32 * there is a tough reason to maintain rtw_edcca_enabled by device. 33 */ 34 bool rtw_edcca_enabled = true; 35 36 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 37 module_param_named(support_bf, rtw_bf_support, bool, 0644); 38 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 39 40 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 41 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 42 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 43 44 static struct ieee80211_channel rtw_channeltable_2g[] = { 45 {.center_freq = 2412, .hw_value = 1,}, 46 {.center_freq = 2417, .hw_value = 2,}, 47 {.center_freq = 2422, .hw_value = 3,}, 48 {.center_freq = 2427, .hw_value = 4,}, 49 {.center_freq = 2432, .hw_value = 5,}, 50 {.center_freq = 2437, .hw_value = 6,}, 51 {.center_freq = 2442, .hw_value = 7,}, 52 {.center_freq = 2447, .hw_value = 8,}, 53 {.center_freq = 2452, .hw_value = 9,}, 54 {.center_freq = 2457, .hw_value = 10,}, 55 {.center_freq = 2462, .hw_value = 11,}, 56 {.center_freq = 2467, .hw_value = 12,}, 57 {.center_freq = 2472, .hw_value = 13,}, 58 {.center_freq = 2484, .hw_value = 14,}, 59 }; 60 61 static struct ieee80211_channel rtw_channeltable_5g[] = { 62 {.center_freq = 5180, .hw_value = 36,}, 63 {.center_freq = 5200, .hw_value = 40,}, 64 {.center_freq = 5220, .hw_value = 44,}, 65 {.center_freq = 5240, .hw_value = 48,}, 66 {.center_freq = 5260, .hw_value = 52,}, 67 {.center_freq = 5280, .hw_value = 56,}, 68 {.center_freq = 5300, .hw_value = 60,}, 69 {.center_freq = 5320, .hw_value = 64,}, 70 {.center_freq = 5500, .hw_value = 100,}, 71 {.center_freq = 5520, .hw_value = 104,}, 72 {.center_freq = 5540, .hw_value = 108,}, 73 {.center_freq = 5560, .hw_value = 112,}, 74 {.center_freq = 5580, .hw_value = 116,}, 75 {.center_freq = 5600, .hw_value = 120,}, 76 {.center_freq = 5620, .hw_value = 124,}, 77 {.center_freq = 5640, .hw_value = 128,}, 78 {.center_freq = 5660, .hw_value = 132,}, 79 {.center_freq = 5680, .hw_value = 136,}, 80 {.center_freq = 5700, .hw_value = 140,}, 81 {.center_freq = 5720, .hw_value = 144,}, 82 {.center_freq = 5745, .hw_value = 149,}, 83 {.center_freq = 5765, .hw_value = 153,}, 84 {.center_freq = 5785, .hw_value = 157,}, 85 {.center_freq = 5805, .hw_value = 161,}, 86 {.center_freq = 5825, .hw_value = 165, 87 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 88 }; 89 90 static struct ieee80211_rate rtw_ratetable[] = { 91 {.bitrate = 10, .hw_value = 0x00,}, 92 {.bitrate = 20, .hw_value = 0x01,}, 93 {.bitrate = 55, .hw_value = 0x02,}, 94 {.bitrate = 110, .hw_value = 0x03,}, 95 {.bitrate = 60, .hw_value = 0x04,}, 96 {.bitrate = 90, .hw_value = 0x05,}, 97 {.bitrate = 120, .hw_value = 0x06,}, 98 {.bitrate = 180, .hw_value = 0x07,}, 99 {.bitrate = 240, .hw_value = 0x08,}, 100 {.bitrate = 360, .hw_value = 0x09,}, 101 {.bitrate = 480, .hw_value = 0x0a,}, 102 {.bitrate = 540, .hw_value = 0x0b,}, 103 }; 104 105 u16 rtw_desc_to_bitrate(u8 desc_rate) 106 { 107 struct ieee80211_rate rate; 108 109 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 110 return 0; 111 112 rate = rtw_ratetable[desc_rate]; 113 114 return rate.bitrate; 115 } 116 117 static struct ieee80211_supported_band rtw_band_2ghz = { 118 .band = NL80211_BAND_2GHZ, 119 120 .channels = rtw_channeltable_2g, 121 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 122 123 .bitrates = rtw_ratetable, 124 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 125 126 .ht_cap = {0}, 127 .vht_cap = {0}, 128 }; 129 130 static struct ieee80211_supported_band rtw_band_5ghz = { 131 .band = NL80211_BAND_5GHZ, 132 133 .channels = rtw_channeltable_5g, 134 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 135 136 /* 5G has no CCK rates */ 137 .bitrates = rtw_ratetable + 4, 138 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 139 140 .ht_cap = {0}, 141 .vht_cap = {0}, 142 }; 143 144 struct rtw_watch_dog_iter_data { 145 struct rtw_dev *rtwdev; 146 struct rtw_vif *rtwvif; 147 }; 148 149 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 150 { 151 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 152 u8 fix_rate_enable = 0; 153 u8 new_csi_rate_idx; 154 155 if (rtwvif->bfee.role != RTW_BFEE_SU && 156 rtwvif->bfee.role != RTW_BFEE_MU) 157 return; 158 159 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 160 bf_info->cur_csi_rpt_rate, 161 fix_rate_enable, &new_csi_rate_idx); 162 163 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 164 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 165 } 166 167 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 168 struct ieee80211_vif *vif) 169 { 170 struct rtw_watch_dog_iter_data *iter_data = data; 171 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 172 173 if (vif->type == NL80211_IFTYPE_STATION) 174 if (vif->bss_conf.assoc) 175 iter_data->rtwvif = rtwvif; 176 177 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 178 179 rtwvif->stats.tx_unicast = 0; 180 rtwvif->stats.rx_unicast = 0; 181 rtwvif->stats.tx_cnt = 0; 182 rtwvif->stats.rx_cnt = 0; 183 } 184 185 /* process TX/RX statistics periodically for hardware, 186 * the information helps hardware to enhance performance 187 */ 188 static void rtw_watch_dog_work(struct work_struct *work) 189 { 190 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 191 watch_dog_work.work); 192 struct rtw_traffic_stats *stats = &rtwdev->stats; 193 struct rtw_watch_dog_iter_data data = {}; 194 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 195 bool ps_active; 196 197 mutex_lock(&rtwdev->mutex); 198 199 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 200 goto unlock; 201 202 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 203 RTW_WATCH_DOG_DELAY_TIME); 204 205 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 206 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 207 else 208 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 209 210 rtw_coex_wl_status_check(rtwdev); 211 rtw_coex_query_bt_hid_list(rtwdev); 212 213 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 214 rtw_coex_wl_status_change_notify(rtwdev, 0); 215 216 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 217 stats->rx_cnt > RTW_LPS_THRESHOLD) 218 ps_active = true; 219 else 220 ps_active = false; 221 222 ewma_tp_add(&stats->tx_ewma_tp, 223 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 224 ewma_tp_add(&stats->rx_ewma_tp, 225 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 226 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 227 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 228 229 /* reset tx/rx statictics */ 230 stats->tx_unicast = 0; 231 stats->rx_unicast = 0; 232 stats->tx_cnt = 0; 233 stats->rx_cnt = 0; 234 235 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 236 goto unlock; 237 238 /* make sure BB/RF is working for dynamic mech */ 239 rtw_leave_lps(rtwdev); 240 241 rtw_phy_dynamic_mechanism(rtwdev); 242 243 data.rtwdev = rtwdev; 244 /* use atomic version to avoid taking local->iflist_mtx mutex */ 245 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 246 247 /* fw supports only one station associated to enter lps, if there are 248 * more than two stations associated to the AP, then we can not enter 249 * lps, because fw does not handle the overlapped beacon interval 250 * 251 * mac80211 should iterate vifs and determine if driver can enter 252 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 253 * get that vif and check if device is having traffic more than the 254 * threshold. 255 */ 256 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 257 !rtwdev->beacon_loss) 258 rtw_enter_lps(rtwdev, data.rtwvif->port); 259 260 rtwdev->watch_dog_cnt++; 261 262 unlock: 263 mutex_unlock(&rtwdev->mutex); 264 } 265 266 static void rtw_c2h_work(struct work_struct *work) 267 { 268 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 269 struct sk_buff *skb, *tmp; 270 271 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 272 skb_unlink(skb, &rtwdev->c2h_queue); 273 rtw_fw_c2h_cmd_handle(rtwdev, skb); 274 dev_kfree_skb_any(skb); 275 } 276 } 277 278 static void rtw_ips_work(struct work_struct *work) 279 { 280 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 281 282 mutex_lock(&rtwdev->mutex); 283 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 284 rtw_enter_ips(rtwdev); 285 mutex_unlock(&rtwdev->mutex); 286 } 287 288 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 289 { 290 unsigned long mac_id; 291 292 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 293 if (mac_id < RTW_MAX_MAC_ID_NUM) 294 set_bit(mac_id, rtwdev->mac_id_map); 295 296 return mac_id; 297 } 298 299 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 300 struct ieee80211_vif *vif) 301 { 302 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 303 int i; 304 305 si->mac_id = rtw_acquire_macid(rtwdev); 306 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 307 return -ENOSPC; 308 309 si->sta = sta; 310 si->vif = vif; 311 si->init_ra_lv = 1; 312 ewma_rssi_init(&si->avg_rssi); 313 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 314 rtw_txq_init(rtwdev, sta->txq[i]); 315 316 rtw_update_sta_info(rtwdev, si, true); 317 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 318 319 rtwdev->sta_cnt++; 320 rtwdev->beacon_loss = false; 321 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 322 sta->addr, si->mac_id); 323 324 return 0; 325 } 326 327 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 328 bool fw_exist) 329 { 330 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 331 int i; 332 333 rtw_release_macid(rtwdev, si->mac_id); 334 if (fw_exist) 335 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 336 337 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 338 rtw_txq_cleanup(rtwdev, sta->txq[i]); 339 340 kfree(si->mask); 341 342 rtwdev->sta_cnt--; 343 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 344 sta->addr, si->mac_id); 345 } 346 347 struct rtw_fwcd_hdr { 348 u32 item; 349 u32 size; 350 u32 padding1; 351 u32 padding2; 352 } __packed; 353 354 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 355 { 356 struct rtw_chip_info *chip = rtwdev->chip; 357 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 358 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 359 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 360 u8 i; 361 362 if (segs) { 363 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 364 365 for (i = 0; i < segs->num; i++) 366 prep_size += segs->segs[i]; 367 } 368 369 desc->data = vmalloc(prep_size); 370 if (!desc->data) 371 return -ENOMEM; 372 373 desc->size = prep_size; 374 desc->next = desc->data; 375 376 return 0; 377 } 378 379 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 380 { 381 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 382 struct rtw_fwcd_hdr *hdr; 383 u8 *next; 384 385 if (!desc->data) { 386 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 387 return NULL; 388 } 389 390 next = desc->next + sizeof(struct rtw_fwcd_hdr); 391 if (next - desc->data + size > desc->size) { 392 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 393 return NULL; 394 } 395 396 hdr = (struct rtw_fwcd_hdr *)(desc->next); 397 hdr->item = item; 398 hdr->size = size; 399 hdr->padding1 = 0x01234567; 400 hdr->padding2 = 0x89abcdef; 401 desc->next = next + size; 402 403 return next; 404 } 405 406 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 407 { 408 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 409 410 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 411 412 /* Data will be freed after lifetime of device coredump. After calling 413 * dev_coredump, data is supposed to be handled by the device coredump 414 * framework. Note that a new dump will be discarded if a previous one 415 * hasn't been released yet. 416 */ 417 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 418 } 419 420 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 421 { 422 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 423 424 if (free_self) { 425 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 426 vfree(desc->data); 427 } 428 429 desc->data = NULL; 430 desc->next = NULL; 431 } 432 433 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 434 { 435 u32 size = rtwdev->chip->fw_rxff_size; 436 u32 *buf; 437 u8 seq; 438 439 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 440 if (!buf) 441 return -ENOMEM; 442 443 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 444 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 445 return -EINVAL; 446 } 447 448 if (GET_FW_DUMP_LEN(buf) == 0) { 449 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 450 return -EINVAL; 451 } 452 453 seq = GET_FW_DUMP_SEQ(buf); 454 if (seq > 0) { 455 rtw_dbg(rtwdev, RTW_DBG_FW, 456 "fw crash dump's seq is wrong: %d\n", seq); 457 return -EINVAL; 458 } 459 460 return 0; 461 } 462 463 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 464 u32 fwcd_item) 465 { 466 u32 rxff = rtwdev->chip->fw_rxff_size; 467 u32 dump_size, done_size = 0; 468 u8 *buf; 469 int ret; 470 471 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 472 if (!buf) 473 return -ENOMEM; 474 475 while (size) { 476 dump_size = size > rxff ? rxff : size; 477 478 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 479 dump_size); 480 if (ret) { 481 rtw_err(rtwdev, 482 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 483 ocp_src, done_size); 484 return ret; 485 } 486 487 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 488 dump_size, (u32 *)(buf + done_size)); 489 if (ret) { 490 rtw_err(rtwdev, 491 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 492 ocp_src, done_size); 493 return ret; 494 } 495 496 size -= dump_size; 497 done_size += dump_size; 498 } 499 500 return 0; 501 } 502 EXPORT_SYMBOL(rtw_dump_fw); 503 504 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 505 { 506 u8 *buf; 507 u32 i; 508 509 if (addr & 0x3) { 510 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 511 return -EINVAL; 512 } 513 514 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 515 if (!buf) 516 return -ENOMEM; 517 518 for (i = 0; i < size; i += 4) 519 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 520 521 return 0; 522 } 523 EXPORT_SYMBOL(rtw_dump_reg); 524 525 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 526 struct ieee80211_bss_conf *conf) 527 { 528 if (conf && conf->assoc) { 529 rtwvif->aid = conf->aid; 530 rtwvif->net_type = RTW_NET_MGD_LINKED; 531 } else { 532 rtwvif->aid = 0; 533 rtwvif->net_type = RTW_NET_NO_LINK; 534 } 535 } 536 537 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 538 struct ieee80211_vif *vif, 539 struct ieee80211_sta *sta, 540 struct ieee80211_key_conf *key, 541 void *data) 542 { 543 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 544 struct rtw_sec_desc *sec = &rtwdev->sec; 545 546 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 547 } 548 549 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 550 { 551 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 552 553 if (rtwdev->sta_cnt == 0) { 554 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 555 return; 556 } 557 rtw_sta_remove(rtwdev, sta, false); 558 } 559 560 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 561 { 562 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 563 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 564 565 rtw_bf_disassoc(rtwdev, vif, NULL); 566 rtw_vif_assoc_changed(rtwvif, NULL); 567 rtw_txq_cleanup(rtwdev, vif->txq); 568 } 569 570 void rtw_fw_recovery(struct rtw_dev *rtwdev) 571 { 572 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 573 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 574 } 575 576 static void __fw_recovery_work(struct rtw_dev *rtwdev) 577 { 578 int ret = 0; 579 580 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 581 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 582 583 ret = rtw_fwcd_prep(rtwdev); 584 if (ret) 585 goto free; 586 ret = rtw_fw_dump_crash_log(rtwdev); 587 if (ret) 588 goto free; 589 ret = rtw_chip_dump_fw_crash(rtwdev); 590 if (ret) 591 goto free; 592 593 rtw_fwcd_dump(rtwdev); 594 free: 595 rtw_fwcd_free(rtwdev, !!ret); 596 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 597 598 WARN(1, "firmware crash, start reset and recover\n"); 599 600 rcu_read_lock(); 601 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 602 rcu_read_unlock(); 603 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 604 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 605 rtw_enter_ips(rtwdev); 606 } 607 608 static void rtw_fw_recovery_work(struct work_struct *work) 609 { 610 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 611 fw_recovery_work); 612 613 mutex_lock(&rtwdev->mutex); 614 __fw_recovery_work(rtwdev); 615 mutex_unlock(&rtwdev->mutex); 616 617 ieee80211_restart_hw(rtwdev->hw); 618 } 619 620 struct rtw_txq_ba_iter_data { 621 }; 622 623 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 624 { 625 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 626 int ret; 627 u8 tid; 628 629 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 630 while (tid != IEEE80211_NUM_TIDS) { 631 clear_bit(tid, si->tid_ba); 632 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 633 if (ret == -EINVAL) { 634 struct ieee80211_txq *txq; 635 struct rtw_txq *rtwtxq; 636 637 txq = sta->txq[tid]; 638 rtwtxq = (struct rtw_txq *)txq->drv_priv; 639 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 640 } 641 642 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 643 } 644 } 645 646 static void rtw_txq_ba_work(struct work_struct *work) 647 { 648 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 649 struct rtw_txq_ba_iter_data data; 650 651 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 652 } 653 654 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 655 { 656 if (IS_CH_2G_BAND(channel)) 657 pkt_stat->band = NL80211_BAND_2GHZ; 658 else if (IS_CH_5G_BAND(channel)) 659 pkt_stat->band = NL80211_BAND_5GHZ; 660 else 661 return; 662 663 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 664 } 665 EXPORT_SYMBOL(rtw_set_rx_freq_band); 666 667 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 668 { 669 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 670 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 671 } 672 673 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 674 struct rtw_channel_params *chan_params) 675 { 676 struct ieee80211_channel *channel = chandef->chan; 677 enum nl80211_chan_width width = chandef->width; 678 u8 *cch_by_bw = chan_params->cch_by_bw; 679 u32 primary_freq, center_freq; 680 u8 center_chan; 681 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 682 u8 primary_chan_idx = 0; 683 u8 i; 684 685 center_chan = channel->hw_value; 686 primary_freq = channel->center_freq; 687 center_freq = chandef->center_freq1; 688 689 /* assign the center channel used while 20M bw is selected */ 690 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 691 692 switch (width) { 693 case NL80211_CHAN_WIDTH_20_NOHT: 694 case NL80211_CHAN_WIDTH_20: 695 bandwidth = RTW_CHANNEL_WIDTH_20; 696 primary_chan_idx = RTW_SC_DONT_CARE; 697 break; 698 case NL80211_CHAN_WIDTH_40: 699 bandwidth = RTW_CHANNEL_WIDTH_40; 700 if (primary_freq > center_freq) { 701 primary_chan_idx = RTW_SC_20_UPPER; 702 center_chan -= 2; 703 } else { 704 primary_chan_idx = RTW_SC_20_LOWER; 705 center_chan += 2; 706 } 707 break; 708 case NL80211_CHAN_WIDTH_80: 709 bandwidth = RTW_CHANNEL_WIDTH_80; 710 if (primary_freq > center_freq) { 711 if (primary_freq - center_freq == 10) { 712 primary_chan_idx = RTW_SC_20_UPPER; 713 center_chan -= 2; 714 } else { 715 primary_chan_idx = RTW_SC_20_UPMOST; 716 center_chan -= 6; 717 } 718 /* assign the center channel used 719 * while 40M bw is selected 720 */ 721 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 722 } else { 723 if (center_freq - primary_freq == 10) { 724 primary_chan_idx = RTW_SC_20_LOWER; 725 center_chan += 2; 726 } else { 727 primary_chan_idx = RTW_SC_20_LOWEST; 728 center_chan += 6; 729 } 730 /* assign the center channel used 731 * while 40M bw is selected 732 */ 733 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 734 } 735 break; 736 default: 737 center_chan = 0; 738 break; 739 } 740 741 chan_params->center_chan = center_chan; 742 chan_params->bandwidth = bandwidth; 743 chan_params->primary_chan_idx = primary_chan_idx; 744 745 /* assign the center channel used while current bw is selected */ 746 cch_by_bw[bandwidth] = center_chan; 747 748 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 749 cch_by_bw[i] = 0; 750 } 751 752 void rtw_set_channel(struct rtw_dev *rtwdev) 753 { 754 struct ieee80211_hw *hw = rtwdev->hw; 755 struct rtw_hal *hal = &rtwdev->hal; 756 struct rtw_chip_info *chip = rtwdev->chip; 757 struct rtw_channel_params ch_param; 758 u8 center_chan, bandwidth, primary_chan_idx; 759 u8 i; 760 761 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 762 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 763 return; 764 765 center_chan = ch_param.center_chan; 766 bandwidth = ch_param.bandwidth; 767 primary_chan_idx = ch_param.primary_chan_idx; 768 769 hal->current_band_width = bandwidth; 770 hal->current_channel = center_chan; 771 hal->current_primary_channel_index = primary_chan_idx; 772 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 773 774 switch (center_chan) { 775 case 1 ... 14: 776 hal->sar_band = RTW_SAR_BAND_0; 777 break; 778 case 36 ... 64: 779 hal->sar_band = RTW_SAR_BAND_1; 780 break; 781 case 100 ... 144: 782 hal->sar_band = RTW_SAR_BAND_3; 783 break; 784 case 149 ... 177: 785 hal->sar_band = RTW_SAR_BAND_4; 786 break; 787 default: 788 WARN(1, "unknown ch(%u) to SAR band\n", center_chan); 789 hal->sar_band = RTW_SAR_BAND_0; 790 break; 791 } 792 793 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 794 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 795 796 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 797 798 if (hal->current_band_type == RTW_BAND_5G) { 799 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 800 } else { 801 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 802 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 803 else 804 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 805 } 806 807 rtw_phy_set_tx_power_level(rtwdev, center_chan); 808 809 /* if the channel isn't set for scanning, we will do RF calibration 810 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 811 * during scanning on each channel takes too long. 812 */ 813 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 814 rtwdev->need_rfk = true; 815 } 816 817 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 818 { 819 struct rtw_chip_info *chip = rtwdev->chip; 820 821 if (rtwdev->need_rfk) { 822 rtwdev->need_rfk = false; 823 chip->ops->phy_calibration(rtwdev); 824 } 825 } 826 827 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 828 { 829 int i; 830 831 for (i = 0; i < ETH_ALEN; i++) 832 rtw_write8(rtwdev, start + i, addr[i]); 833 } 834 835 void rtw_vif_port_config(struct rtw_dev *rtwdev, 836 struct rtw_vif *rtwvif, 837 u32 config) 838 { 839 u32 addr, mask; 840 841 if (config & PORT_SET_MAC_ADDR) { 842 addr = rtwvif->conf->mac_addr.addr; 843 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 844 } 845 if (config & PORT_SET_BSSID) { 846 addr = rtwvif->conf->bssid.addr; 847 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 848 } 849 if (config & PORT_SET_NET_TYPE) { 850 addr = rtwvif->conf->net_type.addr; 851 mask = rtwvif->conf->net_type.mask; 852 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 853 } 854 if (config & PORT_SET_AID) { 855 addr = rtwvif->conf->aid.addr; 856 mask = rtwvif->conf->aid.mask; 857 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 858 } 859 if (config & PORT_SET_BCN_CTRL) { 860 addr = rtwvif->conf->bcn_ctrl.addr; 861 mask = rtwvif->conf->bcn_ctrl.mask; 862 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 863 } 864 } 865 866 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 867 { 868 u8 bw = 0; 869 870 switch (bw_cap) { 871 case EFUSE_HW_CAP_IGNORE: 872 case EFUSE_HW_CAP_SUPP_BW80: 873 bw |= BIT(RTW_CHANNEL_WIDTH_80); 874 fallthrough; 875 case EFUSE_HW_CAP_SUPP_BW40: 876 bw |= BIT(RTW_CHANNEL_WIDTH_40); 877 fallthrough; 878 default: 879 bw |= BIT(RTW_CHANNEL_WIDTH_20); 880 break; 881 } 882 883 return bw; 884 } 885 886 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 887 { 888 struct rtw_hal *hal = &rtwdev->hal; 889 struct rtw_chip_info *chip = rtwdev->chip; 890 891 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 892 hw_ant_num >= hal->rf_path_num) 893 return; 894 895 switch (hw_ant_num) { 896 case 1: 897 hal->rf_type = RF_1T1R; 898 hal->rf_path_num = 1; 899 if (!chip->fix_rf_phy_num) 900 hal->rf_phy_num = hal->rf_path_num; 901 hal->antenna_tx = BB_PATH_A; 902 hal->antenna_rx = BB_PATH_A; 903 break; 904 default: 905 WARN(1, "invalid hw configuration from efuse\n"); 906 break; 907 } 908 } 909 910 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 911 { 912 u64 ra_mask = 0; 913 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 914 u8 vht_mcs_cap; 915 int i, nss; 916 917 /* 4SS, every two bits for MCS7/8/9 */ 918 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 919 vht_mcs_cap = mcs_map & 0x3; 920 switch (vht_mcs_cap) { 921 case 2: /* MCS9 */ 922 ra_mask |= 0x3ffULL << nss; 923 break; 924 case 1: /* MCS8 */ 925 ra_mask |= 0x1ffULL << nss; 926 break; 927 case 0: /* MCS7 */ 928 ra_mask |= 0x0ffULL << nss; 929 break; 930 default: 931 break; 932 } 933 } 934 935 return ra_mask; 936 } 937 938 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 939 { 940 u8 rate_id = 0; 941 942 switch (wireless_set) { 943 case WIRELESS_CCK: 944 rate_id = RTW_RATEID_B_20M; 945 break; 946 case WIRELESS_OFDM: 947 rate_id = RTW_RATEID_G; 948 break; 949 case WIRELESS_CCK | WIRELESS_OFDM: 950 rate_id = RTW_RATEID_BG; 951 break; 952 case WIRELESS_OFDM | WIRELESS_HT: 953 if (tx_num == 1) 954 rate_id = RTW_RATEID_GN_N1SS; 955 else if (tx_num == 2) 956 rate_id = RTW_RATEID_GN_N2SS; 957 else if (tx_num == 3) 958 rate_id = RTW_RATEID_ARFR5_N_3SS; 959 break; 960 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 961 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 962 if (tx_num == 1) 963 rate_id = RTW_RATEID_BGN_40M_1SS; 964 else if (tx_num == 2) 965 rate_id = RTW_RATEID_BGN_40M_2SS; 966 else if (tx_num == 3) 967 rate_id = RTW_RATEID_ARFR5_N_3SS; 968 else if (tx_num == 4) 969 rate_id = RTW_RATEID_ARFR7_N_4SS; 970 } else { 971 if (tx_num == 1) 972 rate_id = RTW_RATEID_BGN_20M_1SS; 973 else if (tx_num == 2) 974 rate_id = RTW_RATEID_BGN_20M_2SS; 975 else if (tx_num == 3) 976 rate_id = RTW_RATEID_ARFR5_N_3SS; 977 else if (tx_num == 4) 978 rate_id = RTW_RATEID_ARFR7_N_4SS; 979 } 980 break; 981 case WIRELESS_OFDM | WIRELESS_VHT: 982 if (tx_num == 1) 983 rate_id = RTW_RATEID_ARFR1_AC_1SS; 984 else if (tx_num == 2) 985 rate_id = RTW_RATEID_ARFR0_AC_2SS; 986 else if (tx_num == 3) 987 rate_id = RTW_RATEID_ARFR4_AC_3SS; 988 else if (tx_num == 4) 989 rate_id = RTW_RATEID_ARFR6_AC_4SS; 990 break; 991 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 992 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 993 if (tx_num == 1) 994 rate_id = RTW_RATEID_ARFR1_AC_1SS; 995 else if (tx_num == 2) 996 rate_id = RTW_RATEID_ARFR0_AC_2SS; 997 else if (tx_num == 3) 998 rate_id = RTW_RATEID_ARFR4_AC_3SS; 999 else if (tx_num == 4) 1000 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1001 } else { 1002 if (tx_num == 1) 1003 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1004 else if (tx_num == 2) 1005 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1006 else if (tx_num == 3) 1007 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1008 else if (tx_num == 4) 1009 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1010 } 1011 break; 1012 default: 1013 break; 1014 } 1015 1016 return rate_id; 1017 } 1018 1019 #define RA_MASK_CCK_RATES 0x0000f 1020 #define RA_MASK_OFDM_RATES 0x00ff0 1021 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1022 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1023 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1024 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1025 RA_MASK_HT_RATES_2SS | \ 1026 RA_MASK_HT_RATES_3SS) 1027 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1028 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1029 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1030 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1031 RA_MASK_VHT_RATES_2SS | \ 1032 RA_MASK_VHT_RATES_3SS) 1033 #define RA_MASK_CCK_IN_BG 0x00005 1034 #define RA_MASK_CCK_IN_HT 0x00005 1035 #define RA_MASK_CCK_IN_VHT 0x00005 1036 #define RA_MASK_OFDM_IN_VHT 0x00010 1037 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1038 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1039 1040 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1041 { 1042 u8 rssi_level = si->rssi_level; 1043 1044 if (wireless_set == WIRELESS_CCK) 1045 return 0xffffffffffffffffULL; 1046 1047 if (rssi_level == 0) 1048 return 0xffffffffffffffffULL; 1049 else if (rssi_level == 1) 1050 return 0xfffffffffffffff0ULL; 1051 else if (rssi_level == 2) 1052 return 0xffffffffffffefe0ULL; 1053 else if (rssi_level == 3) 1054 return 0xffffffffffffcfc0ULL; 1055 else if (rssi_level == 4) 1056 return 0xffffffffffff8f80ULL; 1057 else 1058 return 0xffffffffffff0f00ULL; 1059 } 1060 1061 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1062 { 1063 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1064 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1065 1066 if (ra_mask == 0) 1067 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1068 1069 return ra_mask; 1070 } 1071 1072 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1073 u64 ra_mask, bool is_vht_enable) 1074 { 1075 struct rtw_hal *hal = &rtwdev->hal; 1076 const struct cfg80211_bitrate_mask *mask = si->mask; 1077 u64 cfg_mask = GENMASK_ULL(63, 0); 1078 u8 band; 1079 1080 if (!si->use_cfg_mask) 1081 return ra_mask; 1082 1083 band = hal->current_band_type; 1084 if (band == RTW_BAND_2G) { 1085 band = NL80211_BAND_2GHZ; 1086 cfg_mask = mask->control[band].legacy; 1087 } else if (band == RTW_BAND_5G) { 1088 band = NL80211_BAND_5GHZ; 1089 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1090 RA_MASK_OFDM_RATES); 1091 } 1092 1093 if (!is_vht_enable) { 1094 if (ra_mask & RA_MASK_HT_RATES_1SS) 1095 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1096 RA_MASK_HT_RATES_1SS); 1097 if (ra_mask & RA_MASK_HT_RATES_2SS) 1098 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1099 RA_MASK_HT_RATES_2SS); 1100 } else { 1101 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1102 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1103 RA_MASK_VHT_RATES_1SS); 1104 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1105 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1106 RA_MASK_VHT_RATES_2SS); 1107 } 1108 1109 ra_mask &= cfg_mask; 1110 1111 return ra_mask; 1112 } 1113 1114 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1115 bool reset_ra_mask) 1116 { 1117 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1118 struct ieee80211_sta *sta = si->sta; 1119 struct rtw_efuse *efuse = &rtwdev->efuse; 1120 struct rtw_hal *hal = &rtwdev->hal; 1121 u8 wireless_set; 1122 u8 bw_mode; 1123 u8 rate_id; 1124 u8 rf_type = RF_1T1R; 1125 u8 stbc_en = 0; 1126 u8 ldpc_en = 0; 1127 u8 tx_num = 1; 1128 u64 ra_mask = 0; 1129 u64 ra_mask_bak = 0; 1130 bool is_vht_enable = false; 1131 bool is_support_sgi = false; 1132 1133 if (sta->deflink.vht_cap.vht_supported) { 1134 is_vht_enable = true; 1135 ra_mask |= get_vht_ra_mask(sta); 1136 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1137 stbc_en = VHT_STBC_EN; 1138 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1139 ldpc_en = VHT_LDPC_EN; 1140 } else if (sta->deflink.ht_cap.ht_supported) { 1141 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1142 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1143 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1144 stbc_en = HT_STBC_EN; 1145 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1146 ldpc_en = HT_LDPC_EN; 1147 } 1148 1149 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1150 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1151 1152 if (hal->current_band_type == RTW_BAND_5G) { 1153 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1154 ra_mask_bak = ra_mask; 1155 if (sta->deflink.vht_cap.vht_supported) { 1156 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1157 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1158 } else if (sta->deflink.ht_cap.ht_supported) { 1159 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1160 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1161 } else { 1162 wireless_set = WIRELESS_OFDM; 1163 } 1164 dm_info->rrsr_val_init = RRSR_INIT_5G; 1165 } else if (hal->current_band_type == RTW_BAND_2G) { 1166 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1167 ra_mask_bak = ra_mask; 1168 if (sta->deflink.vht_cap.vht_supported) { 1169 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1170 RA_MASK_OFDM_IN_VHT; 1171 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1172 WIRELESS_HT | WIRELESS_VHT; 1173 } else if (sta->deflink.ht_cap.ht_supported) { 1174 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1175 RA_MASK_OFDM_IN_HT_2G; 1176 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1177 WIRELESS_HT; 1178 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1179 wireless_set = WIRELESS_CCK; 1180 } else { 1181 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1182 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1183 } 1184 dm_info->rrsr_val_init = RRSR_INIT_2G; 1185 } else { 1186 rtw_err(rtwdev, "Unknown band type\n"); 1187 ra_mask_bak = ra_mask; 1188 wireless_set = 0; 1189 } 1190 1191 switch (sta->deflink.bandwidth) { 1192 case IEEE80211_STA_RX_BW_80: 1193 bw_mode = RTW_CHANNEL_WIDTH_80; 1194 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1195 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1196 break; 1197 case IEEE80211_STA_RX_BW_40: 1198 bw_mode = RTW_CHANNEL_WIDTH_40; 1199 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1200 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1201 break; 1202 default: 1203 bw_mode = RTW_CHANNEL_WIDTH_20; 1204 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1205 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1206 break; 1207 } 1208 1209 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { 1210 tx_num = 2; 1211 rf_type = RF_2T2R; 1212 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { 1213 tx_num = 2; 1214 rf_type = RF_2T2R; 1215 } 1216 1217 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1218 1219 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1220 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1221 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1222 1223 si->bw_mode = bw_mode; 1224 si->stbc_en = stbc_en; 1225 si->ldpc_en = ldpc_en; 1226 si->rf_type = rf_type; 1227 si->wireless_set = wireless_set; 1228 si->sgi_enable = is_support_sgi; 1229 si->vht_enable = is_vht_enable; 1230 si->ra_mask = ra_mask; 1231 si->rate_id = rate_id; 1232 1233 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1234 } 1235 1236 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1237 { 1238 struct rtw_chip_info *chip = rtwdev->chip; 1239 struct rtw_fw_state *fw; 1240 1241 fw = &rtwdev->fw; 1242 wait_for_completion(&fw->completion); 1243 if (!fw->firmware) 1244 return -EINVAL; 1245 1246 if (chip->wow_fw_name) { 1247 fw = &rtwdev->wow_fw; 1248 wait_for_completion(&fw->completion); 1249 if (!fw->firmware) 1250 return -EINVAL; 1251 } 1252 1253 return 0; 1254 } 1255 1256 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1257 struct rtw_fw_state *fw) 1258 { 1259 struct rtw_chip_info *chip = rtwdev->chip; 1260 1261 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1262 !fw->feature) 1263 return LPS_DEEP_MODE_NONE; 1264 1265 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1266 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1267 return LPS_DEEP_MODE_PG; 1268 1269 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1270 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1271 return LPS_DEEP_MODE_LCLK; 1272 1273 return LPS_DEEP_MODE_NONE; 1274 } 1275 1276 static int rtw_power_on(struct rtw_dev *rtwdev) 1277 { 1278 struct rtw_chip_info *chip = rtwdev->chip; 1279 struct rtw_fw_state *fw = &rtwdev->fw; 1280 bool wifi_only; 1281 int ret; 1282 1283 ret = rtw_hci_setup(rtwdev); 1284 if (ret) { 1285 rtw_err(rtwdev, "failed to setup hci\n"); 1286 goto err; 1287 } 1288 1289 /* power on MAC before firmware downloaded */ 1290 ret = rtw_mac_power_on(rtwdev); 1291 if (ret) { 1292 rtw_err(rtwdev, "failed to power on mac\n"); 1293 goto err; 1294 } 1295 1296 ret = rtw_wait_firmware_completion(rtwdev); 1297 if (ret) { 1298 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1299 goto err_off; 1300 } 1301 1302 ret = rtw_download_firmware(rtwdev, fw); 1303 if (ret) { 1304 rtw_err(rtwdev, "failed to download firmware\n"); 1305 goto err_off; 1306 } 1307 1308 /* config mac after firmware downloaded */ 1309 ret = rtw_mac_init(rtwdev); 1310 if (ret) { 1311 rtw_err(rtwdev, "failed to configure mac\n"); 1312 goto err_off; 1313 } 1314 1315 chip->ops->phy_set_param(rtwdev); 1316 1317 ret = rtw_hci_start(rtwdev); 1318 if (ret) { 1319 rtw_err(rtwdev, "failed to start hci\n"); 1320 goto err_off; 1321 } 1322 1323 /* send H2C after HCI has started */ 1324 rtw_fw_send_general_info(rtwdev); 1325 rtw_fw_send_phydm_info(rtwdev); 1326 1327 wifi_only = !rtwdev->efuse.btcoex; 1328 rtw_coex_power_on_setting(rtwdev); 1329 rtw_coex_init_hw_config(rtwdev, wifi_only); 1330 1331 return 0; 1332 1333 err_off: 1334 rtw_mac_power_off(rtwdev); 1335 1336 err: 1337 return ret; 1338 } 1339 1340 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1341 { 1342 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1343 return; 1344 1345 if (start) { 1346 rtw_fw_scan_notify(rtwdev, true); 1347 } else { 1348 reinit_completion(&rtwdev->fw_scan_density); 1349 rtw_fw_scan_notify(rtwdev, false); 1350 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1351 SCAN_NOTIFY_TIMEOUT)) 1352 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1353 } 1354 } 1355 1356 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1357 const u8 *mac_addr, bool hw_scan) 1358 { 1359 u32 config = 0; 1360 int ret = 0; 1361 1362 rtw_leave_lps(rtwdev); 1363 1364 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1365 ret = rtw_leave_ips(rtwdev); 1366 if (ret) { 1367 rtw_err(rtwdev, "failed to leave idle state\n"); 1368 return; 1369 } 1370 } 1371 1372 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1373 config |= PORT_SET_MAC_ADDR; 1374 rtw_vif_port_config(rtwdev, rtwvif, config); 1375 1376 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1377 rtw_core_fw_scan_notify(rtwdev, true); 1378 1379 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1380 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1381 } 1382 1383 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1384 bool hw_scan) 1385 { 1386 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1387 u32 config = 0; 1388 1389 if (!rtwvif) 1390 return; 1391 1392 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1393 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1394 1395 rtw_core_fw_scan_notify(rtwdev, false); 1396 1397 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1398 config |= PORT_SET_MAC_ADDR; 1399 rtw_vif_port_config(rtwdev, rtwvif, config); 1400 1401 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1402 1403 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1404 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1405 } 1406 1407 int rtw_core_start(struct rtw_dev *rtwdev) 1408 { 1409 int ret; 1410 1411 ret = rtw_power_on(rtwdev); 1412 if (ret) 1413 return ret; 1414 1415 rtw_sec_enable_sec_engine(rtwdev); 1416 1417 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1418 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1419 1420 /* rcr reset after powered on */ 1421 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1422 1423 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1424 RTW_WATCH_DOG_DELAY_TIME); 1425 1426 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1427 1428 return 0; 1429 } 1430 1431 static void rtw_power_off(struct rtw_dev *rtwdev) 1432 { 1433 rtw_hci_stop(rtwdev); 1434 rtw_coex_power_off_setting(rtwdev); 1435 rtw_mac_power_off(rtwdev); 1436 } 1437 1438 void rtw_core_stop(struct rtw_dev *rtwdev) 1439 { 1440 struct rtw_coex *coex = &rtwdev->coex; 1441 1442 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1443 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1444 1445 mutex_unlock(&rtwdev->mutex); 1446 1447 cancel_work_sync(&rtwdev->c2h_work); 1448 cancel_work_sync(&rtwdev->update_beacon_work); 1449 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1450 cancel_delayed_work_sync(&coex->bt_relink_work); 1451 cancel_delayed_work_sync(&coex->bt_reenable_work); 1452 cancel_delayed_work_sync(&coex->defreeze_work); 1453 cancel_delayed_work_sync(&coex->wl_remain_work); 1454 cancel_delayed_work_sync(&coex->bt_remain_work); 1455 cancel_delayed_work_sync(&coex->wl_connecting_work); 1456 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1457 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1458 1459 mutex_lock(&rtwdev->mutex); 1460 1461 rtw_power_off(rtwdev); 1462 } 1463 1464 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1465 struct ieee80211_sta_ht_cap *ht_cap) 1466 { 1467 struct rtw_efuse *efuse = &rtwdev->efuse; 1468 struct rtw_chip_info *chip = rtwdev->chip; 1469 1470 ht_cap->ht_supported = true; 1471 ht_cap->cap = 0; 1472 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1473 IEEE80211_HT_CAP_MAX_AMSDU | 1474 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1475 1476 if (rtw_chip_has_rx_ldpc(rtwdev)) 1477 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1478 if (rtw_chip_has_tx_stbc(rtwdev)) 1479 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1480 1481 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1482 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1483 IEEE80211_HT_CAP_DSSSCCK40 | 1484 IEEE80211_HT_CAP_SGI_40; 1485 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1486 ht_cap->ampdu_density = chip->ampdu_density; 1487 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1488 if (efuse->hw_cap.nss > 1) { 1489 ht_cap->mcs.rx_mask[0] = 0xFF; 1490 ht_cap->mcs.rx_mask[1] = 0xFF; 1491 ht_cap->mcs.rx_mask[4] = 0x01; 1492 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1493 } else { 1494 ht_cap->mcs.rx_mask[0] = 0xFF; 1495 ht_cap->mcs.rx_mask[1] = 0x00; 1496 ht_cap->mcs.rx_mask[4] = 0x01; 1497 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1498 } 1499 } 1500 1501 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1502 struct ieee80211_sta_vht_cap *vht_cap) 1503 { 1504 struct rtw_efuse *efuse = &rtwdev->efuse; 1505 u16 mcs_map; 1506 __le16 highest; 1507 1508 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1509 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1510 return; 1511 1512 vht_cap->vht_supported = true; 1513 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1514 IEEE80211_VHT_CAP_SHORT_GI_80 | 1515 IEEE80211_VHT_CAP_RXSTBC_1 | 1516 IEEE80211_VHT_CAP_HTC_VHT | 1517 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1518 0; 1519 if (rtwdev->hal.rf_path_num > 1) 1520 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1521 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1522 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1523 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1524 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1525 1526 if (rtw_chip_has_rx_ldpc(rtwdev)) 1527 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1528 1529 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1530 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1531 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1532 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1533 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1534 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1535 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1536 if (efuse->hw_cap.nss > 1) { 1537 highest = cpu_to_le16(780); 1538 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1539 } else { 1540 highest = cpu_to_le16(390); 1541 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1542 } 1543 1544 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1545 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1546 vht_cap->vht_mcs.rx_highest = highest; 1547 vht_cap->vht_mcs.tx_highest = highest; 1548 } 1549 1550 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1551 struct rtw_chip_info *chip) 1552 { 1553 struct rtw_dev *rtwdev = hw->priv; 1554 struct ieee80211_supported_band *sband; 1555 1556 if (chip->band & RTW_BAND_2G) { 1557 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1558 if (!sband) 1559 goto err_out; 1560 if (chip->ht_supported) 1561 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1562 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1563 } 1564 1565 if (chip->band & RTW_BAND_5G) { 1566 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1567 if (!sband) 1568 goto err_out; 1569 if (chip->ht_supported) 1570 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1571 if (chip->vht_supported) 1572 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1573 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1574 } 1575 1576 return; 1577 1578 err_out: 1579 rtw_err(rtwdev, "failed to set supported band\n"); 1580 } 1581 1582 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1583 struct rtw_chip_info *chip) 1584 { 1585 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1586 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1587 } 1588 1589 static void rtw_vif_smps_iter(void *data, u8 *mac, 1590 struct ieee80211_vif *vif) 1591 { 1592 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1593 1594 if (vif->type != NL80211_IFTYPE_STATION || !vif->bss_conf.assoc) 1595 return; 1596 1597 if (rtwdev->hal.txrx_1ss) 1598 ieee80211_request_smps(vif, IEEE80211_SMPS_STATIC); 1599 else 1600 ieee80211_request_smps(vif, IEEE80211_SMPS_OFF); 1601 } 1602 1603 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1604 { 1605 struct rtw_chip_info *chip = rtwdev->chip; 1606 struct rtw_hal *hal = &rtwdev->hal; 1607 1608 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1609 return; 1610 1611 rtwdev->hal.txrx_1ss = txrx_1ss; 1612 if (txrx_1ss) 1613 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1614 else 1615 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1616 hal->antenna_rx, false); 1617 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1618 } 1619 1620 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1621 struct rtw_fw_state *fw) 1622 { 1623 u32 feature; 1624 const struct rtw_fw_hdr *fw_hdr = 1625 (const struct rtw_fw_hdr *)fw->firmware->data; 1626 1627 feature = le32_to_cpu(fw_hdr->feature); 1628 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1629 } 1630 1631 static void __update_firmware_info(struct rtw_dev *rtwdev, 1632 struct rtw_fw_state *fw) 1633 { 1634 const struct rtw_fw_hdr *fw_hdr = 1635 (const struct rtw_fw_hdr *)fw->firmware->data; 1636 1637 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1638 fw->version = le16_to_cpu(fw_hdr->version); 1639 fw->sub_version = fw_hdr->subversion; 1640 fw->sub_index = fw_hdr->subindex; 1641 1642 __update_firmware_feature(rtwdev, fw); 1643 } 1644 1645 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1646 struct rtw_fw_state *fw) 1647 { 1648 struct rtw_fw_hdr_legacy *legacy = 1649 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1650 1651 fw->h2c_version = 0; 1652 fw->version = le16_to_cpu(legacy->version); 1653 fw->sub_version = legacy->subversion1; 1654 fw->sub_index = legacy->subversion2; 1655 } 1656 1657 static void update_firmware_info(struct rtw_dev *rtwdev, 1658 struct rtw_fw_state *fw) 1659 { 1660 if (rtw_chip_wcpu_11n(rtwdev)) 1661 __update_firmware_info_legacy(rtwdev, fw); 1662 else 1663 __update_firmware_info(rtwdev, fw); 1664 } 1665 1666 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1667 { 1668 struct rtw_fw_state *fw = context; 1669 struct rtw_dev *rtwdev = fw->rtwdev; 1670 1671 if (!firmware || !firmware->data) { 1672 rtw_err(rtwdev, "failed to request firmware\n"); 1673 complete_all(&fw->completion); 1674 return; 1675 } 1676 1677 fw->firmware = firmware; 1678 update_firmware_info(rtwdev, fw); 1679 complete_all(&fw->completion); 1680 1681 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1682 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1683 } 1684 1685 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1686 { 1687 const char *fw_name; 1688 struct rtw_fw_state *fw; 1689 int ret; 1690 1691 switch (type) { 1692 case RTW_WOWLAN_FW: 1693 fw = &rtwdev->wow_fw; 1694 fw_name = rtwdev->chip->wow_fw_name; 1695 break; 1696 1697 case RTW_NORMAL_FW: 1698 fw = &rtwdev->fw; 1699 fw_name = rtwdev->chip->fw_name; 1700 break; 1701 1702 default: 1703 rtw_warn(rtwdev, "unsupported firmware type\n"); 1704 return -ENOENT; 1705 } 1706 1707 fw->rtwdev = rtwdev; 1708 init_completion(&fw->completion); 1709 1710 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1711 GFP_KERNEL, fw, rtw_load_firmware_cb); 1712 if (ret) { 1713 rtw_err(rtwdev, "failed to async firmware request\n"); 1714 return ret; 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1721 { 1722 struct rtw_chip_info *chip = rtwdev->chip; 1723 struct rtw_hal *hal = &rtwdev->hal; 1724 struct rtw_efuse *efuse = &rtwdev->efuse; 1725 1726 switch (rtw_hci_type(rtwdev)) { 1727 case RTW_HCI_TYPE_PCIE: 1728 rtwdev->hci.rpwm_addr = 0x03d9; 1729 rtwdev->hci.cpwm_addr = 0x03da; 1730 break; 1731 default: 1732 rtw_err(rtwdev, "unsupported hci type\n"); 1733 return -EINVAL; 1734 } 1735 1736 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1737 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1738 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1739 if (hal->chip_version & BIT_RF_TYPE_ID) { 1740 hal->rf_type = RF_2T2R; 1741 hal->rf_path_num = 2; 1742 hal->antenna_tx = BB_PATH_AB; 1743 hal->antenna_rx = BB_PATH_AB; 1744 } else { 1745 hal->rf_type = RF_1T1R; 1746 hal->rf_path_num = 1; 1747 hal->antenna_tx = BB_PATH_A; 1748 hal->antenna_rx = BB_PATH_A; 1749 } 1750 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1751 hal->rf_path_num; 1752 1753 efuse->physical_size = chip->phy_efuse_size; 1754 efuse->logical_size = chip->log_efuse_size; 1755 efuse->protect_size = chip->ptct_efuse_size; 1756 1757 /* default use ack */ 1758 rtwdev->hal.rcr |= BIT_VHT_DACK; 1759 1760 hal->bfee_sts_cap = 3; 1761 1762 return 0; 1763 } 1764 1765 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1766 { 1767 struct rtw_fw_state *fw = &rtwdev->fw; 1768 int ret; 1769 1770 ret = rtw_hci_setup(rtwdev); 1771 if (ret) { 1772 rtw_err(rtwdev, "failed to setup hci\n"); 1773 goto err; 1774 } 1775 1776 ret = rtw_mac_power_on(rtwdev); 1777 if (ret) { 1778 rtw_err(rtwdev, "failed to power on mac\n"); 1779 goto err; 1780 } 1781 1782 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1783 1784 wait_for_completion(&fw->completion); 1785 if (!fw->firmware) { 1786 ret = -EINVAL; 1787 rtw_err(rtwdev, "failed to load firmware\n"); 1788 goto err; 1789 } 1790 1791 ret = rtw_download_firmware(rtwdev, fw); 1792 if (ret) { 1793 rtw_err(rtwdev, "failed to download firmware\n"); 1794 goto err_off; 1795 } 1796 1797 return 0; 1798 1799 err_off: 1800 rtw_mac_power_off(rtwdev); 1801 1802 err: 1803 return ret; 1804 } 1805 1806 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1807 { 1808 struct rtw_efuse *efuse = &rtwdev->efuse; 1809 u8 hw_feature[HW_FEATURE_LEN]; 1810 u8 id; 1811 u8 bw; 1812 int i; 1813 1814 id = rtw_read8(rtwdev, REG_C2HEVT); 1815 if (id != C2H_HW_FEATURE_REPORT) { 1816 rtw_err(rtwdev, "failed to read hw feature report\n"); 1817 return -EBUSY; 1818 } 1819 1820 for (i = 0; i < HW_FEATURE_LEN; i++) 1821 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1822 1823 rtw_write8(rtwdev, REG_C2HEVT, 0); 1824 1825 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1826 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1827 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1828 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1829 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1830 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1831 1832 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1833 1834 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1835 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1836 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1837 1838 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1839 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1840 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1841 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1842 1843 return 0; 1844 } 1845 1846 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1847 { 1848 rtw_hci_stop(rtwdev); 1849 rtw_mac_power_off(rtwdev); 1850 } 1851 1852 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1853 { 1854 struct rtw_efuse *efuse = &rtwdev->efuse; 1855 int ret; 1856 1857 mutex_lock(&rtwdev->mutex); 1858 1859 /* power on mac to read efuse */ 1860 ret = rtw_chip_efuse_enable(rtwdev); 1861 if (ret) 1862 goto out_unlock; 1863 1864 ret = rtw_parse_efuse_map(rtwdev); 1865 if (ret) 1866 goto out_disable; 1867 1868 ret = rtw_dump_hw_feature(rtwdev); 1869 if (ret) 1870 goto out_disable; 1871 1872 ret = rtw_check_supported_rfe(rtwdev); 1873 if (ret) 1874 goto out_disable; 1875 1876 if (efuse->crystal_cap == 0xff) 1877 efuse->crystal_cap = 0; 1878 if (efuse->pa_type_2g == 0xff) 1879 efuse->pa_type_2g = 0; 1880 if (efuse->pa_type_5g == 0xff) 1881 efuse->pa_type_5g = 0; 1882 if (efuse->lna_type_2g == 0xff) 1883 efuse->lna_type_2g = 0; 1884 if (efuse->lna_type_5g == 0xff) 1885 efuse->lna_type_5g = 0; 1886 if (efuse->channel_plan == 0xff) 1887 efuse->channel_plan = 0x7f; 1888 if (efuse->rf_board_option == 0xff) 1889 efuse->rf_board_option = 0; 1890 if (efuse->bt_setting & BIT(0)) 1891 efuse->share_ant = true; 1892 if (efuse->regd == 0xff) 1893 efuse->regd = 0; 1894 if (efuse->tx_bb_swing_setting_2g == 0xff) 1895 efuse->tx_bb_swing_setting_2g = 0; 1896 if (efuse->tx_bb_swing_setting_5g == 0xff) 1897 efuse->tx_bb_swing_setting_5g = 0; 1898 1899 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1900 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1901 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1902 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1903 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1904 1905 out_disable: 1906 rtw_chip_efuse_disable(rtwdev); 1907 1908 out_unlock: 1909 mutex_unlock(&rtwdev->mutex); 1910 return ret; 1911 } 1912 1913 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1914 { 1915 struct rtw_hal *hal = &rtwdev->hal; 1916 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1917 1918 if (!rfe_def) 1919 return -ENODEV; 1920 1921 rtw_phy_setup_phy_cond(rtwdev, 0); 1922 1923 rtw_phy_init_tx_power(rtwdev); 1924 if (rfe_def->agc_btg_tbl) 1925 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1926 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1927 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1928 rtw_phy_tx_power_by_rate_config(hal); 1929 rtw_phy_tx_power_limit_config(hal); 1930 1931 return 0; 1932 } 1933 1934 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1935 { 1936 int ret; 1937 1938 ret = rtw_chip_parameter_setup(rtwdev); 1939 if (ret) { 1940 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1941 goto err_out; 1942 } 1943 1944 ret = rtw_chip_efuse_info_setup(rtwdev); 1945 if (ret) { 1946 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1947 goto err_out; 1948 } 1949 1950 ret = rtw_chip_board_info_setup(rtwdev); 1951 if (ret) { 1952 rtw_err(rtwdev, "failed to setup chip board info\n"); 1953 goto err_out; 1954 } 1955 1956 return 0; 1957 1958 err_out: 1959 return ret; 1960 } 1961 EXPORT_SYMBOL(rtw_chip_info_setup); 1962 1963 static void rtw_stats_init(struct rtw_dev *rtwdev) 1964 { 1965 struct rtw_traffic_stats *stats = &rtwdev->stats; 1966 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1967 int i; 1968 1969 ewma_tp_init(&stats->tx_ewma_tp); 1970 ewma_tp_init(&stats->rx_ewma_tp); 1971 1972 for (i = 0; i < RTW_EVM_NUM; i++) 1973 ewma_evm_init(&dm_info->ewma_evm[i]); 1974 for (i = 0; i < RTW_SNR_NUM; i++) 1975 ewma_snr_init(&dm_info->ewma_snr[i]); 1976 } 1977 1978 int rtw_core_init(struct rtw_dev *rtwdev) 1979 { 1980 struct rtw_chip_info *chip = rtwdev->chip; 1981 struct rtw_coex *coex = &rtwdev->coex; 1982 int ret; 1983 1984 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1985 INIT_LIST_HEAD(&rtwdev->txqs); 1986 1987 timer_setup(&rtwdev->tx_report.purge_timer, 1988 rtw_tx_report_purge_timer, 0); 1989 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 1990 1991 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1992 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1993 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1994 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1995 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 1996 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 1997 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 1998 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 1999 rtw_coex_bt_multi_link_remain_work); 2000 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2001 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2002 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2003 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2004 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2005 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2006 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2007 skb_queue_head_init(&rtwdev->c2h_queue); 2008 skb_queue_head_init(&rtwdev->coex.queue); 2009 skb_queue_head_init(&rtwdev->tx_report.queue); 2010 2011 spin_lock_init(&rtwdev->rf_lock); 2012 spin_lock_init(&rtwdev->h2c.lock); 2013 spin_lock_init(&rtwdev->txq_lock); 2014 spin_lock_init(&rtwdev->tx_report.q_lock); 2015 2016 mutex_init(&rtwdev->mutex); 2017 mutex_init(&rtwdev->coex.mutex); 2018 mutex_init(&rtwdev->hal.tx_power_mutex); 2019 2020 init_waitqueue_head(&rtwdev->coex.wait); 2021 init_completion(&rtwdev->lps_leave_check); 2022 init_completion(&rtwdev->fw_scan_density); 2023 2024 rtwdev->sec.total_cam_num = 32; 2025 rtwdev->hal.current_channel = 1; 2026 rtwdev->dm_info.fix_rate = U8_MAX; 2027 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2028 2029 rtw_stats_init(rtwdev); 2030 2031 /* default rx filter setting */ 2032 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2033 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2034 BIT_AB | BIT_AM | BIT_APM; 2035 2036 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2037 if (ret) { 2038 rtw_warn(rtwdev, "no firmware loaded\n"); 2039 return ret; 2040 } 2041 2042 if (chip->wow_fw_name) { 2043 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2044 if (ret) { 2045 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2046 wait_for_completion(&rtwdev->fw.completion); 2047 if (rtwdev->fw.firmware) 2048 release_firmware(rtwdev->fw.firmware); 2049 return ret; 2050 } 2051 } 2052 2053 return 0; 2054 } 2055 EXPORT_SYMBOL(rtw_core_init); 2056 2057 void rtw_core_deinit(struct rtw_dev *rtwdev) 2058 { 2059 struct rtw_fw_state *fw = &rtwdev->fw; 2060 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2061 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2062 unsigned long flags; 2063 2064 rtw_wait_firmware_completion(rtwdev); 2065 2066 if (fw->firmware) 2067 release_firmware(fw->firmware); 2068 2069 if (wow_fw->firmware) 2070 release_firmware(wow_fw->firmware); 2071 2072 destroy_workqueue(rtwdev->tx_wq); 2073 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2074 skb_queue_purge(&rtwdev->tx_report.queue); 2075 skb_queue_purge(&rtwdev->coex.queue); 2076 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2077 2078 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2079 build_list) { 2080 list_del(&rsvd_pkt->build_list); 2081 kfree(rsvd_pkt); 2082 } 2083 2084 mutex_destroy(&rtwdev->mutex); 2085 mutex_destroy(&rtwdev->coex.mutex); 2086 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2087 } 2088 EXPORT_SYMBOL(rtw_core_deinit); 2089 2090 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2091 { 2092 struct rtw_hal *hal = &rtwdev->hal; 2093 int max_tx_headroom = 0; 2094 int ret; 2095 2096 /* TODO: USB & SDIO may need extra room? */ 2097 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2098 2099 hw->extra_tx_headroom = max_tx_headroom; 2100 hw->queues = IEEE80211_NUM_ACS; 2101 hw->txq_data_size = sizeof(struct rtw_txq); 2102 hw->sta_data_size = sizeof(struct rtw_sta_info); 2103 hw->vif_data_size = sizeof(struct rtw_vif); 2104 2105 ieee80211_hw_set(hw, SIGNAL_DBM); 2106 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2107 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2108 ieee80211_hw_set(hw, MFP_CAPABLE); 2109 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2110 ieee80211_hw_set(hw, SUPPORTS_PS); 2111 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2112 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2113 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2114 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2115 ieee80211_hw_set(hw, TX_AMSDU); 2116 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2117 2118 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2119 BIT(NL80211_IFTYPE_AP) | 2120 BIT(NL80211_IFTYPE_ADHOC) | 2121 BIT(NL80211_IFTYPE_MESH_POINT); 2122 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2123 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2124 2125 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2126 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2127 2128 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2129 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2130 hw->wiphy->max_scan_ie_len = RTW_SCAN_MAX_IE_LEN; 2131 2132 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2133 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2134 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2135 2136 #ifdef CONFIG_PM 2137 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2138 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2139 #endif 2140 rtw_set_supported_band(hw, rtwdev->chip); 2141 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2142 2143 hw->wiphy->sar_capa = &rtw_sar_capa; 2144 2145 ret = rtw_regd_init(rtwdev); 2146 if (ret) { 2147 rtw_err(rtwdev, "failed to init regd\n"); 2148 return ret; 2149 } 2150 2151 ret = ieee80211_register_hw(hw); 2152 if (ret) { 2153 rtw_err(rtwdev, "failed to register hw\n"); 2154 return ret; 2155 } 2156 2157 ret = rtw_regd_hint(rtwdev); 2158 if (ret) { 2159 rtw_err(rtwdev, "failed to hint regd\n"); 2160 return ret; 2161 } 2162 2163 rtw_debugfs_init(rtwdev); 2164 2165 rtwdev->bf_info.bfer_mu_cnt = 0; 2166 rtwdev->bf_info.bfer_su_cnt = 0; 2167 2168 return 0; 2169 } 2170 EXPORT_SYMBOL(rtw_register_hw); 2171 2172 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2173 { 2174 struct rtw_chip_info *chip = rtwdev->chip; 2175 2176 ieee80211_unregister_hw(hw); 2177 rtw_unset_supported_band(hw, chip); 2178 } 2179 EXPORT_SYMBOL(rtw_unregister_hw); 2180 2181 MODULE_AUTHOR("Realtek Corporation"); 2182 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2183 MODULE_LICENSE("Dual BSD/GPL"); 2184