1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 #include "sdio.h" 22 #include "led.h" 23 24 bool rtw_disable_lps_deep_mode; 25 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 26 bool rtw_bf_support = true; 27 unsigned int rtw_debug_mask; 28 EXPORT_SYMBOL(rtw_debug_mask); 29 /* EDCCA is enabled during normal behavior. For debugging purpose in 30 * a noisy environment, it can be disabled via edcca debugfs. Because 31 * all rtw88 devices will probably be affected if environment is noisy, 32 * rtw_edcca_enabled is just declared by driver instead of by device. 33 * So, turning it off will take effect for all rtw88 devices before 34 * there is a tough reason to maintain rtw_edcca_enabled by device. 35 */ 36 bool rtw_edcca_enabled = true; 37 38 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 39 module_param_named(support_bf, rtw_bf_support, bool, 0644); 40 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 41 42 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 43 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 44 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 45 46 static struct ieee80211_channel rtw_channeltable_2g[] = { 47 {.center_freq = 2412, .hw_value = 1,}, 48 {.center_freq = 2417, .hw_value = 2,}, 49 {.center_freq = 2422, .hw_value = 3,}, 50 {.center_freq = 2427, .hw_value = 4,}, 51 {.center_freq = 2432, .hw_value = 5,}, 52 {.center_freq = 2437, .hw_value = 6,}, 53 {.center_freq = 2442, .hw_value = 7,}, 54 {.center_freq = 2447, .hw_value = 8,}, 55 {.center_freq = 2452, .hw_value = 9,}, 56 {.center_freq = 2457, .hw_value = 10,}, 57 {.center_freq = 2462, .hw_value = 11,}, 58 {.center_freq = 2467, .hw_value = 12,}, 59 {.center_freq = 2472, .hw_value = 13,}, 60 {.center_freq = 2484, .hw_value = 14,}, 61 }; 62 63 static struct ieee80211_channel rtw_channeltable_5g[] = { 64 {.center_freq = 5180, .hw_value = 36,}, 65 {.center_freq = 5200, .hw_value = 40,}, 66 {.center_freq = 5220, .hw_value = 44,}, 67 {.center_freq = 5240, .hw_value = 48,}, 68 {.center_freq = 5260, .hw_value = 52,}, 69 {.center_freq = 5280, .hw_value = 56,}, 70 {.center_freq = 5300, .hw_value = 60,}, 71 {.center_freq = 5320, .hw_value = 64,}, 72 {.center_freq = 5500, .hw_value = 100,}, 73 {.center_freq = 5520, .hw_value = 104,}, 74 {.center_freq = 5540, .hw_value = 108,}, 75 {.center_freq = 5560, .hw_value = 112,}, 76 {.center_freq = 5580, .hw_value = 116,}, 77 {.center_freq = 5600, .hw_value = 120,}, 78 {.center_freq = 5620, .hw_value = 124,}, 79 {.center_freq = 5640, .hw_value = 128,}, 80 {.center_freq = 5660, .hw_value = 132,}, 81 {.center_freq = 5680, .hw_value = 136,}, 82 {.center_freq = 5700, .hw_value = 140,}, 83 {.center_freq = 5720, .hw_value = 144,}, 84 {.center_freq = 5745, .hw_value = 149,}, 85 {.center_freq = 5765, .hw_value = 153,}, 86 {.center_freq = 5785, .hw_value = 157,}, 87 {.center_freq = 5805, .hw_value = 161,}, 88 {.center_freq = 5825, .hw_value = 165, 89 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 90 }; 91 92 static struct ieee80211_rate rtw_ratetable[] = { 93 {.bitrate = 10, .hw_value = 0x00,}, 94 {.bitrate = 20, .hw_value = 0x01,}, 95 {.bitrate = 55, .hw_value = 0x02,}, 96 {.bitrate = 110, .hw_value = 0x03,}, 97 {.bitrate = 60, .hw_value = 0x04,}, 98 {.bitrate = 90, .hw_value = 0x05,}, 99 {.bitrate = 120, .hw_value = 0x06,}, 100 {.bitrate = 180, .hw_value = 0x07,}, 101 {.bitrate = 240, .hw_value = 0x08,}, 102 {.bitrate = 360, .hw_value = 0x09,}, 103 {.bitrate = 480, .hw_value = 0x0a,}, 104 {.bitrate = 540, .hw_value = 0x0b,}, 105 }; 106 107 static const struct ieee80211_iface_limit rtw_iface_limits[] = { 108 { 109 .max = 1, 110 .types = BIT(NL80211_IFTYPE_STATION), 111 }, 112 { 113 .max = 1, 114 .types = BIT(NL80211_IFTYPE_AP), 115 } 116 }; 117 118 static const struct ieee80211_iface_combination rtw_iface_combs[] = { 119 { 120 .limits = rtw_iface_limits, 121 .n_limits = ARRAY_SIZE(rtw_iface_limits), 122 .max_interfaces = 2, 123 .num_different_channels = 1, 124 } 125 }; 126 127 u16 rtw_desc_to_bitrate(u8 desc_rate) 128 { 129 struct ieee80211_rate rate; 130 131 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 132 return 0; 133 134 rate = rtw_ratetable[desc_rate]; 135 136 return rate.bitrate; 137 } 138 139 static const struct ieee80211_supported_band rtw_band_2ghz = { 140 .band = NL80211_BAND_2GHZ, 141 142 .channels = rtw_channeltable_2g, 143 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 144 145 .bitrates = rtw_ratetable, 146 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 147 148 .ht_cap = {0}, 149 .vht_cap = {0}, 150 }; 151 152 static const struct ieee80211_supported_band rtw_band_5ghz = { 153 .band = NL80211_BAND_5GHZ, 154 155 .channels = rtw_channeltable_5g, 156 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 157 158 /* 5G has no CCK rates */ 159 .bitrates = rtw_ratetable + 4, 160 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 161 162 .ht_cap = {0}, 163 .vht_cap = {0}, 164 }; 165 166 struct rtw_watch_dog_iter_data { 167 struct rtw_dev *rtwdev; 168 struct rtw_vif *rtwvif; 169 }; 170 171 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 172 { 173 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 174 u8 fix_rate_enable = 0; 175 u8 new_csi_rate_idx; 176 177 if (rtwvif->bfee.role != RTW_BFEE_SU && 178 rtwvif->bfee.role != RTW_BFEE_MU) 179 return; 180 181 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 182 bf_info->cur_csi_rpt_rate, 183 fix_rate_enable, &new_csi_rate_idx); 184 185 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 186 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 187 } 188 189 static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif) 190 { 191 struct rtw_watch_dog_iter_data *iter_data = data; 192 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 193 194 if (vif->type == NL80211_IFTYPE_STATION) 195 if (vif->cfg.assoc) 196 iter_data->rtwvif = rtwvif; 197 198 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 199 200 rtwvif->stats.tx_unicast = 0; 201 rtwvif->stats.rx_unicast = 0; 202 rtwvif->stats.tx_cnt = 0; 203 rtwvif->stats.rx_cnt = 0; 204 } 205 206 static void rtw_sw_beacon_loss_check(struct rtw_dev *rtwdev, 207 struct rtw_vif *rtwvif, int received_beacons) 208 { 209 int watchdog_delay = 2000000 / 1024; /* TU */ 210 int beacon_int, expected_beacons; 211 212 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_BCN_FILTER) || !rtwvif) 213 return; 214 215 beacon_int = rtwvif_to_vif(rtwvif)->bss_conf.beacon_int; 216 expected_beacons = DIV_ROUND_UP(watchdog_delay, beacon_int); 217 218 rtwdev->beacon_loss = received_beacons < expected_beacons / 2; 219 } 220 221 /* process TX/RX statistics periodically for hardware, 222 * the information helps hardware to enhance performance 223 */ 224 static void rtw_watch_dog_work(struct work_struct *work) 225 { 226 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 227 watch_dog_work.work); 228 struct rtw_traffic_stats *stats = &rtwdev->stats; 229 struct rtw_watch_dog_iter_data data = {}; 230 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 231 int received_beacons = rtwdev->dm_info.cur_pkt_count.num_bcn_pkt; 232 u32 tx_unicast_mbps, rx_unicast_mbps; 233 bool ps_active; 234 235 mutex_lock(&rtwdev->mutex); 236 237 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 238 goto unlock; 239 240 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 241 RTW_WATCH_DOG_DELAY_TIME); 242 243 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 244 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 245 else 246 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 247 248 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 249 rtw_coex_wl_status_change_notify(rtwdev, 0); 250 251 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 252 stats->rx_cnt > RTW_LPS_THRESHOLD) 253 ps_active = true; 254 else 255 ps_active = false; 256 257 tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT; 258 rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT; 259 260 ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps); 261 ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps); 262 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 263 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 264 265 /* reset tx/rx statictics */ 266 stats->tx_unicast = 0; 267 stats->rx_unicast = 0; 268 stats->tx_cnt = 0; 269 stats->rx_cnt = 0; 270 271 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 272 goto unlock; 273 274 /* make sure BB/RF is working for dynamic mech */ 275 rtw_leave_lps(rtwdev); 276 rtw_coex_wl_status_check(rtwdev); 277 rtw_coex_query_bt_hid_list(rtwdev); 278 rtw_coex_active_query_bt_info(rtwdev); 279 280 rtw_phy_dynamic_mechanism(rtwdev); 281 282 rtw_hci_dynamic_rx_agg(rtwdev, 283 tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1); 284 285 data.rtwdev = rtwdev; 286 /* rtw_iterate_vifs internally uses an atomic iterator which is needed 287 * to avoid taking local->iflist_mtx mutex 288 */ 289 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data); 290 291 rtw_sw_beacon_loss_check(rtwdev, data.rtwvif, received_beacons); 292 293 /* fw supports only one station associated to enter lps, if there are 294 * more than two stations associated to the AP, then we can not enter 295 * lps, because fw does not handle the overlapped beacon interval 296 * 297 * rtw_recalc_lps() iterate vifs and determine if driver can enter 298 * ps by vif->type and vif->cfg.ps, all we need to do here is to 299 * get that vif and check if device is having traffic more than the 300 * threshold. 301 */ 302 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 303 !rtwdev->beacon_loss && !rtwdev->ap_active) 304 rtw_enter_lps(rtwdev, data.rtwvif->port); 305 306 rtwdev->watch_dog_cnt++; 307 308 unlock: 309 mutex_unlock(&rtwdev->mutex); 310 } 311 312 static void rtw_c2h_work(struct work_struct *work) 313 { 314 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 315 struct sk_buff *skb, *tmp; 316 317 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 318 skb_unlink(skb, &rtwdev->c2h_queue); 319 rtw_fw_c2h_cmd_handle(rtwdev, skb); 320 dev_kfree_skb_any(skb); 321 } 322 } 323 324 static void rtw_ips_work(struct work_struct *work) 325 { 326 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 327 328 mutex_lock(&rtwdev->mutex); 329 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 330 rtw_enter_ips(rtwdev); 331 mutex_unlock(&rtwdev->mutex); 332 } 333 334 static void rtw_sta_rc_work(struct work_struct *work) 335 { 336 struct rtw_sta_info *si = container_of(work, struct rtw_sta_info, 337 rc_work); 338 struct rtw_dev *rtwdev = si->rtwdev; 339 340 mutex_lock(&rtwdev->mutex); 341 rtw_update_sta_info(rtwdev, si, true); 342 mutex_unlock(&rtwdev->mutex); 343 } 344 345 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 346 struct ieee80211_vif *vif) 347 { 348 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 349 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 350 int i; 351 352 if (vif->type == NL80211_IFTYPE_STATION) { 353 si->mac_id = rtwvif->mac_id; 354 } else { 355 si->mac_id = rtw_acquire_macid(rtwdev); 356 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 357 return -ENOSPC; 358 } 359 360 si->rtwdev = rtwdev; 361 si->sta = sta; 362 si->vif = vif; 363 si->init_ra_lv = 1; 364 ewma_rssi_init(&si->avg_rssi); 365 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 366 rtw_txq_init(rtwdev, sta->txq[i]); 367 INIT_WORK(&si->rc_work, rtw_sta_rc_work); 368 369 rtw_update_sta_info(rtwdev, si, true); 370 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 371 372 rtwdev->sta_cnt++; 373 rtwdev->beacon_loss = false; 374 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 375 sta->addr, si->mac_id); 376 377 return 0; 378 } 379 380 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 381 bool fw_exist) 382 { 383 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 384 struct ieee80211_vif *vif = si->vif; 385 int i; 386 387 cancel_work_sync(&si->rc_work); 388 389 if (vif->type != NL80211_IFTYPE_STATION) 390 rtw_release_macid(rtwdev, si->mac_id); 391 if (fw_exist) 392 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 393 394 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 395 rtw_txq_cleanup(rtwdev, sta->txq[i]); 396 397 kfree(si->mask); 398 399 rtwdev->sta_cnt--; 400 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 401 sta->addr, si->mac_id); 402 } 403 404 struct rtw_fwcd_hdr { 405 u32 item; 406 u32 size; 407 u32 padding1; 408 u32 padding2; 409 } __packed; 410 411 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 412 { 413 const struct rtw_chip_info *chip = rtwdev->chip; 414 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 415 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 416 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 417 u8 i; 418 419 if (segs) { 420 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 421 422 for (i = 0; i < segs->num; i++) 423 prep_size += segs->segs[i]; 424 } 425 426 desc->data = vmalloc(prep_size); 427 if (!desc->data) 428 return -ENOMEM; 429 430 desc->size = prep_size; 431 desc->next = desc->data; 432 433 return 0; 434 } 435 436 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 437 { 438 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 439 struct rtw_fwcd_hdr *hdr; 440 u8 *next; 441 442 if (!desc->data) { 443 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 444 return NULL; 445 } 446 447 next = desc->next + sizeof(struct rtw_fwcd_hdr); 448 if (next - desc->data + size > desc->size) { 449 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 450 return NULL; 451 } 452 453 hdr = (struct rtw_fwcd_hdr *)(desc->next); 454 hdr->item = item; 455 hdr->size = size; 456 hdr->padding1 = 0x01234567; 457 hdr->padding2 = 0x89abcdef; 458 desc->next = next + size; 459 460 return next; 461 } 462 463 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 464 { 465 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 466 467 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 468 469 /* Data will be freed after lifetime of device coredump. After calling 470 * dev_coredump, data is supposed to be handled by the device coredump 471 * framework. Note that a new dump will be discarded if a previous one 472 * hasn't been released yet. 473 */ 474 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 475 } 476 477 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 478 { 479 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 480 481 if (free_self) { 482 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 483 vfree(desc->data); 484 } 485 486 desc->data = NULL; 487 desc->next = NULL; 488 } 489 490 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 491 { 492 u32 size = rtwdev->chip->fw_rxff_size; 493 u32 *buf; 494 u8 seq; 495 496 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 497 if (!buf) 498 return -ENOMEM; 499 500 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 501 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 502 return -EINVAL; 503 } 504 505 if (GET_FW_DUMP_LEN(buf) == 0) { 506 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 507 return -EINVAL; 508 } 509 510 seq = GET_FW_DUMP_SEQ(buf); 511 if (seq > 0) { 512 rtw_dbg(rtwdev, RTW_DBG_FW, 513 "fw crash dump's seq is wrong: %d\n", seq); 514 return -EINVAL; 515 } 516 517 return 0; 518 } 519 520 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 521 u32 fwcd_item) 522 { 523 u32 rxff = rtwdev->chip->fw_rxff_size; 524 u32 dump_size, done_size = 0; 525 u8 *buf; 526 int ret; 527 528 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 529 if (!buf) 530 return -ENOMEM; 531 532 while (size) { 533 dump_size = size > rxff ? rxff : size; 534 535 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 536 dump_size); 537 if (ret) { 538 rtw_err(rtwdev, 539 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 540 ocp_src, done_size); 541 return ret; 542 } 543 544 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 545 dump_size, (u32 *)(buf + done_size)); 546 if (ret) { 547 rtw_err(rtwdev, 548 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 549 ocp_src, done_size); 550 return ret; 551 } 552 553 size -= dump_size; 554 done_size += dump_size; 555 } 556 557 return 0; 558 } 559 EXPORT_SYMBOL(rtw_dump_fw); 560 561 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 562 { 563 u8 *buf; 564 u32 i; 565 566 if (addr & 0x3) { 567 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 568 return -EINVAL; 569 } 570 571 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 572 if (!buf) 573 return -ENOMEM; 574 575 for (i = 0; i < size; i += 4) 576 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 577 578 return 0; 579 } 580 EXPORT_SYMBOL(rtw_dump_reg); 581 582 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 583 struct ieee80211_bss_conf *conf) 584 { 585 struct ieee80211_vif *vif = NULL; 586 587 if (conf) 588 vif = container_of(conf, struct ieee80211_vif, bss_conf); 589 590 if (conf && vif->cfg.assoc) { 591 rtwvif->aid = vif->cfg.aid; 592 rtwvif->net_type = RTW_NET_MGD_LINKED; 593 } else { 594 rtwvif->aid = 0; 595 rtwvif->net_type = RTW_NET_NO_LINK; 596 } 597 } 598 599 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 600 struct ieee80211_vif *vif, 601 struct ieee80211_sta *sta, 602 struct ieee80211_key_conf *key, 603 void *data) 604 { 605 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 606 struct rtw_sec_desc *sec = &rtwdev->sec; 607 608 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 609 } 610 611 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 612 { 613 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 614 615 if (rtwdev->sta_cnt == 0) { 616 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 617 return; 618 } 619 rtw_sta_remove(rtwdev, sta, false); 620 } 621 622 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 623 { 624 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 625 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 626 627 rtw_bf_disassoc(rtwdev, vif, NULL); 628 rtw_vif_assoc_changed(rtwvif, NULL); 629 rtw_txq_cleanup(rtwdev, vif->txq); 630 631 rtw_release_macid(rtwdev, rtwvif->mac_id); 632 } 633 634 void rtw_fw_recovery(struct rtw_dev *rtwdev) 635 { 636 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 637 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 638 } 639 640 static void __fw_recovery_work(struct rtw_dev *rtwdev) 641 { 642 int ret = 0; 643 644 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 645 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 646 647 ret = rtw_fwcd_prep(rtwdev); 648 if (ret) 649 goto free; 650 ret = rtw_fw_dump_crash_log(rtwdev); 651 if (ret) 652 goto free; 653 ret = rtw_chip_dump_fw_crash(rtwdev); 654 if (ret) 655 goto free; 656 657 rtw_fwcd_dump(rtwdev); 658 free: 659 rtw_fwcd_free(rtwdev, !!ret); 660 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 661 662 WARN(1, "firmware crash, start reset and recover\n"); 663 664 rcu_read_lock(); 665 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 666 rcu_read_unlock(); 667 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 668 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 669 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM); 670 rtw_enter_ips(rtwdev); 671 } 672 673 static void rtw_fw_recovery_work(struct work_struct *work) 674 { 675 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 676 fw_recovery_work); 677 678 mutex_lock(&rtwdev->mutex); 679 __fw_recovery_work(rtwdev); 680 mutex_unlock(&rtwdev->mutex); 681 682 ieee80211_restart_hw(rtwdev->hw); 683 } 684 685 struct rtw_txq_ba_iter_data { 686 }; 687 688 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 689 { 690 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 691 int ret; 692 u8 tid; 693 694 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 695 while (tid != IEEE80211_NUM_TIDS) { 696 clear_bit(tid, si->tid_ba); 697 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 698 if (ret == -EINVAL) { 699 struct ieee80211_txq *txq; 700 struct rtw_txq *rtwtxq; 701 702 txq = sta->txq[tid]; 703 rtwtxq = (struct rtw_txq *)txq->drv_priv; 704 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 705 } 706 707 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 708 } 709 } 710 711 static void rtw_txq_ba_work(struct work_struct *work) 712 { 713 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 714 struct rtw_txq_ba_iter_data data; 715 716 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 717 } 718 719 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 720 { 721 if (IS_CH_2G_BAND(channel)) 722 pkt_stat->band = NL80211_BAND_2GHZ; 723 else if (IS_CH_5G_BAND(channel)) 724 pkt_stat->band = NL80211_BAND_5GHZ; 725 else 726 return; 727 728 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 729 } 730 EXPORT_SYMBOL(rtw_set_rx_freq_band); 731 732 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 733 { 734 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 735 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 736 } 737 738 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 739 u8 primary_channel, enum rtw_supported_band band, 740 enum rtw_bandwidth bandwidth) 741 { 742 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band); 743 struct rtw_hal *hal = &rtwdev->hal; 744 u8 *cch_by_bw = hal->cch_by_bw; 745 u32 center_freq, primary_freq; 746 enum rtw_sar_bands sar_band; 747 u8 primary_channel_idx; 748 749 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band); 750 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band); 751 752 /* assign the center channel used while 20M bw is selected */ 753 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel; 754 755 /* assign the center channel used while current bw is selected */ 756 cch_by_bw[bandwidth] = center_channel; 757 758 switch (bandwidth) { 759 case RTW_CHANNEL_WIDTH_20: 760 default: 761 primary_channel_idx = RTW_SC_DONT_CARE; 762 break; 763 case RTW_CHANNEL_WIDTH_40: 764 if (primary_freq > center_freq) 765 primary_channel_idx = RTW_SC_20_UPPER; 766 else 767 primary_channel_idx = RTW_SC_20_LOWER; 768 break; 769 case RTW_CHANNEL_WIDTH_80: 770 if (primary_freq > center_freq) { 771 if (primary_freq - center_freq == 10) 772 primary_channel_idx = RTW_SC_20_UPPER; 773 else 774 primary_channel_idx = RTW_SC_20_UPMOST; 775 776 /* assign the center channel used 777 * while 40M bw is selected 778 */ 779 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4; 780 } else { 781 if (center_freq - primary_freq == 10) 782 primary_channel_idx = RTW_SC_20_LOWER; 783 else 784 primary_channel_idx = RTW_SC_20_LOWEST; 785 786 /* assign the center channel used 787 * while 40M bw is selected 788 */ 789 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4; 790 } 791 break; 792 } 793 794 switch (center_channel) { 795 case 1 ... 14: 796 sar_band = RTW_SAR_BAND_0; 797 break; 798 case 36 ... 64: 799 sar_band = RTW_SAR_BAND_1; 800 break; 801 case 100 ... 144: 802 sar_band = RTW_SAR_BAND_3; 803 break; 804 case 149 ... 177: 805 sar_band = RTW_SAR_BAND_4; 806 break; 807 default: 808 WARN(1, "unknown ch(%u) to SAR band\n", center_channel); 809 sar_band = RTW_SAR_BAND_0; 810 break; 811 } 812 813 hal->current_primary_channel_index = primary_channel_idx; 814 hal->current_band_width = bandwidth; 815 hal->primary_channel = primary_channel; 816 hal->current_channel = center_channel; 817 hal->current_band_type = band; 818 hal->sar_band = sar_band; 819 } 820 821 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 822 struct rtw_channel_params *chan_params) 823 { 824 struct ieee80211_channel *channel = chandef->chan; 825 enum nl80211_chan_width width = chandef->width; 826 u32 primary_freq, center_freq; 827 u8 center_chan; 828 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 829 830 center_chan = channel->hw_value; 831 primary_freq = channel->center_freq; 832 center_freq = chandef->center_freq1; 833 834 switch (width) { 835 case NL80211_CHAN_WIDTH_20_NOHT: 836 case NL80211_CHAN_WIDTH_20: 837 bandwidth = RTW_CHANNEL_WIDTH_20; 838 break; 839 case NL80211_CHAN_WIDTH_40: 840 bandwidth = RTW_CHANNEL_WIDTH_40; 841 if (primary_freq > center_freq) 842 center_chan -= 2; 843 else 844 center_chan += 2; 845 break; 846 case NL80211_CHAN_WIDTH_80: 847 bandwidth = RTW_CHANNEL_WIDTH_80; 848 if (primary_freq > center_freq) { 849 if (primary_freq - center_freq == 10) 850 center_chan -= 2; 851 else 852 center_chan -= 6; 853 } else { 854 if (center_freq - primary_freq == 10) 855 center_chan += 2; 856 else 857 center_chan += 6; 858 } 859 break; 860 default: 861 center_chan = 0; 862 break; 863 } 864 865 chan_params->center_chan = center_chan; 866 chan_params->bandwidth = bandwidth; 867 chan_params->primary_chan = channel->hw_value; 868 } 869 870 void rtw_set_channel(struct rtw_dev *rtwdev) 871 { 872 const struct rtw_chip_info *chip = rtwdev->chip; 873 struct ieee80211_hw *hw = rtwdev->hw; 874 struct rtw_hal *hal = &rtwdev->hal; 875 struct rtw_channel_params ch_param; 876 u8 center_chan, primary_chan, bandwidth, band; 877 878 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 879 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 880 return; 881 882 center_chan = ch_param.center_chan; 883 primary_chan = ch_param.primary_chan; 884 bandwidth = ch_param.bandwidth; 885 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 886 887 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth); 888 889 if (rtwdev->scan_info.op_chan) 890 rtw_store_op_chan(rtwdev, true); 891 892 chip->ops->set_channel(rtwdev, center_chan, bandwidth, 893 hal->current_primary_channel_index); 894 895 if (hal->current_band_type == RTW_BAND_5G) { 896 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 897 } else { 898 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 899 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 900 else 901 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 902 } 903 904 rtw_phy_set_tx_power_level(rtwdev, center_chan); 905 906 /* if the channel isn't set for scanning, we will do RF calibration 907 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 908 * during scanning on each channel takes too long. 909 */ 910 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 911 rtwdev->need_rfk = true; 912 } 913 914 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 915 { 916 const struct rtw_chip_info *chip = rtwdev->chip; 917 918 if (rtwdev->need_rfk) { 919 rtwdev->need_rfk = false; 920 chip->ops->phy_calibration(rtwdev); 921 } 922 } 923 924 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 925 { 926 int i; 927 928 for (i = 0; i < ETH_ALEN; i++) 929 rtw_write8(rtwdev, start + i, addr[i]); 930 } 931 932 void rtw_vif_port_config(struct rtw_dev *rtwdev, 933 struct rtw_vif *rtwvif, 934 u32 config) 935 { 936 u32 addr, mask; 937 938 if (config & PORT_SET_MAC_ADDR) { 939 addr = rtwvif->conf->mac_addr.addr; 940 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 941 } 942 if (config & PORT_SET_BSSID) { 943 addr = rtwvif->conf->bssid.addr; 944 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 945 } 946 if (config & PORT_SET_NET_TYPE) { 947 addr = rtwvif->conf->net_type.addr; 948 mask = rtwvif->conf->net_type.mask; 949 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 950 } 951 if (config & PORT_SET_AID) { 952 addr = rtwvif->conf->aid.addr; 953 mask = rtwvif->conf->aid.mask; 954 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 955 } 956 if (config & PORT_SET_BCN_CTRL) { 957 addr = rtwvif->conf->bcn_ctrl.addr; 958 mask = rtwvif->conf->bcn_ctrl.mask; 959 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 960 } 961 } 962 963 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 964 { 965 u8 bw = 0; 966 967 switch (bw_cap) { 968 case EFUSE_HW_CAP_IGNORE: 969 case EFUSE_HW_CAP_SUPP_BW80: 970 bw |= BIT(RTW_CHANNEL_WIDTH_80); 971 fallthrough; 972 case EFUSE_HW_CAP_SUPP_BW40: 973 bw |= BIT(RTW_CHANNEL_WIDTH_40); 974 fallthrough; 975 default: 976 bw |= BIT(RTW_CHANNEL_WIDTH_20); 977 break; 978 } 979 980 return bw; 981 } 982 983 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 984 { 985 const struct rtw_chip_info *chip = rtwdev->chip; 986 struct rtw_hal *hal = &rtwdev->hal; 987 988 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 989 hw_ant_num >= hal->rf_path_num) 990 return; 991 992 switch (hw_ant_num) { 993 case 1: 994 hal->rf_type = RF_1T1R; 995 hal->rf_path_num = 1; 996 if (!chip->fix_rf_phy_num) 997 hal->rf_phy_num = hal->rf_path_num; 998 hal->antenna_tx = BB_PATH_A; 999 hal->antenna_rx = BB_PATH_A; 1000 break; 1001 default: 1002 WARN(1, "invalid hw configuration from efuse\n"); 1003 break; 1004 } 1005 } 1006 1007 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 1008 { 1009 u64 ra_mask = 0; 1010 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 1011 u8 vht_mcs_cap; 1012 int i, nss; 1013 1014 /* 4SS, every two bits for MCS7/8/9 */ 1015 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 1016 vht_mcs_cap = mcs_map & 0x3; 1017 switch (vht_mcs_cap) { 1018 case 2: /* MCS9 */ 1019 ra_mask |= 0x3ffULL << nss; 1020 break; 1021 case 1: /* MCS8 */ 1022 ra_mask |= 0x1ffULL << nss; 1023 break; 1024 case 0: /* MCS7 */ 1025 ra_mask |= 0x0ffULL << nss; 1026 break; 1027 default: 1028 break; 1029 } 1030 } 1031 1032 return ra_mask; 1033 } 1034 1035 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 1036 { 1037 u8 rate_id = 0; 1038 1039 switch (wireless_set) { 1040 case WIRELESS_CCK: 1041 rate_id = RTW_RATEID_B_20M; 1042 break; 1043 case WIRELESS_OFDM: 1044 rate_id = RTW_RATEID_G; 1045 break; 1046 case WIRELESS_CCK | WIRELESS_OFDM: 1047 rate_id = RTW_RATEID_BG; 1048 break; 1049 case WIRELESS_OFDM | WIRELESS_HT: 1050 if (tx_num == 1) 1051 rate_id = RTW_RATEID_GN_N1SS; 1052 else if (tx_num == 2) 1053 rate_id = RTW_RATEID_GN_N2SS; 1054 else if (tx_num == 3) 1055 rate_id = RTW_RATEID_ARFR5_N_3SS; 1056 break; 1057 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 1058 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 1059 if (tx_num == 1) 1060 rate_id = RTW_RATEID_BGN_40M_1SS; 1061 else if (tx_num == 2) 1062 rate_id = RTW_RATEID_BGN_40M_2SS; 1063 else if (tx_num == 3) 1064 rate_id = RTW_RATEID_ARFR5_N_3SS; 1065 else if (tx_num == 4) 1066 rate_id = RTW_RATEID_ARFR7_N_4SS; 1067 } else { 1068 if (tx_num == 1) 1069 rate_id = RTW_RATEID_BGN_20M_1SS; 1070 else if (tx_num == 2) 1071 rate_id = RTW_RATEID_BGN_20M_2SS; 1072 else if (tx_num == 3) 1073 rate_id = RTW_RATEID_ARFR5_N_3SS; 1074 else if (tx_num == 4) 1075 rate_id = RTW_RATEID_ARFR7_N_4SS; 1076 } 1077 break; 1078 case WIRELESS_OFDM | WIRELESS_VHT: 1079 if (tx_num == 1) 1080 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1081 else if (tx_num == 2) 1082 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1083 else if (tx_num == 3) 1084 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1085 else if (tx_num == 4) 1086 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1087 break; 1088 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 1089 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 1090 if (tx_num == 1) 1091 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1092 else if (tx_num == 2) 1093 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1094 else if (tx_num == 3) 1095 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1096 else if (tx_num == 4) 1097 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1098 } else { 1099 if (tx_num == 1) 1100 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1101 else if (tx_num == 2) 1102 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1103 else if (tx_num == 3) 1104 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1105 else if (tx_num == 4) 1106 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1107 } 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 return rate_id; 1114 } 1115 1116 #define RA_MASK_CCK_RATES 0x0000f 1117 #define RA_MASK_OFDM_RATES 0x00ff0 1118 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1119 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1120 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1121 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1122 RA_MASK_HT_RATES_2SS | \ 1123 RA_MASK_HT_RATES_3SS) 1124 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1125 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1126 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1127 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1128 RA_MASK_VHT_RATES_2SS | \ 1129 RA_MASK_VHT_RATES_3SS) 1130 #define RA_MASK_CCK_IN_BG 0x00005 1131 #define RA_MASK_CCK_IN_HT 0x00005 1132 #define RA_MASK_CCK_IN_VHT 0x00005 1133 #define RA_MASK_OFDM_IN_VHT 0x00010 1134 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1135 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1136 1137 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1138 { 1139 u8 rssi_level = si->rssi_level; 1140 1141 if (wireless_set == WIRELESS_CCK) 1142 return 0xffffffffffffffffULL; 1143 1144 if (rssi_level == 0) 1145 return 0xffffffffffffffffULL; 1146 else if (rssi_level == 1) 1147 return 0xfffffffffffffff0ULL; 1148 else if (rssi_level == 2) 1149 return 0xffffffffffffefe0ULL; 1150 else if (rssi_level == 3) 1151 return 0xffffffffffffcfc0ULL; 1152 else if (rssi_level == 4) 1153 return 0xffffffffffff8f80ULL; 1154 else 1155 return 0xffffffffffff0f00ULL; 1156 } 1157 1158 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1159 { 1160 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1161 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1162 1163 if (ra_mask == 0) 1164 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1165 1166 return ra_mask; 1167 } 1168 1169 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1170 u64 ra_mask, bool is_vht_enable) 1171 { 1172 struct rtw_hal *hal = &rtwdev->hal; 1173 const struct cfg80211_bitrate_mask *mask = si->mask; 1174 u64 cfg_mask = GENMASK_ULL(63, 0); 1175 u8 band; 1176 1177 if (!si->use_cfg_mask) 1178 return ra_mask; 1179 1180 band = hal->current_band_type; 1181 if (band == RTW_BAND_2G) { 1182 band = NL80211_BAND_2GHZ; 1183 cfg_mask = mask->control[band].legacy; 1184 } else if (band == RTW_BAND_5G) { 1185 band = NL80211_BAND_5GHZ; 1186 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1187 RA_MASK_OFDM_RATES); 1188 } 1189 1190 if (!is_vht_enable) { 1191 if (ra_mask & RA_MASK_HT_RATES_1SS) 1192 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1193 RA_MASK_HT_RATES_1SS); 1194 if (ra_mask & RA_MASK_HT_RATES_2SS) 1195 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1196 RA_MASK_HT_RATES_2SS); 1197 } else { 1198 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1199 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1200 RA_MASK_VHT_RATES_1SS); 1201 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1202 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1203 RA_MASK_VHT_RATES_2SS); 1204 } 1205 1206 ra_mask &= cfg_mask; 1207 1208 return ra_mask; 1209 } 1210 1211 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1212 bool reset_ra_mask) 1213 { 1214 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1215 struct ieee80211_sta *sta = si->sta; 1216 struct rtw_efuse *efuse = &rtwdev->efuse; 1217 struct rtw_hal *hal = &rtwdev->hal; 1218 u8 wireless_set; 1219 u8 bw_mode; 1220 u8 rate_id; 1221 u8 stbc_en = 0; 1222 u8 ldpc_en = 0; 1223 u8 tx_num = 1; 1224 u64 ra_mask = 0; 1225 u64 ra_mask_bak = 0; 1226 bool is_vht_enable = false; 1227 bool is_support_sgi = false; 1228 1229 if (sta->deflink.vht_cap.vht_supported) { 1230 is_vht_enable = true; 1231 ra_mask |= get_vht_ra_mask(sta); 1232 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1233 stbc_en = VHT_STBC_EN; 1234 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1235 ldpc_en = VHT_LDPC_EN; 1236 } else if (sta->deflink.ht_cap.ht_supported) { 1237 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 36) | 1238 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 28) | 1239 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1240 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1241 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1242 stbc_en = HT_STBC_EN; 1243 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1244 ldpc_en = HT_LDPC_EN; 1245 } 1246 1247 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1248 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1249 else if (efuse->hw_cap.nss == 2) 1250 ra_mask &= RA_MASK_VHT_RATES_2SS | RA_MASK_HT_RATES_2SS | 1251 RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1252 1253 if (hal->current_band_type == RTW_BAND_5G) { 1254 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1255 ra_mask_bak = ra_mask; 1256 if (sta->deflink.vht_cap.vht_supported) { 1257 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1258 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1259 } else if (sta->deflink.ht_cap.ht_supported) { 1260 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1261 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1262 } else { 1263 wireless_set = WIRELESS_OFDM; 1264 } 1265 dm_info->rrsr_val_init = RRSR_INIT_5G; 1266 } else if (hal->current_band_type == RTW_BAND_2G) { 1267 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1268 ra_mask_bak = ra_mask; 1269 if (sta->deflink.vht_cap.vht_supported) { 1270 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1271 RA_MASK_OFDM_IN_VHT; 1272 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1273 WIRELESS_HT | WIRELESS_VHT; 1274 } else if (sta->deflink.ht_cap.ht_supported) { 1275 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1276 RA_MASK_OFDM_IN_HT_2G; 1277 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1278 WIRELESS_HT; 1279 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1280 wireless_set = WIRELESS_CCK; 1281 } else { 1282 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1283 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1284 } 1285 dm_info->rrsr_val_init = RRSR_INIT_2G; 1286 } else { 1287 rtw_err(rtwdev, "Unknown band type\n"); 1288 ra_mask_bak = ra_mask; 1289 wireless_set = 0; 1290 } 1291 1292 switch (sta->deflink.bandwidth) { 1293 case IEEE80211_STA_RX_BW_80: 1294 bw_mode = RTW_CHANNEL_WIDTH_80; 1295 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1296 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1297 break; 1298 case IEEE80211_STA_RX_BW_40: 1299 bw_mode = RTW_CHANNEL_WIDTH_40; 1300 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1301 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1302 break; 1303 default: 1304 bw_mode = RTW_CHANNEL_WIDTH_20; 1305 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1306 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1307 break; 1308 } 1309 1310 if (sta->deflink.vht_cap.vht_supported || 1311 sta->deflink.ht_cap.ht_supported) 1312 tx_num = efuse->hw_cap.nss; 1313 1314 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1315 1316 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1317 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1318 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1319 1320 si->bw_mode = bw_mode; 1321 si->stbc_en = stbc_en; 1322 si->ldpc_en = ldpc_en; 1323 si->sgi_enable = is_support_sgi; 1324 si->vht_enable = is_vht_enable; 1325 si->ra_mask = ra_mask; 1326 si->rate_id = rate_id; 1327 1328 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1329 } 1330 1331 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1332 { 1333 const struct rtw_chip_info *chip = rtwdev->chip; 1334 struct rtw_fw_state *fw; 1335 int ret = 0; 1336 1337 fw = &rtwdev->fw; 1338 wait_for_completion(&fw->completion); 1339 if (!fw->firmware) 1340 ret = -EINVAL; 1341 1342 if (chip->wow_fw_name) { 1343 fw = &rtwdev->wow_fw; 1344 wait_for_completion(&fw->completion); 1345 if (!fw->firmware) 1346 ret = -EINVAL; 1347 } 1348 1349 return ret; 1350 } 1351 EXPORT_SYMBOL(rtw_wait_firmware_completion); 1352 1353 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1354 struct rtw_fw_state *fw) 1355 { 1356 const struct rtw_chip_info *chip = rtwdev->chip; 1357 1358 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1359 !fw->feature) 1360 return LPS_DEEP_MODE_NONE; 1361 1362 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1363 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1364 return LPS_DEEP_MODE_PG; 1365 1366 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1367 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1368 return LPS_DEEP_MODE_LCLK; 1369 1370 return LPS_DEEP_MODE_NONE; 1371 } 1372 1373 int rtw_power_on(struct rtw_dev *rtwdev) 1374 { 1375 const struct rtw_chip_info *chip = rtwdev->chip; 1376 struct rtw_fw_state *fw = &rtwdev->fw; 1377 bool wifi_only; 1378 int ret; 1379 1380 ret = rtw_hci_setup(rtwdev); 1381 if (ret) { 1382 rtw_err(rtwdev, "failed to setup hci\n"); 1383 goto err; 1384 } 1385 1386 /* power on MAC before firmware downloaded */ 1387 ret = rtw_mac_power_on(rtwdev); 1388 if (ret) { 1389 rtw_err(rtwdev, "failed to power on mac\n"); 1390 goto err; 1391 } 1392 1393 ret = rtw_wait_firmware_completion(rtwdev); 1394 if (ret) { 1395 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1396 goto err_off; 1397 } 1398 1399 ret = rtw_download_firmware(rtwdev, fw); 1400 if (ret) { 1401 rtw_err(rtwdev, "failed to download firmware\n"); 1402 goto err_off; 1403 } 1404 1405 /* config mac after firmware downloaded */ 1406 ret = rtw_mac_init(rtwdev); 1407 if (ret) { 1408 rtw_err(rtwdev, "failed to configure mac\n"); 1409 goto err_off; 1410 } 1411 1412 chip->ops->phy_set_param(rtwdev); 1413 1414 ret = rtw_hci_start(rtwdev); 1415 if (ret) { 1416 rtw_err(rtwdev, "failed to start hci\n"); 1417 goto err_off; 1418 } 1419 1420 /* send H2C after HCI has started */ 1421 rtw_fw_send_general_info(rtwdev); 1422 rtw_fw_send_phydm_info(rtwdev); 1423 1424 wifi_only = !rtwdev->efuse.btcoex; 1425 rtw_coex_power_on_setting(rtwdev); 1426 rtw_coex_init_hw_config(rtwdev, wifi_only); 1427 1428 return 0; 1429 1430 err_off: 1431 rtw_mac_power_off(rtwdev); 1432 1433 err: 1434 return ret; 1435 } 1436 EXPORT_SYMBOL(rtw_power_on); 1437 1438 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1439 { 1440 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1441 return; 1442 1443 if (start) { 1444 rtw_fw_scan_notify(rtwdev, true); 1445 } else { 1446 reinit_completion(&rtwdev->fw_scan_density); 1447 rtw_fw_scan_notify(rtwdev, false); 1448 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1449 SCAN_NOTIFY_TIMEOUT)) 1450 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1451 } 1452 } 1453 1454 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1455 const u8 *mac_addr, bool hw_scan) 1456 { 1457 u32 config = 0; 1458 int ret = 0; 1459 1460 rtw_leave_lps(rtwdev); 1461 1462 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1463 ret = rtw_leave_ips(rtwdev); 1464 if (ret) { 1465 rtw_err(rtwdev, "failed to leave idle state\n"); 1466 return; 1467 } 1468 } 1469 1470 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1471 config |= PORT_SET_MAC_ADDR; 1472 rtw_vif_port_config(rtwdev, rtwvif, config); 1473 1474 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1475 rtw_core_fw_scan_notify(rtwdev, true); 1476 1477 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1478 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1479 } 1480 1481 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1482 bool hw_scan) 1483 { 1484 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1485 u32 config = 0; 1486 1487 if (!rtwvif) 1488 return; 1489 1490 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1491 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1492 1493 rtw_core_fw_scan_notify(rtwdev, false); 1494 1495 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1496 config |= PORT_SET_MAC_ADDR; 1497 rtw_vif_port_config(rtwdev, rtwvif, config); 1498 1499 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1500 1501 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1502 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1503 } 1504 1505 int rtw_core_start(struct rtw_dev *rtwdev) 1506 { 1507 int ret; 1508 1509 ret = rtwdev->chip->ops->power_on(rtwdev); 1510 if (ret) 1511 return ret; 1512 1513 rtw_sec_enable_sec_engine(rtwdev); 1514 1515 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1516 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1517 1518 /* rcr reset after powered on */ 1519 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1520 1521 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1522 RTW_WATCH_DOG_DELAY_TIME); 1523 1524 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1525 1526 return 0; 1527 } 1528 1529 void rtw_power_off(struct rtw_dev *rtwdev) 1530 { 1531 rtw_hci_stop(rtwdev); 1532 rtw_coex_power_off_setting(rtwdev); 1533 rtw_mac_power_off(rtwdev); 1534 } 1535 EXPORT_SYMBOL(rtw_power_off); 1536 1537 void rtw_core_stop(struct rtw_dev *rtwdev) 1538 { 1539 struct rtw_coex *coex = &rtwdev->coex; 1540 1541 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1542 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1543 1544 mutex_unlock(&rtwdev->mutex); 1545 1546 cancel_work_sync(&rtwdev->c2h_work); 1547 cancel_work_sync(&rtwdev->update_beacon_work); 1548 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1549 cancel_delayed_work_sync(&coex->bt_relink_work); 1550 cancel_delayed_work_sync(&coex->bt_reenable_work); 1551 cancel_delayed_work_sync(&coex->defreeze_work); 1552 cancel_delayed_work_sync(&coex->wl_remain_work); 1553 cancel_delayed_work_sync(&coex->bt_remain_work); 1554 cancel_delayed_work_sync(&coex->wl_connecting_work); 1555 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1556 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1557 1558 mutex_lock(&rtwdev->mutex); 1559 1560 rtwdev->chip->ops->power_off(rtwdev); 1561 } 1562 1563 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1564 struct ieee80211_sta_ht_cap *ht_cap) 1565 { 1566 const struct rtw_chip_info *chip = rtwdev->chip; 1567 struct rtw_efuse *efuse = &rtwdev->efuse; 1568 1569 ht_cap->ht_supported = true; 1570 ht_cap->cap = 0; 1571 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1572 IEEE80211_HT_CAP_MAX_AMSDU | 1573 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1574 1575 if (rtw_chip_has_rx_ldpc(rtwdev)) 1576 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1577 if (rtw_chip_has_tx_stbc(rtwdev)) 1578 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1579 1580 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1581 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1582 IEEE80211_HT_CAP_DSSSCCK40 | 1583 IEEE80211_HT_CAP_SGI_40; 1584 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1585 ht_cap->ampdu_density = chip->ampdu_density; 1586 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1587 if (efuse->hw_cap.nss > 1) { 1588 ht_cap->mcs.rx_mask[0] = 0xFF; 1589 ht_cap->mcs.rx_mask[1] = 0xFF; 1590 ht_cap->mcs.rx_mask[4] = 0x01; 1591 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1592 } else { 1593 ht_cap->mcs.rx_mask[0] = 0xFF; 1594 ht_cap->mcs.rx_mask[1] = 0x00; 1595 ht_cap->mcs.rx_mask[4] = 0x01; 1596 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1597 } 1598 } 1599 1600 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1601 struct ieee80211_sta_vht_cap *vht_cap) 1602 { 1603 struct rtw_efuse *efuse = &rtwdev->efuse; 1604 u16 mcs_map; 1605 __le16 highest; 1606 1607 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1608 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1609 return; 1610 1611 vht_cap->vht_supported = true; 1612 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1613 IEEE80211_VHT_CAP_SHORT_GI_80 | 1614 IEEE80211_VHT_CAP_RXSTBC_1 | 1615 IEEE80211_VHT_CAP_HTC_VHT | 1616 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1617 0; 1618 if (rtwdev->hal.rf_path_num > 1) 1619 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1620 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1621 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1622 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1623 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1624 1625 if (rtw_chip_has_rx_ldpc(rtwdev)) 1626 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1627 1628 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1629 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1630 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1631 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1632 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1633 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1634 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1635 if (efuse->hw_cap.nss > 1) { 1636 highest = cpu_to_le16(780); 1637 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1638 } else { 1639 highest = cpu_to_le16(390); 1640 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1641 } 1642 1643 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1644 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1645 vht_cap->vht_mcs.rx_highest = highest; 1646 vht_cap->vht_mcs.tx_highest = highest; 1647 } 1648 1649 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev) 1650 { 1651 u16 len; 1652 1653 len = rtwdev->chip->max_scan_ie_len; 1654 1655 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) && 1656 rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 1657 len = IEEE80211_MAX_DATA_LEN; 1658 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM)) 1659 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE; 1660 1661 return len; 1662 } 1663 1664 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1665 const struct rtw_chip_info *chip) 1666 { 1667 struct rtw_dev *rtwdev = hw->priv; 1668 struct ieee80211_supported_band *sband; 1669 1670 if (chip->band & RTW_BAND_2G) { 1671 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1672 if (!sband) 1673 goto err_out; 1674 if (chip->ht_supported) 1675 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1676 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1677 } 1678 1679 if (chip->band & RTW_BAND_5G) { 1680 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1681 if (!sband) 1682 goto err_out; 1683 if (chip->ht_supported) 1684 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1685 if (chip->vht_supported) 1686 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1687 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1688 } 1689 1690 return; 1691 1692 err_out: 1693 rtw_err(rtwdev, "failed to set supported band\n"); 1694 } 1695 1696 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1697 const struct rtw_chip_info *chip) 1698 { 1699 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1700 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1701 } 1702 1703 static void rtw_vif_smps_iter(void *data, u8 *mac, 1704 struct ieee80211_vif *vif) 1705 { 1706 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1707 1708 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 1709 return; 1710 1711 if (rtwdev->hal.txrx_1ss) 1712 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); 1713 else 1714 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); 1715 } 1716 1717 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1718 { 1719 const struct rtw_chip_info *chip = rtwdev->chip; 1720 struct rtw_hal *hal = &rtwdev->hal; 1721 1722 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1723 return; 1724 1725 rtwdev->hal.txrx_1ss = txrx_1ss; 1726 if (txrx_1ss) 1727 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1728 else 1729 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1730 hal->antenna_rx, false); 1731 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1732 } 1733 1734 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1735 struct rtw_fw_state *fw) 1736 { 1737 u32 feature; 1738 const struct rtw_fw_hdr *fw_hdr = 1739 (const struct rtw_fw_hdr *)fw->firmware->data; 1740 1741 feature = le32_to_cpu(fw_hdr->feature); 1742 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1743 1744 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C && 1745 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13)) 1746 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM; 1747 } 1748 1749 static void __update_firmware_info(struct rtw_dev *rtwdev, 1750 struct rtw_fw_state *fw) 1751 { 1752 const struct rtw_fw_hdr *fw_hdr = 1753 (const struct rtw_fw_hdr *)fw->firmware->data; 1754 1755 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1756 fw->version = le16_to_cpu(fw_hdr->version); 1757 fw->sub_version = fw_hdr->subversion; 1758 fw->sub_index = fw_hdr->subindex; 1759 1760 __update_firmware_feature(rtwdev, fw); 1761 } 1762 1763 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1764 struct rtw_fw_state *fw) 1765 { 1766 struct rtw_fw_hdr_legacy *legacy = 1767 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1768 1769 fw->h2c_version = 0; 1770 fw->version = le16_to_cpu(legacy->version); 1771 fw->sub_version = legacy->subversion1; 1772 fw->sub_index = legacy->subversion2; 1773 } 1774 1775 static void update_firmware_info(struct rtw_dev *rtwdev, 1776 struct rtw_fw_state *fw) 1777 { 1778 if (rtw_chip_wcpu_11n(rtwdev)) 1779 __update_firmware_info_legacy(rtwdev, fw); 1780 else 1781 __update_firmware_info(rtwdev, fw); 1782 } 1783 1784 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1785 { 1786 struct rtw_fw_state *fw = context; 1787 struct rtw_dev *rtwdev = fw->rtwdev; 1788 1789 if (!firmware || !firmware->data) { 1790 rtw_err(rtwdev, "failed to request firmware\n"); 1791 complete_all(&fw->completion); 1792 return; 1793 } 1794 1795 fw->firmware = firmware; 1796 update_firmware_info(rtwdev, fw); 1797 complete_all(&fw->completion); 1798 1799 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n", 1800 fw->type == RTW_WOWLAN_FW ? "WOW " : "", 1801 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1802 } 1803 1804 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1805 { 1806 const char *fw_name; 1807 struct rtw_fw_state *fw; 1808 int ret; 1809 1810 switch (type) { 1811 case RTW_WOWLAN_FW: 1812 fw = &rtwdev->wow_fw; 1813 fw_name = rtwdev->chip->wow_fw_name; 1814 break; 1815 1816 case RTW_NORMAL_FW: 1817 fw = &rtwdev->fw; 1818 fw_name = rtwdev->chip->fw_name; 1819 break; 1820 1821 default: 1822 rtw_warn(rtwdev, "unsupported firmware type\n"); 1823 return -ENOENT; 1824 } 1825 1826 fw->type = type; 1827 fw->rtwdev = rtwdev; 1828 init_completion(&fw->completion); 1829 1830 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1831 GFP_KERNEL, fw, rtw_load_firmware_cb); 1832 if (ret) { 1833 rtw_err(rtwdev, "failed to async firmware request\n"); 1834 return ret; 1835 } 1836 1837 return 0; 1838 } 1839 1840 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1841 { 1842 const struct rtw_chip_info *chip = rtwdev->chip; 1843 struct rtw_hal *hal = &rtwdev->hal; 1844 struct rtw_efuse *efuse = &rtwdev->efuse; 1845 1846 switch (rtw_hci_type(rtwdev)) { 1847 case RTW_HCI_TYPE_PCIE: 1848 rtwdev->hci.rpwm_addr = 0x03d9; 1849 rtwdev->hci.cpwm_addr = 0x03da; 1850 break; 1851 case RTW_HCI_TYPE_SDIO: 1852 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1; 1853 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2; 1854 break; 1855 case RTW_HCI_TYPE_USB: 1856 rtwdev->hci.rpwm_addr = 0xfe58; 1857 rtwdev->hci.cpwm_addr = 0xfe57; 1858 break; 1859 default: 1860 rtw_err(rtwdev, "unsupported hci type\n"); 1861 return -EINVAL; 1862 } 1863 1864 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1865 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1866 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1867 if (hal->chip_version & BIT_RF_TYPE_ID) { 1868 hal->rf_type = RF_2T2R; 1869 hal->rf_path_num = 2; 1870 hal->antenna_tx = BB_PATH_AB; 1871 hal->antenna_rx = BB_PATH_AB; 1872 } else { 1873 hal->rf_type = RF_1T1R; 1874 hal->rf_path_num = 1; 1875 hal->antenna_tx = BB_PATH_A; 1876 hal->antenna_rx = BB_PATH_A; 1877 } 1878 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1879 hal->rf_path_num; 1880 1881 efuse->physical_size = chip->phy_efuse_size; 1882 efuse->logical_size = chip->log_efuse_size; 1883 efuse->protect_size = chip->ptct_efuse_size; 1884 1885 /* default use ack */ 1886 rtwdev->hal.rcr |= BIT_VHT_DACK; 1887 1888 hal->bfee_sts_cap = 3; 1889 1890 return 0; 1891 } 1892 1893 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1894 { 1895 struct rtw_fw_state *fw = &rtwdev->fw; 1896 int ret; 1897 1898 ret = rtw_hci_setup(rtwdev); 1899 if (ret) { 1900 rtw_err(rtwdev, "failed to setup hci\n"); 1901 goto err; 1902 } 1903 1904 ret = rtw_mac_power_on(rtwdev); 1905 if (ret) { 1906 rtw_err(rtwdev, "failed to power on mac\n"); 1907 goto err; 1908 } 1909 1910 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1911 1912 wait_for_completion(&fw->completion); 1913 if (!fw->firmware) { 1914 ret = -EINVAL; 1915 rtw_err(rtwdev, "failed to load firmware\n"); 1916 goto err; 1917 } 1918 1919 ret = rtw_download_firmware(rtwdev, fw); 1920 if (ret) { 1921 rtw_err(rtwdev, "failed to download firmware\n"); 1922 goto err_off; 1923 } 1924 1925 return 0; 1926 1927 err_off: 1928 rtw_mac_power_off(rtwdev); 1929 1930 err: 1931 return ret; 1932 } 1933 1934 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1935 { 1936 struct rtw_efuse *efuse = &rtwdev->efuse; 1937 u8 hw_feature[HW_FEATURE_LEN]; 1938 u8 id; 1939 u8 bw; 1940 int i; 1941 1942 if (!rtwdev->chip->hw_feature_report) 1943 return 0; 1944 1945 id = rtw_read8(rtwdev, REG_C2HEVT); 1946 if (id != C2H_HW_FEATURE_REPORT) { 1947 rtw_err(rtwdev, "failed to read hw feature report\n"); 1948 return -EBUSY; 1949 } 1950 1951 for (i = 0; i < HW_FEATURE_LEN; i++) 1952 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1953 1954 rtw_write8(rtwdev, REG_C2HEVT, 0); 1955 1956 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1957 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1958 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1959 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1960 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1961 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1962 1963 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1964 1965 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1966 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1967 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1968 1969 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1970 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1971 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1972 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1973 1974 return 0; 1975 } 1976 1977 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1978 { 1979 rtw_hci_stop(rtwdev); 1980 rtw_mac_power_off(rtwdev); 1981 } 1982 1983 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1984 { 1985 struct rtw_efuse *efuse = &rtwdev->efuse; 1986 int ret; 1987 1988 mutex_lock(&rtwdev->mutex); 1989 1990 /* power on mac to read efuse */ 1991 ret = rtw_chip_efuse_enable(rtwdev); 1992 if (ret) 1993 goto out_unlock; 1994 1995 ret = rtw_parse_efuse_map(rtwdev); 1996 if (ret) 1997 goto out_disable; 1998 1999 ret = rtw_dump_hw_feature(rtwdev); 2000 if (ret) 2001 goto out_disable; 2002 2003 ret = rtw_check_supported_rfe(rtwdev); 2004 if (ret) 2005 goto out_disable; 2006 2007 if (efuse->crystal_cap == 0xff) 2008 efuse->crystal_cap = 0; 2009 if (efuse->pa_type_2g == 0xff) 2010 efuse->pa_type_2g = 0; 2011 if (efuse->pa_type_5g == 0xff) 2012 efuse->pa_type_5g = 0; 2013 if (efuse->lna_type_2g == 0xff) 2014 efuse->lna_type_2g = 0; 2015 if (efuse->lna_type_5g == 0xff) 2016 efuse->lna_type_5g = 0; 2017 if (efuse->channel_plan == 0xff) 2018 efuse->channel_plan = 0x7f; 2019 if (efuse->rf_board_option == 0xff) 2020 efuse->rf_board_option = 0; 2021 if (efuse->bt_setting & BIT(0)) 2022 efuse->share_ant = true; 2023 if (efuse->regd == 0xff) 2024 efuse->regd = 0; 2025 if (efuse->tx_bb_swing_setting_2g == 0xff) 2026 efuse->tx_bb_swing_setting_2g = 0; 2027 if (efuse->tx_bb_swing_setting_5g == 0xff) 2028 efuse->tx_bb_swing_setting_5g = 0; 2029 2030 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 2031 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 2032 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 2033 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 2034 efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 2035 2036 if (!is_valid_ether_addr(efuse->addr)) { 2037 eth_random_addr(efuse->addr); 2038 dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n"); 2039 } 2040 2041 out_disable: 2042 rtw_chip_efuse_disable(rtwdev); 2043 2044 out_unlock: 2045 mutex_unlock(&rtwdev->mutex); 2046 return ret; 2047 } 2048 2049 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 2050 { 2051 struct rtw_hal *hal = &rtwdev->hal; 2052 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 2053 2054 if (!rfe_def) 2055 return -ENODEV; 2056 2057 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type); 2058 2059 rtw_phy_init_tx_power(rtwdev); 2060 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 2061 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 2062 rtw_phy_tx_power_by_rate_config(hal); 2063 rtw_phy_tx_power_limit_config(hal); 2064 2065 return 0; 2066 } 2067 2068 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 2069 { 2070 int ret; 2071 2072 ret = rtw_chip_parameter_setup(rtwdev); 2073 if (ret) { 2074 rtw_err(rtwdev, "failed to setup chip parameters\n"); 2075 goto err_out; 2076 } 2077 2078 ret = rtw_chip_efuse_info_setup(rtwdev); 2079 if (ret) { 2080 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 2081 goto err_out; 2082 } 2083 2084 ret = rtw_chip_board_info_setup(rtwdev); 2085 if (ret) { 2086 rtw_err(rtwdev, "failed to setup chip board info\n"); 2087 goto err_out; 2088 } 2089 2090 return 0; 2091 2092 err_out: 2093 return ret; 2094 } 2095 EXPORT_SYMBOL(rtw_chip_info_setup); 2096 2097 static void rtw_stats_init(struct rtw_dev *rtwdev) 2098 { 2099 struct rtw_traffic_stats *stats = &rtwdev->stats; 2100 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2101 int i; 2102 2103 ewma_tp_init(&stats->tx_ewma_tp); 2104 ewma_tp_init(&stats->rx_ewma_tp); 2105 2106 for (i = 0; i < RTW_EVM_NUM; i++) 2107 ewma_evm_init(&dm_info->ewma_evm[i]); 2108 for (i = 0; i < RTW_SNR_NUM; i++) 2109 ewma_snr_init(&dm_info->ewma_snr[i]); 2110 } 2111 2112 int rtw_core_init(struct rtw_dev *rtwdev) 2113 { 2114 const struct rtw_chip_info *chip = rtwdev->chip; 2115 struct rtw_coex *coex = &rtwdev->coex; 2116 int ret; 2117 2118 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 2119 INIT_LIST_HEAD(&rtwdev->txqs); 2120 2121 timer_setup(&rtwdev->tx_report.purge_timer, 2122 rtw_tx_report_purge_timer, 0); 2123 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2124 if (!rtwdev->tx_wq) { 2125 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n"); 2126 return -ENOMEM; 2127 } 2128 2129 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 2130 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 2131 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 2132 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 2133 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 2134 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 2135 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 2136 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 2137 rtw_coex_bt_multi_link_remain_work); 2138 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2139 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2140 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2141 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2142 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2143 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2144 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2145 skb_queue_head_init(&rtwdev->c2h_queue); 2146 skb_queue_head_init(&rtwdev->coex.queue); 2147 skb_queue_head_init(&rtwdev->tx_report.queue); 2148 2149 spin_lock_init(&rtwdev->txq_lock); 2150 spin_lock_init(&rtwdev->tx_report.q_lock); 2151 2152 mutex_init(&rtwdev->mutex); 2153 mutex_init(&rtwdev->hal.tx_power_mutex); 2154 2155 init_waitqueue_head(&rtwdev->coex.wait); 2156 init_completion(&rtwdev->lps_leave_check); 2157 init_completion(&rtwdev->fw_scan_density); 2158 2159 rtwdev->sec.total_cam_num = 32; 2160 rtwdev->hal.current_channel = 1; 2161 rtwdev->dm_info.fix_rate = U8_MAX; 2162 2163 rtw_stats_init(rtwdev); 2164 2165 /* default rx filter setting */ 2166 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2167 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2168 BIT_AB | BIT_AM | BIT_APM; 2169 2170 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2171 if (ret) { 2172 rtw_warn(rtwdev, "no firmware loaded\n"); 2173 goto out; 2174 } 2175 2176 if (chip->wow_fw_name) { 2177 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2178 if (ret) { 2179 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2180 wait_for_completion(&rtwdev->fw.completion); 2181 if (rtwdev->fw.firmware) 2182 release_firmware(rtwdev->fw.firmware); 2183 goto out; 2184 } 2185 } 2186 2187 return 0; 2188 2189 out: 2190 destroy_workqueue(rtwdev->tx_wq); 2191 return ret; 2192 } 2193 EXPORT_SYMBOL(rtw_core_init); 2194 2195 void rtw_core_deinit(struct rtw_dev *rtwdev) 2196 { 2197 struct rtw_fw_state *fw = &rtwdev->fw; 2198 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2199 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2200 unsigned long flags; 2201 2202 rtw_wait_firmware_completion(rtwdev); 2203 2204 if (fw->firmware) 2205 release_firmware(fw->firmware); 2206 2207 if (wow_fw->firmware) 2208 release_firmware(wow_fw->firmware); 2209 2210 destroy_workqueue(rtwdev->tx_wq); 2211 timer_delete_sync(&rtwdev->tx_report.purge_timer); 2212 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2213 skb_queue_purge(&rtwdev->tx_report.queue); 2214 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2215 skb_queue_purge(&rtwdev->coex.queue); 2216 skb_queue_purge(&rtwdev->c2h_queue); 2217 2218 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2219 build_list) { 2220 list_del(&rsvd_pkt->build_list); 2221 kfree(rsvd_pkt); 2222 } 2223 2224 mutex_destroy(&rtwdev->mutex); 2225 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2226 } 2227 EXPORT_SYMBOL(rtw_core_deinit); 2228 2229 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2230 { 2231 bool sta_mode_only = rtwdev->hci.type == RTW_HCI_TYPE_SDIO; 2232 struct rtw_hal *hal = &rtwdev->hal; 2233 int max_tx_headroom = 0; 2234 int ret; 2235 2236 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2237 2238 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 2239 max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN; 2240 2241 hw->extra_tx_headroom = max_tx_headroom; 2242 hw->queues = IEEE80211_NUM_ACS; 2243 hw->txq_data_size = sizeof(struct rtw_txq); 2244 hw->sta_data_size = sizeof(struct rtw_sta_info); 2245 hw->vif_data_size = sizeof(struct rtw_vif); 2246 2247 ieee80211_hw_set(hw, SIGNAL_DBM); 2248 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2249 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2250 ieee80211_hw_set(hw, MFP_CAPABLE); 2251 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2252 ieee80211_hw_set(hw, SUPPORTS_PS); 2253 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2254 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2255 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2256 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2257 ieee80211_hw_set(hw, TX_AMSDU); 2258 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2259 2260 if (sta_mode_only) 2261 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 2262 else 2263 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2264 BIT(NL80211_IFTYPE_AP) | 2265 BIT(NL80211_IFTYPE_ADHOC); 2266 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2267 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2268 2269 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2270 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2271 2272 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2273 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2274 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev); 2275 2276 if (!sta_mode_only && rtwdev->chip->id == RTW_CHIP_TYPE_8822C) { 2277 hw->wiphy->iface_combinations = rtw_iface_combs; 2278 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs); 2279 } 2280 2281 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2282 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2283 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2284 2285 #ifdef CONFIG_PM 2286 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2287 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2288 #endif 2289 rtw_set_supported_band(hw, rtwdev->chip); 2290 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2291 2292 hw->wiphy->sar_capa = &rtw_sar_capa; 2293 2294 ret = rtw_regd_init(rtwdev); 2295 if (ret) { 2296 rtw_err(rtwdev, "failed to init regd\n"); 2297 return ret; 2298 } 2299 2300 rtw_led_init(rtwdev); 2301 2302 ret = ieee80211_register_hw(hw); 2303 if (ret) { 2304 rtw_err(rtwdev, "failed to register hw\n"); 2305 goto led_deinit; 2306 } 2307 2308 ret = rtw_regd_hint(rtwdev); 2309 if (ret) { 2310 rtw_err(rtwdev, "failed to hint regd\n"); 2311 goto led_deinit; 2312 } 2313 2314 rtw_debugfs_init(rtwdev); 2315 2316 rtwdev->bf_info.bfer_mu_cnt = 0; 2317 rtwdev->bf_info.bfer_su_cnt = 0; 2318 2319 return 0; 2320 2321 led_deinit: 2322 rtw_led_deinit(rtwdev); 2323 return ret; 2324 } 2325 EXPORT_SYMBOL(rtw_register_hw); 2326 2327 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2328 { 2329 const struct rtw_chip_info *chip = rtwdev->chip; 2330 2331 ieee80211_unregister_hw(hw); 2332 rtw_unset_supported_band(hw, chip); 2333 rtw_debugfs_deinit(rtwdev); 2334 rtw_led_deinit(rtwdev); 2335 } 2336 EXPORT_SYMBOL(rtw_unregister_hw); 2337 2338 static 2339 void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2340 const struct rtw_hw_reg *reg2, u8 nbytes) 2341 { 2342 u8 i; 2343 2344 for (i = 0; i < nbytes; i++) { 2345 u8 v1 = rtw_read8(rtwdev, reg1->addr + i); 2346 u8 v2 = rtw_read8(rtwdev, reg2->addr + i); 2347 2348 rtw_write8(rtwdev, reg1->addr + i, v2); 2349 rtw_write8(rtwdev, reg2->addr + i, v1); 2350 } 2351 } 2352 2353 static 2354 void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2355 const struct rtw_hw_reg *reg2) 2356 { 2357 u32 v1, v2; 2358 2359 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask); 2360 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask); 2361 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1); 2362 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2); 2363 } 2364 2365 struct rtw_iter_port_switch_data { 2366 struct rtw_dev *rtwdev; 2367 struct rtw_vif *rtwvif_ap; 2368 }; 2369 2370 static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif) 2371 { 2372 struct rtw_iter_port_switch_data *iter_data = data; 2373 struct rtw_dev *rtwdev = iter_data->rtwdev; 2374 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv; 2375 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap; 2376 const struct rtw_hw_reg *reg1, *reg2; 2377 2378 if (rtwvif_target->port != RTW_PORT_0) 2379 return; 2380 2381 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n", 2382 rtwvif_ap->port, rtwvif_target->port); 2383 2384 /* Leave LPS so the value swapped are not in PS mode */ 2385 rtw_leave_lps(rtwdev); 2386 2387 reg1 = &rtwvif_ap->conf->net_type; 2388 reg2 = &rtwvif_target->conf->net_type; 2389 rtw_swap_reg_mask(rtwdev, reg1, reg2); 2390 2391 reg1 = &rtwvif_ap->conf->mac_addr; 2392 reg2 = &rtwvif_target->conf->mac_addr; 2393 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2394 2395 reg1 = &rtwvif_ap->conf->bssid; 2396 reg2 = &rtwvif_target->conf->bssid; 2397 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2398 2399 reg1 = &rtwvif_ap->conf->bcn_ctrl; 2400 reg2 = &rtwvif_target->conf->bcn_ctrl; 2401 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1); 2402 2403 swap(rtwvif_target->port, rtwvif_ap->port); 2404 swap(rtwvif_target->conf, rtwvif_ap->conf); 2405 2406 rtw_fw_default_port(rtwdev, rtwvif_target); 2407 } 2408 2409 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 2410 { 2411 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2412 struct rtw_iter_port_switch_data iter_data; 2413 2414 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0) 2415 return; 2416 2417 iter_data.rtwdev = rtwdev; 2418 iter_data.rtwvif_ap = rtwvif; 2419 rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data); 2420 } 2421 2422 static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif) 2423 { 2424 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2425 bool *active = data; 2426 2427 if (*active) 2428 return; 2429 2430 if (vif->type != NL80211_IFTYPE_STATION) 2431 return; 2432 2433 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid)) 2434 *active = true; 2435 } 2436 2437 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev) 2438 { 2439 bool sta_active = false; 2440 2441 rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active); 2442 2443 return rtwdev->ap_active || sta_active; 2444 } 2445 2446 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable) 2447 { 2448 if (!rtwdev->ap_active) 2449 return; 2450 2451 if (enable) { 2452 rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2453 rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2454 } else { 2455 rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2456 rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2457 } 2458 } 2459 2460 MODULE_AUTHOR("Realtek Corporation"); 2461 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2462 MODULE_LICENSE("Dual BSD/GPL"); 2463