1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 #include "sdio.h" 22 23 bool rtw_disable_lps_deep_mode; 24 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 25 bool rtw_bf_support = true; 26 unsigned int rtw_debug_mask; 27 EXPORT_SYMBOL(rtw_debug_mask); 28 /* EDCCA is enabled during normal behavior. For debugging purpose in 29 * a noisy environment, it can be disabled via edcca debugfs. Because 30 * all rtw88 devices will probably be affected if environment is noisy, 31 * rtw_edcca_enabled is just declared by driver instead of by device. 32 * So, turning it off will take effect for all rtw88 devices before 33 * there is a tough reason to maintain rtw_edcca_enabled by device. 34 */ 35 bool rtw_edcca_enabled = true; 36 37 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 38 module_param_named(support_bf, rtw_bf_support, bool, 0644); 39 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 40 41 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 42 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 43 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 44 45 static struct ieee80211_channel rtw_channeltable_2g[] = { 46 {.center_freq = 2412, .hw_value = 1,}, 47 {.center_freq = 2417, .hw_value = 2,}, 48 {.center_freq = 2422, .hw_value = 3,}, 49 {.center_freq = 2427, .hw_value = 4,}, 50 {.center_freq = 2432, .hw_value = 5,}, 51 {.center_freq = 2437, .hw_value = 6,}, 52 {.center_freq = 2442, .hw_value = 7,}, 53 {.center_freq = 2447, .hw_value = 8,}, 54 {.center_freq = 2452, .hw_value = 9,}, 55 {.center_freq = 2457, .hw_value = 10,}, 56 {.center_freq = 2462, .hw_value = 11,}, 57 {.center_freq = 2467, .hw_value = 12,}, 58 {.center_freq = 2472, .hw_value = 13,}, 59 {.center_freq = 2484, .hw_value = 14,}, 60 }; 61 62 static struct ieee80211_channel rtw_channeltable_5g[] = { 63 {.center_freq = 5180, .hw_value = 36,}, 64 {.center_freq = 5200, .hw_value = 40,}, 65 {.center_freq = 5220, .hw_value = 44,}, 66 {.center_freq = 5240, .hw_value = 48,}, 67 {.center_freq = 5260, .hw_value = 52,}, 68 {.center_freq = 5280, .hw_value = 56,}, 69 {.center_freq = 5300, .hw_value = 60,}, 70 {.center_freq = 5320, .hw_value = 64,}, 71 {.center_freq = 5500, .hw_value = 100,}, 72 {.center_freq = 5520, .hw_value = 104,}, 73 {.center_freq = 5540, .hw_value = 108,}, 74 {.center_freq = 5560, .hw_value = 112,}, 75 {.center_freq = 5580, .hw_value = 116,}, 76 {.center_freq = 5600, .hw_value = 120,}, 77 {.center_freq = 5620, .hw_value = 124,}, 78 {.center_freq = 5640, .hw_value = 128,}, 79 {.center_freq = 5660, .hw_value = 132,}, 80 {.center_freq = 5680, .hw_value = 136,}, 81 {.center_freq = 5700, .hw_value = 140,}, 82 {.center_freq = 5720, .hw_value = 144,}, 83 {.center_freq = 5745, .hw_value = 149,}, 84 {.center_freq = 5765, .hw_value = 153,}, 85 {.center_freq = 5785, .hw_value = 157,}, 86 {.center_freq = 5805, .hw_value = 161,}, 87 {.center_freq = 5825, .hw_value = 165, 88 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 89 }; 90 91 static struct ieee80211_rate rtw_ratetable[] = { 92 {.bitrate = 10, .hw_value = 0x00,}, 93 {.bitrate = 20, .hw_value = 0x01,}, 94 {.bitrate = 55, .hw_value = 0x02,}, 95 {.bitrate = 110, .hw_value = 0x03,}, 96 {.bitrate = 60, .hw_value = 0x04,}, 97 {.bitrate = 90, .hw_value = 0x05,}, 98 {.bitrate = 120, .hw_value = 0x06,}, 99 {.bitrate = 180, .hw_value = 0x07,}, 100 {.bitrate = 240, .hw_value = 0x08,}, 101 {.bitrate = 360, .hw_value = 0x09,}, 102 {.bitrate = 480, .hw_value = 0x0a,}, 103 {.bitrate = 540, .hw_value = 0x0b,}, 104 }; 105 106 static const struct ieee80211_iface_limit rtw_iface_limits[] = { 107 { 108 .max = 1, 109 .types = BIT(NL80211_IFTYPE_STATION), 110 }, 111 { 112 .max = 1, 113 .types = BIT(NL80211_IFTYPE_AP), 114 } 115 }; 116 117 static const struct ieee80211_iface_combination rtw_iface_combs[] = { 118 { 119 .limits = rtw_iface_limits, 120 .n_limits = ARRAY_SIZE(rtw_iface_limits), 121 .max_interfaces = 2, 122 .num_different_channels = 1, 123 } 124 }; 125 126 u16 rtw_desc_to_bitrate(u8 desc_rate) 127 { 128 struct ieee80211_rate rate; 129 130 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 131 return 0; 132 133 rate = rtw_ratetable[desc_rate]; 134 135 return rate.bitrate; 136 } 137 138 static struct ieee80211_supported_band rtw_band_2ghz = { 139 .band = NL80211_BAND_2GHZ, 140 141 .channels = rtw_channeltable_2g, 142 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 143 144 .bitrates = rtw_ratetable, 145 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 146 147 .ht_cap = {0}, 148 .vht_cap = {0}, 149 }; 150 151 static struct ieee80211_supported_band rtw_band_5ghz = { 152 .band = NL80211_BAND_5GHZ, 153 154 .channels = rtw_channeltable_5g, 155 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 156 157 /* 5G has no CCK rates */ 158 .bitrates = rtw_ratetable + 4, 159 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 160 161 .ht_cap = {0}, 162 .vht_cap = {0}, 163 }; 164 165 struct rtw_watch_dog_iter_data { 166 struct rtw_dev *rtwdev; 167 struct rtw_vif *rtwvif; 168 }; 169 170 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 171 { 172 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 173 u8 fix_rate_enable = 0; 174 u8 new_csi_rate_idx; 175 176 if (rtwvif->bfee.role != RTW_BFEE_SU && 177 rtwvif->bfee.role != RTW_BFEE_MU) 178 return; 179 180 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 181 bf_info->cur_csi_rpt_rate, 182 fix_rate_enable, &new_csi_rate_idx); 183 184 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 185 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 186 } 187 188 static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif) 189 { 190 struct rtw_watch_dog_iter_data *iter_data = data; 191 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 192 193 if (vif->type == NL80211_IFTYPE_STATION) 194 if (vif->cfg.assoc) 195 iter_data->rtwvif = rtwvif; 196 197 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 198 199 rtwvif->stats.tx_unicast = 0; 200 rtwvif->stats.rx_unicast = 0; 201 rtwvif->stats.tx_cnt = 0; 202 rtwvif->stats.rx_cnt = 0; 203 } 204 205 /* process TX/RX statistics periodically for hardware, 206 * the information helps hardware to enhance performance 207 */ 208 static void rtw_watch_dog_work(struct work_struct *work) 209 { 210 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 211 watch_dog_work.work); 212 struct rtw_traffic_stats *stats = &rtwdev->stats; 213 struct rtw_watch_dog_iter_data data = {}; 214 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 215 bool ps_active; 216 217 mutex_lock(&rtwdev->mutex); 218 219 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 220 goto unlock; 221 222 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 223 RTW_WATCH_DOG_DELAY_TIME); 224 225 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 226 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 227 else 228 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 229 230 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 231 rtw_coex_wl_status_change_notify(rtwdev, 0); 232 233 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 234 stats->rx_cnt > RTW_LPS_THRESHOLD) 235 ps_active = true; 236 else 237 ps_active = false; 238 239 ewma_tp_add(&stats->tx_ewma_tp, 240 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 241 ewma_tp_add(&stats->rx_ewma_tp, 242 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 243 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 244 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 245 246 /* reset tx/rx statictics */ 247 stats->tx_unicast = 0; 248 stats->rx_unicast = 0; 249 stats->tx_cnt = 0; 250 stats->rx_cnt = 0; 251 252 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 253 goto unlock; 254 255 /* make sure BB/RF is working for dynamic mech */ 256 rtw_leave_lps(rtwdev); 257 rtw_coex_wl_status_check(rtwdev); 258 rtw_coex_query_bt_hid_list(rtwdev); 259 260 rtw_phy_dynamic_mechanism(rtwdev); 261 262 data.rtwdev = rtwdev; 263 /* rtw_iterate_vifs internally uses an atomic iterator which is needed 264 * to avoid taking local->iflist_mtx mutex 265 */ 266 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data); 267 268 /* fw supports only one station associated to enter lps, if there are 269 * more than two stations associated to the AP, then we can not enter 270 * lps, because fw does not handle the overlapped beacon interval 271 * 272 * rtw_recalc_lps() iterate vifs and determine if driver can enter 273 * ps by vif->type and vif->cfg.ps, all we need to do here is to 274 * get that vif and check if device is having traffic more than the 275 * threshold. 276 */ 277 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 278 !rtwdev->beacon_loss && !rtwdev->ap_active) 279 rtw_enter_lps(rtwdev, data.rtwvif->port); 280 281 rtwdev->watch_dog_cnt++; 282 283 unlock: 284 mutex_unlock(&rtwdev->mutex); 285 } 286 287 static void rtw_c2h_work(struct work_struct *work) 288 { 289 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 290 struct sk_buff *skb, *tmp; 291 292 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 293 skb_unlink(skb, &rtwdev->c2h_queue); 294 rtw_fw_c2h_cmd_handle(rtwdev, skb); 295 dev_kfree_skb_any(skb); 296 } 297 } 298 299 static void rtw_ips_work(struct work_struct *work) 300 { 301 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 302 303 mutex_lock(&rtwdev->mutex); 304 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 305 rtw_enter_ips(rtwdev); 306 mutex_unlock(&rtwdev->mutex); 307 } 308 309 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 310 { 311 unsigned long mac_id; 312 313 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 314 if (mac_id < RTW_MAX_MAC_ID_NUM) 315 set_bit(mac_id, rtwdev->mac_id_map); 316 317 return mac_id; 318 } 319 320 static void rtw_sta_rc_work(struct work_struct *work) 321 { 322 struct rtw_sta_info *si = container_of(work, struct rtw_sta_info, 323 rc_work); 324 struct rtw_dev *rtwdev = si->rtwdev; 325 326 mutex_lock(&rtwdev->mutex); 327 rtw_update_sta_info(rtwdev, si, true); 328 mutex_unlock(&rtwdev->mutex); 329 } 330 331 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 332 struct ieee80211_vif *vif) 333 { 334 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 335 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 336 int i; 337 338 si->mac_id = rtw_acquire_macid(rtwdev); 339 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 340 return -ENOSPC; 341 342 if (vif->type == NL80211_IFTYPE_STATION && vif->cfg.assoc == 0) 343 rtwvif->mac_id = si->mac_id; 344 si->rtwdev = rtwdev; 345 si->sta = sta; 346 si->vif = vif; 347 si->init_ra_lv = 1; 348 ewma_rssi_init(&si->avg_rssi); 349 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 350 rtw_txq_init(rtwdev, sta->txq[i]); 351 INIT_WORK(&si->rc_work, rtw_sta_rc_work); 352 353 rtw_update_sta_info(rtwdev, si, true); 354 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 355 356 rtwdev->sta_cnt++; 357 rtwdev->beacon_loss = false; 358 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 359 sta->addr, si->mac_id); 360 361 return 0; 362 } 363 364 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 365 bool fw_exist) 366 { 367 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 368 int i; 369 370 cancel_work_sync(&si->rc_work); 371 372 rtw_release_macid(rtwdev, si->mac_id); 373 if (fw_exist) 374 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 375 376 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 377 rtw_txq_cleanup(rtwdev, sta->txq[i]); 378 379 kfree(si->mask); 380 381 rtwdev->sta_cnt--; 382 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 383 sta->addr, si->mac_id); 384 } 385 386 struct rtw_fwcd_hdr { 387 u32 item; 388 u32 size; 389 u32 padding1; 390 u32 padding2; 391 } __packed; 392 393 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 394 { 395 const struct rtw_chip_info *chip = rtwdev->chip; 396 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 397 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 398 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 399 u8 i; 400 401 if (segs) { 402 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 403 404 for (i = 0; i < segs->num; i++) 405 prep_size += segs->segs[i]; 406 } 407 408 desc->data = vmalloc(prep_size); 409 if (!desc->data) 410 return -ENOMEM; 411 412 desc->size = prep_size; 413 desc->next = desc->data; 414 415 return 0; 416 } 417 418 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 419 { 420 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 421 struct rtw_fwcd_hdr *hdr; 422 u8 *next; 423 424 if (!desc->data) { 425 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 426 return NULL; 427 } 428 429 next = desc->next + sizeof(struct rtw_fwcd_hdr); 430 if (next - desc->data + size > desc->size) { 431 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 432 return NULL; 433 } 434 435 hdr = (struct rtw_fwcd_hdr *)(desc->next); 436 hdr->item = item; 437 hdr->size = size; 438 hdr->padding1 = 0x01234567; 439 hdr->padding2 = 0x89abcdef; 440 desc->next = next + size; 441 442 return next; 443 } 444 445 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 446 { 447 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 448 449 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 450 451 /* Data will be freed after lifetime of device coredump. After calling 452 * dev_coredump, data is supposed to be handled by the device coredump 453 * framework. Note that a new dump will be discarded if a previous one 454 * hasn't been released yet. 455 */ 456 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 457 } 458 459 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 460 { 461 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 462 463 if (free_self) { 464 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 465 vfree(desc->data); 466 } 467 468 desc->data = NULL; 469 desc->next = NULL; 470 } 471 472 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 473 { 474 u32 size = rtwdev->chip->fw_rxff_size; 475 u32 *buf; 476 u8 seq; 477 478 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 479 if (!buf) 480 return -ENOMEM; 481 482 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 483 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 484 return -EINVAL; 485 } 486 487 if (GET_FW_DUMP_LEN(buf) == 0) { 488 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 489 return -EINVAL; 490 } 491 492 seq = GET_FW_DUMP_SEQ(buf); 493 if (seq > 0) { 494 rtw_dbg(rtwdev, RTW_DBG_FW, 495 "fw crash dump's seq is wrong: %d\n", seq); 496 return -EINVAL; 497 } 498 499 return 0; 500 } 501 502 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 503 u32 fwcd_item) 504 { 505 u32 rxff = rtwdev->chip->fw_rxff_size; 506 u32 dump_size, done_size = 0; 507 u8 *buf; 508 int ret; 509 510 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 511 if (!buf) 512 return -ENOMEM; 513 514 while (size) { 515 dump_size = size > rxff ? rxff : size; 516 517 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 518 dump_size); 519 if (ret) { 520 rtw_err(rtwdev, 521 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 522 ocp_src, done_size); 523 return ret; 524 } 525 526 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 527 dump_size, (u32 *)(buf + done_size)); 528 if (ret) { 529 rtw_err(rtwdev, 530 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 531 ocp_src, done_size); 532 return ret; 533 } 534 535 size -= dump_size; 536 done_size += dump_size; 537 } 538 539 return 0; 540 } 541 EXPORT_SYMBOL(rtw_dump_fw); 542 543 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 544 { 545 u8 *buf; 546 u32 i; 547 548 if (addr & 0x3) { 549 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 550 return -EINVAL; 551 } 552 553 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 554 if (!buf) 555 return -ENOMEM; 556 557 for (i = 0; i < size; i += 4) 558 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 559 560 return 0; 561 } 562 EXPORT_SYMBOL(rtw_dump_reg); 563 564 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 565 struct ieee80211_bss_conf *conf) 566 { 567 struct ieee80211_vif *vif = NULL; 568 569 if (conf) 570 vif = container_of(conf, struct ieee80211_vif, bss_conf); 571 572 if (conf && vif->cfg.assoc) { 573 rtwvif->aid = vif->cfg.aid; 574 rtwvif->net_type = RTW_NET_MGD_LINKED; 575 } else { 576 rtwvif->aid = 0; 577 rtwvif->net_type = RTW_NET_NO_LINK; 578 } 579 } 580 581 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 582 struct ieee80211_vif *vif, 583 struct ieee80211_sta *sta, 584 struct ieee80211_key_conf *key, 585 void *data) 586 { 587 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 588 struct rtw_sec_desc *sec = &rtwdev->sec; 589 590 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 591 } 592 593 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 594 { 595 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 596 597 if (rtwdev->sta_cnt == 0) { 598 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 599 return; 600 } 601 rtw_sta_remove(rtwdev, sta, false); 602 } 603 604 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 605 { 606 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 607 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 608 609 rtw_bf_disassoc(rtwdev, vif, NULL); 610 rtw_vif_assoc_changed(rtwvif, NULL); 611 rtw_txq_cleanup(rtwdev, vif->txq); 612 } 613 614 void rtw_fw_recovery(struct rtw_dev *rtwdev) 615 { 616 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 617 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 618 } 619 620 static void __fw_recovery_work(struct rtw_dev *rtwdev) 621 { 622 int ret = 0; 623 624 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 625 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 626 627 ret = rtw_fwcd_prep(rtwdev); 628 if (ret) 629 goto free; 630 ret = rtw_fw_dump_crash_log(rtwdev); 631 if (ret) 632 goto free; 633 ret = rtw_chip_dump_fw_crash(rtwdev); 634 if (ret) 635 goto free; 636 637 rtw_fwcd_dump(rtwdev); 638 free: 639 rtw_fwcd_free(rtwdev, !!ret); 640 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 641 642 WARN(1, "firmware crash, start reset and recover\n"); 643 644 rcu_read_lock(); 645 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 646 rcu_read_unlock(); 647 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 648 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 649 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM); 650 rtw_enter_ips(rtwdev); 651 } 652 653 static void rtw_fw_recovery_work(struct work_struct *work) 654 { 655 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 656 fw_recovery_work); 657 658 mutex_lock(&rtwdev->mutex); 659 __fw_recovery_work(rtwdev); 660 mutex_unlock(&rtwdev->mutex); 661 662 ieee80211_restart_hw(rtwdev->hw); 663 } 664 665 struct rtw_txq_ba_iter_data { 666 }; 667 668 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 669 { 670 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 671 int ret; 672 u8 tid; 673 674 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 675 while (tid != IEEE80211_NUM_TIDS) { 676 clear_bit(tid, si->tid_ba); 677 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 678 if (ret == -EINVAL) { 679 struct ieee80211_txq *txq; 680 struct rtw_txq *rtwtxq; 681 682 txq = sta->txq[tid]; 683 rtwtxq = (struct rtw_txq *)txq->drv_priv; 684 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 685 } 686 687 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 688 } 689 } 690 691 static void rtw_txq_ba_work(struct work_struct *work) 692 { 693 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 694 struct rtw_txq_ba_iter_data data; 695 696 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 697 } 698 699 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 700 { 701 if (IS_CH_2G_BAND(channel)) 702 pkt_stat->band = NL80211_BAND_2GHZ; 703 else if (IS_CH_5G_BAND(channel)) 704 pkt_stat->band = NL80211_BAND_5GHZ; 705 else 706 return; 707 708 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 709 } 710 EXPORT_SYMBOL(rtw_set_rx_freq_band); 711 712 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 713 { 714 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 715 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 716 } 717 718 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 719 u8 primary_channel, enum rtw_supported_band band, 720 enum rtw_bandwidth bandwidth) 721 { 722 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band); 723 struct rtw_hal *hal = &rtwdev->hal; 724 u8 *cch_by_bw = hal->cch_by_bw; 725 u32 center_freq, primary_freq; 726 enum rtw_sar_bands sar_band; 727 u8 primary_channel_idx; 728 729 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band); 730 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band); 731 732 /* assign the center channel used while 20M bw is selected */ 733 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel; 734 735 /* assign the center channel used while current bw is selected */ 736 cch_by_bw[bandwidth] = center_channel; 737 738 switch (bandwidth) { 739 case RTW_CHANNEL_WIDTH_20: 740 default: 741 primary_channel_idx = RTW_SC_DONT_CARE; 742 break; 743 case RTW_CHANNEL_WIDTH_40: 744 if (primary_freq > center_freq) 745 primary_channel_idx = RTW_SC_20_UPPER; 746 else 747 primary_channel_idx = RTW_SC_20_LOWER; 748 break; 749 case RTW_CHANNEL_WIDTH_80: 750 if (primary_freq > center_freq) { 751 if (primary_freq - center_freq == 10) 752 primary_channel_idx = RTW_SC_20_UPPER; 753 else 754 primary_channel_idx = RTW_SC_20_UPMOST; 755 756 /* assign the center channel used 757 * while 40M bw is selected 758 */ 759 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4; 760 } else { 761 if (center_freq - primary_freq == 10) 762 primary_channel_idx = RTW_SC_20_LOWER; 763 else 764 primary_channel_idx = RTW_SC_20_LOWEST; 765 766 /* assign the center channel used 767 * while 40M bw is selected 768 */ 769 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4; 770 } 771 break; 772 } 773 774 switch (center_channel) { 775 case 1 ... 14: 776 sar_band = RTW_SAR_BAND_0; 777 break; 778 case 36 ... 64: 779 sar_band = RTW_SAR_BAND_1; 780 break; 781 case 100 ... 144: 782 sar_band = RTW_SAR_BAND_3; 783 break; 784 case 149 ... 177: 785 sar_band = RTW_SAR_BAND_4; 786 break; 787 default: 788 WARN(1, "unknown ch(%u) to SAR band\n", center_channel); 789 sar_band = RTW_SAR_BAND_0; 790 break; 791 } 792 793 hal->current_primary_channel_index = primary_channel_idx; 794 hal->current_band_width = bandwidth; 795 hal->primary_channel = primary_channel; 796 hal->current_channel = center_channel; 797 hal->current_band_type = band; 798 hal->sar_band = sar_band; 799 } 800 801 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 802 struct rtw_channel_params *chan_params) 803 { 804 struct ieee80211_channel *channel = chandef->chan; 805 enum nl80211_chan_width width = chandef->width; 806 u32 primary_freq, center_freq; 807 u8 center_chan; 808 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 809 810 center_chan = channel->hw_value; 811 primary_freq = channel->center_freq; 812 center_freq = chandef->center_freq1; 813 814 switch (width) { 815 case NL80211_CHAN_WIDTH_20_NOHT: 816 case NL80211_CHAN_WIDTH_20: 817 bandwidth = RTW_CHANNEL_WIDTH_20; 818 break; 819 case NL80211_CHAN_WIDTH_40: 820 bandwidth = RTW_CHANNEL_WIDTH_40; 821 if (primary_freq > center_freq) 822 center_chan -= 2; 823 else 824 center_chan += 2; 825 break; 826 case NL80211_CHAN_WIDTH_80: 827 bandwidth = RTW_CHANNEL_WIDTH_80; 828 if (primary_freq > center_freq) { 829 if (primary_freq - center_freq == 10) 830 center_chan -= 2; 831 else 832 center_chan -= 6; 833 } else { 834 if (center_freq - primary_freq == 10) 835 center_chan += 2; 836 else 837 center_chan += 6; 838 } 839 break; 840 default: 841 center_chan = 0; 842 break; 843 } 844 845 chan_params->center_chan = center_chan; 846 chan_params->bandwidth = bandwidth; 847 chan_params->primary_chan = channel->hw_value; 848 } 849 850 void rtw_set_channel(struct rtw_dev *rtwdev) 851 { 852 const struct rtw_chip_info *chip = rtwdev->chip; 853 struct ieee80211_hw *hw = rtwdev->hw; 854 struct rtw_hal *hal = &rtwdev->hal; 855 struct rtw_channel_params ch_param; 856 u8 center_chan, primary_chan, bandwidth, band; 857 858 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 859 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 860 return; 861 862 center_chan = ch_param.center_chan; 863 primary_chan = ch_param.primary_chan; 864 bandwidth = ch_param.bandwidth; 865 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 866 867 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth); 868 869 if (rtwdev->scan_info.op_chan) 870 rtw_store_op_chan(rtwdev, true); 871 872 chip->ops->set_channel(rtwdev, center_chan, bandwidth, 873 hal->current_primary_channel_index); 874 875 if (hal->current_band_type == RTW_BAND_5G) { 876 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 877 } else { 878 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 879 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 880 else 881 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 882 } 883 884 rtw_phy_set_tx_power_level(rtwdev, center_chan); 885 886 /* if the channel isn't set for scanning, we will do RF calibration 887 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 888 * during scanning on each channel takes too long. 889 */ 890 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 891 rtwdev->need_rfk = true; 892 } 893 894 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 895 { 896 const struct rtw_chip_info *chip = rtwdev->chip; 897 898 if (rtwdev->need_rfk) { 899 rtwdev->need_rfk = false; 900 chip->ops->phy_calibration(rtwdev); 901 } 902 } 903 904 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 905 { 906 int i; 907 908 for (i = 0; i < ETH_ALEN; i++) 909 rtw_write8(rtwdev, start + i, addr[i]); 910 } 911 912 void rtw_vif_port_config(struct rtw_dev *rtwdev, 913 struct rtw_vif *rtwvif, 914 u32 config) 915 { 916 u32 addr, mask; 917 918 if (config & PORT_SET_MAC_ADDR) { 919 addr = rtwvif->conf->mac_addr.addr; 920 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 921 } 922 if (config & PORT_SET_BSSID) { 923 addr = rtwvif->conf->bssid.addr; 924 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 925 } 926 if (config & PORT_SET_NET_TYPE) { 927 addr = rtwvif->conf->net_type.addr; 928 mask = rtwvif->conf->net_type.mask; 929 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 930 } 931 if (config & PORT_SET_AID) { 932 addr = rtwvif->conf->aid.addr; 933 mask = rtwvif->conf->aid.mask; 934 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 935 } 936 if (config & PORT_SET_BCN_CTRL) { 937 addr = rtwvif->conf->bcn_ctrl.addr; 938 mask = rtwvif->conf->bcn_ctrl.mask; 939 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 940 } 941 } 942 943 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 944 { 945 u8 bw = 0; 946 947 switch (bw_cap) { 948 case EFUSE_HW_CAP_IGNORE: 949 case EFUSE_HW_CAP_SUPP_BW80: 950 bw |= BIT(RTW_CHANNEL_WIDTH_80); 951 fallthrough; 952 case EFUSE_HW_CAP_SUPP_BW40: 953 bw |= BIT(RTW_CHANNEL_WIDTH_40); 954 fallthrough; 955 default: 956 bw |= BIT(RTW_CHANNEL_WIDTH_20); 957 break; 958 } 959 960 return bw; 961 } 962 963 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 964 { 965 const struct rtw_chip_info *chip = rtwdev->chip; 966 struct rtw_hal *hal = &rtwdev->hal; 967 968 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 969 hw_ant_num >= hal->rf_path_num) 970 return; 971 972 switch (hw_ant_num) { 973 case 1: 974 hal->rf_type = RF_1T1R; 975 hal->rf_path_num = 1; 976 if (!chip->fix_rf_phy_num) 977 hal->rf_phy_num = hal->rf_path_num; 978 hal->antenna_tx = BB_PATH_A; 979 hal->antenna_rx = BB_PATH_A; 980 break; 981 default: 982 WARN(1, "invalid hw configuration from efuse\n"); 983 break; 984 } 985 } 986 987 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 988 { 989 u64 ra_mask = 0; 990 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 991 u8 vht_mcs_cap; 992 int i, nss; 993 994 /* 4SS, every two bits for MCS7/8/9 */ 995 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 996 vht_mcs_cap = mcs_map & 0x3; 997 switch (vht_mcs_cap) { 998 case 2: /* MCS9 */ 999 ra_mask |= 0x3ffULL << nss; 1000 break; 1001 case 1: /* MCS8 */ 1002 ra_mask |= 0x1ffULL << nss; 1003 break; 1004 case 0: /* MCS7 */ 1005 ra_mask |= 0x0ffULL << nss; 1006 break; 1007 default: 1008 break; 1009 } 1010 } 1011 1012 return ra_mask; 1013 } 1014 1015 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 1016 { 1017 u8 rate_id = 0; 1018 1019 switch (wireless_set) { 1020 case WIRELESS_CCK: 1021 rate_id = RTW_RATEID_B_20M; 1022 break; 1023 case WIRELESS_OFDM: 1024 rate_id = RTW_RATEID_G; 1025 break; 1026 case WIRELESS_CCK | WIRELESS_OFDM: 1027 rate_id = RTW_RATEID_BG; 1028 break; 1029 case WIRELESS_OFDM | WIRELESS_HT: 1030 if (tx_num == 1) 1031 rate_id = RTW_RATEID_GN_N1SS; 1032 else if (tx_num == 2) 1033 rate_id = RTW_RATEID_GN_N2SS; 1034 else if (tx_num == 3) 1035 rate_id = RTW_RATEID_ARFR5_N_3SS; 1036 break; 1037 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 1038 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 1039 if (tx_num == 1) 1040 rate_id = RTW_RATEID_BGN_40M_1SS; 1041 else if (tx_num == 2) 1042 rate_id = RTW_RATEID_BGN_40M_2SS; 1043 else if (tx_num == 3) 1044 rate_id = RTW_RATEID_ARFR5_N_3SS; 1045 else if (tx_num == 4) 1046 rate_id = RTW_RATEID_ARFR7_N_4SS; 1047 } else { 1048 if (tx_num == 1) 1049 rate_id = RTW_RATEID_BGN_20M_1SS; 1050 else if (tx_num == 2) 1051 rate_id = RTW_RATEID_BGN_20M_2SS; 1052 else if (tx_num == 3) 1053 rate_id = RTW_RATEID_ARFR5_N_3SS; 1054 else if (tx_num == 4) 1055 rate_id = RTW_RATEID_ARFR7_N_4SS; 1056 } 1057 break; 1058 case WIRELESS_OFDM | WIRELESS_VHT: 1059 if (tx_num == 1) 1060 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1061 else if (tx_num == 2) 1062 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1063 else if (tx_num == 3) 1064 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1065 else if (tx_num == 4) 1066 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1067 break; 1068 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 1069 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 1070 if (tx_num == 1) 1071 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1072 else if (tx_num == 2) 1073 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1074 else if (tx_num == 3) 1075 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1076 else if (tx_num == 4) 1077 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1078 } else { 1079 if (tx_num == 1) 1080 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1081 else if (tx_num == 2) 1082 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1083 else if (tx_num == 3) 1084 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1085 else if (tx_num == 4) 1086 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1087 } 1088 break; 1089 default: 1090 break; 1091 } 1092 1093 return rate_id; 1094 } 1095 1096 #define RA_MASK_CCK_RATES 0x0000f 1097 #define RA_MASK_OFDM_RATES 0x00ff0 1098 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1099 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1100 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1101 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1102 RA_MASK_HT_RATES_2SS | \ 1103 RA_MASK_HT_RATES_3SS) 1104 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1105 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1106 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1107 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1108 RA_MASK_VHT_RATES_2SS | \ 1109 RA_MASK_VHT_RATES_3SS) 1110 #define RA_MASK_CCK_IN_BG 0x00005 1111 #define RA_MASK_CCK_IN_HT 0x00005 1112 #define RA_MASK_CCK_IN_VHT 0x00005 1113 #define RA_MASK_OFDM_IN_VHT 0x00010 1114 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1115 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1116 1117 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1118 { 1119 u8 rssi_level = si->rssi_level; 1120 1121 if (wireless_set == WIRELESS_CCK) 1122 return 0xffffffffffffffffULL; 1123 1124 if (rssi_level == 0) 1125 return 0xffffffffffffffffULL; 1126 else if (rssi_level == 1) 1127 return 0xfffffffffffffff0ULL; 1128 else if (rssi_level == 2) 1129 return 0xffffffffffffefe0ULL; 1130 else if (rssi_level == 3) 1131 return 0xffffffffffffcfc0ULL; 1132 else if (rssi_level == 4) 1133 return 0xffffffffffff8f80ULL; 1134 else 1135 return 0xffffffffffff0f00ULL; 1136 } 1137 1138 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1139 { 1140 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1141 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1142 1143 if (ra_mask == 0) 1144 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1145 1146 return ra_mask; 1147 } 1148 1149 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1150 u64 ra_mask, bool is_vht_enable) 1151 { 1152 struct rtw_hal *hal = &rtwdev->hal; 1153 const struct cfg80211_bitrate_mask *mask = si->mask; 1154 u64 cfg_mask = GENMASK_ULL(63, 0); 1155 u8 band; 1156 1157 if (!si->use_cfg_mask) 1158 return ra_mask; 1159 1160 band = hal->current_band_type; 1161 if (band == RTW_BAND_2G) { 1162 band = NL80211_BAND_2GHZ; 1163 cfg_mask = mask->control[band].legacy; 1164 } else if (band == RTW_BAND_5G) { 1165 band = NL80211_BAND_5GHZ; 1166 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1167 RA_MASK_OFDM_RATES); 1168 } 1169 1170 if (!is_vht_enable) { 1171 if (ra_mask & RA_MASK_HT_RATES_1SS) 1172 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1173 RA_MASK_HT_RATES_1SS); 1174 if (ra_mask & RA_MASK_HT_RATES_2SS) 1175 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1176 RA_MASK_HT_RATES_2SS); 1177 } else { 1178 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1179 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1180 RA_MASK_VHT_RATES_1SS); 1181 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1182 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1183 RA_MASK_VHT_RATES_2SS); 1184 } 1185 1186 ra_mask &= cfg_mask; 1187 1188 return ra_mask; 1189 } 1190 1191 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1192 bool reset_ra_mask) 1193 { 1194 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1195 struct ieee80211_sta *sta = si->sta; 1196 struct rtw_efuse *efuse = &rtwdev->efuse; 1197 struct rtw_hal *hal = &rtwdev->hal; 1198 u8 wireless_set; 1199 u8 bw_mode; 1200 u8 rate_id; 1201 u8 rf_type = RF_1T1R; 1202 u8 stbc_en = 0; 1203 u8 ldpc_en = 0; 1204 u8 tx_num = 1; 1205 u64 ra_mask = 0; 1206 u64 ra_mask_bak = 0; 1207 bool is_vht_enable = false; 1208 bool is_support_sgi = false; 1209 1210 if (sta->deflink.vht_cap.vht_supported) { 1211 is_vht_enable = true; 1212 ra_mask |= get_vht_ra_mask(sta); 1213 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1214 stbc_en = VHT_STBC_EN; 1215 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1216 ldpc_en = VHT_LDPC_EN; 1217 } else if (sta->deflink.ht_cap.ht_supported) { 1218 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1219 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1220 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1221 stbc_en = HT_STBC_EN; 1222 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1223 ldpc_en = HT_LDPC_EN; 1224 } 1225 1226 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1227 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1228 1229 if (hal->current_band_type == RTW_BAND_5G) { 1230 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1231 ra_mask_bak = ra_mask; 1232 if (sta->deflink.vht_cap.vht_supported) { 1233 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1234 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1235 } else if (sta->deflink.ht_cap.ht_supported) { 1236 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1237 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1238 } else { 1239 wireless_set = WIRELESS_OFDM; 1240 } 1241 dm_info->rrsr_val_init = RRSR_INIT_5G; 1242 } else if (hal->current_band_type == RTW_BAND_2G) { 1243 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1244 ra_mask_bak = ra_mask; 1245 if (sta->deflink.vht_cap.vht_supported) { 1246 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1247 RA_MASK_OFDM_IN_VHT; 1248 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1249 WIRELESS_HT | WIRELESS_VHT; 1250 } else if (sta->deflink.ht_cap.ht_supported) { 1251 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1252 RA_MASK_OFDM_IN_HT_2G; 1253 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1254 WIRELESS_HT; 1255 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1256 wireless_set = WIRELESS_CCK; 1257 } else { 1258 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1259 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1260 } 1261 dm_info->rrsr_val_init = RRSR_INIT_2G; 1262 } else { 1263 rtw_err(rtwdev, "Unknown band type\n"); 1264 ra_mask_bak = ra_mask; 1265 wireless_set = 0; 1266 } 1267 1268 switch (sta->deflink.bandwidth) { 1269 case IEEE80211_STA_RX_BW_80: 1270 bw_mode = RTW_CHANNEL_WIDTH_80; 1271 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1272 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1273 break; 1274 case IEEE80211_STA_RX_BW_40: 1275 bw_mode = RTW_CHANNEL_WIDTH_40; 1276 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1277 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1278 break; 1279 default: 1280 bw_mode = RTW_CHANNEL_WIDTH_20; 1281 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1282 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1283 break; 1284 } 1285 1286 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { 1287 tx_num = 2; 1288 rf_type = RF_2T2R; 1289 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { 1290 tx_num = 2; 1291 rf_type = RF_2T2R; 1292 } 1293 1294 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1295 1296 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1297 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1298 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1299 1300 si->bw_mode = bw_mode; 1301 si->stbc_en = stbc_en; 1302 si->ldpc_en = ldpc_en; 1303 si->rf_type = rf_type; 1304 si->sgi_enable = is_support_sgi; 1305 si->vht_enable = is_vht_enable; 1306 si->ra_mask = ra_mask; 1307 si->rate_id = rate_id; 1308 1309 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1310 } 1311 1312 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1313 { 1314 const struct rtw_chip_info *chip = rtwdev->chip; 1315 struct rtw_fw_state *fw; 1316 1317 fw = &rtwdev->fw; 1318 wait_for_completion(&fw->completion); 1319 if (!fw->firmware) 1320 return -EINVAL; 1321 1322 if (chip->wow_fw_name) { 1323 fw = &rtwdev->wow_fw; 1324 wait_for_completion(&fw->completion); 1325 if (!fw->firmware) 1326 return -EINVAL; 1327 } 1328 1329 return 0; 1330 } 1331 1332 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1333 struct rtw_fw_state *fw) 1334 { 1335 const struct rtw_chip_info *chip = rtwdev->chip; 1336 1337 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1338 !fw->feature) 1339 return LPS_DEEP_MODE_NONE; 1340 1341 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1342 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1343 return LPS_DEEP_MODE_PG; 1344 1345 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1346 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1347 return LPS_DEEP_MODE_LCLK; 1348 1349 return LPS_DEEP_MODE_NONE; 1350 } 1351 1352 static int rtw_power_on(struct rtw_dev *rtwdev) 1353 { 1354 const struct rtw_chip_info *chip = rtwdev->chip; 1355 struct rtw_fw_state *fw = &rtwdev->fw; 1356 bool wifi_only; 1357 int ret; 1358 1359 ret = rtw_hci_setup(rtwdev); 1360 if (ret) { 1361 rtw_err(rtwdev, "failed to setup hci\n"); 1362 goto err; 1363 } 1364 1365 /* power on MAC before firmware downloaded */ 1366 ret = rtw_mac_power_on(rtwdev); 1367 if (ret) { 1368 rtw_err(rtwdev, "failed to power on mac\n"); 1369 goto err; 1370 } 1371 1372 ret = rtw_wait_firmware_completion(rtwdev); 1373 if (ret) { 1374 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1375 goto err_off; 1376 } 1377 1378 ret = rtw_download_firmware(rtwdev, fw); 1379 if (ret) { 1380 rtw_err(rtwdev, "failed to download firmware\n"); 1381 goto err_off; 1382 } 1383 1384 /* config mac after firmware downloaded */ 1385 ret = rtw_mac_init(rtwdev); 1386 if (ret) { 1387 rtw_err(rtwdev, "failed to configure mac\n"); 1388 goto err_off; 1389 } 1390 1391 chip->ops->phy_set_param(rtwdev); 1392 1393 ret = rtw_hci_start(rtwdev); 1394 if (ret) { 1395 rtw_err(rtwdev, "failed to start hci\n"); 1396 goto err_off; 1397 } 1398 1399 /* send H2C after HCI has started */ 1400 rtw_fw_send_general_info(rtwdev); 1401 rtw_fw_send_phydm_info(rtwdev); 1402 1403 wifi_only = !rtwdev->efuse.btcoex; 1404 rtw_coex_power_on_setting(rtwdev); 1405 rtw_coex_init_hw_config(rtwdev, wifi_only); 1406 1407 return 0; 1408 1409 err_off: 1410 rtw_mac_power_off(rtwdev); 1411 1412 err: 1413 return ret; 1414 } 1415 1416 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1417 { 1418 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1419 return; 1420 1421 if (start) { 1422 rtw_fw_scan_notify(rtwdev, true); 1423 } else { 1424 reinit_completion(&rtwdev->fw_scan_density); 1425 rtw_fw_scan_notify(rtwdev, false); 1426 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1427 SCAN_NOTIFY_TIMEOUT)) 1428 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1429 } 1430 } 1431 1432 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1433 const u8 *mac_addr, bool hw_scan) 1434 { 1435 u32 config = 0; 1436 int ret = 0; 1437 1438 rtw_leave_lps(rtwdev); 1439 1440 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1441 ret = rtw_leave_ips(rtwdev); 1442 if (ret) { 1443 rtw_err(rtwdev, "failed to leave idle state\n"); 1444 return; 1445 } 1446 } 1447 1448 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1449 config |= PORT_SET_MAC_ADDR; 1450 rtw_vif_port_config(rtwdev, rtwvif, config); 1451 1452 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1453 rtw_core_fw_scan_notify(rtwdev, true); 1454 1455 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1456 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1457 } 1458 1459 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1460 bool hw_scan) 1461 { 1462 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1463 u32 config = 0; 1464 1465 if (!rtwvif) 1466 return; 1467 1468 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1469 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1470 1471 rtw_core_fw_scan_notify(rtwdev, false); 1472 1473 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1474 config |= PORT_SET_MAC_ADDR; 1475 rtw_vif_port_config(rtwdev, rtwvif, config); 1476 1477 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1478 1479 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1480 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1481 } 1482 1483 int rtw_core_start(struct rtw_dev *rtwdev) 1484 { 1485 int ret; 1486 1487 ret = rtw_power_on(rtwdev); 1488 if (ret) 1489 return ret; 1490 1491 rtw_sec_enable_sec_engine(rtwdev); 1492 1493 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1494 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1495 1496 /* rcr reset after powered on */ 1497 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1498 1499 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1500 RTW_WATCH_DOG_DELAY_TIME); 1501 1502 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1503 1504 return 0; 1505 } 1506 1507 static void rtw_power_off(struct rtw_dev *rtwdev) 1508 { 1509 rtw_hci_stop(rtwdev); 1510 rtw_coex_power_off_setting(rtwdev); 1511 rtw_mac_power_off(rtwdev); 1512 } 1513 1514 void rtw_core_stop(struct rtw_dev *rtwdev) 1515 { 1516 struct rtw_coex *coex = &rtwdev->coex; 1517 1518 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1519 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1520 1521 mutex_unlock(&rtwdev->mutex); 1522 1523 cancel_work_sync(&rtwdev->c2h_work); 1524 cancel_work_sync(&rtwdev->update_beacon_work); 1525 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1526 cancel_delayed_work_sync(&coex->bt_relink_work); 1527 cancel_delayed_work_sync(&coex->bt_reenable_work); 1528 cancel_delayed_work_sync(&coex->defreeze_work); 1529 cancel_delayed_work_sync(&coex->wl_remain_work); 1530 cancel_delayed_work_sync(&coex->bt_remain_work); 1531 cancel_delayed_work_sync(&coex->wl_connecting_work); 1532 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1533 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1534 1535 mutex_lock(&rtwdev->mutex); 1536 1537 rtw_power_off(rtwdev); 1538 } 1539 1540 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1541 struct ieee80211_sta_ht_cap *ht_cap) 1542 { 1543 const struct rtw_chip_info *chip = rtwdev->chip; 1544 struct rtw_efuse *efuse = &rtwdev->efuse; 1545 1546 ht_cap->ht_supported = true; 1547 ht_cap->cap = 0; 1548 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1549 IEEE80211_HT_CAP_MAX_AMSDU | 1550 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1551 1552 if (rtw_chip_has_rx_ldpc(rtwdev)) 1553 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1554 if (rtw_chip_has_tx_stbc(rtwdev)) 1555 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1556 1557 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1558 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1559 IEEE80211_HT_CAP_DSSSCCK40 | 1560 IEEE80211_HT_CAP_SGI_40; 1561 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1562 ht_cap->ampdu_density = chip->ampdu_density; 1563 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1564 if (efuse->hw_cap.nss > 1) { 1565 ht_cap->mcs.rx_mask[0] = 0xFF; 1566 ht_cap->mcs.rx_mask[1] = 0xFF; 1567 ht_cap->mcs.rx_mask[4] = 0x01; 1568 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1569 } else { 1570 ht_cap->mcs.rx_mask[0] = 0xFF; 1571 ht_cap->mcs.rx_mask[1] = 0x00; 1572 ht_cap->mcs.rx_mask[4] = 0x01; 1573 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1574 } 1575 } 1576 1577 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1578 struct ieee80211_sta_vht_cap *vht_cap) 1579 { 1580 struct rtw_efuse *efuse = &rtwdev->efuse; 1581 u16 mcs_map; 1582 __le16 highest; 1583 1584 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1585 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1586 return; 1587 1588 vht_cap->vht_supported = true; 1589 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1590 IEEE80211_VHT_CAP_SHORT_GI_80 | 1591 IEEE80211_VHT_CAP_RXSTBC_1 | 1592 IEEE80211_VHT_CAP_HTC_VHT | 1593 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1594 0; 1595 if (rtwdev->hal.rf_path_num > 1) 1596 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1597 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1598 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1599 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1600 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1601 1602 if (rtw_chip_has_rx_ldpc(rtwdev)) 1603 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1604 1605 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1606 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1607 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1608 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1609 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1610 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1611 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1612 if (efuse->hw_cap.nss > 1) { 1613 highest = cpu_to_le16(780); 1614 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1615 } else { 1616 highest = cpu_to_le16(390); 1617 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1618 } 1619 1620 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1621 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1622 vht_cap->vht_mcs.rx_highest = highest; 1623 vht_cap->vht_mcs.tx_highest = highest; 1624 } 1625 1626 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev) 1627 { 1628 u16 len; 1629 1630 len = rtwdev->chip->max_scan_ie_len; 1631 1632 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) && 1633 rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 1634 len = IEEE80211_MAX_DATA_LEN; 1635 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM)) 1636 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE; 1637 1638 return len; 1639 } 1640 1641 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1642 const struct rtw_chip_info *chip) 1643 { 1644 struct rtw_dev *rtwdev = hw->priv; 1645 struct ieee80211_supported_band *sband; 1646 1647 if (chip->band & RTW_BAND_2G) { 1648 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1649 if (!sband) 1650 goto err_out; 1651 if (chip->ht_supported) 1652 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1653 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1654 } 1655 1656 if (chip->band & RTW_BAND_5G) { 1657 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1658 if (!sband) 1659 goto err_out; 1660 if (chip->ht_supported) 1661 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1662 if (chip->vht_supported) 1663 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1664 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1665 } 1666 1667 return; 1668 1669 err_out: 1670 rtw_err(rtwdev, "failed to set supported band\n"); 1671 } 1672 1673 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1674 const struct rtw_chip_info *chip) 1675 { 1676 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1677 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1678 } 1679 1680 static void rtw_vif_smps_iter(void *data, u8 *mac, 1681 struct ieee80211_vif *vif) 1682 { 1683 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1684 1685 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 1686 return; 1687 1688 if (rtwdev->hal.txrx_1ss) 1689 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); 1690 else 1691 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); 1692 } 1693 1694 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1695 { 1696 const struct rtw_chip_info *chip = rtwdev->chip; 1697 struct rtw_hal *hal = &rtwdev->hal; 1698 1699 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1700 return; 1701 1702 rtwdev->hal.txrx_1ss = txrx_1ss; 1703 if (txrx_1ss) 1704 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1705 else 1706 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1707 hal->antenna_rx, false); 1708 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1709 } 1710 1711 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1712 struct rtw_fw_state *fw) 1713 { 1714 u32 feature; 1715 const struct rtw_fw_hdr *fw_hdr = 1716 (const struct rtw_fw_hdr *)fw->firmware->data; 1717 1718 feature = le32_to_cpu(fw_hdr->feature); 1719 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1720 1721 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C && 1722 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13)) 1723 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM; 1724 } 1725 1726 static void __update_firmware_info(struct rtw_dev *rtwdev, 1727 struct rtw_fw_state *fw) 1728 { 1729 const struct rtw_fw_hdr *fw_hdr = 1730 (const struct rtw_fw_hdr *)fw->firmware->data; 1731 1732 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1733 fw->version = le16_to_cpu(fw_hdr->version); 1734 fw->sub_version = fw_hdr->subversion; 1735 fw->sub_index = fw_hdr->subindex; 1736 1737 __update_firmware_feature(rtwdev, fw); 1738 } 1739 1740 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1741 struct rtw_fw_state *fw) 1742 { 1743 struct rtw_fw_hdr_legacy *legacy = 1744 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1745 1746 fw->h2c_version = 0; 1747 fw->version = le16_to_cpu(legacy->version); 1748 fw->sub_version = legacy->subversion1; 1749 fw->sub_index = legacy->subversion2; 1750 } 1751 1752 static void update_firmware_info(struct rtw_dev *rtwdev, 1753 struct rtw_fw_state *fw) 1754 { 1755 if (rtw_chip_wcpu_11n(rtwdev)) 1756 __update_firmware_info_legacy(rtwdev, fw); 1757 else 1758 __update_firmware_info(rtwdev, fw); 1759 } 1760 1761 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1762 { 1763 struct rtw_fw_state *fw = context; 1764 struct rtw_dev *rtwdev = fw->rtwdev; 1765 1766 if (!firmware || !firmware->data) { 1767 rtw_err(rtwdev, "failed to request firmware\n"); 1768 complete_all(&fw->completion); 1769 return; 1770 } 1771 1772 fw->firmware = firmware; 1773 update_firmware_info(rtwdev, fw); 1774 complete_all(&fw->completion); 1775 1776 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n", 1777 fw->type == RTW_WOWLAN_FW ? "WOW " : "", 1778 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1779 } 1780 1781 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1782 { 1783 const char *fw_name; 1784 struct rtw_fw_state *fw; 1785 int ret; 1786 1787 switch (type) { 1788 case RTW_WOWLAN_FW: 1789 fw = &rtwdev->wow_fw; 1790 fw_name = rtwdev->chip->wow_fw_name; 1791 break; 1792 1793 case RTW_NORMAL_FW: 1794 fw = &rtwdev->fw; 1795 fw_name = rtwdev->chip->fw_name; 1796 break; 1797 1798 default: 1799 rtw_warn(rtwdev, "unsupported firmware type\n"); 1800 return -ENOENT; 1801 } 1802 1803 fw->type = type; 1804 fw->rtwdev = rtwdev; 1805 init_completion(&fw->completion); 1806 1807 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1808 GFP_KERNEL, fw, rtw_load_firmware_cb); 1809 if (ret) { 1810 rtw_err(rtwdev, "failed to async firmware request\n"); 1811 return ret; 1812 } 1813 1814 return 0; 1815 } 1816 1817 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1818 { 1819 const struct rtw_chip_info *chip = rtwdev->chip; 1820 struct rtw_hal *hal = &rtwdev->hal; 1821 struct rtw_efuse *efuse = &rtwdev->efuse; 1822 1823 switch (rtw_hci_type(rtwdev)) { 1824 case RTW_HCI_TYPE_PCIE: 1825 rtwdev->hci.rpwm_addr = 0x03d9; 1826 rtwdev->hci.cpwm_addr = 0x03da; 1827 break; 1828 case RTW_HCI_TYPE_SDIO: 1829 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1; 1830 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2; 1831 break; 1832 case RTW_HCI_TYPE_USB: 1833 rtwdev->hci.rpwm_addr = 0xfe58; 1834 rtwdev->hci.cpwm_addr = 0xfe57; 1835 break; 1836 default: 1837 rtw_err(rtwdev, "unsupported hci type\n"); 1838 return -EINVAL; 1839 } 1840 1841 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1842 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1843 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1844 if (hal->chip_version & BIT_RF_TYPE_ID) { 1845 hal->rf_type = RF_2T2R; 1846 hal->rf_path_num = 2; 1847 hal->antenna_tx = BB_PATH_AB; 1848 hal->antenna_rx = BB_PATH_AB; 1849 } else { 1850 hal->rf_type = RF_1T1R; 1851 hal->rf_path_num = 1; 1852 hal->antenna_tx = BB_PATH_A; 1853 hal->antenna_rx = BB_PATH_A; 1854 } 1855 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1856 hal->rf_path_num; 1857 1858 efuse->physical_size = chip->phy_efuse_size; 1859 efuse->logical_size = chip->log_efuse_size; 1860 efuse->protect_size = chip->ptct_efuse_size; 1861 1862 /* default use ack */ 1863 rtwdev->hal.rcr |= BIT_VHT_DACK; 1864 1865 hal->bfee_sts_cap = 3; 1866 1867 return 0; 1868 } 1869 1870 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1871 { 1872 struct rtw_fw_state *fw = &rtwdev->fw; 1873 int ret; 1874 1875 ret = rtw_hci_setup(rtwdev); 1876 if (ret) { 1877 rtw_err(rtwdev, "failed to setup hci\n"); 1878 goto err; 1879 } 1880 1881 ret = rtw_mac_power_on(rtwdev); 1882 if (ret) { 1883 rtw_err(rtwdev, "failed to power on mac\n"); 1884 goto err; 1885 } 1886 1887 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1888 1889 wait_for_completion(&fw->completion); 1890 if (!fw->firmware) { 1891 ret = -EINVAL; 1892 rtw_err(rtwdev, "failed to load firmware\n"); 1893 goto err; 1894 } 1895 1896 ret = rtw_download_firmware(rtwdev, fw); 1897 if (ret) { 1898 rtw_err(rtwdev, "failed to download firmware\n"); 1899 goto err_off; 1900 } 1901 1902 return 0; 1903 1904 err_off: 1905 rtw_mac_power_off(rtwdev); 1906 1907 err: 1908 return ret; 1909 } 1910 1911 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1912 { 1913 struct rtw_efuse *efuse = &rtwdev->efuse; 1914 u8 hw_feature[HW_FEATURE_LEN]; 1915 u8 id; 1916 u8 bw; 1917 int i; 1918 1919 id = rtw_read8(rtwdev, REG_C2HEVT); 1920 if (id != C2H_HW_FEATURE_REPORT) { 1921 rtw_err(rtwdev, "failed to read hw feature report\n"); 1922 return -EBUSY; 1923 } 1924 1925 for (i = 0; i < HW_FEATURE_LEN; i++) 1926 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1927 1928 rtw_write8(rtwdev, REG_C2HEVT, 0); 1929 1930 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1931 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1932 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1933 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1934 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1935 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1936 1937 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1938 1939 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1940 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1941 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1942 1943 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1944 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1945 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1946 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1947 1948 return 0; 1949 } 1950 1951 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1952 { 1953 rtw_hci_stop(rtwdev); 1954 rtw_mac_power_off(rtwdev); 1955 } 1956 1957 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1958 { 1959 struct rtw_efuse *efuse = &rtwdev->efuse; 1960 int ret; 1961 1962 mutex_lock(&rtwdev->mutex); 1963 1964 /* power on mac to read efuse */ 1965 ret = rtw_chip_efuse_enable(rtwdev); 1966 if (ret) 1967 goto out_unlock; 1968 1969 ret = rtw_parse_efuse_map(rtwdev); 1970 if (ret) 1971 goto out_disable; 1972 1973 ret = rtw_dump_hw_feature(rtwdev); 1974 if (ret) 1975 goto out_disable; 1976 1977 ret = rtw_check_supported_rfe(rtwdev); 1978 if (ret) 1979 goto out_disable; 1980 1981 if (efuse->crystal_cap == 0xff) 1982 efuse->crystal_cap = 0; 1983 if (efuse->pa_type_2g == 0xff) 1984 efuse->pa_type_2g = 0; 1985 if (efuse->pa_type_5g == 0xff) 1986 efuse->pa_type_5g = 0; 1987 if (efuse->lna_type_2g == 0xff) 1988 efuse->lna_type_2g = 0; 1989 if (efuse->lna_type_5g == 0xff) 1990 efuse->lna_type_5g = 0; 1991 if (efuse->channel_plan == 0xff) 1992 efuse->channel_plan = 0x7f; 1993 if (efuse->rf_board_option == 0xff) 1994 efuse->rf_board_option = 0; 1995 if (efuse->bt_setting & BIT(0)) 1996 efuse->share_ant = true; 1997 if (efuse->regd == 0xff) 1998 efuse->regd = 0; 1999 if (efuse->tx_bb_swing_setting_2g == 0xff) 2000 efuse->tx_bb_swing_setting_2g = 0; 2001 if (efuse->tx_bb_swing_setting_5g == 0xff) 2002 efuse->tx_bb_swing_setting_5g = 0; 2003 2004 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 2005 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 2006 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 2007 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 2008 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 2009 2010 if (!is_valid_ether_addr(efuse->addr)) { 2011 eth_random_addr(efuse->addr); 2012 dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n"); 2013 } 2014 2015 out_disable: 2016 rtw_chip_efuse_disable(rtwdev); 2017 2018 out_unlock: 2019 mutex_unlock(&rtwdev->mutex); 2020 return ret; 2021 } 2022 2023 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 2024 { 2025 struct rtw_hal *hal = &rtwdev->hal; 2026 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 2027 2028 if (!rfe_def) 2029 return -ENODEV; 2030 2031 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type); 2032 2033 rtw_phy_init_tx_power(rtwdev); 2034 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 2035 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 2036 rtw_phy_tx_power_by_rate_config(hal); 2037 rtw_phy_tx_power_limit_config(hal); 2038 2039 return 0; 2040 } 2041 2042 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 2043 { 2044 int ret; 2045 2046 ret = rtw_chip_parameter_setup(rtwdev); 2047 if (ret) { 2048 rtw_err(rtwdev, "failed to setup chip parameters\n"); 2049 goto err_out; 2050 } 2051 2052 ret = rtw_chip_efuse_info_setup(rtwdev); 2053 if (ret) { 2054 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 2055 goto err_out; 2056 } 2057 2058 ret = rtw_chip_board_info_setup(rtwdev); 2059 if (ret) { 2060 rtw_err(rtwdev, "failed to setup chip board info\n"); 2061 goto err_out; 2062 } 2063 2064 return 0; 2065 2066 err_out: 2067 return ret; 2068 } 2069 EXPORT_SYMBOL(rtw_chip_info_setup); 2070 2071 static void rtw_stats_init(struct rtw_dev *rtwdev) 2072 { 2073 struct rtw_traffic_stats *stats = &rtwdev->stats; 2074 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2075 int i; 2076 2077 ewma_tp_init(&stats->tx_ewma_tp); 2078 ewma_tp_init(&stats->rx_ewma_tp); 2079 2080 for (i = 0; i < RTW_EVM_NUM; i++) 2081 ewma_evm_init(&dm_info->ewma_evm[i]); 2082 for (i = 0; i < RTW_SNR_NUM; i++) 2083 ewma_snr_init(&dm_info->ewma_snr[i]); 2084 } 2085 2086 int rtw_core_init(struct rtw_dev *rtwdev) 2087 { 2088 const struct rtw_chip_info *chip = rtwdev->chip; 2089 struct rtw_coex *coex = &rtwdev->coex; 2090 int ret; 2091 2092 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 2093 INIT_LIST_HEAD(&rtwdev->txqs); 2094 2095 timer_setup(&rtwdev->tx_report.purge_timer, 2096 rtw_tx_report_purge_timer, 0); 2097 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2098 if (!rtwdev->tx_wq) { 2099 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n"); 2100 return -ENOMEM; 2101 } 2102 2103 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 2104 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 2105 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 2106 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 2107 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 2108 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 2109 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 2110 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 2111 rtw_coex_bt_multi_link_remain_work); 2112 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2113 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2114 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2115 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2116 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2117 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2118 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2119 skb_queue_head_init(&rtwdev->c2h_queue); 2120 skb_queue_head_init(&rtwdev->coex.queue); 2121 skb_queue_head_init(&rtwdev->tx_report.queue); 2122 2123 spin_lock_init(&rtwdev->txq_lock); 2124 spin_lock_init(&rtwdev->tx_report.q_lock); 2125 2126 mutex_init(&rtwdev->mutex); 2127 mutex_init(&rtwdev->hal.tx_power_mutex); 2128 2129 init_waitqueue_head(&rtwdev->coex.wait); 2130 init_completion(&rtwdev->lps_leave_check); 2131 init_completion(&rtwdev->fw_scan_density); 2132 2133 rtwdev->sec.total_cam_num = 32; 2134 rtwdev->hal.current_channel = 1; 2135 rtwdev->dm_info.fix_rate = U8_MAX; 2136 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2137 2138 rtw_stats_init(rtwdev); 2139 2140 /* default rx filter setting */ 2141 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2142 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2143 BIT_AB | BIT_AM | BIT_APM; 2144 2145 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2146 if (ret) { 2147 rtw_warn(rtwdev, "no firmware loaded\n"); 2148 goto out; 2149 } 2150 2151 if (chip->wow_fw_name) { 2152 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2153 if (ret) { 2154 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2155 wait_for_completion(&rtwdev->fw.completion); 2156 if (rtwdev->fw.firmware) 2157 release_firmware(rtwdev->fw.firmware); 2158 goto out; 2159 } 2160 } 2161 2162 return 0; 2163 2164 out: 2165 destroy_workqueue(rtwdev->tx_wq); 2166 return ret; 2167 } 2168 EXPORT_SYMBOL(rtw_core_init); 2169 2170 void rtw_core_deinit(struct rtw_dev *rtwdev) 2171 { 2172 struct rtw_fw_state *fw = &rtwdev->fw; 2173 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2174 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2175 unsigned long flags; 2176 2177 rtw_wait_firmware_completion(rtwdev); 2178 2179 if (fw->firmware) 2180 release_firmware(fw->firmware); 2181 2182 if (wow_fw->firmware) 2183 release_firmware(wow_fw->firmware); 2184 2185 destroy_workqueue(rtwdev->tx_wq); 2186 timer_delete_sync(&rtwdev->tx_report.purge_timer); 2187 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2188 skb_queue_purge(&rtwdev->tx_report.queue); 2189 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2190 skb_queue_purge(&rtwdev->coex.queue); 2191 skb_queue_purge(&rtwdev->c2h_queue); 2192 2193 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2194 build_list) { 2195 list_del(&rsvd_pkt->build_list); 2196 kfree(rsvd_pkt); 2197 } 2198 2199 mutex_destroy(&rtwdev->mutex); 2200 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2201 } 2202 EXPORT_SYMBOL(rtw_core_deinit); 2203 2204 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2205 { 2206 bool sta_mode_only = rtwdev->hci.type == RTW_HCI_TYPE_SDIO; 2207 struct rtw_hal *hal = &rtwdev->hal; 2208 int max_tx_headroom = 0; 2209 int ret; 2210 2211 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2212 2213 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 2214 max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN; 2215 2216 hw->extra_tx_headroom = max_tx_headroom; 2217 hw->queues = IEEE80211_NUM_ACS; 2218 hw->txq_data_size = sizeof(struct rtw_txq); 2219 hw->sta_data_size = sizeof(struct rtw_sta_info); 2220 hw->vif_data_size = sizeof(struct rtw_vif); 2221 2222 ieee80211_hw_set(hw, SIGNAL_DBM); 2223 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2224 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2225 ieee80211_hw_set(hw, MFP_CAPABLE); 2226 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2227 ieee80211_hw_set(hw, SUPPORTS_PS); 2228 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2229 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2230 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2231 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2232 ieee80211_hw_set(hw, TX_AMSDU); 2233 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2234 2235 if (sta_mode_only) 2236 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 2237 else 2238 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2239 BIT(NL80211_IFTYPE_AP) | 2240 BIT(NL80211_IFTYPE_ADHOC); 2241 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2242 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2243 2244 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2245 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2246 2247 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2248 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2249 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev); 2250 2251 if (!sta_mode_only && rtwdev->chip->id == RTW_CHIP_TYPE_8822C) { 2252 hw->wiphy->iface_combinations = rtw_iface_combs; 2253 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs); 2254 } 2255 2256 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2257 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2258 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2259 2260 #ifdef CONFIG_PM 2261 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2262 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2263 #endif 2264 rtw_set_supported_band(hw, rtwdev->chip); 2265 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2266 2267 hw->wiphy->sar_capa = &rtw_sar_capa; 2268 2269 ret = rtw_regd_init(rtwdev); 2270 if (ret) { 2271 rtw_err(rtwdev, "failed to init regd\n"); 2272 return ret; 2273 } 2274 2275 ret = ieee80211_register_hw(hw); 2276 if (ret) { 2277 rtw_err(rtwdev, "failed to register hw\n"); 2278 return ret; 2279 } 2280 2281 ret = rtw_regd_hint(rtwdev); 2282 if (ret) { 2283 rtw_err(rtwdev, "failed to hint regd\n"); 2284 return ret; 2285 } 2286 2287 rtw_debugfs_init(rtwdev); 2288 2289 rtwdev->bf_info.bfer_mu_cnt = 0; 2290 rtwdev->bf_info.bfer_su_cnt = 0; 2291 2292 return 0; 2293 } 2294 EXPORT_SYMBOL(rtw_register_hw); 2295 2296 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2297 { 2298 const struct rtw_chip_info *chip = rtwdev->chip; 2299 2300 ieee80211_unregister_hw(hw); 2301 rtw_unset_supported_band(hw, chip); 2302 } 2303 EXPORT_SYMBOL(rtw_unregister_hw); 2304 2305 static 2306 void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2307 const struct rtw_hw_reg *reg2, u8 nbytes) 2308 { 2309 u8 i; 2310 2311 for (i = 0; i < nbytes; i++) { 2312 u8 v1 = rtw_read8(rtwdev, reg1->addr + i); 2313 u8 v2 = rtw_read8(rtwdev, reg2->addr + i); 2314 2315 rtw_write8(rtwdev, reg1->addr + i, v2); 2316 rtw_write8(rtwdev, reg2->addr + i, v1); 2317 } 2318 } 2319 2320 static 2321 void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2322 const struct rtw_hw_reg *reg2) 2323 { 2324 u32 v1, v2; 2325 2326 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask); 2327 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask); 2328 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1); 2329 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2); 2330 } 2331 2332 struct rtw_iter_port_switch_data { 2333 struct rtw_dev *rtwdev; 2334 struct rtw_vif *rtwvif_ap; 2335 }; 2336 2337 static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif) 2338 { 2339 struct rtw_iter_port_switch_data *iter_data = data; 2340 struct rtw_dev *rtwdev = iter_data->rtwdev; 2341 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv; 2342 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap; 2343 const struct rtw_hw_reg *reg1, *reg2; 2344 2345 if (rtwvif_target->port != RTW_PORT_0) 2346 return; 2347 2348 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n", 2349 rtwvif_ap->port, rtwvif_target->port); 2350 2351 /* Leave LPS so the value swapped are not in PS mode */ 2352 rtw_leave_lps(rtwdev); 2353 2354 reg1 = &rtwvif_ap->conf->net_type; 2355 reg2 = &rtwvif_target->conf->net_type; 2356 rtw_swap_reg_mask(rtwdev, reg1, reg2); 2357 2358 reg1 = &rtwvif_ap->conf->mac_addr; 2359 reg2 = &rtwvif_target->conf->mac_addr; 2360 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2361 2362 reg1 = &rtwvif_ap->conf->bssid; 2363 reg2 = &rtwvif_target->conf->bssid; 2364 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2365 2366 reg1 = &rtwvif_ap->conf->bcn_ctrl; 2367 reg2 = &rtwvif_target->conf->bcn_ctrl; 2368 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1); 2369 2370 swap(rtwvif_target->port, rtwvif_ap->port); 2371 swap(rtwvif_target->conf, rtwvif_ap->conf); 2372 2373 rtw_fw_default_port(rtwdev, rtwvif_target); 2374 } 2375 2376 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 2377 { 2378 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2379 struct rtw_iter_port_switch_data iter_data; 2380 2381 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0) 2382 return; 2383 2384 iter_data.rtwdev = rtwdev; 2385 iter_data.rtwvif_ap = rtwvif; 2386 rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data); 2387 } 2388 2389 static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif) 2390 { 2391 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2392 bool *active = data; 2393 2394 if (*active) 2395 return; 2396 2397 if (vif->type != NL80211_IFTYPE_STATION) 2398 return; 2399 2400 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid)) 2401 *active = true; 2402 } 2403 2404 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev) 2405 { 2406 bool sta_active = false; 2407 2408 rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active); 2409 2410 return rtwdev->ap_active || sta_active; 2411 } 2412 2413 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable) 2414 { 2415 if (!rtwdev->ap_active) 2416 return; 2417 2418 if (enable) { 2419 rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2420 rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2421 } else { 2422 rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2423 rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2424 } 2425 } 2426 2427 MODULE_AUTHOR("Realtek Corporation"); 2428 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2429 MODULE_LICENSE("Dual BSD/GPL"); 2430