1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "mac.h" 7 #include "reg.h" 8 #include "fw.h" 9 #include "debug.h" 10 11 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, 12 u8 primary_ch_idx) 13 { 14 u8 txsc40 = 0, txsc20 = 0; 15 u32 value32; 16 u8 value8; 17 18 txsc20 = primary_ch_idx; 19 if (bw == RTW_CHANNEL_WIDTH_80) { 20 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 21 txsc40 = RTW_SC_40_UPPER; 22 else 23 txsc40 = RTW_SC_40_LOWER; 24 } 25 rtw_write8(rtwdev, REG_DATA_SC, 26 BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); 27 28 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL); 29 value32 &= ~BIT_RFMOD; 30 switch (bw) { 31 case RTW_CHANNEL_WIDTH_80: 32 value32 |= BIT_RFMOD_80M; 33 break; 34 case RTW_CHANNEL_WIDTH_40: 35 value32 |= BIT_RFMOD_40M; 36 break; 37 case RTW_CHANNEL_WIDTH_20: 38 default: 39 break; 40 } 41 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32); 42 43 if (rtw_chip_wcpu_11n(rtwdev)) 44 return; 45 46 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL); 47 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); 48 rtw_write32(rtwdev, REG_AFE_CTRL1, value32); 49 50 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 51 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 52 53 value8 = rtw_read8(rtwdev, REG_CCK_CHECK); 54 value8 = value8 & ~BIT_CHECK_CCK_EN; 55 if (IS_CH_5G_BAND(channel)) 56 value8 |= BIT_CHECK_CCK_EN; 57 rtw_write8(rtwdev, REG_CCK_CHECK, value8); 58 } 59 60 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev) 61 { 62 u32 value32; 63 u8 value8; 64 65 rtw_write8(rtwdev, REG_RSV_CTRL, 0); 66 67 if (rtw_chip_wcpu_11n(rtwdev)) { 68 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO) 69 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL); 70 else 71 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL); 72 return 0; 73 } 74 75 switch (rtw_hci_type(rtwdev)) { 76 case RTW_HCI_TYPE_PCIE: 77 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_BT_DIG_CLK_EN); 78 break; 79 case RTW_HCI_TYPE_USB: 80 break; 81 default: 82 return -EINVAL; 83 } 84 85 /* config PIN Mux */ 86 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); 87 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL; 88 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); 89 90 value32 = rtw_read32(rtwdev, REG_LED_CFG); 91 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN); 92 rtw_write32(rtwdev, REG_LED_CFG, value32); 93 94 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG); 95 value32 |= BIT_WLRFE_4_5_EN; 96 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32); 97 98 /* disable BB/RF */ 99 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 100 value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 101 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8); 102 103 value8 = rtw_read8(rtwdev, REG_RF_CTRL); 104 value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN); 105 rtw_write8(rtwdev, REG_RF_CTRL, value8); 106 107 value32 = rtw_read32(rtwdev, REG_WLRF1); 108 value32 &= ~BIT_WLRF1_BBRF_EN; 109 rtw_write32(rtwdev, REG_WLRF1, value32); 110 111 return 0; 112 } 113 114 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target) 115 { 116 u32 cnt; 117 118 target &= mask; 119 120 for (cnt = 0; cnt < RTW_PWR_POLLING_CNT; cnt++) { 121 if ((rtw_read8(rtwdev, addr) & mask) == target) 122 return true; 123 124 udelay(50); 125 } 126 127 return false; 128 } 129 130 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev, 131 const struct rtw_pwr_seq_cmd *cmd) 132 { 133 u8 value; 134 u32 offset; 135 136 if (cmd->base == RTW_PWR_ADDR_SDIO) 137 offset = cmd->offset | SDIO_LOCAL_OFFSET; 138 else 139 offset = cmd->offset; 140 141 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 142 return 0; 143 144 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE) 145 goto err; 146 147 /* if PCIE, toggle BIT_PFM_WOWL and try again */ 148 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL); 149 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 150 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 151 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 152 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 153 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 154 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 155 156 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 157 return 0; 158 159 err: 160 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n", 161 offset, cmd->mask, cmd->value); 162 return -EBUSY; 163 } 164 165 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask, 166 u8 cut_mask, 167 const struct rtw_pwr_seq_cmd *cmd) 168 { 169 const struct rtw_pwr_seq_cmd *cur_cmd; 170 u32 offset; 171 u8 value; 172 173 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) { 174 if (!(cur_cmd->intf_mask & intf_mask) || 175 !(cur_cmd->cut_mask & cut_mask)) 176 continue; 177 178 switch (cur_cmd->cmd) { 179 case RTW_PWR_CMD_WRITE: 180 offset = cur_cmd->offset; 181 182 if (cur_cmd->base == RTW_PWR_ADDR_SDIO) 183 offset |= SDIO_LOCAL_OFFSET; 184 185 value = rtw_read8(rtwdev, offset); 186 value &= ~cur_cmd->mask; 187 value |= (cur_cmd->value & cur_cmd->mask); 188 rtw_write8(rtwdev, offset, value); 189 break; 190 case RTW_PWR_CMD_POLLING: 191 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd)) 192 return -EBUSY; 193 break; 194 case RTW_PWR_CMD_DELAY: 195 if (cur_cmd->value == RTW_PWR_DELAY_US) 196 udelay(cur_cmd->offset); 197 else 198 mdelay(cur_cmd->offset); 199 break; 200 case RTW_PWR_CMD_READ: 201 break; 202 default: 203 return -EINVAL; 204 } 205 } 206 207 return 0; 208 } 209 210 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev, 211 const struct rtw_pwr_seq_cmd **cmd_seq) 212 { 213 u8 cut_mask; 214 u8 intf_mask; 215 u8 cut; 216 u32 idx = 0; 217 const struct rtw_pwr_seq_cmd *cmd; 218 int ret; 219 220 cut = rtwdev->hal.cut_version; 221 cut_mask = cut_version_to_mask(cut); 222 switch (rtw_hci_type(rtwdev)) { 223 case RTW_HCI_TYPE_PCIE: 224 intf_mask = BIT(2); 225 break; 226 case RTW_HCI_TYPE_USB: 227 intf_mask = BIT(1); 228 break; 229 default: 230 return -EINVAL; 231 } 232 233 do { 234 cmd = cmd_seq[idx]; 235 if (!cmd) 236 break; 237 238 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd); 239 if (ret) 240 return -EBUSY; 241 242 idx++; 243 } while (1); 244 245 return 0; 246 } 247 248 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) 249 { 250 struct rtw_chip_info *chip = rtwdev->chip; 251 const struct rtw_pwr_seq_cmd **pwr_seq; 252 u8 rpwm; 253 bool cur_pwr; 254 255 if (rtw_chip_wcpu_11ac(rtwdev)) { 256 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr); 257 258 /* Check FW still exist or not */ 259 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) { 260 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE; 261 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm); 262 } 263 } 264 265 if (rtw_read8(rtwdev, REG_CR) == 0xea) 266 cur_pwr = false; 267 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 268 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) 269 cur_pwr = false; 270 else 271 cur_pwr = true; 272 273 if (pwr_on == cur_pwr) 274 return -EALREADY; 275 276 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; 277 if (rtw_pwr_seq_parser(rtwdev, pwr_seq)) 278 return -EINVAL; 279 280 return 0; 281 } 282 283 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 284 { 285 u8 sys_func_en = rtwdev->chip->sys_func_en; 286 u8 value8; 287 u32 value, tmp; 288 289 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON); 290 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN; 291 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value); 292 293 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en); 294 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C; 295 rtw_write8(rtwdev, REG_CR_EXT + 3, value8); 296 297 /* disable boot-from-flash for driver's DL FW */ 298 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL); 299 if (tmp & BIT_BOOT_FSPI_EN) { 300 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); 301 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); 302 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value); 303 } 304 305 return 0; 306 } 307 308 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev) 309 { 310 rtw_write8(rtwdev, REG_CR, 0xff); 311 mdelay(2); 312 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f); 313 mdelay(2); 314 315 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN); 316 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC); 317 318 rtw_write16(rtwdev, REG_CR, 0x2ff); 319 320 return 0; 321 } 322 323 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 324 { 325 if (rtw_chip_wcpu_11n(rtwdev)) 326 return __rtw_mac_init_system_cfg_legacy(rtwdev); 327 328 return __rtw_mac_init_system_cfg(rtwdev); 329 } 330 331 int rtw_mac_power_on(struct rtw_dev *rtwdev) 332 { 333 int ret = 0; 334 335 ret = rtw_mac_pre_system_cfg(rtwdev); 336 if (ret) 337 goto err; 338 339 ret = rtw_mac_power_switch(rtwdev, true); 340 if (ret == -EALREADY) { 341 rtw_mac_power_switch(rtwdev, false); 342 ret = rtw_mac_power_switch(rtwdev, true); 343 if (ret) 344 goto err; 345 } else if (ret) { 346 goto err; 347 } 348 349 ret = rtw_mac_init_system_cfg(rtwdev); 350 if (ret) 351 goto err; 352 353 return 0; 354 355 err: 356 rtw_err(rtwdev, "mac power on failed"); 357 return ret; 358 } 359 360 void rtw_mac_power_off(struct rtw_dev *rtwdev) 361 { 362 rtw_mac_power_switch(rtwdev, false); 363 } 364 365 static bool check_firmware_size(const u8 *data, u32 size) 366 { 367 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 368 u32 dmem_size; 369 u32 imem_size; 370 u32 emem_size; 371 u32 real_size; 372 373 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 374 imem_size = le32_to_cpu(fw_hdr->imem_size); 375 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 376 le32_to_cpu(fw_hdr->emem_size) : 0; 377 378 dmem_size += FW_HDR_CHKSUM_SIZE; 379 imem_size += FW_HDR_CHKSUM_SIZE; 380 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 381 real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size; 382 if (real_size != size) 383 return false; 384 385 return true; 386 } 387 388 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable) 389 { 390 if (enable) { 391 /* cpu io interface enable */ 392 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 393 394 /* cpu enable */ 395 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 396 } else { 397 /* cpu io interface disable */ 398 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 399 400 /* cpu disable */ 401 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 402 } 403 } 404 405 #define DLFW_RESTORE_REG_NUM 6 406 407 static void download_firmware_reg_backup(struct rtw_dev *rtwdev, 408 struct rtw_backup_info *bckp) 409 { 410 u8 tmp; 411 u8 bckp_idx = 0; 412 413 /* set HIQ to hi priority */ 414 bckp[bckp_idx].len = 1; 415 bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; 416 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); 417 bckp_idx++; 418 tmp = RTW_DMA_MAPPING_HIGH << 6; 419 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp); 420 421 /* DLFW only use HIQ, map HIQ to hi priority */ 422 bckp[bckp_idx].len = 1; 423 bckp[bckp_idx].reg = REG_CR; 424 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); 425 bckp_idx++; 426 bckp[bckp_idx].len = 4; 427 bckp[bckp_idx].reg = REG_H2CQ_CSR; 428 bckp[bckp_idx].val = BIT_H2CQ_FULL; 429 bckp_idx++; 430 tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; 431 rtw_write8(rtwdev, REG_CR, tmp); 432 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 433 434 /* Config hi priority queue and public priority queue page number */ 435 bckp[bckp_idx].len = 2; 436 bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; 437 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); 438 bckp_idx++; 439 bckp[bckp_idx].len = 4; 440 bckp[bckp_idx].reg = REG_RQPN_CTRL_2; 441 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; 442 bckp_idx++; 443 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200); 444 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); 445 446 /* Disable beacon related functions */ 447 tmp = rtw_read8(rtwdev, REG_BCN_CTRL); 448 bckp[bckp_idx].len = 1; 449 bckp[bckp_idx].reg = REG_BCN_CTRL; 450 bckp[bckp_idx].val = tmp; 451 bckp_idx++; 452 tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT); 453 rtw_write8(rtwdev, REG_BCN_CTRL, tmp); 454 455 WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n"); 456 } 457 458 static void download_firmware_reset_platform(struct rtw_dev *rtwdev) 459 { 460 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 461 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 462 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 463 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 464 } 465 466 static void download_firmware_reg_restore(struct rtw_dev *rtwdev, 467 struct rtw_backup_info *bckp, 468 u8 bckp_num) 469 { 470 rtw_restore_reg(rtwdev, bckp, bckp_num); 471 } 472 473 #define TX_DESC_SIZE 48 474 475 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 476 const u8 *data, u32 size) 477 { 478 u8 *buf; 479 int ret; 480 481 buf = kmemdup(data, size, GFP_KERNEL); 482 if (!buf) 483 return -ENOMEM; 484 485 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 486 kfree(buf); 487 return ret; 488 } 489 490 static int 491 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size) 492 { 493 int ret; 494 495 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 496 !((size + TX_DESC_SIZE) & (512 - 1))) 497 size += 1; 498 499 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size); 500 if (ret) 501 rtw_err(rtwdev, "failed to download rsvd page\n"); 502 503 return ret; 504 } 505 506 static int 507 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl) 508 { 509 rtw_write32(rtwdev, REG_DDMA_CH0SA, src); 510 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst); 511 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl); 512 513 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 514 return -EBUSY; 515 516 return 0; 517 } 518 519 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst, 520 u32 len, u8 first) 521 { 522 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; 523 524 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 525 return -EBUSY; 526 527 ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN; 528 if (!first) 529 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; 530 531 if (iddma_enable(rtwdev, src, dst, ch0_ctrl)) 532 return -EBUSY; 533 534 return 0; 535 } 536 537 static bool 538 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr) 539 { 540 u8 fw_ctrl; 541 542 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL); 543 544 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { 545 if (addr < OCPBASE_DMEM_88XX) { 546 fw_ctrl |= BIT_IMEM_DW_OK; 547 fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; 548 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 549 } else { 550 fw_ctrl |= BIT_DMEM_DW_OK; 551 fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; 552 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 553 } 554 555 rtw_err(rtwdev, "invalid fw checksum\n"); 556 557 return false; 558 } 559 560 if (addr < OCPBASE_DMEM_88XX) { 561 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); 562 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 563 } else { 564 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); 565 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 566 } 567 568 return true; 569 } 570 571 static int 572 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data, 573 u32 src, u32 dst, u32 size) 574 { 575 struct rtw_chip_info *chip = rtwdev->chip; 576 u32 desc_size = chip->tx_pkt_desc_sz; 577 u8 first_part; 578 u32 mem_offset; 579 u32 residue_size; 580 u32 pkt_size; 581 u32 max_size = 0x1000; 582 u32 val; 583 int ret; 584 585 mem_offset = 0; 586 first_part = 1; 587 residue_size = size; 588 589 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); 590 val |= BIT_DDMACH0_RESET_CHKSUM_STS; 591 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); 592 593 while (residue_size) { 594 if (residue_size >= max_size) 595 pkt_size = max_size; 596 else 597 pkt_size = residue_size; 598 599 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7), 600 data + mem_offset, pkt_size); 601 if (ret) 602 return ret; 603 604 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX + 605 src + desc_size, 606 dst + mem_offset, pkt_size, 607 first_part); 608 if (ret) 609 return ret; 610 611 first_part = 0; 612 mem_offset += pkt_size; 613 residue_size -= pkt_size; 614 } 615 616 if (!check_fw_checksum(rtwdev, dst)) 617 return -EINVAL; 618 619 return 0; 620 } 621 622 static int 623 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size) 624 { 625 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 626 const u8 *cur_fw; 627 u16 val; 628 u32 imem_size; 629 u32 dmem_size; 630 u32 emem_size; 631 u32 addr; 632 int ret; 633 634 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 635 imem_size = le32_to_cpu(fw_hdr->imem_size); 636 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 637 le32_to_cpu(fw_hdr->emem_size) : 0; 638 dmem_size += FW_HDR_CHKSUM_SIZE; 639 imem_size += FW_HDR_CHKSUM_SIZE; 640 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 641 642 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); 643 val |= BIT_MCUFWDL_EN; 644 rtw_write16(rtwdev, REG_MCUFW_CTRL, val); 645 646 cur_fw = data + FW_HDR_SIZE; 647 addr = le32_to_cpu(fw_hdr->dmem_addr); 648 addr &= ~BIT(31); 649 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size); 650 if (ret) 651 return ret; 652 653 cur_fw = data + FW_HDR_SIZE + dmem_size; 654 addr = le32_to_cpu(fw_hdr->imem_addr); 655 addr &= ~BIT(31); 656 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size); 657 if (ret) 658 return ret; 659 660 if (emem_size) { 661 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size; 662 addr = le32_to_cpu(fw_hdr->emem_addr); 663 addr &= ~BIT(31); 664 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, 665 emem_size); 666 if (ret) 667 return ret; 668 } 669 670 return 0; 671 } 672 673 static int download_firmware_validate(struct rtw_dev *rtwdev) 674 { 675 u32 fw_key; 676 677 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) { 678 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK; 679 if (fw_key == ILLEGAL_KEY_GROUP) 680 rtw_err(rtwdev, "invalid fw key\n"); 681 return -EINVAL; 682 } 683 684 return 0; 685 } 686 687 static void download_firmware_end_flow(struct rtw_dev *rtwdev) 688 { 689 u16 fw_ctrl; 690 691 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF); 692 693 /* Check IMEM & DMEM checksum is OK or not */ 694 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL); 695 if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK) 696 return; 697 698 fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN; 699 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 700 } 701 702 static int __rtw_download_firmware(struct rtw_dev *rtwdev, 703 struct rtw_fw_state *fw) 704 { 705 struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM]; 706 const u8 *data = fw->firmware->data; 707 u32 size = fw->firmware->size; 708 u32 ltecoex_bckp; 709 int ret; 710 711 if (!check_firmware_size(data, size)) 712 return -EINVAL; 713 714 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp)) 715 return -EBUSY; 716 717 wlan_cpu_enable(rtwdev, false); 718 719 download_firmware_reg_backup(rtwdev, bckp); 720 download_firmware_reset_platform(rtwdev); 721 722 ret = start_download_firmware(rtwdev, data, size); 723 if (ret) 724 goto dlfw_fail; 725 726 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM); 727 728 download_firmware_end_flow(rtwdev); 729 730 wlan_cpu_enable(rtwdev, true); 731 732 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) 733 return -EBUSY; 734 735 ret = download_firmware_validate(rtwdev); 736 if (ret) 737 goto dlfw_fail; 738 739 /* reset desc and index */ 740 rtw_hci_setup(rtwdev); 741 742 rtwdev->h2c.last_box_num = 0; 743 rtwdev->h2c.seq = 0; 744 745 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 746 747 return 0; 748 749 dlfw_fail: 750 /* Disable FWDL_EN */ 751 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 752 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 753 754 return ret; 755 } 756 757 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en) 758 { 759 int try; 760 761 if (en) { 762 wlan_cpu_enable(rtwdev, false); 763 wlan_cpu_enable(rtwdev, true); 764 765 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 766 767 for (try = 0; try < 10; try++) { 768 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN) 769 goto fwdl_ready; 770 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 771 msleep(20); 772 } 773 rtw_err(rtwdev, "failed to check fw download ready\n"); 774 fwdl_ready: 775 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN); 776 } else { 777 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 778 } 779 } 780 781 static void 782 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size) 783 { 784 u32 val32; 785 u32 block_nr; 786 u32 remain_size; 787 u32 write_addr = FW_START_ADDR_LEGACY; 788 const __le32 *ptr = (const __le32 *)data; 789 u32 block; 790 __le32 remain_data = 0; 791 792 block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY; 793 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1); 794 795 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 796 val32 &= ~BIT_ROM_PGE; 797 val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE; 798 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 799 800 for (block = 0; block < block_nr; block++) { 801 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr)); 802 803 write_addr += DLFW_BLK_SIZE_LEGACY; 804 ptr++; 805 } 806 807 if (remain_size) { 808 memcpy(&remain_data, ptr, remain_size); 809 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data)); 810 } 811 } 812 813 static int 814 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size) 815 { 816 u32 page; 817 u32 total_page; 818 u32 last_page_size; 819 820 data += sizeof(struct rtw_fw_hdr_legacy); 821 size -= sizeof(struct rtw_fw_hdr_legacy); 822 823 total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY; 824 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1); 825 826 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT); 827 828 for (page = 0; page < total_page; page++) { 829 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY); 830 data += DLFW_PAGE_SIZE_LEGACY; 831 } 832 if (last_page_size) 833 write_firmware_page(rtwdev, page, data, last_page_size); 834 835 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) { 836 rtw_err(rtwdev, "failed to check download firmware report\n"); 837 return -EINVAL; 838 } 839 840 return 0; 841 } 842 843 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev) 844 { 845 u32 val32; 846 int try; 847 848 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 849 val32 |= BIT_MCUFWDL_RDY; 850 val32 &= ~BIT_WINTINI_RDY; 851 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 852 853 wlan_cpu_enable(rtwdev, false); 854 wlan_cpu_enable(rtwdev, true); 855 856 for (try = 0; try < 10; try++) { 857 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 858 if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY) 859 return 0; 860 msleep(20); 861 } 862 863 rtw_err(rtwdev, "failed to validate firmware\n"); 864 return -EINVAL; 865 } 866 867 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev, 868 struct rtw_fw_state *fw) 869 { 870 int ret = 0; 871 872 en_download_firmware_legacy(rtwdev, true); 873 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size); 874 en_download_firmware_legacy(rtwdev, false); 875 if (ret) 876 goto out; 877 878 ret = download_firmware_validate_legacy(rtwdev); 879 if (ret) 880 goto out; 881 882 /* reset desc and index */ 883 rtw_hci_setup(rtwdev); 884 885 rtwdev->h2c.last_box_num = 0; 886 rtwdev->h2c.seq = 0; 887 888 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 889 890 out: 891 return ret; 892 } 893 894 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 895 { 896 if (rtw_chip_wcpu_11n(rtwdev)) 897 return __rtw_download_firmware_legacy(rtwdev, fw); 898 899 return __rtw_download_firmware(rtwdev, fw); 900 } 901 902 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues) 903 { 904 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn; 905 u32 prio_queues = 0; 906 907 if (queues & BIT(IEEE80211_AC_VO)) 908 prio_queues |= BIT(rqpn->dma_map_vo); 909 if (queues & BIT(IEEE80211_AC_VI)) 910 prio_queues |= BIT(rqpn->dma_map_vi); 911 if (queues & BIT(IEEE80211_AC_BE)) 912 prio_queues |= BIT(rqpn->dma_map_be); 913 if (queues & BIT(IEEE80211_AC_BK)) 914 prio_queues |= BIT(rqpn->dma_map_bk); 915 916 return prio_queues; 917 } 918 919 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev, 920 u32 prio_queue, bool drop) 921 { 922 u32 addr; 923 u16 avail_page, rsvd_page; 924 int i; 925 926 switch (prio_queue) { 927 case RTW_DMA_MAPPING_EXTRA: 928 addr = REG_FIFOPAGE_INFO_4; 929 break; 930 case RTW_DMA_MAPPING_LOW: 931 addr = REG_FIFOPAGE_INFO_2; 932 break; 933 case RTW_DMA_MAPPING_NORMAL: 934 addr = REG_FIFOPAGE_INFO_3; 935 break; 936 case RTW_DMA_MAPPING_HIGH: 937 addr = REG_FIFOPAGE_INFO_1; 938 break; 939 default: 940 return; 941 } 942 943 /* check if all of the reserved pages are available for 100 msecs */ 944 for (i = 0; i < 5; i++) { 945 rsvd_page = rtw_read16(rtwdev, addr); 946 avail_page = rtw_read16(rtwdev, addr + 2); 947 if (rsvd_page == avail_page) 948 return; 949 950 msleep(20); 951 } 952 953 /* priority queue is still not empty, throw a warning, 954 * 955 * Note that if we want to flush the tx queue when having a lot of 956 * traffic (ex, 100Mbps up), some of the packets could be dropped. 957 * And it requires like ~2secs to flush the full priority queue. 958 */ 959 if (!drop) 960 rtw_warn(rtwdev, "timed out to flush queue %d\n", prio_queue); 961 } 962 963 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev, 964 u32 prio_queues, bool drop) 965 { 966 u32 q; 967 968 for (q = 0; q < RTW_DMA_MAPPING_MAX; q++) 969 if (prio_queues & BIT(q)) 970 __rtw_mac_flush_prio_queue(rtwdev, q, drop); 971 } 972 973 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 974 { 975 u32 prio_queues = 0; 976 977 /* If all of the hardware queues are requested to flush, 978 * or the priority queues are not mapped yet, 979 * flush all of the priority queues 980 */ 981 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn) 982 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1; 983 else 984 prio_queues = get_priority_queues(rtwdev, queues); 985 986 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop); 987 } 988 989 static int txdma_queue_mapping(struct rtw_dev *rtwdev) 990 { 991 struct rtw_chip_info *chip = rtwdev->chip; 992 const struct rtw_rqpn *rqpn = NULL; 993 u16 txdma_pq_map = 0; 994 995 switch (rtw_hci_type(rtwdev)) { 996 case RTW_HCI_TYPE_PCIE: 997 rqpn = &chip->rqpn_table[1]; 998 break; 999 case RTW_HCI_TYPE_USB: 1000 if (rtwdev->hci.bulkout_num == 2) 1001 rqpn = &chip->rqpn_table[2]; 1002 else if (rtwdev->hci.bulkout_num == 3) 1003 rqpn = &chip->rqpn_table[3]; 1004 else if (rtwdev->hci.bulkout_num == 4) 1005 rqpn = &chip->rqpn_table[4]; 1006 else 1007 return -EINVAL; 1008 break; 1009 default: 1010 return -EINVAL; 1011 } 1012 1013 rtwdev->fifo.rqpn = rqpn; 1014 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi); 1015 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg); 1016 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk); 1017 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be); 1018 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi); 1019 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo); 1020 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map); 1021 1022 rtw_write8(rtwdev, REG_CR, 0); 1023 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE); 1024 if (rtw_chip_wcpu_11ac(rtwdev)) 1025 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 1026 1027 return 0; 1028 } 1029 1030 static int set_trx_fifo_info(struct rtw_dev *rtwdev) 1031 { 1032 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1033 struct rtw_chip_info *chip = rtwdev->chip; 1034 u16 cur_pg_addr; 1035 u8 csi_buf_pg_num = chip->csi_buf_pg_num; 1036 1037 /* config rsvd page num */ 1038 fifo->rsvd_drv_pg_num = 8; 1039 fifo->txff_pg_num = chip->txff_size >> 7; 1040 if (rtw_chip_wcpu_11n(rtwdev)) 1041 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num; 1042 else 1043 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num + 1044 RSVD_PG_H2C_EXTRAINFO_NUM + 1045 RSVD_PG_H2C_STATICINFO_NUM + 1046 RSVD_PG_H2CQ_NUM + 1047 RSVD_PG_CPU_INSTRUCTION_NUM + 1048 RSVD_PG_FW_TXBUF_NUM + 1049 csi_buf_pg_num; 1050 1051 if (fifo->rsvd_pg_num > fifo->txff_pg_num) 1052 return -ENOMEM; 1053 1054 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num; 1055 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num; 1056 1057 cur_pg_addr = fifo->txff_pg_num; 1058 if (rtw_chip_wcpu_11ac(rtwdev)) { 1059 cur_pg_addr -= csi_buf_pg_num; 1060 fifo->rsvd_csibuf_addr = cur_pg_addr; 1061 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; 1062 fifo->rsvd_fw_txbuf_addr = cur_pg_addr; 1063 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; 1064 fifo->rsvd_cpu_instr_addr = cur_pg_addr; 1065 cur_pg_addr -= RSVD_PG_H2CQ_NUM; 1066 fifo->rsvd_h2cq_addr = cur_pg_addr; 1067 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; 1068 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr; 1069 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; 1070 fifo->rsvd_h2c_info_addr = cur_pg_addr; 1071 } 1072 cur_pg_addr -= fifo->rsvd_drv_pg_num; 1073 fifo->rsvd_drv_addr = cur_pg_addr; 1074 1075 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) { 1076 rtw_err(rtwdev, "wrong rsvd driver address\n"); 1077 return -EINVAL; 1078 } 1079 1080 return 0; 1081 } 1082 1083 static int __priority_queue_cfg(struct rtw_dev *rtwdev, 1084 const struct rtw_page_table *pg_tbl, 1085 u16 pubq_num) 1086 { 1087 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1088 struct rtw_chip_info *chip = rtwdev->chip; 1089 1090 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num); 1091 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num); 1092 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num); 1093 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num); 1094 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num); 1095 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); 1096 1097 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary); 1098 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16); 1099 1100 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary); 1101 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); 1102 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); 1103 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); 1104 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); 1105 1106 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) 1107 return -EBUSY; 1108 1109 rtw_write8(rtwdev, REG_CR + 3, 0); 1110 1111 return 0; 1112 } 1113 1114 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev, 1115 const struct rtw_page_table *pg_tbl, 1116 u16 pubq_num) 1117 { 1118 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1119 struct rtw_chip_info *chip = rtwdev->chip; 1120 u32 val32; 1121 1122 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num); 1123 rtw_write32(rtwdev, REG_RQPN_NPQ, val32); 1124 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num); 1125 rtw_write32(rtwdev, REG_RQPN, val32); 1126 1127 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary); 1128 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1); 1129 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary); 1130 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary); 1131 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary); 1132 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary); 1133 1134 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT); 1135 1136 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0)) 1137 return -EBUSY; 1138 1139 return 0; 1140 } 1141 1142 static int priority_queue_cfg(struct rtw_dev *rtwdev) 1143 { 1144 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1145 struct rtw_chip_info *chip = rtwdev->chip; 1146 const struct rtw_page_table *pg_tbl = NULL; 1147 u16 pubq_num; 1148 int ret; 1149 1150 ret = set_trx_fifo_info(rtwdev); 1151 if (ret) 1152 return ret; 1153 1154 switch (rtw_hci_type(rtwdev)) { 1155 case RTW_HCI_TYPE_PCIE: 1156 pg_tbl = &chip->page_table[1]; 1157 break; 1158 case RTW_HCI_TYPE_USB: 1159 if (rtwdev->hci.bulkout_num == 2) 1160 pg_tbl = &chip->page_table[2]; 1161 else if (rtwdev->hci.bulkout_num == 3) 1162 pg_tbl = &chip->page_table[3]; 1163 else if (rtwdev->hci.bulkout_num == 4) 1164 pg_tbl = &chip->page_table[4]; 1165 else 1166 return -EINVAL; 1167 break; 1168 default: 1169 return -EINVAL; 1170 } 1171 1172 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num - 1173 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num; 1174 if (rtw_chip_wcpu_11n(rtwdev)) 1175 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num); 1176 else 1177 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num); 1178 } 1179 1180 static int init_h2c(struct rtw_dev *rtwdev) 1181 { 1182 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1183 u8 value8; 1184 u32 value32; 1185 u32 h2cq_addr; 1186 u32 h2cq_size; 1187 u32 h2cq_free; 1188 u32 wp, rp; 1189 1190 if (rtw_chip_wcpu_11n(rtwdev)) 1191 return 0; 1192 1193 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT; 1194 h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT; 1195 1196 value32 = rtw_read32(rtwdev, REG_H2C_HEAD); 1197 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1198 rtw_write32(rtwdev, REG_H2C_HEAD, value32); 1199 1200 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR); 1201 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1202 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32); 1203 1204 value32 = rtw_read32(rtwdev, REG_H2C_TAIL); 1205 value32 &= 0xFFFC0000; 1206 value32 |= (h2cq_addr + h2cq_size); 1207 rtw_write32(rtwdev, REG_H2C_TAIL, value32); 1208 1209 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1210 value8 = (u8)((value8 & 0xFC) | 0x01); 1211 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1212 1213 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1214 value8 = (u8)((value8 & 0xFB) | 0x04); 1215 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1216 1217 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1); 1218 value8 = (u8)((value8 & 0x7f) | 0x80); 1219 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8); 1220 1221 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; 1222 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF; 1223 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; 1224 1225 if (h2cq_size != h2cq_free) { 1226 rtw_err(rtwdev, "H2C queue mismatch\n"); 1227 return -EINVAL; 1228 } 1229 1230 return 0; 1231 } 1232 1233 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev) 1234 { 1235 int ret; 1236 1237 ret = txdma_queue_mapping(rtwdev); 1238 if (ret) 1239 return ret; 1240 1241 ret = priority_queue_cfg(rtwdev); 1242 if (ret) 1243 return ret; 1244 1245 ret = init_h2c(rtwdev); 1246 if (ret) 1247 return ret; 1248 1249 return 0; 1250 } 1251 1252 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev) 1253 { 1254 u8 value8; 1255 1256 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE); 1257 if (rtw_chip_wcpu_11ac(rtwdev)) { 1258 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1); 1259 value8 &= 0xF0; 1260 /* For rxdesc len = 0 issue */ 1261 value8 |= 0xF; 1262 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8); 1263 } 1264 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); 1265 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); 1266 1267 return 0; 1268 } 1269 1270 int rtw_mac_init(struct rtw_dev *rtwdev) 1271 { 1272 struct rtw_chip_info *chip = rtwdev->chip; 1273 int ret; 1274 1275 ret = rtw_init_trx_cfg(rtwdev); 1276 if (ret) 1277 return ret; 1278 1279 ret = chip->ops->mac_init(rtwdev); 1280 if (ret) 1281 return ret; 1282 1283 ret = rtw_drv_info_cfg(rtwdev); 1284 if (ret) 1285 return ret; 1286 1287 rtw_hci_interface_cfg(rtwdev); 1288 1289 return 0; 1290 } 1291