1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "mac.h" 7 #include "reg.h" 8 #include "fw.h" 9 #include "debug.h" 10 #include "sdio.h" 11 12 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, 13 u8 primary_ch_idx) 14 { 15 u8 txsc40 = 0, txsc20 = 0; 16 u32 value32; 17 u8 value8; 18 19 txsc20 = primary_ch_idx; 20 if (bw == RTW_CHANNEL_WIDTH_80) { 21 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 22 txsc40 = RTW_SC_40_UPPER; 23 else 24 txsc40 = RTW_SC_40_LOWER; 25 } 26 rtw_write8(rtwdev, REG_DATA_SC, 27 BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); 28 29 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL); 30 value32 &= ~BIT_RFMOD; 31 switch (bw) { 32 case RTW_CHANNEL_WIDTH_80: 33 value32 |= BIT_RFMOD_80M; 34 break; 35 case RTW_CHANNEL_WIDTH_40: 36 value32 |= BIT_RFMOD_40M; 37 break; 38 case RTW_CHANNEL_WIDTH_20: 39 default: 40 break; 41 } 42 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32); 43 44 if (rtw_chip_wcpu_11n(rtwdev)) 45 return; 46 47 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL); 48 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); 49 rtw_write32(rtwdev, REG_AFE_CTRL1, value32); 50 51 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 52 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 53 54 value8 = rtw_read8(rtwdev, REG_CCK_CHECK); 55 value8 = value8 & ~BIT_CHECK_CCK_EN; 56 if (IS_CH_5G_BAND(channel)) 57 value8 |= BIT_CHECK_CCK_EN; 58 rtw_write8(rtwdev, REG_CCK_CHECK, value8); 59 } 60 EXPORT_SYMBOL(rtw_set_channel_mac); 61 62 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev) 63 { 64 unsigned int retry; 65 u32 value32; 66 u8 value8; 67 68 rtw_write8(rtwdev, REG_RSV_CTRL, 0); 69 70 if (rtw_chip_wcpu_11n(rtwdev)) { 71 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO) 72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL); 73 else 74 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL); 75 return 0; 76 } 77 78 switch (rtw_hci_type(rtwdev)) { 79 case RTW_HCI_TYPE_PCIE: 80 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); 81 break; 82 case RTW_HCI_TYPE_SDIO: 83 rtw_write8_clr(rtwdev, REG_SDIO_HSUS_CTRL, BIT_HCI_SUS_REQ); 84 85 for (retry = 0; retry < RTW_PWR_POLLING_CNT; retry++) { 86 if (rtw_read8(rtwdev, REG_SDIO_HSUS_CTRL) & BIT_HCI_RESUME_RDY) 87 break; 88 89 usleep_range(10, 50); 90 } 91 92 if (retry == RTW_PWR_POLLING_CNT) { 93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]"); 94 return -ETIMEDOUT; 95 } 96 97 if (rtw_sdio_is_sdio30_supported(rtwdev)) 98 rtw_write8_set(rtwdev, REG_HCI_OPT_CTRL + 2, 99 BIT_SDIO_PAD_E5 >> 16); 100 else 101 rtw_write8_clr(rtwdev, REG_HCI_OPT_CTRL + 2, 102 BIT_SDIO_PAD_E5 >> 16); 103 break; 104 case RTW_HCI_TYPE_USB: 105 break; 106 default: 107 return -EINVAL; 108 } 109 110 /* config PIN Mux */ 111 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); 112 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL; 113 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); 114 115 value32 = rtw_read32(rtwdev, REG_LED_CFG); 116 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN); 117 rtw_write32(rtwdev, REG_LED_CFG, value32); 118 119 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG); 120 value32 |= BIT_WLRFE_4_5_EN; 121 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32); 122 123 /* disable BB/RF */ 124 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 125 value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 126 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8); 127 128 value8 = rtw_read8(rtwdev, REG_RF_CTRL); 129 value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN); 130 rtw_write8(rtwdev, REG_RF_CTRL, value8); 131 132 value32 = rtw_read32(rtwdev, REG_WLRF1); 133 value32 &= ~BIT_WLRF1_BBRF_EN; 134 rtw_write32(rtwdev, REG_WLRF1, value32); 135 136 return 0; 137 } 138 139 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target) 140 { 141 u32 val; 142 143 target &= mask; 144 145 return read_poll_timeout_atomic(rtw_read8, val, (val & mask) == target, 146 50, 50 * RTW_PWR_POLLING_CNT, false, 147 rtwdev, addr) == 0; 148 } 149 150 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev, 151 const struct rtw_pwr_seq_cmd *cmd) 152 { 153 u8 value; 154 u32 offset; 155 156 if (cmd->base == RTW_PWR_ADDR_SDIO) 157 offset = cmd->offset | SDIO_LOCAL_OFFSET; 158 else 159 offset = cmd->offset; 160 161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 162 return 0; 163 164 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE) 165 goto err; 166 167 /* if PCIE, toggle BIT_PFM_WOWL and try again */ 168 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL); 169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 170 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 171 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 172 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 174 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 175 176 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 177 return 0; 178 179 err: 180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n", 181 offset, cmd->mask, cmd->value); 182 return -EBUSY; 183 } 184 185 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask, 186 u8 cut_mask, 187 const struct rtw_pwr_seq_cmd *cmd) 188 { 189 const struct rtw_pwr_seq_cmd *cur_cmd; 190 u32 offset; 191 u8 value; 192 193 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) { 194 if (!(cur_cmd->intf_mask & intf_mask) || 195 !(cur_cmd->cut_mask & cut_mask)) 196 continue; 197 198 switch (cur_cmd->cmd) { 199 case RTW_PWR_CMD_WRITE: 200 offset = cur_cmd->offset; 201 202 if (cur_cmd->base == RTW_PWR_ADDR_SDIO) 203 offset |= SDIO_LOCAL_OFFSET; 204 205 value = rtw_read8(rtwdev, offset); 206 value &= ~cur_cmd->mask; 207 value |= (cur_cmd->value & cur_cmd->mask); 208 rtw_write8(rtwdev, offset, value); 209 break; 210 case RTW_PWR_CMD_POLLING: 211 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd)) 212 return -EBUSY; 213 break; 214 case RTW_PWR_CMD_DELAY: 215 if (cur_cmd->value == RTW_PWR_DELAY_US) 216 udelay(cur_cmd->offset); 217 else 218 mdelay(cur_cmd->offset); 219 break; 220 case RTW_PWR_CMD_READ: 221 break; 222 default: 223 return -EINVAL; 224 } 225 } 226 227 return 0; 228 } 229 230 int rtw_pwr_seq_parser(struct rtw_dev *rtwdev, 231 const struct rtw_pwr_seq_cmd * const *cmd_seq) 232 { 233 u8 cut_mask; 234 u8 intf_mask; 235 u8 cut; 236 u32 idx = 0; 237 const struct rtw_pwr_seq_cmd *cmd; 238 int ret; 239 240 cut = rtwdev->hal.cut_version; 241 cut_mask = cut_version_to_mask(cut); 242 switch (rtw_hci_type(rtwdev)) { 243 case RTW_HCI_TYPE_PCIE: 244 intf_mask = RTW_PWR_INTF_PCI_MSK; 245 break; 246 case RTW_HCI_TYPE_USB: 247 intf_mask = RTW_PWR_INTF_USB_MSK; 248 break; 249 case RTW_HCI_TYPE_SDIO: 250 intf_mask = RTW_PWR_INTF_SDIO_MSK; 251 break; 252 default: 253 return -EINVAL; 254 } 255 256 do { 257 cmd = cmd_seq[idx]; 258 if (!cmd) 259 break; 260 261 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd); 262 if (ret) 263 return ret; 264 265 idx++; 266 } while (1); 267 268 return 0; 269 } 270 EXPORT_SYMBOL(rtw_pwr_seq_parser); 271 272 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) 273 { 274 const struct rtw_chip_info *chip = rtwdev->chip; 275 const struct rtw_pwr_seq_cmd * const *pwr_seq; 276 u32 imr = 0; 277 u8 rpwm; 278 bool cur_pwr; 279 int ret; 280 281 if (rtw_chip_wcpu_11ac(rtwdev)) { 282 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr); 283 284 /* Check FW still exist or not */ 285 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) { 286 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE; 287 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm); 288 } 289 } 290 291 if (rtw_read8(rtwdev, REG_CR) == 0xea) 292 cur_pwr = false; 293 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 294 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) 295 cur_pwr = false; 296 else 297 cur_pwr = true; 298 299 if (pwr_on == cur_pwr) 300 return -EALREADY; 301 302 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) { 303 imr = rtw_read32(rtwdev, REG_SDIO_HIMR); 304 rtw_write32(rtwdev, REG_SDIO_HIMR, 0); 305 } 306 307 if (!pwr_on) 308 clear_bit(RTW_FLAG_POWERON, rtwdev->flags); 309 310 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; 311 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq); 312 313 if (pwr_on && rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { 314 if (chip->id == RTW_CHIP_TYPE_8822C || 315 chip->id == RTW_CHIP_TYPE_8822B || 316 chip->id == RTW_CHIP_TYPE_8821C) 317 rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0)); 318 } 319 320 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 321 rtw_write32(rtwdev, REG_SDIO_HIMR, imr); 322 323 if (!ret && pwr_on) 324 set_bit(RTW_FLAG_POWERON, rtwdev->flags); 325 326 return ret; 327 } 328 329 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 330 { 331 u8 sys_func_en = rtwdev->chip->sys_func_en; 332 u8 value8; 333 u32 value, tmp; 334 335 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON); 336 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN; 337 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value); 338 339 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en); 340 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C; 341 rtw_write8(rtwdev, REG_CR_EXT + 3, value8); 342 343 /* disable boot-from-flash for driver's DL FW */ 344 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL); 345 if (tmp & BIT_BOOT_FSPI_EN) { 346 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); 347 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); 348 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value); 349 } 350 351 return 0; 352 } 353 354 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev) 355 { 356 rtw_write8(rtwdev, REG_CR, 0xff); 357 mdelay(2); 358 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f); 359 mdelay(2); 360 361 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN); 362 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC); 363 364 rtw_write16(rtwdev, REG_CR, 0x2ff); 365 366 return 0; 367 } 368 369 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 370 { 371 if (rtw_chip_wcpu_11n(rtwdev)) 372 return __rtw_mac_init_system_cfg_legacy(rtwdev); 373 374 return __rtw_mac_init_system_cfg(rtwdev); 375 } 376 377 int rtw_mac_power_on(struct rtw_dev *rtwdev) 378 { 379 int ret = 0; 380 381 ret = rtw_mac_pre_system_cfg(rtwdev); 382 if (ret) 383 goto err; 384 385 ret = rtw_mac_power_switch(rtwdev, true); 386 if (ret == -EALREADY) { 387 rtw_mac_power_switch(rtwdev, false); 388 389 ret = rtw_mac_pre_system_cfg(rtwdev); 390 if (ret) 391 goto err; 392 393 ret = rtw_mac_power_switch(rtwdev, true); 394 if (ret) 395 goto err; 396 } else if (ret) { 397 goto err; 398 } 399 400 ret = rtw_mac_init_system_cfg(rtwdev); 401 if (ret) 402 goto err; 403 404 return 0; 405 406 err: 407 rtw_err(rtwdev, "mac power on failed"); 408 return ret; 409 } 410 411 void rtw_mac_power_off(struct rtw_dev *rtwdev) 412 { 413 rtw_mac_power_switch(rtwdev, false); 414 } 415 416 static bool check_firmware_size(const u8 *data, u32 size) 417 { 418 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 419 u32 dmem_size; 420 u32 imem_size; 421 u32 emem_size; 422 u32 real_size; 423 424 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 425 imem_size = le32_to_cpu(fw_hdr->imem_size); 426 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 427 le32_to_cpu(fw_hdr->emem_size) : 0; 428 429 dmem_size += FW_HDR_CHKSUM_SIZE; 430 imem_size += FW_HDR_CHKSUM_SIZE; 431 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 432 real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size; 433 if (real_size != size) 434 return false; 435 436 return true; 437 } 438 439 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable) 440 { 441 if (enable) { 442 /* cpu io interface enable */ 443 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 444 445 /* cpu enable */ 446 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 447 } else { 448 /* cpu io interface disable */ 449 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 450 451 /* cpu disable */ 452 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 453 } 454 } 455 456 #define DLFW_RESTORE_REG_NUM 6 457 458 static void download_firmware_reg_backup(struct rtw_dev *rtwdev, 459 struct rtw_backup_info *bckp) 460 { 461 u8 tmp; 462 u8 bckp_idx = 0; 463 464 /* set HIQ to hi priority */ 465 bckp[bckp_idx].len = 1; 466 bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; 467 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); 468 bckp_idx++; 469 tmp = RTW_DMA_MAPPING_HIGH << 6; 470 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp); 471 472 /* DLFW only use HIQ, map HIQ to hi priority */ 473 bckp[bckp_idx].len = 1; 474 bckp[bckp_idx].reg = REG_CR; 475 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); 476 bckp_idx++; 477 bckp[bckp_idx].len = 4; 478 bckp[bckp_idx].reg = REG_H2CQ_CSR; 479 bckp[bckp_idx].val = BIT_H2CQ_FULL; 480 bckp_idx++; 481 tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; 482 rtw_write8(rtwdev, REG_CR, tmp); 483 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 484 485 /* Config hi priority queue and public priority queue page number */ 486 bckp[bckp_idx].len = 2; 487 bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; 488 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); 489 bckp_idx++; 490 bckp[bckp_idx].len = 4; 491 bckp[bckp_idx].reg = REG_RQPN_CTRL_2; 492 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; 493 bckp_idx++; 494 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200); 495 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); 496 497 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 498 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG); 499 500 /* Disable beacon related functions */ 501 tmp = rtw_read8(rtwdev, REG_BCN_CTRL); 502 bckp[bckp_idx].len = 1; 503 bckp[bckp_idx].reg = REG_BCN_CTRL; 504 bckp[bckp_idx].val = tmp; 505 bckp_idx++; 506 tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT); 507 rtw_write8(rtwdev, REG_BCN_CTRL, tmp); 508 509 WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n"); 510 } 511 512 static void download_firmware_reset_platform(struct rtw_dev *rtwdev) 513 { 514 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 515 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 516 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 517 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 518 } 519 520 static void download_firmware_reg_restore(struct rtw_dev *rtwdev, 521 struct rtw_backup_info *bckp, 522 u8 bckp_num) 523 { 524 rtw_restore_reg(rtwdev, bckp, bckp_num); 525 } 526 527 #define TX_DESC_SIZE 48 528 529 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 530 const u8 *data, u32 size) 531 { 532 u8 *buf; 533 int ret; 534 535 buf = kmemdup(data, size, GFP_KERNEL); 536 if (!buf) 537 return -ENOMEM; 538 539 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 540 kfree(buf); 541 return ret; 542 } 543 544 static int 545 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size) 546 { 547 int ret; 548 549 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 550 !((size + TX_DESC_SIZE) & (512 - 1))) 551 size += 1; 552 553 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size); 554 if (ret) 555 rtw_err(rtwdev, "failed to download rsvd page\n"); 556 557 return ret; 558 } 559 560 static int 561 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl) 562 { 563 rtw_write32(rtwdev, REG_DDMA_CH0SA, src); 564 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst); 565 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl); 566 567 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 568 return -EBUSY; 569 570 return 0; 571 } 572 573 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst, 574 u32 len, u8 first) 575 { 576 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; 577 578 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 579 return -EBUSY; 580 581 ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN; 582 if (!first) 583 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; 584 585 if (iddma_enable(rtwdev, src, dst, ch0_ctrl)) 586 return -EBUSY; 587 588 return 0; 589 } 590 591 int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size) 592 { 593 u32 ch0_ctrl = BIT_DDMACH0_OWN | BIT_DDMACH0_DDMA_MODE; 594 595 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) { 596 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n"); 597 return -EBUSY; 598 } 599 600 ch0_ctrl |= size & BIT_MASK_DDMACH0_DLEN; 601 602 if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) { 603 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n"); 604 return -EBUSY; 605 } 606 607 return 0; 608 } 609 610 static bool 611 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr) 612 { 613 u8 fw_ctrl; 614 615 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL); 616 617 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { 618 if (addr < OCPBASE_DMEM_88XX) { 619 fw_ctrl |= BIT_IMEM_DW_OK; 620 fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; 621 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 622 } else { 623 fw_ctrl |= BIT_DMEM_DW_OK; 624 fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; 625 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 626 } 627 628 rtw_err(rtwdev, "invalid fw checksum\n"); 629 630 return false; 631 } 632 633 if (addr < OCPBASE_DMEM_88XX) { 634 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); 635 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 636 } else { 637 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); 638 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 639 } 640 641 return true; 642 } 643 644 static int 645 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data, 646 u32 src, u32 dst, u32 size) 647 { 648 const struct rtw_chip_info *chip = rtwdev->chip; 649 u32 desc_size = chip->tx_pkt_desc_sz; 650 u8 first_part; 651 u32 mem_offset; 652 u32 residue_size; 653 u32 pkt_size; 654 u32 max_size = 0x1000; 655 u32 val; 656 int ret; 657 658 mem_offset = 0; 659 first_part = 1; 660 residue_size = size; 661 662 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); 663 val |= BIT_DDMACH0_RESET_CHKSUM_STS; 664 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); 665 666 while (residue_size) { 667 if (residue_size >= max_size) 668 pkt_size = max_size; 669 else 670 pkt_size = residue_size; 671 672 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7), 673 data + mem_offset, pkt_size); 674 if (ret) 675 return ret; 676 677 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX + 678 src + desc_size, 679 dst + mem_offset, pkt_size, 680 first_part); 681 if (ret) 682 return ret; 683 684 first_part = 0; 685 mem_offset += pkt_size; 686 residue_size -= pkt_size; 687 } 688 689 if (!check_fw_checksum(rtwdev, dst)) 690 return -EINVAL; 691 692 return 0; 693 } 694 695 static int 696 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size) 697 { 698 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 699 const u8 *cur_fw; 700 u16 val; 701 u32 imem_size; 702 u32 dmem_size; 703 u32 emem_size; 704 u32 addr; 705 int ret; 706 707 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 708 imem_size = le32_to_cpu(fw_hdr->imem_size); 709 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 710 le32_to_cpu(fw_hdr->emem_size) : 0; 711 dmem_size += FW_HDR_CHKSUM_SIZE; 712 imem_size += FW_HDR_CHKSUM_SIZE; 713 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 714 715 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); 716 val |= BIT_MCUFWDL_EN; 717 rtw_write16(rtwdev, REG_MCUFW_CTRL, val); 718 719 cur_fw = data + FW_HDR_SIZE; 720 addr = le32_to_cpu(fw_hdr->dmem_addr); 721 addr &= ~BIT(31); 722 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size); 723 if (ret) 724 return ret; 725 726 cur_fw = data + FW_HDR_SIZE + dmem_size; 727 addr = le32_to_cpu(fw_hdr->imem_addr); 728 addr &= ~BIT(31); 729 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size); 730 if (ret) 731 return ret; 732 733 if (emem_size) { 734 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size; 735 addr = le32_to_cpu(fw_hdr->emem_addr); 736 addr &= ~BIT(31); 737 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, 738 emem_size); 739 if (ret) 740 return ret; 741 } 742 743 return 0; 744 } 745 746 static int download_firmware_validate(struct rtw_dev *rtwdev) 747 { 748 u32 fw_key; 749 750 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) { 751 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK; 752 if (fw_key == ILLEGAL_KEY_GROUP) 753 rtw_err(rtwdev, "invalid fw key\n"); 754 return -EINVAL; 755 } 756 757 return 0; 758 } 759 760 static void download_firmware_end_flow(struct rtw_dev *rtwdev) 761 { 762 u16 fw_ctrl; 763 764 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF); 765 766 /* Check IMEM & DMEM checksum is OK or not */ 767 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL); 768 if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK) 769 return; 770 771 fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN; 772 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 773 } 774 775 static int __rtw_download_firmware(struct rtw_dev *rtwdev, 776 struct rtw_fw_state *fw) 777 { 778 struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM]; 779 const u8 *data = fw->firmware->data; 780 u32 size = fw->firmware->size; 781 u32 ltecoex_bckp; 782 int ret; 783 784 if (!check_firmware_size(data, size)) 785 return -EINVAL; 786 787 if (rtwdev->chip->ltecoex_addr && 788 !ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp)) 789 return -EBUSY; 790 791 wlan_cpu_enable(rtwdev, false); 792 793 download_firmware_reg_backup(rtwdev, bckp); 794 download_firmware_reset_platform(rtwdev); 795 796 ret = start_download_firmware(rtwdev, data, size); 797 if (ret) 798 goto dlfw_fail; 799 800 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM); 801 802 download_firmware_end_flow(rtwdev); 803 804 wlan_cpu_enable(rtwdev, true); 805 806 if (rtwdev->chip->ltecoex_addr && 807 !ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) { 808 ret = -EBUSY; 809 goto dlfw_fail; 810 } 811 812 ret = download_firmware_validate(rtwdev); 813 if (ret) 814 goto dlfw_fail; 815 816 /* reset desc and index */ 817 rtw_hci_setup(rtwdev); 818 819 rtwdev->h2c.last_box_num = 0; 820 rtwdev->h2c.seq = 0; 821 822 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 823 824 return 0; 825 826 dlfw_fail: 827 /* Disable FWDL_EN */ 828 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 829 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 830 831 return ret; 832 } 833 834 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en) 835 { 836 int try; 837 838 if (en) { 839 wlan_cpu_enable(rtwdev, false); 840 wlan_cpu_enable(rtwdev, true); 841 842 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 843 844 for (try = 0; try < 10; try++) { 845 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN) 846 goto fwdl_ready; 847 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 848 msleep(20); 849 } 850 rtw_err(rtwdev, "failed to check fw download ready\n"); 851 fwdl_ready: 852 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN); 853 } else { 854 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 855 } 856 } 857 858 static void 859 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size) 860 { 861 u32 val32; 862 u32 block_nr; 863 u32 remain_size; 864 u32 write_addr = FW_START_ADDR_LEGACY; 865 const __le32 *ptr = (const __le32 *)data; 866 u32 block; 867 __le32 remain_data = 0; 868 869 block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY; 870 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1); 871 872 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 873 val32 &= ~BIT_ROM_PGE; 874 val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE; 875 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 876 877 for (block = 0; block < block_nr; block++) { 878 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr)); 879 880 write_addr += DLFW_BLK_SIZE_LEGACY; 881 ptr++; 882 } 883 884 if (remain_size) { 885 memcpy(&remain_data, ptr, remain_size); 886 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data)); 887 } 888 } 889 890 static int 891 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size) 892 { 893 u32 page; 894 u32 total_page; 895 u32 last_page_size; 896 897 data += sizeof(struct rtw_fw_hdr_legacy); 898 size -= sizeof(struct rtw_fw_hdr_legacy); 899 900 total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY; 901 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1); 902 903 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT); 904 905 for (page = 0; page < total_page; page++) { 906 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY); 907 data += DLFW_PAGE_SIZE_LEGACY; 908 } 909 if (last_page_size) 910 write_firmware_page(rtwdev, page, data, last_page_size); 911 912 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) { 913 rtw_err(rtwdev, "failed to check download firmware report\n"); 914 return -EINVAL; 915 } 916 917 return 0; 918 } 919 920 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev) 921 { 922 u32 val32; 923 int try; 924 925 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 926 val32 |= BIT_MCUFWDL_RDY; 927 val32 &= ~BIT_WINTINI_RDY; 928 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 929 930 wlan_cpu_enable(rtwdev, false); 931 wlan_cpu_enable(rtwdev, true); 932 933 for (try = 0; try < 10; try++) { 934 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 935 if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY) 936 return 0; 937 msleep(20); 938 } 939 940 rtw_err(rtwdev, "failed to validate firmware\n"); 941 return -EINVAL; 942 } 943 944 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev, 945 struct rtw_fw_state *fw) 946 { 947 int ret = 0; 948 949 /* reset firmware if still present */ 950 if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B && 951 rtw_read8_mask(rtwdev, REG_MCUFW_CTRL, BIT_RAM_DL_SEL)) { 952 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00); 953 } 954 955 en_download_firmware_legacy(rtwdev, true); 956 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size); 957 en_download_firmware_legacy(rtwdev, false); 958 if (ret) 959 goto out; 960 961 ret = download_firmware_validate_legacy(rtwdev); 962 if (ret) 963 goto out; 964 965 /* reset desc and index */ 966 rtw_hci_setup(rtwdev); 967 968 rtwdev->h2c.last_box_num = 0; 969 rtwdev->h2c.seq = 0; 970 971 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 972 973 out: 974 return ret; 975 } 976 977 static 978 int _rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 979 { 980 if (rtw_chip_wcpu_11n(rtwdev)) 981 return __rtw_download_firmware_legacy(rtwdev, fw); 982 983 return __rtw_download_firmware(rtwdev, fw); 984 } 985 986 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 987 { 988 int ret; 989 990 ret = _rtw_download_firmware(rtwdev, fw); 991 if (ret) 992 return ret; 993 994 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE && 995 rtwdev->chip->id == RTW_CHIP_TYPE_8821C) 996 rtw_fw_set_recover_bt_device(rtwdev); 997 998 return 0; 999 } 1000 EXPORT_SYMBOL(rtw_download_firmware); 1001 1002 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues) 1003 { 1004 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn; 1005 u32 prio_queues = 0; 1006 1007 if (queues & BIT(IEEE80211_AC_VO)) 1008 prio_queues |= BIT(rqpn->dma_map_vo); 1009 if (queues & BIT(IEEE80211_AC_VI)) 1010 prio_queues |= BIT(rqpn->dma_map_vi); 1011 if (queues & BIT(IEEE80211_AC_BE)) 1012 prio_queues |= BIT(rqpn->dma_map_be); 1013 if (queues & BIT(IEEE80211_AC_BK)) 1014 prio_queues |= BIT(rqpn->dma_map_bk); 1015 1016 return prio_queues; 1017 } 1018 1019 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev, 1020 u32 prio_queue, bool drop) 1021 { 1022 const struct rtw_chip_info *chip = rtwdev->chip; 1023 const struct rtw_prioq_addr *addr; 1024 bool wsize; 1025 u16 avail_page, rsvd_page; 1026 int i; 1027 1028 if (prio_queue >= RTW_DMA_MAPPING_MAX) 1029 return; 1030 1031 addr = &chip->prioq_addrs->prio[prio_queue]; 1032 wsize = chip->prioq_addrs->wsize; 1033 1034 /* check if all of the reserved pages are available for 100 msecs */ 1035 for (i = 0; i < 5; i++) { 1036 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) : 1037 rtw_read8(rtwdev, addr->rsvd); 1038 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) : 1039 rtw_read8(rtwdev, addr->avail); 1040 if (rsvd_page == avail_page) 1041 return; 1042 1043 msleep(20); 1044 } 1045 1046 /* priority queue is still not empty, throw a debug message 1047 * 1048 * Note that if we want to flush the tx queue when having a lot of 1049 * traffic (ex, 100Mbps up), some of the packets could be dropped. 1050 * And it requires like ~2secs to flush the full priority queue. 1051 */ 1052 if (!drop) 1053 rtw_dbg(rtwdev, RTW_DBG_UNEXP, 1054 "timed out to flush queue %d\n", prio_queue); 1055 } 1056 1057 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev, 1058 u32 prio_queues, bool drop) 1059 { 1060 u32 q; 1061 1062 for (q = 0; q < RTW_DMA_MAPPING_MAX; q++) 1063 if (prio_queues & BIT(q)) 1064 __rtw_mac_flush_prio_queue(rtwdev, q, drop); 1065 } 1066 1067 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 1068 { 1069 u32 prio_queues = 0; 1070 1071 /* If all of the hardware queues are requested to flush, 1072 * or the priority queues are not mapped yet, 1073 * flush all of the priority queues 1074 */ 1075 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn) 1076 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1; 1077 else 1078 prio_queues = get_priority_queues(rtwdev, queues); 1079 1080 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop); 1081 } 1082 1083 static int txdma_queue_mapping(struct rtw_dev *rtwdev) 1084 { 1085 const struct rtw_chip_info *chip = rtwdev->chip; 1086 const struct rtw_rqpn *rqpn = NULL; 1087 u16 txdma_pq_map = 0; 1088 1089 switch (rtw_hci_type(rtwdev)) { 1090 case RTW_HCI_TYPE_PCIE: 1091 rqpn = &chip->rqpn_table[1]; 1092 break; 1093 case RTW_HCI_TYPE_USB: 1094 if (rtwdev->hci.bulkout_num == 2) 1095 rqpn = &chip->rqpn_table[2]; 1096 else if (rtwdev->hci.bulkout_num == 3) 1097 rqpn = &chip->rqpn_table[3]; 1098 else if (rtwdev->hci.bulkout_num == 4) 1099 rqpn = &chip->rqpn_table[4]; 1100 else 1101 return -EINVAL; 1102 break; 1103 case RTW_HCI_TYPE_SDIO: 1104 rqpn = &chip->rqpn_table[0]; 1105 break; 1106 default: 1107 return -EINVAL; 1108 } 1109 1110 rtwdev->fifo.rqpn = rqpn; 1111 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi); 1112 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg); 1113 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk); 1114 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be); 1115 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi); 1116 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo); 1117 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map); 1118 1119 rtw_write8(rtwdev, REG_CR, 0); 1120 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE); 1121 if (rtw_chip_wcpu_11ac(rtwdev)) 1122 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 1123 1124 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) { 1125 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG); 1126 rtw_write32(rtwdev, REG_SDIO_TX_CTRL, 0); 1127 } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { 1128 rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_ARBBW_EN); 1129 } 1130 1131 return 0; 1132 } 1133 1134 int rtw_set_trx_fifo_info(struct rtw_dev *rtwdev) 1135 { 1136 const struct rtw_chip_info *chip = rtwdev->chip; 1137 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1138 u16 cur_pg_addr; 1139 u8 csi_buf_pg_num = chip->csi_buf_pg_num; 1140 1141 /* config rsvd page num */ 1142 fifo->rsvd_drv_pg_num = chip->rsvd_drv_pg_num; 1143 fifo->txff_pg_num = chip->txff_size / chip->page_size; 1144 if (rtw_chip_wcpu_11n(rtwdev)) 1145 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num; 1146 else 1147 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num + 1148 RSVD_PG_H2C_EXTRAINFO_NUM + 1149 RSVD_PG_H2C_STATICINFO_NUM + 1150 RSVD_PG_H2CQ_NUM + 1151 RSVD_PG_CPU_INSTRUCTION_NUM + 1152 RSVD_PG_FW_TXBUF_NUM + 1153 csi_buf_pg_num; 1154 1155 if (fifo->rsvd_pg_num > fifo->txff_pg_num) 1156 return -ENOMEM; 1157 1158 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num; 1159 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num; 1160 1161 cur_pg_addr = fifo->txff_pg_num; 1162 if (rtw_chip_wcpu_11ac(rtwdev)) { 1163 cur_pg_addr -= csi_buf_pg_num; 1164 fifo->rsvd_csibuf_addr = cur_pg_addr; 1165 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; 1166 fifo->rsvd_fw_txbuf_addr = cur_pg_addr; 1167 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; 1168 fifo->rsvd_cpu_instr_addr = cur_pg_addr; 1169 cur_pg_addr -= RSVD_PG_H2CQ_NUM; 1170 fifo->rsvd_h2cq_addr = cur_pg_addr; 1171 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; 1172 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr; 1173 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; 1174 fifo->rsvd_h2c_info_addr = cur_pg_addr; 1175 } 1176 cur_pg_addr -= fifo->rsvd_drv_pg_num; 1177 fifo->rsvd_drv_addr = cur_pg_addr; 1178 1179 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) { 1180 rtw_err(rtwdev, "wrong rsvd driver address\n"); 1181 return -EINVAL; 1182 } 1183 1184 return 0; 1185 } 1186 EXPORT_SYMBOL(rtw_set_trx_fifo_info); 1187 1188 static int __priority_queue_cfg(struct rtw_dev *rtwdev, 1189 const struct rtw_page_table *pg_tbl, 1190 u16 pubq_num) 1191 { 1192 const struct rtw_chip_info *chip = rtwdev->chip; 1193 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1194 1195 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num); 1196 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num); 1197 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num); 1198 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num); 1199 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num); 1200 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); 1201 1202 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary); 1203 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16); 1204 1205 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary); 1206 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); 1207 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); 1208 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); 1209 1210 if (rtwdev->hci.type == RTW_HCI_TYPE_USB) { 1211 rtw_write8_mask(rtwdev, REG_AUTO_LLT_V1, BIT_MASK_BLK_DESC_NUM, 1212 chip->usb_tx_agg_desc_num); 1213 1214 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num); 1215 rtw_write8_set(rtwdev, REG_TXDMA_OFFSET_CHK + 1, BIT(1)); 1216 } 1217 1218 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); 1219 1220 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) 1221 return -EBUSY; 1222 1223 rtw_write8(rtwdev, REG_CR + 3, 0); 1224 1225 return 0; 1226 } 1227 1228 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev, 1229 const struct rtw_page_table *pg_tbl, 1230 u16 pubq_num) 1231 { 1232 const struct rtw_chip_info *chip = rtwdev->chip; 1233 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1234 u32 val32; 1235 1236 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num); 1237 rtw_write32(rtwdev, REG_RQPN_NPQ, val32); 1238 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num); 1239 rtw_write32(rtwdev, REG_RQPN, val32); 1240 1241 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary); 1242 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1); 1243 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary); 1244 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary); 1245 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary); 1246 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary); 1247 1248 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT); 1249 1250 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0)) 1251 return -EBUSY; 1252 1253 return 0; 1254 } 1255 1256 static int priority_queue_cfg(struct rtw_dev *rtwdev) 1257 { 1258 const struct rtw_chip_info *chip = rtwdev->chip; 1259 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1260 const struct rtw_page_table *pg_tbl = NULL; 1261 u16 pubq_num; 1262 int ret; 1263 1264 ret = rtw_set_trx_fifo_info(rtwdev); 1265 if (ret) 1266 return ret; 1267 1268 switch (rtw_hci_type(rtwdev)) { 1269 case RTW_HCI_TYPE_PCIE: 1270 pg_tbl = &chip->page_table[1]; 1271 break; 1272 case RTW_HCI_TYPE_USB: 1273 if (rtwdev->hci.bulkout_num == 2) 1274 pg_tbl = &chip->page_table[2]; 1275 else if (rtwdev->hci.bulkout_num == 3) 1276 pg_tbl = &chip->page_table[3]; 1277 else if (rtwdev->hci.bulkout_num == 4) 1278 pg_tbl = &chip->page_table[4]; 1279 else 1280 return -EINVAL; 1281 break; 1282 case RTW_HCI_TYPE_SDIO: 1283 pg_tbl = &chip->page_table[0]; 1284 break; 1285 default: 1286 return -EINVAL; 1287 } 1288 1289 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num - 1290 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num; 1291 if (rtw_chip_wcpu_11n(rtwdev)) 1292 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num); 1293 else 1294 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num); 1295 } 1296 1297 static int init_h2c(struct rtw_dev *rtwdev) 1298 { 1299 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1300 u8 value8; 1301 u32 value32; 1302 u32 h2cq_addr; 1303 u32 h2cq_size; 1304 u32 h2cq_free; 1305 u32 wp, rp; 1306 1307 if (rtw_chip_wcpu_11n(rtwdev)) 1308 return 0; 1309 1310 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT; 1311 h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT; 1312 1313 value32 = rtw_read32(rtwdev, REG_H2C_HEAD); 1314 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1315 rtw_write32(rtwdev, REG_H2C_HEAD, value32); 1316 1317 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR); 1318 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1319 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32); 1320 1321 value32 = rtw_read32(rtwdev, REG_H2C_TAIL); 1322 value32 &= 0xFFFC0000; 1323 value32 |= (h2cq_addr + h2cq_size); 1324 rtw_write32(rtwdev, REG_H2C_TAIL, value32); 1325 1326 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1327 value8 = (u8)((value8 & 0xFC) | 0x01); 1328 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1329 1330 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1331 value8 = (u8)((value8 & 0xFB) | 0x04); 1332 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1333 1334 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1); 1335 value8 = (u8)((value8 & 0x7f) | 0x80); 1336 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8); 1337 1338 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; 1339 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF; 1340 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; 1341 1342 if (h2cq_size != h2cq_free) { 1343 rtw_err(rtwdev, "H2C queue mismatch\n"); 1344 return -EINVAL; 1345 } 1346 1347 return 0; 1348 } 1349 1350 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev) 1351 { 1352 int ret; 1353 1354 ret = txdma_queue_mapping(rtwdev); 1355 if (ret) 1356 return ret; 1357 1358 ret = priority_queue_cfg(rtwdev); 1359 if (ret) 1360 return ret; 1361 1362 ret = init_h2c(rtwdev); 1363 if (ret) 1364 return ret; 1365 1366 return 0; 1367 } 1368 1369 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev) 1370 { 1371 u8 value8; 1372 1373 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE); 1374 if (rtw_chip_wcpu_11ac(rtwdev)) { 1375 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1); 1376 value8 &= 0xF0; 1377 /* For rxdesc len = 0 issue */ 1378 value8 |= 0xF; 1379 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8); 1380 } 1381 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); 1382 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); 1383 1384 return 0; 1385 } 1386 1387 int rtw_mac_init(struct rtw_dev *rtwdev) 1388 { 1389 const struct rtw_chip_info *chip = rtwdev->chip; 1390 int ret; 1391 1392 ret = rtw_init_trx_cfg(rtwdev); 1393 if (ret) 1394 return ret; 1395 1396 ret = chip->ops->mac_init(rtwdev); 1397 if (ret) 1398 return ret; 1399 1400 ret = rtw_drv_info_cfg(rtwdev); 1401 if (ret) 1402 return ret; 1403 1404 rtw_hci_interface_cfg(rtwdev); 1405 1406 return 0; 1407 } 1408