1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FW_NLO_INFO_CHECK_SIZE 4 16 17 #define FIFO_PAGE_SIZE_SHIFT 12 18 #define FIFO_PAGE_SIZE 4096 19 #define FIFO_DUMP_ADDR 0x8000 20 21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12 22 #define DLFW_PAGE_SIZE_LEGACY 0x1000 23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2 24 #define DLFW_BLK_SIZE_LEGACY 4 25 #define FW_START_ADDR_LEGACY 0x1000 26 27 #define BCN_LOSS_CNT 10 28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0 29 #define BCN_FILTER_CONNECTION_LOSS 1 30 #define BCN_FILTER_CONNECTED 2 31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3 32 33 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10) 34 35 #define RTW_CHANNEL_TIME 45 36 #define RTW_OFF_CHAN_TIME 100 37 #define RTW_PASS_CHAN_TIME 105 38 #define RTW_DFS_CHAN_TIME 20 39 #define RTW_CH_INFO_SIZE 4 40 #define RTW_EX_CH_INFO_SIZE 3 41 #define RTW_EX_CH_INFO_HDR_SIZE 2 42 #define RTW_SCAN_WIDTH 0 43 #define RTW_PRI_CH_IDX 1 44 #define RTW_OLD_PROBE_PG_CNT 2 45 #define RTW_PROBE_PG_CNT 4 46 47 enum rtw_c2h_cmd_id { 48 C2H_CCX_TX_RPT = 0x03, 49 C2H_BT_INFO = 0x09, 50 C2H_BT_MP_INFO = 0x0b, 51 C2H_BT_HID_INFO = 0x45, 52 C2H_RA_RPT = 0x0c, 53 C2H_HW_FEATURE_REPORT = 0x19, 54 C2H_WLAN_INFO = 0x27, 55 C2H_WLAN_RFON = 0x32, 56 C2H_BCN_FILTER_NOTIFY = 0x36, 57 C2H_ADAPTIVITY = 0x37, 58 C2H_SCAN_RESULT = 0x38, 59 C2H_HW_FEATURE_DUMP = 0xfd, 60 C2H_HALMAC = 0xff, 61 }; 62 63 enum rtw_c2h_cmd_id_ext { 64 C2H_SCAN_STATUS_RPT = 0x3, 65 C2H_CCX_RPT = 0x0f, 66 C2H_CHAN_SWITCH = 0x22, 67 }; 68 69 struct rtw_c2h_cmd { 70 u8 id; 71 u8 seq; 72 u8 payload[]; 73 } __packed; 74 75 struct rtw_c2h_adaptivity { 76 u8 density; 77 u8 igi; 78 u8 l2h_th_init; 79 u8 l2h; 80 u8 h2l; 81 u8 option; 82 } __packed; 83 84 struct rtw_h2c_cmd { 85 __le32 msg; 86 __le32 msg_ext; 87 } __packed; 88 89 enum rtw_rsvd_packet_type { 90 RSVD_BEACON, 91 RSVD_DUMMY, 92 RSVD_PS_POLL, 93 RSVD_PROBE_RESP, 94 RSVD_NULL, 95 RSVD_QOS_NULL, 96 RSVD_LPS_PG_DPK, 97 RSVD_LPS_PG_INFO, 98 RSVD_PROBE_REQ, 99 RSVD_NLO_INFO, 100 RSVD_CH_INFO, 101 }; 102 103 enum rtw_fw_rf_type { 104 FW_RF_1T2R = 0, 105 FW_RF_2T4R = 1, 106 FW_RF_2T2R = 2, 107 FW_RF_2T3R = 3, 108 FW_RF_1T1R = 4, 109 FW_RF_2T2R_GREEN = 5, 110 FW_RF_3T3R = 6, 111 FW_RF_3T4R = 7, 112 FW_RF_4T4R = 8, 113 FW_RF_MAX_TYPE = 0xF, 114 }; 115 116 enum rtw_fw_feature { 117 FW_FEATURE_SIG = BIT(0), 118 FW_FEATURE_LPS_C2H = BIT(1), 119 FW_FEATURE_LCLK = BIT(2), 120 FW_FEATURE_PG = BIT(3), 121 FW_FEATURE_TX_WAKE = BIT(4), 122 FW_FEATURE_BCN_FILTER = BIT(5), 123 FW_FEATURE_NOTIFY_SCAN = BIT(6), 124 FW_FEATURE_ADAPTIVITY = BIT(7), 125 FW_FEATURE_SCAN_OFFLOAD = BIT(8), 126 FW_FEATURE_MAX = BIT(31), 127 }; 128 129 enum rtw_fw_feature_ext { 130 FW_FEATURE_EXT_OLD_PAGE_NUM = BIT(0), 131 }; 132 133 enum rtw_beacon_filter_offload_mode { 134 BCN_FILTER_OFFLOAD_MODE_0 = 0, 135 BCN_FILTER_OFFLOAD_MODE_1, 136 BCN_FILTER_OFFLOAD_MODE_2, 137 BCN_FILTER_OFFLOAD_MODE_3, 138 139 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0, 140 }; 141 142 struct rtw_coex_info_req { 143 u8 seq; 144 u8 op_code; 145 u8 para1; 146 u8 para2; 147 u8 para3; 148 }; 149 150 struct rtw_iqk_para { 151 u8 clear; 152 u8 segment_iqk; 153 }; 154 155 struct rtw_lps_pg_dpk_hdr { 156 u16 dpk_path_ok; 157 u8 dpk_txagc[2]; 158 u16 dpk_gs[2]; 159 u32 coef[2][20]; 160 u8 dpk_ch; 161 } __packed; 162 163 struct rtw_lps_pg_info_hdr { 164 u8 macid; 165 u8 mbssid; 166 u8 pattern_count; 167 u8 mu_tab_group_id; 168 u8 sec_cam_count; 169 u8 tx_bu_page_count; 170 u16 rsvd; 171 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 172 } __packed; 173 174 struct rtw_rsvd_page { 175 /* associated with each vif */ 176 struct list_head vif_list; 177 struct rtw_vif *rtwvif; 178 179 /* associated when build rsvd page */ 180 struct list_head build_list; 181 182 struct sk_buff *skb; 183 enum rtw_rsvd_packet_type type; 184 u8 page; 185 u16 tim_offset; 186 bool add_txdesc; 187 struct cfg80211_ssid *ssid; 188 u16 probe_req_size; 189 }; 190 191 enum rtw_keep_alive_pkt_type { 192 KEEP_ALIVE_NULL_PKT = 0, 193 KEEP_ALIVE_ARP_RSP = 1, 194 }; 195 196 struct rtw_nlo_info_hdr { 197 u8 nlo_count; 198 u8 hidden_ap_count; 199 u8 rsvd1[2]; 200 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; 201 u8 rsvd2[8]; 202 u8 ssid_len[16]; 203 u8 chiper[16]; 204 u8 rsvd3[16]; 205 u8 location[8]; 206 } __packed; 207 208 enum rtw_packet_type { 209 RTW_PACKET_PROBE_REQ = 0x00, 210 211 RTW_PACKET_UNDEFINE = 0x7FFFFFFF, 212 }; 213 214 struct rtw_fw_wow_keep_alive_para { 215 bool adopt; 216 u8 pkt_type; 217 u8 period; /* unit: sec */ 218 }; 219 220 struct rtw_fw_wow_disconnect_para { 221 bool adopt; 222 u8 period; /* unit: sec */ 223 u8 retry_count; 224 }; 225 226 enum rtw_channel_type { 227 RTW_CHANNEL_PASSIVE, 228 RTW_CHANNEL_ACTIVE, 229 RTW_CHANNEL_RADAR, 230 }; 231 232 enum rtw_scan_extra_id { 233 RTW_SCAN_EXTRA_ID_DFS, 234 }; 235 236 enum rtw_scan_extra_info { 237 RTW_SCAN_EXTRA_ACTION_SCAN, 238 }; 239 240 enum rtw_scan_report_code { 241 RTW_SCAN_REPORT_SUCCESS = 0x00, 242 RTW_SCAN_REPORT_ERR_PHYDM = 0x01, 243 RTW_SCAN_REPORT_ERR_ID = 0x02, 244 RTW_SCAN_REPORT_ERR_TX = 0x03, 245 RTW_SCAN_REPORT_CANCELED = 0x10, 246 RTW_SCAN_REPORT_CANCELED_EXT = 0x11, 247 RTW_SCAN_REPORT_FW_DISABLED = 0xF0, 248 }; 249 250 enum rtw_scan_notify_id { 251 RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00, 252 RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01, 253 RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02, 254 RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03, 255 RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04, 256 RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05, 257 RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06, 258 RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07, 259 RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08, 260 RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09, 261 RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A, 262 }; 263 264 enum rtw_scan_notify_status { 265 RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00, 266 RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01, 267 RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02, 268 RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03, 269 }; 270 271 struct rtw_ch_switch_option { 272 u8 periodic_option; 273 u32 tsf_high; 274 u32 tsf_low; 275 u8 dest_ch_en; 276 u8 absolute_time_en; 277 u8 dest_ch; 278 u8 normal_period; 279 u8 normal_period_sel; 280 u8 normal_cycle; 281 u8 slow_period; 282 u8 slow_period_sel; 283 u8 nlo_en; 284 bool switch_en; 285 bool back_op_en; 286 }; 287 288 struct rtw_fw_hdr { 289 __le16 signature; 290 u8 category; 291 u8 function; 292 __le16 version; /* 0x04 */ 293 u8 subversion; 294 u8 subindex; 295 __le32 rsvd; /* 0x08 */ 296 __le32 feature; /* 0x0C */ 297 u8 month; /* 0x10 */ 298 u8 day; 299 u8 hour; 300 u8 min; 301 __le16 year; /* 0x14 */ 302 __le16 rsvd3; 303 u8 mem_usage; /* 0x18 */ 304 u8 rsvd4[3]; 305 __le16 h2c_fmt_ver; /* 0x1C */ 306 __le16 rsvd5; 307 __le32 dmem_addr; /* 0x20 */ 308 __le32 dmem_size; 309 __le32 rsvd6; 310 __le32 rsvd7; 311 __le32 imem_size; /* 0x30 */ 312 __le32 emem_size; 313 __le32 emem_addr; 314 __le32 imem_addr; 315 } __packed; 316 317 struct rtw_fw_hdr_legacy { 318 __le16 signature; 319 u8 category; 320 u8 function; 321 __le16 version; /* 0x04 */ 322 u8 subversion1; 323 u8 subversion2; 324 u8 month; /* 0x08 */ 325 u8 day; 326 u8 hour; 327 u8 minute; 328 __le16 size; 329 __le16 rsvd2; 330 __le32 idx; /* 0x10 */ 331 __le32 rsvd3; 332 __le32 rsvd4; /* 0x18 */ 333 __le32 rsvd5; 334 } __packed; 335 336 #define RTW_FW_VER_CODE(ver, sub_ver, idx) \ 337 (((ver) << 16) | ((sub_ver) << 8) | (idx)) 338 #define RTW_FW_SUIT_VER_CODE(s) \ 339 RTW_FW_VER_CODE((s).version, (s).sub_version, (s).sub_index) 340 341 /* C2H */ 342 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc) 343 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0) 344 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc) 345 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0) 346 347 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload) (c2h_payload[2] & 0xff) 348 349 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2]) 350 #define GET_CHAN_SWITCH_ID(c2h_payload) (c2h_payload[3]) 351 #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4]) 352 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 353 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 354 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 355 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 356 357 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf) 358 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10) 359 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100) 360 361 /* PKT H2C */ 362 #define H2C_PKT_CMD_ID 0xFF 363 #define H2C_PKT_CATEGORY 0x01 364 365 #define H2C_PKT_GENERAL_INFO 0x0D 366 #define H2C_PKT_PHYDM_INFO 0x11 367 #define H2C_PKT_IQK 0x0E 368 369 #define H2C_PKT_CH_SWITCH 0x02 370 #define H2C_PKT_UPDATE_PKT 0x0C 371 #define H2C_PKT_SCAN_OFFLOAD 0x19 372 373 #define H2C_PKT_CH_SWITCH_LEN 0x20 374 #define H2C_PKT_UPDATE_PKT_LEN 0x4 375 376 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 377 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 378 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 379 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 380 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 381 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 382 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 383 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 384 385 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 386 { 387 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 388 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 389 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 390 } 391 392 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 393 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 394 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 395 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 396 397 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 398 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 399 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 400 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 401 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 402 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 403 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 404 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 405 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 406 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 407 #define IQK_SET_CLEAR(h2c_pkt, value) \ 408 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 409 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 410 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 411 412 #define CHSW_INFO_SET_CH(pkt, value) \ 413 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) 414 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ 415 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) 416 #define CHSW_INFO_SET_BW(pkt, value) \ 417 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) 418 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ 419 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) 420 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ 421 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) 422 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value) \ 423 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31)) 424 425 #define CH_INFO_SET_CH(pkt, value) \ 426 u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0)) 427 #define CH_INFO_SET_PRI_CH_IDX(pkt, value) \ 428 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0)) 429 #define CH_INFO_SET_BW(pkt, value) \ 430 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4)) 431 #define CH_INFO_SET_TIMEOUT(pkt, value) \ 432 u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0)) 433 #define CH_INFO_SET_ACTION_ID(pkt, value) \ 434 u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0)) 435 #define CH_INFO_SET_EXTRA_INFO(pkt, value) \ 436 u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7)) 437 438 #define EXTRA_CH_INFO_SET_ID(pkt, value) \ 439 u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0)) 440 #define EXTRA_CH_INFO_SET_INFO(pkt, value) \ 441 u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7)) 442 #define EXTRA_CH_INFO_SET_SIZE(pkt, value) \ 443 u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0)) 444 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value) \ 445 u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0)) 446 447 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ 448 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) 449 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ 450 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 451 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ 452 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) 453 454 #define CH_SWITCH_SET_START(h2c_pkt, value) \ 455 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 456 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ 457 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 458 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ 459 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 460 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ 461 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) 462 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \ 463 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5)) 464 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value) \ 465 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6)) 466 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ 467 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 468 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ 469 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 470 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ 471 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 472 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ 473 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 474 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ 475 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 476 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ 477 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) 478 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ 479 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) 480 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ 481 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) 482 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ 483 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) 484 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ 485 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) 486 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ 487 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) 488 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ 489 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) 490 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ 491 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) 492 493 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value) \ 494 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 495 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value) \ 496 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 497 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value) \ 498 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 499 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value) \ 500 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3)) 501 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value) \ 502 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4)) 503 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value) \ 504 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 505 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value) \ 506 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16)) 507 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value) \ 508 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 509 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value) \ 510 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8)) 511 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value) \ 512 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16)) 513 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value) \ 514 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20)) 515 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value) \ 516 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24)) 517 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value) \ 518 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0)) 519 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value) \ 520 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16)) 521 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value) \ 522 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0)) 523 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value) \ 524 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4)) 525 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value) \ 526 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8)) 527 528 /* Command H2C */ 529 #define H2C_CMD_RSVD_PAGE 0x0 530 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 531 #define H2C_CMD_SET_PWR_MODE 0x20 532 #define H2C_CMD_LPS_PG_INFO 0x2b 533 #define H2C_CMD_RA_INFO 0x40 534 #define H2C_CMD_RSSI_MONITOR 0x42 535 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56 536 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57 537 #define H2C_CMD_WL_PHY_INFO 0x58 538 #define H2C_CMD_SCAN 0x59 539 #define H2C_CMD_ADAPTIVITY 0x5A 540 541 #define H2C_CMD_COEX_TDMA_TYPE 0x60 542 #define H2C_CMD_QUERY_BT_INFO 0x61 543 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 544 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 545 #define H2C_CMD_WL_CH_INFO 0x66 546 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 547 #define H2C_CMD_BT_WIFI_CONTROL 0x69 548 #define H2C_CMD_WIFI_CALIBRATION 0x6d 549 #define H2C_CMD_QUERY_BT_HID_INFO 0x73 550 551 #define H2C_CMD_KEEP_ALIVE 0x03 552 #define H2C_CMD_DISCONNECT_DECISION 0x04 553 #define H2C_CMD_WOWLAN 0x80 554 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 555 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 556 #define H2C_CMD_NLO_INFO 0x8C 557 558 #define H2C_CMD_RECOVER_BT_DEV 0xD1 559 560 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 561 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 562 563 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 564 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 565 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 566 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 567 568 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \ 569 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8)) 570 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \ 571 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18)) 572 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \ 573 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 574 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \ 575 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 576 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \ 577 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 578 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \ 579 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 580 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \ 581 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16)) 582 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \ 583 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17)) 584 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \ 585 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21)) 586 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \ 587 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 588 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \ 589 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0)) 590 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \ 591 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4)) 592 593 #define SET_SCAN_START(h2c_pkt, value) \ 594 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 595 596 #define SET_ADAPTIVITY_MODE(h2c_pkt, value) \ 597 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8)) 598 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value) \ 599 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 600 #define SET_ADAPTIVITY_IGI(h2c_pkt, value) \ 601 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 602 #define SET_ADAPTIVITY_L2H(h2c_pkt, value) \ 603 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 604 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value) \ 605 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 606 607 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 608 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 609 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 610 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 611 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 612 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 613 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 614 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 615 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 616 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 617 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 618 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 619 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 620 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 621 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 622 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 623 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 624 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 625 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ 626 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 627 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 628 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 629 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 630 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 631 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 632 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 633 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 634 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 635 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 636 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 637 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 638 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 639 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 640 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 641 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 642 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 643 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 644 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 645 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 646 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 647 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 648 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 649 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 650 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 651 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 652 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 653 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 654 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 655 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 656 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 657 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 658 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 659 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 660 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 661 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 662 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 663 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 664 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 665 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 666 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 667 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 668 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 669 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 670 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 671 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 672 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 673 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 674 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 675 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 676 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 677 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 678 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 679 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 680 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 681 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 682 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 683 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 684 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 685 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 686 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 687 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 688 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 689 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 690 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 691 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 692 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 693 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 694 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 695 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 696 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 697 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 698 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 699 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 700 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 701 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 702 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 703 704 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value) \ 705 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 706 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value) \ 707 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 708 709 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ 710 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 711 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ 712 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 713 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ 714 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 715 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ 716 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 717 718 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ 719 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 720 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ 721 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 722 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ 723 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 724 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ 725 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 726 727 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ 728 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 729 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ 730 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 731 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ 732 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 733 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ 734 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) 735 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ 736 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) 737 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ 738 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) 739 740 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ 741 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 742 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ 743 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) 744 745 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ 746 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 747 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ 748 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 749 750 #define SET_NLO_FUN_EN(h2c_pkt, value) \ 751 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 752 #define SET_NLO_PS_32K(h2c_pkt, value) \ 753 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 754 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ 755 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 756 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ 757 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 758 759 #define SET_RECOVER_BT_DEV_EN(h2c_pkt, value) \ 760 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 761 762 #define GET_FW_DUMP_LEN(_header) \ 763 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0)) 764 #define GET_FW_DUMP_SEQ(_header) \ 765 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16)) 766 #define GET_FW_DUMP_MORE(_header) \ 767 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23)) 768 #define GET_FW_DUMP_VERSION(_header) \ 769 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24)) 770 #define GET_FW_DUMP_TLV_TYPE(_header) \ 771 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0)) 772 #define GET_FW_DUMP_TLV_LEN(_header) \ 773 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16)) 774 #define GET_FW_DUMP_TLV_VAL(_header) \ 775 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0)) 776 777 #define RFK_SET_INFORM_START(h2c_pkt, value) \ 778 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 779 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 780 { 781 u32 pkt_offset; 782 783 pkt_offset = *((u32 *)skb->cb); 784 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 785 } 786 787 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw, 788 enum rtw_fw_feature feature) 789 { 790 return !!(fw->feature & feature); 791 } 792 793 static inline bool rtw_fw_feature_ext_check(struct rtw_fw_state *fw, 794 enum rtw_fw_feature_ext feature) 795 { 796 return !!(fw->feature_ext & feature); 797 } 798 799 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 800 struct sk_buff *skb); 801 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 802 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 803 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 804 805 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 806 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start); 807 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 808 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 809 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 810 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 811 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 812 struct rtw_coex_info_req *req); 813 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 814 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 815 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 816 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 817 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data); 818 819 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 820 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 821 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 822 bool reset_ra_mask); 823 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 824 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev); 825 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect, 826 struct ieee80211_vif *vif); 827 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 828 u8 *buf, u32 size); 829 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev, 830 struct rtw_vif *rtwvif); 831 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev, 832 struct rtw_vif *rtwvif); 833 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev, 834 struct rtw_vif *rtwvif); 835 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev, 836 struct rtw_vif *rtwvif); 837 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev); 838 void rtw_fw_update_beacon_work(struct work_struct *work); 839 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 840 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 841 u32 offset, u32 size, u32 *buf); 842 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 843 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 844 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); 845 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); 846 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, 847 u8 pairwise_key_enc, 848 u8 group_key_enc); 849 850 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); 851 void rtw_fw_set_recover_bt_device(struct rtw_dev *rtwdev); 852 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, 853 struct cfg80211_ssid *ssid); 854 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); 855 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c); 856 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev); 857 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size, 858 u32 *buffer); 859 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 860 void rtw_fw_adaptivity(struct rtw_dev *rtwdev); 861 void rtw_store_op_chan(struct rtw_dev *rtwdev, bool backup); 862 void rtw_clear_op_chan(struct rtw_dev *rtwdev); 863 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 864 struct ieee80211_scan_request *req); 865 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 866 bool aborted); 867 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 868 bool enable); 869 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb); 870 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb); 871 void rtw_hw_scan_abort(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 872 #endif 873