1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #ifndef __RTL_WIFI_H__ 5 #define __RTL_WIFI_H__ 6 7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 8 9 #include <linux/sched.h> 10 #include <linux/firmware.h> 11 #include <linux/etherdevice.h> 12 #include <linux/vmalloc.h> 13 #include <linux/usb.h> 14 #include <net/mac80211.h> 15 #include <linux/completion.h> 16 #include "debug.h" 17 18 #define MASKBYTE0 0xff 19 #define MASKBYTE1 0xff00 20 #define MASKBYTE2 0xff0000 21 #define MASKBYTE3 0xff000000 22 #define MASKHWORD 0xffff0000 23 #define MASKLWORD 0x0000ffff 24 #define MASKDWORD 0xffffffff 25 #define MASK12BITS 0xfff 26 #define MASKH4BITS 0xf0000000 27 #define MASKOFDM_D 0xffc00000 28 #define MASKCCK 0x3f3f3f3f 29 30 #define MASK4BITS 0x0f 31 #define MASK20BITS 0xfffff 32 #define RFREG_OFFSET_MASK 0xfffff 33 34 #define MASKBYTE0 0xff 35 #define MASKBYTE1 0xff00 36 #define MASKBYTE2 0xff0000 37 #define MASKBYTE3 0xff000000 38 #define MASKHWORD 0xffff0000 39 #define MASKLWORD 0x0000ffff 40 #define MASKDWORD 0xffffffff 41 #define MASK12BITS 0xfff 42 #define MASKH4BITS 0xf0000000 43 #define MASKOFDM_D 0xffc00000 44 #define MASKCCK 0x3f3f3f3f 45 46 #define MASK4BITS 0x0f 47 #define MASK20BITS 0xfffff 48 #define RFREG_OFFSET_MASK 0xfffff 49 50 #define RF_CHANGE_BY_INIT 0 51 #define RF_CHANGE_BY_IPS BIT(28) 52 #define RF_CHANGE_BY_PS BIT(29) 53 #define RF_CHANGE_BY_HW BIT(30) 54 #define RF_CHANGE_BY_SW BIT(31) 55 56 #define IQK_ADDA_REG_NUM 16 57 #define IQK_MAC_REG_NUM 4 58 #define IQK_THRESHOLD 8 59 60 #define MAX_KEY_LEN 61 61 #define KEY_BUF_SIZE 5 62 63 /* QoS related. */ 64 /*aci: 0x00 Best Effort*/ 65 /*aci: 0x01 Background*/ 66 /*aci: 0x10 Video*/ 67 /*aci: 0x11 Voice*/ 68 /*Max: define total number.*/ 69 #define AC0_BE 0 70 #define AC1_BK 1 71 #define AC2_VI 2 72 #define AC3_VO 3 73 #define AC_MAX 4 74 #define QOS_QUEUE_NUM 4 75 #define RTL_MAC80211_NUM_QUEUE 5 76 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 77 #define RTL_USB_MAX_RX_COUNT 100 78 #define QBSS_LOAD_SIZE 5 79 #define MAX_WMMELE_LENGTH 64 80 #define ASPM_L1_LATENCY 7 81 82 #define TOTAL_CAM_ENTRY 32 83 84 /*slot time for 11g. */ 85 #define RTL_SLOT_TIME_9 9 86 #define RTL_SLOT_TIME_20 20 87 88 /*related to tcp/ip. */ 89 #define SNAP_SIZE 6 90 #define PROTOC_TYPE_SIZE 2 91 92 /*related with 802.11 frame*/ 93 #define MAC80211_3ADDR_LEN 24 94 #define MAC80211_4ADDR_LEN 30 95 96 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 97 #define CHANNEL_MAX_NUMBER_2G 14 98 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to 99 *"phy_GetChnlGroup8812A" and 100 * "Hal_ReadTxPowerInfo8812A" 101 */ 102 #define CHANNEL_MAX_NUMBER_5G_80M 7 103 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 104 #define MAX_PG_GROUP 13 105 #define CHANNEL_GROUP_MAX_2G 3 106 #define CHANNEL_GROUP_IDX_5GL 3 107 #define CHANNEL_GROUP_IDX_5GM 6 108 #define CHANNEL_GROUP_IDX_5GH 9 109 #define CHANNEL_GROUP_MAX_5G 9 110 #define CHANNEL_MAX_NUMBER_2G 14 111 #define AVG_THERMAL_NUM 8 112 #define AVG_THERMAL_NUM_88E 4 113 #define AVG_THERMAL_NUM_8723BE 4 114 #define MAX_TID_COUNT 9 115 116 /* for early mode */ 117 #define FCS_LEN 4 118 #define EM_HDR_LEN 8 119 120 enum rtl8192c_h2c_cmd { 121 H2C_AP_OFFLOAD = 0, 122 H2C_SETPWRMODE = 1, 123 H2C_JOINBSSRPT = 2, 124 H2C_RSVDPAGE = 3, 125 H2C_RSSI_REPORT = 5, 126 H2C_RA_MASK = 6, 127 H2C_MACID_PS_MODE = 7, 128 H2C_P2P_PS_OFFLOAD = 8, 129 H2C_MAC_MODE_SEL = 9, 130 H2C_PWRM = 15, 131 H2C_P2P_PS_CTW_CMD = 24, 132 MAX_H2CCMD 133 }; 134 135 enum { 136 H2C_BT_PORT_ID = 0x71, 137 }; 138 139 enum rtl_c2h_evt_v1 { 140 C2H_DBG = 0, 141 C2H_LB = 1, 142 C2H_TXBF = 2, 143 C2H_TX_REPORT = 3, 144 C2H_BT_INFO = 9, 145 C2H_BT_MP = 11, 146 C2H_RA_RPT = 12, 147 148 C2H_FW_SWCHNL = 0x10, 149 C2H_IQK_FINISH = 0x11, 150 151 C2H_EXT_V2 = 0xFF, 152 }; 153 154 enum rtl_c2h_evt_v2 { 155 C2H_V2_CCX_RPT = 0x0F, 156 }; 157 158 #define GET_C2H_CMD_ID(c2h) ({u8 *__c2h = c2h; __c2h[0]; }) 159 #define GET_C2H_SEQ(c2h) ({u8 *__c2h = c2h; __c2h[1]; }) 160 #define C2H_DATA_OFFSET 2 161 #define GET_C2H_DATA_PTR(c2h) ({u8 *__c2h = c2h; &__c2h[C2H_DATA_OFFSET]; }) 162 163 #define GET_TX_REPORT_SN_V1(c2h) (c2h[6]) 164 #define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0) 165 #define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F) 166 #define GET_TX_REPORT_SN_V2(c2h) (c2h[6]) 167 #define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0) 168 #define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F) 169 170 #define MAX_TX_COUNT 4 171 #define MAX_REGULATION_NUM 4 172 #define MAX_RF_PATH_NUM 4 173 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */ 174 #define MAX_2_4G_BANDWIDTH_NUM 4 175 #define MAX_5G_BANDWIDTH_NUM 4 176 #define MAX_RF_PATH 4 177 #define MAX_CHNL_GROUP_24G 6 178 #define MAX_CHNL_GROUP_5G 14 179 180 #define TX_PWR_BY_RATE_NUM_BAND 2 181 #define TX_PWR_BY_RATE_NUM_RF 4 182 #define TX_PWR_BY_RATE_NUM_SECTION 12 183 #define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */ 184 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */ 185 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */ 186 187 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 188 189 #define DEL_SW_IDX_SZ 30 190 191 /* For now, it's just for 8192ee 192 * but not OK yet, keep it 0 193 */ 194 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM 195 196 enum rf_tx_num { 197 RF_1TX = 0, 198 RF_2TX, 199 RF_MAX_TX_NUM, 200 RF_TX_NUM_NONIMPLEMENT, 201 }; 202 203 #define PACKET_NORMAL 0 204 #define PACKET_DHCP 1 205 #define PACKET_ARP 2 206 #define PACKET_EAPOL 3 207 208 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 209 #define RSVD_WOL_PATTERN_NUM 1 210 #define WKFMCAM_ADDR_NUM 6 211 #define WKFMCAM_SIZE 24 212 213 #define MAX_WOL_BIT_MASK_SIZE 16 214 /* MIN LEN keeps 13 here */ 215 #define MIN_WOL_PATTERN_SIZE 13 216 #define MAX_WOL_PATTERN_SIZE 128 217 218 #define WAKE_ON_MAGIC_PACKET BIT(0) 219 #define WAKE_ON_PATTERN_MATCH BIT(1) 220 221 #define WOL_REASON_PTK_UPDATE BIT(0) 222 #define WOL_REASON_GTK_UPDATE BIT(1) 223 #define WOL_REASON_DISASSOC BIT(2) 224 #define WOL_REASON_DEAUTH BIT(3) 225 #define WOL_REASON_AP_LOST BIT(4) 226 #define WOL_REASON_MAGIC_PKT BIT(5) 227 #define WOL_REASON_UNICAST_PKT BIT(6) 228 #define WOL_REASON_PATTERN_PKT BIT(7) 229 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 230 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 231 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 232 233 struct rtlwifi_firmware_header { 234 __le16 signature; 235 u8 category; 236 u8 function; 237 __le16 version; 238 u8 subversion; 239 u8 rsvd1; 240 u8 month; 241 u8 date; 242 u8 hour; 243 u8 minute; 244 __le16 ramcodesize; 245 __le16 rsvd2; 246 __le32 svnindex; 247 __le32 rsvd3; 248 __le32 rsvd4; 249 __le32 rsvd5; 250 }; 251 252 struct txpower_info_2g { 253 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 254 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 255 /*If only one tx, only BW20 and OFDM are used.*/ 256 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 257 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 258 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 259 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 260 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 261 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 262 }; 263 264 struct txpower_info_5g { 265 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 266 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 267 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 268 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 269 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 270 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 271 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 272 }; 273 274 enum rate_section { 275 CCK = 0, 276 OFDM, 277 HT_MCS0_MCS7, 278 HT_MCS8_MCS15, 279 VHT_1SSMCS0_1SSMCS9, 280 VHT_2SSMCS0_2SSMCS9, 281 MAX_RATE_SECTION, 282 }; 283 284 enum intf_type { 285 INTF_PCI = 0, 286 INTF_USB = 1, 287 }; 288 289 enum radio_path { 290 RF90_PATH_A = 0, 291 RF90_PATH_B = 1, 292 RF90_PATH_C = 2, 293 RF90_PATH_D = 3, 294 }; 295 296 enum radio_mask { 297 RF_MASK_A = BIT(0), 298 RF_MASK_B = BIT(1), 299 RF_MASK_C = BIT(2), 300 RF_MASK_D = BIT(3), 301 }; 302 303 enum regulation_txpwr_lmt { 304 TXPWR_LMT_FCC = 0, 305 TXPWR_LMT_MKK = 1, 306 TXPWR_LMT_ETSI = 2, 307 TXPWR_LMT_WW = 3, 308 309 TXPWR_LMT_MAX_REGULATION_NUM = 4 310 }; 311 312 enum rt_eeprom_type { 313 EEPROM_93C46, 314 EEPROM_93C56, 315 EEPROM_BOOT_EFUSE, 316 }; 317 318 enum ttl_status { 319 RTL_STATUS_INTERFACE_START = 0, 320 }; 321 322 enum hardware_type { 323 HARDWARE_TYPE_RTL8192E, 324 HARDWARE_TYPE_RTL8192U, 325 HARDWARE_TYPE_RTL8192SE, 326 HARDWARE_TYPE_RTL8192SU, 327 HARDWARE_TYPE_RTL8192CE, 328 HARDWARE_TYPE_RTL8192CU, 329 HARDWARE_TYPE_RTL8192DE, 330 HARDWARE_TYPE_RTL8192DU, 331 HARDWARE_TYPE_RTL8723AE, 332 HARDWARE_TYPE_RTL8723U, 333 HARDWARE_TYPE_RTL8188EE, 334 HARDWARE_TYPE_RTL8723BE, 335 HARDWARE_TYPE_RTL8192EE, 336 HARDWARE_TYPE_RTL8821AE, 337 HARDWARE_TYPE_RTL8812AE, 338 HARDWARE_TYPE_RTL8822BE, 339 340 /* keep it last */ 341 HARDWARE_TYPE_NUM 342 }; 343 344 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type) 345 #define IS_NEW_GENERATION_IC(rtlpriv) \ 346 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE) 347 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \ 348 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE) 349 #define IS_HARDWARE_TYPE_8812(rtlpriv) \ 350 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE) 351 #define IS_HARDWARE_TYPE_8821(rtlpriv) \ 352 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE) 353 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \ 354 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE) 355 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \ 356 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE) 357 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \ 358 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE) 359 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \ 360 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE) 361 362 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 363 ((rxmcs) == DESC_RATE1M || \ 364 (rxmcs) == DESC_RATE2M || \ 365 (rxmcs) == DESC_RATE5_5M || \ 366 (rxmcs) == DESC_RATE11M) 367 368 enum scan_operation_backup_opt { 369 SCAN_OPT_BACKUP = 0, 370 SCAN_OPT_BACKUP_BAND0 = 0, 371 SCAN_OPT_BACKUP_BAND1, 372 SCAN_OPT_RESTORE, 373 SCAN_OPT_MAX 374 }; 375 376 /*RF state.*/ 377 enum rf_pwrstate { 378 ERFON, 379 ERFSLEEP, 380 ERFOFF 381 }; 382 383 struct bb_reg_def { 384 u32 rfintfs; 385 u32 rfintfi; 386 u32 rfintfo; 387 u32 rfintfe; 388 u32 rf3wire_offset; 389 u32 rflssi_select; 390 u32 rftxgain_stage; 391 u32 rfhssi_para1; 392 u32 rfhssi_para2; 393 u32 rfsw_ctrl; 394 u32 rfagc_control1; 395 u32 rfagc_control2; 396 u32 rfrxiq_imbal; 397 u32 rfrx_afe; 398 u32 rftxiq_imbal; 399 u32 rftx_afe; 400 u32 rf_rb; /* rflssi_readback */ 401 u32 rf_rbpi; /* rflssi_readbackpi */ 402 }; 403 404 enum io_type { 405 IO_CMD_PAUSE_DM_BY_SCAN = 0, 406 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 407 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 408 IO_CMD_RESUME_DM_BY_SCAN = 2, 409 }; 410 411 enum hw_variables { 412 HW_VAR_ETHER_ADDR = 0x0, 413 HW_VAR_MULTICAST_REG = 0x1, 414 HW_VAR_BASIC_RATE = 0x2, 415 HW_VAR_BSSID = 0x3, 416 HW_VAR_MEDIA_STATUS = 0x4, 417 HW_VAR_SECURITY_CONF = 0x5, 418 HW_VAR_BEACON_INTERVAL = 0x6, 419 HW_VAR_ATIM_WINDOW = 0x7, 420 HW_VAR_LISTEN_INTERVAL = 0x8, 421 HW_VAR_CS_COUNTER = 0x9, 422 HW_VAR_DEFAULTKEY0 = 0xa, 423 HW_VAR_DEFAULTKEY1 = 0xb, 424 HW_VAR_DEFAULTKEY2 = 0xc, 425 HW_VAR_DEFAULTKEY3 = 0xd, 426 HW_VAR_SIFS = 0xe, 427 HW_VAR_R2T_SIFS = 0xf, 428 HW_VAR_DIFS = 0x10, 429 HW_VAR_EIFS = 0x11, 430 HW_VAR_SLOT_TIME = 0x12, 431 HW_VAR_ACK_PREAMBLE = 0x13, 432 HW_VAR_CW_CONFIG = 0x14, 433 HW_VAR_CW_VALUES = 0x15, 434 HW_VAR_RATE_FALLBACK_CONTROL = 0x16, 435 HW_VAR_CONTENTION_WINDOW = 0x17, 436 HW_VAR_RETRY_COUNT = 0x18, 437 HW_VAR_TR_SWITCH = 0x19, 438 HW_VAR_COMMAND = 0x1a, 439 HW_VAR_WPA_CONFIG = 0x1b, 440 HW_VAR_AMPDU_MIN_SPACE = 0x1c, 441 HW_VAR_SHORTGI_DENSITY = 0x1d, 442 HW_VAR_AMPDU_FACTOR = 0x1e, 443 HW_VAR_MCS_RATE_AVAILABLE = 0x1f, 444 HW_VAR_AC_PARAM = 0x20, 445 HW_VAR_ACM_CTRL = 0x21, 446 HW_VAR_DIS_REQ_QSIZE = 0x22, 447 HW_VAR_CCX_CHNL_LOAD = 0x23, 448 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24, 449 HW_VAR_CCX_CLM_NHM = 0x25, 450 HW_VAR_TXOPLIMIT = 0x26, 451 HW_VAR_TURBO_MODE = 0x27, 452 HW_VAR_RF_STATE = 0x28, 453 HW_VAR_RF_OFF_BY_HW = 0x29, 454 HW_VAR_BUS_SPEED = 0x2a, 455 HW_VAR_SET_DEV_POWER = 0x2b, 456 457 HW_VAR_RCR = 0x2c, 458 HW_VAR_RATR_0 = 0x2d, 459 HW_VAR_RRSR = 0x2e, 460 HW_VAR_CPU_RST = 0x2f, 461 HW_VAR_CHECK_BSSID = 0x30, 462 HW_VAR_LBK_MODE = 0x31, 463 HW_VAR_AES_11N_FIX = 0x32, 464 HW_VAR_USB_RX_AGGR = 0x33, 465 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34, 466 HW_VAR_RETRY_LIMIT = 0x35, 467 HW_VAR_INIT_TX_RATE = 0x36, 468 HW_VAR_TX_RATE_REG = 0x37, 469 HW_VAR_EFUSE_USAGE = 0x38, 470 HW_VAR_EFUSE_BYTES = 0x39, 471 HW_VAR_AUTOLOAD_STATUS = 0x3a, 472 HW_VAR_RF_2R_DISABLE = 0x3b, 473 HW_VAR_SET_RPWM = 0x3c, 474 HW_VAR_H2C_FW_PWRMODE = 0x3d, 475 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e, 476 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f, 477 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40, 478 HW_VAR_FW_PSMODE_STATUS = 0x41, 479 HW_VAR_INIT_RTS_RATE = 0x42, 480 HW_VAR_RESUME_CLK_ON = 0x43, 481 HW_VAR_FW_LPS_ACTION = 0x44, 482 HW_VAR_1X1_RECV_COMBINE = 0x45, 483 HW_VAR_STOP_SEND_BEACON = 0x46, 484 HW_VAR_TSF_TIMER = 0x47, 485 HW_VAR_IO_CMD = 0x48, 486 487 HW_VAR_RF_RECOVERY = 0x49, 488 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a, 489 HW_VAR_WF_MASK = 0x4b, 490 HW_VAR_WF_CRC = 0x4c, 491 HW_VAR_WF_IS_MAC_ADDR = 0x4d, 492 HW_VAR_H2C_FW_OFFLOAD = 0x4e, 493 HW_VAR_RESET_WFCRC = 0x4f, 494 495 HW_VAR_HANDLE_FW_C2H = 0x50, 496 HW_VAR_DL_FW_RSVD_PAGE = 0x51, 497 HW_VAR_AID = 0x52, 498 HW_VAR_HW_SEQ_ENABLE = 0x53, 499 HW_VAR_CORRECT_TSF = 0x54, 500 HW_VAR_BCN_VALID = 0x55, 501 HW_VAR_FWLPS_RF_ON = 0x56, 502 HW_VAR_DUAL_TSF_RST = 0x57, 503 HW_VAR_SWITCH_EPHY_WOWLAN = 0x58, 504 HW_VAR_INT_MIGRATION = 0x59, 505 HW_VAR_INT_AC = 0x5a, 506 HW_VAR_RF_TIMING = 0x5b, 507 508 HAL_DEF_WOWLAN = 0x5c, 509 HW_VAR_MRC = 0x5d, 510 HW_VAR_KEEP_ALIVE = 0x5e, 511 HW_VAR_NAV_UPPER = 0x5f, 512 513 HW_VAR_MGT_FILTER = 0x60, 514 HW_VAR_CTRL_FILTER = 0x61, 515 HW_VAR_DATA_FILTER = 0x62, 516 }; 517 518 enum rt_media_status { 519 RT_MEDIA_DISCONNECT = 0, 520 RT_MEDIA_CONNECT = 1 521 }; 522 523 enum rt_oem_id { 524 RT_CID_DEFAULT = 0, 525 RT_CID_8187_ALPHA0 = 1, 526 RT_CID_8187_SERCOMM_PS = 2, 527 RT_CID_8187_HW_LED = 3, 528 RT_CID_8187_NETGEAR = 4, 529 RT_CID_WHQL = 5, 530 RT_CID_819X_CAMEO = 6, 531 RT_CID_819X_RUNTOP = 7, 532 RT_CID_819X_SENAO = 8, 533 RT_CID_TOSHIBA = 9, 534 RT_CID_819X_NETCORE = 10, 535 RT_CID_NETTRONIX = 11, 536 RT_CID_DLINK = 12, 537 RT_CID_PRONET = 13, 538 RT_CID_COREGA = 14, 539 RT_CID_819X_ALPHA = 15, 540 RT_CID_819X_SITECOM = 16, 541 RT_CID_CCX = 17, 542 RT_CID_819X_LENOVO = 18, 543 RT_CID_819X_QMI = 19, 544 RT_CID_819X_EDIMAX_BELKIN = 20, 545 RT_CID_819X_SERCOMM_BELKIN = 21, 546 RT_CID_819X_CAMEO1 = 22, 547 RT_CID_819X_MSI = 23, 548 RT_CID_819X_ACER = 24, 549 RT_CID_819X_HP = 27, 550 RT_CID_819X_CLEVO = 28, 551 RT_CID_819X_ARCADYAN_BELKIN = 29, 552 RT_CID_819X_SAMSUNG = 30, 553 RT_CID_819X_WNC_COREGA = 31, 554 RT_CID_819X_FOXCOON = 32, 555 RT_CID_819X_DELL = 33, 556 RT_CID_819X_PRONETS = 34, 557 RT_CID_819X_EDIMAX_ASUS = 35, 558 RT_CID_NETGEAR = 36, 559 RT_CID_PLANEX = 37, 560 RT_CID_CC_C = 38, 561 RT_CID_LENOVO_CHINA = 40, 562 }; 563 564 enum hw_descs { 565 HW_DESC_OWN, 566 HW_DESC_RXOWN, 567 HW_DESC_TX_NEXTDESC_ADDR, 568 HW_DESC_TXBUFF_ADDR, 569 HW_DESC_RXBUFF_ADDR, 570 HW_DESC_RXPKT_LEN, 571 HW_DESC_RXERO, 572 HW_DESC_RX_PREPARE, 573 }; 574 575 enum prime_sc { 576 PRIME_CHNL_OFFSET_DONT_CARE = 0, 577 PRIME_CHNL_OFFSET_LOWER = 1, 578 PRIME_CHNL_OFFSET_UPPER = 2, 579 }; 580 581 enum rf_type { 582 RF_1T1R = 0, 583 RF_1T2R = 1, 584 RF_2T2R = 2, 585 RF_2T2R_GREEN = 3, 586 RF_2T3R = 4, 587 RF_2T4R = 5, 588 RF_3T3R = 6, 589 RF_3T4R = 7, 590 RF_4T4R = 8, 591 }; 592 593 enum ht_channel_width { 594 HT_CHANNEL_WIDTH_20 = 0, 595 HT_CHANNEL_WIDTH_20_40 = 1, 596 HT_CHANNEL_WIDTH_80 = 2, 597 HT_CHANNEL_WIDTH_MAX, 598 }; 599 600 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 601 * Cipher Suites Encryption Algorithms 602 */ 603 enum rt_enc_alg { 604 NO_ENCRYPTION = 0, 605 WEP40_ENCRYPTION = 1, 606 TKIP_ENCRYPTION = 2, 607 RSERVED_ENCRYPTION = 3, 608 AESCCMP_ENCRYPTION = 4, 609 WEP104_ENCRYPTION = 5, 610 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 611 }; 612 613 enum rtl_hal_state { 614 _HAL_STATE_STOP = 0, 615 _HAL_STATE_START = 1, 616 }; 617 618 enum rtl_desc_rate { 619 DESC_RATE1M = 0x00, 620 DESC_RATE2M = 0x01, 621 DESC_RATE5_5M = 0x02, 622 DESC_RATE11M = 0x03, 623 624 DESC_RATE6M = 0x04, 625 DESC_RATE9M = 0x05, 626 DESC_RATE12M = 0x06, 627 DESC_RATE18M = 0x07, 628 DESC_RATE24M = 0x08, 629 DESC_RATE36M = 0x09, 630 DESC_RATE48M = 0x0a, 631 DESC_RATE54M = 0x0b, 632 633 DESC_RATEMCS0 = 0x0c, 634 DESC_RATEMCS1 = 0x0d, 635 DESC_RATEMCS2 = 0x0e, 636 DESC_RATEMCS3 = 0x0f, 637 DESC_RATEMCS4 = 0x10, 638 DESC_RATEMCS5 = 0x11, 639 DESC_RATEMCS6 = 0x12, 640 DESC_RATEMCS7 = 0x13, 641 DESC_RATEMCS8 = 0x14, 642 DESC_RATEMCS9 = 0x15, 643 DESC_RATEMCS10 = 0x16, 644 DESC_RATEMCS11 = 0x17, 645 DESC_RATEMCS12 = 0x18, 646 DESC_RATEMCS13 = 0x19, 647 DESC_RATEMCS14 = 0x1a, 648 DESC_RATEMCS15 = 0x1b, 649 DESC_RATEMCS15_SG = 0x1c, 650 DESC_RATEMCS32 = 0x20, 651 652 DESC_RATEVHT1SS_MCS0 = 0x2c, 653 DESC_RATEVHT1SS_MCS1 = 0x2d, 654 DESC_RATEVHT1SS_MCS2 = 0x2e, 655 DESC_RATEVHT1SS_MCS3 = 0x2f, 656 DESC_RATEVHT1SS_MCS4 = 0x30, 657 DESC_RATEVHT1SS_MCS5 = 0x31, 658 DESC_RATEVHT1SS_MCS6 = 0x32, 659 DESC_RATEVHT1SS_MCS7 = 0x33, 660 DESC_RATEVHT1SS_MCS8 = 0x34, 661 DESC_RATEVHT1SS_MCS9 = 0x35, 662 DESC_RATEVHT2SS_MCS0 = 0x36, 663 DESC_RATEVHT2SS_MCS1 = 0x37, 664 DESC_RATEVHT2SS_MCS2 = 0x38, 665 DESC_RATEVHT2SS_MCS3 = 0x39, 666 DESC_RATEVHT2SS_MCS4 = 0x3a, 667 DESC_RATEVHT2SS_MCS5 = 0x3b, 668 DESC_RATEVHT2SS_MCS6 = 0x3c, 669 DESC_RATEVHT2SS_MCS7 = 0x3d, 670 DESC_RATEVHT2SS_MCS8 = 0x3e, 671 DESC_RATEVHT2SS_MCS9 = 0x3f, 672 }; 673 674 enum rtl_var_map { 675 /*reg map */ 676 SYS_ISO_CTRL = 0, 677 SYS_FUNC_EN, 678 SYS_CLK, 679 MAC_RCR_AM, 680 MAC_RCR_AB, 681 MAC_RCR_ACRC32, 682 MAC_RCR_ACF, 683 MAC_RCR_AAP, 684 MAC_HIMR, 685 MAC_HIMRE, 686 MAC_HSISR, 687 688 /*efuse map */ 689 EFUSE_TEST, 690 EFUSE_CTRL, 691 EFUSE_CLK, 692 EFUSE_CLK_CTRL, 693 EFUSE_PWC_EV12V, 694 EFUSE_FEN_ELDR, 695 EFUSE_LOADER_CLK_EN, 696 EFUSE_ANA8M, 697 EFUSE_HWSET_MAX_SIZE, 698 EFUSE_MAX_SECTION_MAP, 699 EFUSE_REAL_CONTENT_SIZE, 700 EFUSE_OOB_PROTECT_BYTES_LEN, 701 EFUSE_ACCESS, 702 703 /*CAM map */ 704 RWCAM, 705 WCAMI, 706 RCAMO, 707 CAMDBG, 708 SECR, 709 SEC_CAM_NONE, 710 SEC_CAM_WEP40, 711 SEC_CAM_TKIP, 712 SEC_CAM_AES, 713 SEC_CAM_WEP104, 714 715 /*IMR map */ 716 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 717 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 718 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 719 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 720 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 721 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 722 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 723 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 724 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 725 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 726 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 727 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 728 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 729 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 730 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 731 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 732 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 733 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 734 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 735 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 736 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 737 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 738 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */ 739 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 740 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 741 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 742 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 743 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 744 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 745 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 746 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 747 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 748 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 749 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 750 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 751 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 752 * RTL_IMR_TBDER) 753 */ 754 RTL_IMR_C2HCMD, /*fw interrupt*/ 755 756 /*CCK Rates, TxHT = 0 */ 757 RTL_RC_CCK_RATE1M, 758 RTL_RC_CCK_RATE2M, 759 RTL_RC_CCK_RATE5_5M, 760 RTL_RC_CCK_RATE11M, 761 762 /*OFDM Rates, TxHT = 0 */ 763 RTL_RC_OFDM_RATE6M, 764 RTL_RC_OFDM_RATE9M, 765 RTL_RC_OFDM_RATE12M, 766 RTL_RC_OFDM_RATE18M, 767 RTL_RC_OFDM_RATE24M, 768 RTL_RC_OFDM_RATE36M, 769 RTL_RC_OFDM_RATE48M, 770 RTL_RC_OFDM_RATE54M, 771 772 RTL_RC_HT_RATEMCS7, 773 RTL_RC_HT_RATEMCS15, 774 775 RTL_RC_VHT_RATE_1SS_MCS7, 776 RTL_RC_VHT_RATE_1SS_MCS8, 777 RTL_RC_VHT_RATE_1SS_MCS9, 778 RTL_RC_VHT_RATE_2SS_MCS7, 779 RTL_RC_VHT_RATE_2SS_MCS8, 780 RTL_RC_VHT_RATE_2SS_MCS9, 781 782 /*keep it last */ 783 RTL_VAR_MAP_MAX, 784 }; 785 786 /*Firmware PS mode for control LPS.*/ 787 enum _fw_ps_mode { 788 FW_PS_ACTIVE_MODE = 0, 789 FW_PS_MIN_MODE = 1, 790 FW_PS_MAX_MODE = 2, 791 FW_PS_DTIM_MODE = 3, 792 FW_PS_VOIP_MODE = 4, 793 FW_PS_UAPSD_WMM_MODE = 5, 794 FW_PS_UAPSD_MODE = 6, 795 FW_PS_IBSS_MODE = 7, 796 FW_PS_WWLAN_MODE = 8, 797 FW_PS_PM_RADIO_OFF = 9, 798 FW_PS_PM_CARD_DISABLE = 10, 799 }; 800 801 enum rt_psmode { 802 EACTIVE, /*Active/Continuous access. */ 803 EMAXPS, /*Max power save mode. */ 804 EFASTPS, /*Fast power save mode. */ 805 EAUTOPS, /*Auto power save mode. */ 806 }; 807 808 /*LED related.*/ 809 enum led_ctl_mode { 810 LED_CTL_POWER_ON = 1, 811 LED_CTL_LINK = 2, 812 LED_CTL_NO_LINK = 3, 813 LED_CTL_TX = 4, 814 LED_CTL_RX = 5, 815 LED_CTL_SITE_SURVEY = 6, 816 LED_CTL_POWER_OFF = 7, 817 LED_CTL_START_TO_LINK = 8, 818 LED_CTL_START_WPS = 9, 819 LED_CTL_STOP_WPS = 10, 820 }; 821 822 enum rtl_led_pin { 823 LED_PIN_GPIO0, 824 LED_PIN_LED0, 825 LED_PIN_LED1, 826 LED_PIN_LED2 827 }; 828 829 /*QoS related.*/ 830 /*acm implementation method.*/ 831 enum acm_method { 832 EACMWAY0_SWANDHW = 0, 833 EACMWAY1_HW = 1, 834 EACMWAY2_SW = 2, 835 }; 836 837 enum macphy_mode { 838 SINGLEMAC_SINGLEPHY = 0, 839 DUALMAC_DUALPHY, 840 DUALMAC_SINGLEPHY, 841 }; 842 843 enum band_type { 844 BAND_ON_2_4G = 0, 845 BAND_ON_5G, 846 BAND_ON_BOTH, 847 BANDMAX 848 }; 849 850 /* aci/aifsn Field. 851 * Ref: WMM spec 2.2.2: WME Parameter Element, p.12. 852 */ 853 union aci_aifsn { 854 u8 char_data; 855 856 struct { 857 u8 aifsn:4; 858 u8 acm:1; 859 u8 aci:2; 860 u8 reserved:1; 861 } f; /* Field */ 862 }; 863 864 /*mlme related.*/ 865 enum wireless_mode { 866 WIRELESS_MODE_UNKNOWN = 0x00, 867 WIRELESS_MODE_A = 0x01, 868 WIRELESS_MODE_B = 0x02, 869 WIRELESS_MODE_G = 0x04, 870 WIRELESS_MODE_AUTO = 0x08, 871 WIRELESS_MODE_N_24G = 0x10, 872 WIRELESS_MODE_N_5G = 0x20, 873 WIRELESS_MODE_AC_5G = 0x40, 874 WIRELESS_MODE_AC_24G = 0x80, 875 WIRELESS_MODE_AC_ONLY = 0x100, 876 WIRELESS_MODE_MAX = 0x800 877 }; 878 879 #define IS_WIRELESS_MODE_A(wirelessmode) \ 880 (wirelessmode == WIRELESS_MODE_A) 881 #define IS_WIRELESS_MODE_B(wirelessmode) \ 882 (wirelessmode == WIRELESS_MODE_B) 883 #define IS_WIRELESS_MODE_G(wirelessmode) \ 884 (wirelessmode == WIRELESS_MODE_G) 885 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 886 (wirelessmode == WIRELESS_MODE_N_24G) 887 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 888 (wirelessmode == WIRELESS_MODE_N_5G) 889 890 enum ratr_table_mode { 891 RATR_INX_WIRELESS_NGB = 0, 892 RATR_INX_WIRELESS_NG = 1, 893 RATR_INX_WIRELESS_NB = 2, 894 RATR_INX_WIRELESS_N = 3, 895 RATR_INX_WIRELESS_GB = 4, 896 RATR_INX_WIRELESS_G = 5, 897 RATR_INX_WIRELESS_B = 6, 898 RATR_INX_WIRELESS_MC = 7, 899 RATR_INX_WIRELESS_A = 8, 900 RATR_INX_WIRELESS_AC_5N = 8, 901 RATR_INX_WIRELESS_AC_24N = 9, 902 }; 903 904 enum ratr_table_mode_new { 905 RATEID_IDX_BGN_40M_2SS = 0, 906 RATEID_IDX_BGN_40M_1SS = 1, 907 RATEID_IDX_BGN_20M_2SS_BN = 2, 908 RATEID_IDX_BGN_20M_1SS_BN = 3, 909 RATEID_IDX_GN_N2SS = 4, 910 RATEID_IDX_GN_N1SS = 5, 911 RATEID_IDX_BG = 6, 912 RATEID_IDX_G = 7, 913 RATEID_IDX_B = 8, 914 RATEID_IDX_VHT_2SS = 9, 915 RATEID_IDX_VHT_1SS = 10, 916 RATEID_IDX_MIX1 = 11, 917 RATEID_IDX_MIX2 = 12, 918 RATEID_IDX_VHT_3SS = 13, 919 RATEID_IDX_BGN_3SS = 14, 920 }; 921 922 enum rtl_link_state { 923 MAC80211_NOLINK = 0, 924 MAC80211_LINKING = 1, 925 MAC80211_LINKED = 2, 926 MAC80211_LINKED_SCANNING = 3, 927 }; 928 929 enum act_category { 930 ACT_CAT_QOS = 1, 931 ACT_CAT_DLS = 2, 932 ACT_CAT_BA = 3, 933 ACT_CAT_HT = 7, 934 ACT_CAT_WMM = 17, 935 }; 936 937 enum ba_action { 938 ACT_ADDBAREQ = 0, 939 ACT_ADDBARSP = 1, 940 ACT_DELBA = 2, 941 }; 942 943 enum rt_polarity_ctl { 944 RT_POLARITY_LOW_ACT = 0, 945 RT_POLARITY_HIGH_ACT = 1, 946 }; 947 948 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 949 enum fw_wow_reason_v2 { 950 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 951 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 952 FW_WOW_V2_DISASSOC_EVENT = 0x04, 953 FW_WOW_V2_DEAUTH_EVENT = 0x08, 954 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 955 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 956 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 957 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 958 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 959 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 960 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 961 FW_WOW_V2_REASON_MAX = 0xff, 962 }; 963 964 enum wolpattern_type { 965 UNICAST_PATTERN = 0, 966 MULTICAST_PATTERN = 1, 967 BROADCAST_PATTERN = 2, 968 DONT_CARE_DA = 3, 969 UNKNOWN_TYPE = 4, 970 }; 971 972 enum package_type { 973 PACKAGE_DEFAULT, 974 PACKAGE_QFN68, 975 PACKAGE_TFBGA90, 976 PACKAGE_TFBGA80, 977 PACKAGE_TFBGA79 978 }; 979 980 enum rtl_spec_ver { 981 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */ 982 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */ 983 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */ 984 }; 985 986 enum dm_info_query { 987 DM_INFO_FA_OFDM, 988 DM_INFO_FA_CCK, 989 DM_INFO_FA_TOTAL, 990 DM_INFO_CCA_OFDM, 991 DM_INFO_CCA_CCK, 992 DM_INFO_CCA_ALL, 993 DM_INFO_CRC32_OK_VHT, 994 DM_INFO_CRC32_OK_HT, 995 DM_INFO_CRC32_OK_LEGACY, 996 DM_INFO_CRC32_OK_CCK, 997 DM_INFO_CRC32_ERROR_VHT, 998 DM_INFO_CRC32_ERROR_HT, 999 DM_INFO_CRC32_ERROR_LEGACY, 1000 DM_INFO_CRC32_ERROR_CCK, 1001 DM_INFO_EDCCA_FLAG, 1002 DM_INFO_OFDM_ENABLE, 1003 DM_INFO_CCK_ENABLE, 1004 DM_INFO_CRC32_OK_HT_AGG, 1005 DM_INFO_CRC32_ERROR_HT_AGG, 1006 DM_INFO_DBG_PORT_0, 1007 DM_INFO_CURR_IGI, 1008 DM_INFO_RSSI_MIN, 1009 DM_INFO_RSSI_MAX, 1010 DM_INFO_CLM_RATIO, 1011 DM_INFO_NHM_RATIO, 1012 DM_INFO_IQK_ALL, 1013 DM_INFO_IQK_OK, 1014 DM_INFO_IQK_NG, 1015 DM_INFO_SIZE, 1016 }; 1017 1018 enum rx_packet_type { 1019 NORMAL_RX, 1020 TX_REPORT1, 1021 TX_REPORT2, 1022 HIS_REPORT, 1023 C2H_PACKET, 1024 }; 1025 1026 struct rtlwifi_tx_info { 1027 int sn; 1028 unsigned long send_time; 1029 }; 1030 1031 static inline struct rtlwifi_tx_info *rtl_tx_skb_cb_info(struct sk_buff *skb) 1032 { 1033 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1034 1035 BUILD_BUG_ON(sizeof(struct rtlwifi_tx_info) > 1036 sizeof(info->status.status_driver_data)); 1037 1038 return (struct rtlwifi_tx_info *)(info->status.status_driver_data); 1039 } 1040 1041 struct octet_string { 1042 u8 *octet; 1043 u16 length; 1044 }; 1045 1046 struct rtl_hdr_3addr { 1047 __le16 frame_ctl; 1048 __le16 duration_id; 1049 u8 addr1[ETH_ALEN]; 1050 u8 addr2[ETH_ALEN]; 1051 u8 addr3[ETH_ALEN]; 1052 __le16 seq_ctl; 1053 u8 payload[0]; 1054 } __packed; 1055 1056 struct rtl_info_element { 1057 u8 id; 1058 u8 len; 1059 u8 data[0]; 1060 } __packed; 1061 1062 struct rtl_probe_rsp { 1063 struct rtl_hdr_3addr header; 1064 u32 time_stamp[2]; 1065 __le16 beacon_interval; 1066 __le16 capability; 1067 /*SSID, supported rates, FH params, DS params, 1068 * CF params, IBSS params, TIM (if beacon), RSN 1069 */ 1070 struct rtl_info_element info_element[0]; 1071 } __packed; 1072 1073 /*LED related.*/ 1074 /*ledpin Identify how to implement this SW led.*/ 1075 struct rtl_led { 1076 void *hw; 1077 enum rtl_led_pin ledpin; 1078 bool ledon; 1079 }; 1080 1081 struct rtl_led_ctl { 1082 bool led_opendrain; 1083 struct rtl_led sw_led0; 1084 struct rtl_led sw_led1; 1085 }; 1086 1087 struct rtl_qos_parameters { 1088 __le16 cw_min; 1089 __le16 cw_max; 1090 u8 aifs; 1091 u8 flag; 1092 __le16 tx_op; 1093 } __packed; 1094 1095 struct rt_smooth_data { 1096 u32 elements[100]; /*array to store values */ 1097 u32 index; /*index to current array to store */ 1098 u32 total_num; /*num of valid elements */ 1099 u32 total_val; /*sum of valid elements */ 1100 }; 1101 1102 struct false_alarm_statistics { 1103 u32 cnt_parity_fail; 1104 u32 cnt_rate_illegal; 1105 u32 cnt_crc8_fail; 1106 u32 cnt_mcs_fail; 1107 u32 cnt_fast_fsync_fail; 1108 u32 cnt_sb_search_fail; 1109 u32 cnt_ofdm_fail; 1110 u32 cnt_cck_fail; 1111 u32 cnt_all; 1112 u32 cnt_ofdm_cca; 1113 u32 cnt_cck_cca; 1114 u32 cnt_cca_all; 1115 u32 cnt_bw_usc; 1116 u32 cnt_bw_lsc; 1117 }; 1118 1119 struct init_gain { 1120 u8 xaagccore1; 1121 u8 xbagccore1; 1122 u8 xcagccore1; 1123 u8 xdagccore1; 1124 u8 cca; 1125 1126 }; 1127 1128 struct wireless_stats { 1129 u64 txbytesunicast; 1130 u64 txbytesmulticast; 1131 u64 txbytesbroadcast; 1132 u64 rxbytesunicast; 1133 1134 u64 txbytesunicast_inperiod; 1135 u64 rxbytesunicast_inperiod; 1136 u32 txbytesunicast_inperiod_tp; 1137 u32 rxbytesunicast_inperiod_tp; 1138 u64 txbytesunicast_last; 1139 u64 rxbytesunicast_last; 1140 1141 long rx_snr_db[4]; 1142 /*Correct smoothed ss in Dbm, only used 1143 * in driver to report real power now. 1144 */ 1145 long recv_signal_power; 1146 long signal_quality; 1147 long last_sigstrength_inpercent; 1148 1149 u32 rssi_calculate_cnt; 1150 u32 pwdb_all_cnt; 1151 1152 /* Transformed, in dbm. Beautified signal 1153 * strength for UI, not correct. 1154 */ 1155 long signal_strength; 1156 1157 u8 rx_rssi_percentage[4]; 1158 u8 rx_evm_dbm[4]; 1159 u8 rx_evm_percentage[2]; 1160 1161 u16 rx_cfo_short[4]; 1162 u16 rx_cfo_tail[4]; 1163 1164 struct rt_smooth_data ui_rssi; 1165 struct rt_smooth_data ui_link_quality; 1166 }; 1167 1168 struct rate_adaptive { 1169 u8 rate_adaptive_disabled; 1170 u8 ratr_state; 1171 u16 reserve; 1172 1173 u32 high_rssi_thresh_for_ra; 1174 u32 high2low_rssi_thresh_for_ra; 1175 u8 low2high_rssi_thresh_for_ra40m; 1176 u32 low_rssi_thresh_for_ra40m; 1177 u8 low2high_rssi_thresh_for_ra20m; 1178 u32 low_rssi_thresh_for_ra20m; 1179 u32 upper_rssi_threshold_ratr; 1180 u32 middleupper_rssi_threshold_ratr; 1181 u32 middle_rssi_threshold_ratr; 1182 u32 middlelow_rssi_threshold_ratr; 1183 u32 low_rssi_threshold_ratr; 1184 u32 ultralow_rssi_threshold_ratr; 1185 u32 low_rssi_threshold_ratr_40m; 1186 u32 low_rssi_threshold_ratr_20m; 1187 u8 ping_rssi_enable; 1188 u32 ping_rssi_ratr; 1189 u32 ping_rssi_thresh_for_ra; 1190 u32 last_ratr; 1191 u8 pre_ratr_state; 1192 u8 ldpc_thres; 1193 bool use_ldpc; 1194 bool lower_rts_rate; 1195 bool is_special_data; 1196 }; 1197 1198 struct regd_pair_mapping { 1199 u16 reg_dmnenum; 1200 u16 reg_5ghz_ctl; 1201 u16 reg_2ghz_ctl; 1202 }; 1203 1204 struct dynamic_primary_cca { 1205 u8 pricca_flag; 1206 u8 intf_flag; 1207 u8 intf_type; 1208 u8 dup_rts_flag; 1209 u8 monitor_flag; 1210 u8 ch_offset; 1211 u8 mf_state; 1212 }; 1213 1214 struct rtl_regulatory { 1215 s8 alpha2[2]; 1216 u16 country_code; 1217 u16 max_power_level; 1218 u32 tp_scale; 1219 u16 current_rd; 1220 u16 current_rd_ext; 1221 int16_t power_limit; 1222 struct regd_pair_mapping *regpair; 1223 }; 1224 1225 struct rtl_rfkill { 1226 bool rfkill_state; /*0 is off, 1 is on */ 1227 }; 1228 1229 /*for P2P PS**/ 1230 #define P2P_MAX_NOA_NUM 2 1231 1232 enum p2p_role { 1233 P2P_ROLE_DISABLE = 0, 1234 P2P_ROLE_DEVICE = 1, 1235 P2P_ROLE_CLIENT = 2, 1236 P2P_ROLE_GO = 3 1237 }; 1238 1239 enum p2p_ps_state { 1240 P2P_PS_DISABLE = 0, 1241 P2P_PS_ENABLE = 1, 1242 P2P_PS_SCAN = 2, 1243 P2P_PS_SCAN_DONE = 3, 1244 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1245 }; 1246 1247 enum p2p_ps_mode { 1248 P2P_PS_NONE = 0, 1249 P2P_PS_CTWINDOW = 1, 1250 P2P_PS_NOA = 2, 1251 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1252 }; 1253 1254 struct rtl_p2p_ps_info { 1255 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1256 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1257 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1258 /* Client traffic window. A period of time in TU after TBTT. */ 1259 u8 ctwindow; 1260 u8 opp_ps; /* opportunistic power save. */ 1261 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1262 /* Count for owner, Type of client. */ 1263 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1264 /* Max duration for owner, preferred or min acceptable duration 1265 * for client. 1266 */ 1267 u32 noa_duration[P2P_MAX_NOA_NUM]; 1268 /* Length of interval for owner, preferred or max acceptable intervali 1269 * of client. 1270 */ 1271 u32 noa_interval[P2P_MAX_NOA_NUM]; 1272 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1273 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1274 }; 1275 1276 struct p2p_ps_offload_t { 1277 u8 offload_en:1; 1278 u8 role:1; /* 1: Owner, 0: Client */ 1279 u8 ctwindow_en:1; 1280 u8 noa0_en:1; 1281 u8 noa1_en:1; 1282 u8 allstasleep:1; 1283 u8 discovery:1; 1284 u8 reserved:1; 1285 }; 1286 1287 #define IQK_MATRIX_REG_NUM 8 1288 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1289 1290 struct iqk_matrix_regs { 1291 bool iqk_done; 1292 long value[1][IQK_MATRIX_REG_NUM]; 1293 }; 1294 1295 struct phy_parameters { 1296 u16 length; 1297 u32 *pdata; 1298 }; 1299 1300 enum hw_param_tab_index { 1301 PHY_REG_2T, 1302 PHY_REG_1T, 1303 PHY_REG_PG, 1304 RADIOA_2T, 1305 RADIOB_2T, 1306 RADIOA_1T, 1307 RADIOB_1T, 1308 MAC_REG, 1309 AGCTAB_2T, 1310 AGCTAB_1T, 1311 MAX_TAB 1312 }; 1313 1314 struct rtl_phy { 1315 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1316 struct init_gain initgain_backup; 1317 enum io_type current_io_type; 1318 1319 u8 rf_mode; 1320 u8 rf_type; 1321 u8 current_chan_bw; 1322 u8 set_bwmode_inprogress; 1323 u8 sw_chnl_inprogress; 1324 u8 sw_chnl_stage; 1325 u8 sw_chnl_step; 1326 u8 current_channel; 1327 u8 h2c_box_num; 1328 u8 set_io_inprogress; 1329 u8 lck_inprogress; 1330 1331 /* record for power tracking */ 1332 s32 reg_e94; 1333 s32 reg_e9c; 1334 s32 reg_ea4; 1335 s32 reg_eac; 1336 s32 reg_eb4; 1337 s32 reg_ebc; 1338 s32 reg_ec4; 1339 s32 reg_ecc; 1340 u8 rfpienable; 1341 u8 reserve_0; 1342 u16 reserve_1; 1343 u32 reg_c04, reg_c08, reg_874; 1344 u32 adda_backup[16]; 1345 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1346 u32 iqk_bb_backup[10]; 1347 bool iqk_initialized; 1348 1349 bool rfpath_rx_enable[MAX_RF_PATH]; 1350 u8 reg_837; 1351 /* Dual mac */ 1352 bool need_iqk; 1353 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1354 1355 bool rfpi_enable; 1356 bool iqk_in_progress; 1357 1358 u8 pwrgroup_cnt; 1359 u8 cck_high_power; 1360 /* this is for 88E & 8723A */ 1361 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1362 /* MAX_PG_GROUP groups of pwr diff by rates */ 1363 u32 mcs_offset[MAX_PG_GROUP][16]; 1364 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1365 [TX_PWR_BY_RATE_NUM_RF] 1366 [TX_PWR_BY_RATE_NUM_RF] 1367 [TX_PWR_BY_RATE_NUM_RATE]; 1368 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1369 [TX_PWR_BY_RATE_NUM_RF] 1370 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1371 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1372 [TX_PWR_BY_RATE_NUM_RF] 1373 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1374 u8 default_initialgain[4]; 1375 1376 /* the current Tx power level */ 1377 u8 cur_cck_txpwridx; 1378 u8 cur_ofdm24g_txpwridx; 1379 u8 cur_bw20_txpwridx; 1380 u8 cur_bw40_txpwridx; 1381 1382 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM] 1383 [MAX_2_4G_BANDWIDTH_NUM] 1384 [MAX_RATE_SECTION_NUM] 1385 [CHANNEL_MAX_NUMBER_2G] 1386 [MAX_RF_PATH_NUM]; 1387 s8 txpwr_limit_5g[MAX_REGULATION_NUM] 1388 [MAX_5G_BANDWIDTH_NUM] 1389 [MAX_RATE_SECTION_NUM] 1390 [CHANNEL_MAX_NUMBER_5G] 1391 [MAX_RF_PATH_NUM]; 1392 1393 u32 rfreg_chnlval[2]; 1394 bool apk_done; 1395 u32 reg_rf3c[2]; /* pathA / pathB */ 1396 1397 u32 backup_rf_0x1a;/*92ee*/ 1398 /* bfsync */ 1399 u8 framesync; 1400 u32 framesync_c34; 1401 1402 u8 num_total_rfpath; 1403 struct phy_parameters hwparam_tables[MAX_TAB]; 1404 u16 rf_pathmap; 1405 1406 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1407 enum rt_polarity_ctl polarity_ctl; 1408 }; 1409 1410 #define MAX_TID_COUNT 9 1411 #define RTL_AGG_STOP 0 1412 #define RTL_AGG_PROGRESS 1 1413 #define RTL_AGG_START 2 1414 #define RTL_AGG_OPERATIONAL 3 1415 #define RTL_AGG_OFF 0 1416 #define RTL_AGG_ON 1 1417 #define RTL_RX_AGG_START 1 1418 #define RTL_RX_AGG_STOP 0 1419 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1420 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1421 1422 struct rtl_ht_agg { 1423 u16 txq_id; 1424 u16 wait_for_ba; 1425 u16 start_idx; 1426 u64 bitmap; 1427 u32 rate_n_flags; 1428 u8 agg_state; 1429 u8 rx_agg_state; 1430 }; 1431 1432 struct rssi_sta { 1433 long undec_sm_pwdb; 1434 long undec_sm_cck; 1435 }; 1436 1437 struct rtl_tid_data { 1438 struct rtl_ht_agg agg; 1439 }; 1440 1441 struct rtl_sta_info { 1442 struct list_head list; 1443 struct rtl_tid_data tids[MAX_TID_COUNT]; 1444 /* just used for ap adhoc or mesh*/ 1445 struct rssi_sta rssi_stat; 1446 u8 rssi_level; 1447 u16 wireless_mode; 1448 u8 ratr_index; 1449 u8 mimo_ps; 1450 u8 mac_addr[ETH_ALEN]; 1451 } __packed; 1452 1453 struct rtl_priv; 1454 struct rtl_io { 1455 struct device *dev; 1456 struct mutex bb_mutex; 1457 1458 /*PCI MEM map */ 1459 unsigned long pci_mem_end; /*shared mem end */ 1460 unsigned long pci_mem_start; /*shared mem start */ 1461 1462 /*PCI IO map */ 1463 unsigned long pci_base_addr; /*device I/O address */ 1464 1465 void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val); 1466 void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val); 1467 void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val); 1468 void (*writen_sync)(struct rtl_priv *rtlpriv, u32 addr, void *buf, 1469 u16 len); 1470 1471 u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr); 1472 u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr); 1473 u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr); 1474 1475 }; 1476 1477 struct rtl_mac { 1478 u8 mac_addr[ETH_ALEN]; 1479 u8 mac80211_registered; 1480 u8 beacon_enabled; 1481 1482 u32 tx_ss_num; 1483 u32 rx_ss_num; 1484 1485 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1486 struct ieee80211_hw *hw; 1487 struct ieee80211_vif *vif; 1488 enum nl80211_iftype opmode; 1489 1490 /*Probe Beacon management */ 1491 struct rtl_tid_data tids[MAX_TID_COUNT]; 1492 enum rtl_link_state link_state; 1493 1494 int n_channels; 1495 int n_bitrates; 1496 1497 bool offchan_delay; 1498 u8 p2p; /*using p2p role*/ 1499 bool p2p_in_use; 1500 1501 /*filters */ 1502 u32 rx_conf; 1503 u16 rx_mgt_filter; 1504 u16 rx_ctrl_filter; 1505 u16 rx_data_filter; 1506 1507 bool act_scanning; 1508 u8 cnt_after_linked; 1509 bool skip_scan; 1510 1511 /* early mode */ 1512 /* skb wait queue */ 1513 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1514 1515 u8 ht_stbc_cap; 1516 u8 ht_cur_stbc; 1517 1518 /*vht support*/ 1519 u8 vht_enable; 1520 u8 bw_80; 1521 u8 vht_cur_ldpc; 1522 u8 vht_cur_stbc; 1523 u8 vht_stbc_cap; 1524 u8 vht_ldpc_cap; 1525 1526 /*RDG*/ 1527 bool rdg_en; 1528 1529 /*AP*/ 1530 u8 bssid[ETH_ALEN] __aligned(2); 1531 u32 vendor; 1532 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1533 u32 basic_rates; /* b/g rates */ 1534 u8 ht_enable; 1535 u8 sgi_40; 1536 u8 sgi_20; 1537 u8 bw_40; 1538 u16 mode; /* wireless mode */ 1539 u8 slot_time; 1540 u8 short_preamble; 1541 u8 use_cts_protect; 1542 u8 cur_40_prime_sc; 1543 u8 cur_40_prime_sc_bk; 1544 u8 cur_80_prime_sc; 1545 u64 tsf; 1546 u8 retry_short; 1547 u8 retry_long; 1548 u16 assoc_id; 1549 bool hiddenssid; 1550 1551 /*IBSS*/ 1552 int beacon_interval; 1553 1554 /*AMPDU*/ 1555 u8 min_space_cfg; /*For Min spacing configurations */ 1556 u8 max_mss_density; 1557 u8 current_ampdu_factor; 1558 u8 current_ampdu_density; 1559 1560 /*QOS & EDCA */ 1561 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1562 struct rtl_qos_parameters ac[AC_MAX]; 1563 1564 /* counters */ 1565 u64 last_txok_cnt; 1566 u64 last_rxok_cnt; 1567 u32 last_bt_edca_ul; 1568 u32 last_bt_edca_dl; 1569 }; 1570 1571 struct btdm_8723 { 1572 bool all_off; 1573 bool agc_table_en; 1574 bool adc_back_off_on; 1575 bool b2_ant_hid_en; 1576 bool low_penalty_rate_adaptive; 1577 bool rf_rx_lpf_shrink; 1578 bool reject_aggre_pkt; 1579 bool tra_tdma_on; 1580 u8 tra_tdma_nav; 1581 u8 tra_tdma_ant; 1582 bool tdma_on; 1583 u8 tdma_ant; 1584 u8 tdma_nav; 1585 u8 tdma_dac_swing; 1586 u8 fw_dac_swing_lvl; 1587 bool ps_tdma_on; 1588 u8 ps_tdma_byte[5]; 1589 bool pta_on; 1590 u32 val_0x6c0; 1591 u32 val_0x6c8; 1592 u32 val_0x6cc; 1593 bool sw_dac_swing_on; 1594 u32 sw_dac_swing_lvl; 1595 u32 wlan_act_hi; 1596 u32 wlan_act_lo; 1597 u32 bt_retry_index; 1598 bool dec_bt_pwr; 1599 bool ignore_wlan_act; 1600 }; 1601 1602 struct bt_coexist_8723 { 1603 u32 high_priority_tx; 1604 u32 high_priority_rx; 1605 u32 low_priority_tx; 1606 u32 low_priority_rx; 1607 u8 c2h_bt_info; 1608 bool c2h_bt_info_req_sent; 1609 bool c2h_bt_inquiry_page; 1610 u32 bt_inq_page_start_time; 1611 u8 bt_retry_cnt; 1612 u8 c2h_bt_info_original; 1613 u8 bt_inquiry_page_cnt; 1614 struct btdm_8723 btdm; 1615 }; 1616 1617 struct rtl_hal { 1618 struct ieee80211_hw *hw; 1619 bool driver_is_goingto_unload; 1620 bool up_first_time; 1621 bool first_init; 1622 bool being_init_adapter; 1623 bool bbrf_ready; 1624 bool mac_func_enable; 1625 bool pre_edcca_enable; 1626 struct bt_coexist_8723 hal_coex_8723; 1627 1628 enum intf_type interface; 1629 u16 hw_type; /*92c or 92d or 92s and so on */ 1630 u8 ic_class; 1631 u8 oem_id; 1632 u32 version; /*version of chip */ 1633 u8 state; /*stop 0, start 1 */ 1634 u8 board_type; 1635 u8 package_type; 1636 u8 external_pa; 1637 1638 u8 pa_mode; 1639 u8 pa_type_2g; 1640 u8 pa_type_5g; 1641 u8 lna_type_2g; 1642 u8 lna_type_5g; 1643 u8 external_pa_2g; 1644 u8 external_lna_2g; 1645 u8 external_pa_5g; 1646 u8 external_lna_5g; 1647 u8 type_glna; 1648 u8 type_gpa; 1649 u8 type_alna; 1650 u8 type_apa; 1651 u8 rfe_type; 1652 1653 /*firmware */ 1654 u32 fwsize; 1655 u8 *pfirmware; 1656 u16 fw_version; 1657 u16 fw_subversion; 1658 bool h2c_setinprogress; 1659 u8 last_hmeboxnum; 1660 bool fw_ready; 1661 /*Reserve page start offset except beacon in TxQ. */ 1662 u8 fw_rsvdpage_startoffset; 1663 u8 h2c_txcmd_seq; 1664 u8 current_ra_rate; 1665 1666 /* FW Cmd IO related */ 1667 u16 fwcmd_iomap; 1668 u32 fwcmd_ioparam; 1669 bool set_fwcmd_inprogress; 1670 u8 current_fwcmd_io; 1671 1672 struct p2p_ps_offload_t p2p_ps_offload; 1673 bool fw_clk_change_in_progress; 1674 bool allow_sw_to_change_hwclc; 1675 u8 fw_ps_state; 1676 /**/ 1677 bool driver_going2unload; 1678 1679 /*AMPDU init min space*/ 1680 u8 minspace_cfg; /*For Min spacing configurations */ 1681 1682 /* Dual mac */ 1683 enum macphy_mode macphymode; 1684 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1685 enum band_type current_bandtypebackup; 1686 enum band_type bandset; 1687 /* dual MAC 0--Mac0 1--Mac1 */ 1688 u32 interfaceindex; 1689 /* just for DualMac S3S4 */ 1690 u8 macphyctl_reg; 1691 bool earlymode_enable; 1692 u8 max_earlymode_num; 1693 /* Dual mac*/ 1694 bool during_mac0init_radiob; 1695 bool during_mac1init_radioa; 1696 bool reloadtxpowerindex; 1697 /* True if IMR or IQK have done 1698 * for 2.4G in scan progress 1699 */ 1700 bool load_imrandiqk_setting_for2g; 1701 1702 bool disable_amsdu_8k; 1703 bool master_of_dmsp; 1704 bool slave_of_dmsp; 1705 1706 u16 rx_tag;/*for 92ee*/ 1707 u8 rts_en; 1708 1709 /*for wowlan*/ 1710 bool wow_enable; 1711 bool enter_pnp_sleep; 1712 bool wake_from_pnp_sleep; 1713 bool wow_enabled; 1714 time64_t last_suspend_sec; 1715 u32 wowlan_fwsize; 1716 u8 *wowlan_firmware; 1717 1718 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1719 1720 bool real_wow_v2_enable; 1721 bool re_init_llt_table; 1722 }; 1723 1724 struct rtl_security { 1725 /*default 0 */ 1726 bool use_sw_sec; 1727 1728 bool being_setkey; 1729 bool use_defaultkey; 1730 /*Encryption Algorithm for Unicast Packet */ 1731 enum rt_enc_alg pairwise_enc_algorithm; 1732 /*Encryption Algorithm for Brocast/Multicast */ 1733 enum rt_enc_alg group_enc_algorithm; 1734 /*Cam Entry Bitmap */ 1735 u32 hwsec_cam_bitmap; 1736 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1737 /*local Key buffer, indx 0 is for 1738 * pairwise key 1-4 is for agoup key. 1739 */ 1740 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1741 u8 key_len[KEY_BUF_SIZE]; 1742 1743 /*The pointer of Pairwise Key, 1744 * it always points to KeyBuf[4] 1745 */ 1746 u8 *pairwise_key; 1747 }; 1748 1749 #define ASSOCIATE_ENTRY_NUM 33 1750 1751 struct fast_ant_training { 1752 u8 bssid[6]; 1753 u8 antsel_rx_keep_0; 1754 u8 antsel_rx_keep_1; 1755 u8 antsel_rx_keep_2; 1756 u32 ant_sum[7]; 1757 u32 ant_cnt[7]; 1758 u32 ant_ave[7]; 1759 u8 fat_state; 1760 u32 train_idx; 1761 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1762 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1763 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1764 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1765 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1766 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1767 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1768 u8 rx_idle_ant; 1769 bool becomelinked; 1770 }; 1771 1772 struct dm_phy_dbg_info { 1773 s8 rx_snrdb[4]; 1774 u64 num_qry_phy_status; 1775 u64 num_qry_phy_status_cck; 1776 u64 num_qry_phy_status_ofdm; 1777 u16 num_qry_beacon_pkt; 1778 u16 num_non_be_pkt; 1779 s32 rx_evm[4]; 1780 }; 1781 1782 struct rtl_dm { 1783 /*PHY status for Dynamic Management */ 1784 long entry_min_undec_sm_pwdb; 1785 long undec_sm_cck; 1786 long undec_sm_pwdb; /*out dm */ 1787 long entry_max_undec_sm_pwdb; 1788 s32 ofdm_pkt_cnt; 1789 bool dm_initialgain_enable; 1790 bool dynamic_txpower_enable; 1791 bool current_turbo_edca; 1792 bool is_any_nonbepkts; /*out dm */ 1793 bool is_cur_rdlstate; 1794 bool txpower_trackinginit; 1795 bool disable_framebursting; 1796 bool cck_inch14; 1797 bool txpower_tracking; 1798 bool useramask; 1799 bool rfpath_rxenable[4]; 1800 bool inform_fw_driverctrldm; 1801 bool current_mrc_switch; 1802 u8 txpowercount; 1803 u8 powerindex_backup[6]; 1804 1805 u8 thermalvalue_rxgain; 1806 u8 thermalvalue_iqk; 1807 u8 thermalvalue_lck; 1808 u8 thermalvalue; 1809 u8 last_dtp_lvl; 1810 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1811 u8 thermalvalue_avg_index; 1812 u8 tm_trigger; 1813 bool done_txpower; 1814 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1815 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1816 u8 dm_flag_tmp; 1817 u8 dm_type; 1818 u8 dm_rssi_sel; 1819 u8 txpower_track_control; 1820 bool interrupt_migration; 1821 bool disable_tx_int; 1822 s8 ofdm_index[MAX_RF_PATH]; 1823 u8 default_ofdm_index; 1824 u8 default_cck_index; 1825 s8 cck_index; 1826 s8 delta_power_index[MAX_RF_PATH]; 1827 s8 delta_power_index_last[MAX_RF_PATH]; 1828 s8 power_index_offset[MAX_RF_PATH]; 1829 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 1830 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 1831 s8 remnant_cck_idx; 1832 bool modify_txagc_flag_path_a; 1833 bool modify_txagc_flag_path_b; 1834 1835 bool one_entry_only; 1836 struct dm_phy_dbg_info dbginfo; 1837 1838 /* Dynamic ATC switch */ 1839 bool atc_status; 1840 bool large_cfo_hit; 1841 bool is_freeze; 1842 int cfo_tail[2]; 1843 int cfo_ave_pre; 1844 int crystal_cap; 1845 u8 cfo_threshold; 1846 u32 packet_count; 1847 u32 packet_count_pre; 1848 u8 tx_rate; 1849 1850 /*88e tx power tracking*/ 1851 u8 swing_idx_ofdm[MAX_RF_PATH]; 1852 u8 swing_idx_ofdm_cur; 1853 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1854 bool swing_flag_ofdm; 1855 u8 swing_idx_cck; 1856 u8 swing_idx_cck_cur; 1857 u8 swing_idx_cck_base; 1858 bool swing_flag_cck; 1859 1860 s8 swing_diff_2g; 1861 s8 swing_diff_5g; 1862 1863 /* DMSP */ 1864 bool supp_phymode_switch; 1865 1866 /* DulMac */ 1867 struct fast_ant_training fat_table; 1868 1869 u8 resp_tx_path; 1870 u8 path_sel; 1871 u32 patha_sum; 1872 u32 pathb_sum; 1873 u32 patha_cnt; 1874 u32 pathb_cnt; 1875 1876 u8 pre_channel; 1877 u8 *p_channel; 1878 u8 linked_interval; 1879 1880 u64 last_tx_ok_cnt; 1881 u64 last_rx_ok_cnt; 1882 }; 1883 1884 #define EFUSE_MAX_LOGICAL_SIZE 512 1885 1886 struct rtl_efuse { 1887 const struct rtl_efuse_ops *efuse_ops; 1888 bool autoload_ok; 1889 bool bootfromefuse; 1890 u16 max_physical_size; 1891 1892 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1893 u16 efuse_usedbytes; 1894 u8 efuse_usedpercentage; 1895 1896 u8 autoload_failflag; 1897 u8 autoload_status; 1898 1899 short epromtype; 1900 u16 eeprom_vid; 1901 u16 eeprom_did; 1902 u16 eeprom_svid; 1903 u16 eeprom_smid; 1904 u8 eeprom_oemid; 1905 u16 eeprom_channelplan; 1906 u8 eeprom_version; 1907 u8 board_type; 1908 u8 external_pa; 1909 1910 u8 dev_addr[6]; 1911 u8 wowlan_enable; 1912 u8 antenna_div_cfg; 1913 u8 antenna_div_type; 1914 1915 bool txpwr_fromeprom; 1916 u8 eeprom_crystalcap; 1917 u8 eeprom_tssi[2]; 1918 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1919 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1920 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1921 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1922 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1923 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1924 1925 u8 internal_pa_5g[2]; /* pathA / pathB */ 1926 u8 eeprom_c9; 1927 u8 eeprom_cc; 1928 1929 /*For power group */ 1930 u8 eeprom_pwrgroup[2][3]; 1931 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1932 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1933 1934 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1935 /*For HT 40MHZ pwr */ 1936 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1937 /*For HT 40MHZ pwr */ 1938 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1939 1940 /*--------------------------------------------------------* 1941 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1942 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1943 * define new arrays in Windows code. 1944 * BUT, in linux code, we use the same array for all ICs. 1945 * 1946 * The Correspondance relation between two arrays is: 1947 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1948 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1949 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1950 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1951 * 1952 * Sizes of these arrays are decided by the larger ones. 1953 */ 1954 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1955 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1956 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1957 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1958 1959 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1960 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1961 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1962 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1963 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1964 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1965 1966 u8 txpwr_safetyflag; /* Band edge enable flag */ 1967 u16 eeprom_txpowerdiff; 1968 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1969 u8 antenna_txpwdiff[3]; 1970 1971 u8 eeprom_regulatory; 1972 u8 eeprom_thermalmeter; 1973 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1974 u16 tssi_13dbm; 1975 u8 crystalcap; /* CrystalCap. */ 1976 u8 delta_iqk; 1977 u8 delta_lck; 1978 1979 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1980 bool apk_thermalmeterignore; 1981 1982 bool b1x1_recvcombine; 1983 bool b1ss_support; 1984 1985 /*channel plan */ 1986 u8 channel_plan; 1987 }; 1988 1989 struct rtl_efuse_ops { 1990 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data); 1991 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type, 1992 u16 offset, u32 *value); 1993 }; 1994 1995 struct rtl_tx_report { 1996 atomic_t sn; 1997 u16 last_sent_sn; 1998 unsigned long last_sent_time; 1999 u16 last_recv_sn; 2000 struct sk_buff_head queue; 2001 }; 2002 2003 struct rtl_ps_ctl { 2004 bool pwrdomain_protect; 2005 bool in_powersavemode; 2006 bool rfchange_inprogress; 2007 bool swrf_processing; 2008 bool hwradiooff; 2009 /* just for PCIE ASPM 2010 * If it supports ASPM, Offset[560h] = 0x40, 2011 * otherwise Offset[560h] = 0x00. 2012 */ 2013 bool support_aspm; 2014 bool support_backdoor; 2015 2016 /*for LPS */ 2017 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 2018 bool swctrl_lps; 2019 bool leisure_ps; 2020 bool fwctrl_lps; 2021 u8 fwctrl_psmode; 2022 /*For Fw control LPS mode */ 2023 u8 reg_fwctrl_lps; 2024 /*Record Fw PS mode status. */ 2025 bool fw_current_inpsmode; 2026 u8 reg_max_lps_awakeintvl; 2027 bool report_linked; 2028 bool low_power_enable;/*for 32k*/ 2029 2030 /*for IPS */ 2031 bool inactiveps; 2032 2033 u32 rfoff_reason; 2034 2035 /*RF OFF Level */ 2036 u32 cur_ps_level; 2037 u32 reg_rfps_level; 2038 2039 /*just for PCIE ASPM */ 2040 u8 const_amdpci_aspm; 2041 bool pwrdown_mode; 2042 2043 enum rf_pwrstate inactive_pwrstate; 2044 enum rf_pwrstate rfpwr_state; /*cur power state */ 2045 2046 /* for SW LPS*/ 2047 bool sw_ps_enabled; 2048 bool state; 2049 bool state_inap; 2050 bool multi_buffered; 2051 u16 nullfunc_seq; 2052 unsigned int dtim_counter; 2053 unsigned int sleep_ms; 2054 unsigned long last_sleep_jiffies; 2055 unsigned long last_awake_jiffies; 2056 unsigned long last_delaylps_stamp_jiffies; 2057 unsigned long last_dtim; 2058 unsigned long last_beacon; 2059 unsigned long last_action; 2060 unsigned long last_slept; 2061 2062 /*For P2P PS */ 2063 struct rtl_p2p_ps_info p2p_ps_info; 2064 u8 pwr_mode; 2065 u8 smart_ps; 2066 2067 /* wake up on line */ 2068 u8 wo_wlan_mode; 2069 u8 arp_offload_enable; 2070 u8 gtk_offload_enable; 2071 /* Used for WOL, indicates the reason for waking event.*/ 2072 u32 wakeup_reason; 2073 }; 2074 2075 struct rtl_stats { 2076 u8 psaddr[ETH_ALEN]; 2077 u32 mac_time[2]; 2078 s8 rssi; 2079 u8 signal; 2080 u8 noise; 2081 u8 rate; /* hw desc rate */ 2082 u8 received_channel; 2083 u8 control; 2084 u8 mask; 2085 u8 freq; 2086 u16 len; 2087 u64 tsf; 2088 u32 beacon_time; 2089 u8 nic_type; 2090 u16 length; 2091 u8 signalquality; /*in 0-100 index. */ 2092 /* Real power in dBm for this packet, 2093 * no beautification and aggregation. 2094 */ 2095 s32 recvsignalpower; 2096 s8 rxpower; /*in dBm Translate from PWdB */ 2097 u8 signalstrength; /*in 0-100 index. */ 2098 u16 hwerror:1; 2099 u16 crc:1; 2100 u16 icv:1; 2101 u16 shortpreamble:1; 2102 u16 antenna:1; 2103 u16 decrypted:1; 2104 u16 wakeup:1; 2105 u32 timestamp_low; 2106 u32 timestamp_high; 2107 bool shift; 2108 2109 u8 rx_drvinfo_size; 2110 u8 rx_bufshift; 2111 bool isampdu; 2112 bool isfirst_ampdu; 2113 bool rx_is40mhzpacket; 2114 u8 rx_packet_bw; 2115 u32 rx_pwdb_all; 2116 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2117 s8 rx_mimo_signalquality[4]; 2118 u8 rx_mimo_evm_dbm[4]; 2119 u16 cfo_short[4]; /* per-path's Cfo_short */ 2120 u16 cfo_tail[4]; 2121 2122 s8 rx_mimo_sig_qual[4]; 2123 u8 rx_pwr[4]; /* per-path's pwdb */ 2124 u8 rx_snr[4]; /* per-path's SNR */ 2125 u8 bandwidth; 2126 u8 bt_coex_pwr_adjust; 2127 bool packet_matchbssid; 2128 bool is_cck; 2129 bool is_ht; 2130 bool packet_toself; 2131 bool packet_beacon; /*for rssi */ 2132 s8 cck_adc_pwdb[4]; /*for rx path selection */ 2133 2134 bool is_vht; 2135 bool is_short_gi; 2136 u8 vht_nss; 2137 2138 u8 packet_report_type; 2139 2140 u32 macid; 2141 u32 bt_rx_rssi_percentage; 2142 u32 macid_valid_entry[2]; 2143 }; 2144 2145 struct rt_link_detect { 2146 /* count for roaming */ 2147 u32 bcn_rx_inperiod; 2148 u32 roam_times; 2149 2150 u32 num_tx_in4period[4]; 2151 u32 num_rx_in4period[4]; 2152 2153 u32 num_tx_inperiod; 2154 u32 num_rx_inperiod; 2155 2156 bool busytraffic; 2157 bool tx_busy_traffic; 2158 bool rx_busy_traffic; 2159 bool higher_busytraffic; 2160 bool higher_busyrxtraffic; 2161 2162 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2163 u32 tidtx_inperiod[MAX_TID_COUNT]; 2164 bool higher_busytxtraffic[MAX_TID_COUNT]; 2165 }; 2166 2167 struct rtl_tcb_desc { 2168 u8 packet_bw:2; 2169 u8 multicast:1; 2170 u8 broadcast:1; 2171 2172 u8 rts_stbc:1; 2173 u8 rts_enable:1; 2174 u8 cts_enable:1; 2175 u8 rts_use_shortpreamble:1; 2176 u8 rts_use_shortgi:1; 2177 u8 rts_sc:1; 2178 u8 rts_bw:1; 2179 u8 rts_rate; 2180 2181 u8 use_shortgi:1; 2182 u8 use_shortpreamble:1; 2183 u8 use_driver_rate:1; 2184 u8 disable_ratefallback:1; 2185 2186 u8 use_spe_rpt:1; 2187 2188 u8 ratr_index; 2189 u8 mac_id; 2190 u8 hw_rate; 2191 2192 u8 last_inipkt:1; 2193 u8 cmd_or_init:1; 2194 u8 queue_index; 2195 2196 /* early mode */ 2197 u8 empkt_num; 2198 /* The max value by HW */ 2199 u32 empkt_len[10]; 2200 bool tx_enable_sw_calc_duration; 2201 }; 2202 2203 struct rtl_wow_pattern { 2204 u8 type; 2205 u16 crc; 2206 u32 mask[4]; 2207 }; 2208 2209 /* struct to store contents of interrupt vectors */ 2210 struct rtl_int { 2211 u32 inta; 2212 u32 intb; 2213 u32 intc; 2214 u32 intd; 2215 }; 2216 2217 struct rtl_hal_ops { 2218 int (*init_sw_vars)(struct ieee80211_hw *hw); 2219 void (*deinit_sw_vars)(struct ieee80211_hw *hw); 2220 void (*read_chip_version)(struct ieee80211_hw *hw); 2221 void (*read_eeprom_info)(struct ieee80211_hw *hw); 2222 void (*interrupt_recognized)(struct ieee80211_hw *hw, 2223 struct rtl_int *intvec); 2224 int (*hw_init)(struct ieee80211_hw *hw); 2225 void (*hw_disable)(struct ieee80211_hw *hw); 2226 void (*hw_suspend)(struct ieee80211_hw *hw); 2227 void (*hw_resume)(struct ieee80211_hw *hw); 2228 void (*enable_interrupt)(struct ieee80211_hw *hw); 2229 void (*disable_interrupt)(struct ieee80211_hw *hw); 2230 int (*set_network_type)(struct ieee80211_hw *hw, 2231 enum nl80211_iftype type); 2232 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2233 bool check_bssid); 2234 void (*set_bw_mode)(struct ieee80211_hw *hw, 2235 enum nl80211_channel_type ch_type); 2236 u8 (*switch_channel)(struct ieee80211_hw *hw); 2237 void (*set_qos)(struct ieee80211_hw *hw, int aci); 2238 void (*set_bcn_reg)(struct ieee80211_hw *hw); 2239 void (*set_bcn_intv)(struct ieee80211_hw *hw); 2240 void (*update_interrupt_mask)(struct ieee80211_hw *hw, 2241 u32 add_msr, u32 rm_msr); 2242 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val); 2243 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val); 2244 void (*update_rate_tbl)(struct ieee80211_hw *hw, 2245 struct ieee80211_sta *sta, u8 rssi_leve, 2246 bool update_bw); 2247 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2248 u8 *desc, u8 queue_index, 2249 struct sk_buff *skb, dma_addr_t addr); 2250 void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level); 2251 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2252 u8 queue_index); 2253 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2254 u8 queue_index); 2255 void (*fill_tx_desc)(struct ieee80211_hw *hw, 2256 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2257 u8 *pbd_desc_tx, 2258 struct ieee80211_tx_info *info, 2259 struct ieee80211_sta *sta, 2260 struct sk_buff *skb, u8 hw_queue, 2261 struct rtl_tcb_desc *ptcb_desc); 2262 void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc, 2263 u32 buffer_len, bool bsspspoll); 2264 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc, 2265 bool firstseg, bool lastseg, 2266 struct sk_buff *skb); 2267 void (*fill_tx_special_desc)(struct ieee80211_hw *hw, 2268 u8 *pdesc, u8 *pbd_desc, 2269 struct sk_buff *skb, u8 hw_queue); 2270 bool (*query_rx_desc)(struct ieee80211_hw *hw, 2271 struct rtl_stats *stats, 2272 struct ieee80211_rx_status *rx_status, 2273 u8 *pdesc, struct sk_buff *skb); 2274 void (*set_channel_access)(struct ieee80211_hw *hw); 2275 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid); 2276 void (*dm_watchdog)(struct ieee80211_hw *hw); 2277 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation); 2278 bool (*set_rf_power_state)(struct ieee80211_hw *hw, 2279 enum rf_pwrstate rfpwr_state); 2280 void (*led_control)(struct ieee80211_hw *hw, 2281 enum led_ctl_mode ledaction); 2282 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2283 u8 desc_name, u8 *val); 2284 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2285 u8 desc_name); 2286 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw, 2287 u8 hw_queue, u16 index); 2288 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue); 2289 void (*enable_hw_sec)(struct ieee80211_hw *hw); 2290 void (*set_key)(struct ieee80211_hw *hw, u32 key_index, 2291 u8 *macaddr, bool is_group, u8 enc_algo, 2292 bool is_wepkey, bool clear_all); 2293 void (*init_sw_leds)(struct ieee80211_hw *hw); 2294 void (*deinit_sw_leds)(struct ieee80211_hw *hw); 2295 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2296 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2297 u32 data); 2298 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath, 2299 u32 regaddr, u32 bitmask); 2300 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath, 2301 u32 regaddr, u32 bitmask, u32 data); 2302 void (*linked_set_reg)(struct ieee80211_hw *hw); 2303 void (*chk_switch_dmdp)(struct ieee80211_hw *hw); 2304 void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw); 2305 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw); 2306 bool (*phy_rf6052_config)(struct ieee80211_hw *hw); 2307 void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw, 2308 u8 *powerlevel); 2309 void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw, 2310 u8 *ppowerlevel, u8 channel); 2311 bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw, 2312 u8 configtype); 2313 bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw, 2314 u8 configtype); 2315 void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t); 2316 void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw); 2317 void (*dm_dynamic_txpower)(struct ieee80211_hw *hw); 2318 void (*c2h_command_handle)(struct ieee80211_hw *hw); 2319 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw, 2320 bool mstate); 2321 void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw); 2322 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id, 2323 u32 cmd_len, u8 *p_cmdbuffer); 2324 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw); 2325 bool (*get_btc_status)(void); 2326 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2327 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2328 struct rtl_wow_pattern *rtl_pattern, 2329 u8 index); 2330 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2331 void (*c2h_ra_report_handler)(struct ieee80211_hw *hw, 2332 u8 *cmd_buf, u8 cmd_len); 2333 }; 2334 2335 struct rtl_intf_ops { 2336 /*com */ 2337 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2338 int (*adapter_start)(struct ieee80211_hw *hw); 2339 void (*adapter_stop)(struct ieee80211_hw *hw); 2340 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2341 struct rtl_priv **buddy_priv); 2342 2343 int (*adapter_tx)(struct ieee80211_hw *hw, 2344 struct ieee80211_sta *sta, 2345 struct sk_buff *skb, 2346 struct rtl_tcb_desc *ptcb_desc); 2347 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2348 int (*reset_trx_ring)(struct ieee80211_hw *hw); 2349 bool (*waitq_insert)(struct ieee80211_hw *hw, 2350 struct ieee80211_sta *sta, 2351 struct sk_buff *skb); 2352 2353 /*pci */ 2354 void (*disable_aspm)(struct ieee80211_hw *hw); 2355 void (*enable_aspm)(struct ieee80211_hw *hw); 2356 2357 /*usb */ 2358 }; 2359 2360 struct rtl_mod_params { 2361 /* default: 0,0 */ 2362 u64 debug_mask; 2363 /* default: 0 = using hardware encryption */ 2364 bool sw_crypto; 2365 2366 /* default: 0 = DBG_EMERG (0)*/ 2367 int debug_level; 2368 2369 /* default: 1 = using no linked power save */ 2370 bool inactiveps; 2371 2372 /* default: 1 = using linked sw power save */ 2373 bool swctrl_lps; 2374 2375 /* default: 1 = using linked fw power save */ 2376 bool fwctrl_lps; 2377 2378 /* default: 0 = not using MSI interrupts mode 2379 * submodules should set their own default value 2380 */ 2381 bool msi_support; 2382 2383 /* default: 0 = dma 32 */ 2384 bool dma64; 2385 2386 /* default: 1 = enable aspm */ 2387 int aspm_support; 2388 2389 /* default 0: 1 means disable */ 2390 bool disable_watchdog; 2391 2392 /* default 0: 1 means do not disable interrupts */ 2393 bool int_clear; 2394 2395 /* select antenna */ 2396 int ant_sel; 2397 }; 2398 2399 struct rtl_hal_usbint_cfg { 2400 /* data - rx */ 2401 u32 in_ep_num; 2402 u32 rx_urb_num; 2403 u32 rx_max_size; 2404 2405 /* op - rx */ 2406 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2407 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2408 struct sk_buff_head *); 2409 2410 /* tx */ 2411 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2412 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2413 struct sk_buff *); 2414 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2415 struct sk_buff_head *); 2416 2417 /* endpoint mapping */ 2418 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2419 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2420 }; 2421 2422 struct rtl_hal_cfg { 2423 u8 bar_id; 2424 bool write_readback; 2425 char *name; 2426 char *alt_fw_name; 2427 struct rtl_hal_ops *ops; 2428 struct rtl_mod_params *mod_params; 2429 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2430 enum rtl_spec_ver spec_ver; 2431 2432 /*this map used for some registers or vars 2433 * defined int HAL but used in MAIN 2434 */ 2435 u32 maps[RTL_VAR_MAP_MAX]; 2436 2437 }; 2438 2439 struct rtl_locks { 2440 /* mutex */ 2441 struct mutex conf_mutex; 2442 struct mutex ips_mutex; /* mutex for enter/leave IPS */ 2443 struct mutex lps_mutex; /* mutex for enter/leave LPS */ 2444 2445 /*spin lock */ 2446 spinlock_t irq_th_lock; 2447 spinlock_t h2c_lock; 2448 spinlock_t rf_ps_lock; 2449 spinlock_t rf_lock; 2450 spinlock_t waitq_lock; 2451 spinlock_t entry_list_lock; 2452 spinlock_t usb_lock; 2453 spinlock_t c2hcmd_lock; 2454 spinlock_t scan_list_lock; /* lock for the scan list */ 2455 2456 /*FW clock change */ 2457 spinlock_t fw_ps_lock; 2458 2459 /*Dual mac*/ 2460 spinlock_t cck_and_rw_pagea_lock; 2461 2462 spinlock_t iqk_lock; 2463 }; 2464 2465 struct rtl_works { 2466 struct ieee80211_hw *hw; 2467 2468 /*timer */ 2469 struct timer_list watchdog_timer; 2470 struct timer_list dualmac_easyconcurrent_retrytimer; 2471 struct timer_list fw_clockoff_timer; 2472 struct timer_list fast_antenna_training_timer; 2473 /*task */ 2474 struct tasklet_struct irq_tasklet; 2475 struct tasklet_struct irq_prepare_bcn_tasklet; 2476 2477 /*work queue */ 2478 struct workqueue_struct *rtl_wq; 2479 struct delayed_work watchdog_wq; 2480 struct delayed_work ips_nic_off_wq; 2481 struct delayed_work c2hcmd_wq; 2482 2483 /* For SW LPS */ 2484 struct delayed_work ps_work; 2485 struct delayed_work ps_rfon_wq; 2486 struct delayed_work fwevt_wq; 2487 2488 struct work_struct lps_change_work; 2489 struct work_struct fill_h2c_cmd; 2490 }; 2491 2492 struct rtl_debug { 2493 /* add for debug */ 2494 struct dentry *debugfs_dir; 2495 char debugfs_name[20]; 2496 }; 2497 2498 #define MIMO_PS_STATIC 0 2499 #define MIMO_PS_DYNAMIC 1 2500 #define MIMO_PS_NOLIMIT 3 2501 2502 struct rtl_dualmac_easy_concurrent_ctl { 2503 enum band_type currentbandtype_backfordmdp; 2504 bool close_bbandrf_for_dmsp; 2505 bool change_to_dmdp; 2506 bool change_to_dmsp; 2507 bool switch_in_process; 2508 }; 2509 2510 struct rtl_dmsp_ctl { 2511 bool activescan_for_slaveofdmsp; 2512 bool scan_for_anothermac_fordmsp; 2513 bool scan_for_itself_fordmsp; 2514 bool writedig_for_anothermacofdmsp; 2515 u32 curdigvalue_for_anothermacofdmsp; 2516 bool changecckpdstate_for_anothermacofdmsp; 2517 u8 curcckpdstate_for_anothermacofdmsp; 2518 bool changetxhighpowerlvl_for_anothermacofdmsp; 2519 u8 curtxhighlvl_for_anothermacofdmsp; 2520 long rssivalmin_for_anothermacofdmsp; 2521 }; 2522 2523 struct ps_t { 2524 u8 pre_ccastate; 2525 u8 cur_ccasate; 2526 u8 pre_rfstate; 2527 u8 cur_rfstate; 2528 u8 initialize; 2529 long rssi_val_min; 2530 }; 2531 2532 struct dig_t { 2533 u32 rssi_lowthresh; 2534 u32 rssi_highthresh; 2535 u32 fa_lowthresh; 2536 u32 fa_highthresh; 2537 long last_min_undec_pwdb_for_dm; 2538 long rssi_highpower_lowthresh; 2539 long rssi_highpower_highthresh; 2540 u32 recover_cnt; 2541 u32 pre_igvalue; 2542 u32 cur_igvalue; 2543 long rssi_val; 2544 u8 dig_enable_flag; 2545 u8 dig_ext_port_stage; 2546 u8 dig_algorithm; 2547 u8 dig_twoport_algorithm; 2548 u8 dig_dbgmode; 2549 u8 dig_slgorithm_switch; 2550 u8 cursta_cstate; 2551 u8 presta_cstate; 2552 u8 curmultista_cstate; 2553 u8 stop_dig; 2554 s8 back_val; 2555 s8 back_range_max; 2556 s8 back_range_min; 2557 u8 rx_gain_max; 2558 u8 rx_gain_min; 2559 u8 min_undec_pwdb_for_dm; 2560 u8 rssi_val_min; 2561 u8 pre_cck_cca_thres; 2562 u8 cur_cck_cca_thres; 2563 u8 pre_cck_pd_state; 2564 u8 cur_cck_pd_state; 2565 u8 pre_cck_fa_state; 2566 u8 cur_cck_fa_state; 2567 u8 pre_ccastate; 2568 u8 cur_ccasate; 2569 u8 large_fa_hit; 2570 u8 forbidden_igi; 2571 u8 dig_state; 2572 u8 dig_highpwrstate; 2573 u8 cur_sta_cstate; 2574 u8 pre_sta_cstate; 2575 u8 cur_ap_cstate; 2576 u8 pre_ap_cstate; 2577 u8 cur_pd_thstate; 2578 u8 pre_pd_thstate; 2579 u8 cur_cs_ratiostate; 2580 u8 pre_cs_ratiostate; 2581 u8 backoff_enable_flag; 2582 s8 backoffval_range_max; 2583 s8 backoffval_range_min; 2584 u8 dig_min_0; 2585 u8 dig_min_1; 2586 u8 bt30_cur_igi; 2587 bool media_connect_0; 2588 bool media_connect_1; 2589 2590 u32 antdiv_rssi_max; 2591 u32 rssi_max; 2592 }; 2593 2594 struct rtl_global_var { 2595 /* from this list we can get 2596 * other adapter's rtl_priv 2597 */ 2598 struct list_head glb_priv_list; 2599 spinlock_t glb_list_lock; 2600 }; 2601 2602 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */ 2603 2604 struct rtl_btc_info { 2605 u8 bt_type; 2606 u8 btcoexist; 2607 u8 ant_num; 2608 u8 single_ant_path; 2609 2610 u8 ap_num; 2611 bool in_4way; 2612 unsigned long in_4way_ts; 2613 }; 2614 2615 struct bt_coexist_info { 2616 struct rtl_btc_ops *btc_ops; 2617 struct rtl_btc_info btc_info; 2618 /* btc context */ 2619 void *btc_context; 2620 void *wifi_only_context; 2621 /* EEPROM BT info. */ 2622 u8 eeprom_bt_coexist; 2623 u8 eeprom_bt_type; 2624 u8 eeprom_bt_ant_num; 2625 u8 eeprom_bt_ant_isol; 2626 u8 eeprom_bt_radio_shared; 2627 2628 u8 bt_coexistence; 2629 u8 bt_ant_num; 2630 u8 bt_coexist_type; 2631 u8 bt_state; 2632 u8 bt_cur_state; /* 0:on, 1:off */ 2633 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2634 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2635 u8 bt_service; 2636 u8 bt_radio_shared_type; 2637 u8 bt_rfreg_origin_1e; 2638 u8 bt_rfreg_origin_1f; 2639 u8 bt_rssi_state; 2640 u32 ratio_tx; 2641 u32 ratio_pri; 2642 u32 bt_edca_ul; 2643 u32 bt_edca_dl; 2644 2645 bool init_set; 2646 bool bt_busy_traffic; 2647 bool bt_traffic_mode_set; 2648 bool bt_non_traffic_mode_set; 2649 2650 bool fw_coexist_all_off; 2651 bool sw_coexist_all_off; 2652 bool hw_coexist_all_off; 2653 u32 cstate; 2654 u32 previous_state; 2655 u32 cstate_h; 2656 u32 previous_state_h; 2657 2658 u8 bt_pre_rssi_state; 2659 u8 bt_pre_rssi_state1; 2660 2661 u8 reg_bt_iso; 2662 u8 reg_bt_sco; 2663 bool balance_on; 2664 u8 bt_active_zero_cnt; 2665 bool cur_bt_disabled; 2666 bool pre_bt_disabled; 2667 2668 u8 bt_profile_case; 2669 u8 bt_profile_action; 2670 bool bt_busy; 2671 bool hold_for_bt_operation; 2672 u8 lps_counter; 2673 }; 2674 2675 struct rtl_btc_ops { 2676 void (*btc_init_variables)(struct rtl_priv *rtlpriv); 2677 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv); 2678 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv); 2679 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv); 2680 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv); 2681 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv); 2682 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv); 2683 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type); 2684 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2685 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype); 2686 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv, 2687 u8 scantype); 2688 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action); 2689 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv, 2690 enum rt_media_status mstatus); 2691 void (*btc_periodical)(struct rtl_priv *rtlpriv); 2692 void (*btc_halt_notify)(struct rtl_priv *rtlpriv); 2693 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv, 2694 u8 *tmp_buf, u8 length); 2695 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv, 2696 u8 *tmp_buf, u8 length); 2697 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv); 2698 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv); 2699 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv); 2700 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2701 u8 pkt_type); 2702 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type, 2703 bool scanning); 2704 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv, 2705 u8 type, bool scanning); 2706 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv, 2707 struct seq_file *m); 2708 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len); 2709 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv); 2710 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv); 2711 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv); 2712 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg, 2713 u8 *ctrl_agg_size, u8 *agg_size); 2714 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv); 2715 }; 2716 2717 struct proxim { 2718 bool proxim_on; 2719 2720 void *proximity_priv; 2721 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2722 struct sk_buff *skb); 2723 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2724 }; 2725 2726 struct rtl_c2hcmd { 2727 struct list_head list; 2728 u8 tag; 2729 u8 len; 2730 u8 *val; 2731 }; 2732 2733 struct rtl_bssid_entry { 2734 struct list_head list; 2735 u8 bssid[ETH_ALEN]; 2736 u32 age; 2737 }; 2738 2739 struct rtl_scan_list { 2740 int num; 2741 struct list_head list; /* sort by age */ 2742 }; 2743 2744 struct rtl_priv { 2745 struct ieee80211_hw *hw; 2746 struct completion firmware_loading_complete; 2747 struct list_head list; 2748 struct rtl_priv *buddy_priv; 2749 struct rtl_global_var *glb_var; 2750 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2751 struct rtl_dmsp_ctl dmsp_ctl; 2752 struct rtl_locks locks; 2753 struct rtl_works works; 2754 struct rtl_mac mac80211; 2755 struct rtl_hal rtlhal; 2756 struct rtl_regulatory regd; 2757 struct rtl_rfkill rfkill; 2758 struct rtl_io io; 2759 struct rtl_phy phy; 2760 struct rtl_dm dm; 2761 struct rtl_security sec; 2762 struct rtl_efuse efuse; 2763 struct rtl_led_ctl ledctl; 2764 struct rtl_tx_report tx_report; 2765 struct rtl_scan_list scan_list; 2766 2767 struct rtl_ps_ctl psc; 2768 struct rate_adaptive ra; 2769 struct dynamic_primary_cca primarycca; 2770 struct wireless_stats stats; 2771 struct rt_link_detect link_info; 2772 struct false_alarm_statistics falsealm_cnt; 2773 2774 struct rtl_rate_priv *rate_priv; 2775 2776 /* sta entry list for ap adhoc or mesh */ 2777 struct list_head entry_list; 2778 2779 /* c2hcmd list for kthread level access */ 2780 struct sk_buff_head c2hcmd_queue; 2781 2782 struct rtl_debug dbg; 2783 int max_fw_size; 2784 2785 /* hal_cfg : for diff cards 2786 * intf_ops : for diff interrface usb/pcie 2787 */ 2788 struct rtl_hal_cfg *cfg; 2789 const struct rtl_intf_ops *intf_ops; 2790 2791 /* this var will be set by set_bit, 2792 * and was used to indicate status of 2793 * interface or hardware 2794 */ 2795 unsigned long status; 2796 2797 /* tables for dm */ 2798 struct dig_t dm_digtable; 2799 struct ps_t dm_pstable; 2800 2801 u32 reg_874; 2802 u32 reg_c70; 2803 u32 reg_85c; 2804 u32 reg_a74; 2805 bool reg_init; /* true if regs saved */ 2806 bool bt_operation_on; 2807 __le32 *usb_data; 2808 int usb_data_index; 2809 bool initialized; 2810 bool enter_ps; /* true when entering PS */ 2811 u8 rate_mask[5]; 2812 2813 /* intel Proximity, should be alloc mem 2814 * in intel Proximity module and can only 2815 * be used in intel Proximity mode 2816 */ 2817 struct proxim proximity; 2818 2819 /*for bt coexist use*/ 2820 struct bt_coexist_info btcoexist; 2821 2822 /* separate 92ee from other ICs, 2823 * 92ee use new trx flow. 2824 */ 2825 bool use_new_trx_flow; 2826 2827 #ifdef CONFIG_PM 2828 struct wiphy_wowlan_support wowlan; 2829 #endif 2830 /* This must be the last item so 2831 * that it points to the data allocated 2832 * beyond this structure like: 2833 * rtl_pci_priv or rtl_usb_priv 2834 */ 2835 u8 priv[0] __aligned(sizeof(void *)); 2836 }; 2837 2838 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2839 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2840 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2841 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2842 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2843 2844 /* Bluetooth Co-existence Related */ 2845 2846 enum bt_ant_num { 2847 ANT_X2 = 0, 2848 ANT_X1 = 1, 2849 }; 2850 2851 enum bt_ant_path { 2852 ANT_MAIN = 0, 2853 ANT_AUX = 1, 2854 }; 2855 2856 enum bt_co_type { 2857 BT_2WIRE = 0, 2858 BT_ISSC_3WIRE = 1, 2859 BT_ACCEL = 2, 2860 BT_CSR_BC4 = 3, 2861 BT_CSR_BC8 = 4, 2862 BT_RTL8756 = 5, 2863 BT_RTL8723A = 6, 2864 BT_RTL8821A = 7, 2865 BT_RTL8723B = 8, 2866 BT_RTL8192E = 9, 2867 BT_RTL8812A = 11, 2868 }; 2869 2870 enum bt_cur_state { 2871 BT_OFF = 0, 2872 BT_ON = 1, 2873 }; 2874 2875 enum bt_service_type { 2876 BT_SCO = 0, 2877 BT_A2DP = 1, 2878 BT_HID = 2, 2879 BT_HID_IDLE = 3, 2880 BT_SCAN = 4, 2881 BT_IDLE = 5, 2882 BT_OTHER_ACTION = 6, 2883 BT_BUSY = 7, 2884 BT_OTHERBUSY = 8, 2885 BT_PAN = 9, 2886 }; 2887 2888 enum bt_radio_shared { 2889 BT_RADIO_SHARED = 0, 2890 BT_RADIO_INDIVIDUAL = 1, 2891 }; 2892 2893 /**************************************** 2894 * mem access macro define start 2895 * Call endian free function when 2896 * 1. Read/write packet content. 2897 * 2. Before write integer to IO. 2898 * 3. After read integer from IO. 2899 ****************************************/ 2900 /* Convert little data endian to host ordering */ 2901 #define EF1BYTE(_val) \ 2902 ((u8)(_val)) 2903 #define EF2BYTE(_val) \ 2904 (le16_to_cpu(_val)) 2905 #define EF4BYTE(_val) \ 2906 (le32_to_cpu(_val)) 2907 2908 /* Read data from memory */ 2909 #define READEF1BYTE(_ptr) \ 2910 EF1BYTE(*((u8 *)(_ptr))) 2911 /* Read le16 data from memory and convert to host ordering */ 2912 #define READEF2BYTE(_ptr) \ 2913 EF2BYTE(*(_ptr)) 2914 #define READEF4BYTE(_ptr) \ 2915 EF4BYTE(*(_ptr)) 2916 2917 /* Create a bit mask 2918 * Examples: 2919 * BIT_LEN_MASK_32(0) => 0x00000000 2920 * BIT_LEN_MASK_32(1) => 0x00000001 2921 * BIT_LEN_MASK_32(2) => 0x00000003 2922 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2923 */ 2924 #define BIT_LEN_MASK_32(__bitlen) \ 2925 (0xFFFFFFFF >> (32 - (__bitlen))) 2926 #define BIT_LEN_MASK_16(__bitlen) \ 2927 (0xFFFF >> (16 - (__bitlen))) 2928 #define BIT_LEN_MASK_8(__bitlen) \ 2929 (0xFF >> (8 - (__bitlen))) 2930 2931 /* Create an offset bit mask 2932 * Examples: 2933 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2934 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2935 */ 2936 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2937 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2938 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2939 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2940 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2941 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2942 2943 /*Description: 2944 * Return 4-byte value in host byte ordering from 2945 * 4-byte pointer in little-endian system. 2946 */ 2947 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2948 (EF4BYTE(*((__le32 *)(__pstart)))) 2949 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2950 (EF2BYTE(*((__le16 *)(__pstart)))) 2951 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2952 (EF1BYTE(*((u8 *)(__pstart)))) 2953 2954 /*Description: 2955 * Translate subfield (continuous bits in little-endian) of 4-byte 2956 * value to host byte ordering. 2957 */ 2958 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2959 ( \ 2960 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2961 BIT_LEN_MASK_32(__bitlen) \ 2962 ) 2963 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2964 ( \ 2965 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2966 BIT_LEN_MASK_16(__bitlen) \ 2967 ) 2968 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2969 ( \ 2970 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2971 BIT_LEN_MASK_8(__bitlen) \ 2972 ) 2973 2974 /* Description: 2975 * Mask subfield (continuous bits in little-endian) of 4-byte value 2976 * and return the result in 4-byte value in host byte ordering. 2977 */ 2978 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2979 ( \ 2980 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2981 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2982 ) 2983 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2984 ( \ 2985 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2986 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2987 ) 2988 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2989 ( \ 2990 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2991 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2992 ) 2993 2994 /* Description: 2995 * Set subfield of little-endian 4-byte value to specified value. 2996 */ 2997 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2998 *((__le32 *)(__pstart)) = \ 2999 cpu_to_le32( \ 3000 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 3001 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 3002 ) 3003 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 3004 *((__le16 *)(__pstart)) = \ 3005 cpu_to_le16( \ 3006 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 3007 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 3008 ) 3009 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 3010 *((u8 *)(__pstart)) = EF1BYTE \ 3011 ( \ 3012 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 3013 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 3014 ) 3015 3016 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 3017 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 3018 3019 /* mem access macro define end */ 3020 3021 #define byte(x, n) ((x >> (8 * n)) & 0xff) 3022 3023 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 3024 #define RTL_WATCH_DOG_TIME 2000 3025 #define MSECS(t) msecs_to_jiffies(t) 3026 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 3027 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 3028 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 3029 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 3030 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 3031 3032 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 3033 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 3034 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 3035 /*NIC halt, re-initialize hw parameters*/ 3036 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 3037 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 3038 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 3039 /*Always enable ASPM and Clock Req in initialization.*/ 3040 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 3041 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 3042 #define RT_PS_LEVEL_ASPM BIT(7) 3043 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 3044 #define RT_RF_LPS_DISALBE_2R BIT(30) 3045 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 3046 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 3047 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 3048 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 3049 (ppsc->cur_ps_level &= (~(_ps_flg))) 3050 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 3051 (ppsc->cur_ps_level |= _ps_flg) 3052 3053 #define container_of_dwork_rtl(x, y, z) \ 3054 container_of(to_delayed_work(x), y, z) 3055 3056 #define FILL_OCTET_STRING(_os, _octet, _len) \ 3057 (_os).octet = (u8 *)(_octet); \ 3058 (_os).length = (_len); 3059 3060 #define CP_MACADDR(des, src) \ 3061 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 3062 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 3063 (des)[4] = (src)[4], (des)[5] = (src)[5]) 3064 3065 #define LDPC_HT_ENABLE_RX BIT(0) 3066 #define LDPC_HT_ENABLE_TX BIT(1) 3067 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 3068 #define LDPC_HT_CAP_TX BIT(3) 3069 3070 #define STBC_HT_ENABLE_RX BIT(0) 3071 #define STBC_HT_ENABLE_TX BIT(1) 3072 #define STBC_HT_TEST_TX_ENABLE BIT(2) 3073 #define STBC_HT_CAP_TX BIT(3) 3074 3075 #define LDPC_VHT_ENABLE_RX BIT(0) 3076 #define LDPC_VHT_ENABLE_TX BIT(1) 3077 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 3078 #define LDPC_VHT_CAP_TX BIT(3) 3079 3080 #define STBC_VHT_ENABLE_RX BIT(0) 3081 #define STBC_VHT_ENABLE_TX BIT(1) 3082 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 3083 #define STBC_VHT_CAP_TX BIT(3) 3084 3085 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G]; 3086 3087 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M]; 3088 3089 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 3090 { 3091 return rtlpriv->io.read8_sync(rtlpriv, addr); 3092 } 3093 3094 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 3095 { 3096 return rtlpriv->io.read16_sync(rtlpriv, addr); 3097 } 3098 3099 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 3100 { 3101 return rtlpriv->io.read32_sync(rtlpriv, addr); 3102 } 3103 3104 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 3105 { 3106 rtlpriv->io.write8_async(rtlpriv, addr, val8); 3107 3108 if (rtlpriv->cfg->write_readback) 3109 rtlpriv->io.read8_sync(rtlpriv, addr); 3110 } 3111 3112 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw, 3113 u32 addr, u32 val8) 3114 { 3115 struct rtl_priv *rtlpriv = rtl_priv(hw); 3116 3117 rtl_write_byte(rtlpriv, addr, (u8)val8); 3118 } 3119 3120 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 3121 { 3122 rtlpriv->io.write16_async(rtlpriv, addr, val16); 3123 3124 if (rtlpriv->cfg->write_readback) 3125 rtlpriv->io.read16_sync(rtlpriv, addr); 3126 } 3127 3128 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 3129 u32 addr, u32 val32) 3130 { 3131 rtlpriv->io.write32_async(rtlpriv, addr, val32); 3132 3133 if (rtlpriv->cfg->write_readback) 3134 rtlpriv->io.read32_sync(rtlpriv, addr); 3135 } 3136 3137 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 3138 u32 regaddr, u32 bitmask) 3139 { 3140 struct rtl_priv *rtlpriv = hw->priv; 3141 3142 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 3143 } 3144 3145 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 3146 u32 bitmask, u32 data) 3147 { 3148 struct rtl_priv *rtlpriv = hw->priv; 3149 3150 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 3151 } 3152 3153 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw, 3154 u32 regaddr, u32 data) 3155 { 3156 rtl_set_bbreg(hw, regaddr, 0xffffffff, data); 3157 } 3158 3159 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 3160 enum radio_path rfpath, u32 regaddr, 3161 u32 bitmask) 3162 { 3163 struct rtl_priv *rtlpriv = hw->priv; 3164 3165 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 3166 } 3167 3168 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 3169 enum radio_path rfpath, u32 regaddr, 3170 u32 bitmask, u32 data) 3171 { 3172 struct rtl_priv *rtlpriv = hw->priv; 3173 3174 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 3175 } 3176 3177 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 3178 { 3179 return (_HAL_STATE_STOP == rtlhal->state); 3180 } 3181 3182 static inline void set_hal_start(struct rtl_hal *rtlhal) 3183 { 3184 rtlhal->state = _HAL_STATE_START; 3185 } 3186 3187 static inline void set_hal_stop(struct rtl_hal *rtlhal) 3188 { 3189 rtlhal->state = _HAL_STATE_STOP; 3190 } 3191 3192 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 3193 { 3194 return rtlphy->rf_type; 3195 } 3196 3197 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3198 { 3199 return (struct ieee80211_hdr *)(skb->data); 3200 } 3201 3202 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3203 { 3204 return rtl_get_hdr(skb)->frame_control; 3205 } 3206 3207 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3208 { 3209 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3210 } 3211 3212 static inline u16 rtl_get_tid(struct sk_buff *skb) 3213 { 3214 return rtl_get_tid_h(rtl_get_hdr(skb)); 3215 } 3216 3217 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3218 struct ieee80211_vif *vif, 3219 const u8 *bssid) 3220 { 3221 return ieee80211_find_sta(vif, bssid); 3222 } 3223 3224 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3225 u8 *mac_addr) 3226 { 3227 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3228 3229 return ieee80211_find_sta(mac->vif, mac_addr); 3230 } 3231 3232 #endif 3233