1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_WIFI_H__ 27 #define __RTL_WIFI_H__ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sched.h> 32 #include <linux/firmware.h> 33 #include <linux/etherdevice.h> 34 #include <linux/vmalloc.h> 35 #include <linux/usb.h> 36 #include <net/mac80211.h> 37 #include <linux/completion.h> 38 #include "debug.h" 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKHWORD 0xffff0000 45 #define MASKLWORD 0x0000ffff 46 #define MASKDWORD 0xffffffff 47 #define MASK12BITS 0xfff 48 #define MASKH4BITS 0xf0000000 49 #define MASKOFDM_D 0xffc00000 50 #define MASKCCK 0x3f3f3f3f 51 52 #define MASK4BITS 0x0f 53 #define MASK20BITS 0xfffff 54 #define RFREG_OFFSET_MASK 0xfffff 55 56 #define MASKBYTE0 0xff 57 #define MASKBYTE1 0xff00 58 #define MASKBYTE2 0xff0000 59 #define MASKBYTE3 0xff000000 60 #define MASKHWORD 0xffff0000 61 #define MASKLWORD 0x0000ffff 62 #define MASKDWORD 0xffffffff 63 #define MASK12BITS 0xfff 64 #define MASKH4BITS 0xf0000000 65 #define MASKOFDM_D 0xffc00000 66 #define MASKCCK 0x3f3f3f3f 67 68 #define MASK4BITS 0x0f 69 #define MASK20BITS 0xfffff 70 #define RFREG_OFFSET_MASK 0xfffff 71 72 #define RF_CHANGE_BY_INIT 0 73 #define RF_CHANGE_BY_IPS BIT(28) 74 #define RF_CHANGE_BY_PS BIT(29) 75 #define RF_CHANGE_BY_HW BIT(30) 76 #define RF_CHANGE_BY_SW BIT(31) 77 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_MAC_REG_NUM 4 80 #define IQK_THRESHOLD 8 81 82 #define MAX_KEY_LEN 61 83 #define KEY_BUF_SIZE 5 84 85 /* QoS related. */ 86 /*aci: 0x00 Best Effort*/ 87 /*aci: 0x01 Background*/ 88 /*aci: 0x10 Video*/ 89 /*aci: 0x11 Voice*/ 90 /*Max: define total number.*/ 91 #define AC0_BE 0 92 #define AC1_BK 1 93 #define AC2_VI 2 94 #define AC3_VO 3 95 #define AC_MAX 4 96 #define QOS_QUEUE_NUM 4 97 #define RTL_MAC80211_NUM_QUEUE 5 98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99 #define RTL_USB_MAX_RX_COUNT 100 100 #define QBSS_LOAD_SIZE 5 101 #define MAX_WMMELE_LENGTH 64 102 103 #define TOTAL_CAM_ENTRY 32 104 105 /*slot time for 11g. */ 106 #define RTL_SLOT_TIME_9 9 107 #define RTL_SLOT_TIME_20 20 108 109 /*related to tcp/ip. */ 110 #define SNAP_SIZE 6 111 #define PROTOC_TYPE_SIZE 2 112 113 /*related with 802.11 frame*/ 114 #define MAC80211_3ADDR_LEN 24 115 #define MAC80211_4ADDR_LEN 30 116 117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 118 #define CHANNEL_MAX_NUMBER_2G 14 119 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to 120 *"phy_GetChnlGroup8812A" and 121 * "Hal_ReadTxPowerInfo8812A" 122 */ 123 #define CHANNEL_MAX_NUMBER_5G_80M 7 124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 125 #define MAX_PG_GROUP 13 126 #define CHANNEL_GROUP_MAX_2G 3 127 #define CHANNEL_GROUP_IDX_5GL 3 128 #define CHANNEL_GROUP_IDX_5GM 6 129 #define CHANNEL_GROUP_IDX_5GH 9 130 #define CHANNEL_GROUP_MAX_5G 9 131 #define CHANNEL_MAX_NUMBER_2G 14 132 #define AVG_THERMAL_NUM 8 133 #define AVG_THERMAL_NUM_88E 4 134 #define AVG_THERMAL_NUM_8723BE 4 135 #define MAX_TID_COUNT 9 136 137 /* for early mode */ 138 #define FCS_LEN 4 139 #define EM_HDR_LEN 8 140 141 enum rtl8192c_h2c_cmd { 142 H2C_AP_OFFLOAD = 0, 143 H2C_SETPWRMODE = 1, 144 H2C_JOINBSSRPT = 2, 145 H2C_RSVDPAGE = 3, 146 H2C_RSSI_REPORT = 5, 147 H2C_RA_MASK = 6, 148 H2C_MACID_PS_MODE = 7, 149 H2C_P2P_PS_OFFLOAD = 8, 150 H2C_MAC_MODE_SEL = 9, 151 H2C_PWRM = 15, 152 H2C_P2P_PS_CTW_CMD = 24, 153 MAX_H2CCMD 154 }; 155 156 #define MAX_TX_COUNT 4 157 #define MAX_REGULATION_NUM 4 158 #define MAX_RF_PATH_NUM 4 159 #define MAX_RATE_SECTION_NUM 6 160 #define MAX_2_4G_BANDWIDTH_NUM 4 161 #define MAX_5G_BANDWIDTH_NUM 4 162 #define MAX_RF_PATH 4 163 #define MAX_CHNL_GROUP_24G 6 164 #define MAX_CHNL_GROUP_5G 14 165 166 #define TX_PWR_BY_RATE_NUM_BAND 2 167 #define TX_PWR_BY_RATE_NUM_RF 4 168 #define TX_PWR_BY_RATE_NUM_SECTION 12 169 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 170 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 171 172 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 173 174 #define DEL_SW_IDX_SZ 30 175 176 /* For now, it's just for 8192ee 177 * but not OK yet, keep it 0 178 */ 179 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM 180 181 enum rf_tx_num { 182 RF_1TX = 0, 183 RF_2TX, 184 RF_MAX_TX_NUM, 185 RF_TX_NUM_NONIMPLEMENT, 186 }; 187 188 #define PACKET_NORMAL 0 189 #define PACKET_DHCP 1 190 #define PACKET_ARP 2 191 #define PACKET_EAPOL 3 192 193 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 194 #define RSVD_WOL_PATTERN_NUM 1 195 #define WKFMCAM_ADDR_NUM 6 196 #define WKFMCAM_SIZE 24 197 198 #define MAX_WOL_BIT_MASK_SIZE 16 199 /* MIN LEN keeps 13 here */ 200 #define MIN_WOL_PATTERN_SIZE 13 201 #define MAX_WOL_PATTERN_SIZE 128 202 203 #define WAKE_ON_MAGIC_PACKET BIT(0) 204 #define WAKE_ON_PATTERN_MATCH BIT(1) 205 206 #define WOL_REASON_PTK_UPDATE BIT(0) 207 #define WOL_REASON_GTK_UPDATE BIT(1) 208 #define WOL_REASON_DISASSOC BIT(2) 209 #define WOL_REASON_DEAUTH BIT(3) 210 #define WOL_REASON_AP_LOST BIT(4) 211 #define WOL_REASON_MAGIC_PKT BIT(5) 212 #define WOL_REASON_UNICAST_PKT BIT(6) 213 #define WOL_REASON_PATTERN_PKT BIT(7) 214 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 215 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 216 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 217 218 struct rtlwifi_firmware_header { 219 __le16 signature; 220 u8 category; 221 u8 function; 222 __le16 version; 223 u8 subversion; 224 u8 rsvd1; 225 u8 month; 226 u8 date; 227 u8 hour; 228 u8 minute; 229 __le16 ramcodeSize; 230 __le16 rsvd2; 231 __le32 svnindex; 232 __le32 rsvd3; 233 __le32 rsvd4; 234 __le32 rsvd5; 235 }; 236 237 struct txpower_info_2g { 238 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 239 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 240 /*If only one tx, only BW20 and OFDM are used.*/ 241 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 242 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 243 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 244 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 245 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 246 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 247 }; 248 249 struct txpower_info_5g { 250 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 251 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 252 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 253 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 254 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 255 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 256 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 257 }; 258 259 enum rate_section { 260 CCK = 0, 261 OFDM, 262 HT_MCS0_MCS7, 263 HT_MCS8_MCS15, 264 VHT_1SSMCS0_1SSMCS9, 265 VHT_2SSMCS0_2SSMCS9, 266 }; 267 268 enum intf_type { 269 INTF_PCI = 0, 270 INTF_USB = 1, 271 }; 272 273 enum radio_path { 274 RF90_PATH_A = 0, 275 RF90_PATH_B = 1, 276 RF90_PATH_C = 2, 277 RF90_PATH_D = 3, 278 }; 279 280 enum regulation_txpwr_lmt { 281 TXPWR_LMT_FCC = 0, 282 TXPWR_LMT_MKK = 1, 283 TXPWR_LMT_ETSI = 2, 284 TXPWR_LMT_WW = 3, 285 286 TXPWR_LMT_MAX_REGULATION_NUM = 4 287 }; 288 289 enum rt_eeprom_type { 290 EEPROM_93C46, 291 EEPROM_93C56, 292 EEPROM_BOOT_EFUSE, 293 }; 294 295 enum ttl_status { 296 RTL_STATUS_INTERFACE_START = 0, 297 }; 298 299 enum hardware_type { 300 HARDWARE_TYPE_RTL8192E, 301 HARDWARE_TYPE_RTL8192U, 302 HARDWARE_TYPE_RTL8192SE, 303 HARDWARE_TYPE_RTL8192SU, 304 HARDWARE_TYPE_RTL8192CE, 305 HARDWARE_TYPE_RTL8192CU, 306 HARDWARE_TYPE_RTL8192DE, 307 HARDWARE_TYPE_RTL8192DU, 308 HARDWARE_TYPE_RTL8723AE, 309 HARDWARE_TYPE_RTL8723U, 310 HARDWARE_TYPE_RTL8188EE, 311 HARDWARE_TYPE_RTL8723BE, 312 HARDWARE_TYPE_RTL8192EE, 313 HARDWARE_TYPE_RTL8821AE, 314 HARDWARE_TYPE_RTL8812AE, 315 HARDWARE_TYPE_RTL8822BE, 316 317 /* keep it last */ 318 HARDWARE_TYPE_NUM 319 }; 320 321 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type) 322 #define IS_NEW_GENERATION_IC(rtlpriv) \ 323 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE) 324 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \ 325 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE) 326 #define IS_HARDWARE_TYPE_8812(rtlpriv) \ 327 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE) 328 #define IS_HARDWARE_TYPE_8821(rtlpriv) \ 329 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE) 330 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \ 331 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE) 332 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \ 333 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE) 334 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \ 335 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE) 336 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \ 337 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE) 338 339 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 340 ((rxmcs) == DESC_RATE1M || \ 341 (rxmcs) == DESC_RATE2M || \ 342 (rxmcs) == DESC_RATE5_5M || \ 343 (rxmcs) == DESC_RATE11M) 344 345 enum scan_operation_backup_opt { 346 SCAN_OPT_BACKUP = 0, 347 SCAN_OPT_BACKUP_BAND0 = 0, 348 SCAN_OPT_BACKUP_BAND1, 349 SCAN_OPT_RESTORE, 350 SCAN_OPT_MAX 351 }; 352 353 /*RF state.*/ 354 enum rf_pwrstate { 355 ERFON, 356 ERFSLEEP, 357 ERFOFF 358 }; 359 360 struct bb_reg_def { 361 u32 rfintfs; 362 u32 rfintfi; 363 u32 rfintfo; 364 u32 rfintfe; 365 u32 rf3wire_offset; 366 u32 rflssi_select; 367 u32 rftxgain_stage; 368 u32 rfhssi_para1; 369 u32 rfhssi_para2; 370 u32 rfsw_ctrl; 371 u32 rfagc_control1; 372 u32 rfagc_control2; 373 u32 rfrxiq_imbal; 374 u32 rfrx_afe; 375 u32 rftxiq_imbal; 376 u32 rftx_afe; 377 u32 rf_rb; /* rflssi_readback */ 378 u32 rf_rbpi; /* rflssi_readbackpi */ 379 }; 380 381 enum io_type { 382 IO_CMD_PAUSE_DM_BY_SCAN = 0, 383 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 384 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 385 IO_CMD_RESUME_DM_BY_SCAN = 2, 386 }; 387 388 enum hw_variables { 389 HW_VAR_ETHER_ADDR = 0x0, 390 HW_VAR_MULTICAST_REG = 0x1, 391 HW_VAR_BASIC_RATE = 0x2, 392 HW_VAR_BSSID = 0x3, 393 HW_VAR_MEDIA_STATUS= 0x4, 394 HW_VAR_SECURITY_CONF= 0x5, 395 HW_VAR_BEACON_INTERVAL = 0x6, 396 HW_VAR_ATIM_WINDOW = 0x7, 397 HW_VAR_LISTEN_INTERVAL = 0x8, 398 HW_VAR_CS_COUNTER = 0x9, 399 HW_VAR_DEFAULTKEY0 = 0xa, 400 HW_VAR_DEFAULTKEY1 = 0xb, 401 HW_VAR_DEFAULTKEY2 = 0xc, 402 HW_VAR_DEFAULTKEY3 = 0xd, 403 HW_VAR_SIFS = 0xe, 404 HW_VAR_R2T_SIFS = 0xf, 405 HW_VAR_DIFS = 0x10, 406 HW_VAR_EIFS = 0x11, 407 HW_VAR_SLOT_TIME = 0x12, 408 HW_VAR_ACK_PREAMBLE = 0x13, 409 HW_VAR_CW_CONFIG = 0x14, 410 HW_VAR_CW_VALUES = 0x15, 411 HW_VAR_RATE_FALLBACK_CONTROL= 0x16, 412 HW_VAR_CONTENTION_WINDOW = 0x17, 413 HW_VAR_RETRY_COUNT = 0x18, 414 HW_VAR_TR_SWITCH = 0x19, 415 HW_VAR_COMMAND = 0x1a, 416 HW_VAR_WPA_CONFIG = 0x1b, 417 HW_VAR_AMPDU_MIN_SPACE = 0x1c, 418 HW_VAR_SHORTGI_DENSITY = 0x1d, 419 HW_VAR_AMPDU_FACTOR = 0x1e, 420 HW_VAR_MCS_RATE_AVAILABLE = 0x1f, 421 HW_VAR_AC_PARAM = 0x20, 422 HW_VAR_ACM_CTRL = 0x21, 423 HW_VAR_DIS_Req_Qsize = 0x22, 424 HW_VAR_CCX_CHNL_LOAD = 0x23, 425 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24, 426 HW_VAR_CCX_CLM_NHM = 0x25, 427 HW_VAR_TxOPLimit = 0x26, 428 HW_VAR_TURBO_MODE = 0x27, 429 HW_VAR_RF_STATE = 0x28, 430 HW_VAR_RF_OFF_BY_HW = 0x29, 431 HW_VAR_BUS_SPEED = 0x2a, 432 HW_VAR_SET_DEV_POWER = 0x2b, 433 434 HW_VAR_RCR = 0x2c, 435 HW_VAR_RATR_0 = 0x2d, 436 HW_VAR_RRSR = 0x2e, 437 HW_VAR_CPU_RST = 0x2f, 438 HW_VAR_CHECK_BSSID = 0x30, 439 HW_VAR_LBK_MODE = 0x31, 440 HW_VAR_AES_11N_FIX = 0x32, 441 HW_VAR_USB_RX_AGGR = 0x33, 442 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34, 443 HW_VAR_RETRY_LIMIT = 0x35, 444 HW_VAR_INIT_TX_RATE = 0x36, 445 HW_VAR_TX_RATE_REG = 0x37, 446 HW_VAR_EFUSE_USAGE = 0x38, 447 HW_VAR_EFUSE_BYTES = 0x39, 448 HW_VAR_AUTOLOAD_STATUS = 0x3a, 449 HW_VAR_RF_2R_DISABLE = 0x3b, 450 HW_VAR_SET_RPWM = 0x3c, 451 HW_VAR_H2C_FW_PWRMODE = 0x3d, 452 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e, 453 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f, 454 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40, 455 HW_VAR_FW_PSMODE_STATUS = 0x41, 456 HW_VAR_INIT_RTS_RATE = 0x42, 457 HW_VAR_RESUME_CLK_ON = 0x43, 458 HW_VAR_FW_LPS_ACTION = 0x44, 459 HW_VAR_1X1_RECV_COMBINE = 0x45, 460 HW_VAR_STOP_SEND_BEACON = 0x46, 461 HW_VAR_TSF_TIMER = 0x47, 462 HW_VAR_IO_CMD = 0x48, 463 464 HW_VAR_RF_RECOVERY = 0x49, 465 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a, 466 HW_VAR_WF_MASK = 0x4b, 467 HW_VAR_WF_CRC = 0x4c, 468 HW_VAR_WF_IS_MAC_ADDR = 0x4d, 469 HW_VAR_H2C_FW_OFFLOAD = 0x4e, 470 HW_VAR_RESET_WFCRC = 0x4f, 471 472 HW_VAR_HANDLE_FW_C2H = 0x50, 473 HW_VAR_DL_FW_RSVD_PAGE = 0x51, 474 HW_VAR_AID = 0x52, 475 HW_VAR_HW_SEQ_ENABLE = 0x53, 476 HW_VAR_CORRECT_TSF = 0x54, 477 HW_VAR_BCN_VALID = 0x55, 478 HW_VAR_FWLPS_RF_ON = 0x56, 479 HW_VAR_DUAL_TSF_RST = 0x57, 480 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58, 481 HW_VAR_INT_MIGRATION = 0x59, 482 HW_VAR_INT_AC = 0x5a, 483 HW_VAR_RF_TIMING = 0x5b, 484 485 HAL_DEF_WOWLAN = 0x5c, 486 HW_VAR_MRC = 0x5d, 487 HW_VAR_KEEP_ALIVE = 0x5e, 488 HW_VAR_NAV_UPPER = 0x5f, 489 490 HW_VAR_MGT_FILTER = 0x60, 491 HW_VAR_CTRL_FILTER = 0x61, 492 HW_VAR_DATA_FILTER = 0x62, 493 }; 494 495 enum rt_media_status { 496 RT_MEDIA_DISCONNECT = 0, 497 RT_MEDIA_CONNECT = 1 498 }; 499 500 enum rt_oem_id { 501 RT_CID_DEFAULT = 0, 502 RT_CID_8187_ALPHA0 = 1, 503 RT_CID_8187_SERCOMM_PS = 2, 504 RT_CID_8187_HW_LED = 3, 505 RT_CID_8187_NETGEAR = 4, 506 RT_CID_WHQL = 5, 507 RT_CID_819X_CAMEO = 6, 508 RT_CID_819X_RUNTOP = 7, 509 RT_CID_819X_SENAO = 8, 510 RT_CID_TOSHIBA = 9, 511 RT_CID_819X_NETCORE = 10, 512 RT_CID_NETTRONIX = 11, 513 RT_CID_DLINK = 12, 514 RT_CID_PRONET = 13, 515 RT_CID_COREGA = 14, 516 RT_CID_819X_ALPHA = 15, 517 RT_CID_819X_SITECOM = 16, 518 RT_CID_CCX = 17, 519 RT_CID_819X_LENOVO = 18, 520 RT_CID_819X_QMI = 19, 521 RT_CID_819X_EDIMAX_BELKIN = 20, 522 RT_CID_819X_SERCOMM_BELKIN = 21, 523 RT_CID_819X_CAMEO1 = 22, 524 RT_CID_819X_MSI = 23, 525 RT_CID_819X_ACER = 24, 526 RT_CID_819X_HP = 27, 527 RT_CID_819X_CLEVO = 28, 528 RT_CID_819X_ARCADYAN_BELKIN = 29, 529 RT_CID_819X_SAMSUNG = 30, 530 RT_CID_819X_WNC_COREGA = 31, 531 RT_CID_819X_FOXCOON = 32, 532 RT_CID_819X_DELL = 33, 533 RT_CID_819X_PRONETS = 34, 534 RT_CID_819X_EDIMAX_ASUS = 35, 535 RT_CID_NETGEAR = 36, 536 RT_CID_PLANEX = 37, 537 RT_CID_CC_C = 38, 538 }; 539 540 enum hw_descs { 541 HW_DESC_OWN, 542 HW_DESC_RXOWN, 543 HW_DESC_TX_NEXTDESC_ADDR, 544 HW_DESC_TXBUFF_ADDR, 545 HW_DESC_RXBUFF_ADDR, 546 HW_DESC_RXPKT_LEN, 547 HW_DESC_RXERO, 548 HW_DESC_RX_PREPARE, 549 }; 550 551 enum prime_sc { 552 PRIME_CHNL_OFFSET_DONT_CARE = 0, 553 PRIME_CHNL_OFFSET_LOWER = 1, 554 PRIME_CHNL_OFFSET_UPPER = 2, 555 }; 556 557 enum rf_type { 558 RF_1T1R = 0, 559 RF_1T2R = 1, 560 RF_2T2R = 2, 561 RF_2T2R_GREEN = 3, 562 RF_2T3R = 4, 563 RF_2T4R = 5, 564 RF_3T3R = 6, 565 RF_3T4R = 7, 566 RF_4T4R = 8, 567 }; 568 569 enum ht_channel_width { 570 HT_CHANNEL_WIDTH_20 = 0, 571 HT_CHANNEL_WIDTH_20_40 = 1, 572 HT_CHANNEL_WIDTH_80 = 2, 573 }; 574 575 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 576 Cipher Suites Encryption Algorithms */ 577 enum rt_enc_alg { 578 NO_ENCRYPTION = 0, 579 WEP40_ENCRYPTION = 1, 580 TKIP_ENCRYPTION = 2, 581 RSERVED_ENCRYPTION = 3, 582 AESCCMP_ENCRYPTION = 4, 583 WEP104_ENCRYPTION = 5, 584 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 585 }; 586 587 enum rtl_hal_state { 588 _HAL_STATE_STOP = 0, 589 _HAL_STATE_START = 1, 590 }; 591 592 enum rtl_desc_rate { 593 DESC_RATE1M = 0x00, 594 DESC_RATE2M = 0x01, 595 DESC_RATE5_5M = 0x02, 596 DESC_RATE11M = 0x03, 597 598 DESC_RATE6M = 0x04, 599 DESC_RATE9M = 0x05, 600 DESC_RATE12M = 0x06, 601 DESC_RATE18M = 0x07, 602 DESC_RATE24M = 0x08, 603 DESC_RATE36M = 0x09, 604 DESC_RATE48M = 0x0a, 605 DESC_RATE54M = 0x0b, 606 607 DESC_RATEMCS0 = 0x0c, 608 DESC_RATEMCS1 = 0x0d, 609 DESC_RATEMCS2 = 0x0e, 610 DESC_RATEMCS3 = 0x0f, 611 DESC_RATEMCS4 = 0x10, 612 DESC_RATEMCS5 = 0x11, 613 DESC_RATEMCS6 = 0x12, 614 DESC_RATEMCS7 = 0x13, 615 DESC_RATEMCS8 = 0x14, 616 DESC_RATEMCS9 = 0x15, 617 DESC_RATEMCS10 = 0x16, 618 DESC_RATEMCS11 = 0x17, 619 DESC_RATEMCS12 = 0x18, 620 DESC_RATEMCS13 = 0x19, 621 DESC_RATEMCS14 = 0x1a, 622 DESC_RATEMCS15 = 0x1b, 623 DESC_RATEMCS15_SG = 0x1c, 624 DESC_RATEMCS32 = 0x20, 625 626 DESC_RATEVHT1SS_MCS0 = 0x2c, 627 DESC_RATEVHT1SS_MCS1 = 0x2d, 628 DESC_RATEVHT1SS_MCS2 = 0x2e, 629 DESC_RATEVHT1SS_MCS3 = 0x2f, 630 DESC_RATEVHT1SS_MCS4 = 0x30, 631 DESC_RATEVHT1SS_MCS5 = 0x31, 632 DESC_RATEVHT1SS_MCS6 = 0x32, 633 DESC_RATEVHT1SS_MCS7 = 0x33, 634 DESC_RATEVHT1SS_MCS8 = 0x34, 635 DESC_RATEVHT1SS_MCS9 = 0x35, 636 DESC_RATEVHT2SS_MCS0 = 0x36, 637 DESC_RATEVHT2SS_MCS1 = 0x37, 638 DESC_RATEVHT2SS_MCS2 = 0x38, 639 DESC_RATEVHT2SS_MCS3 = 0x39, 640 DESC_RATEVHT2SS_MCS4 = 0x3a, 641 DESC_RATEVHT2SS_MCS5 = 0x3b, 642 DESC_RATEVHT2SS_MCS6 = 0x3c, 643 DESC_RATEVHT2SS_MCS7 = 0x3d, 644 DESC_RATEVHT2SS_MCS8 = 0x3e, 645 DESC_RATEVHT2SS_MCS9 = 0x3f, 646 }; 647 648 enum rtl_var_map { 649 /*reg map */ 650 SYS_ISO_CTRL = 0, 651 SYS_FUNC_EN, 652 SYS_CLK, 653 MAC_RCR_AM, 654 MAC_RCR_AB, 655 MAC_RCR_ACRC32, 656 MAC_RCR_ACF, 657 MAC_RCR_AAP, 658 MAC_HIMR, 659 MAC_HIMRE, 660 MAC_HSISR, 661 662 /*efuse map */ 663 EFUSE_TEST, 664 EFUSE_CTRL, 665 EFUSE_CLK, 666 EFUSE_CLK_CTRL, 667 EFUSE_PWC_EV12V, 668 EFUSE_FEN_ELDR, 669 EFUSE_LOADER_CLK_EN, 670 EFUSE_ANA8M, 671 EFUSE_HWSET_MAX_SIZE, 672 EFUSE_MAX_SECTION_MAP, 673 EFUSE_REAL_CONTENT_SIZE, 674 EFUSE_OOB_PROTECT_BYTES_LEN, 675 EFUSE_ACCESS, 676 677 /*CAM map */ 678 RWCAM, 679 WCAMI, 680 RCAMO, 681 CAMDBG, 682 SECR, 683 SEC_CAM_NONE, 684 SEC_CAM_WEP40, 685 SEC_CAM_TKIP, 686 SEC_CAM_AES, 687 SEC_CAM_WEP104, 688 689 /*IMR map */ 690 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 691 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 692 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 693 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 694 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 695 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 696 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 697 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 698 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 699 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 700 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 701 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 702 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 703 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 704 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 705 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 706 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 707 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 708 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 709 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 710 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 711 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 712 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 713 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 714 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 715 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 716 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 717 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 718 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 719 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 720 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 721 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 722 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 723 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 724 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 725 * RTL_IMR_TBDER) */ 726 RTL_IMR_C2HCMD, /*fw interrupt*/ 727 728 /*CCK Rates, TxHT = 0 */ 729 RTL_RC_CCK_RATE1M, 730 RTL_RC_CCK_RATE2M, 731 RTL_RC_CCK_RATE5_5M, 732 RTL_RC_CCK_RATE11M, 733 734 /*OFDM Rates, TxHT = 0 */ 735 RTL_RC_OFDM_RATE6M, 736 RTL_RC_OFDM_RATE9M, 737 RTL_RC_OFDM_RATE12M, 738 RTL_RC_OFDM_RATE18M, 739 RTL_RC_OFDM_RATE24M, 740 RTL_RC_OFDM_RATE36M, 741 RTL_RC_OFDM_RATE48M, 742 RTL_RC_OFDM_RATE54M, 743 744 RTL_RC_HT_RATEMCS7, 745 RTL_RC_HT_RATEMCS15, 746 747 RTL_RC_VHT_RATE_1SS_MCS7, 748 RTL_RC_VHT_RATE_1SS_MCS8, 749 RTL_RC_VHT_RATE_1SS_MCS9, 750 RTL_RC_VHT_RATE_2SS_MCS7, 751 RTL_RC_VHT_RATE_2SS_MCS8, 752 RTL_RC_VHT_RATE_2SS_MCS9, 753 754 /*keep it last */ 755 RTL_VAR_MAP_MAX, 756 }; 757 758 /*Firmware PS mode for control LPS.*/ 759 enum _fw_ps_mode { 760 FW_PS_ACTIVE_MODE = 0, 761 FW_PS_MIN_MODE = 1, 762 FW_PS_MAX_MODE = 2, 763 FW_PS_DTIM_MODE = 3, 764 FW_PS_VOIP_MODE = 4, 765 FW_PS_UAPSD_WMM_MODE = 5, 766 FW_PS_UAPSD_MODE = 6, 767 FW_PS_IBSS_MODE = 7, 768 FW_PS_WWLAN_MODE = 8, 769 FW_PS_PM_Radio_Off = 9, 770 FW_PS_PM_Card_Disable = 10, 771 }; 772 773 enum rt_psmode { 774 EACTIVE, /*Active/Continuous access. */ 775 EMAXPS, /*Max power save mode. */ 776 EFASTPS, /*Fast power save mode. */ 777 EAUTOPS, /*Auto power save mode. */ 778 }; 779 780 /*LED related.*/ 781 enum led_ctl_mode { 782 LED_CTL_POWER_ON = 1, 783 LED_CTL_LINK = 2, 784 LED_CTL_NO_LINK = 3, 785 LED_CTL_TX = 4, 786 LED_CTL_RX = 5, 787 LED_CTL_SITE_SURVEY = 6, 788 LED_CTL_POWER_OFF = 7, 789 LED_CTL_START_TO_LINK = 8, 790 LED_CTL_START_WPS = 9, 791 LED_CTL_STOP_WPS = 10, 792 }; 793 794 enum rtl_led_pin { 795 LED_PIN_GPIO0, 796 LED_PIN_LED0, 797 LED_PIN_LED1, 798 LED_PIN_LED2 799 }; 800 801 /*QoS related.*/ 802 /*acm implementation method.*/ 803 enum acm_method { 804 eAcmWay0_SwAndHw = 0, 805 eAcmWay1_HW = 1, 806 EACMWAY2_SW = 2, 807 }; 808 809 enum macphy_mode { 810 SINGLEMAC_SINGLEPHY = 0, 811 DUALMAC_DUALPHY, 812 DUALMAC_SINGLEPHY, 813 }; 814 815 enum band_type { 816 BAND_ON_2_4G = 0, 817 BAND_ON_5G, 818 BAND_ON_BOTH, 819 BANDMAX 820 }; 821 822 /*aci/aifsn Field. 823 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 824 union aci_aifsn { 825 u8 char_data; 826 827 struct { 828 u8 aifsn:4; 829 u8 acm:1; 830 u8 aci:2; 831 u8 reserved:1; 832 } f; /* Field */ 833 }; 834 835 /*mlme related.*/ 836 enum wireless_mode { 837 WIRELESS_MODE_UNKNOWN = 0x00, 838 WIRELESS_MODE_A = 0x01, 839 WIRELESS_MODE_B = 0x02, 840 WIRELESS_MODE_G = 0x04, 841 WIRELESS_MODE_AUTO = 0x08, 842 WIRELESS_MODE_N_24G = 0x10, 843 WIRELESS_MODE_N_5G = 0x20, 844 WIRELESS_MODE_AC_5G = 0x40, 845 WIRELESS_MODE_AC_24G = 0x80, 846 WIRELESS_MODE_AC_ONLY = 0x100, 847 WIRELESS_MODE_MAX = 0x800 848 }; 849 850 #define IS_WIRELESS_MODE_A(wirelessmode) \ 851 (wirelessmode == WIRELESS_MODE_A) 852 #define IS_WIRELESS_MODE_B(wirelessmode) \ 853 (wirelessmode == WIRELESS_MODE_B) 854 #define IS_WIRELESS_MODE_G(wirelessmode) \ 855 (wirelessmode == WIRELESS_MODE_G) 856 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 857 (wirelessmode == WIRELESS_MODE_N_24G) 858 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 859 (wirelessmode == WIRELESS_MODE_N_5G) 860 861 enum ratr_table_mode { 862 RATR_INX_WIRELESS_NGB = 0, 863 RATR_INX_WIRELESS_NG = 1, 864 RATR_INX_WIRELESS_NB = 2, 865 RATR_INX_WIRELESS_N = 3, 866 RATR_INX_WIRELESS_GB = 4, 867 RATR_INX_WIRELESS_G = 5, 868 RATR_INX_WIRELESS_B = 6, 869 RATR_INX_WIRELESS_MC = 7, 870 RATR_INX_WIRELESS_A = 8, 871 RATR_INX_WIRELESS_AC_5N = 8, 872 RATR_INX_WIRELESS_AC_24N = 9, 873 }; 874 875 enum rtl_link_state { 876 MAC80211_NOLINK = 0, 877 MAC80211_LINKING = 1, 878 MAC80211_LINKED = 2, 879 MAC80211_LINKED_SCANNING = 3, 880 }; 881 882 enum act_category { 883 ACT_CAT_QOS = 1, 884 ACT_CAT_DLS = 2, 885 ACT_CAT_BA = 3, 886 ACT_CAT_HT = 7, 887 ACT_CAT_WMM = 17, 888 }; 889 890 enum ba_action { 891 ACT_ADDBAREQ = 0, 892 ACT_ADDBARSP = 1, 893 ACT_DELBA = 2, 894 }; 895 896 enum rt_polarity_ctl { 897 RT_POLARITY_LOW_ACT = 0, 898 RT_POLARITY_HIGH_ACT = 1, 899 }; 900 901 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 902 enum fw_wow_reason_v2 { 903 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 904 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 905 FW_WOW_V2_DISASSOC_EVENT = 0x04, 906 FW_WOW_V2_DEAUTH_EVENT = 0x08, 907 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 908 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 909 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 910 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 911 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 912 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 913 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 914 FW_WOW_V2_REASON_MAX = 0xff, 915 }; 916 917 enum wolpattern_type { 918 UNICAST_PATTERN = 0, 919 MULTICAST_PATTERN = 1, 920 BROADCAST_PATTERN = 2, 921 DONT_CARE_DA = 3, 922 UNKNOWN_TYPE = 4, 923 }; 924 925 enum package_type { 926 PACKAGE_DEFAULT, 927 PACKAGE_QFN68, 928 PACKAGE_TFBGA90, 929 PACKAGE_TFBGA80, 930 PACKAGE_TFBGA79 931 }; 932 933 struct octet_string { 934 u8 *octet; 935 u16 length; 936 }; 937 938 struct rtl_hdr_3addr { 939 __le16 frame_ctl; 940 __le16 duration_id; 941 u8 addr1[ETH_ALEN]; 942 u8 addr2[ETH_ALEN]; 943 u8 addr3[ETH_ALEN]; 944 __le16 seq_ctl; 945 u8 payload[0]; 946 } __packed; 947 948 struct rtl_info_element { 949 u8 id; 950 u8 len; 951 u8 data[0]; 952 } __packed; 953 954 struct rtl_probe_rsp { 955 struct rtl_hdr_3addr header; 956 u32 time_stamp[2]; 957 __le16 beacon_interval; 958 __le16 capability; 959 /*SSID, supported rates, FH params, DS params, 960 CF params, IBSS params, TIM (if beacon), RSN */ 961 struct rtl_info_element info_element[0]; 962 } __packed; 963 964 /*LED related.*/ 965 /*ledpin Identify how to implement this SW led.*/ 966 struct rtl_led { 967 void *hw; 968 enum rtl_led_pin ledpin; 969 bool ledon; 970 }; 971 972 struct rtl_led_ctl { 973 bool led_opendrain; 974 struct rtl_led sw_led0; 975 struct rtl_led sw_led1; 976 }; 977 978 struct rtl_qos_parameters { 979 __le16 cw_min; 980 __le16 cw_max; 981 u8 aifs; 982 u8 flag; 983 __le16 tx_op; 984 } __packed; 985 986 struct rt_smooth_data { 987 u32 elements[100]; /*array to store values */ 988 u32 index; /*index to current array to store */ 989 u32 total_num; /*num of valid elements */ 990 u32 total_val; /*sum of valid elements */ 991 }; 992 993 struct false_alarm_statistics { 994 u32 cnt_parity_fail; 995 u32 cnt_rate_illegal; 996 u32 cnt_crc8_fail; 997 u32 cnt_mcs_fail; 998 u32 cnt_fast_fsync_fail; 999 u32 cnt_sb_search_fail; 1000 u32 cnt_ofdm_fail; 1001 u32 cnt_cck_fail; 1002 u32 cnt_all; 1003 u32 cnt_ofdm_cca; 1004 u32 cnt_cck_cca; 1005 u32 cnt_cca_all; 1006 u32 cnt_bw_usc; 1007 u32 cnt_bw_lsc; 1008 }; 1009 1010 struct init_gain { 1011 u8 xaagccore1; 1012 u8 xbagccore1; 1013 u8 xcagccore1; 1014 u8 xdagccore1; 1015 u8 cca; 1016 1017 }; 1018 1019 struct wireless_stats { 1020 u64 txbytesunicast; 1021 u64 txbytesmulticast; 1022 u64 txbytesbroadcast; 1023 u64 rxbytesunicast; 1024 1025 u64 txbytesunicast_inperiod; 1026 u64 rxbytesunicast_inperiod; 1027 u32 txbytesunicast_inperiod_tp; 1028 u32 rxbytesunicast_inperiod_tp; 1029 u64 txbytesunicast_last; 1030 u64 rxbytesunicast_last; 1031 1032 long rx_snr_db[4]; 1033 /*Correct smoothed ss in Dbm, only used 1034 in driver to report real power now. */ 1035 long recv_signal_power; 1036 long signal_quality; 1037 long last_sigstrength_inpercent; 1038 1039 u32 rssi_calculate_cnt; 1040 u32 pwdb_all_cnt; 1041 1042 /*Transformed, in dbm. Beautified signal 1043 strength for UI, not correct. */ 1044 long signal_strength; 1045 1046 u8 rx_rssi_percentage[4]; 1047 u8 rx_evm_dbm[4]; 1048 u8 rx_evm_percentage[2]; 1049 1050 u16 rx_cfo_short[4]; 1051 u16 rx_cfo_tail[4]; 1052 1053 struct rt_smooth_data ui_rssi; 1054 struct rt_smooth_data ui_link_quality; 1055 }; 1056 1057 struct rate_adaptive { 1058 u8 rate_adaptive_disabled; 1059 u8 ratr_state; 1060 u16 reserve; 1061 1062 u32 high_rssi_thresh_for_ra; 1063 u32 high2low_rssi_thresh_for_ra; 1064 u8 low2high_rssi_thresh_for_ra40m; 1065 u32 low_rssi_thresh_for_ra40m; 1066 u8 low2high_rssi_thresh_for_ra20m; 1067 u32 low_rssi_thresh_for_ra20m; 1068 u32 upper_rssi_threshold_ratr; 1069 u32 middleupper_rssi_threshold_ratr; 1070 u32 middle_rssi_threshold_ratr; 1071 u32 middlelow_rssi_threshold_ratr; 1072 u32 low_rssi_threshold_ratr; 1073 u32 ultralow_rssi_threshold_ratr; 1074 u32 low_rssi_threshold_ratr_40m; 1075 u32 low_rssi_threshold_ratr_20m; 1076 u8 ping_rssi_enable; 1077 u32 ping_rssi_ratr; 1078 u32 ping_rssi_thresh_for_ra; 1079 u32 last_ratr; 1080 u8 pre_ratr_state; 1081 u8 ldpc_thres; 1082 bool use_ldpc; 1083 bool lower_rts_rate; 1084 bool is_special_data; 1085 }; 1086 1087 struct regd_pair_mapping { 1088 u16 reg_dmnenum; 1089 u16 reg_5ghz_ctl; 1090 u16 reg_2ghz_ctl; 1091 }; 1092 1093 struct dynamic_primary_cca { 1094 u8 pricca_flag; 1095 u8 intf_flag; 1096 u8 intf_type; 1097 u8 dup_rts_flag; 1098 u8 monitor_flag; 1099 u8 ch_offset; 1100 u8 mf_state; 1101 }; 1102 1103 struct rtl_regulatory { 1104 s8 alpha2[2]; 1105 u16 country_code; 1106 u16 max_power_level; 1107 u32 tp_scale; 1108 u16 current_rd; 1109 u16 current_rd_ext; 1110 int16_t power_limit; 1111 struct regd_pair_mapping *regpair; 1112 }; 1113 1114 struct rtl_rfkill { 1115 bool rfkill_state; /*0 is off, 1 is on */ 1116 }; 1117 1118 /*for P2P PS**/ 1119 #define P2P_MAX_NOA_NUM 2 1120 1121 enum p2p_role { 1122 P2P_ROLE_DISABLE = 0, 1123 P2P_ROLE_DEVICE = 1, 1124 P2P_ROLE_CLIENT = 2, 1125 P2P_ROLE_GO = 3 1126 }; 1127 1128 enum p2p_ps_state { 1129 P2P_PS_DISABLE = 0, 1130 P2P_PS_ENABLE = 1, 1131 P2P_PS_SCAN = 2, 1132 P2P_PS_SCAN_DONE = 3, 1133 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1134 }; 1135 1136 enum p2p_ps_mode { 1137 P2P_PS_NONE = 0, 1138 P2P_PS_CTWINDOW = 1, 1139 P2P_PS_NOA = 2, 1140 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1141 }; 1142 1143 struct rtl_p2p_ps_info { 1144 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1145 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1146 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1147 /* Client traffic window. A period of time in TU after TBTT. */ 1148 u8 ctwindow; 1149 u8 opp_ps; /* opportunistic power save. */ 1150 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1151 /* Count for owner, Type of client. */ 1152 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1153 /* Max duration for owner, preferred or min acceptable duration 1154 * for client. 1155 */ 1156 u32 noa_duration[P2P_MAX_NOA_NUM]; 1157 /* Length of interval for owner, preferred or max acceptable intervali 1158 * of client. 1159 */ 1160 u32 noa_interval[P2P_MAX_NOA_NUM]; 1161 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1162 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1163 }; 1164 1165 struct p2p_ps_offload_t { 1166 u8 offload_en:1; 1167 u8 role:1; /* 1: Owner, 0: Client */ 1168 u8 ctwindow_en:1; 1169 u8 noa0_en:1; 1170 u8 noa1_en:1; 1171 u8 allstasleep:1; 1172 u8 discovery:1; 1173 u8 reserved:1; 1174 }; 1175 1176 #define IQK_MATRIX_REG_NUM 8 1177 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1178 1179 struct iqk_matrix_regs { 1180 bool iqk_done; 1181 long value[1][IQK_MATRIX_REG_NUM]; 1182 }; 1183 1184 struct phy_parameters { 1185 u16 length; 1186 u32 *pdata; 1187 }; 1188 1189 enum hw_param_tab_index { 1190 PHY_REG_2T, 1191 PHY_REG_1T, 1192 PHY_REG_PG, 1193 RADIOA_2T, 1194 RADIOB_2T, 1195 RADIOA_1T, 1196 RADIOB_1T, 1197 MAC_REG, 1198 AGCTAB_2T, 1199 AGCTAB_1T, 1200 MAX_TAB 1201 }; 1202 1203 struct rtl_phy { 1204 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1205 struct init_gain initgain_backup; 1206 enum io_type current_io_type; 1207 1208 u8 rf_mode; 1209 u8 rf_type; 1210 u8 current_chan_bw; 1211 u8 set_bwmode_inprogress; 1212 u8 sw_chnl_inprogress; 1213 u8 sw_chnl_stage; 1214 u8 sw_chnl_step; 1215 u8 current_channel; 1216 u8 h2c_box_num; 1217 u8 set_io_inprogress; 1218 u8 lck_inprogress; 1219 1220 /* record for power tracking */ 1221 s32 reg_e94; 1222 s32 reg_e9c; 1223 s32 reg_ea4; 1224 s32 reg_eac; 1225 s32 reg_eb4; 1226 s32 reg_ebc; 1227 s32 reg_ec4; 1228 s32 reg_ecc; 1229 u8 rfpienable; 1230 u8 reserve_0; 1231 u16 reserve_1; 1232 u32 reg_c04, reg_c08, reg_874; 1233 u32 adda_backup[16]; 1234 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1235 u32 iqk_bb_backup[10]; 1236 bool iqk_initialized; 1237 1238 bool rfpath_rx_enable[MAX_RF_PATH]; 1239 u8 reg_837; 1240 /* Dual mac */ 1241 bool need_iqk; 1242 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1243 1244 bool rfpi_enable; 1245 bool iqk_in_progress; 1246 1247 u8 pwrgroup_cnt; 1248 u8 cck_high_power; 1249 /* this is for 88E & 8723A */ 1250 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1251 /* MAX_PG_GROUP groups of pwr diff by rates */ 1252 u32 mcs_offset[MAX_PG_GROUP][16]; 1253 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1254 [TX_PWR_BY_RATE_NUM_RF] 1255 [TX_PWR_BY_RATE_NUM_RF] 1256 [TX_PWR_BY_RATE_NUM_SECTION]; 1257 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1258 [TX_PWR_BY_RATE_NUM_RF] 1259 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1260 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1261 [TX_PWR_BY_RATE_NUM_RF] 1262 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1263 u8 default_initialgain[4]; 1264 1265 /* the current Tx power level */ 1266 u8 cur_cck_txpwridx; 1267 u8 cur_ofdm24g_txpwridx; 1268 u8 cur_bw20_txpwridx; 1269 u8 cur_bw40_txpwridx; 1270 1271 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM] 1272 [MAX_2_4G_BANDWIDTH_NUM] 1273 [MAX_RATE_SECTION_NUM] 1274 [CHANNEL_MAX_NUMBER_2G] 1275 [MAX_RF_PATH_NUM]; 1276 s8 txpwr_limit_5g[MAX_REGULATION_NUM] 1277 [MAX_5G_BANDWIDTH_NUM] 1278 [MAX_RATE_SECTION_NUM] 1279 [CHANNEL_MAX_NUMBER_5G] 1280 [MAX_RF_PATH_NUM]; 1281 1282 u32 rfreg_chnlval[2]; 1283 bool apk_done; 1284 u32 reg_rf3c[2]; /* pathA / pathB */ 1285 1286 u32 backup_rf_0x1a;/*92ee*/ 1287 /* bfsync */ 1288 u8 framesync; 1289 u32 framesync_c34; 1290 1291 u8 num_total_rfpath; 1292 struct phy_parameters hwparam_tables[MAX_TAB]; 1293 u16 rf_pathmap; 1294 1295 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1296 enum rt_polarity_ctl polarity_ctl; 1297 }; 1298 1299 #define MAX_TID_COUNT 9 1300 #define RTL_AGG_STOP 0 1301 #define RTL_AGG_PROGRESS 1 1302 #define RTL_AGG_START 2 1303 #define RTL_AGG_OPERATIONAL 3 1304 #define RTL_AGG_OFF 0 1305 #define RTL_AGG_ON 1 1306 #define RTL_RX_AGG_START 1 1307 #define RTL_RX_AGG_STOP 0 1308 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1309 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1310 1311 struct rtl_ht_agg { 1312 u16 txq_id; 1313 u16 wait_for_ba; 1314 u16 start_idx; 1315 u64 bitmap; 1316 u32 rate_n_flags; 1317 u8 agg_state; 1318 u8 rx_agg_state; 1319 }; 1320 1321 struct rssi_sta { 1322 long undec_sm_pwdb; 1323 long undec_sm_cck; 1324 }; 1325 1326 struct rtl_tid_data { 1327 u16 seq_number; 1328 struct rtl_ht_agg agg; 1329 }; 1330 1331 struct rtl_sta_info { 1332 struct list_head list; 1333 struct rtl_tid_data tids[MAX_TID_COUNT]; 1334 /* just used for ap adhoc or mesh*/ 1335 struct rssi_sta rssi_stat; 1336 u8 rssi_level; 1337 u16 wireless_mode; 1338 u8 ratr_index; 1339 u8 mimo_ps; 1340 u8 mac_addr[ETH_ALEN]; 1341 } __packed; 1342 1343 struct rtl_priv; 1344 struct rtl_io { 1345 struct device *dev; 1346 struct mutex bb_mutex; 1347 1348 /*PCI MEM map */ 1349 unsigned long pci_mem_end; /*shared mem end */ 1350 unsigned long pci_mem_start; /*shared mem start */ 1351 1352 /*PCI IO map */ 1353 unsigned long pci_base_addr; /*device I/O address */ 1354 1355 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1356 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1357 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1358 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1359 u16 len); 1360 1361 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1362 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1363 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1364 1365 }; 1366 1367 struct rtl_mac { 1368 u8 mac_addr[ETH_ALEN]; 1369 u8 mac80211_registered; 1370 u8 beacon_enabled; 1371 1372 u32 tx_ss_num; 1373 u32 rx_ss_num; 1374 1375 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1376 struct ieee80211_hw *hw; 1377 struct ieee80211_vif *vif; 1378 enum nl80211_iftype opmode; 1379 1380 /*Probe Beacon management */ 1381 struct rtl_tid_data tids[MAX_TID_COUNT]; 1382 enum rtl_link_state link_state; 1383 1384 int n_channels; 1385 int n_bitrates; 1386 1387 bool offchan_delay; 1388 u8 p2p; /*using p2p role*/ 1389 bool p2p_in_use; 1390 1391 /*filters */ 1392 u32 rx_conf; 1393 u16 rx_mgt_filter; 1394 u16 rx_ctrl_filter; 1395 u16 rx_data_filter; 1396 1397 bool act_scanning; 1398 u8 cnt_after_linked; 1399 bool skip_scan; 1400 1401 /* early mode */ 1402 /* skb wait queue */ 1403 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1404 1405 u8 ht_stbc_cap; 1406 u8 ht_cur_stbc; 1407 1408 /*vht support*/ 1409 u8 vht_enable; 1410 u8 bw_80; 1411 u8 vht_cur_ldpc; 1412 u8 vht_cur_stbc; 1413 u8 vht_stbc_cap; 1414 u8 vht_ldpc_cap; 1415 1416 /*RDG*/ 1417 bool rdg_en; 1418 1419 /*AP*/ 1420 u8 bssid[ETH_ALEN] __aligned(2); 1421 u32 vendor; 1422 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1423 u32 basic_rates; /* b/g rates */ 1424 u8 ht_enable; 1425 u8 sgi_40; 1426 u8 sgi_20; 1427 u8 bw_40; 1428 u16 mode; /* wireless mode */ 1429 u8 slot_time; 1430 u8 short_preamble; 1431 u8 use_cts_protect; 1432 u8 cur_40_prime_sc; 1433 u8 cur_40_prime_sc_bk; 1434 u8 cur_80_prime_sc; 1435 u64 tsf; 1436 u8 retry_short; 1437 u8 retry_long; 1438 u16 assoc_id; 1439 bool hiddenssid; 1440 1441 /*IBSS*/ 1442 int beacon_interval; 1443 1444 /*AMPDU*/ 1445 u8 min_space_cfg; /*For Min spacing configurations */ 1446 u8 max_mss_density; 1447 u8 current_ampdu_factor; 1448 u8 current_ampdu_density; 1449 1450 /*QOS & EDCA */ 1451 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1452 struct rtl_qos_parameters ac[AC_MAX]; 1453 1454 /* counters */ 1455 u64 last_txok_cnt; 1456 u64 last_rxok_cnt; 1457 u32 last_bt_edca_ul; 1458 u32 last_bt_edca_dl; 1459 }; 1460 1461 struct btdm_8723 { 1462 bool all_off; 1463 bool agc_table_en; 1464 bool adc_back_off_on; 1465 bool b2_ant_hid_en; 1466 bool low_penalty_rate_adaptive; 1467 bool rf_rx_lpf_shrink; 1468 bool reject_aggre_pkt; 1469 bool tra_tdma_on; 1470 u8 tra_tdma_nav; 1471 u8 tra_tdma_ant; 1472 bool tdma_on; 1473 u8 tdma_ant; 1474 u8 tdma_nav; 1475 u8 tdma_dac_swing; 1476 u8 fw_dac_swing_lvl; 1477 bool ps_tdma_on; 1478 u8 ps_tdma_byte[5]; 1479 bool pta_on; 1480 u32 val_0x6c0; 1481 u32 val_0x6c8; 1482 u32 val_0x6cc; 1483 bool sw_dac_swing_on; 1484 u32 sw_dac_swing_lvl; 1485 u32 wlan_act_hi; 1486 u32 wlan_act_lo; 1487 u32 bt_retry_index; 1488 bool dec_bt_pwr; 1489 bool ignore_wlan_act; 1490 }; 1491 1492 struct bt_coexist_8723 { 1493 u32 high_priority_tx; 1494 u32 high_priority_rx; 1495 u32 low_priority_tx; 1496 u32 low_priority_rx; 1497 u8 c2h_bt_info; 1498 bool c2h_bt_info_req_sent; 1499 bool c2h_bt_inquiry_page; 1500 u32 bt_inq_page_start_time; 1501 u8 bt_retry_cnt; 1502 u8 c2h_bt_info_original; 1503 u8 bt_inquiry_page_cnt; 1504 struct btdm_8723 btdm; 1505 }; 1506 1507 struct rtl_hal { 1508 struct ieee80211_hw *hw; 1509 bool driver_is_goingto_unload; 1510 bool up_first_time; 1511 bool first_init; 1512 bool being_init_adapter; 1513 bool bbrf_ready; 1514 bool mac_func_enable; 1515 bool pre_edcca_enable; 1516 struct bt_coexist_8723 hal_coex_8723; 1517 1518 enum intf_type interface; 1519 u16 hw_type; /*92c or 92d or 92s and so on */ 1520 u8 ic_class; 1521 u8 oem_id; 1522 u32 version; /*version of chip */ 1523 u8 state; /*stop 0, start 1 */ 1524 u8 board_type; 1525 u8 package_type; 1526 u8 external_pa; 1527 1528 u8 pa_mode; 1529 u8 pa_type_2g; 1530 u8 pa_type_5g; 1531 u8 lna_type_2g; 1532 u8 lna_type_5g; 1533 u8 external_pa_2g; 1534 u8 external_lna_2g; 1535 u8 external_pa_5g; 1536 u8 external_lna_5g; 1537 u8 type_glna; 1538 u8 type_gpa; 1539 u8 type_alna; 1540 u8 type_apa; 1541 u8 rfe_type; 1542 1543 /*firmware */ 1544 u32 fwsize; 1545 u8 *pfirmware; 1546 u16 fw_version; 1547 u16 fw_subversion; 1548 bool h2c_setinprogress; 1549 u8 last_hmeboxnum; 1550 bool fw_ready; 1551 /*Reserve page start offset except beacon in TxQ. */ 1552 u8 fw_rsvdpage_startoffset; 1553 u8 h2c_txcmd_seq; 1554 u8 current_ra_rate; 1555 1556 /* FW Cmd IO related */ 1557 u16 fwcmd_iomap; 1558 u32 fwcmd_ioparam; 1559 bool set_fwcmd_inprogress; 1560 u8 current_fwcmd_io; 1561 1562 struct p2p_ps_offload_t p2p_ps_offload; 1563 bool fw_clk_change_in_progress; 1564 bool allow_sw_to_change_hwclc; 1565 u8 fw_ps_state; 1566 /**/ 1567 bool driver_going2unload; 1568 1569 /*AMPDU init min space*/ 1570 u8 minspace_cfg; /*For Min spacing configurations */ 1571 1572 /* Dual mac */ 1573 enum macphy_mode macphymode; 1574 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1575 enum band_type current_bandtypebackup; 1576 enum band_type bandset; 1577 /* dual MAC 0--Mac0 1--Mac1 */ 1578 u32 interfaceindex; 1579 /* just for DualMac S3S4 */ 1580 u8 macphyctl_reg; 1581 bool earlymode_enable; 1582 u8 max_earlymode_num; 1583 /* Dual mac*/ 1584 bool during_mac0init_radiob; 1585 bool during_mac1init_radioa; 1586 bool reloadtxpowerindex; 1587 /* True if IMR or IQK have done 1588 for 2.4G in scan progress */ 1589 bool load_imrandiqk_setting_for2g; 1590 1591 bool disable_amsdu_8k; 1592 bool master_of_dmsp; 1593 bool slave_of_dmsp; 1594 1595 u16 rx_tag;/*for 92ee*/ 1596 u8 rts_en; 1597 1598 /*for wowlan*/ 1599 bool wow_enable; 1600 bool enter_pnp_sleep; 1601 bool wake_from_pnp_sleep; 1602 bool wow_enabled; 1603 __kernel_time_t last_suspend_sec; 1604 u32 wowlan_fwsize; 1605 u8 *wowlan_firmware; 1606 1607 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1608 1609 bool real_wow_v2_enable; 1610 bool re_init_llt_table; 1611 }; 1612 1613 struct rtl_security { 1614 /*default 0 */ 1615 bool use_sw_sec; 1616 1617 bool being_setkey; 1618 bool use_defaultkey; 1619 /*Encryption Algorithm for Unicast Packet */ 1620 enum rt_enc_alg pairwise_enc_algorithm; 1621 /*Encryption Algorithm for Brocast/Multicast */ 1622 enum rt_enc_alg group_enc_algorithm; 1623 /*Cam Entry Bitmap */ 1624 u32 hwsec_cam_bitmap; 1625 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1626 /*local Key buffer, indx 0 is for 1627 pairwise key 1-4 is for agoup key. */ 1628 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1629 u8 key_len[KEY_BUF_SIZE]; 1630 1631 /*The pointer of Pairwise Key, 1632 it always points to KeyBuf[4] */ 1633 u8 *pairwise_key; 1634 }; 1635 1636 #define ASSOCIATE_ENTRY_NUM 33 1637 1638 struct fast_ant_training { 1639 u8 bssid[6]; 1640 u8 antsel_rx_keep_0; 1641 u8 antsel_rx_keep_1; 1642 u8 antsel_rx_keep_2; 1643 u32 ant_sum[7]; 1644 u32 ant_cnt[7]; 1645 u32 ant_ave[7]; 1646 u8 fat_state; 1647 u32 train_idx; 1648 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1649 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1650 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1651 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1652 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1653 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1654 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1655 u8 rx_idle_ant; 1656 bool becomelinked; 1657 }; 1658 1659 struct dm_phy_dbg_info { 1660 s8 rx_snrdb[4]; 1661 u64 num_qry_phy_status; 1662 u64 num_qry_phy_status_cck; 1663 u64 num_qry_phy_status_ofdm; 1664 u16 num_qry_beacon_pkt; 1665 u16 num_non_be_pkt; 1666 s32 rx_evm[4]; 1667 }; 1668 1669 struct rtl_dm { 1670 /*PHY status for Dynamic Management */ 1671 long entry_min_undec_sm_pwdb; 1672 long undec_sm_cck; 1673 long undec_sm_pwdb; /*out dm */ 1674 long entry_max_undec_sm_pwdb; 1675 s32 ofdm_pkt_cnt; 1676 bool dm_initialgain_enable; 1677 bool dynamic_txpower_enable; 1678 bool current_turbo_edca; 1679 bool is_any_nonbepkts; /*out dm */ 1680 bool is_cur_rdlstate; 1681 bool txpower_trackinginit; 1682 bool disable_framebursting; 1683 bool cck_inch14; 1684 bool txpower_tracking; 1685 bool useramask; 1686 bool rfpath_rxenable[4]; 1687 bool inform_fw_driverctrldm; 1688 bool current_mrc_switch; 1689 u8 txpowercount; 1690 u8 powerindex_backup[6]; 1691 1692 u8 thermalvalue_rxgain; 1693 u8 thermalvalue_iqk; 1694 u8 thermalvalue_lck; 1695 u8 thermalvalue; 1696 u8 last_dtp_lvl; 1697 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1698 u8 thermalvalue_avg_index; 1699 u8 tm_trigger; 1700 bool done_txpower; 1701 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1702 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1703 u8 dm_flag_tmp; 1704 u8 dm_type; 1705 u8 dm_rssi_sel; 1706 u8 txpower_track_control; 1707 bool interrupt_migration; 1708 bool disable_tx_int; 1709 s8 ofdm_index[MAX_RF_PATH]; 1710 u8 default_ofdm_index; 1711 u8 default_cck_index; 1712 s8 cck_index; 1713 s8 delta_power_index[MAX_RF_PATH]; 1714 s8 delta_power_index_last[MAX_RF_PATH]; 1715 s8 power_index_offset[MAX_RF_PATH]; 1716 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 1717 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 1718 s8 remnant_cck_idx; 1719 bool modify_txagc_flag_path_a; 1720 bool modify_txagc_flag_path_b; 1721 1722 bool one_entry_only; 1723 struct dm_phy_dbg_info dbginfo; 1724 1725 /* Dynamic ATC switch */ 1726 bool atc_status; 1727 bool large_cfo_hit; 1728 bool is_freeze; 1729 int cfo_tail[2]; 1730 int cfo_ave_pre; 1731 int crystal_cap; 1732 u8 cfo_threshold; 1733 u32 packet_count; 1734 u32 packet_count_pre; 1735 u8 tx_rate; 1736 1737 /*88e tx power tracking*/ 1738 u8 swing_idx_ofdm[MAX_RF_PATH]; 1739 u8 swing_idx_ofdm_cur; 1740 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1741 bool swing_flag_ofdm; 1742 u8 swing_idx_cck; 1743 u8 swing_idx_cck_cur; 1744 u8 swing_idx_cck_base; 1745 bool swing_flag_cck; 1746 1747 s8 swing_diff_2g; 1748 s8 swing_diff_5g; 1749 1750 /* DMSP */ 1751 bool supp_phymode_switch; 1752 1753 /* DulMac */ 1754 struct fast_ant_training fat_table; 1755 1756 u8 resp_tx_path; 1757 u8 path_sel; 1758 u32 patha_sum; 1759 u32 pathb_sum; 1760 u32 patha_cnt; 1761 u32 pathb_cnt; 1762 1763 u8 pre_channel; 1764 u8 *p_channel; 1765 u8 linked_interval; 1766 1767 u64 last_tx_ok_cnt; 1768 u64 last_rx_ok_cnt; 1769 }; 1770 1771 #define EFUSE_MAX_LOGICAL_SIZE 512 1772 1773 struct rtl_efuse { 1774 bool autoLoad_ok; 1775 bool bootfromefuse; 1776 u16 max_physical_size; 1777 1778 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1779 u16 efuse_usedbytes; 1780 u8 efuse_usedpercentage; 1781 #ifdef EFUSE_REPG_WORKAROUND 1782 bool efuse_re_pg_sec1flag; 1783 u8 efuse_re_pg_data[8]; 1784 #endif 1785 1786 u8 autoload_failflag; 1787 u8 autoload_status; 1788 1789 short epromtype; 1790 u16 eeprom_vid; 1791 u16 eeprom_did; 1792 u16 eeprom_svid; 1793 u16 eeprom_smid; 1794 u8 eeprom_oemid; 1795 u16 eeprom_channelplan; 1796 u8 eeprom_version; 1797 u8 board_type; 1798 u8 external_pa; 1799 1800 u8 dev_addr[6]; 1801 u8 wowlan_enable; 1802 u8 antenna_div_cfg; 1803 u8 antenna_div_type; 1804 1805 bool txpwr_fromeprom; 1806 u8 eeprom_crystalcap; 1807 u8 eeprom_tssi[2]; 1808 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1809 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1810 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1811 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1812 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1813 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1814 1815 u8 internal_pa_5g[2]; /* pathA / pathB */ 1816 u8 eeprom_c9; 1817 u8 eeprom_cc; 1818 1819 /*For power group */ 1820 u8 eeprom_pwrgroup[2][3]; 1821 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1822 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1823 1824 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1825 /*For HT 40MHZ pwr */ 1826 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1827 /*For HT 40MHZ pwr */ 1828 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1829 1830 /*--------------------------------------------------------* 1831 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1832 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1833 * define new arrays in Windows code. 1834 * BUT, in linux code, we use the same array for all ICs. 1835 * 1836 * The Correspondance relation between two arrays is: 1837 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1838 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1839 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1840 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1841 * 1842 * Sizes of these arrays are decided by the larger ones. 1843 */ 1844 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1845 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1846 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1847 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1848 1849 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1850 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1851 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1852 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1853 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1854 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1855 1856 u8 txpwr_safetyflag; /* Band edge enable flag */ 1857 u16 eeprom_txpowerdiff; 1858 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1859 u8 antenna_txpwdiff[3]; 1860 1861 u8 eeprom_regulatory; 1862 u8 eeprom_thermalmeter; 1863 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1864 u16 tssi_13dbm; 1865 u8 crystalcap; /* CrystalCap. */ 1866 u8 delta_iqk; 1867 u8 delta_lck; 1868 1869 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1870 bool apk_thermalmeterignore; 1871 1872 bool b1x1_recvcombine; 1873 bool b1ss_support; 1874 1875 /*channel plan */ 1876 u8 channel_plan; 1877 }; 1878 1879 struct rtl_tx_report { 1880 atomic_t sn; 1881 u16 last_sent_sn; 1882 unsigned long last_sent_time; 1883 u16 last_recv_sn; 1884 }; 1885 1886 struct rtl_ps_ctl { 1887 bool pwrdomain_protect; 1888 bool in_powersavemode; 1889 bool rfchange_inprogress; 1890 bool swrf_processing; 1891 bool hwradiooff; 1892 /* 1893 * just for PCIE ASPM 1894 * If it supports ASPM, Offset[560h] = 0x40, 1895 * otherwise Offset[560h] = 0x00. 1896 * */ 1897 bool support_aspm; 1898 bool support_backdoor; 1899 1900 /*for LPS */ 1901 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1902 bool swctrl_lps; 1903 bool leisure_ps; 1904 bool fwctrl_lps; 1905 u8 fwctrl_psmode; 1906 /*For Fw control LPS mode */ 1907 u8 reg_fwctrl_lps; 1908 /*Record Fw PS mode status. */ 1909 bool fw_current_inpsmode; 1910 u8 reg_max_lps_awakeintvl; 1911 bool report_linked; 1912 bool low_power_enable;/*for 32k*/ 1913 1914 /*for IPS */ 1915 bool inactiveps; 1916 1917 u32 rfoff_reason; 1918 1919 /*RF OFF Level */ 1920 u32 cur_ps_level; 1921 u32 reg_rfps_level; 1922 1923 /*just for PCIE ASPM */ 1924 u8 const_amdpci_aspm; 1925 bool pwrdown_mode; 1926 1927 enum rf_pwrstate inactive_pwrstate; 1928 enum rf_pwrstate rfpwr_state; /*cur power state */ 1929 1930 /* for SW LPS*/ 1931 bool sw_ps_enabled; 1932 bool state; 1933 bool state_inap; 1934 bool multi_buffered; 1935 u16 nullfunc_seq; 1936 unsigned int dtim_counter; 1937 unsigned int sleep_ms; 1938 unsigned long last_sleep_jiffies; 1939 unsigned long last_awake_jiffies; 1940 unsigned long last_delaylps_stamp_jiffies; 1941 unsigned long last_dtim; 1942 unsigned long last_beacon; 1943 unsigned long last_action; 1944 unsigned long last_slept; 1945 1946 /*For P2P PS */ 1947 struct rtl_p2p_ps_info p2p_ps_info; 1948 u8 pwr_mode; 1949 u8 smart_ps; 1950 1951 /* wake up on line */ 1952 u8 wo_wlan_mode; 1953 u8 arp_offload_enable; 1954 u8 gtk_offload_enable; 1955 /* Used for WOL, indicates the reason for waking event.*/ 1956 u32 wakeup_reason; 1957 /* Record the last waking time for comparison with setting key. */ 1958 u64 last_wakeup_time; 1959 }; 1960 1961 struct rtl_stats { 1962 u8 psaddr[ETH_ALEN]; 1963 u32 mac_time[2]; 1964 s8 rssi; 1965 u8 signal; 1966 u8 noise; 1967 u8 rate; /* hw desc rate */ 1968 u8 received_channel; 1969 u8 control; 1970 u8 mask; 1971 u8 freq; 1972 u16 len; 1973 u64 tsf; 1974 u32 beacon_time; 1975 u8 nic_type; 1976 u16 length; 1977 u8 signalquality; /*in 0-100 index. */ 1978 /* 1979 * Real power in dBm for this packet, 1980 * no beautification and aggregation. 1981 * */ 1982 s32 recvsignalpower; 1983 s8 rxpower; /*in dBm Translate from PWdB */ 1984 u8 signalstrength; /*in 0-100 index. */ 1985 u16 hwerror:1; 1986 u16 crc:1; 1987 u16 icv:1; 1988 u16 shortpreamble:1; 1989 u16 antenna:1; 1990 u16 decrypted:1; 1991 u16 wakeup:1; 1992 u32 timestamp_low; 1993 u32 timestamp_high; 1994 bool shift; 1995 1996 u8 rx_drvinfo_size; 1997 u8 rx_bufshift; 1998 bool isampdu; 1999 bool isfirst_ampdu; 2000 bool rx_is40Mhzpacket; 2001 u8 rx_packet_bw; 2002 u32 rx_pwdb_all; 2003 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2004 s8 rx_mimo_signalquality[4]; 2005 u8 rx_mimo_evm_dbm[4]; 2006 u16 cfo_short[4]; /* per-path's Cfo_short */ 2007 u16 cfo_tail[4]; 2008 2009 s8 rx_mimo_sig_qual[4]; 2010 u8 rx_pwr[4]; /* per-path's pwdb */ 2011 u8 rx_snr[4]; /* per-path's SNR */ 2012 u8 bandwidth; 2013 u8 bt_coex_pwr_adjust; 2014 bool packet_matchbssid; 2015 bool is_cck; 2016 bool is_ht; 2017 bool packet_toself; 2018 bool packet_beacon; /*for rssi */ 2019 s8 cck_adc_pwdb[4]; /*for rx path selection */ 2020 2021 bool is_vht; 2022 bool is_short_gi; 2023 u8 vht_nss; 2024 2025 u8 packet_report_type; 2026 2027 u32 macid; 2028 u8 wake_match; 2029 u32 bt_rx_rssi_percentage; 2030 u32 macid_valid_entry[2]; 2031 }; 2032 2033 2034 struct rt_link_detect { 2035 /* count for roaming */ 2036 u32 bcn_rx_inperiod; 2037 u32 roam_times; 2038 2039 u32 num_tx_in4period[4]; 2040 u32 num_rx_in4period[4]; 2041 2042 u32 num_tx_inperiod; 2043 u32 num_rx_inperiod; 2044 2045 bool busytraffic; 2046 bool tx_busy_traffic; 2047 bool rx_busy_traffic; 2048 bool higher_busytraffic; 2049 bool higher_busyrxtraffic; 2050 2051 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2052 u32 tidtx_inperiod[MAX_TID_COUNT]; 2053 bool higher_busytxtraffic[MAX_TID_COUNT]; 2054 }; 2055 2056 struct rtl_tcb_desc { 2057 u8 packet_bw:2; 2058 u8 multicast:1; 2059 u8 broadcast:1; 2060 2061 u8 rts_stbc:1; 2062 u8 rts_enable:1; 2063 u8 cts_enable:1; 2064 u8 rts_use_shortpreamble:1; 2065 u8 rts_use_shortgi:1; 2066 u8 rts_sc:1; 2067 u8 rts_bw:1; 2068 u8 rts_rate; 2069 2070 u8 use_shortgi:1; 2071 u8 use_shortpreamble:1; 2072 u8 use_driver_rate:1; 2073 u8 disable_ratefallback:1; 2074 2075 u8 use_spe_rpt:1; 2076 2077 u8 ratr_index; 2078 u8 mac_id; 2079 u8 hw_rate; 2080 2081 u8 last_inipkt:1; 2082 u8 cmd_or_init:1; 2083 u8 queue_index; 2084 2085 /* early mode */ 2086 u8 empkt_num; 2087 /* The max value by HW */ 2088 u32 empkt_len[10]; 2089 bool tx_enable_sw_calc_duration; 2090 }; 2091 2092 struct rtl_wow_pattern { 2093 u8 type; 2094 u16 crc; 2095 u32 mask[4]; 2096 }; 2097 2098 struct rtl_hal_ops { 2099 int (*init_sw_vars) (struct ieee80211_hw *hw); 2100 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2101 void (*read_chip_version)(struct ieee80211_hw *hw); 2102 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2103 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2104 u32 *p_inta, u32 *p_intb); 2105 int (*hw_init) (struct ieee80211_hw *hw); 2106 void (*hw_disable) (struct ieee80211_hw *hw); 2107 void (*hw_suspend) (struct ieee80211_hw *hw); 2108 void (*hw_resume) (struct ieee80211_hw *hw); 2109 void (*enable_interrupt) (struct ieee80211_hw *hw); 2110 void (*disable_interrupt) (struct ieee80211_hw *hw); 2111 int (*set_network_type) (struct ieee80211_hw *hw, 2112 enum nl80211_iftype type); 2113 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2114 bool check_bssid); 2115 void (*set_bw_mode) (struct ieee80211_hw *hw, 2116 enum nl80211_channel_type ch_type); 2117 u8(*switch_channel) (struct ieee80211_hw *hw); 2118 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2119 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2120 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2121 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2122 u32 add_msr, u32 rm_msr); 2123 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2124 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2125 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2126 struct ieee80211_sta *sta, u8 rssi_leve, 2127 bool update_bw); 2128 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2129 u8 *desc, u8 queue_index, 2130 struct sk_buff *skb, dma_addr_t addr); 2131 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2132 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2133 u8 queue_index); 2134 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2135 u8 queue_index); 2136 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2137 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2138 u8 *pbd_desc_tx, 2139 struct ieee80211_tx_info *info, 2140 struct ieee80211_sta *sta, 2141 struct sk_buff *skb, u8 hw_queue, 2142 struct rtl_tcb_desc *ptcb_desc); 2143 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2144 u32 buffer_len, bool bIsPsPoll); 2145 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2146 bool firstseg, bool lastseg, 2147 struct sk_buff *skb); 2148 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2149 struct rtl_stats *stats, 2150 struct ieee80211_rx_status *rx_status, 2151 u8 *pdesc, struct sk_buff *skb); 2152 void (*set_channel_access) (struct ieee80211_hw *hw); 2153 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2154 void (*dm_watchdog) (struct ieee80211_hw *hw); 2155 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2156 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2157 enum rf_pwrstate rfpwr_state); 2158 void (*led_control) (struct ieee80211_hw *hw, 2159 enum led_ctl_mode ledaction); 2160 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2161 u8 desc_name, u8 *val); 2162 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2163 u8 desc_name); 2164 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2165 u8 hw_queue, u16 index); 2166 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2167 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2168 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2169 u8 *macaddr, bool is_group, u8 enc_algo, 2170 bool is_wepkey, bool clear_all); 2171 void (*init_sw_leds) (struct ieee80211_hw *hw); 2172 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2173 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2174 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2175 u32 data); 2176 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2177 u32 regaddr, u32 bitmask); 2178 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2179 u32 regaddr, u32 bitmask, u32 data); 2180 void (*linked_set_reg) (struct ieee80211_hw *hw); 2181 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2182 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2183 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2184 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2185 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2186 u8 *powerlevel); 2187 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2188 u8 *ppowerlevel, u8 channel); 2189 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2190 u8 configtype); 2191 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2192 u8 configtype); 2193 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2194 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2195 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2196 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2197 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2198 bool mstate); 2199 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2200 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2201 u32 cmd_len, u8 *p_cmdbuffer); 2202 bool (*get_btc_status) (void); 2203 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2204 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2205 const struct rtl_stats *status, struct sk_buff *skb); 2206 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2207 struct rtl_wow_pattern *rtl_pattern, 2208 u8 index); 2209 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2210 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len, 2211 u8 *val); 2212 }; 2213 2214 struct rtl_intf_ops { 2215 /*com */ 2216 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2217 int (*adapter_start) (struct ieee80211_hw *hw); 2218 void (*adapter_stop) (struct ieee80211_hw *hw); 2219 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2220 struct rtl_priv **buddy_priv); 2221 2222 int (*adapter_tx) (struct ieee80211_hw *hw, 2223 struct ieee80211_sta *sta, 2224 struct sk_buff *skb, 2225 struct rtl_tcb_desc *ptcb_desc); 2226 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2227 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2228 bool (*waitq_insert) (struct ieee80211_hw *hw, 2229 struct ieee80211_sta *sta, 2230 struct sk_buff *skb); 2231 2232 /*pci */ 2233 void (*disable_aspm) (struct ieee80211_hw *hw); 2234 void (*enable_aspm) (struct ieee80211_hw *hw); 2235 2236 /*usb */ 2237 }; 2238 2239 struct rtl_mod_params { 2240 /* default: 0,0 */ 2241 u64 debug_mask; 2242 /* default: 0 = using hardware encryption */ 2243 bool sw_crypto; 2244 2245 /* default: 0 = DBG_EMERG (0)*/ 2246 int debug_level; 2247 2248 /* default: 1 = using no linked power save */ 2249 bool inactiveps; 2250 2251 /* default: 1 = using linked sw power save */ 2252 bool swctrl_lps; 2253 2254 /* default: 1 = using linked fw power save */ 2255 bool fwctrl_lps; 2256 2257 /* default: 0 = not using MSI interrupts mode 2258 * submodules should set their own default value 2259 */ 2260 bool msi_support; 2261 2262 /* default: 0 = dma 32 */ 2263 bool dma64; 2264 2265 /* default: 1 = enable aspm */ 2266 int aspm_support; 2267 2268 /* default 0: 1 means disable */ 2269 bool disable_watchdog; 2270 2271 /* default 0: 1 means do not disable interrupts */ 2272 bool int_clear; 2273 2274 /* select antenna */ 2275 int ant_sel; 2276 }; 2277 2278 struct rtl_hal_usbint_cfg { 2279 /* data - rx */ 2280 u32 in_ep_num; 2281 u32 rx_urb_num; 2282 u32 rx_max_size; 2283 2284 /* op - rx */ 2285 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2286 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2287 struct sk_buff_head *); 2288 2289 /* tx */ 2290 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2291 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2292 struct sk_buff *); 2293 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2294 struct sk_buff_head *); 2295 2296 /* endpoint mapping */ 2297 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2298 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2299 }; 2300 2301 struct rtl_hal_cfg { 2302 u8 bar_id; 2303 bool write_readback; 2304 char *name; 2305 char *alt_fw_name; 2306 struct rtl_hal_ops *ops; 2307 struct rtl_mod_params *mod_params; 2308 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2309 2310 /*this map used for some registers or vars 2311 defined int HAL but used in MAIN */ 2312 u32 maps[RTL_VAR_MAP_MAX]; 2313 2314 }; 2315 2316 struct rtl_locks { 2317 /* mutex */ 2318 struct mutex conf_mutex; 2319 struct mutex ps_mutex; 2320 2321 /*spin lock */ 2322 spinlock_t ips_lock; 2323 spinlock_t irq_th_lock; 2324 spinlock_t irq_pci_lock; 2325 spinlock_t tx_lock; 2326 spinlock_t h2c_lock; 2327 spinlock_t rf_ps_lock; 2328 spinlock_t rf_lock; 2329 spinlock_t lps_lock; 2330 spinlock_t waitq_lock; 2331 spinlock_t entry_list_lock; 2332 spinlock_t usb_lock; 2333 spinlock_t c2hcmd_lock; 2334 spinlock_t scan_list_lock; /* lock for the scan list */ 2335 2336 /*FW clock change */ 2337 spinlock_t fw_ps_lock; 2338 2339 /*Dual mac*/ 2340 spinlock_t cck_and_rw_pagea_lock; 2341 2342 /*Easy concurrent*/ 2343 spinlock_t check_sendpkt_lock; 2344 2345 spinlock_t iqk_lock; 2346 }; 2347 2348 struct rtl_works { 2349 struct ieee80211_hw *hw; 2350 2351 /*timer */ 2352 struct timer_list watchdog_timer; 2353 struct timer_list dualmac_easyconcurrent_retrytimer; 2354 struct timer_list fw_clockoff_timer; 2355 struct timer_list fast_antenna_training_timer; 2356 /*task */ 2357 struct tasklet_struct irq_tasklet; 2358 struct tasklet_struct irq_prepare_bcn_tasklet; 2359 2360 /*work queue */ 2361 struct workqueue_struct *rtl_wq; 2362 struct delayed_work watchdog_wq; 2363 struct delayed_work ips_nic_off_wq; 2364 struct delayed_work c2hcmd_wq; 2365 2366 /* For SW LPS */ 2367 struct delayed_work ps_work; 2368 struct delayed_work ps_rfon_wq; 2369 struct delayed_work fwevt_wq; 2370 2371 struct work_struct lps_change_work; 2372 struct work_struct fill_h2c_cmd; 2373 }; 2374 2375 #define MIMO_PS_STATIC 0 2376 #define MIMO_PS_DYNAMIC 1 2377 #define MIMO_PS_NOLIMIT 3 2378 2379 struct rtl_dualmac_easy_concurrent_ctl { 2380 enum band_type currentbandtype_backfordmdp; 2381 bool close_bbandrf_for_dmsp; 2382 bool change_to_dmdp; 2383 bool change_to_dmsp; 2384 bool switch_in_process; 2385 }; 2386 2387 struct rtl_dmsp_ctl { 2388 bool activescan_for_slaveofdmsp; 2389 bool scan_for_anothermac_fordmsp; 2390 bool scan_for_itself_fordmsp; 2391 bool writedig_for_anothermacofdmsp; 2392 u32 curdigvalue_for_anothermacofdmsp; 2393 bool changecckpdstate_for_anothermacofdmsp; 2394 u8 curcckpdstate_for_anothermacofdmsp; 2395 bool changetxhighpowerlvl_for_anothermacofdmsp; 2396 u8 curtxhighlvl_for_anothermacofdmsp; 2397 long rssivalmin_for_anothermacofdmsp; 2398 }; 2399 2400 struct ps_t { 2401 u8 pre_ccastate; 2402 u8 cur_ccasate; 2403 u8 pre_rfstate; 2404 u8 cur_rfstate; 2405 u8 initialize; 2406 long rssi_val_min; 2407 }; 2408 2409 struct dig_t { 2410 u32 rssi_lowthresh; 2411 u32 rssi_highthresh; 2412 u32 fa_lowthresh; 2413 u32 fa_highthresh; 2414 long last_min_undec_pwdb_for_dm; 2415 long rssi_highpower_lowthresh; 2416 long rssi_highpower_highthresh; 2417 u32 recover_cnt; 2418 u32 pre_igvalue; 2419 u32 cur_igvalue; 2420 long rssi_val; 2421 u8 dig_enable_flag; 2422 u8 dig_ext_port_stage; 2423 u8 dig_algorithm; 2424 u8 dig_twoport_algorithm; 2425 u8 dig_dbgmode; 2426 u8 dig_slgorithm_switch; 2427 u8 cursta_cstate; 2428 u8 presta_cstate; 2429 u8 curmultista_cstate; 2430 u8 stop_dig; 2431 s8 back_val; 2432 s8 back_range_max; 2433 s8 back_range_min; 2434 u8 rx_gain_max; 2435 u8 rx_gain_min; 2436 u8 min_undec_pwdb_for_dm; 2437 u8 rssi_val_min; 2438 u8 pre_cck_cca_thres; 2439 u8 cur_cck_cca_thres; 2440 u8 pre_cck_pd_state; 2441 u8 cur_cck_pd_state; 2442 u8 pre_cck_fa_state; 2443 u8 cur_cck_fa_state; 2444 u8 pre_ccastate; 2445 u8 cur_ccasate; 2446 u8 large_fa_hit; 2447 u8 forbidden_igi; 2448 u8 dig_state; 2449 u8 dig_highpwrstate; 2450 u8 cur_sta_cstate; 2451 u8 pre_sta_cstate; 2452 u8 cur_ap_cstate; 2453 u8 pre_ap_cstate; 2454 u8 cur_pd_thstate; 2455 u8 pre_pd_thstate; 2456 u8 cur_cs_ratiostate; 2457 u8 pre_cs_ratiostate; 2458 u8 backoff_enable_flag; 2459 s8 backoffval_range_max; 2460 s8 backoffval_range_min; 2461 u8 dig_min_0; 2462 u8 dig_min_1; 2463 u8 bt30_cur_igi; 2464 bool media_connect_0; 2465 bool media_connect_1; 2466 2467 u32 antdiv_rssi_max; 2468 u32 rssi_max; 2469 }; 2470 2471 struct rtl_global_var { 2472 /* from this list we can get 2473 * other adapter's rtl_priv */ 2474 struct list_head glb_priv_list; 2475 spinlock_t glb_list_lock; 2476 }; 2477 2478 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */ 2479 2480 struct rtl_btc_info { 2481 u8 bt_type; 2482 u8 btcoexist; 2483 u8 ant_num; 2484 u8 single_ant_path; 2485 2486 u8 ap_num; 2487 bool in_4way; 2488 unsigned long in_4way_ts; 2489 }; 2490 2491 struct bt_coexist_info { 2492 struct rtl_btc_ops *btc_ops; 2493 struct rtl_btc_info btc_info; 2494 /* EEPROM BT info. */ 2495 u8 eeprom_bt_coexist; 2496 u8 eeprom_bt_type; 2497 u8 eeprom_bt_ant_num; 2498 u8 eeprom_bt_ant_isol; 2499 u8 eeprom_bt_radio_shared; 2500 2501 u8 bt_coexistence; 2502 u8 bt_ant_num; 2503 u8 bt_coexist_type; 2504 u8 bt_state; 2505 u8 bt_cur_state; /* 0:on, 1:off */ 2506 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2507 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2508 u8 bt_service; 2509 u8 bt_radio_shared_type; 2510 u8 bt_rfreg_origin_1e; 2511 u8 bt_rfreg_origin_1f; 2512 u8 bt_rssi_state; 2513 u32 ratio_tx; 2514 u32 ratio_pri; 2515 u32 bt_edca_ul; 2516 u32 bt_edca_dl; 2517 2518 bool init_set; 2519 bool bt_busy_traffic; 2520 bool bt_traffic_mode_set; 2521 bool bt_non_traffic_mode_set; 2522 2523 bool fw_coexist_all_off; 2524 bool sw_coexist_all_off; 2525 bool hw_coexist_all_off; 2526 u32 cstate; 2527 u32 previous_state; 2528 u32 cstate_h; 2529 u32 previous_state_h; 2530 2531 u8 bt_pre_rssi_state; 2532 u8 bt_pre_rssi_state1; 2533 2534 u8 reg_bt_iso; 2535 u8 reg_bt_sco; 2536 bool balance_on; 2537 u8 bt_active_zero_cnt; 2538 bool cur_bt_disabled; 2539 bool pre_bt_disabled; 2540 2541 u8 bt_profile_case; 2542 u8 bt_profile_action; 2543 bool bt_busy; 2544 bool hold_for_bt_operation; 2545 u8 lps_counter; 2546 }; 2547 2548 struct rtl_btc_ops { 2549 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2550 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2551 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2552 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2553 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2554 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2555 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2556 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2557 enum rt_media_status mstatus); 2558 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2559 void (*btc_halt_notify) (void); 2560 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2561 u8 *tmp_buf, u8 length); 2562 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv, 2563 u8 *tmp_buf, u8 length); 2564 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2565 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2566 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2567 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2568 u8 pkt_type); 2569 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len); 2570 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv); 2571 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv); 2572 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv); 2573 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg, 2574 u8 *ctrl_agg_size, u8 *agg_size); 2575 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv); 2576 }; 2577 2578 struct proxim { 2579 bool proxim_on; 2580 2581 void *proximity_priv; 2582 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2583 struct sk_buff *skb); 2584 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2585 }; 2586 2587 struct rtl_c2hcmd { 2588 struct list_head list; 2589 u8 tag; 2590 u8 len; 2591 u8 *val; 2592 }; 2593 2594 struct rtl_bssid_entry { 2595 struct list_head list; 2596 u8 bssid[ETH_ALEN]; 2597 u32 age; 2598 }; 2599 2600 struct rtl_scan_list { 2601 int num; 2602 struct list_head list; /* sort by age */ 2603 }; 2604 2605 struct rtl_priv { 2606 struct ieee80211_hw *hw; 2607 struct completion firmware_loading_complete; 2608 struct list_head list; 2609 struct rtl_priv *buddy_priv; 2610 struct rtl_global_var *glb_var; 2611 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2612 struct rtl_dmsp_ctl dmsp_ctl; 2613 struct rtl_locks locks; 2614 struct rtl_works works; 2615 struct rtl_mac mac80211; 2616 struct rtl_hal rtlhal; 2617 struct rtl_regulatory regd; 2618 struct rtl_rfkill rfkill; 2619 struct rtl_io io; 2620 struct rtl_phy phy; 2621 struct rtl_dm dm; 2622 struct rtl_security sec; 2623 struct rtl_efuse efuse; 2624 struct rtl_led_ctl ledctl; 2625 struct rtl_tx_report tx_report; 2626 struct rtl_scan_list scan_list; 2627 2628 struct rtl_ps_ctl psc; 2629 struct rate_adaptive ra; 2630 struct dynamic_primary_cca primarycca; 2631 struct wireless_stats stats; 2632 struct rt_link_detect link_info; 2633 struct false_alarm_statistics falsealm_cnt; 2634 2635 struct rtl_rate_priv *rate_priv; 2636 2637 /* sta entry list for ap adhoc or mesh */ 2638 struct list_head entry_list; 2639 2640 /* c2hcmd list for kthread level access */ 2641 struct list_head c2hcmd_list; 2642 2643 int max_fw_size; 2644 2645 /* 2646 *hal_cfg : for diff cards 2647 *intf_ops : for diff interrface usb/pcie 2648 */ 2649 struct rtl_hal_cfg *cfg; 2650 const struct rtl_intf_ops *intf_ops; 2651 2652 /*this var will be set by set_bit, 2653 and was used to indicate status of 2654 interface or hardware */ 2655 unsigned long status; 2656 2657 /* tables for dm */ 2658 struct dig_t dm_digtable; 2659 struct ps_t dm_pstable; 2660 2661 u32 reg_874; 2662 u32 reg_c70; 2663 u32 reg_85c; 2664 u32 reg_a74; 2665 bool reg_init; /* true if regs saved */ 2666 bool bt_operation_on; 2667 __le32 *usb_data; 2668 int usb_data_index; 2669 bool initialized; 2670 bool enter_ps; /* true when entering PS */ 2671 u8 rate_mask[5]; 2672 2673 /* intel Proximity, should be alloc mem 2674 * in intel Proximity module and can only 2675 * be used in intel Proximity mode 2676 */ 2677 struct proxim proximity; 2678 2679 /*for bt coexist use*/ 2680 struct bt_coexist_info btcoexist; 2681 2682 /* separate 92ee from other ICs, 2683 * 92ee use new trx flow. 2684 */ 2685 bool use_new_trx_flow; 2686 2687 #ifdef CONFIG_PM 2688 struct wiphy_wowlan_support wowlan; 2689 #endif 2690 /*This must be the last item so 2691 that it points to the data allocated 2692 beyond this structure like: 2693 rtl_pci_priv or rtl_usb_priv */ 2694 u8 priv[0] __aligned(sizeof(void *)); 2695 }; 2696 2697 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2698 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2699 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2700 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2701 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2702 2703 2704 /*************************************** 2705 Bluetooth Co-existence Related 2706 ****************************************/ 2707 2708 enum bt_ant_num { 2709 ANT_X2 = 0, 2710 ANT_X1 = 1, 2711 }; 2712 2713 enum bt_co_type { 2714 BT_2WIRE = 0, 2715 BT_ISSC_3WIRE = 1, 2716 BT_ACCEL = 2, 2717 BT_CSR_BC4 = 3, 2718 BT_CSR_BC8 = 4, 2719 BT_RTL8756 = 5, 2720 BT_RTL8723A = 6, 2721 BT_RTL8821A = 7, 2722 BT_RTL8723B = 8, 2723 BT_RTL8192E = 9, 2724 BT_RTL8812A = 11, 2725 }; 2726 2727 enum bt_total_ant_num { 2728 ANT_TOTAL_X2 = 0, 2729 ANT_TOTAL_X1 = 1 2730 }; 2731 2732 enum bt_cur_state { 2733 BT_OFF = 0, 2734 BT_ON = 1, 2735 }; 2736 2737 enum bt_service_type { 2738 BT_SCO = 0, 2739 BT_A2DP = 1, 2740 BT_HID = 2, 2741 BT_HID_IDLE = 3, 2742 BT_SCAN = 4, 2743 BT_IDLE = 5, 2744 BT_OTHER_ACTION = 6, 2745 BT_BUSY = 7, 2746 BT_OTHERBUSY = 8, 2747 BT_PAN = 9, 2748 }; 2749 2750 enum bt_radio_shared { 2751 BT_RADIO_SHARED = 0, 2752 BT_RADIO_INDIVIDUAL = 1, 2753 }; 2754 2755 2756 /**************************************** 2757 mem access macro define start 2758 Call endian free function when 2759 1. Read/write packet content. 2760 2. Before write integer to IO. 2761 3. After read integer from IO. 2762 ****************************************/ 2763 /* Convert little data endian to host ordering */ 2764 #define EF1BYTE(_val) \ 2765 ((u8)(_val)) 2766 #define EF2BYTE(_val) \ 2767 (le16_to_cpu(_val)) 2768 #define EF4BYTE(_val) \ 2769 (le32_to_cpu(_val)) 2770 2771 /* Read data from memory */ 2772 #define READEF1BYTE(_ptr) \ 2773 EF1BYTE(*((u8 *)(_ptr))) 2774 /* Read le16 data from memory and convert to host ordering */ 2775 #define READEF2BYTE(_ptr) \ 2776 EF2BYTE(*(_ptr)) 2777 #define READEF4BYTE(_ptr) \ 2778 EF4BYTE(*(_ptr)) 2779 2780 /* Create a bit mask 2781 * Examples: 2782 * BIT_LEN_MASK_32(0) => 0x00000000 2783 * BIT_LEN_MASK_32(1) => 0x00000001 2784 * BIT_LEN_MASK_32(2) => 0x00000003 2785 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2786 */ 2787 #define BIT_LEN_MASK_32(__bitlen) \ 2788 (0xFFFFFFFF >> (32 - (__bitlen))) 2789 #define BIT_LEN_MASK_16(__bitlen) \ 2790 (0xFFFF >> (16 - (__bitlen))) 2791 #define BIT_LEN_MASK_8(__bitlen) \ 2792 (0xFF >> (8 - (__bitlen))) 2793 2794 /* Create an offset bit mask 2795 * Examples: 2796 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2797 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2798 */ 2799 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2800 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2801 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2802 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2803 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2804 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2805 2806 /*Description: 2807 * Return 4-byte value in host byte ordering from 2808 * 4-byte pointer in little-endian system. 2809 */ 2810 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2811 (EF4BYTE(*((__le32 *)(__pstart)))) 2812 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2813 (EF2BYTE(*((__le16 *)(__pstart)))) 2814 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2815 (EF1BYTE(*((u8 *)(__pstart)))) 2816 2817 /*Description: 2818 Translate subfield (continuous bits in little-endian) of 4-byte 2819 value to host byte ordering.*/ 2820 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2821 ( \ 2822 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2823 BIT_LEN_MASK_32(__bitlen) \ 2824 ) 2825 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2826 ( \ 2827 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2828 BIT_LEN_MASK_16(__bitlen) \ 2829 ) 2830 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2831 ( \ 2832 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2833 BIT_LEN_MASK_8(__bitlen) \ 2834 ) 2835 2836 /* Description: 2837 * Mask subfield (continuous bits in little-endian) of 4-byte value 2838 * and return the result in 4-byte value in host byte ordering. 2839 */ 2840 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2841 ( \ 2842 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2843 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2844 ) 2845 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2846 ( \ 2847 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2848 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2849 ) 2850 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2851 ( \ 2852 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2853 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2854 ) 2855 2856 /* Description: 2857 * Set subfield of little-endian 4-byte value to specified value. 2858 */ 2859 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2860 *((__le32 *)(__pstart)) = \ 2861 cpu_to_le32( \ 2862 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 2863 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 2864 ) 2865 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2866 *((__le16 *)(__pstart)) = \ 2867 cpu_to_le16( \ 2868 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 2869 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 2870 ) 2871 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2872 *((u8 *)(__pstart)) = EF1BYTE \ 2873 ( \ 2874 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 2875 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 2876 ) 2877 2878 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 2879 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 2880 2881 /**************************************** 2882 mem access macro define end 2883 ****************************************/ 2884 2885 #define byte(x, n) ((x >> (8 * n)) & 0xff) 2886 2887 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 2888 #define RTL_WATCH_DOG_TIME 2000 2889 #define MSECS(t) msecs_to_jiffies(t) 2890 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 2891 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 2892 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 2893 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 2894 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 2895 2896 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 2897 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 2898 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 2899 /*NIC halt, re-initialize hw parameters*/ 2900 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 2901 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 2902 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 2903 /*Always enable ASPM and Clock Req in initialization.*/ 2904 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 2905 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 2906 #define RT_PS_LEVEL_ASPM BIT(7) 2907 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 2908 #define RT_RF_LPS_DISALBE_2R BIT(30) 2909 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 2910 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 2911 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 2912 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 2913 (ppsc->cur_ps_level &= (~(_ps_flg))) 2914 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 2915 (ppsc->cur_ps_level |= _ps_flg) 2916 2917 #define container_of_dwork_rtl(x, y, z) \ 2918 container_of(to_delayed_work(x), y, z) 2919 2920 #define FILL_OCTET_STRING(_os, _octet, _len) \ 2921 (_os).octet = (u8 *)(_octet); \ 2922 (_os).length = (_len); 2923 2924 #define CP_MACADDR(des, src) \ 2925 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 2926 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 2927 (des)[4] = (src)[4], (des)[5] = (src)[5]) 2928 2929 #define LDPC_HT_ENABLE_RX BIT(0) 2930 #define LDPC_HT_ENABLE_TX BIT(1) 2931 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 2932 #define LDPC_HT_CAP_TX BIT(3) 2933 2934 #define STBC_HT_ENABLE_RX BIT(0) 2935 #define STBC_HT_ENABLE_TX BIT(1) 2936 #define STBC_HT_TEST_TX_ENABLE BIT(2) 2937 #define STBC_HT_CAP_TX BIT(3) 2938 2939 #define LDPC_VHT_ENABLE_RX BIT(0) 2940 #define LDPC_VHT_ENABLE_TX BIT(1) 2941 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 2942 #define LDPC_VHT_CAP_TX BIT(3) 2943 2944 #define STBC_VHT_ENABLE_RX BIT(0) 2945 #define STBC_VHT_ENABLE_TX BIT(1) 2946 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 2947 #define STBC_VHT_CAP_TX BIT(3) 2948 2949 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G]; 2950 2951 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M]; 2952 2953 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 2954 { 2955 return rtlpriv->io.read8_sync(rtlpriv, addr); 2956 } 2957 2958 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 2959 { 2960 return rtlpriv->io.read16_sync(rtlpriv, addr); 2961 } 2962 2963 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 2964 { 2965 return rtlpriv->io.read32_sync(rtlpriv, addr); 2966 } 2967 2968 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 2969 { 2970 rtlpriv->io.write8_async(rtlpriv, addr, val8); 2971 2972 if (rtlpriv->cfg->write_readback) 2973 rtlpriv->io.read8_sync(rtlpriv, addr); 2974 } 2975 2976 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw, 2977 u32 addr, u32 val8) 2978 { 2979 struct rtl_priv *rtlpriv = rtl_priv(hw); 2980 2981 rtl_write_byte(rtlpriv, addr, (u8)val8); 2982 } 2983 2984 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 2985 { 2986 rtlpriv->io.write16_async(rtlpriv, addr, val16); 2987 2988 if (rtlpriv->cfg->write_readback) 2989 rtlpriv->io.read16_sync(rtlpriv, addr); 2990 } 2991 2992 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 2993 u32 addr, u32 val32) 2994 { 2995 rtlpriv->io.write32_async(rtlpriv, addr, val32); 2996 2997 if (rtlpriv->cfg->write_readback) 2998 rtlpriv->io.read32_sync(rtlpriv, addr); 2999 } 3000 3001 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 3002 u32 regaddr, u32 bitmask) 3003 { 3004 struct rtl_priv *rtlpriv = hw->priv; 3005 3006 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 3007 } 3008 3009 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 3010 u32 bitmask, u32 data) 3011 { 3012 struct rtl_priv *rtlpriv = hw->priv; 3013 3014 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 3015 } 3016 3017 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw, 3018 u32 regaddr, u32 data) 3019 { 3020 rtl_set_bbreg(hw, regaddr, 0xffffffff, data); 3021 } 3022 3023 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 3024 enum radio_path rfpath, u32 regaddr, 3025 u32 bitmask) 3026 { 3027 struct rtl_priv *rtlpriv = hw->priv; 3028 3029 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 3030 } 3031 3032 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 3033 enum radio_path rfpath, u32 regaddr, 3034 u32 bitmask, u32 data) 3035 { 3036 struct rtl_priv *rtlpriv = hw->priv; 3037 3038 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 3039 } 3040 3041 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 3042 { 3043 return (_HAL_STATE_STOP == rtlhal->state); 3044 } 3045 3046 static inline void set_hal_start(struct rtl_hal *rtlhal) 3047 { 3048 rtlhal->state = _HAL_STATE_START; 3049 } 3050 3051 static inline void set_hal_stop(struct rtl_hal *rtlhal) 3052 { 3053 rtlhal->state = _HAL_STATE_STOP; 3054 } 3055 3056 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 3057 { 3058 return rtlphy->rf_type; 3059 } 3060 3061 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3062 { 3063 return (struct ieee80211_hdr *)(skb->data); 3064 } 3065 3066 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3067 { 3068 return rtl_get_hdr(skb)->frame_control; 3069 } 3070 3071 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3072 { 3073 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3074 } 3075 3076 static inline u16 rtl_get_tid(struct sk_buff *skb) 3077 { 3078 return rtl_get_tid_h(rtl_get_hdr(skb)); 3079 } 3080 3081 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3082 struct ieee80211_vif *vif, 3083 const u8 *bssid) 3084 { 3085 return ieee80211_find_sta(vif, bssid); 3086 } 3087 3088 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3089 u8 *mac_addr) 3090 { 3091 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3092 return ieee80211_find_sta(mac->vif, mac_addr); 3093 } 3094 3095 #endif 3096