1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_WIFI_H__ 27 #define __RTL_WIFI_H__ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sched.h> 32 #include <linux/firmware.h> 33 #include <linux/etherdevice.h> 34 #include <linux/vmalloc.h> 35 #include <linux/usb.h> 36 #include <net/mac80211.h> 37 #include <linux/completion.h> 38 #include "debug.h" 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKHWORD 0xffff0000 45 #define MASKLWORD 0x0000ffff 46 #define MASKDWORD 0xffffffff 47 #define MASK12BITS 0xfff 48 #define MASKH4BITS 0xf0000000 49 #define MASKOFDM_D 0xffc00000 50 #define MASKCCK 0x3f3f3f3f 51 52 #define MASK4BITS 0x0f 53 #define MASK20BITS 0xfffff 54 #define RFREG_OFFSET_MASK 0xfffff 55 56 #define MASKBYTE0 0xff 57 #define MASKBYTE1 0xff00 58 #define MASKBYTE2 0xff0000 59 #define MASKBYTE3 0xff000000 60 #define MASKHWORD 0xffff0000 61 #define MASKLWORD 0x0000ffff 62 #define MASKDWORD 0xffffffff 63 #define MASK12BITS 0xfff 64 #define MASKH4BITS 0xf0000000 65 #define MASKOFDM_D 0xffc00000 66 #define MASKCCK 0x3f3f3f3f 67 68 #define MASK4BITS 0x0f 69 #define MASK20BITS 0xfffff 70 #define RFREG_OFFSET_MASK 0xfffff 71 72 #define RF_CHANGE_BY_INIT 0 73 #define RF_CHANGE_BY_IPS BIT(28) 74 #define RF_CHANGE_BY_PS BIT(29) 75 #define RF_CHANGE_BY_HW BIT(30) 76 #define RF_CHANGE_BY_SW BIT(31) 77 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_MAC_REG_NUM 4 80 #define IQK_THRESHOLD 8 81 82 #define MAX_KEY_LEN 61 83 #define KEY_BUF_SIZE 5 84 85 /* QoS related. */ 86 /*aci: 0x00 Best Effort*/ 87 /*aci: 0x01 Background*/ 88 /*aci: 0x10 Video*/ 89 /*aci: 0x11 Voice*/ 90 /*Max: define total number.*/ 91 #define AC0_BE 0 92 #define AC1_BK 1 93 #define AC2_VI 2 94 #define AC3_VO 3 95 #define AC_MAX 4 96 #define QOS_QUEUE_NUM 4 97 #define RTL_MAC80211_NUM_QUEUE 5 98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99 #define RTL_USB_MAX_RX_COUNT 100 100 #define QBSS_LOAD_SIZE 5 101 #define MAX_WMMELE_LENGTH 64 102 103 #define TOTAL_CAM_ENTRY 32 104 105 /*slot time for 11g. */ 106 #define RTL_SLOT_TIME_9 9 107 #define RTL_SLOT_TIME_20 20 108 109 /*related to tcp/ip. */ 110 #define SNAP_SIZE 6 111 #define PROTOC_TYPE_SIZE 2 112 113 /*related with 802.11 frame*/ 114 #define MAC80211_3ADDR_LEN 24 115 #define MAC80211_4ADDR_LEN 30 116 117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 118 #define CHANNEL_MAX_NUMBER_2G 14 119 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to 120 *"phy_GetChnlGroup8812A" and 121 * "Hal_ReadTxPowerInfo8812A" 122 */ 123 #define CHANNEL_MAX_NUMBER_5G_80M 7 124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 125 #define MAX_PG_GROUP 13 126 #define CHANNEL_GROUP_MAX_2G 3 127 #define CHANNEL_GROUP_IDX_5GL 3 128 #define CHANNEL_GROUP_IDX_5GM 6 129 #define CHANNEL_GROUP_IDX_5GH 9 130 #define CHANNEL_GROUP_MAX_5G 9 131 #define CHANNEL_MAX_NUMBER_2G 14 132 #define AVG_THERMAL_NUM 8 133 #define AVG_THERMAL_NUM_88E 4 134 #define AVG_THERMAL_NUM_8723BE 4 135 #define MAX_TID_COUNT 9 136 137 /* for early mode */ 138 #define FCS_LEN 4 139 #define EM_HDR_LEN 8 140 141 enum rtl8192c_h2c_cmd { 142 H2C_AP_OFFLOAD = 0, 143 H2C_SETPWRMODE = 1, 144 H2C_JOINBSSRPT = 2, 145 H2C_RSVDPAGE = 3, 146 H2C_RSSI_REPORT = 5, 147 H2C_RA_MASK = 6, 148 H2C_MACID_PS_MODE = 7, 149 H2C_P2P_PS_OFFLOAD = 8, 150 H2C_MAC_MODE_SEL = 9, 151 H2C_PWRM = 15, 152 H2C_P2P_PS_CTW_CMD = 24, 153 MAX_H2CCMD 154 }; 155 156 #define MAX_TX_COUNT 4 157 #define MAX_REGULATION_NUM 4 158 #define MAX_RF_PATH_NUM 4 159 #define MAX_RATE_SECTION_NUM 6 160 #define MAX_2_4G_BANDWIDTH_NUM 4 161 #define MAX_5G_BANDWIDTH_NUM 4 162 #define MAX_RF_PATH 4 163 #define MAX_CHNL_GROUP_24G 6 164 #define MAX_CHNL_GROUP_5G 14 165 166 #define TX_PWR_BY_RATE_NUM_BAND 2 167 #define TX_PWR_BY_RATE_NUM_RF 4 168 #define TX_PWR_BY_RATE_NUM_SECTION 12 169 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 170 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 171 172 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 173 174 #define DEL_SW_IDX_SZ 30 175 176 /* For now, it's just for 8192ee 177 * but not OK yet, keep it 0 178 */ 179 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM 180 181 enum rf_tx_num { 182 RF_1TX = 0, 183 RF_2TX, 184 RF_MAX_TX_NUM, 185 RF_TX_NUM_NONIMPLEMENT, 186 }; 187 188 #define PACKET_NORMAL 0 189 #define PACKET_DHCP 1 190 #define PACKET_ARP 2 191 #define PACKET_EAPOL 3 192 193 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 194 #define RSVD_WOL_PATTERN_NUM 1 195 #define WKFMCAM_ADDR_NUM 6 196 #define WKFMCAM_SIZE 24 197 198 #define MAX_WOL_BIT_MASK_SIZE 16 199 /* MIN LEN keeps 13 here */ 200 #define MIN_WOL_PATTERN_SIZE 13 201 #define MAX_WOL_PATTERN_SIZE 128 202 203 #define WAKE_ON_MAGIC_PACKET BIT(0) 204 #define WAKE_ON_PATTERN_MATCH BIT(1) 205 206 #define WOL_REASON_PTK_UPDATE BIT(0) 207 #define WOL_REASON_GTK_UPDATE BIT(1) 208 #define WOL_REASON_DISASSOC BIT(2) 209 #define WOL_REASON_DEAUTH BIT(3) 210 #define WOL_REASON_AP_LOST BIT(4) 211 #define WOL_REASON_MAGIC_PKT BIT(5) 212 #define WOL_REASON_UNICAST_PKT BIT(6) 213 #define WOL_REASON_PATTERN_PKT BIT(7) 214 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 215 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 216 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 217 218 struct rtlwifi_firmware_header { 219 __le16 signature; 220 u8 category; 221 u8 function; 222 __le16 version; 223 u8 subversion; 224 u8 rsvd1; 225 u8 month; 226 u8 date; 227 u8 hour; 228 u8 minute; 229 __le16 ramcodeSize; 230 __le16 rsvd2; 231 __le32 svnindex; 232 __le32 rsvd3; 233 __le32 rsvd4; 234 __le32 rsvd5; 235 }; 236 237 struct txpower_info_2g { 238 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 239 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 240 /*If only one tx, only BW20 and OFDM are used.*/ 241 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 242 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 243 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 244 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 245 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 246 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 247 }; 248 249 struct txpower_info_5g { 250 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 251 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 252 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 253 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 254 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 255 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 256 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 257 }; 258 259 enum rate_section { 260 CCK = 0, 261 OFDM, 262 HT_MCS0_MCS7, 263 HT_MCS8_MCS15, 264 VHT_1SSMCS0_1SSMCS9, 265 VHT_2SSMCS0_2SSMCS9, 266 }; 267 268 enum intf_type { 269 INTF_PCI = 0, 270 INTF_USB = 1, 271 }; 272 273 enum radio_path { 274 RF90_PATH_A = 0, 275 RF90_PATH_B = 1, 276 RF90_PATH_C = 2, 277 RF90_PATH_D = 3, 278 }; 279 280 enum regulation_txpwr_lmt { 281 TXPWR_LMT_FCC = 0, 282 TXPWR_LMT_MKK = 1, 283 TXPWR_LMT_ETSI = 2, 284 TXPWR_LMT_WW = 3, 285 286 TXPWR_LMT_MAX_REGULATION_NUM = 4 287 }; 288 289 enum rt_eeprom_type { 290 EEPROM_93C46, 291 EEPROM_93C56, 292 EEPROM_BOOT_EFUSE, 293 }; 294 295 enum ttl_status { 296 RTL_STATUS_INTERFACE_START = 0, 297 }; 298 299 enum hardware_type { 300 HARDWARE_TYPE_RTL8192E, 301 HARDWARE_TYPE_RTL8192U, 302 HARDWARE_TYPE_RTL8192SE, 303 HARDWARE_TYPE_RTL8192SU, 304 HARDWARE_TYPE_RTL8192CE, 305 HARDWARE_TYPE_RTL8192CU, 306 HARDWARE_TYPE_RTL8192DE, 307 HARDWARE_TYPE_RTL8192DU, 308 HARDWARE_TYPE_RTL8723AE, 309 HARDWARE_TYPE_RTL8723U, 310 HARDWARE_TYPE_RTL8188EE, 311 HARDWARE_TYPE_RTL8723BE, 312 HARDWARE_TYPE_RTL8192EE, 313 HARDWARE_TYPE_RTL8821AE, 314 HARDWARE_TYPE_RTL8812AE, 315 HARDWARE_TYPE_RTL8822BE, 316 317 /* keep it last */ 318 HARDWARE_TYPE_NUM 319 }; 320 321 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type) 322 #define IS_NEW_GENERATION_IC(rtlpriv) \ 323 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE) 324 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \ 325 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE) 326 #define IS_HARDWARE_TYPE_8812(rtlpriv) \ 327 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE) 328 #define IS_HARDWARE_TYPE_8821(rtlpriv) \ 329 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE) 330 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \ 331 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE) 332 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \ 333 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE) 334 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \ 335 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE) 336 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \ 337 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE) 338 339 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 340 ((rxmcs) == DESC_RATE1M || \ 341 (rxmcs) == DESC_RATE2M || \ 342 (rxmcs) == DESC_RATE5_5M || \ 343 (rxmcs) == DESC_RATE11M) 344 345 enum scan_operation_backup_opt { 346 SCAN_OPT_BACKUP = 0, 347 SCAN_OPT_BACKUP_BAND0 = 0, 348 SCAN_OPT_BACKUP_BAND1, 349 SCAN_OPT_RESTORE, 350 SCAN_OPT_MAX 351 }; 352 353 /*RF state.*/ 354 enum rf_pwrstate { 355 ERFON, 356 ERFSLEEP, 357 ERFOFF 358 }; 359 360 struct bb_reg_def { 361 u32 rfintfs; 362 u32 rfintfi; 363 u32 rfintfo; 364 u32 rfintfe; 365 u32 rf3wire_offset; 366 u32 rflssi_select; 367 u32 rftxgain_stage; 368 u32 rfhssi_para1; 369 u32 rfhssi_para2; 370 u32 rfsw_ctrl; 371 u32 rfagc_control1; 372 u32 rfagc_control2; 373 u32 rfrxiq_imbal; 374 u32 rfrx_afe; 375 u32 rftxiq_imbal; 376 u32 rftx_afe; 377 u32 rf_rb; /* rflssi_readback */ 378 u32 rf_rbpi; /* rflssi_readbackpi */ 379 }; 380 381 enum io_type { 382 IO_CMD_PAUSE_DM_BY_SCAN = 0, 383 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 384 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 385 IO_CMD_RESUME_DM_BY_SCAN = 2, 386 }; 387 388 enum hw_variables { 389 HW_VAR_ETHER_ADDR = 0x0, 390 HW_VAR_MULTICAST_REG = 0x1, 391 HW_VAR_BASIC_RATE = 0x2, 392 HW_VAR_BSSID = 0x3, 393 HW_VAR_MEDIA_STATUS= 0x4, 394 HW_VAR_SECURITY_CONF= 0x5, 395 HW_VAR_BEACON_INTERVAL = 0x6, 396 HW_VAR_ATIM_WINDOW = 0x7, 397 HW_VAR_LISTEN_INTERVAL = 0x8, 398 HW_VAR_CS_COUNTER = 0x9, 399 HW_VAR_DEFAULTKEY0 = 0xa, 400 HW_VAR_DEFAULTKEY1 = 0xb, 401 HW_VAR_DEFAULTKEY2 = 0xc, 402 HW_VAR_DEFAULTKEY3 = 0xd, 403 HW_VAR_SIFS = 0xe, 404 HW_VAR_R2T_SIFS = 0xf, 405 HW_VAR_DIFS = 0x10, 406 HW_VAR_EIFS = 0x11, 407 HW_VAR_SLOT_TIME = 0x12, 408 HW_VAR_ACK_PREAMBLE = 0x13, 409 HW_VAR_CW_CONFIG = 0x14, 410 HW_VAR_CW_VALUES = 0x15, 411 HW_VAR_RATE_FALLBACK_CONTROL= 0x16, 412 HW_VAR_CONTENTION_WINDOW = 0x17, 413 HW_VAR_RETRY_COUNT = 0x18, 414 HW_VAR_TR_SWITCH = 0x19, 415 HW_VAR_COMMAND = 0x1a, 416 HW_VAR_WPA_CONFIG = 0x1b, 417 HW_VAR_AMPDU_MIN_SPACE = 0x1c, 418 HW_VAR_SHORTGI_DENSITY = 0x1d, 419 HW_VAR_AMPDU_FACTOR = 0x1e, 420 HW_VAR_MCS_RATE_AVAILABLE = 0x1f, 421 HW_VAR_AC_PARAM = 0x20, 422 HW_VAR_ACM_CTRL = 0x21, 423 HW_VAR_DIS_Req_Qsize = 0x22, 424 HW_VAR_CCX_CHNL_LOAD = 0x23, 425 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24, 426 HW_VAR_CCX_CLM_NHM = 0x25, 427 HW_VAR_TxOPLimit = 0x26, 428 HW_VAR_TURBO_MODE = 0x27, 429 HW_VAR_RF_STATE = 0x28, 430 HW_VAR_RF_OFF_BY_HW = 0x29, 431 HW_VAR_BUS_SPEED = 0x2a, 432 HW_VAR_SET_DEV_POWER = 0x2b, 433 434 HW_VAR_RCR = 0x2c, 435 HW_VAR_RATR_0 = 0x2d, 436 HW_VAR_RRSR = 0x2e, 437 HW_VAR_CPU_RST = 0x2f, 438 HW_VAR_CHECK_BSSID = 0x30, 439 HW_VAR_LBK_MODE = 0x31, 440 HW_VAR_AES_11N_FIX = 0x32, 441 HW_VAR_USB_RX_AGGR = 0x33, 442 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34, 443 HW_VAR_RETRY_LIMIT = 0x35, 444 HW_VAR_INIT_TX_RATE = 0x36, 445 HW_VAR_TX_RATE_REG = 0x37, 446 HW_VAR_EFUSE_USAGE = 0x38, 447 HW_VAR_EFUSE_BYTES = 0x39, 448 HW_VAR_AUTOLOAD_STATUS = 0x3a, 449 HW_VAR_RF_2R_DISABLE = 0x3b, 450 HW_VAR_SET_RPWM = 0x3c, 451 HW_VAR_H2C_FW_PWRMODE = 0x3d, 452 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e, 453 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f, 454 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40, 455 HW_VAR_FW_PSMODE_STATUS = 0x41, 456 HW_VAR_INIT_RTS_RATE = 0x42, 457 HW_VAR_RESUME_CLK_ON = 0x43, 458 HW_VAR_FW_LPS_ACTION = 0x44, 459 HW_VAR_1X1_RECV_COMBINE = 0x45, 460 HW_VAR_STOP_SEND_BEACON = 0x46, 461 HW_VAR_TSF_TIMER = 0x47, 462 HW_VAR_IO_CMD = 0x48, 463 464 HW_VAR_RF_RECOVERY = 0x49, 465 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a, 466 HW_VAR_WF_MASK = 0x4b, 467 HW_VAR_WF_CRC = 0x4c, 468 HW_VAR_WF_IS_MAC_ADDR = 0x4d, 469 HW_VAR_H2C_FW_OFFLOAD = 0x4e, 470 HW_VAR_RESET_WFCRC = 0x4f, 471 472 HW_VAR_HANDLE_FW_C2H = 0x50, 473 HW_VAR_DL_FW_RSVD_PAGE = 0x51, 474 HW_VAR_AID = 0x52, 475 HW_VAR_HW_SEQ_ENABLE = 0x53, 476 HW_VAR_CORRECT_TSF = 0x54, 477 HW_VAR_BCN_VALID = 0x55, 478 HW_VAR_FWLPS_RF_ON = 0x56, 479 HW_VAR_DUAL_TSF_RST = 0x57, 480 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58, 481 HW_VAR_INT_MIGRATION = 0x59, 482 HW_VAR_INT_AC = 0x5a, 483 HW_VAR_RF_TIMING = 0x5b, 484 485 HAL_DEF_WOWLAN = 0x5c, 486 HW_VAR_MRC = 0x5d, 487 HW_VAR_KEEP_ALIVE = 0x5e, 488 HW_VAR_NAV_UPPER = 0x5f, 489 490 HW_VAR_MGT_FILTER = 0x60, 491 HW_VAR_CTRL_FILTER = 0x61, 492 HW_VAR_DATA_FILTER = 0x62, 493 }; 494 495 enum rt_media_status { 496 RT_MEDIA_DISCONNECT = 0, 497 RT_MEDIA_CONNECT = 1 498 }; 499 500 enum rt_oem_id { 501 RT_CID_DEFAULT = 0, 502 RT_CID_8187_ALPHA0 = 1, 503 RT_CID_8187_SERCOMM_PS = 2, 504 RT_CID_8187_HW_LED = 3, 505 RT_CID_8187_NETGEAR = 4, 506 RT_CID_WHQL = 5, 507 RT_CID_819X_CAMEO = 6, 508 RT_CID_819X_RUNTOP = 7, 509 RT_CID_819X_SENAO = 8, 510 RT_CID_TOSHIBA = 9, 511 RT_CID_819X_NETCORE = 10, 512 RT_CID_NETTRONIX = 11, 513 RT_CID_DLINK = 12, 514 RT_CID_PRONET = 13, 515 RT_CID_COREGA = 14, 516 RT_CID_819X_ALPHA = 15, 517 RT_CID_819X_SITECOM = 16, 518 RT_CID_CCX = 17, 519 RT_CID_819X_LENOVO = 18, 520 RT_CID_819X_QMI = 19, 521 RT_CID_819X_EDIMAX_BELKIN = 20, 522 RT_CID_819X_SERCOMM_BELKIN = 21, 523 RT_CID_819X_CAMEO1 = 22, 524 RT_CID_819X_MSI = 23, 525 RT_CID_819X_ACER = 24, 526 RT_CID_819X_HP = 27, 527 RT_CID_819X_CLEVO = 28, 528 RT_CID_819X_ARCADYAN_BELKIN = 29, 529 RT_CID_819X_SAMSUNG = 30, 530 RT_CID_819X_WNC_COREGA = 31, 531 RT_CID_819X_FOXCOON = 32, 532 RT_CID_819X_DELL = 33, 533 RT_CID_819X_PRONETS = 34, 534 RT_CID_819X_EDIMAX_ASUS = 35, 535 RT_CID_NETGEAR = 36, 536 RT_CID_PLANEX = 37, 537 RT_CID_CC_C = 38, 538 }; 539 540 enum hw_descs { 541 HW_DESC_OWN, 542 HW_DESC_RXOWN, 543 HW_DESC_TX_NEXTDESC_ADDR, 544 HW_DESC_TXBUFF_ADDR, 545 HW_DESC_RXBUFF_ADDR, 546 HW_DESC_RXPKT_LEN, 547 HW_DESC_RXERO, 548 HW_DESC_RX_PREPARE, 549 }; 550 551 enum prime_sc { 552 PRIME_CHNL_OFFSET_DONT_CARE = 0, 553 PRIME_CHNL_OFFSET_LOWER = 1, 554 PRIME_CHNL_OFFSET_UPPER = 2, 555 }; 556 557 enum rf_type { 558 RF_1T1R = 0, 559 RF_1T2R = 1, 560 RF_2T2R = 2, 561 RF_2T2R_GREEN = 3, 562 RF_2T3R = 4, 563 RF_2T4R = 5, 564 RF_3T3R = 6, 565 RF_3T4R = 7, 566 RF_4T4R = 8, 567 }; 568 569 enum ht_channel_width { 570 HT_CHANNEL_WIDTH_20 = 0, 571 HT_CHANNEL_WIDTH_20_40 = 1, 572 HT_CHANNEL_WIDTH_80 = 2, 573 }; 574 575 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 576 Cipher Suites Encryption Algorithms */ 577 enum rt_enc_alg { 578 NO_ENCRYPTION = 0, 579 WEP40_ENCRYPTION = 1, 580 TKIP_ENCRYPTION = 2, 581 RSERVED_ENCRYPTION = 3, 582 AESCCMP_ENCRYPTION = 4, 583 WEP104_ENCRYPTION = 5, 584 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 585 }; 586 587 enum rtl_hal_state { 588 _HAL_STATE_STOP = 0, 589 _HAL_STATE_START = 1, 590 }; 591 592 enum rtl_desc_rate { 593 DESC_RATE1M = 0x00, 594 DESC_RATE2M = 0x01, 595 DESC_RATE5_5M = 0x02, 596 DESC_RATE11M = 0x03, 597 598 DESC_RATE6M = 0x04, 599 DESC_RATE9M = 0x05, 600 DESC_RATE12M = 0x06, 601 DESC_RATE18M = 0x07, 602 DESC_RATE24M = 0x08, 603 DESC_RATE36M = 0x09, 604 DESC_RATE48M = 0x0a, 605 DESC_RATE54M = 0x0b, 606 607 DESC_RATEMCS0 = 0x0c, 608 DESC_RATEMCS1 = 0x0d, 609 DESC_RATEMCS2 = 0x0e, 610 DESC_RATEMCS3 = 0x0f, 611 DESC_RATEMCS4 = 0x10, 612 DESC_RATEMCS5 = 0x11, 613 DESC_RATEMCS6 = 0x12, 614 DESC_RATEMCS7 = 0x13, 615 DESC_RATEMCS8 = 0x14, 616 DESC_RATEMCS9 = 0x15, 617 DESC_RATEMCS10 = 0x16, 618 DESC_RATEMCS11 = 0x17, 619 DESC_RATEMCS12 = 0x18, 620 DESC_RATEMCS13 = 0x19, 621 DESC_RATEMCS14 = 0x1a, 622 DESC_RATEMCS15 = 0x1b, 623 DESC_RATEMCS15_SG = 0x1c, 624 DESC_RATEMCS32 = 0x20, 625 626 DESC_RATEVHT1SS_MCS0 = 0x2c, 627 DESC_RATEVHT1SS_MCS1 = 0x2d, 628 DESC_RATEVHT1SS_MCS2 = 0x2e, 629 DESC_RATEVHT1SS_MCS3 = 0x2f, 630 DESC_RATEVHT1SS_MCS4 = 0x30, 631 DESC_RATEVHT1SS_MCS5 = 0x31, 632 DESC_RATEVHT1SS_MCS6 = 0x32, 633 DESC_RATEVHT1SS_MCS7 = 0x33, 634 DESC_RATEVHT1SS_MCS8 = 0x34, 635 DESC_RATEVHT1SS_MCS9 = 0x35, 636 DESC_RATEVHT2SS_MCS0 = 0x36, 637 DESC_RATEVHT2SS_MCS1 = 0x37, 638 DESC_RATEVHT2SS_MCS2 = 0x38, 639 DESC_RATEVHT2SS_MCS3 = 0x39, 640 DESC_RATEVHT2SS_MCS4 = 0x3a, 641 DESC_RATEVHT2SS_MCS5 = 0x3b, 642 DESC_RATEVHT2SS_MCS6 = 0x3c, 643 DESC_RATEVHT2SS_MCS7 = 0x3d, 644 DESC_RATEVHT2SS_MCS8 = 0x3e, 645 DESC_RATEVHT2SS_MCS9 = 0x3f, 646 }; 647 648 enum rtl_var_map { 649 /*reg map */ 650 SYS_ISO_CTRL = 0, 651 SYS_FUNC_EN, 652 SYS_CLK, 653 MAC_RCR_AM, 654 MAC_RCR_AB, 655 MAC_RCR_ACRC32, 656 MAC_RCR_ACF, 657 MAC_RCR_AAP, 658 MAC_HIMR, 659 MAC_HIMRE, 660 MAC_HSISR, 661 662 /*efuse map */ 663 EFUSE_TEST, 664 EFUSE_CTRL, 665 EFUSE_CLK, 666 EFUSE_CLK_CTRL, 667 EFUSE_PWC_EV12V, 668 EFUSE_FEN_ELDR, 669 EFUSE_LOADER_CLK_EN, 670 EFUSE_ANA8M, 671 EFUSE_HWSET_MAX_SIZE, 672 EFUSE_MAX_SECTION_MAP, 673 EFUSE_REAL_CONTENT_SIZE, 674 EFUSE_OOB_PROTECT_BYTES_LEN, 675 EFUSE_ACCESS, 676 677 /*CAM map */ 678 RWCAM, 679 WCAMI, 680 RCAMO, 681 CAMDBG, 682 SECR, 683 SEC_CAM_NONE, 684 SEC_CAM_WEP40, 685 SEC_CAM_TKIP, 686 SEC_CAM_AES, 687 SEC_CAM_WEP104, 688 689 /*IMR map */ 690 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 691 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 692 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 693 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 694 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 695 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 696 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 697 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 698 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 699 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 700 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 701 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 702 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 703 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 704 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 705 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 706 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 707 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 708 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 709 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 710 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 711 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 712 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */ 713 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 714 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 715 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 716 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 717 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 718 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 719 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 720 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 721 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 722 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 723 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 724 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 725 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 726 * RTL_IMR_TBDER) */ 727 RTL_IMR_C2HCMD, /*fw interrupt*/ 728 729 /*CCK Rates, TxHT = 0 */ 730 RTL_RC_CCK_RATE1M, 731 RTL_RC_CCK_RATE2M, 732 RTL_RC_CCK_RATE5_5M, 733 RTL_RC_CCK_RATE11M, 734 735 /*OFDM Rates, TxHT = 0 */ 736 RTL_RC_OFDM_RATE6M, 737 RTL_RC_OFDM_RATE9M, 738 RTL_RC_OFDM_RATE12M, 739 RTL_RC_OFDM_RATE18M, 740 RTL_RC_OFDM_RATE24M, 741 RTL_RC_OFDM_RATE36M, 742 RTL_RC_OFDM_RATE48M, 743 RTL_RC_OFDM_RATE54M, 744 745 RTL_RC_HT_RATEMCS7, 746 RTL_RC_HT_RATEMCS15, 747 748 RTL_RC_VHT_RATE_1SS_MCS7, 749 RTL_RC_VHT_RATE_1SS_MCS8, 750 RTL_RC_VHT_RATE_1SS_MCS9, 751 RTL_RC_VHT_RATE_2SS_MCS7, 752 RTL_RC_VHT_RATE_2SS_MCS8, 753 RTL_RC_VHT_RATE_2SS_MCS9, 754 755 /*keep it last */ 756 RTL_VAR_MAP_MAX, 757 }; 758 759 /*Firmware PS mode for control LPS.*/ 760 enum _fw_ps_mode { 761 FW_PS_ACTIVE_MODE = 0, 762 FW_PS_MIN_MODE = 1, 763 FW_PS_MAX_MODE = 2, 764 FW_PS_DTIM_MODE = 3, 765 FW_PS_VOIP_MODE = 4, 766 FW_PS_UAPSD_WMM_MODE = 5, 767 FW_PS_UAPSD_MODE = 6, 768 FW_PS_IBSS_MODE = 7, 769 FW_PS_WWLAN_MODE = 8, 770 FW_PS_PM_Radio_Off = 9, 771 FW_PS_PM_Card_Disable = 10, 772 }; 773 774 enum rt_psmode { 775 EACTIVE, /*Active/Continuous access. */ 776 EMAXPS, /*Max power save mode. */ 777 EFASTPS, /*Fast power save mode. */ 778 EAUTOPS, /*Auto power save mode. */ 779 }; 780 781 /*LED related.*/ 782 enum led_ctl_mode { 783 LED_CTL_POWER_ON = 1, 784 LED_CTL_LINK = 2, 785 LED_CTL_NO_LINK = 3, 786 LED_CTL_TX = 4, 787 LED_CTL_RX = 5, 788 LED_CTL_SITE_SURVEY = 6, 789 LED_CTL_POWER_OFF = 7, 790 LED_CTL_START_TO_LINK = 8, 791 LED_CTL_START_WPS = 9, 792 LED_CTL_STOP_WPS = 10, 793 }; 794 795 enum rtl_led_pin { 796 LED_PIN_GPIO0, 797 LED_PIN_LED0, 798 LED_PIN_LED1, 799 LED_PIN_LED2 800 }; 801 802 /*QoS related.*/ 803 /*acm implementation method.*/ 804 enum acm_method { 805 eAcmWay0_SwAndHw = 0, 806 eAcmWay1_HW = 1, 807 EACMWAY2_SW = 2, 808 }; 809 810 enum macphy_mode { 811 SINGLEMAC_SINGLEPHY = 0, 812 DUALMAC_DUALPHY, 813 DUALMAC_SINGLEPHY, 814 }; 815 816 enum band_type { 817 BAND_ON_2_4G = 0, 818 BAND_ON_5G, 819 BAND_ON_BOTH, 820 BANDMAX 821 }; 822 823 /*aci/aifsn Field. 824 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 825 union aci_aifsn { 826 u8 char_data; 827 828 struct { 829 u8 aifsn:4; 830 u8 acm:1; 831 u8 aci:2; 832 u8 reserved:1; 833 } f; /* Field */ 834 }; 835 836 /*mlme related.*/ 837 enum wireless_mode { 838 WIRELESS_MODE_UNKNOWN = 0x00, 839 WIRELESS_MODE_A = 0x01, 840 WIRELESS_MODE_B = 0x02, 841 WIRELESS_MODE_G = 0x04, 842 WIRELESS_MODE_AUTO = 0x08, 843 WIRELESS_MODE_N_24G = 0x10, 844 WIRELESS_MODE_N_5G = 0x20, 845 WIRELESS_MODE_AC_5G = 0x40, 846 WIRELESS_MODE_AC_24G = 0x80, 847 WIRELESS_MODE_AC_ONLY = 0x100, 848 WIRELESS_MODE_MAX = 0x800 849 }; 850 851 #define IS_WIRELESS_MODE_A(wirelessmode) \ 852 (wirelessmode == WIRELESS_MODE_A) 853 #define IS_WIRELESS_MODE_B(wirelessmode) \ 854 (wirelessmode == WIRELESS_MODE_B) 855 #define IS_WIRELESS_MODE_G(wirelessmode) \ 856 (wirelessmode == WIRELESS_MODE_G) 857 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 858 (wirelessmode == WIRELESS_MODE_N_24G) 859 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 860 (wirelessmode == WIRELESS_MODE_N_5G) 861 862 enum ratr_table_mode { 863 RATR_INX_WIRELESS_NGB = 0, 864 RATR_INX_WIRELESS_NG = 1, 865 RATR_INX_WIRELESS_NB = 2, 866 RATR_INX_WIRELESS_N = 3, 867 RATR_INX_WIRELESS_GB = 4, 868 RATR_INX_WIRELESS_G = 5, 869 RATR_INX_WIRELESS_B = 6, 870 RATR_INX_WIRELESS_MC = 7, 871 RATR_INX_WIRELESS_A = 8, 872 RATR_INX_WIRELESS_AC_5N = 8, 873 RATR_INX_WIRELESS_AC_24N = 9, 874 }; 875 876 enum ratr_table_mode_new { 877 RATEID_IDX_BGN_40M_2SS = 0, 878 RATEID_IDX_BGN_40M_1SS = 1, 879 RATEID_IDX_BGN_20M_2SS_BN = 2, 880 RATEID_IDX_BGN_20M_1SS_BN = 3, 881 RATEID_IDX_GN_N2SS = 4, 882 RATEID_IDX_GN_N1SS = 5, 883 RATEID_IDX_BG = 6, 884 RATEID_IDX_G = 7, 885 RATEID_IDX_B = 8, 886 RATEID_IDX_VHT_2SS = 9, 887 RATEID_IDX_VHT_1SS = 10, 888 RATEID_IDX_MIX1 = 11, 889 RATEID_IDX_MIX2 = 12, 890 RATEID_IDX_VHT_3SS = 13, 891 RATEID_IDX_BGN_3SS = 14, 892 }; 893 894 enum rtl_link_state { 895 MAC80211_NOLINK = 0, 896 MAC80211_LINKING = 1, 897 MAC80211_LINKED = 2, 898 MAC80211_LINKED_SCANNING = 3, 899 }; 900 901 enum act_category { 902 ACT_CAT_QOS = 1, 903 ACT_CAT_DLS = 2, 904 ACT_CAT_BA = 3, 905 ACT_CAT_HT = 7, 906 ACT_CAT_WMM = 17, 907 }; 908 909 enum ba_action { 910 ACT_ADDBAREQ = 0, 911 ACT_ADDBARSP = 1, 912 ACT_DELBA = 2, 913 }; 914 915 enum rt_polarity_ctl { 916 RT_POLARITY_LOW_ACT = 0, 917 RT_POLARITY_HIGH_ACT = 1, 918 }; 919 920 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 921 enum fw_wow_reason_v2 { 922 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 923 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 924 FW_WOW_V2_DISASSOC_EVENT = 0x04, 925 FW_WOW_V2_DEAUTH_EVENT = 0x08, 926 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 927 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 928 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 929 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 930 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 931 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 932 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 933 FW_WOW_V2_REASON_MAX = 0xff, 934 }; 935 936 enum wolpattern_type { 937 UNICAST_PATTERN = 0, 938 MULTICAST_PATTERN = 1, 939 BROADCAST_PATTERN = 2, 940 DONT_CARE_DA = 3, 941 UNKNOWN_TYPE = 4, 942 }; 943 944 enum package_type { 945 PACKAGE_DEFAULT, 946 PACKAGE_QFN68, 947 PACKAGE_TFBGA90, 948 PACKAGE_TFBGA80, 949 PACKAGE_TFBGA79 950 }; 951 952 enum rtl_spec_ver { 953 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */ 954 }; 955 956 struct octet_string { 957 u8 *octet; 958 u16 length; 959 }; 960 961 struct rtl_hdr_3addr { 962 __le16 frame_ctl; 963 __le16 duration_id; 964 u8 addr1[ETH_ALEN]; 965 u8 addr2[ETH_ALEN]; 966 u8 addr3[ETH_ALEN]; 967 __le16 seq_ctl; 968 u8 payload[0]; 969 } __packed; 970 971 struct rtl_info_element { 972 u8 id; 973 u8 len; 974 u8 data[0]; 975 } __packed; 976 977 struct rtl_probe_rsp { 978 struct rtl_hdr_3addr header; 979 u32 time_stamp[2]; 980 __le16 beacon_interval; 981 __le16 capability; 982 /*SSID, supported rates, FH params, DS params, 983 CF params, IBSS params, TIM (if beacon), RSN */ 984 struct rtl_info_element info_element[0]; 985 } __packed; 986 987 /*LED related.*/ 988 /*ledpin Identify how to implement this SW led.*/ 989 struct rtl_led { 990 void *hw; 991 enum rtl_led_pin ledpin; 992 bool ledon; 993 }; 994 995 struct rtl_led_ctl { 996 bool led_opendrain; 997 struct rtl_led sw_led0; 998 struct rtl_led sw_led1; 999 }; 1000 1001 struct rtl_qos_parameters { 1002 __le16 cw_min; 1003 __le16 cw_max; 1004 u8 aifs; 1005 u8 flag; 1006 __le16 tx_op; 1007 } __packed; 1008 1009 struct rt_smooth_data { 1010 u32 elements[100]; /*array to store values */ 1011 u32 index; /*index to current array to store */ 1012 u32 total_num; /*num of valid elements */ 1013 u32 total_val; /*sum of valid elements */ 1014 }; 1015 1016 struct false_alarm_statistics { 1017 u32 cnt_parity_fail; 1018 u32 cnt_rate_illegal; 1019 u32 cnt_crc8_fail; 1020 u32 cnt_mcs_fail; 1021 u32 cnt_fast_fsync_fail; 1022 u32 cnt_sb_search_fail; 1023 u32 cnt_ofdm_fail; 1024 u32 cnt_cck_fail; 1025 u32 cnt_all; 1026 u32 cnt_ofdm_cca; 1027 u32 cnt_cck_cca; 1028 u32 cnt_cca_all; 1029 u32 cnt_bw_usc; 1030 u32 cnt_bw_lsc; 1031 }; 1032 1033 struct init_gain { 1034 u8 xaagccore1; 1035 u8 xbagccore1; 1036 u8 xcagccore1; 1037 u8 xdagccore1; 1038 u8 cca; 1039 1040 }; 1041 1042 struct wireless_stats { 1043 u64 txbytesunicast; 1044 u64 txbytesmulticast; 1045 u64 txbytesbroadcast; 1046 u64 rxbytesunicast; 1047 1048 u64 txbytesunicast_inperiod; 1049 u64 rxbytesunicast_inperiod; 1050 u32 txbytesunicast_inperiod_tp; 1051 u32 rxbytesunicast_inperiod_tp; 1052 u64 txbytesunicast_last; 1053 u64 rxbytesunicast_last; 1054 1055 long rx_snr_db[4]; 1056 /*Correct smoothed ss in Dbm, only used 1057 in driver to report real power now. */ 1058 long recv_signal_power; 1059 long signal_quality; 1060 long last_sigstrength_inpercent; 1061 1062 u32 rssi_calculate_cnt; 1063 u32 pwdb_all_cnt; 1064 1065 /*Transformed, in dbm. Beautified signal 1066 strength for UI, not correct. */ 1067 long signal_strength; 1068 1069 u8 rx_rssi_percentage[4]; 1070 u8 rx_evm_dbm[4]; 1071 u8 rx_evm_percentage[2]; 1072 1073 u16 rx_cfo_short[4]; 1074 u16 rx_cfo_tail[4]; 1075 1076 struct rt_smooth_data ui_rssi; 1077 struct rt_smooth_data ui_link_quality; 1078 }; 1079 1080 struct rate_adaptive { 1081 u8 rate_adaptive_disabled; 1082 u8 ratr_state; 1083 u16 reserve; 1084 1085 u32 high_rssi_thresh_for_ra; 1086 u32 high2low_rssi_thresh_for_ra; 1087 u8 low2high_rssi_thresh_for_ra40m; 1088 u32 low_rssi_thresh_for_ra40m; 1089 u8 low2high_rssi_thresh_for_ra20m; 1090 u32 low_rssi_thresh_for_ra20m; 1091 u32 upper_rssi_threshold_ratr; 1092 u32 middleupper_rssi_threshold_ratr; 1093 u32 middle_rssi_threshold_ratr; 1094 u32 middlelow_rssi_threshold_ratr; 1095 u32 low_rssi_threshold_ratr; 1096 u32 ultralow_rssi_threshold_ratr; 1097 u32 low_rssi_threshold_ratr_40m; 1098 u32 low_rssi_threshold_ratr_20m; 1099 u8 ping_rssi_enable; 1100 u32 ping_rssi_ratr; 1101 u32 ping_rssi_thresh_for_ra; 1102 u32 last_ratr; 1103 u8 pre_ratr_state; 1104 u8 ldpc_thres; 1105 bool use_ldpc; 1106 bool lower_rts_rate; 1107 bool is_special_data; 1108 }; 1109 1110 struct regd_pair_mapping { 1111 u16 reg_dmnenum; 1112 u16 reg_5ghz_ctl; 1113 u16 reg_2ghz_ctl; 1114 }; 1115 1116 struct dynamic_primary_cca { 1117 u8 pricca_flag; 1118 u8 intf_flag; 1119 u8 intf_type; 1120 u8 dup_rts_flag; 1121 u8 monitor_flag; 1122 u8 ch_offset; 1123 u8 mf_state; 1124 }; 1125 1126 struct rtl_regulatory { 1127 s8 alpha2[2]; 1128 u16 country_code; 1129 u16 max_power_level; 1130 u32 tp_scale; 1131 u16 current_rd; 1132 u16 current_rd_ext; 1133 int16_t power_limit; 1134 struct regd_pair_mapping *regpair; 1135 }; 1136 1137 struct rtl_rfkill { 1138 bool rfkill_state; /*0 is off, 1 is on */ 1139 }; 1140 1141 /*for P2P PS**/ 1142 #define P2P_MAX_NOA_NUM 2 1143 1144 enum p2p_role { 1145 P2P_ROLE_DISABLE = 0, 1146 P2P_ROLE_DEVICE = 1, 1147 P2P_ROLE_CLIENT = 2, 1148 P2P_ROLE_GO = 3 1149 }; 1150 1151 enum p2p_ps_state { 1152 P2P_PS_DISABLE = 0, 1153 P2P_PS_ENABLE = 1, 1154 P2P_PS_SCAN = 2, 1155 P2P_PS_SCAN_DONE = 3, 1156 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1157 }; 1158 1159 enum p2p_ps_mode { 1160 P2P_PS_NONE = 0, 1161 P2P_PS_CTWINDOW = 1, 1162 P2P_PS_NOA = 2, 1163 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1164 }; 1165 1166 struct rtl_p2p_ps_info { 1167 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1168 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1169 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1170 /* Client traffic window. A period of time in TU after TBTT. */ 1171 u8 ctwindow; 1172 u8 opp_ps; /* opportunistic power save. */ 1173 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1174 /* Count for owner, Type of client. */ 1175 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1176 /* Max duration for owner, preferred or min acceptable duration 1177 * for client. 1178 */ 1179 u32 noa_duration[P2P_MAX_NOA_NUM]; 1180 /* Length of interval for owner, preferred or max acceptable intervali 1181 * of client. 1182 */ 1183 u32 noa_interval[P2P_MAX_NOA_NUM]; 1184 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1185 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1186 }; 1187 1188 struct p2p_ps_offload_t { 1189 u8 offload_en:1; 1190 u8 role:1; /* 1: Owner, 0: Client */ 1191 u8 ctwindow_en:1; 1192 u8 noa0_en:1; 1193 u8 noa1_en:1; 1194 u8 allstasleep:1; 1195 u8 discovery:1; 1196 u8 reserved:1; 1197 }; 1198 1199 #define IQK_MATRIX_REG_NUM 8 1200 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1201 1202 struct iqk_matrix_regs { 1203 bool iqk_done; 1204 long value[1][IQK_MATRIX_REG_NUM]; 1205 }; 1206 1207 struct phy_parameters { 1208 u16 length; 1209 u32 *pdata; 1210 }; 1211 1212 enum hw_param_tab_index { 1213 PHY_REG_2T, 1214 PHY_REG_1T, 1215 PHY_REG_PG, 1216 RADIOA_2T, 1217 RADIOB_2T, 1218 RADIOA_1T, 1219 RADIOB_1T, 1220 MAC_REG, 1221 AGCTAB_2T, 1222 AGCTAB_1T, 1223 MAX_TAB 1224 }; 1225 1226 struct rtl_phy { 1227 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1228 struct init_gain initgain_backup; 1229 enum io_type current_io_type; 1230 1231 u8 rf_mode; 1232 u8 rf_type; 1233 u8 current_chan_bw; 1234 u8 set_bwmode_inprogress; 1235 u8 sw_chnl_inprogress; 1236 u8 sw_chnl_stage; 1237 u8 sw_chnl_step; 1238 u8 current_channel; 1239 u8 h2c_box_num; 1240 u8 set_io_inprogress; 1241 u8 lck_inprogress; 1242 1243 /* record for power tracking */ 1244 s32 reg_e94; 1245 s32 reg_e9c; 1246 s32 reg_ea4; 1247 s32 reg_eac; 1248 s32 reg_eb4; 1249 s32 reg_ebc; 1250 s32 reg_ec4; 1251 s32 reg_ecc; 1252 u8 rfpienable; 1253 u8 reserve_0; 1254 u16 reserve_1; 1255 u32 reg_c04, reg_c08, reg_874; 1256 u32 adda_backup[16]; 1257 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1258 u32 iqk_bb_backup[10]; 1259 bool iqk_initialized; 1260 1261 bool rfpath_rx_enable[MAX_RF_PATH]; 1262 u8 reg_837; 1263 /* Dual mac */ 1264 bool need_iqk; 1265 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1266 1267 bool rfpi_enable; 1268 bool iqk_in_progress; 1269 1270 u8 pwrgroup_cnt; 1271 u8 cck_high_power; 1272 /* this is for 88E & 8723A */ 1273 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1274 /* MAX_PG_GROUP groups of pwr diff by rates */ 1275 u32 mcs_offset[MAX_PG_GROUP][16]; 1276 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1277 [TX_PWR_BY_RATE_NUM_RF] 1278 [TX_PWR_BY_RATE_NUM_RF] 1279 [TX_PWR_BY_RATE_NUM_SECTION]; 1280 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1281 [TX_PWR_BY_RATE_NUM_RF] 1282 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1283 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1284 [TX_PWR_BY_RATE_NUM_RF] 1285 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1286 u8 default_initialgain[4]; 1287 1288 /* the current Tx power level */ 1289 u8 cur_cck_txpwridx; 1290 u8 cur_ofdm24g_txpwridx; 1291 u8 cur_bw20_txpwridx; 1292 u8 cur_bw40_txpwridx; 1293 1294 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM] 1295 [MAX_2_4G_BANDWIDTH_NUM] 1296 [MAX_RATE_SECTION_NUM] 1297 [CHANNEL_MAX_NUMBER_2G] 1298 [MAX_RF_PATH_NUM]; 1299 s8 txpwr_limit_5g[MAX_REGULATION_NUM] 1300 [MAX_5G_BANDWIDTH_NUM] 1301 [MAX_RATE_SECTION_NUM] 1302 [CHANNEL_MAX_NUMBER_5G] 1303 [MAX_RF_PATH_NUM]; 1304 1305 u32 rfreg_chnlval[2]; 1306 bool apk_done; 1307 u32 reg_rf3c[2]; /* pathA / pathB */ 1308 1309 u32 backup_rf_0x1a;/*92ee*/ 1310 /* bfsync */ 1311 u8 framesync; 1312 u32 framesync_c34; 1313 1314 u8 num_total_rfpath; 1315 struct phy_parameters hwparam_tables[MAX_TAB]; 1316 u16 rf_pathmap; 1317 1318 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1319 enum rt_polarity_ctl polarity_ctl; 1320 }; 1321 1322 #define MAX_TID_COUNT 9 1323 #define RTL_AGG_STOP 0 1324 #define RTL_AGG_PROGRESS 1 1325 #define RTL_AGG_START 2 1326 #define RTL_AGG_OPERATIONAL 3 1327 #define RTL_AGG_OFF 0 1328 #define RTL_AGG_ON 1 1329 #define RTL_RX_AGG_START 1 1330 #define RTL_RX_AGG_STOP 0 1331 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1332 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1333 1334 struct rtl_ht_agg { 1335 u16 txq_id; 1336 u16 wait_for_ba; 1337 u16 start_idx; 1338 u64 bitmap; 1339 u32 rate_n_flags; 1340 u8 agg_state; 1341 u8 rx_agg_state; 1342 }; 1343 1344 struct rssi_sta { 1345 long undec_sm_pwdb; 1346 long undec_sm_cck; 1347 }; 1348 1349 struct rtl_tid_data { 1350 struct rtl_ht_agg agg; 1351 }; 1352 1353 struct rtl_sta_info { 1354 struct list_head list; 1355 struct rtl_tid_data tids[MAX_TID_COUNT]; 1356 /* just used for ap adhoc or mesh*/ 1357 struct rssi_sta rssi_stat; 1358 u8 rssi_level; 1359 u16 wireless_mode; 1360 u8 ratr_index; 1361 u8 mimo_ps; 1362 u8 mac_addr[ETH_ALEN]; 1363 } __packed; 1364 1365 struct rtl_priv; 1366 struct rtl_io { 1367 struct device *dev; 1368 struct mutex bb_mutex; 1369 1370 /*PCI MEM map */ 1371 unsigned long pci_mem_end; /*shared mem end */ 1372 unsigned long pci_mem_start; /*shared mem start */ 1373 1374 /*PCI IO map */ 1375 unsigned long pci_base_addr; /*device I/O address */ 1376 1377 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1378 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1379 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1380 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1381 u16 len); 1382 1383 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1384 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1385 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1386 1387 }; 1388 1389 struct rtl_mac { 1390 u8 mac_addr[ETH_ALEN]; 1391 u8 mac80211_registered; 1392 u8 beacon_enabled; 1393 1394 u32 tx_ss_num; 1395 u32 rx_ss_num; 1396 1397 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1398 struct ieee80211_hw *hw; 1399 struct ieee80211_vif *vif; 1400 enum nl80211_iftype opmode; 1401 1402 /*Probe Beacon management */ 1403 struct rtl_tid_data tids[MAX_TID_COUNT]; 1404 enum rtl_link_state link_state; 1405 1406 int n_channels; 1407 int n_bitrates; 1408 1409 bool offchan_delay; 1410 u8 p2p; /*using p2p role*/ 1411 bool p2p_in_use; 1412 1413 /*filters */ 1414 u32 rx_conf; 1415 u16 rx_mgt_filter; 1416 u16 rx_ctrl_filter; 1417 u16 rx_data_filter; 1418 1419 bool act_scanning; 1420 u8 cnt_after_linked; 1421 bool skip_scan; 1422 1423 /* early mode */ 1424 /* skb wait queue */ 1425 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1426 1427 u8 ht_stbc_cap; 1428 u8 ht_cur_stbc; 1429 1430 /*vht support*/ 1431 u8 vht_enable; 1432 u8 bw_80; 1433 u8 vht_cur_ldpc; 1434 u8 vht_cur_stbc; 1435 u8 vht_stbc_cap; 1436 u8 vht_ldpc_cap; 1437 1438 /*RDG*/ 1439 bool rdg_en; 1440 1441 /*AP*/ 1442 u8 bssid[ETH_ALEN] __aligned(2); 1443 u32 vendor; 1444 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1445 u32 basic_rates; /* b/g rates */ 1446 u8 ht_enable; 1447 u8 sgi_40; 1448 u8 sgi_20; 1449 u8 bw_40; 1450 u16 mode; /* wireless mode */ 1451 u8 slot_time; 1452 u8 short_preamble; 1453 u8 use_cts_protect; 1454 u8 cur_40_prime_sc; 1455 u8 cur_40_prime_sc_bk; 1456 u8 cur_80_prime_sc; 1457 u64 tsf; 1458 u8 retry_short; 1459 u8 retry_long; 1460 u16 assoc_id; 1461 bool hiddenssid; 1462 1463 /*IBSS*/ 1464 int beacon_interval; 1465 1466 /*AMPDU*/ 1467 u8 min_space_cfg; /*For Min spacing configurations */ 1468 u8 max_mss_density; 1469 u8 current_ampdu_factor; 1470 u8 current_ampdu_density; 1471 1472 /*QOS & EDCA */ 1473 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1474 struct rtl_qos_parameters ac[AC_MAX]; 1475 1476 /* counters */ 1477 u64 last_txok_cnt; 1478 u64 last_rxok_cnt; 1479 u32 last_bt_edca_ul; 1480 u32 last_bt_edca_dl; 1481 }; 1482 1483 struct btdm_8723 { 1484 bool all_off; 1485 bool agc_table_en; 1486 bool adc_back_off_on; 1487 bool b2_ant_hid_en; 1488 bool low_penalty_rate_adaptive; 1489 bool rf_rx_lpf_shrink; 1490 bool reject_aggre_pkt; 1491 bool tra_tdma_on; 1492 u8 tra_tdma_nav; 1493 u8 tra_tdma_ant; 1494 bool tdma_on; 1495 u8 tdma_ant; 1496 u8 tdma_nav; 1497 u8 tdma_dac_swing; 1498 u8 fw_dac_swing_lvl; 1499 bool ps_tdma_on; 1500 u8 ps_tdma_byte[5]; 1501 bool pta_on; 1502 u32 val_0x6c0; 1503 u32 val_0x6c8; 1504 u32 val_0x6cc; 1505 bool sw_dac_swing_on; 1506 u32 sw_dac_swing_lvl; 1507 u32 wlan_act_hi; 1508 u32 wlan_act_lo; 1509 u32 bt_retry_index; 1510 bool dec_bt_pwr; 1511 bool ignore_wlan_act; 1512 }; 1513 1514 struct bt_coexist_8723 { 1515 u32 high_priority_tx; 1516 u32 high_priority_rx; 1517 u32 low_priority_tx; 1518 u32 low_priority_rx; 1519 u8 c2h_bt_info; 1520 bool c2h_bt_info_req_sent; 1521 bool c2h_bt_inquiry_page; 1522 u32 bt_inq_page_start_time; 1523 u8 bt_retry_cnt; 1524 u8 c2h_bt_info_original; 1525 u8 bt_inquiry_page_cnt; 1526 struct btdm_8723 btdm; 1527 }; 1528 1529 struct rtl_hal { 1530 struct ieee80211_hw *hw; 1531 bool driver_is_goingto_unload; 1532 bool up_first_time; 1533 bool first_init; 1534 bool being_init_adapter; 1535 bool bbrf_ready; 1536 bool mac_func_enable; 1537 bool pre_edcca_enable; 1538 struct bt_coexist_8723 hal_coex_8723; 1539 1540 enum intf_type interface; 1541 u16 hw_type; /*92c or 92d or 92s and so on */ 1542 u8 ic_class; 1543 u8 oem_id; 1544 u32 version; /*version of chip */ 1545 u8 state; /*stop 0, start 1 */ 1546 u8 board_type; 1547 u8 package_type; 1548 u8 external_pa; 1549 1550 u8 pa_mode; 1551 u8 pa_type_2g; 1552 u8 pa_type_5g; 1553 u8 lna_type_2g; 1554 u8 lna_type_5g; 1555 u8 external_pa_2g; 1556 u8 external_lna_2g; 1557 u8 external_pa_5g; 1558 u8 external_lna_5g; 1559 u8 type_glna; 1560 u8 type_gpa; 1561 u8 type_alna; 1562 u8 type_apa; 1563 u8 rfe_type; 1564 1565 /*firmware */ 1566 u32 fwsize; 1567 u8 *pfirmware; 1568 u16 fw_version; 1569 u16 fw_subversion; 1570 bool h2c_setinprogress; 1571 u8 last_hmeboxnum; 1572 bool fw_ready; 1573 /*Reserve page start offset except beacon in TxQ. */ 1574 u8 fw_rsvdpage_startoffset; 1575 u8 h2c_txcmd_seq; 1576 u8 current_ra_rate; 1577 1578 /* FW Cmd IO related */ 1579 u16 fwcmd_iomap; 1580 u32 fwcmd_ioparam; 1581 bool set_fwcmd_inprogress; 1582 u8 current_fwcmd_io; 1583 1584 struct p2p_ps_offload_t p2p_ps_offload; 1585 bool fw_clk_change_in_progress; 1586 bool allow_sw_to_change_hwclc; 1587 u8 fw_ps_state; 1588 /**/ 1589 bool driver_going2unload; 1590 1591 /*AMPDU init min space*/ 1592 u8 minspace_cfg; /*For Min spacing configurations */ 1593 1594 /* Dual mac */ 1595 enum macphy_mode macphymode; 1596 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1597 enum band_type current_bandtypebackup; 1598 enum band_type bandset; 1599 /* dual MAC 0--Mac0 1--Mac1 */ 1600 u32 interfaceindex; 1601 /* just for DualMac S3S4 */ 1602 u8 macphyctl_reg; 1603 bool earlymode_enable; 1604 u8 max_earlymode_num; 1605 /* Dual mac*/ 1606 bool during_mac0init_radiob; 1607 bool during_mac1init_radioa; 1608 bool reloadtxpowerindex; 1609 /* True if IMR or IQK have done 1610 for 2.4G in scan progress */ 1611 bool load_imrandiqk_setting_for2g; 1612 1613 bool disable_amsdu_8k; 1614 bool master_of_dmsp; 1615 bool slave_of_dmsp; 1616 1617 u16 rx_tag;/*for 92ee*/ 1618 u8 rts_en; 1619 1620 /*for wowlan*/ 1621 bool wow_enable; 1622 bool enter_pnp_sleep; 1623 bool wake_from_pnp_sleep; 1624 bool wow_enabled; 1625 time64_t last_suspend_sec; 1626 u32 wowlan_fwsize; 1627 u8 *wowlan_firmware; 1628 1629 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1630 1631 bool real_wow_v2_enable; 1632 bool re_init_llt_table; 1633 }; 1634 1635 struct rtl_security { 1636 /*default 0 */ 1637 bool use_sw_sec; 1638 1639 bool being_setkey; 1640 bool use_defaultkey; 1641 /*Encryption Algorithm for Unicast Packet */ 1642 enum rt_enc_alg pairwise_enc_algorithm; 1643 /*Encryption Algorithm for Brocast/Multicast */ 1644 enum rt_enc_alg group_enc_algorithm; 1645 /*Cam Entry Bitmap */ 1646 u32 hwsec_cam_bitmap; 1647 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1648 /*local Key buffer, indx 0 is for 1649 pairwise key 1-4 is for agoup key. */ 1650 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1651 u8 key_len[KEY_BUF_SIZE]; 1652 1653 /*The pointer of Pairwise Key, 1654 it always points to KeyBuf[4] */ 1655 u8 *pairwise_key; 1656 }; 1657 1658 #define ASSOCIATE_ENTRY_NUM 33 1659 1660 struct fast_ant_training { 1661 u8 bssid[6]; 1662 u8 antsel_rx_keep_0; 1663 u8 antsel_rx_keep_1; 1664 u8 antsel_rx_keep_2; 1665 u32 ant_sum[7]; 1666 u32 ant_cnt[7]; 1667 u32 ant_ave[7]; 1668 u8 fat_state; 1669 u32 train_idx; 1670 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1671 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1672 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1673 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1674 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1675 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1676 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1677 u8 rx_idle_ant; 1678 bool becomelinked; 1679 }; 1680 1681 struct dm_phy_dbg_info { 1682 s8 rx_snrdb[4]; 1683 u64 num_qry_phy_status; 1684 u64 num_qry_phy_status_cck; 1685 u64 num_qry_phy_status_ofdm; 1686 u16 num_qry_beacon_pkt; 1687 u16 num_non_be_pkt; 1688 s32 rx_evm[4]; 1689 }; 1690 1691 struct rtl_dm { 1692 /*PHY status for Dynamic Management */ 1693 long entry_min_undec_sm_pwdb; 1694 long undec_sm_cck; 1695 long undec_sm_pwdb; /*out dm */ 1696 long entry_max_undec_sm_pwdb; 1697 s32 ofdm_pkt_cnt; 1698 bool dm_initialgain_enable; 1699 bool dynamic_txpower_enable; 1700 bool current_turbo_edca; 1701 bool is_any_nonbepkts; /*out dm */ 1702 bool is_cur_rdlstate; 1703 bool txpower_trackinginit; 1704 bool disable_framebursting; 1705 bool cck_inch14; 1706 bool txpower_tracking; 1707 bool useramask; 1708 bool rfpath_rxenable[4]; 1709 bool inform_fw_driverctrldm; 1710 bool current_mrc_switch; 1711 u8 txpowercount; 1712 u8 powerindex_backup[6]; 1713 1714 u8 thermalvalue_rxgain; 1715 u8 thermalvalue_iqk; 1716 u8 thermalvalue_lck; 1717 u8 thermalvalue; 1718 u8 last_dtp_lvl; 1719 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1720 u8 thermalvalue_avg_index; 1721 u8 tm_trigger; 1722 bool done_txpower; 1723 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1724 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1725 u8 dm_flag_tmp; 1726 u8 dm_type; 1727 u8 dm_rssi_sel; 1728 u8 txpower_track_control; 1729 bool interrupt_migration; 1730 bool disable_tx_int; 1731 s8 ofdm_index[MAX_RF_PATH]; 1732 u8 default_ofdm_index; 1733 u8 default_cck_index; 1734 s8 cck_index; 1735 s8 delta_power_index[MAX_RF_PATH]; 1736 s8 delta_power_index_last[MAX_RF_PATH]; 1737 s8 power_index_offset[MAX_RF_PATH]; 1738 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 1739 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 1740 s8 remnant_cck_idx; 1741 bool modify_txagc_flag_path_a; 1742 bool modify_txagc_flag_path_b; 1743 1744 bool one_entry_only; 1745 struct dm_phy_dbg_info dbginfo; 1746 1747 /* Dynamic ATC switch */ 1748 bool atc_status; 1749 bool large_cfo_hit; 1750 bool is_freeze; 1751 int cfo_tail[2]; 1752 int cfo_ave_pre; 1753 int crystal_cap; 1754 u8 cfo_threshold; 1755 u32 packet_count; 1756 u32 packet_count_pre; 1757 u8 tx_rate; 1758 1759 /*88e tx power tracking*/ 1760 u8 swing_idx_ofdm[MAX_RF_PATH]; 1761 u8 swing_idx_ofdm_cur; 1762 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1763 bool swing_flag_ofdm; 1764 u8 swing_idx_cck; 1765 u8 swing_idx_cck_cur; 1766 u8 swing_idx_cck_base; 1767 bool swing_flag_cck; 1768 1769 s8 swing_diff_2g; 1770 s8 swing_diff_5g; 1771 1772 /* DMSP */ 1773 bool supp_phymode_switch; 1774 1775 /* DulMac */ 1776 struct fast_ant_training fat_table; 1777 1778 u8 resp_tx_path; 1779 u8 path_sel; 1780 u32 patha_sum; 1781 u32 pathb_sum; 1782 u32 patha_cnt; 1783 u32 pathb_cnt; 1784 1785 u8 pre_channel; 1786 u8 *p_channel; 1787 u8 linked_interval; 1788 1789 u64 last_tx_ok_cnt; 1790 u64 last_rx_ok_cnt; 1791 }; 1792 1793 #define EFUSE_MAX_LOGICAL_SIZE 512 1794 1795 struct rtl_efuse { 1796 bool autoLoad_ok; 1797 bool bootfromefuse; 1798 u16 max_physical_size; 1799 1800 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1801 u16 efuse_usedbytes; 1802 u8 efuse_usedpercentage; 1803 #ifdef EFUSE_REPG_WORKAROUND 1804 bool efuse_re_pg_sec1flag; 1805 u8 efuse_re_pg_data[8]; 1806 #endif 1807 1808 u8 autoload_failflag; 1809 u8 autoload_status; 1810 1811 short epromtype; 1812 u16 eeprom_vid; 1813 u16 eeprom_did; 1814 u16 eeprom_svid; 1815 u16 eeprom_smid; 1816 u8 eeprom_oemid; 1817 u16 eeprom_channelplan; 1818 u8 eeprom_version; 1819 u8 board_type; 1820 u8 external_pa; 1821 1822 u8 dev_addr[6]; 1823 u8 wowlan_enable; 1824 u8 antenna_div_cfg; 1825 u8 antenna_div_type; 1826 1827 bool txpwr_fromeprom; 1828 u8 eeprom_crystalcap; 1829 u8 eeprom_tssi[2]; 1830 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1831 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1832 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1833 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1834 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1835 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1836 1837 u8 internal_pa_5g[2]; /* pathA / pathB */ 1838 u8 eeprom_c9; 1839 u8 eeprom_cc; 1840 1841 /*For power group */ 1842 u8 eeprom_pwrgroup[2][3]; 1843 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1844 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1845 1846 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1847 /*For HT 40MHZ pwr */ 1848 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1849 /*For HT 40MHZ pwr */ 1850 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1851 1852 /*--------------------------------------------------------* 1853 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1854 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1855 * define new arrays in Windows code. 1856 * BUT, in linux code, we use the same array for all ICs. 1857 * 1858 * The Correspondance relation between two arrays is: 1859 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1860 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1861 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1862 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1863 * 1864 * Sizes of these arrays are decided by the larger ones. 1865 */ 1866 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1867 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1868 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1869 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1870 1871 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1872 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1873 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1874 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1875 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1876 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1877 1878 u8 txpwr_safetyflag; /* Band edge enable flag */ 1879 u16 eeprom_txpowerdiff; 1880 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1881 u8 antenna_txpwdiff[3]; 1882 1883 u8 eeprom_regulatory; 1884 u8 eeprom_thermalmeter; 1885 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1886 u16 tssi_13dbm; 1887 u8 crystalcap; /* CrystalCap. */ 1888 u8 delta_iqk; 1889 u8 delta_lck; 1890 1891 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1892 bool apk_thermalmeterignore; 1893 1894 bool b1x1_recvcombine; 1895 bool b1ss_support; 1896 1897 /*channel plan */ 1898 u8 channel_plan; 1899 }; 1900 1901 struct rtl_tx_report { 1902 atomic_t sn; 1903 u16 last_sent_sn; 1904 unsigned long last_sent_time; 1905 u16 last_recv_sn; 1906 }; 1907 1908 struct rtl_ps_ctl { 1909 bool pwrdomain_protect; 1910 bool in_powersavemode; 1911 bool rfchange_inprogress; 1912 bool swrf_processing; 1913 bool hwradiooff; 1914 /* 1915 * just for PCIE ASPM 1916 * If it supports ASPM, Offset[560h] = 0x40, 1917 * otherwise Offset[560h] = 0x00. 1918 * */ 1919 bool support_aspm; 1920 bool support_backdoor; 1921 1922 /*for LPS */ 1923 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1924 bool swctrl_lps; 1925 bool leisure_ps; 1926 bool fwctrl_lps; 1927 u8 fwctrl_psmode; 1928 /*For Fw control LPS mode */ 1929 u8 reg_fwctrl_lps; 1930 /*Record Fw PS mode status. */ 1931 bool fw_current_inpsmode; 1932 u8 reg_max_lps_awakeintvl; 1933 bool report_linked; 1934 bool low_power_enable;/*for 32k*/ 1935 1936 /*for IPS */ 1937 bool inactiveps; 1938 1939 u32 rfoff_reason; 1940 1941 /*RF OFF Level */ 1942 u32 cur_ps_level; 1943 u32 reg_rfps_level; 1944 1945 /*just for PCIE ASPM */ 1946 u8 const_amdpci_aspm; 1947 bool pwrdown_mode; 1948 1949 enum rf_pwrstate inactive_pwrstate; 1950 enum rf_pwrstate rfpwr_state; /*cur power state */ 1951 1952 /* for SW LPS*/ 1953 bool sw_ps_enabled; 1954 bool state; 1955 bool state_inap; 1956 bool multi_buffered; 1957 u16 nullfunc_seq; 1958 unsigned int dtim_counter; 1959 unsigned int sleep_ms; 1960 unsigned long last_sleep_jiffies; 1961 unsigned long last_awake_jiffies; 1962 unsigned long last_delaylps_stamp_jiffies; 1963 unsigned long last_dtim; 1964 unsigned long last_beacon; 1965 unsigned long last_action; 1966 unsigned long last_slept; 1967 1968 /*For P2P PS */ 1969 struct rtl_p2p_ps_info p2p_ps_info; 1970 u8 pwr_mode; 1971 u8 smart_ps; 1972 1973 /* wake up on line */ 1974 u8 wo_wlan_mode; 1975 u8 arp_offload_enable; 1976 u8 gtk_offload_enable; 1977 /* Used for WOL, indicates the reason for waking event.*/ 1978 u32 wakeup_reason; 1979 }; 1980 1981 struct rtl_stats { 1982 u8 psaddr[ETH_ALEN]; 1983 u32 mac_time[2]; 1984 s8 rssi; 1985 u8 signal; 1986 u8 noise; 1987 u8 rate; /* hw desc rate */ 1988 u8 received_channel; 1989 u8 control; 1990 u8 mask; 1991 u8 freq; 1992 u16 len; 1993 u64 tsf; 1994 u32 beacon_time; 1995 u8 nic_type; 1996 u16 length; 1997 u8 signalquality; /*in 0-100 index. */ 1998 /* 1999 * Real power in dBm for this packet, 2000 * no beautification and aggregation. 2001 * */ 2002 s32 recvsignalpower; 2003 s8 rxpower; /*in dBm Translate from PWdB */ 2004 u8 signalstrength; /*in 0-100 index. */ 2005 u16 hwerror:1; 2006 u16 crc:1; 2007 u16 icv:1; 2008 u16 shortpreamble:1; 2009 u16 antenna:1; 2010 u16 decrypted:1; 2011 u16 wakeup:1; 2012 u32 timestamp_low; 2013 u32 timestamp_high; 2014 bool shift; 2015 2016 u8 rx_drvinfo_size; 2017 u8 rx_bufshift; 2018 bool isampdu; 2019 bool isfirst_ampdu; 2020 bool rx_is40Mhzpacket; 2021 u8 rx_packet_bw; 2022 u32 rx_pwdb_all; 2023 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2024 s8 rx_mimo_signalquality[4]; 2025 u8 rx_mimo_evm_dbm[4]; 2026 u16 cfo_short[4]; /* per-path's Cfo_short */ 2027 u16 cfo_tail[4]; 2028 2029 s8 rx_mimo_sig_qual[4]; 2030 u8 rx_pwr[4]; /* per-path's pwdb */ 2031 u8 rx_snr[4]; /* per-path's SNR */ 2032 u8 bandwidth; 2033 u8 bt_coex_pwr_adjust; 2034 bool packet_matchbssid; 2035 bool is_cck; 2036 bool is_ht; 2037 bool packet_toself; 2038 bool packet_beacon; /*for rssi */ 2039 s8 cck_adc_pwdb[4]; /*for rx path selection */ 2040 2041 bool is_vht; 2042 bool is_short_gi; 2043 u8 vht_nss; 2044 2045 u8 packet_report_type; 2046 2047 u32 macid; 2048 u8 wake_match; 2049 u32 bt_rx_rssi_percentage; 2050 u32 macid_valid_entry[2]; 2051 }; 2052 2053 2054 struct rt_link_detect { 2055 /* count for roaming */ 2056 u32 bcn_rx_inperiod; 2057 u32 roam_times; 2058 2059 u32 num_tx_in4period[4]; 2060 u32 num_rx_in4period[4]; 2061 2062 u32 num_tx_inperiod; 2063 u32 num_rx_inperiod; 2064 2065 bool busytraffic; 2066 bool tx_busy_traffic; 2067 bool rx_busy_traffic; 2068 bool higher_busytraffic; 2069 bool higher_busyrxtraffic; 2070 2071 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2072 u32 tidtx_inperiod[MAX_TID_COUNT]; 2073 bool higher_busytxtraffic[MAX_TID_COUNT]; 2074 }; 2075 2076 struct rtl_tcb_desc { 2077 u8 packet_bw:2; 2078 u8 multicast:1; 2079 u8 broadcast:1; 2080 2081 u8 rts_stbc:1; 2082 u8 rts_enable:1; 2083 u8 cts_enable:1; 2084 u8 rts_use_shortpreamble:1; 2085 u8 rts_use_shortgi:1; 2086 u8 rts_sc:1; 2087 u8 rts_bw:1; 2088 u8 rts_rate; 2089 2090 u8 use_shortgi:1; 2091 u8 use_shortpreamble:1; 2092 u8 use_driver_rate:1; 2093 u8 disable_ratefallback:1; 2094 2095 u8 use_spe_rpt:1; 2096 2097 u8 ratr_index; 2098 u8 mac_id; 2099 u8 hw_rate; 2100 2101 u8 last_inipkt:1; 2102 u8 cmd_or_init:1; 2103 u8 queue_index; 2104 2105 /* early mode */ 2106 u8 empkt_num; 2107 /* The max value by HW */ 2108 u32 empkt_len[10]; 2109 bool tx_enable_sw_calc_duration; 2110 }; 2111 2112 struct rtl_wow_pattern { 2113 u8 type; 2114 u16 crc; 2115 u32 mask[4]; 2116 }; 2117 2118 /* struct to store contents of interrupt vectors */ 2119 struct rtl_int { 2120 u32 inta; 2121 u32 intb; 2122 u32 intc; 2123 u32 intd; 2124 }; 2125 2126 struct rtl_hal_ops { 2127 int (*init_sw_vars) (struct ieee80211_hw *hw); 2128 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2129 void (*read_chip_version)(struct ieee80211_hw *hw); 2130 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2131 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2132 struct rtl_int *intvec); 2133 int (*hw_init) (struct ieee80211_hw *hw); 2134 void (*hw_disable) (struct ieee80211_hw *hw); 2135 void (*hw_suspend) (struct ieee80211_hw *hw); 2136 void (*hw_resume) (struct ieee80211_hw *hw); 2137 void (*enable_interrupt) (struct ieee80211_hw *hw); 2138 void (*disable_interrupt) (struct ieee80211_hw *hw); 2139 int (*set_network_type) (struct ieee80211_hw *hw, 2140 enum nl80211_iftype type); 2141 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2142 bool check_bssid); 2143 void (*set_bw_mode) (struct ieee80211_hw *hw, 2144 enum nl80211_channel_type ch_type); 2145 u8(*switch_channel) (struct ieee80211_hw *hw); 2146 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2147 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2148 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2149 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2150 u32 add_msr, u32 rm_msr); 2151 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2152 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2153 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2154 struct ieee80211_sta *sta, u8 rssi_leve, 2155 bool update_bw); 2156 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2157 u8 *desc, u8 queue_index, 2158 struct sk_buff *skb, dma_addr_t addr); 2159 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2160 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2161 u8 queue_index); 2162 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2163 u8 queue_index); 2164 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2165 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2166 u8 *pbd_desc_tx, 2167 struct ieee80211_tx_info *info, 2168 struct ieee80211_sta *sta, 2169 struct sk_buff *skb, u8 hw_queue, 2170 struct rtl_tcb_desc *ptcb_desc); 2171 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2172 u32 buffer_len, bool bIsPsPoll); 2173 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2174 bool firstseg, bool lastseg, 2175 struct sk_buff *skb); 2176 void (*fill_tx_special_desc)(struct ieee80211_hw *hw, 2177 u8 *pdesc, u8 *pbd_desc, 2178 struct sk_buff *skb, u8 hw_queue); 2179 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2180 struct rtl_stats *stats, 2181 struct ieee80211_rx_status *rx_status, 2182 u8 *pdesc, struct sk_buff *skb); 2183 void (*set_channel_access) (struct ieee80211_hw *hw); 2184 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2185 void (*dm_watchdog) (struct ieee80211_hw *hw); 2186 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2187 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2188 enum rf_pwrstate rfpwr_state); 2189 void (*led_control) (struct ieee80211_hw *hw, 2190 enum led_ctl_mode ledaction); 2191 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2192 u8 desc_name, u8 *val); 2193 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2194 u8 desc_name); 2195 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2196 u8 hw_queue, u16 index); 2197 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2198 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2199 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2200 u8 *macaddr, bool is_group, u8 enc_algo, 2201 bool is_wepkey, bool clear_all); 2202 void (*init_sw_leds) (struct ieee80211_hw *hw); 2203 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2204 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2205 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2206 u32 data); 2207 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2208 u32 regaddr, u32 bitmask); 2209 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2210 u32 regaddr, u32 bitmask, u32 data); 2211 void (*linked_set_reg) (struct ieee80211_hw *hw); 2212 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2213 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2214 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2215 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2216 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2217 u8 *powerlevel); 2218 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2219 u8 *ppowerlevel, u8 channel); 2220 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2221 u8 configtype); 2222 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2223 u8 configtype); 2224 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2225 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2226 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2227 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2228 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2229 bool mstate); 2230 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2231 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2232 u32 cmd_len, u8 *p_cmdbuffer); 2233 bool (*get_btc_status) (void); 2234 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2235 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2236 const struct rtl_stats *status, struct sk_buff *skb); 2237 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2238 struct rtl_wow_pattern *rtl_pattern, 2239 u8 index); 2240 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2241 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len, 2242 u8 *val); 2243 }; 2244 2245 struct rtl_intf_ops { 2246 /*com */ 2247 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2248 int (*adapter_start) (struct ieee80211_hw *hw); 2249 void (*adapter_stop) (struct ieee80211_hw *hw); 2250 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2251 struct rtl_priv **buddy_priv); 2252 2253 int (*adapter_tx) (struct ieee80211_hw *hw, 2254 struct ieee80211_sta *sta, 2255 struct sk_buff *skb, 2256 struct rtl_tcb_desc *ptcb_desc); 2257 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2258 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2259 bool (*waitq_insert) (struct ieee80211_hw *hw, 2260 struct ieee80211_sta *sta, 2261 struct sk_buff *skb); 2262 2263 /*pci */ 2264 void (*disable_aspm) (struct ieee80211_hw *hw); 2265 void (*enable_aspm) (struct ieee80211_hw *hw); 2266 2267 /*usb */ 2268 }; 2269 2270 struct rtl_mod_params { 2271 /* default: 0,0 */ 2272 u64 debug_mask; 2273 /* default: 0 = using hardware encryption */ 2274 bool sw_crypto; 2275 2276 /* default: 0 = DBG_EMERG (0)*/ 2277 int debug_level; 2278 2279 /* default: 1 = using no linked power save */ 2280 bool inactiveps; 2281 2282 /* default: 1 = using linked sw power save */ 2283 bool swctrl_lps; 2284 2285 /* default: 1 = using linked fw power save */ 2286 bool fwctrl_lps; 2287 2288 /* default: 0 = not using MSI interrupts mode 2289 * submodules should set their own default value 2290 */ 2291 bool msi_support; 2292 2293 /* default: 0 = dma 32 */ 2294 bool dma64; 2295 2296 /* default: 1 = enable aspm */ 2297 int aspm_support; 2298 2299 /* default 0: 1 means disable */ 2300 bool disable_watchdog; 2301 2302 /* default 0: 1 means do not disable interrupts */ 2303 bool int_clear; 2304 2305 /* select antenna */ 2306 int ant_sel; 2307 }; 2308 2309 struct rtl_hal_usbint_cfg { 2310 /* data - rx */ 2311 u32 in_ep_num; 2312 u32 rx_urb_num; 2313 u32 rx_max_size; 2314 2315 /* op - rx */ 2316 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2317 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2318 struct sk_buff_head *); 2319 2320 /* tx */ 2321 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2322 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2323 struct sk_buff *); 2324 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2325 struct sk_buff_head *); 2326 2327 /* endpoint mapping */ 2328 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2329 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2330 }; 2331 2332 struct rtl_hal_cfg { 2333 u8 bar_id; 2334 bool write_readback; 2335 char *name; 2336 char *alt_fw_name; 2337 struct rtl_hal_ops *ops; 2338 struct rtl_mod_params *mod_params; 2339 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2340 enum rtl_spec_ver spec_ver; 2341 2342 /*this map used for some registers or vars 2343 defined int HAL but used in MAIN */ 2344 u32 maps[RTL_VAR_MAP_MAX]; 2345 2346 }; 2347 2348 struct rtl_locks { 2349 /* mutex */ 2350 struct mutex conf_mutex; 2351 struct mutex ips_mutex; /* mutex for enter/leave IPS */ 2352 struct mutex lps_mutex; /* mutex for enter/leave LPS */ 2353 2354 /*spin lock */ 2355 spinlock_t irq_th_lock; 2356 spinlock_t h2c_lock; 2357 spinlock_t rf_ps_lock; 2358 spinlock_t rf_lock; 2359 spinlock_t waitq_lock; 2360 spinlock_t entry_list_lock; 2361 spinlock_t usb_lock; 2362 spinlock_t c2hcmd_lock; 2363 spinlock_t scan_list_lock; /* lock for the scan list */ 2364 2365 /*FW clock change */ 2366 spinlock_t fw_ps_lock; 2367 2368 /*Dual mac*/ 2369 spinlock_t cck_and_rw_pagea_lock; 2370 2371 spinlock_t iqk_lock; 2372 }; 2373 2374 struct rtl_works { 2375 struct ieee80211_hw *hw; 2376 2377 /*timer */ 2378 struct timer_list watchdog_timer; 2379 struct timer_list dualmac_easyconcurrent_retrytimer; 2380 struct timer_list fw_clockoff_timer; 2381 struct timer_list fast_antenna_training_timer; 2382 /*task */ 2383 struct tasklet_struct irq_tasklet; 2384 struct tasklet_struct irq_prepare_bcn_tasklet; 2385 2386 /*work queue */ 2387 struct workqueue_struct *rtl_wq; 2388 struct delayed_work watchdog_wq; 2389 struct delayed_work ips_nic_off_wq; 2390 struct delayed_work c2hcmd_wq; 2391 2392 /* For SW LPS */ 2393 struct delayed_work ps_work; 2394 struct delayed_work ps_rfon_wq; 2395 struct delayed_work fwevt_wq; 2396 2397 struct work_struct lps_change_work; 2398 struct work_struct fill_h2c_cmd; 2399 }; 2400 2401 struct rtl_debug { 2402 /* add for debug */ 2403 struct dentry *debugfs_dir; 2404 char debugfs_name[20]; 2405 }; 2406 2407 #define MIMO_PS_STATIC 0 2408 #define MIMO_PS_DYNAMIC 1 2409 #define MIMO_PS_NOLIMIT 3 2410 2411 struct rtl_dualmac_easy_concurrent_ctl { 2412 enum band_type currentbandtype_backfordmdp; 2413 bool close_bbandrf_for_dmsp; 2414 bool change_to_dmdp; 2415 bool change_to_dmsp; 2416 bool switch_in_process; 2417 }; 2418 2419 struct rtl_dmsp_ctl { 2420 bool activescan_for_slaveofdmsp; 2421 bool scan_for_anothermac_fordmsp; 2422 bool scan_for_itself_fordmsp; 2423 bool writedig_for_anothermacofdmsp; 2424 u32 curdigvalue_for_anothermacofdmsp; 2425 bool changecckpdstate_for_anothermacofdmsp; 2426 u8 curcckpdstate_for_anothermacofdmsp; 2427 bool changetxhighpowerlvl_for_anothermacofdmsp; 2428 u8 curtxhighlvl_for_anothermacofdmsp; 2429 long rssivalmin_for_anothermacofdmsp; 2430 }; 2431 2432 struct ps_t { 2433 u8 pre_ccastate; 2434 u8 cur_ccasate; 2435 u8 pre_rfstate; 2436 u8 cur_rfstate; 2437 u8 initialize; 2438 long rssi_val_min; 2439 }; 2440 2441 struct dig_t { 2442 u32 rssi_lowthresh; 2443 u32 rssi_highthresh; 2444 u32 fa_lowthresh; 2445 u32 fa_highthresh; 2446 long last_min_undec_pwdb_for_dm; 2447 long rssi_highpower_lowthresh; 2448 long rssi_highpower_highthresh; 2449 u32 recover_cnt; 2450 u32 pre_igvalue; 2451 u32 cur_igvalue; 2452 long rssi_val; 2453 u8 dig_enable_flag; 2454 u8 dig_ext_port_stage; 2455 u8 dig_algorithm; 2456 u8 dig_twoport_algorithm; 2457 u8 dig_dbgmode; 2458 u8 dig_slgorithm_switch; 2459 u8 cursta_cstate; 2460 u8 presta_cstate; 2461 u8 curmultista_cstate; 2462 u8 stop_dig; 2463 s8 back_val; 2464 s8 back_range_max; 2465 s8 back_range_min; 2466 u8 rx_gain_max; 2467 u8 rx_gain_min; 2468 u8 min_undec_pwdb_for_dm; 2469 u8 rssi_val_min; 2470 u8 pre_cck_cca_thres; 2471 u8 cur_cck_cca_thres; 2472 u8 pre_cck_pd_state; 2473 u8 cur_cck_pd_state; 2474 u8 pre_cck_fa_state; 2475 u8 cur_cck_fa_state; 2476 u8 pre_ccastate; 2477 u8 cur_ccasate; 2478 u8 large_fa_hit; 2479 u8 forbidden_igi; 2480 u8 dig_state; 2481 u8 dig_highpwrstate; 2482 u8 cur_sta_cstate; 2483 u8 pre_sta_cstate; 2484 u8 cur_ap_cstate; 2485 u8 pre_ap_cstate; 2486 u8 cur_pd_thstate; 2487 u8 pre_pd_thstate; 2488 u8 cur_cs_ratiostate; 2489 u8 pre_cs_ratiostate; 2490 u8 backoff_enable_flag; 2491 s8 backoffval_range_max; 2492 s8 backoffval_range_min; 2493 u8 dig_min_0; 2494 u8 dig_min_1; 2495 u8 bt30_cur_igi; 2496 bool media_connect_0; 2497 bool media_connect_1; 2498 2499 u32 antdiv_rssi_max; 2500 u32 rssi_max; 2501 }; 2502 2503 struct rtl_global_var { 2504 /* from this list we can get 2505 * other adapter's rtl_priv */ 2506 struct list_head glb_priv_list; 2507 spinlock_t glb_list_lock; 2508 }; 2509 2510 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */ 2511 2512 struct rtl_btc_info { 2513 u8 bt_type; 2514 u8 btcoexist; 2515 u8 ant_num; 2516 u8 single_ant_path; 2517 2518 u8 ap_num; 2519 bool in_4way; 2520 unsigned long in_4way_ts; 2521 }; 2522 2523 struct bt_coexist_info { 2524 struct rtl_btc_ops *btc_ops; 2525 struct rtl_btc_info btc_info; 2526 /* btc context */ 2527 void *btc_context; 2528 void *wifi_only_context; 2529 /* EEPROM BT info. */ 2530 u8 eeprom_bt_coexist; 2531 u8 eeprom_bt_type; 2532 u8 eeprom_bt_ant_num; 2533 u8 eeprom_bt_ant_isol; 2534 u8 eeprom_bt_radio_shared; 2535 2536 u8 bt_coexistence; 2537 u8 bt_ant_num; 2538 u8 bt_coexist_type; 2539 u8 bt_state; 2540 u8 bt_cur_state; /* 0:on, 1:off */ 2541 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2542 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2543 u8 bt_service; 2544 u8 bt_radio_shared_type; 2545 u8 bt_rfreg_origin_1e; 2546 u8 bt_rfreg_origin_1f; 2547 u8 bt_rssi_state; 2548 u32 ratio_tx; 2549 u32 ratio_pri; 2550 u32 bt_edca_ul; 2551 u32 bt_edca_dl; 2552 2553 bool init_set; 2554 bool bt_busy_traffic; 2555 bool bt_traffic_mode_set; 2556 bool bt_non_traffic_mode_set; 2557 2558 bool fw_coexist_all_off; 2559 bool sw_coexist_all_off; 2560 bool hw_coexist_all_off; 2561 u32 cstate; 2562 u32 previous_state; 2563 u32 cstate_h; 2564 u32 previous_state_h; 2565 2566 u8 bt_pre_rssi_state; 2567 u8 bt_pre_rssi_state1; 2568 2569 u8 reg_bt_iso; 2570 u8 reg_bt_sco; 2571 bool balance_on; 2572 u8 bt_active_zero_cnt; 2573 bool cur_bt_disabled; 2574 bool pre_bt_disabled; 2575 2576 u8 bt_profile_case; 2577 u8 bt_profile_action; 2578 bool bt_busy; 2579 bool hold_for_bt_operation; 2580 u8 lps_counter; 2581 }; 2582 2583 struct rtl_btc_ops { 2584 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2585 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv); 2586 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv); 2587 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2588 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv); 2589 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2590 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv); 2591 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2592 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2593 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2594 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv, 2595 u8 scantype); 2596 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2597 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2598 enum rt_media_status mstatus); 2599 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2600 void (*btc_halt_notify)(struct rtl_priv *rtlpriv); 2601 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2602 u8 *tmp_buf, u8 length); 2603 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv, 2604 u8 *tmp_buf, u8 length); 2605 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2606 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2607 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2608 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2609 u8 pkt_type); 2610 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type, 2611 bool scanning); 2612 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv, 2613 u8 type, bool scanning); 2614 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv, 2615 struct seq_file *m); 2616 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len); 2617 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv); 2618 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv); 2619 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv); 2620 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg, 2621 u8 *ctrl_agg_size, u8 *agg_size); 2622 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv); 2623 }; 2624 2625 struct proxim { 2626 bool proxim_on; 2627 2628 void *proximity_priv; 2629 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2630 struct sk_buff *skb); 2631 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2632 }; 2633 2634 struct rtl_c2hcmd { 2635 struct list_head list; 2636 u8 tag; 2637 u8 len; 2638 u8 *val; 2639 }; 2640 2641 struct rtl_bssid_entry { 2642 struct list_head list; 2643 u8 bssid[ETH_ALEN]; 2644 u32 age; 2645 }; 2646 2647 struct rtl_scan_list { 2648 int num; 2649 struct list_head list; /* sort by age */ 2650 }; 2651 2652 struct rtl_priv { 2653 struct ieee80211_hw *hw; 2654 struct completion firmware_loading_complete; 2655 struct list_head list; 2656 struct rtl_priv *buddy_priv; 2657 struct rtl_global_var *glb_var; 2658 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2659 struct rtl_dmsp_ctl dmsp_ctl; 2660 struct rtl_locks locks; 2661 struct rtl_works works; 2662 struct rtl_mac mac80211; 2663 struct rtl_hal rtlhal; 2664 struct rtl_regulatory regd; 2665 struct rtl_rfkill rfkill; 2666 struct rtl_io io; 2667 struct rtl_phy phy; 2668 struct rtl_dm dm; 2669 struct rtl_security sec; 2670 struct rtl_efuse efuse; 2671 struct rtl_led_ctl ledctl; 2672 struct rtl_tx_report tx_report; 2673 struct rtl_scan_list scan_list; 2674 2675 struct rtl_ps_ctl psc; 2676 struct rate_adaptive ra; 2677 struct dynamic_primary_cca primarycca; 2678 struct wireless_stats stats; 2679 struct rt_link_detect link_info; 2680 struct false_alarm_statistics falsealm_cnt; 2681 2682 struct rtl_rate_priv *rate_priv; 2683 2684 /* sta entry list for ap adhoc or mesh */ 2685 struct list_head entry_list; 2686 2687 /* c2hcmd list for kthread level access */ 2688 struct list_head c2hcmd_list; 2689 2690 struct rtl_debug dbg; 2691 int max_fw_size; 2692 2693 /* 2694 *hal_cfg : for diff cards 2695 *intf_ops : for diff interrface usb/pcie 2696 */ 2697 struct rtl_hal_cfg *cfg; 2698 const struct rtl_intf_ops *intf_ops; 2699 2700 /*this var will be set by set_bit, 2701 and was used to indicate status of 2702 interface or hardware */ 2703 unsigned long status; 2704 2705 /* tables for dm */ 2706 struct dig_t dm_digtable; 2707 struct ps_t dm_pstable; 2708 2709 u32 reg_874; 2710 u32 reg_c70; 2711 u32 reg_85c; 2712 u32 reg_a74; 2713 bool reg_init; /* true if regs saved */ 2714 bool bt_operation_on; 2715 __le32 *usb_data; 2716 int usb_data_index; 2717 bool initialized; 2718 bool enter_ps; /* true when entering PS */ 2719 u8 rate_mask[5]; 2720 2721 /* intel Proximity, should be alloc mem 2722 * in intel Proximity module and can only 2723 * be used in intel Proximity mode 2724 */ 2725 struct proxim proximity; 2726 2727 /*for bt coexist use*/ 2728 struct bt_coexist_info btcoexist; 2729 2730 /* separate 92ee from other ICs, 2731 * 92ee use new trx flow. 2732 */ 2733 bool use_new_trx_flow; 2734 2735 #ifdef CONFIG_PM 2736 struct wiphy_wowlan_support wowlan; 2737 #endif 2738 /*This must be the last item so 2739 that it points to the data allocated 2740 beyond this structure like: 2741 rtl_pci_priv or rtl_usb_priv */ 2742 u8 priv[0] __aligned(sizeof(void *)); 2743 }; 2744 2745 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2746 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2747 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2748 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2749 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2750 2751 2752 /*************************************** 2753 Bluetooth Co-existence Related 2754 ****************************************/ 2755 2756 enum bt_ant_num { 2757 ANT_X2 = 0, 2758 ANT_X1 = 1, 2759 }; 2760 2761 enum bt_co_type { 2762 BT_2WIRE = 0, 2763 BT_ISSC_3WIRE = 1, 2764 BT_ACCEL = 2, 2765 BT_CSR_BC4 = 3, 2766 BT_CSR_BC8 = 4, 2767 BT_RTL8756 = 5, 2768 BT_RTL8723A = 6, 2769 BT_RTL8821A = 7, 2770 BT_RTL8723B = 8, 2771 BT_RTL8192E = 9, 2772 BT_RTL8812A = 11, 2773 }; 2774 2775 enum bt_total_ant_num { 2776 ANT_TOTAL_X2 = 0, 2777 ANT_TOTAL_X1 = 1 2778 }; 2779 2780 enum bt_cur_state { 2781 BT_OFF = 0, 2782 BT_ON = 1, 2783 }; 2784 2785 enum bt_service_type { 2786 BT_SCO = 0, 2787 BT_A2DP = 1, 2788 BT_HID = 2, 2789 BT_HID_IDLE = 3, 2790 BT_SCAN = 4, 2791 BT_IDLE = 5, 2792 BT_OTHER_ACTION = 6, 2793 BT_BUSY = 7, 2794 BT_OTHERBUSY = 8, 2795 BT_PAN = 9, 2796 }; 2797 2798 enum bt_radio_shared { 2799 BT_RADIO_SHARED = 0, 2800 BT_RADIO_INDIVIDUAL = 1, 2801 }; 2802 2803 2804 /**************************************** 2805 mem access macro define start 2806 Call endian free function when 2807 1. Read/write packet content. 2808 2. Before write integer to IO. 2809 3. After read integer from IO. 2810 ****************************************/ 2811 /* Convert little data endian to host ordering */ 2812 #define EF1BYTE(_val) \ 2813 ((u8)(_val)) 2814 #define EF2BYTE(_val) \ 2815 (le16_to_cpu(_val)) 2816 #define EF4BYTE(_val) \ 2817 (le32_to_cpu(_val)) 2818 2819 /* Read data from memory */ 2820 #define READEF1BYTE(_ptr) \ 2821 EF1BYTE(*((u8 *)(_ptr))) 2822 /* Read le16 data from memory and convert to host ordering */ 2823 #define READEF2BYTE(_ptr) \ 2824 EF2BYTE(*(_ptr)) 2825 #define READEF4BYTE(_ptr) \ 2826 EF4BYTE(*(_ptr)) 2827 2828 /* Create a bit mask 2829 * Examples: 2830 * BIT_LEN_MASK_32(0) => 0x00000000 2831 * BIT_LEN_MASK_32(1) => 0x00000001 2832 * BIT_LEN_MASK_32(2) => 0x00000003 2833 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2834 */ 2835 #define BIT_LEN_MASK_32(__bitlen) \ 2836 (0xFFFFFFFF >> (32 - (__bitlen))) 2837 #define BIT_LEN_MASK_16(__bitlen) \ 2838 (0xFFFF >> (16 - (__bitlen))) 2839 #define BIT_LEN_MASK_8(__bitlen) \ 2840 (0xFF >> (8 - (__bitlen))) 2841 2842 /* Create an offset bit mask 2843 * Examples: 2844 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2845 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2846 */ 2847 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2848 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2849 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2850 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2851 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2852 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2853 2854 /*Description: 2855 * Return 4-byte value in host byte ordering from 2856 * 4-byte pointer in little-endian system. 2857 */ 2858 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2859 (EF4BYTE(*((__le32 *)(__pstart)))) 2860 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2861 (EF2BYTE(*((__le16 *)(__pstart)))) 2862 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2863 (EF1BYTE(*((u8 *)(__pstart)))) 2864 2865 /*Description: 2866 Translate subfield (continuous bits in little-endian) of 4-byte 2867 value to host byte ordering.*/ 2868 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2869 ( \ 2870 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2871 BIT_LEN_MASK_32(__bitlen) \ 2872 ) 2873 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2874 ( \ 2875 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2876 BIT_LEN_MASK_16(__bitlen) \ 2877 ) 2878 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2879 ( \ 2880 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2881 BIT_LEN_MASK_8(__bitlen) \ 2882 ) 2883 2884 /* Description: 2885 * Mask subfield (continuous bits in little-endian) of 4-byte value 2886 * and return the result in 4-byte value in host byte ordering. 2887 */ 2888 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2889 ( \ 2890 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2891 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2892 ) 2893 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2894 ( \ 2895 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2896 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2897 ) 2898 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2899 ( \ 2900 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2901 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2902 ) 2903 2904 /* Description: 2905 * Set subfield of little-endian 4-byte value to specified value. 2906 */ 2907 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2908 *((__le32 *)(__pstart)) = \ 2909 cpu_to_le32( \ 2910 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 2911 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 2912 ) 2913 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2914 *((__le16 *)(__pstart)) = \ 2915 cpu_to_le16( \ 2916 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 2917 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 2918 ) 2919 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2920 *((u8 *)(__pstart)) = EF1BYTE \ 2921 ( \ 2922 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 2923 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 2924 ) 2925 2926 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 2927 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 2928 2929 /**************************************** 2930 mem access macro define end 2931 ****************************************/ 2932 2933 #define byte(x, n) ((x >> (8 * n)) & 0xff) 2934 2935 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 2936 #define RTL_WATCH_DOG_TIME 2000 2937 #define MSECS(t) msecs_to_jiffies(t) 2938 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 2939 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 2940 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 2941 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 2942 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 2943 2944 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 2945 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 2946 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 2947 /*NIC halt, re-initialize hw parameters*/ 2948 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 2949 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 2950 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 2951 /*Always enable ASPM and Clock Req in initialization.*/ 2952 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 2953 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 2954 #define RT_PS_LEVEL_ASPM BIT(7) 2955 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 2956 #define RT_RF_LPS_DISALBE_2R BIT(30) 2957 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 2958 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 2959 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 2960 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 2961 (ppsc->cur_ps_level &= (~(_ps_flg))) 2962 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 2963 (ppsc->cur_ps_level |= _ps_flg) 2964 2965 #define container_of_dwork_rtl(x, y, z) \ 2966 container_of(to_delayed_work(x), y, z) 2967 2968 #define FILL_OCTET_STRING(_os, _octet, _len) \ 2969 (_os).octet = (u8 *)(_octet); \ 2970 (_os).length = (_len); 2971 2972 #define CP_MACADDR(des, src) \ 2973 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 2974 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 2975 (des)[4] = (src)[4], (des)[5] = (src)[5]) 2976 2977 #define LDPC_HT_ENABLE_RX BIT(0) 2978 #define LDPC_HT_ENABLE_TX BIT(1) 2979 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 2980 #define LDPC_HT_CAP_TX BIT(3) 2981 2982 #define STBC_HT_ENABLE_RX BIT(0) 2983 #define STBC_HT_ENABLE_TX BIT(1) 2984 #define STBC_HT_TEST_TX_ENABLE BIT(2) 2985 #define STBC_HT_CAP_TX BIT(3) 2986 2987 #define LDPC_VHT_ENABLE_RX BIT(0) 2988 #define LDPC_VHT_ENABLE_TX BIT(1) 2989 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 2990 #define LDPC_VHT_CAP_TX BIT(3) 2991 2992 #define STBC_VHT_ENABLE_RX BIT(0) 2993 #define STBC_VHT_ENABLE_TX BIT(1) 2994 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 2995 #define STBC_VHT_CAP_TX BIT(3) 2996 2997 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G]; 2998 2999 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M]; 3000 3001 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 3002 { 3003 return rtlpriv->io.read8_sync(rtlpriv, addr); 3004 } 3005 3006 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 3007 { 3008 return rtlpriv->io.read16_sync(rtlpriv, addr); 3009 } 3010 3011 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 3012 { 3013 return rtlpriv->io.read32_sync(rtlpriv, addr); 3014 } 3015 3016 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 3017 { 3018 rtlpriv->io.write8_async(rtlpriv, addr, val8); 3019 3020 if (rtlpriv->cfg->write_readback) 3021 rtlpriv->io.read8_sync(rtlpriv, addr); 3022 } 3023 3024 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw, 3025 u32 addr, u32 val8) 3026 { 3027 struct rtl_priv *rtlpriv = rtl_priv(hw); 3028 3029 rtl_write_byte(rtlpriv, addr, (u8)val8); 3030 } 3031 3032 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 3033 { 3034 rtlpriv->io.write16_async(rtlpriv, addr, val16); 3035 3036 if (rtlpriv->cfg->write_readback) 3037 rtlpriv->io.read16_sync(rtlpriv, addr); 3038 } 3039 3040 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 3041 u32 addr, u32 val32) 3042 { 3043 rtlpriv->io.write32_async(rtlpriv, addr, val32); 3044 3045 if (rtlpriv->cfg->write_readback) 3046 rtlpriv->io.read32_sync(rtlpriv, addr); 3047 } 3048 3049 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 3050 u32 regaddr, u32 bitmask) 3051 { 3052 struct rtl_priv *rtlpriv = hw->priv; 3053 3054 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 3055 } 3056 3057 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 3058 u32 bitmask, u32 data) 3059 { 3060 struct rtl_priv *rtlpriv = hw->priv; 3061 3062 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 3063 } 3064 3065 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw, 3066 u32 regaddr, u32 data) 3067 { 3068 rtl_set_bbreg(hw, regaddr, 0xffffffff, data); 3069 } 3070 3071 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 3072 enum radio_path rfpath, u32 regaddr, 3073 u32 bitmask) 3074 { 3075 struct rtl_priv *rtlpriv = hw->priv; 3076 3077 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 3078 } 3079 3080 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 3081 enum radio_path rfpath, u32 regaddr, 3082 u32 bitmask, u32 data) 3083 { 3084 struct rtl_priv *rtlpriv = hw->priv; 3085 3086 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 3087 } 3088 3089 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 3090 { 3091 return (_HAL_STATE_STOP == rtlhal->state); 3092 } 3093 3094 static inline void set_hal_start(struct rtl_hal *rtlhal) 3095 { 3096 rtlhal->state = _HAL_STATE_START; 3097 } 3098 3099 static inline void set_hal_stop(struct rtl_hal *rtlhal) 3100 { 3101 rtlhal->state = _HAL_STATE_STOP; 3102 } 3103 3104 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 3105 { 3106 return rtlphy->rf_type; 3107 } 3108 3109 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3110 { 3111 return (struct ieee80211_hdr *)(skb->data); 3112 } 3113 3114 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3115 { 3116 return rtl_get_hdr(skb)->frame_control; 3117 } 3118 3119 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3120 { 3121 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3122 } 3123 3124 static inline u16 rtl_get_tid(struct sk_buff *skb) 3125 { 3126 return rtl_get_tid_h(rtl_get_hdr(skb)); 3127 } 3128 3129 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3130 struct ieee80211_vif *vif, 3131 const u8 *bssid) 3132 { 3133 return ieee80211_find_sta(vif, bssid); 3134 } 3135 3136 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3137 u8 *mac_addr) 3138 { 3139 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3140 return ieee80211_find_sta(mac->vif, mac_addr); 3141 } 3142 3143 #endif 3144