1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2010 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../pci.h" 6 #include "../ps.h" 7 #include "reg.h" 8 #include "def.h" 9 #include "phy.h" 10 #include "rf.h" 11 #include "dm.h" 12 #include "table.h" 13 #include "trx.h" 14 #include "../btcoexist/halbt_precomp.h" 15 #include "hw.h" 16 #include "../efuse.h" 17 18 #define READ_NEXT_PAIR(array_table, v1, v2, i) \ 19 do { \ 20 i += 2; \ 21 v1 = array_table[i]; \ 22 v2 = array_table[i+1]; \ 23 } while (0) 24 25 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw, 26 enum radio_path rfpath, u32 offset); 27 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw, 28 enum radio_path rfpath, u32 offset, 29 u32 data); 30 static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask) 31 { 32 u32 i = ffs(bitmask); 33 34 return i ? i - 1 : 32; 35 } 36 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw); 37 /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/ 38 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 39 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 40 u8 configtype); 41 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 42 u8 configtype); 43 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); 44 45 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 46 enum wireless_mode wirelessmode, 47 u8 txpwridx); 48 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw); 49 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw); 50 51 static void rtl8812ae_fixspur(struct ieee80211_hw *hw, 52 enum ht_channel_width band_width, u8 channel) 53 { 54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 55 56 /*C cut Item12 ADC FIFO CLOCK*/ 57 if (IS_VENDOR_8812A_C_CUT(rtlhal->version)) { 58 if (band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11) 59 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3); 60 /* 0x8AC[11:10] = 2'b11*/ 61 else 62 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2); 63 /* 0x8AC[11:10] = 2'b10*/ 64 65 /* <20120914, Kordan> A workaround to resolve 66 * 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson) 67 */ 68 if (band_width == HT_CHANNEL_WIDTH_20 && 69 (channel == 13 || channel == 14)) { 70 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); 71 /*0x8AC[9:8] = 2'b11*/ 72 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); 73 /* 0x8C4[30] = 1*/ 74 } else if (band_width == HT_CHANNEL_WIDTH_20_40 && 75 channel == 11) { 76 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); 77 /*0x8C4[30] = 1*/ 78 } else if (band_width != HT_CHANNEL_WIDTH_80) { 79 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2); 80 /*0x8AC[9:8] = 2'b10*/ 81 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); 82 /*0x8C4[30] = 0*/ 83 } 84 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 85 /* <20120914, Kordan> A workaround to resolve 86 * 2480Mhz spur by setting ADC clock as 160M. 87 */ 88 if (band_width == HT_CHANNEL_WIDTH_20 && 89 (channel == 13 || channel == 14)) 90 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); 91 /*0x8AC[9:8] = 11*/ 92 else if (channel <= 14) /*2.4G only*/ 93 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2); 94 /*0x8AC[9:8] = 10*/ 95 } 96 } 97 98 u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, 99 u32 bitmask) 100 { 101 struct rtl_priv *rtlpriv = rtl_priv(hw); 102 u32 returnvalue, originalvalue, bitshift; 103 104 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 105 "regaddr(%#x), bitmask(%#x)\n", 106 regaddr, bitmask); 107 originalvalue = rtl_read_dword(rtlpriv, regaddr); 108 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 109 returnvalue = (originalvalue & bitmask) >> bitshift; 110 111 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 112 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 113 bitmask, regaddr, originalvalue); 114 return returnvalue; 115 } 116 117 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw, 118 u32 regaddr, u32 bitmask, u32 data) 119 { 120 struct rtl_priv *rtlpriv = rtl_priv(hw); 121 u32 originalvalue, bitshift; 122 123 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 124 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 125 regaddr, bitmask, data); 126 127 if (bitmask != MASKDWORD) { 128 originalvalue = rtl_read_dword(rtlpriv, regaddr); 129 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 130 data = ((originalvalue & (~bitmask)) | 131 ((data << bitshift) & bitmask)); 132 } 133 134 rtl_write_dword(rtlpriv, regaddr, data); 135 136 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 137 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 138 regaddr, bitmask, data); 139 } 140 141 u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw, 142 enum radio_path rfpath, u32 regaddr, 143 u32 bitmask) 144 { 145 struct rtl_priv *rtlpriv = rtl_priv(hw); 146 u32 original_value, readback_value, bitshift; 147 148 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 149 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 150 regaddr, rfpath, bitmask); 151 152 spin_lock(&rtlpriv->locks.rf_lock); 153 154 original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); 155 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 156 readback_value = (original_value & bitmask) >> bitshift; 157 158 spin_unlock(&rtlpriv->locks.rf_lock); 159 160 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 161 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 162 regaddr, rfpath, bitmask, original_value); 163 164 return readback_value; 165 } 166 167 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw, 168 enum radio_path rfpath, 169 u32 regaddr, u32 bitmask, u32 data) 170 { 171 struct rtl_priv *rtlpriv = rtl_priv(hw); 172 u32 original_value, bitshift; 173 174 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 175 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 176 regaddr, bitmask, data, rfpath); 177 178 spin_lock(&rtlpriv->locks.rf_lock); 179 180 if (bitmask != RFREG_OFFSET_MASK) { 181 original_value = 182 _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); 183 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 184 data = ((original_value & (~bitmask)) | (data << bitshift)); 185 } 186 187 _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data); 188 189 spin_unlock(&rtlpriv->locks.rf_lock); 190 191 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 192 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 193 regaddr, bitmask, data, rfpath); 194 } 195 196 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw, 197 enum radio_path rfpath, u32 offset) 198 { 199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 200 bool is_pi_mode = false; 201 u32 retvalue = 0; 202 203 /* 2009/06/17 MH We can not execute IO for power 204 save or other accident mode.*/ 205 if (RT_CANNOT_IO(hw)) { 206 pr_err("return all one\n"); 207 return 0xFFFFFFFF; 208 } 209 /* <20120809, Kordan> CCA OFF(when entering), 210 asked by James to avoid reading the wrong value. 211 <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/ 212 if (offset != 0x0 && 213 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 214 (IS_VENDOR_8812A_C_CUT(rtlhal->version)))) 215 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1); 216 offset &= 0xff; 217 218 if (rfpath == RF90_PATH_A) 219 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xC00, 0x4); 220 else if (rfpath == RF90_PATH_B) 221 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xE00, 0x4); 222 223 rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset); 224 225 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 226 (IS_VENDOR_8812A_C_CUT(rtlhal->version))) 227 udelay(20); 228 229 if (is_pi_mode) { 230 if (rfpath == RF90_PATH_A) 231 retvalue = 232 rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA); 233 else if (rfpath == RF90_PATH_B) 234 retvalue = 235 rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA); 236 } else { 237 if (rfpath == RF90_PATH_A) 238 retvalue = 239 rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA); 240 else if (rfpath == RF90_PATH_B) 241 retvalue = 242 rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA); 243 } 244 245 /*<20120809, Kordan> CCA ON(when exiting), 246 * asked by James to avoid reading the wrong value. 247 * <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it! 248 */ 249 if (offset != 0x0 && 250 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 251 (IS_VENDOR_8812A_C_CUT(rtlhal->version)))) 252 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0); 253 return retvalue; 254 } 255 256 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw, 257 enum radio_path rfpath, u32 offset, 258 u32 data) 259 { 260 struct rtl_priv *rtlpriv = rtl_priv(hw); 261 struct rtl_phy *rtlphy = &rtlpriv->phy; 262 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 263 u32 data_and_addr; 264 u32 newoffset; 265 266 if (RT_CANNOT_IO(hw)) { 267 pr_err("stop\n"); 268 return; 269 } 270 offset &= 0xff; 271 newoffset = offset; 272 data_and_addr = ((newoffset << 20) | 273 (data & 0x000fffff)) & 0x0fffffff; 274 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 275 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 276 "RFW-%d Addr[0x%x]=0x%x\n", 277 rfpath, pphyreg->rf3wire_offset, data_and_addr); 278 } 279 280 bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw) 281 { 282 bool rtstatus = 0; 283 284 rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw); 285 286 return rtstatus; 287 } 288 289 bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw) 290 { 291 bool rtstatus = true; 292 struct rtl_priv *rtlpriv = rtl_priv(hw); 293 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 294 struct rtl_phy *rtlphy = &rtlpriv->phy; 295 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 296 u8 regval; 297 u8 crystal_cap; 298 299 phy_init_bb_rf_register_definition(hw); 300 301 regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 302 regval |= FEN_PCIEA; 303 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval); 304 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 305 regval | FEN_BB_GLB_RSTN | FEN_BBRSTB); 306 307 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7); 308 rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7); 309 310 rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw); 311 312 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 313 crystal_cap = rtlefuse->crystalcap & 0x3F; 314 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000, 315 (crystal_cap | (crystal_cap << 6))); 316 } else { 317 crystal_cap = rtlefuse->crystalcap & 0x3F; 318 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, 319 (crystal_cap | (crystal_cap << 6))); 320 } 321 rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837); 322 323 return rtstatus; 324 } 325 326 bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw) 327 { 328 return rtl8821ae_phy_rf6052_config(hw); 329 } 330 331 static void _rtl8812ae_phy_set_rfe_reg_24g(struct ieee80211_hw *hw) 332 { 333 struct rtl_priv *rtlpriv = rtl_priv(hw); 334 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 335 u8 tmp; 336 337 switch (rtlhal->rfe_type) { 338 case 3: 339 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337770); 340 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337770); 341 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 342 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 343 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1); 344 break; 345 case 4: 346 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777); 347 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777); 348 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x001); 349 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x001); 350 break; 351 case 5: 352 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x77); 353 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777); 354 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3); 355 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp & ~0x1); 356 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 357 break; 358 case 1: 359 if (rtlpriv->btcoexist.bt_coexistence) { 360 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x777777); 361 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 362 0x77777777); 363 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000); 364 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 365 break; 366 } 367 fallthrough; 368 case 0: 369 case 2: 370 default: 371 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777); 372 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777); 373 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000); 374 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 375 break; 376 } 377 } 378 379 static void _rtl8812ae_phy_set_rfe_reg_5g(struct ieee80211_hw *hw) 380 { 381 struct rtl_priv *rtlpriv = rtl_priv(hw); 382 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 383 u8 tmp; 384 385 switch (rtlhal->rfe_type) { 386 case 0: 387 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337717); 388 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337717); 389 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 390 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 391 break; 392 case 1: 393 if (rtlpriv->btcoexist.bt_coexistence) { 394 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x337717); 395 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 396 0x77337717); 397 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000); 398 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 399 } else { 400 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 401 0x77337717); 402 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 403 0x77337717); 404 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000); 405 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 406 } 407 break; 408 case 3: 409 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337717); 410 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337717); 411 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 412 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 413 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1); 414 break; 415 case 5: 416 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x33); 417 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777); 418 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3); 419 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp | 0x1); 420 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 421 break; 422 case 2: 423 case 4: 424 default: 425 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777); 426 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777); 427 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 428 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 429 break; 430 } 431 } 432 433 u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band, 434 u8 rf_path) 435 { 436 struct rtl_priv *rtlpriv = rtl_priv(hw); 437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 438 struct rtl_dm *rtldm = rtl_dm(rtlpriv); 439 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 440 s8 reg_swing_2g = -1;/* 0xff; */ 441 s8 reg_swing_5g = -1;/* 0xff; */ 442 s8 swing_2g = -1 * reg_swing_2g; 443 s8 swing_5g = -1 * reg_swing_5g; 444 u32 out = 0x200; 445 const s8 auto_temp = -1; 446 447 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 448 "===> PHY_GetTXBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d,autoload_failflag=%d.\n", 449 (int)swing_2g, (int)swing_5g, 450 (int)rtlefuse->autoload_failflag); 451 452 if (rtlefuse->autoload_failflag) { 453 if (band == BAND_ON_2_4G) { 454 rtldm->swing_diff_2g = swing_2g; 455 if (swing_2g == 0) { 456 out = 0x200; /* 0 dB */ 457 } else if (swing_2g == -3) { 458 out = 0x16A; /* -3 dB */ 459 } else if (swing_2g == -6) { 460 out = 0x101; /* -6 dB */ 461 } else if (swing_2g == -9) { 462 out = 0x0B6; /* -9 dB */ 463 } else { 464 rtldm->swing_diff_2g = 0; 465 out = 0x200; 466 } 467 } else if (band == BAND_ON_5G) { 468 rtldm->swing_diff_5g = swing_5g; 469 if (swing_5g == 0) { 470 out = 0x200; /* 0 dB */ 471 } else if (swing_5g == -3) { 472 out = 0x16A; /* -3 dB */ 473 } else if (swing_5g == -6) { 474 out = 0x101; /* -6 dB */ 475 } else if (swing_5g == -9) { 476 out = 0x0B6; /* -9 dB */ 477 } else { 478 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 479 rtldm->swing_diff_5g = -3; 480 out = 0x16A; 481 } else { 482 rtldm->swing_diff_5g = 0; 483 out = 0x200; 484 } 485 } 486 } else { 487 rtldm->swing_diff_2g = -3; 488 rtldm->swing_diff_5g = -3; 489 out = 0x16A; /* -3 dB */ 490 } 491 } else { 492 u32 swing = 0, swing_a = 0, swing_b = 0; 493 494 if (band == BAND_ON_2_4G) { 495 if (reg_swing_2g == auto_temp) { 496 efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing); 497 swing = (swing == 0xFF) ? 0x00 : swing; 498 } else if (swing_2g == 0) { 499 swing = 0x00; /* 0 dB */ 500 } else if (swing_2g == -3) { 501 swing = 0x05; /* -3 dB */ 502 } else if (swing_2g == -6) { 503 swing = 0x0A; /* -6 dB */ 504 } else if (swing_2g == -9) { 505 swing = 0xFF; /* -9 dB */ 506 } else { 507 swing = 0x00; 508 } 509 } else { 510 if (reg_swing_5g == auto_temp) { 511 efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing); 512 swing = (swing == 0xFF) ? 0x00 : swing; 513 } else if (swing_5g == 0) { 514 swing = 0x00; /* 0 dB */ 515 } else if (swing_5g == -3) { 516 swing = 0x05; /* -3 dB */ 517 } else if (swing_5g == -6) { 518 swing = 0x0A; /* -6 dB */ 519 } else if (swing_5g == -9) { 520 swing = 0xFF; /* -9 dB */ 521 } else { 522 swing = 0x00; 523 } 524 } 525 526 swing_a = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */ 527 swing_b = (swing & 0xC) >> 2; /* 0xC6/C7[3:2] */ 528 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 529 "===> PHY_GetTXBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n", 530 swing_a, swing_b); 531 532 /* 3 Path-A */ 533 if (swing_a == 0x0) { 534 if (band == BAND_ON_2_4G) 535 rtldm->swing_diff_2g = 0; 536 else 537 rtldm->swing_diff_5g = 0; 538 out = 0x200; /* 0 dB */ 539 } else if (swing_a == 0x1) { 540 if (band == BAND_ON_2_4G) 541 rtldm->swing_diff_2g = -3; 542 else 543 rtldm->swing_diff_5g = -3; 544 out = 0x16A; /* -3 dB */ 545 } else if (swing_a == 0x2) { 546 if (band == BAND_ON_2_4G) 547 rtldm->swing_diff_2g = -6; 548 else 549 rtldm->swing_diff_5g = -6; 550 out = 0x101; /* -6 dB */ 551 } else if (swing_a == 0x3) { 552 if (band == BAND_ON_2_4G) 553 rtldm->swing_diff_2g = -9; 554 else 555 rtldm->swing_diff_5g = -9; 556 out = 0x0B6; /* -9 dB */ 557 } 558 /* 3 Path-B */ 559 if (swing_b == 0x0) { 560 if (band == BAND_ON_2_4G) 561 rtldm->swing_diff_2g = 0; 562 else 563 rtldm->swing_diff_5g = 0; 564 out = 0x200; /* 0 dB */ 565 } else if (swing_b == 0x1) { 566 if (band == BAND_ON_2_4G) 567 rtldm->swing_diff_2g = -3; 568 else 569 rtldm->swing_diff_5g = -3; 570 out = 0x16A; /* -3 dB */ 571 } else if (swing_b == 0x2) { 572 if (band == BAND_ON_2_4G) 573 rtldm->swing_diff_2g = -6; 574 else 575 rtldm->swing_diff_5g = -6; 576 out = 0x101; /* -6 dB */ 577 } else if (swing_b == 0x3) { 578 if (band == BAND_ON_2_4G) 579 rtldm->swing_diff_2g = -9; 580 else 581 rtldm->swing_diff_5g = -9; 582 out = 0x0B6; /* -9 dB */ 583 } 584 } 585 586 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 587 "<=== PHY_GetTXBBSwing_8812A, out = 0x%X\n", out); 588 return out; 589 } 590 591 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) 592 { 593 struct rtl_priv *rtlpriv = rtl_priv(hw); 594 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 595 struct rtl_dm *rtldm = rtl_dm(rtlpriv); 596 u8 current_band = rtlhal->current_bandtype; 597 s8 bb_diff_between_band; 598 599 rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0); 600 rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000); 601 rtlhal->current_bandtype = (enum band_type) band; 602 /* reconfig BB/RF according to wireless mode */ 603 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 604 /* BB & RF Config */ 605 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03); 606 607 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 608 /* 0xCB0[15:12] = 0x7 (LNA_On)*/ 609 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7); 610 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/ 611 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7); 612 } 613 614 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 615 /*0x834[1:0] = 0x1*/ 616 rtl_set_bbreg(hw, 0x834, 0x3, 0x1); 617 } 618 619 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 620 /* 0xC1C[11:8] = 0 */ 621 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0); 622 } else { 623 /* 0x82C[1:0] = 2b'00 */ 624 rtl_set_bbreg(hw, 0x82c, 0x3, 0); 625 } 626 627 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 628 _rtl8812ae_phy_set_rfe_reg_24g(hw); 629 630 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1); 631 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1); 632 633 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0); 634 } else {/* 5G band */ 635 u16 count, reg_41a; 636 637 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 638 /*0xCB0[15:12] = 0x5 (LNA_On)*/ 639 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5); 640 /*0xCB0[7:4] = 0x4 (PAPE_A)*/ 641 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4); 642 } 643 /*CCK_CHECK_en*/ 644 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80); 645 646 count = 0; 647 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 648 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 649 "Reg41A value %d\n", reg_41a); 650 reg_41a &= 0x30; 651 while ((reg_41a != 0x30) && (count < 50)) { 652 udelay(50); 653 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "Delay 50us\n"); 654 655 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 656 reg_41a &= 0x30; 657 count++; 658 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 659 "Reg41A value %d\n", reg_41a); 660 } 661 if (count != 0) 662 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 663 "PHY_SwitchWirelessBand8812(): Switch to 5G Band. Count = %d reg41A=0x%x\n", 664 count, reg_41a); 665 666 /* 2012/02/01, Sinda add registry to switch workaround 667 without long-run verification for scan issue. */ 668 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03); 669 670 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 671 /*0x834[1:0] = 0x2*/ 672 rtl_set_bbreg(hw, 0x834, 0x3, 0x2); 673 } 674 675 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 676 /* AGC table select */ 677 /* 0xC1C[11:8] = 1*/ 678 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1); 679 } else 680 /* 0x82C[1:0] = 2'b00 */ 681 rtl_set_bbreg(hw, 0x82c, 0x3, 1); 682 683 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 684 _rtl8812ae_phy_set_rfe_reg_5g(hw); 685 686 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0); 687 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf); 688 689 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 690 "==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n", 691 rtlpriv->dm.ofdm_index[RF90_PATH_A]); 692 } 693 694 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 695 (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) { 696 /* 0xC1C[31:21] */ 697 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, 698 phy_get_tx_swing_8812A(hw, band, RF90_PATH_A)); 699 /* 0xE1C[31:21] */ 700 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000, 701 phy_get_tx_swing_8812A(hw, band, RF90_PATH_B)); 702 703 /* <20121005, Kordan> When TxPowerTrack is ON, 704 * we should take care of the change of BB swing. 705 * That is, reset all info to trigger Tx power tracking. 706 */ 707 if (band != current_band) { 708 bb_diff_between_band = 709 (rtldm->swing_diff_2g - rtldm->swing_diff_5g); 710 bb_diff_between_band = (band == BAND_ON_2_4G) ? 711 bb_diff_between_band : 712 (-1 * bb_diff_between_band); 713 rtldm->default_ofdm_index += bb_diff_between_band * 2; 714 } 715 rtl8821ae_dm_clear_txpower_tracking_state(hw); 716 } 717 718 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 719 "<==%s():Switch Band OK.\n", __func__); 720 return; 721 } 722 723 static bool _rtl8821ae_check_positive(struct ieee80211_hw *hw, 724 const u32 condition1, 725 const u32 condition2) 726 { 727 struct rtl_priv *rtlpriv = rtl_priv(hw); 728 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 729 u32 cut_ver = ((rtlhal->version & CHIP_VER_RTL_MASK) 730 >> CHIP_VER_RTL_SHIFT); 731 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); 732 733 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ 734 ((rtlhal->board_type & BIT(3)) >> 3) << 1 | /* _GPA */ 735 ((rtlhal->board_type & BIT(7)) >> 7) << 2 | /* _ALNA */ 736 ((rtlhal->board_type & BIT(6)) >> 6) << 3 | /* _APA */ 737 ((rtlhal->board_type & BIT(2)) >> 2) << 4; /* _BT */ 738 739 u32 cond1 = condition1, cond2 = condition2; 740 u32 driver1 = cut_ver << 24 | /* CUT ver */ 741 0 << 20 | /* interface 2/2 */ 742 0x04 << 16 | /* platform */ 743 rtlhal->package_type << 12 | 744 intf << 8 | /* interface 1/2 */ 745 board_type; 746 747 u32 driver2 = rtlhal->type_glna << 0 | 748 rtlhal->type_gpa << 8 | 749 rtlhal->type_alna << 16 | 750 rtlhal->type_apa << 24; 751 752 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 753 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n", 754 cond1, cond2); 755 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 756 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n", 757 driver1, driver2); 758 759 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 760 " (Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf); 761 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 762 " (Board, Package) = (0x%X, 0x%X)\n", 763 rtlhal->board_type, rtlhal->package_type); 764 765 /*============== Value Defined Check ===============*/ 766 /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ 767 768 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != 769 (driver1 & 0x0000F000))) 770 return false; 771 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != 772 (driver1 & 0x0F000000))) 773 return false; 774 775 /*=============== Bit Defined Check ================*/ 776 /* We don't care [31:28] */ 777 778 cond1 &= 0x00FF0FFF; 779 driver1 &= 0x00FF0FFF; 780 781 if ((cond1 & driver1) == cond1) { 782 u32 mask = 0; 783 784 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ 785 return true; 786 787 if ((cond1 & BIT(0)) != 0) /*GLNA*/ 788 mask |= 0x000000FF; 789 if ((cond1 & BIT(1)) != 0) /*GPA*/ 790 mask |= 0x0000FF00; 791 if ((cond1 & BIT(2)) != 0) /*ALNA*/ 792 mask |= 0x00FF0000; 793 if ((cond1 & BIT(3)) != 0) /*APA*/ 794 mask |= 0xFF000000; 795 796 /* BoardType of each RF path is matched*/ 797 if ((cond2 & mask) == (driver2 & mask)) 798 return true; 799 else 800 return false; 801 } else 802 return false; 803 } 804 805 static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw, 806 const u32 condition) 807 { 808 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 809 u32 _board = rtlefuse->board_type; /*need efuse define*/ 810 u32 _interface = 0x01; /* ODM_ITRF_PCIE */ 811 u32 _platform = 0x08;/* ODM_WIN */ 812 u32 cond = condition; 813 814 if (condition == 0xCDCDCDCD) 815 return true; 816 817 cond = condition & 0xFF; 818 if ((_board != cond) && cond != 0xFF) 819 return false; 820 821 cond = condition & 0xFF00; 822 cond = cond >> 8; 823 if ((_interface & cond) == 0 && cond != 0x07) 824 return false; 825 826 cond = condition & 0xFF0000; 827 cond = cond >> 16; 828 if ((_platform & cond) == 0 && cond != 0x0F) 829 return false; 830 return true; 831 } 832 833 static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw, 834 u32 addr, u32 data, 835 enum radio_path rfpath, u32 regaddr) 836 { 837 if (addr == 0xfe || addr == 0xffe) { 838 /* In order not to disturb BT music when 839 * wifi init.(1ant NIC only) 840 */ 841 mdelay(50); 842 } else { 843 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); 844 udelay(1); 845 } 846 } 847 848 static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw, 849 u32 addr, u32 data) 850 { 851 u32 content = 0x1000; /*RF Content: radio_a_txt*/ 852 u32 maskforphyset = (u32)(content & 0xE000); 853 854 _rtl8821ae_config_rf_reg(hw, addr, data, 855 RF90_PATH_A, addr | maskforphyset); 856 } 857 858 static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw, 859 u32 addr, u32 data) 860 { 861 u32 content = 0x1001; /*RF Content: radio_b_txt*/ 862 u32 maskforphyset = (u32)(content & 0xE000); 863 864 _rtl8821ae_config_rf_reg(hw, addr, data, 865 RF90_PATH_B, addr | maskforphyset); 866 } 867 868 static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw, 869 u32 addr, u32 data) 870 { 871 if (addr == 0xfe) 872 mdelay(50); 873 else if (addr == 0xfd) 874 mdelay(5); 875 else if (addr == 0xfc) 876 mdelay(1); 877 else if (addr == 0xfb) 878 udelay(50); 879 else if (addr == 0xfa) 880 udelay(5); 881 else if (addr == 0xf9) 882 udelay(1); 883 else 884 rtl_set_bbreg(hw, addr, MASKDWORD, data); 885 886 udelay(1); 887 } 888 889 static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) 890 { 891 struct rtl_priv *rtlpriv = rtl_priv(hw); 892 struct rtl_phy *rtlphy = &rtlpriv->phy; 893 u8 band, rfpath, txnum, rate_section; 894 895 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) 896 for (rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath) 897 for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum) 898 for (rate_section = 0; 899 rate_section < TX_PWR_BY_RATE_NUM_SECTION; 900 ++rate_section) 901 rtlphy->tx_power_by_rate_offset[band] 902 [rfpath][txnum][rate_section] = 0; 903 } 904 905 static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, 906 u8 band, u8 path, 907 u8 rate_section, 908 u8 txnum, u8 value) 909 { 910 struct rtl_priv *rtlpriv = rtl_priv(hw); 911 struct rtl_phy *rtlphy = &rtlpriv->phy; 912 913 if (path > RF90_PATH_D) { 914 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 915 "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path); 916 return; 917 } 918 919 if (band == BAND_ON_2_4G) { 920 switch (rate_section) { 921 case CCK: 922 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value; 923 break; 924 case OFDM: 925 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value; 926 break; 927 case HT_MCS0_MCS7: 928 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value; 929 break; 930 case HT_MCS8_MCS15: 931 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value; 932 break; 933 case VHT_1SSMCS0_1SSMCS9: 934 rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value; 935 break; 936 case VHT_2SSMCS0_2SSMCS9: 937 rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value; 938 break; 939 default: 940 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 941 "Invalid RateSection %d in Band 2.4G,Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n", 942 rate_section, path, txnum); 943 break; 944 } 945 } else if (band == BAND_ON_5G) { 946 switch (rate_section) { 947 case OFDM: 948 rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value; 949 break; 950 case HT_MCS0_MCS7: 951 rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value; 952 break; 953 case HT_MCS8_MCS15: 954 rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value; 955 break; 956 case VHT_1SSMCS0_1SSMCS9: 957 rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value; 958 break; 959 case VHT_2SSMCS0_2SSMCS9: 960 rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value; 961 break; 962 default: 963 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 964 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n", 965 rate_section, path, txnum); 966 break; 967 } 968 } else { 969 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 970 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band); 971 } 972 } 973 974 static u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, 975 u8 band, u8 path, 976 u8 txnum, u8 rate_section) 977 { 978 struct rtl_priv *rtlpriv = rtl_priv(hw); 979 struct rtl_phy *rtlphy = &rtlpriv->phy; 980 u8 value = 0; 981 982 if (path > RF90_PATH_D) { 983 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 984 "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n", 985 path); 986 return 0; 987 } 988 989 if (band == BAND_ON_2_4G) { 990 switch (rate_section) { 991 case CCK: 992 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0]; 993 break; 994 case OFDM: 995 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1]; 996 break; 997 case HT_MCS0_MCS7: 998 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2]; 999 break; 1000 case HT_MCS8_MCS15: 1001 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3]; 1002 break; 1003 case VHT_1SSMCS0_1SSMCS9: 1004 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4]; 1005 break; 1006 case VHT_2SSMCS0_2SSMCS9: 1007 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5]; 1008 break; 1009 default: 1010 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1011 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n", 1012 rate_section, path, txnum); 1013 break; 1014 } 1015 } else if (band == BAND_ON_5G) { 1016 switch (rate_section) { 1017 case OFDM: 1018 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0]; 1019 break; 1020 case HT_MCS0_MCS7: 1021 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1]; 1022 break; 1023 case HT_MCS8_MCS15: 1024 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2]; 1025 break; 1026 case VHT_1SSMCS0_1SSMCS9: 1027 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3]; 1028 break; 1029 case VHT_2SSMCS0_2SSMCS9: 1030 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4]; 1031 break; 1032 default: 1033 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1034 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n", 1035 rate_section, path, txnum); 1036 break; 1037 } 1038 } else { 1039 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1040 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band); 1041 } 1042 1043 return value; 1044 } 1045 1046 static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) 1047 { 1048 struct rtl_priv *rtlpriv = rtl_priv(hw); 1049 struct rtl_phy *rtlphy = &rtlpriv->phy; 1050 u16 rawvalue = 0; 1051 u8 base = 0, path = 0; 1052 1053 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) { 1054 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF; 1055 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1056 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base); 1057 1058 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF; 1059 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1060 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base); 1061 1062 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF; 1063 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1064 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base); 1065 1066 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF; 1067 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1068 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base); 1069 1070 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF; 1071 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1072 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); 1073 1074 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF; 1075 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1076 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); 1077 1078 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF; 1079 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1080 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base); 1081 1082 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF; 1083 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1084 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base); 1085 1086 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF; 1087 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1088 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base); 1089 1090 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF; 1091 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1092 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); 1093 1094 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF; 1095 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1096 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); 1097 } 1098 } 1099 1100 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start, 1101 u8 end, u8 base_val) 1102 { 1103 int i; 1104 u8 temp_value = 0; 1105 u32 temp_data = 0; 1106 1107 for (i = 3; i >= 0; --i) { 1108 if (i >= start && i <= end) { 1109 /* Get the exact value */ 1110 temp_value = (u8)(*data >> (i * 8)) & 0xF; 1111 temp_value += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10; 1112 1113 /* Change the value to a relative value */ 1114 temp_value = (temp_value > base_val) ? temp_value - 1115 base_val : base_val - temp_value; 1116 } else { 1117 temp_value = (u8)(*data >> (i * 8)) & 0xFF; 1118 } 1119 temp_data <<= 8; 1120 temp_data |= temp_value; 1121 } 1122 *data = temp_data; 1123 } 1124 1125 static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw) 1126 { 1127 struct rtl_priv *rtlpriv = rtl_priv(hw); 1128 struct rtl_phy *rtlphy = &rtlpriv->phy; 1129 u8 regulation, bw, channel, rate_section; 1130 s8 temp_pwrlmt = 0; 1131 1132 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { 1133 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { 1134 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) { 1135 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) { 1136 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation] 1137 [bw][rate_section][channel][RF90_PATH_A]; 1138 if (temp_pwrlmt == MAX_POWER_INDEX) { 1139 if (bw == 0 || bw == 1) { /*5G 20M 40M VHT and HT can cross reference*/ 1140 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1141 "No power limit table of the specified band %d, bandwidth %d, ratesection %d, channel %d, rf path %d\n", 1142 1, bw, rate_section, channel, RF90_PATH_A); 1143 if (rate_section == 2) { 1144 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A] = 1145 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A]; 1146 } else if (rate_section == 4) { 1147 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A] = 1148 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A]; 1149 } else if (rate_section == 3) { 1150 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A] = 1151 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A]; 1152 } else if (rate_section == 5) { 1153 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A] = 1154 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A]; 1155 } 1156 1157 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1158 "use other value %d\n", 1159 temp_pwrlmt); 1160 } 1161 } 1162 } 1163 } 1164 } 1165 } 1166 } 1167 1168 static u8 _rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw *hw, 1169 enum band_type band, u8 rate) 1170 { 1171 struct rtl_priv *rtlpriv = rtl_priv(hw); 1172 u8 index = 0; 1173 if (band == BAND_ON_2_4G) { 1174 switch (rate) { 1175 case MGN_1M: 1176 case MGN_2M: 1177 case MGN_5_5M: 1178 case MGN_11M: 1179 index = 0; 1180 break; 1181 1182 case MGN_6M: 1183 case MGN_9M: 1184 case MGN_12M: 1185 case MGN_18M: 1186 case MGN_24M: 1187 case MGN_36M: 1188 case MGN_48M: 1189 case MGN_54M: 1190 index = 1; 1191 break; 1192 1193 case MGN_MCS0: 1194 case MGN_MCS1: 1195 case MGN_MCS2: 1196 case MGN_MCS3: 1197 case MGN_MCS4: 1198 case MGN_MCS5: 1199 case MGN_MCS6: 1200 case MGN_MCS7: 1201 index = 2; 1202 break; 1203 1204 case MGN_MCS8: 1205 case MGN_MCS9: 1206 case MGN_MCS10: 1207 case MGN_MCS11: 1208 case MGN_MCS12: 1209 case MGN_MCS13: 1210 case MGN_MCS14: 1211 case MGN_MCS15: 1212 index = 3; 1213 break; 1214 1215 default: 1216 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1217 "Wrong rate 0x%x to obtain index in 2.4G in PHY_GetTxPowerByRateBaseIndex()\n", 1218 rate); 1219 break; 1220 } 1221 } else if (band == BAND_ON_5G) { 1222 switch (rate) { 1223 case MGN_6M: 1224 case MGN_9M: 1225 case MGN_12M: 1226 case MGN_18M: 1227 case MGN_24M: 1228 case MGN_36M: 1229 case MGN_48M: 1230 case MGN_54M: 1231 index = 0; 1232 break; 1233 1234 case MGN_MCS0: 1235 case MGN_MCS1: 1236 case MGN_MCS2: 1237 case MGN_MCS3: 1238 case MGN_MCS4: 1239 case MGN_MCS5: 1240 case MGN_MCS6: 1241 case MGN_MCS7: 1242 index = 1; 1243 break; 1244 1245 case MGN_MCS8: 1246 case MGN_MCS9: 1247 case MGN_MCS10: 1248 case MGN_MCS11: 1249 case MGN_MCS12: 1250 case MGN_MCS13: 1251 case MGN_MCS14: 1252 case MGN_MCS15: 1253 index = 2; 1254 break; 1255 1256 case MGN_VHT1SS_MCS0: 1257 case MGN_VHT1SS_MCS1: 1258 case MGN_VHT1SS_MCS2: 1259 case MGN_VHT1SS_MCS3: 1260 case MGN_VHT1SS_MCS4: 1261 case MGN_VHT1SS_MCS5: 1262 case MGN_VHT1SS_MCS6: 1263 case MGN_VHT1SS_MCS7: 1264 case MGN_VHT1SS_MCS8: 1265 case MGN_VHT1SS_MCS9: 1266 index = 3; 1267 break; 1268 1269 case MGN_VHT2SS_MCS0: 1270 case MGN_VHT2SS_MCS1: 1271 case MGN_VHT2SS_MCS2: 1272 case MGN_VHT2SS_MCS3: 1273 case MGN_VHT2SS_MCS4: 1274 case MGN_VHT2SS_MCS5: 1275 case MGN_VHT2SS_MCS6: 1276 case MGN_VHT2SS_MCS7: 1277 case MGN_VHT2SS_MCS8: 1278 case MGN_VHT2SS_MCS9: 1279 index = 4; 1280 break; 1281 1282 default: 1283 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1284 "Wrong rate 0x%x to obtain index in 5G in PHY_GetTxPowerByRateBaseIndex()\n", 1285 rate); 1286 break; 1287 } 1288 } 1289 1290 return index; 1291 } 1292 1293 static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw) 1294 { 1295 struct rtl_priv *rtlpriv = rtl_priv(hw); 1296 struct rtl_phy *rtlphy = &rtlpriv->phy; 1297 u8 bw40_pwr_base_dbm2_4G, bw40_pwr_base_dbm5G; 1298 u8 regulation, bw, channel, rate_section; 1299 u8 base_index2_4G = 0; 1300 u8 base_index5G = 0; 1301 s8 temp_value = 0, temp_pwrlmt = 0; 1302 u8 rf_path = 0; 1303 1304 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1305 "=====> _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n"); 1306 1307 _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw); 1308 1309 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { 1310 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { 1311 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) { 1312 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) { 1313 /* obtain the base dBm values in 2.4G band 1314 CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15*/ 1315 if (rate_section == 0) { /*CCK*/ 1316 base_index2_4G = 1317 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1318 BAND_ON_2_4G, MGN_11M); 1319 } else if (rate_section == 1) { /*OFDM*/ 1320 base_index2_4G = 1321 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1322 BAND_ON_2_4G, MGN_54M); 1323 } else if (rate_section == 2) { /*HT IT*/ 1324 base_index2_4G = 1325 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1326 BAND_ON_2_4G, MGN_MCS7); 1327 } else if (rate_section == 3) { /*HT 2T*/ 1328 base_index2_4G = 1329 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1330 BAND_ON_2_4G, MGN_MCS15); 1331 } 1332 1333 temp_pwrlmt = rtlphy->txpwr_limit_2_4g[regulation] 1334 [bw][rate_section][channel][RF90_PATH_A]; 1335 1336 for (rf_path = RF90_PATH_A; 1337 rf_path < MAX_RF_PATH_NUM; 1338 ++rf_path) { 1339 if (rate_section == 3) 1340 bw40_pwr_base_dbm2_4G = 1341 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_2TX][base_index2_4G]; 1342 else 1343 bw40_pwr_base_dbm2_4G = 1344 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_1TX][base_index2_4G]; 1345 1346 if (temp_pwrlmt != MAX_POWER_INDEX) { 1347 temp_value = temp_pwrlmt - bw40_pwr_base_dbm2_4G; 1348 rtlphy->txpwr_limit_2_4g[regulation] 1349 [bw][rate_section][channel][rf_path] = 1350 temp_value; 1351 } 1352 1353 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1354 "TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfpath %d] %d)\n", 1355 regulation, bw, rate_section, channel, 1356 rtlphy->txpwr_limit_2_4g[regulation][bw] 1357 [rate_section][channel][rf_path], (temp_pwrlmt == 63) 1358 ? 0 : temp_pwrlmt/2, channel, rf_path, 1359 bw40_pwr_base_dbm2_4G); 1360 } 1361 } 1362 } 1363 } 1364 } 1365 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { 1366 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { 1367 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) { 1368 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) { 1369 /* obtain the base dBm values in 5G band 1370 OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15, 1371 VHT => 1SSMCS7, VHT 2T => 2SSMCS7*/ 1372 if (rate_section == 1) { /*OFDM*/ 1373 base_index5G = 1374 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1375 BAND_ON_5G, MGN_54M); 1376 } else if (rate_section == 2) { /*HT 1T*/ 1377 base_index5G = 1378 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1379 BAND_ON_5G, MGN_MCS7); 1380 } else if (rate_section == 3) { /*HT 2T*/ 1381 base_index5G = 1382 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1383 BAND_ON_5G, MGN_MCS15); 1384 } else if (rate_section == 4) { /*VHT 1T*/ 1385 base_index5G = 1386 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1387 BAND_ON_5G, MGN_VHT1SS_MCS7); 1388 } else if (rate_section == 5) { /*VHT 2T*/ 1389 base_index5G = 1390 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1391 BAND_ON_5G, MGN_VHT2SS_MCS7); 1392 } 1393 1394 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation] 1395 [bw][rate_section][channel] 1396 [RF90_PATH_A]; 1397 1398 for (rf_path = RF90_PATH_A; 1399 rf_path < MAX_RF_PATH_NUM; 1400 ++rf_path) { 1401 if (rate_section == 3 || rate_section == 5) 1402 bw40_pwr_base_dbm5G = 1403 rtlphy->txpwr_by_rate_base_5g[rf_path] 1404 [RF_2TX][base_index5G]; 1405 else 1406 bw40_pwr_base_dbm5G = 1407 rtlphy->txpwr_by_rate_base_5g[rf_path] 1408 [RF_1TX][base_index5G]; 1409 1410 if (temp_pwrlmt != MAX_POWER_INDEX) { 1411 temp_value = 1412 temp_pwrlmt - bw40_pwr_base_dbm5G; 1413 rtlphy->txpwr_limit_5g[regulation] 1414 [bw][rate_section][channel] 1415 [rf_path] = temp_value; 1416 } 1417 1418 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1419 "TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfpath %d] %d)\n", 1420 regulation, bw, rate_section, 1421 channel, rtlphy->txpwr_limit_5g[regulation] 1422 [bw][rate_section][channel][rf_path], 1423 temp_pwrlmt, channel, rf_path, bw40_pwr_base_dbm5G); 1424 } 1425 } 1426 } 1427 } 1428 } 1429 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1430 "<===== %s()\n", __func__); 1431 } 1432 1433 static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw *hw) 1434 { 1435 struct rtl_priv *rtlpriv = rtl_priv(hw); 1436 struct rtl_phy *rtlphy = &rtlpriv->phy; 1437 u8 i, j, k, l, m; 1438 1439 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1440 "=====>`%s()!\n", __func__); 1441 1442 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 1443 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) 1444 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) 1445 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m) 1446 for (l = 0; l < MAX_RF_PATH_NUM; ++l) 1447 rtlphy->txpwr_limit_2_4g 1448 [i][j][k][m][l] 1449 = MAX_POWER_INDEX; 1450 } 1451 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 1452 for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) 1453 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) 1454 for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m) 1455 for (l = 0; l < MAX_RF_PATH_NUM; ++l) 1456 rtlphy->txpwr_limit_5g 1457 [i][j][k][m][l] 1458 = MAX_POWER_INDEX; 1459 } 1460 1461 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1462 "<===== %s()!\n", __func__); 1463 } 1464 1465 static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw) 1466 { 1467 struct rtl_priv *rtlpriv = rtl_priv(hw); 1468 struct rtl_phy *rtlphy = &rtlpriv->phy; 1469 u8 base = 0, rfpath = 0; 1470 1471 for (rfpath = RF90_PATH_A; rfpath <= RF90_PATH_B; ++rfpath) { 1472 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, CCK); 1473 _phy_convert_txpower_dbm_to_relative_value( 1474 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0], 1475 0, 3, base); 1476 1477 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, OFDM); 1478 _phy_convert_txpower_dbm_to_relative_value( 1479 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][1], 1480 0, 3, base); 1481 _phy_convert_txpower_dbm_to_relative_value( 1482 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][2], 1483 0, 3, base); 1484 1485 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, HT_MCS0_MCS7); 1486 _phy_convert_txpower_dbm_to_relative_value( 1487 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][3], 1488 0, 3, base); 1489 _phy_convert_txpower_dbm_to_relative_value( 1490 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][4], 1491 0, 3, base); 1492 1493 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, HT_MCS8_MCS15); 1494 1495 _phy_convert_txpower_dbm_to_relative_value( 1496 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][5], 1497 0, 3, base); 1498 1499 _phy_convert_txpower_dbm_to_relative_value( 1500 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][6], 1501 0, 3, base); 1502 1503 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9); 1504 _phy_convert_txpower_dbm_to_relative_value( 1505 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][7], 1506 0, 3, base); 1507 _phy_convert_txpower_dbm_to_relative_value( 1508 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][8], 1509 0, 3, base); 1510 _phy_convert_txpower_dbm_to_relative_value( 1511 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9], 1512 0, 1, base); 1513 1514 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9); 1515 _phy_convert_txpower_dbm_to_relative_value( 1516 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9], 1517 2, 3, base); 1518 _phy_convert_txpower_dbm_to_relative_value( 1519 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][10], 1520 0, 3, base); 1521 _phy_convert_txpower_dbm_to_relative_value( 1522 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][11], 1523 0, 3, base); 1524 1525 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, OFDM); 1526 _phy_convert_txpower_dbm_to_relative_value( 1527 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][1], 1528 0, 3, base); 1529 _phy_convert_txpower_dbm_to_relative_value( 1530 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][2], 1531 0, 3, base); 1532 1533 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, HT_MCS0_MCS7); 1534 _phy_convert_txpower_dbm_to_relative_value( 1535 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][3], 1536 0, 3, base); 1537 _phy_convert_txpower_dbm_to_relative_value( 1538 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][4], 1539 0, 3, base); 1540 1541 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, HT_MCS8_MCS15); 1542 _phy_convert_txpower_dbm_to_relative_value( 1543 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][5], 1544 0, 3, base); 1545 _phy_convert_txpower_dbm_to_relative_value( 1546 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][6], 1547 0, 3, base); 1548 1549 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9); 1550 _phy_convert_txpower_dbm_to_relative_value( 1551 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][7], 1552 0, 3, base); 1553 _phy_convert_txpower_dbm_to_relative_value( 1554 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][8], 1555 0, 3, base); 1556 _phy_convert_txpower_dbm_to_relative_value( 1557 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9], 1558 0, 1, base); 1559 1560 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9); 1561 _phy_convert_txpower_dbm_to_relative_value( 1562 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9], 1563 2, 3, base); 1564 _phy_convert_txpower_dbm_to_relative_value( 1565 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][10], 1566 0, 3, base); 1567 _phy_convert_txpower_dbm_to_relative_value( 1568 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][11], 1569 0, 3, base); 1570 } 1571 1572 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 1573 "<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n"); 1574 } 1575 1576 static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw) 1577 { 1578 _rtl8821ae_phy_store_txpower_by_rate_base(hw); 1579 _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw); 1580 } 1581 1582 /* string is in decimal */ 1583 static bool _rtl8812ae_get_integer_from_string(const char *str, u8 *pint) 1584 { 1585 u16 i = 0; 1586 *pint = 0; 1587 1588 while (str[i] != '\0') { 1589 if (str[i] >= '0' && str[i] <= '9') { 1590 *pint *= 10; 1591 *pint += (str[i] - '0'); 1592 } else { 1593 return false; 1594 } 1595 ++i; 1596 } 1597 1598 return true; 1599 } 1600 1601 static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw, 1602 u8 band, u8 channel) 1603 { 1604 struct rtl_priv *rtlpriv = rtl_priv(hw); 1605 s8 channel_index = -1; 1606 u8 i = 0; 1607 1608 if (band == BAND_ON_2_4G) 1609 channel_index = channel - 1; 1610 else if (band == BAND_ON_5G) { 1611 for (i = 0; i < sizeof(channel5g)/sizeof(u8); ++i) { 1612 if (channel5g[i] == channel) 1613 channel_index = i; 1614 } 1615 } else 1616 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Band %d in %s\n", 1617 band, __func__); 1618 1619 if (channel_index == -1) 1620 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 1621 "Invalid Channel %d of Band %d in %s\n", channel, 1622 band, __func__); 1623 1624 return channel_index; 1625 } 1626 1627 static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, 1628 const char *pregulation, 1629 const char *pband, const char *pbandwidth, 1630 const char *prate_section, const char *prf_path, 1631 const char *pchannel, const char *ppower_limit) 1632 { 1633 struct rtl_priv *rtlpriv = rtl_priv(hw); 1634 struct rtl_phy *rtlphy = &rtlpriv->phy; 1635 u8 regulation = 0, bandwidth = 0, rate_section = 0, channel; 1636 u8 channel_index; 1637 s8 power_limit = 0, prev_power_limit, ret; 1638 1639 if (!_rtl8812ae_get_integer_from_string(pchannel, &channel) || 1640 !_rtl8812ae_get_integer_from_string(ppower_limit, 1641 &power_limit)) { 1642 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1643 "Illegal index of pwr_lmt table [chnl %d][val %d]\n", 1644 channel, power_limit); 1645 } 1646 1647 power_limit = power_limit > MAX_POWER_INDEX ? 1648 MAX_POWER_INDEX : power_limit; 1649 1650 if (strcmp(pregulation, "FCC") == 0) 1651 regulation = 0; 1652 else if (strcmp(pregulation, "MKK") == 0) 1653 regulation = 1; 1654 else if (strcmp(pregulation, "ETSI") == 0) 1655 regulation = 2; 1656 else if (strcmp(pregulation, "WW13") == 0) 1657 regulation = 3; 1658 1659 if (strcmp(prate_section, "CCK") == 0) 1660 rate_section = 0; 1661 else if (strcmp(prate_section, "OFDM") == 0) 1662 rate_section = 1; 1663 else if (strcmp(prate_section, "HT") == 0 && 1664 strcmp(prf_path, "1T") == 0) 1665 rate_section = 2; 1666 else if (strcmp(prate_section, "HT") == 0 && 1667 strcmp(prf_path, "2T") == 0) 1668 rate_section = 3; 1669 else if (strcmp(prate_section, "VHT") == 0 && 1670 strcmp(prf_path, "1T") == 0) 1671 rate_section = 4; 1672 else if (strcmp(prate_section, "VHT") == 0 && 1673 strcmp(prf_path, "2T") == 0) 1674 rate_section = 5; 1675 1676 if (strcmp(pbandwidth, "20M") == 0) 1677 bandwidth = 0; 1678 else if (strcmp(pbandwidth, "40M") == 0) 1679 bandwidth = 1; 1680 else if (strcmp(pbandwidth, "80M") == 0) 1681 bandwidth = 2; 1682 else if (strcmp(pbandwidth, "160M") == 0) 1683 bandwidth = 3; 1684 1685 if (strcmp(pband, "2.4G") == 0) { 1686 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 1687 BAND_ON_2_4G, 1688 channel); 1689 1690 if (ret == -1) 1691 return; 1692 1693 channel_index = ret; 1694 1695 prev_power_limit = rtlphy->txpwr_limit_2_4g[regulation] 1696 [bandwidth][rate_section] 1697 [channel_index][RF90_PATH_A]; 1698 1699 if (power_limit < prev_power_limit) 1700 rtlphy->txpwr_limit_2_4g[regulation][bandwidth] 1701 [rate_section][channel_index][RF90_PATH_A] = 1702 power_limit; 1703 1704 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1705 "2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n", 1706 regulation, bandwidth, rate_section, channel_index, 1707 rtlphy->txpwr_limit_2_4g[regulation][bandwidth] 1708 [rate_section][channel_index][RF90_PATH_A]); 1709 } else if (strcmp(pband, "5G") == 0) { 1710 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 1711 BAND_ON_5G, 1712 channel); 1713 1714 if (ret == -1) 1715 return; 1716 1717 channel_index = ret; 1718 1719 prev_power_limit = rtlphy->txpwr_limit_5g[regulation][bandwidth] 1720 [rate_section][channel_index] 1721 [RF90_PATH_A]; 1722 1723 if (power_limit < prev_power_limit) 1724 rtlphy->txpwr_limit_5g[regulation][bandwidth] 1725 [rate_section][channel_index][RF90_PATH_A] = power_limit; 1726 1727 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1728 "5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n", 1729 regulation, bandwidth, rate_section, channel, 1730 rtlphy->txpwr_limit_5g[regulation][bandwidth] 1731 [rate_section][channel_index][RF90_PATH_A]); 1732 } else { 1733 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1734 "Cannot recognize the band info in %s\n", pband); 1735 return; 1736 } 1737 } 1738 1739 static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw, 1740 const char *regulation, const char *band, 1741 const char *bandwidth, const char *rate_section, 1742 const char *rf_path, const char *channel, 1743 const char *power_limit) 1744 { 1745 _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth, 1746 rate_section, rf_path, channel, 1747 power_limit); 1748 } 1749 1750 static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw) 1751 { 1752 struct rtl_priv *rtlpriv = rtl_priv(hw); 1753 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1754 u32 i = 0; 1755 u32 array_len; 1756 const char **array; 1757 1758 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1759 array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN; 1760 array = RTL8812AE_TXPWR_LMT; 1761 } else { 1762 array_len = RTL8821AE_TXPWR_LMT_ARRAY_LEN; 1763 array = RTL8821AE_TXPWR_LMT; 1764 } 1765 1766 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n"); 1767 1768 for (i = 0; i < array_len; i += 7) { 1769 const char *regulation = array[i]; 1770 const char *band = array[i+1]; 1771 const char *bandwidth = array[i+2]; 1772 const char *rate = array[i+3]; 1773 const char *rf_path = array[i+4]; 1774 const char *chnl = array[i+5]; 1775 const char *val = array[i+6]; 1776 1777 _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band, 1778 bandwidth, rate, rf_path, 1779 chnl, val); 1780 } 1781 } 1782 1783 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw) 1784 { 1785 struct rtl_priv *rtlpriv = rtl_priv(hw); 1786 struct rtl_phy *rtlphy = &rtlpriv->phy; 1787 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1788 bool rtstatus; 1789 1790 _rtl8821ae_phy_init_txpower_limit(hw); 1791 1792 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */ 1793 if (rtlefuse->eeprom_regulatory != 2) 1794 _rtl8821ae_phy_read_and_config_txpwr_lmt(hw); 1795 1796 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw, 1797 BASEBAND_CONFIG_PHY_REG); 1798 if (!rtstatus) { 1799 pr_err("Write BB Reg Fail!!\n"); 1800 return false; 1801 } 1802 _rtl8821ae_phy_init_tx_power_by_rate(hw); 1803 if (!rtlefuse->autoload_failflag) { 1804 rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw, 1805 BASEBAND_CONFIG_PHY_REG); 1806 } 1807 if (!rtstatus) { 1808 pr_err("BB_PG Reg Fail!!\n"); 1809 return false; 1810 } 1811 1812 _rtl8821ae_phy_txpower_by_rate_configuration(hw); 1813 1814 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */ 1815 if (rtlefuse->eeprom_regulatory != 2) 1816 _rtl8812ae_phy_convert_txpower_limit_to_power_index(hw); 1817 1818 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw, 1819 BASEBAND_CONFIG_AGC_TAB); 1820 1821 if (!rtstatus) { 1822 pr_err("AGC Table Fail\n"); 1823 return false; 1824 } 1825 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, 1826 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 1827 return true; 1828 } 1829 1830 static bool 1831 __rtl8821ae_phy_config_with_headerfile(struct ieee80211_hw *hw, 1832 u32 *array_table, u16 arraylen, 1833 void (*set_reg)(struct ieee80211_hw *hw, 1834 u32 regaddr, u32 data)) 1835 { 1836 #define COND_ELSE 2 1837 #define COND_ENDIF 3 1838 1839 int i = 0; 1840 u8 cond; 1841 bool matched = true, skipped = false; 1842 1843 while ((i + 1) < arraylen) { 1844 u32 v1 = array_table[i]; 1845 u32 v2 = array_table[i + 1]; 1846 1847 if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ 1848 if (v1 & BIT(31)) {/* positive condition*/ 1849 cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); 1850 if (cond == COND_ENDIF) {/*end*/ 1851 matched = true; 1852 skipped = false; 1853 } else if (cond == COND_ELSE) /*else*/ 1854 matched = skipped ? false : true; 1855 else {/*if , else if*/ 1856 if (skipped) { 1857 matched = false; 1858 } else { 1859 if (_rtl8821ae_check_positive( 1860 hw, v1, v2)) { 1861 matched = true; 1862 skipped = true; 1863 } else { 1864 matched = false; 1865 skipped = false; 1866 } 1867 } 1868 } 1869 } else if (v1 & BIT(30)) { /*negative condition*/ 1870 /*do nothing*/ 1871 } 1872 } else { 1873 if (matched) 1874 set_reg(hw, v1, v2); 1875 } 1876 i = i + 2; 1877 } 1878 1879 return true; 1880 } 1881 1882 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) 1883 { 1884 struct rtl_priv *rtlpriv = rtl_priv(hw); 1885 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1886 u32 arraylength; 1887 u32 *ptrarray; 1888 1889 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read MAC_REG_Array\n"); 1890 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1891 arraylength = RTL8821AE_MAC_1T_ARRAYLEN; 1892 ptrarray = RTL8821AE_MAC_REG_ARRAY; 1893 } else { 1894 arraylength = RTL8812AE_MAC_1T_ARRAYLEN; 1895 ptrarray = RTL8812AE_MAC_REG_ARRAY; 1896 } 1897 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1898 "Img: MAC_REG_ARRAY LEN %d\n", arraylength); 1899 1900 return __rtl8821ae_phy_config_with_headerfile(hw, 1901 ptrarray, arraylength, rtl_write_byte_with_val32); 1902 } 1903 1904 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 1905 u8 configtype) 1906 { 1907 struct rtl_priv *rtlpriv = rtl_priv(hw); 1908 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1909 u32 *array_table; 1910 u16 arraylen; 1911 1912 if (configtype == BASEBAND_CONFIG_PHY_REG) { 1913 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1914 arraylen = RTL8812AE_PHY_REG_1TARRAYLEN; 1915 array_table = RTL8812AE_PHY_REG_ARRAY; 1916 } else { 1917 arraylen = RTL8821AE_PHY_REG_1TARRAYLEN; 1918 array_table = RTL8821AE_PHY_REG_ARRAY; 1919 } 1920 1921 return __rtl8821ae_phy_config_with_headerfile(hw, 1922 array_table, arraylen, 1923 _rtl8821ae_config_bb_reg); 1924 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 1925 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1926 arraylen = RTL8812AE_AGC_TAB_1TARRAYLEN; 1927 array_table = RTL8812AE_AGC_TAB_ARRAY; 1928 } else { 1929 arraylen = RTL8821AE_AGC_TAB_1TARRAYLEN; 1930 array_table = RTL8821AE_AGC_TAB_ARRAY; 1931 } 1932 1933 return __rtl8821ae_phy_config_with_headerfile(hw, 1934 array_table, arraylen, 1935 rtl_set_bbreg_with_dwmask); 1936 } 1937 return true; 1938 } 1939 1940 static u8 _rtl8821ae_get_rate_section_index(u32 regaddr) 1941 { 1942 u8 index = 0; 1943 regaddr &= 0xFFF; 1944 if (regaddr >= 0xC20 && regaddr <= 0xC4C) 1945 index = (u8)((regaddr - 0xC20) / 4); 1946 else if (regaddr >= 0xE20 && regaddr <= 0xE4C) 1947 index = (u8)((regaddr - 0xE20) / 4); 1948 else 1949 WARN_ONCE(true, 1950 "rtl8821ae: Invalid RegAddr 0x%x\n", regaddr); 1951 return index; 1952 } 1953 1954 static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw, 1955 u32 band, u32 rfpath, 1956 u32 txnum, u32 regaddr, 1957 u32 bitmask, u32 data) 1958 { 1959 struct rtl_priv *rtlpriv = rtl_priv(hw); 1960 struct rtl_phy *rtlphy = &rtlpriv->phy; 1961 u8 rate_section = _rtl8821ae_get_rate_section_index(regaddr); 1962 1963 if (band != BAND_ON_2_4G && band != BAND_ON_5G) { 1964 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid Band %d\n", band); 1965 band = BAND_ON_2_4G; 1966 } 1967 if (rfpath >= MAX_RF_PATH) { 1968 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid RfPath %d\n", rfpath); 1969 rfpath = MAX_RF_PATH - 1; 1970 } 1971 if (txnum >= MAX_RF_PATH) { 1972 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid TxNum %d\n", txnum); 1973 txnum = MAX_RF_PATH - 1; 1974 } 1975 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data; 1976 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1977 "TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n", 1978 band, rfpath, txnum, rate_section, 1979 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]); 1980 } 1981 1982 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 1983 u8 configtype) 1984 { 1985 struct rtl_priv *rtlpriv = rtl_priv(hw); 1986 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1987 int i; 1988 u32 *array; 1989 u16 arraylen; 1990 u32 v1, v2, v3, v4, v5, v6; 1991 1992 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1993 arraylen = RTL8812AE_PHY_REG_ARRAY_PGLEN; 1994 array = RTL8812AE_PHY_REG_ARRAY_PG; 1995 } else { 1996 arraylen = RTL8821AE_PHY_REG_ARRAY_PGLEN; 1997 array = RTL8821AE_PHY_REG_ARRAY_PG; 1998 } 1999 2000 if (configtype != BASEBAND_CONFIG_PHY_REG) { 2001 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, 2002 "configtype != BaseBand_Config_PHY_REG\n"); 2003 return true; 2004 } 2005 for (i = 0; i < arraylen; i += 6) { 2006 v1 = array[i]; 2007 v2 = array[i+1]; 2008 v3 = array[i+2]; 2009 v4 = array[i+3]; 2010 v5 = array[i+4]; 2011 v6 = array[i+5]; 2012 2013 if (v1 < 0xCDCDCDCD) { 2014 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE && 2015 (v4 == 0xfe || v4 == 0xffe)) { 2016 msleep(50); 2017 continue; 2018 } 2019 2020 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2021 if (v4 == 0xfe) 2022 msleep(50); 2023 else if (v4 == 0xfd) 2024 mdelay(5); 2025 else if (v4 == 0xfc) 2026 mdelay(1); 2027 else if (v4 == 0xfb) 2028 udelay(50); 2029 else if (v4 == 0xfa) 2030 udelay(5); 2031 else if (v4 == 0xf9) 2032 udelay(1); 2033 } 2034 _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, 2035 v4, v5, v6); 2036 continue; 2037 } else { 2038 /*don't need the hw_body*/ 2039 if (!_rtl8821ae_check_condition(hw, v1)) { 2040 i += 2; /* skip the pair of expression*/ 2041 v1 = array[i]; 2042 v2 = array[i+1]; 2043 v3 = array[i+2]; 2044 while (v2 != 0xDEAD) { 2045 i += 3; 2046 v1 = array[i]; 2047 v2 = array[i+1]; 2048 v3 = array[i+2]; 2049 } 2050 } 2051 } 2052 } 2053 2054 return true; 2055 } 2056 2057 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 2058 enum radio_path rfpath) 2059 { 2060 u32 *radioa_array_table_a, *radioa_array_table_b; 2061 u16 radioa_arraylen_a, radioa_arraylen_b; 2062 struct rtl_priv *rtlpriv = rtl_priv(hw); 2063 2064 radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN; 2065 radioa_array_table_a = RTL8812AE_RADIOA_ARRAY; 2066 radioa_arraylen_b = RTL8812AE_RADIOB_1TARRAYLEN; 2067 radioa_array_table_b = RTL8812AE_RADIOB_ARRAY; 2068 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2069 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen_a); 2070 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 2071 switch (rfpath) { 2072 case RF90_PATH_A: 2073 return __rtl8821ae_phy_config_with_headerfile(hw, 2074 radioa_array_table_a, radioa_arraylen_a, 2075 _rtl8821ae_config_rf_radio_a); 2076 case RF90_PATH_B: 2077 return __rtl8821ae_phy_config_with_headerfile(hw, 2078 radioa_array_table_b, radioa_arraylen_b, 2079 _rtl8821ae_config_rf_radio_b); 2080 case RF90_PATH_C: 2081 case RF90_PATH_D: 2082 pr_err("switch case %#x not processed\n", rfpath); 2083 break; 2084 } 2085 return true; 2086 } 2087 2088 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 2089 enum radio_path rfpath) 2090 { 2091 u32 *radioa_array_table; 2092 u16 radioa_arraylen; 2093 struct rtl_priv *rtlpriv = rtl_priv(hw); 2094 2095 radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN; 2096 radioa_array_table = RTL8821AE_RADIOA_ARRAY; 2097 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2098 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen); 2099 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 2100 switch (rfpath) { 2101 case RF90_PATH_A: 2102 return __rtl8821ae_phy_config_with_headerfile(hw, 2103 radioa_array_table, radioa_arraylen, 2104 _rtl8821ae_config_rf_radio_a); 2105 2106 case RF90_PATH_B: 2107 case RF90_PATH_C: 2108 case RF90_PATH_D: 2109 pr_err("switch case %#x not processed\n", rfpath); 2110 break; 2111 } 2112 return true; 2113 } 2114 2115 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 2116 { 2117 struct rtl_priv *rtlpriv = rtl_priv(hw); 2118 struct rtl_phy *rtlphy = &rtlpriv->phy; 2119 2120 rtlphy->default_initialgain[0] = 2121 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 2122 rtlphy->default_initialgain[1] = 2123 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 2124 rtlphy->default_initialgain[2] = 2125 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 2126 rtlphy->default_initialgain[3] = 2127 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 2128 2129 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2130 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 2131 rtlphy->default_initialgain[0], 2132 rtlphy->default_initialgain[1], 2133 rtlphy->default_initialgain[2], 2134 rtlphy->default_initialgain[3]); 2135 2136 rtlphy->framesync = (u8)rtl_get_bbreg(hw, 2137 ROFDM0_RXDETECTOR3, MASKBYTE0); 2138 rtlphy->framesync_c34 = rtl_get_bbreg(hw, 2139 ROFDM0_RXDETECTOR2, MASKDWORD); 2140 2141 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2142 "Default framesync (0x%x) = 0x%x\n", 2143 ROFDM0_RXDETECTOR3, rtlphy->framesync); 2144 } 2145 2146 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 2147 { 2148 struct rtl_priv *rtlpriv = rtl_priv(hw); 2149 struct rtl_phy *rtlphy = &rtlpriv->phy; 2150 2151 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 2152 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 2153 2154 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 2155 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 2156 2157 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 2158 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 2159 2160 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A; 2161 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A; 2162 2163 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE; 2164 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE; 2165 2166 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8821A; 2167 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8821A; 2168 2169 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8821A; 2170 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8821A; 2171 } 2172 2173 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 2174 { 2175 struct rtl_priv *rtlpriv = rtl_priv(hw); 2176 struct rtl_phy *rtlphy = &rtlpriv->phy; 2177 u8 txpwr_level; 2178 long txpwr_dbm; 2179 2180 txpwr_level = rtlphy->cur_cck_txpwridx; 2181 txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw, 2182 WIRELESS_MODE_B, txpwr_level); 2183 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 2184 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw, 2185 WIRELESS_MODE_G, 2186 txpwr_level) > txpwr_dbm) 2187 txpwr_dbm = 2188 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 2189 txpwr_level); 2190 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 2191 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw, 2192 WIRELESS_MODE_N_24G, 2193 txpwr_level) > txpwr_dbm) 2194 txpwr_dbm = 2195 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 2196 txpwr_level); 2197 *powerlevel = txpwr_dbm; 2198 } 2199 2200 static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index) 2201 { 2202 u8 i = 0; 2203 bool in_24g = true; 2204 2205 if (channel <= 14) { 2206 in_24g = true; 2207 *chnl_index = channel - 1; 2208 } else { 2209 in_24g = false; 2210 2211 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; ++i) { 2212 if (channel5g[i] == channel) { 2213 *chnl_index = i; 2214 return in_24g; 2215 } 2216 } 2217 } 2218 return in_24g; 2219 } 2220 2221 static s8 _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate) 2222 { 2223 s8 rate_section = 0; 2224 switch (rate) { 2225 case DESC_RATE1M: 2226 case DESC_RATE2M: 2227 case DESC_RATE5_5M: 2228 case DESC_RATE11M: 2229 rate_section = 0; 2230 break; 2231 case DESC_RATE6M: 2232 case DESC_RATE9M: 2233 case DESC_RATE12M: 2234 case DESC_RATE18M: 2235 rate_section = 1; 2236 break; 2237 case DESC_RATE24M: 2238 case DESC_RATE36M: 2239 case DESC_RATE48M: 2240 case DESC_RATE54M: 2241 rate_section = 2; 2242 break; 2243 case DESC_RATEMCS0: 2244 case DESC_RATEMCS1: 2245 case DESC_RATEMCS2: 2246 case DESC_RATEMCS3: 2247 rate_section = 3; 2248 break; 2249 case DESC_RATEMCS4: 2250 case DESC_RATEMCS5: 2251 case DESC_RATEMCS6: 2252 case DESC_RATEMCS7: 2253 rate_section = 4; 2254 break; 2255 case DESC_RATEMCS8: 2256 case DESC_RATEMCS9: 2257 case DESC_RATEMCS10: 2258 case DESC_RATEMCS11: 2259 rate_section = 5; 2260 break; 2261 case DESC_RATEMCS12: 2262 case DESC_RATEMCS13: 2263 case DESC_RATEMCS14: 2264 case DESC_RATEMCS15: 2265 rate_section = 6; 2266 break; 2267 case DESC_RATEVHT1SS_MCS0: 2268 case DESC_RATEVHT1SS_MCS1: 2269 case DESC_RATEVHT1SS_MCS2: 2270 case DESC_RATEVHT1SS_MCS3: 2271 rate_section = 7; 2272 break; 2273 case DESC_RATEVHT1SS_MCS4: 2274 case DESC_RATEVHT1SS_MCS5: 2275 case DESC_RATEVHT1SS_MCS6: 2276 case DESC_RATEVHT1SS_MCS7: 2277 rate_section = 8; 2278 break; 2279 case DESC_RATEVHT1SS_MCS8: 2280 case DESC_RATEVHT1SS_MCS9: 2281 case DESC_RATEVHT2SS_MCS0: 2282 case DESC_RATEVHT2SS_MCS1: 2283 rate_section = 9; 2284 break; 2285 case DESC_RATEVHT2SS_MCS2: 2286 case DESC_RATEVHT2SS_MCS3: 2287 case DESC_RATEVHT2SS_MCS4: 2288 case DESC_RATEVHT2SS_MCS5: 2289 rate_section = 10; 2290 break; 2291 case DESC_RATEVHT2SS_MCS6: 2292 case DESC_RATEVHT2SS_MCS7: 2293 case DESC_RATEVHT2SS_MCS8: 2294 case DESC_RATEVHT2SS_MCS9: 2295 rate_section = 11; 2296 break; 2297 default: 2298 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n"); 2299 break; 2300 } 2301 2302 return rate_section; 2303 } 2304 2305 static s8 _rtl8812ae_phy_get_world_wide_limit(s8 *limit_table) 2306 { 2307 s8 min = limit_table[0]; 2308 u8 i = 0; 2309 2310 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 2311 if (limit_table[i] < min) 2312 min = limit_table[i]; 2313 } 2314 return min; 2315 } 2316 2317 static s8 _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw *hw, 2318 u8 band, 2319 enum ht_channel_width bandwidth, 2320 enum radio_path rf_path, 2321 u8 rate, u8 channel) 2322 { 2323 struct rtl_priv *rtlpriv = rtl_priv(hw); 2324 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 2325 struct rtl_phy *rtlphy = &rtlpriv->phy; 2326 short band_temp = -1, regulation = -1, bandwidth_temp = -1, 2327 rate_section = -1, channel_temp = -1; 2328 u16 regu, bdwidth, sec, chnl; 2329 s8 power_limit = MAX_POWER_INDEX; 2330 2331 if (rtlefuse->eeprom_regulatory == 2) 2332 return MAX_POWER_INDEX; 2333 2334 regulation = TXPWR_LMT_WW; 2335 2336 if (band == BAND_ON_2_4G) 2337 band_temp = 0; 2338 else if (band == BAND_ON_5G) 2339 band_temp = 1; 2340 2341 if (bandwidth == HT_CHANNEL_WIDTH_20) 2342 bandwidth_temp = 0; 2343 else if (bandwidth == HT_CHANNEL_WIDTH_20_40) 2344 bandwidth_temp = 1; 2345 else if (bandwidth == HT_CHANNEL_WIDTH_80) 2346 bandwidth_temp = 2; 2347 2348 switch (rate) { 2349 case DESC_RATE1M: 2350 case DESC_RATE2M: 2351 case DESC_RATE5_5M: 2352 case DESC_RATE11M: 2353 rate_section = 0; 2354 break; 2355 case DESC_RATE6M: 2356 case DESC_RATE9M: 2357 case DESC_RATE12M: 2358 case DESC_RATE18M: 2359 case DESC_RATE24M: 2360 case DESC_RATE36M: 2361 case DESC_RATE48M: 2362 case DESC_RATE54M: 2363 rate_section = 1; 2364 break; 2365 case DESC_RATEMCS0: 2366 case DESC_RATEMCS1: 2367 case DESC_RATEMCS2: 2368 case DESC_RATEMCS3: 2369 case DESC_RATEMCS4: 2370 case DESC_RATEMCS5: 2371 case DESC_RATEMCS6: 2372 case DESC_RATEMCS7: 2373 rate_section = 2; 2374 break; 2375 case DESC_RATEMCS8: 2376 case DESC_RATEMCS9: 2377 case DESC_RATEMCS10: 2378 case DESC_RATEMCS11: 2379 case DESC_RATEMCS12: 2380 case DESC_RATEMCS13: 2381 case DESC_RATEMCS14: 2382 case DESC_RATEMCS15: 2383 rate_section = 3; 2384 break; 2385 case DESC_RATEVHT1SS_MCS0: 2386 case DESC_RATEVHT1SS_MCS1: 2387 case DESC_RATEVHT1SS_MCS2: 2388 case DESC_RATEVHT1SS_MCS3: 2389 case DESC_RATEVHT1SS_MCS4: 2390 case DESC_RATEVHT1SS_MCS5: 2391 case DESC_RATEVHT1SS_MCS6: 2392 case DESC_RATEVHT1SS_MCS7: 2393 case DESC_RATEVHT1SS_MCS8: 2394 case DESC_RATEVHT1SS_MCS9: 2395 rate_section = 4; 2396 break; 2397 case DESC_RATEVHT2SS_MCS0: 2398 case DESC_RATEVHT2SS_MCS1: 2399 case DESC_RATEVHT2SS_MCS2: 2400 case DESC_RATEVHT2SS_MCS3: 2401 case DESC_RATEVHT2SS_MCS4: 2402 case DESC_RATEVHT2SS_MCS5: 2403 case DESC_RATEVHT2SS_MCS6: 2404 case DESC_RATEVHT2SS_MCS7: 2405 case DESC_RATEVHT2SS_MCS8: 2406 case DESC_RATEVHT2SS_MCS9: 2407 rate_section = 5; 2408 break; 2409 default: 2410 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2411 "Wrong rate 0x%x\n", rate); 2412 break; 2413 } 2414 2415 if (band_temp == BAND_ON_5G && rate_section == 0) 2416 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2417 "Wrong rate 0x%x: No CCK in 5G Band\n", rate); 2418 2419 /*workaround for wrong index combination to obtain tx power limit, 2420 OFDM only exists in BW 20M*/ 2421 if (rate_section == 1) 2422 bandwidth_temp = 0; 2423 2424 /*workaround for wrong index combination to obtain tx power limit, 2425 *HT on 80M will reference to HT on 40M 2426 */ 2427 if ((rate_section == 2 || rate_section == 3) && band == BAND_ON_5G && 2428 bandwidth_temp == 2) 2429 bandwidth_temp = 1; 2430 2431 if (band == BAND_ON_2_4G) 2432 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 2433 BAND_ON_2_4G, channel); 2434 else if (band == BAND_ON_5G) 2435 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 2436 BAND_ON_5G, channel); 2437 else if (band == BAND_ON_BOTH) { 2438 ;/* BAND_ON_BOTH don't care temporarily */ 2439 } 2440 2441 if (band_temp == -1 || regulation == -1 || bandwidth_temp == -1 || 2442 rate_section == -1 || channel_temp == -1) { 2443 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2444 "Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n", 2445 band_temp, regulation, bandwidth_temp, rf_path, 2446 rate_section, channel_temp); 2447 return MAX_POWER_INDEX; 2448 } 2449 2450 regu = regulation; 2451 bdwidth = bandwidth_temp; 2452 sec = rate_section; 2453 chnl = channel_temp; 2454 2455 if (band == BAND_ON_2_4G) { 2456 s8 limits[10] = {0}; 2457 u8 i; 2458 2459 for (i = 0; i < 4; ++i) 2460 limits[i] = rtlphy->txpwr_limit_2_4g[i][bdwidth] 2461 [sec][chnl][rf_path]; 2462 2463 power_limit = (regulation == TXPWR_LMT_WW) ? 2464 _rtl8812ae_phy_get_world_wide_limit(limits) : 2465 rtlphy->txpwr_limit_2_4g[regu][bdwidth] 2466 [sec][chnl][rf_path]; 2467 } else if (band == BAND_ON_5G) { 2468 s8 limits[10] = {0}; 2469 u8 i; 2470 2471 for (i = 0; i < MAX_REGULATION_NUM; ++i) 2472 limits[i] = rtlphy->txpwr_limit_5g[i][bdwidth] 2473 [sec][chnl][rf_path]; 2474 2475 power_limit = (regulation == TXPWR_LMT_WW) ? 2476 _rtl8812ae_phy_get_world_wide_limit(limits) : 2477 rtlphy->txpwr_limit_5g[regu][chnl] 2478 [sec][chnl][rf_path]; 2479 } else { 2480 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2481 "No power limit table of the specified band\n"); 2482 } 2483 return power_limit; 2484 } 2485 2486 static s8 _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw, 2487 u8 band, u8 path, u8 rate) 2488 { 2489 struct rtl_priv *rtlpriv = rtl_priv(hw); 2490 struct rtl_phy *rtlphy = &rtlpriv->phy; 2491 u8 shift = 0, rate_section, tx_num; 2492 s8 tx_pwr_diff = 0; 2493 s8 limit = 0; 2494 2495 rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate); 2496 tx_num = RF_TX_NUM_NONIMPLEMENT; 2497 2498 if (tx_num == RF_TX_NUM_NONIMPLEMENT) { 2499 if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) || 2500 (rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9)) 2501 tx_num = RF_2TX; 2502 else 2503 tx_num = RF_1TX; 2504 } 2505 2506 switch (rate) { 2507 case DESC_RATE1M: 2508 case DESC_RATE6M: 2509 case DESC_RATE24M: 2510 case DESC_RATEMCS0: 2511 case DESC_RATEMCS4: 2512 case DESC_RATEMCS8: 2513 case DESC_RATEMCS12: 2514 case DESC_RATEVHT1SS_MCS0: 2515 case DESC_RATEVHT1SS_MCS4: 2516 case DESC_RATEVHT1SS_MCS8: 2517 case DESC_RATEVHT2SS_MCS2: 2518 case DESC_RATEVHT2SS_MCS6: 2519 shift = 0; 2520 break; 2521 case DESC_RATE2M: 2522 case DESC_RATE9M: 2523 case DESC_RATE36M: 2524 case DESC_RATEMCS1: 2525 case DESC_RATEMCS5: 2526 case DESC_RATEMCS9: 2527 case DESC_RATEMCS13: 2528 case DESC_RATEVHT1SS_MCS1: 2529 case DESC_RATEVHT1SS_MCS5: 2530 case DESC_RATEVHT1SS_MCS9: 2531 case DESC_RATEVHT2SS_MCS3: 2532 case DESC_RATEVHT2SS_MCS7: 2533 shift = 8; 2534 break; 2535 case DESC_RATE5_5M: 2536 case DESC_RATE12M: 2537 case DESC_RATE48M: 2538 case DESC_RATEMCS2: 2539 case DESC_RATEMCS6: 2540 case DESC_RATEMCS10: 2541 case DESC_RATEMCS14: 2542 case DESC_RATEVHT1SS_MCS2: 2543 case DESC_RATEVHT1SS_MCS6: 2544 case DESC_RATEVHT2SS_MCS0: 2545 case DESC_RATEVHT2SS_MCS4: 2546 case DESC_RATEVHT2SS_MCS8: 2547 shift = 16; 2548 break; 2549 case DESC_RATE11M: 2550 case DESC_RATE18M: 2551 case DESC_RATE54M: 2552 case DESC_RATEMCS3: 2553 case DESC_RATEMCS7: 2554 case DESC_RATEMCS11: 2555 case DESC_RATEMCS15: 2556 case DESC_RATEVHT1SS_MCS3: 2557 case DESC_RATEVHT1SS_MCS7: 2558 case DESC_RATEVHT2SS_MCS1: 2559 case DESC_RATEVHT2SS_MCS5: 2560 case DESC_RATEVHT2SS_MCS9: 2561 shift = 24; 2562 break; 2563 default: 2564 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n"); 2565 break; 2566 } 2567 2568 tx_pwr_diff = (u8)(rtlphy->tx_power_by_rate_offset[band][path] 2569 [tx_num][rate_section] >> shift) & 0xff; 2570 2571 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */ 2572 if (rtlpriv->efuse.eeprom_regulatory != 2) { 2573 limit = _rtl8812ae_phy_get_txpower_limit(hw, band, 2574 rtlphy->current_chan_bw, path, rate, 2575 rtlphy->current_channel); 2576 2577 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 || 2578 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) { 2579 if (limit < 0) { 2580 if (tx_pwr_diff < (-limit)) 2581 tx_pwr_diff = -limit; 2582 } 2583 } else { 2584 if (limit < 0) 2585 tx_pwr_diff = limit; 2586 else 2587 tx_pwr_diff = tx_pwr_diff > limit ? limit : tx_pwr_diff; 2588 } 2589 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 2590 "Maximum power by rate %d, final power by rate %d\n", 2591 limit, tx_pwr_diff); 2592 } 2593 2594 return tx_pwr_diff; 2595 } 2596 2597 static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path, 2598 u8 rate, u8 bandwidth, u8 channel) 2599 { 2600 struct rtl_priv *rtlpriv = rtl_priv(hw); 2601 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2602 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2603 u8 index = (channel - 1); 2604 u8 txpower = 0; 2605 bool in_24g = false; 2606 s8 powerdiff_byrate = 0; 2607 2608 if (((rtlhal->current_bandtype == BAND_ON_2_4G) && 2609 (channel > 14 || channel < 1)) || 2610 ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) { 2611 index = 0; 2612 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 2613 "Illegal channel!!\n"); 2614 } 2615 2616 in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index); 2617 if (in_24g) { 2618 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) 2619 txpower = rtlefuse->txpwrlevel_cck[path][index]; 2620 else if (DESC_RATE6M <= rate) 2621 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index]; 2622 else 2623 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "invalid rate\n"); 2624 2625 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && 2626 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) 2627 txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S]; 2628 2629 if (bandwidth == HT_CHANNEL_WIDTH_20) { 2630 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2631 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2632 txpower += rtlefuse->txpwr_ht20diff[path][TX_1S]; 2633 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2634 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2635 txpower += rtlefuse->txpwr_ht20diff[path][TX_2S]; 2636 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) { 2637 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2638 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2639 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S]; 2640 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2641 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2642 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S]; 2643 } else if (bandwidth == HT_CHANNEL_WIDTH_80) { 2644 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2645 (DESC_RATEVHT1SS_MCS0 <= rate && 2646 rate <= DESC_RATEVHT2SS_MCS9)) 2647 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S]; 2648 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2649 (DESC_RATEVHT2SS_MCS0 <= rate && 2650 rate <= DESC_RATEVHT2SS_MCS9)) 2651 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S]; 2652 } 2653 } else { 2654 if (DESC_RATE6M <= rate) 2655 txpower = rtlefuse->txpwr_5g_bw40base[path][index]; 2656 else 2657 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_WARNING, 2658 "INVALID Rate.\n"); 2659 2660 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && 2661 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) 2662 txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S]; 2663 2664 if (bandwidth == HT_CHANNEL_WIDTH_20) { 2665 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2666 (DESC_RATEVHT1SS_MCS0 <= rate && 2667 rate <= DESC_RATEVHT2SS_MCS9)) 2668 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S]; 2669 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2670 (DESC_RATEVHT2SS_MCS0 <= rate && 2671 rate <= DESC_RATEVHT2SS_MCS9)) 2672 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S]; 2673 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) { 2674 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2675 (DESC_RATEVHT1SS_MCS0 <= rate && 2676 rate <= DESC_RATEVHT2SS_MCS9)) 2677 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S]; 2678 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2679 (DESC_RATEVHT2SS_MCS0 <= rate && 2680 rate <= DESC_RATEVHT2SS_MCS9)) 2681 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S]; 2682 } else if (bandwidth == HT_CHANNEL_WIDTH_80) { 2683 u8 i; 2684 2685 for (i = 0; i < sizeof(channel5g_80m) / sizeof(u8); ++i) 2686 if (channel5g_80m[i] == channel) 2687 index = i; 2688 2689 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2690 (DESC_RATEVHT1SS_MCS0 <= rate && 2691 rate <= DESC_RATEVHT2SS_MCS9)) 2692 txpower = rtlefuse->txpwr_5g_bw80base[path][index] 2693 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S]; 2694 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2695 (DESC_RATEVHT2SS_MCS0 <= rate && 2696 rate <= DESC_RATEVHT2SS_MCS9)) 2697 txpower = rtlefuse->txpwr_5g_bw80base[path][index] 2698 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S] 2699 + rtlefuse->txpwr_5g_bw80diff[path][TX_2S]; 2700 } 2701 } 2702 if (rtlefuse->eeprom_regulatory != 2) 2703 powerdiff_byrate = 2704 _rtl8821ae_phy_get_txpower_by_rate(hw, (u8)(!in_24g), 2705 path, rate); 2706 2707 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 || 2708 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) 2709 txpower -= powerdiff_byrate; 2710 else 2711 txpower += powerdiff_byrate; 2712 2713 if (rate > DESC_RATE11M) 2714 txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path]; 2715 else 2716 txpower += rtlpriv->dm.remnant_cck_idx; 2717 2718 if (txpower > MAX_POWER_INDEX) 2719 txpower = MAX_POWER_INDEX; 2720 2721 return txpower; 2722 } 2723 2724 static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw, 2725 u8 power_index, u8 path, u8 rate) 2726 { 2727 struct rtl_priv *rtlpriv = rtl_priv(hw); 2728 2729 if (path == RF90_PATH_A) { 2730 switch (rate) { 2731 case DESC_RATE1M: 2732 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2733 MASKBYTE0, power_index); 2734 break; 2735 case DESC_RATE2M: 2736 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2737 MASKBYTE1, power_index); 2738 break; 2739 case DESC_RATE5_5M: 2740 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2741 MASKBYTE2, power_index); 2742 break; 2743 case DESC_RATE11M: 2744 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2745 MASKBYTE3, power_index); 2746 break; 2747 case DESC_RATE6M: 2748 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2749 MASKBYTE0, power_index); 2750 break; 2751 case DESC_RATE9M: 2752 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2753 MASKBYTE1, power_index); 2754 break; 2755 case DESC_RATE12M: 2756 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2757 MASKBYTE2, power_index); 2758 break; 2759 case DESC_RATE18M: 2760 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2761 MASKBYTE3, power_index); 2762 break; 2763 case DESC_RATE24M: 2764 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2765 MASKBYTE0, power_index); 2766 break; 2767 case DESC_RATE36M: 2768 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2769 MASKBYTE1, power_index); 2770 break; 2771 case DESC_RATE48M: 2772 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2773 MASKBYTE2, power_index); 2774 break; 2775 case DESC_RATE54M: 2776 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2777 MASKBYTE3, power_index); 2778 break; 2779 case DESC_RATEMCS0: 2780 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2781 MASKBYTE0, power_index); 2782 break; 2783 case DESC_RATEMCS1: 2784 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2785 MASKBYTE1, power_index); 2786 break; 2787 case DESC_RATEMCS2: 2788 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2789 MASKBYTE2, power_index); 2790 break; 2791 case DESC_RATEMCS3: 2792 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2793 MASKBYTE3, power_index); 2794 break; 2795 case DESC_RATEMCS4: 2796 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2797 MASKBYTE0, power_index); 2798 break; 2799 case DESC_RATEMCS5: 2800 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2801 MASKBYTE1, power_index); 2802 break; 2803 case DESC_RATEMCS6: 2804 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2805 MASKBYTE2, power_index); 2806 break; 2807 case DESC_RATEMCS7: 2808 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2809 MASKBYTE3, power_index); 2810 break; 2811 case DESC_RATEMCS8: 2812 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2813 MASKBYTE0, power_index); 2814 break; 2815 case DESC_RATEMCS9: 2816 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2817 MASKBYTE1, power_index); 2818 break; 2819 case DESC_RATEMCS10: 2820 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2821 MASKBYTE2, power_index); 2822 break; 2823 case DESC_RATEMCS11: 2824 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2825 MASKBYTE3, power_index); 2826 break; 2827 case DESC_RATEMCS12: 2828 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2829 MASKBYTE0, power_index); 2830 break; 2831 case DESC_RATEMCS13: 2832 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2833 MASKBYTE1, power_index); 2834 break; 2835 case DESC_RATEMCS14: 2836 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2837 MASKBYTE2, power_index); 2838 break; 2839 case DESC_RATEMCS15: 2840 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2841 MASKBYTE3, power_index); 2842 break; 2843 case DESC_RATEVHT1SS_MCS0: 2844 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2845 MASKBYTE0, power_index); 2846 break; 2847 case DESC_RATEVHT1SS_MCS1: 2848 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2849 MASKBYTE1, power_index); 2850 break; 2851 case DESC_RATEVHT1SS_MCS2: 2852 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2853 MASKBYTE2, power_index); 2854 break; 2855 case DESC_RATEVHT1SS_MCS3: 2856 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2857 MASKBYTE3, power_index); 2858 break; 2859 case DESC_RATEVHT1SS_MCS4: 2860 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2861 MASKBYTE0, power_index); 2862 break; 2863 case DESC_RATEVHT1SS_MCS5: 2864 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2865 MASKBYTE1, power_index); 2866 break; 2867 case DESC_RATEVHT1SS_MCS6: 2868 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2869 MASKBYTE2, power_index); 2870 break; 2871 case DESC_RATEVHT1SS_MCS7: 2872 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2873 MASKBYTE3, power_index); 2874 break; 2875 case DESC_RATEVHT1SS_MCS8: 2876 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2877 MASKBYTE0, power_index); 2878 break; 2879 case DESC_RATEVHT1SS_MCS9: 2880 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2881 MASKBYTE1, power_index); 2882 break; 2883 case DESC_RATEVHT2SS_MCS0: 2884 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2885 MASKBYTE2, power_index); 2886 break; 2887 case DESC_RATEVHT2SS_MCS1: 2888 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2889 MASKBYTE3, power_index); 2890 break; 2891 case DESC_RATEVHT2SS_MCS2: 2892 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2893 MASKBYTE0, power_index); 2894 break; 2895 case DESC_RATEVHT2SS_MCS3: 2896 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2897 MASKBYTE1, power_index); 2898 break; 2899 case DESC_RATEVHT2SS_MCS4: 2900 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2901 MASKBYTE2, power_index); 2902 break; 2903 case DESC_RATEVHT2SS_MCS5: 2904 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2905 MASKBYTE3, power_index); 2906 break; 2907 case DESC_RATEVHT2SS_MCS6: 2908 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2909 MASKBYTE0, power_index); 2910 break; 2911 case DESC_RATEVHT2SS_MCS7: 2912 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2913 MASKBYTE1, power_index); 2914 break; 2915 case DESC_RATEVHT2SS_MCS8: 2916 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2917 MASKBYTE2, power_index); 2918 break; 2919 case DESC_RATEVHT2SS_MCS9: 2920 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2921 MASKBYTE3, power_index); 2922 break; 2923 default: 2924 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2925 "Invalid Rate!!\n"); 2926 break; 2927 } 2928 } else if (path == RF90_PATH_B) { 2929 switch (rate) { 2930 case DESC_RATE1M: 2931 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2932 MASKBYTE0, power_index); 2933 break; 2934 case DESC_RATE2M: 2935 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2936 MASKBYTE1, power_index); 2937 break; 2938 case DESC_RATE5_5M: 2939 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2940 MASKBYTE2, power_index); 2941 break; 2942 case DESC_RATE11M: 2943 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2944 MASKBYTE3, power_index); 2945 break; 2946 case DESC_RATE6M: 2947 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2948 MASKBYTE0, power_index); 2949 break; 2950 case DESC_RATE9M: 2951 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2952 MASKBYTE1, power_index); 2953 break; 2954 case DESC_RATE12M: 2955 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2956 MASKBYTE2, power_index); 2957 break; 2958 case DESC_RATE18M: 2959 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2960 MASKBYTE3, power_index); 2961 break; 2962 case DESC_RATE24M: 2963 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2964 MASKBYTE0, power_index); 2965 break; 2966 case DESC_RATE36M: 2967 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2968 MASKBYTE1, power_index); 2969 break; 2970 case DESC_RATE48M: 2971 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2972 MASKBYTE2, power_index); 2973 break; 2974 case DESC_RATE54M: 2975 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2976 MASKBYTE3, power_index); 2977 break; 2978 case DESC_RATEMCS0: 2979 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 2980 MASKBYTE0, power_index); 2981 break; 2982 case DESC_RATEMCS1: 2983 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 2984 MASKBYTE1, power_index); 2985 break; 2986 case DESC_RATEMCS2: 2987 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 2988 MASKBYTE2, power_index); 2989 break; 2990 case DESC_RATEMCS3: 2991 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 2992 MASKBYTE3, power_index); 2993 break; 2994 case DESC_RATEMCS4: 2995 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 2996 MASKBYTE0, power_index); 2997 break; 2998 case DESC_RATEMCS5: 2999 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 3000 MASKBYTE1, power_index); 3001 break; 3002 case DESC_RATEMCS6: 3003 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 3004 MASKBYTE2, power_index); 3005 break; 3006 case DESC_RATEMCS7: 3007 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 3008 MASKBYTE3, power_index); 3009 break; 3010 case DESC_RATEMCS8: 3011 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3012 MASKBYTE0, power_index); 3013 break; 3014 case DESC_RATEMCS9: 3015 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3016 MASKBYTE1, power_index); 3017 break; 3018 case DESC_RATEMCS10: 3019 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3020 MASKBYTE2, power_index); 3021 break; 3022 case DESC_RATEMCS11: 3023 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3024 MASKBYTE3, power_index); 3025 break; 3026 case DESC_RATEMCS12: 3027 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3028 MASKBYTE0, power_index); 3029 break; 3030 case DESC_RATEMCS13: 3031 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3032 MASKBYTE1, power_index); 3033 break; 3034 case DESC_RATEMCS14: 3035 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3036 MASKBYTE2, power_index); 3037 break; 3038 case DESC_RATEMCS15: 3039 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3040 MASKBYTE3, power_index); 3041 break; 3042 case DESC_RATEVHT1SS_MCS0: 3043 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3044 MASKBYTE0, power_index); 3045 break; 3046 case DESC_RATEVHT1SS_MCS1: 3047 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3048 MASKBYTE1, power_index); 3049 break; 3050 case DESC_RATEVHT1SS_MCS2: 3051 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3052 MASKBYTE2, power_index); 3053 break; 3054 case DESC_RATEVHT1SS_MCS3: 3055 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3056 MASKBYTE3, power_index); 3057 break; 3058 case DESC_RATEVHT1SS_MCS4: 3059 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3060 MASKBYTE0, power_index); 3061 break; 3062 case DESC_RATEVHT1SS_MCS5: 3063 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3064 MASKBYTE1, power_index); 3065 break; 3066 case DESC_RATEVHT1SS_MCS6: 3067 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3068 MASKBYTE2, power_index); 3069 break; 3070 case DESC_RATEVHT1SS_MCS7: 3071 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3072 MASKBYTE3, power_index); 3073 break; 3074 case DESC_RATEVHT1SS_MCS8: 3075 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3076 MASKBYTE0, power_index); 3077 break; 3078 case DESC_RATEVHT1SS_MCS9: 3079 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3080 MASKBYTE1, power_index); 3081 break; 3082 case DESC_RATEVHT2SS_MCS0: 3083 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3084 MASKBYTE2, power_index); 3085 break; 3086 case DESC_RATEVHT2SS_MCS1: 3087 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3088 MASKBYTE3, power_index); 3089 break; 3090 case DESC_RATEVHT2SS_MCS2: 3091 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3092 MASKBYTE0, power_index); 3093 break; 3094 case DESC_RATEVHT2SS_MCS3: 3095 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3096 MASKBYTE1, power_index); 3097 break; 3098 case DESC_RATEVHT2SS_MCS4: 3099 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3100 MASKBYTE2, power_index); 3101 break; 3102 case DESC_RATEVHT2SS_MCS5: 3103 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3104 MASKBYTE3, power_index); 3105 break; 3106 case DESC_RATEVHT2SS_MCS6: 3107 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3108 MASKBYTE0, power_index); 3109 break; 3110 case DESC_RATEVHT2SS_MCS7: 3111 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3112 MASKBYTE1, power_index); 3113 break; 3114 case DESC_RATEVHT2SS_MCS8: 3115 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3116 MASKBYTE2, power_index); 3117 break; 3118 case DESC_RATEVHT2SS_MCS9: 3119 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3120 MASKBYTE3, power_index); 3121 break; 3122 default: 3123 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 3124 "Invalid Rate!!\n"); 3125 break; 3126 } 3127 } else { 3128 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 3129 "Invalid RFPath!!\n"); 3130 } 3131 } 3132 3133 static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, 3134 u8 *array, u8 path, 3135 u8 channel, u8 size) 3136 { 3137 struct rtl_priv *rtlpriv = rtl_priv(hw); 3138 struct rtl_phy *rtlphy = &rtlpriv->phy; 3139 u8 i; 3140 u8 power_index; 3141 3142 for (i = 0; i < size; i++) { 3143 power_index = 3144 _rtl8821ae_get_txpower_index(hw, path, array[i], 3145 rtlphy->current_chan_bw, 3146 channel); 3147 _rtl8821ae_phy_set_txpower_index(hw, power_index, path, 3148 array[i]); 3149 } 3150 } 3151 3152 static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw, 3153 u8 bw, u8 channel, u8 path) 3154 { 3155 struct rtl_priv *rtlpriv = rtl_priv(hw); 3156 struct rtl_phy *rtlphy = &rtlpriv->phy; 3157 3158 u8 i; 3159 u32 power_level, data, offset; 3160 3161 if (path >= rtlphy->num_total_rfpath) 3162 return; 3163 3164 data = 0; 3165 if (path == RF90_PATH_A) { 3166 power_level = 3167 _rtl8821ae_get_txpower_index(hw, RF90_PATH_A, 3168 DESC_RATEMCS7, bw, channel); 3169 offset = RA_TXPWRTRAING; 3170 } else { 3171 power_level = 3172 _rtl8821ae_get_txpower_index(hw, RF90_PATH_B, 3173 DESC_RATEMCS7, bw, channel); 3174 offset = RB_TXPWRTRAING; 3175 } 3176 3177 for (i = 0; i < 3; i++) { 3178 if (i == 0) 3179 power_level = power_level - 10; 3180 else if (i == 1) 3181 power_level = power_level - 8; 3182 else 3183 power_level = power_level - 6; 3184 3185 data |= (((power_level > 2) ? (power_level) : 2) << (i * 8)); 3186 } 3187 rtl_set_bbreg(hw, offset, 0xffffff, data); 3188 } 3189 3190 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, 3191 u8 channel, u8 path) 3192 { 3193 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */ 3194 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3195 struct rtl_priv *rtlpriv = rtl_priv(hw); 3196 struct rtl_phy *rtlphy = &rtlpriv->phy; 3197 u8 cck_rates[] = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, 3198 DESC_RATE11M}; 3199 u8 sizes_of_cck_retes = 4; 3200 u8 ofdm_rates[] = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, 3201 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M, 3202 DESC_RATE48M, DESC_RATE54M}; 3203 u8 sizes_of_ofdm_retes = 8; 3204 u8 ht_rates_1t[] = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, 3205 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5, 3206 DESC_RATEMCS6, DESC_RATEMCS7}; 3207 u8 sizes_of_ht_retes_1t = 8; 3208 u8 ht_rates_2t[] = {DESC_RATEMCS8, DESC_RATEMCS9, 3209 DESC_RATEMCS10, DESC_RATEMCS11, 3210 DESC_RATEMCS12, DESC_RATEMCS13, 3211 DESC_RATEMCS14, DESC_RATEMCS15}; 3212 u8 sizes_of_ht_retes_2t = 8; 3213 u8 vht_rates_1t[] = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, 3214 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, 3215 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5, 3216 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, 3217 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9}; 3218 u8 vht_rates_2t[] = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, 3219 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, 3220 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5, 3221 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, 3222 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9}; 3223 u8 sizes_of_vht_retes = 10; 3224 3225 if (rtlhal->current_bandtype == BAND_ON_2_4G) 3226 _rtl8821ae_phy_set_txpower_level_by_path(hw, cck_rates, path, channel, 3227 sizes_of_cck_retes); 3228 3229 _rtl8821ae_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel, 3230 sizes_of_ofdm_retes); 3231 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel, 3232 sizes_of_ht_retes_1t); 3233 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_1t, path, channel, 3234 sizes_of_vht_retes); 3235 3236 if (rtlphy->num_total_rfpath >= 2) { 3237 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_2t, path, 3238 channel, 3239 sizes_of_ht_retes_2t); 3240 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_2t, path, 3241 channel, 3242 sizes_of_vht_retes); 3243 } 3244 3245 _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw, 3246 channel, path); 3247 } 3248 3249 /*just in case, write txpower in DW, to reduce time*/ 3250 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 3251 { 3252 struct rtl_priv *rtlpriv = rtl_priv(hw); 3253 struct rtl_phy *rtlphy = &rtlpriv->phy; 3254 u8 path = 0; 3255 3256 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path) 3257 rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path); 3258 } 3259 3260 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 3261 enum wireless_mode wirelessmode, 3262 u8 txpwridx) 3263 { 3264 long offset; 3265 long pwrout_dbm; 3266 3267 switch (wirelessmode) { 3268 case WIRELESS_MODE_B: 3269 offset = -7; 3270 break; 3271 case WIRELESS_MODE_G: 3272 case WIRELESS_MODE_N_24G: 3273 offset = -8; 3274 break; 3275 default: 3276 offset = -8; 3277 break; 3278 } 3279 pwrout_dbm = txpwridx / 2 + offset; 3280 return pwrout_dbm; 3281 } 3282 3283 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) 3284 { 3285 struct rtl_priv *rtlpriv = rtl_priv(hw); 3286 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3287 enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 3288 3289 if (!is_hal_stop(rtlhal)) { 3290 switch (operation) { 3291 case SCAN_OPT_BACKUP_BAND0: 3292 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 3293 rtlpriv->cfg->ops->set_hw_reg(hw, 3294 HW_VAR_IO_CMD, 3295 (u8 *)&iotype); 3296 3297 break; 3298 case SCAN_OPT_BACKUP_BAND1: 3299 iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN; 3300 rtlpriv->cfg->ops->set_hw_reg(hw, 3301 HW_VAR_IO_CMD, 3302 (u8 *)&iotype); 3303 3304 break; 3305 case SCAN_OPT_RESTORE: 3306 iotype = IO_CMD_RESUME_DM_BY_SCAN; 3307 rtlpriv->cfg->ops->set_hw_reg(hw, 3308 HW_VAR_IO_CMD, 3309 (u8 *)&iotype); 3310 break; 3311 default: 3312 pr_err("Unknown Scan Backup operation.\n"); 3313 break; 3314 } 3315 } 3316 } 3317 3318 static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv *rtlpriv, u8 bw) 3319 { 3320 u16 reg_rf_mode_bw, tmp = 0; 3321 3322 reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL); 3323 switch (bw) { 3324 case HT_CHANNEL_WIDTH_20: 3325 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F); 3326 break; 3327 case HT_CHANNEL_WIDTH_20_40: 3328 tmp = reg_rf_mode_bw | BIT(7); 3329 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF); 3330 break; 3331 case HT_CHANNEL_WIDTH_80: 3332 tmp = reg_rf_mode_bw | BIT(8); 3333 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F); 3334 break; 3335 default: 3336 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "unknown Bandwidth: 0x%x\n", bw); 3337 break; 3338 } 3339 } 3340 3341 static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv *rtlpriv) 3342 { 3343 struct rtl_phy *rtlphy = &rtlpriv->phy; 3344 struct rtl_mac *mac = rtl_mac(rtlpriv); 3345 u8 sc_set_40 = 0, sc_set_20 = 0; 3346 3347 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) { 3348 if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER) 3349 sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ; 3350 else if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER) 3351 sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ; 3352 else 3353 pr_err("SCMapping: Not Correct Primary40MHz Setting\n"); 3354 3355 if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) && 3356 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER)) 3357 sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ; 3358 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) && 3359 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER)) 3360 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; 3361 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) && 3362 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER)) 3363 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; 3364 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) && 3365 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER)) 3366 sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ; 3367 else 3368 pr_err("SCMapping: Not Correct Primary40MHz Setting\n"); 3369 } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 3370 if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) 3371 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; 3372 else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) 3373 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; 3374 else 3375 pr_err("SCMapping: Not Correct Primary40MHz Setting\n"); 3376 } 3377 return (sc_set_40 << 4) | sc_set_20; 3378 } 3379 3380 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 3381 { 3382 struct rtl_priv *rtlpriv = rtl_priv(hw); 3383 struct rtl_phy *rtlphy = &rtlpriv->phy; 3384 u8 sub_chnl = 0; 3385 u8 l1pk_val = 0; 3386 3387 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 3388 "Switch to %s bandwidth\n", 3389 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 3390 "20MHz" : 3391 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ? 3392 "40MHz" : "80MHz"))); 3393 3394 _rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw); 3395 sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv); 3396 rtl_write_byte(rtlpriv, 0x0483, sub_chnl); 3397 3398 switch (rtlphy->current_chan_bw) { 3399 case HT_CHANNEL_WIDTH_20: 3400 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200); 3401 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); 3402 3403 if (rtlphy->rf_type == RF_2T2R) 3404 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7); 3405 else 3406 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8); 3407 break; 3408 case HT_CHANNEL_WIDTH_20_40: 3409 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201); 3410 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); 3411 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl); 3412 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl); 3413 3414 if (rtlphy->reg_837 & BIT(2)) 3415 l1pk_val = 6; 3416 else { 3417 if (rtlphy->rf_type == RF_2T2R) 3418 l1pk_val = 7; 3419 else 3420 l1pk_val = 8; 3421 } 3422 /* 0x848[25:22] = 0x6 */ 3423 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val); 3424 3425 if (sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ) 3426 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1); 3427 else 3428 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0); 3429 break; 3430 3431 case HT_CHANNEL_WIDTH_80: 3432 /* 0x8ac[21,20,9:6,1,0]=8'b11100010 */ 3433 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202); 3434 /* 0x8c4[30] = 1 */ 3435 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); 3436 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl); 3437 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl); 3438 3439 if (rtlphy->reg_837 & BIT(2)) 3440 l1pk_val = 5; 3441 else { 3442 if (rtlphy->rf_type == RF_2T2R) 3443 l1pk_val = 6; 3444 else 3445 l1pk_val = 7; 3446 } 3447 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val); 3448 3449 break; 3450 default: 3451 pr_err("unknown bandwidth: %#X\n", 3452 rtlphy->current_chan_bw); 3453 break; 3454 } 3455 3456 rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel); 3457 3458 rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 3459 rtlphy->set_bwmode_inprogress = false; 3460 3461 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n"); 3462 } 3463 3464 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw, 3465 enum nl80211_channel_type ch_type) 3466 { 3467 struct rtl_priv *rtlpriv = rtl_priv(hw); 3468 struct rtl_phy *rtlphy = &rtlpriv->phy; 3469 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3470 u8 tmp_bw = rtlphy->current_chan_bw; 3471 3472 if (rtlphy->set_bwmode_inprogress) 3473 return; 3474 rtlphy->set_bwmode_inprogress = true; 3475 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) 3476 rtl8821ae_phy_set_bw_mode_callback(hw); 3477 else { 3478 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 3479 "FALSE driver sleep or unload\n"); 3480 rtlphy->set_bwmode_inprogress = false; 3481 rtlphy->current_chan_bw = tmp_bw; 3482 } 3483 } 3484 3485 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw) 3486 { 3487 struct rtl_priv *rtlpriv = rtl_priv(hw); 3488 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3489 struct rtl_phy *rtlphy = &rtlpriv->phy; 3490 u8 channel = rtlphy->current_channel; 3491 u8 path; 3492 u32 data; 3493 3494 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 3495 "switch to channel%d\n", rtlphy->current_channel); 3496 if (is_hal_stop(rtlhal)) 3497 return; 3498 3499 if (36 <= channel && channel <= 48) 3500 data = 0x494; 3501 else if (50 <= channel && channel <= 64) 3502 data = 0x453; 3503 else if (100 <= channel && channel <= 116) 3504 data = 0x452; 3505 else if (118 <= channel) 3506 data = 0x412; 3507 else 3508 data = 0x96a; 3509 rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data); 3510 3511 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++) { 3512 if (36 <= channel && channel <= 64) 3513 data = 0x101; 3514 else if (100 <= channel && channel <= 140) 3515 data = 0x301; 3516 else if (140 < channel) 3517 data = 0x501; 3518 else 3519 data = 0x000; 3520 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW, 3521 BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data); 3522 3523 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW, 3524 BMASKBYTE0, channel); 3525 3526 if (channel > 14) { 3527 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 3528 if (36 <= channel && channel <= 64) 3529 data = 0x114E9; 3530 else 3531 data = 0x110E9; 3532 rtl8821ae_phy_set_rf_reg(hw, path, RF_APK, 3533 BRFREGOFFSETMASK, data); 3534 } 3535 } 3536 } 3537 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 3538 } 3539 3540 u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw) 3541 { 3542 struct rtl_priv *rtlpriv = rtl_priv(hw); 3543 struct rtl_phy *rtlphy = &rtlpriv->phy; 3544 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3545 u32 timeout = 1000, timecount = 0; 3546 u8 channel = rtlphy->current_channel; 3547 3548 if (rtlphy->sw_chnl_inprogress) 3549 return 0; 3550 if (rtlphy->set_bwmode_inprogress) 3551 return 0; 3552 3553 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 3554 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 3555 "sw_chnl_inprogress false driver sleep or unload\n"); 3556 return 0; 3557 } 3558 while (rtlphy->lck_inprogress && timecount < timeout) { 3559 mdelay(50); 3560 timecount += 50; 3561 } 3562 3563 if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G) 3564 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G); 3565 else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G) 3566 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); 3567 3568 rtlphy->sw_chnl_inprogress = true; 3569 if (channel == 0) 3570 channel = 1; 3571 3572 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 3573 "switch to channel%d, band type is %d\n", 3574 rtlphy->current_channel, rtlhal->current_bandtype); 3575 3576 rtl8821ae_phy_sw_chnl_callback(hw); 3577 3578 rtl8821ae_dm_clear_txpower_tracking_state(hw); 3579 rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel); 3580 3581 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 3582 rtlphy->sw_chnl_inprogress = false; 3583 return 1; 3584 } 3585 3586 u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl) 3587 { 3588 static const u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] = { 3589 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 3590 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 3591 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 3592 110, 112, 114, 116, 118, 120, 122, 124, 126, 3593 128, 130, 132, 134, 136, 138, 140, 149, 151, 3594 153, 155, 157, 159, 161, 163, 165}; 3595 u8 place; 3596 3597 if (chnl > 14) { 3598 for (place = 14; place < sizeof(channel_all); place++) 3599 if (channel_all[place] == chnl) 3600 return place-13; 3601 } 3602 3603 return 0; 3604 } 3605 3606 #define MACBB_REG_NUM 10 3607 #define AFE_REG_NUM 14 3608 #define RF_REG_NUM 3 3609 3610 static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw *hw, 3611 u32 *macbb_backup, 3612 u32 *backup_macbb_reg, u32 mac_bb_num) 3613 { 3614 struct rtl_priv *rtlpriv = rtl_priv(hw); 3615 u32 i; 3616 3617 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3618 /*save MACBB default value*/ 3619 for (i = 0; i < mac_bb_num; i++) 3620 macbb_backup[i] = rtl_read_dword(rtlpriv, backup_macbb_reg[i]); 3621 3622 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupMacBB Success!!!!\n"); 3623 } 3624 3625 static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw *hw, u32 *afe_backup, 3626 u32 *backup_afe_REG, u32 afe_num) 3627 { 3628 struct rtl_priv *rtlpriv = rtl_priv(hw); 3629 u32 i; 3630 3631 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3632 /*Save AFE Parameters */ 3633 for (i = 0; i < afe_num; i++) 3634 afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]); 3635 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupAFE Success!!!!\n"); 3636 } 3637 3638 static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw *hw, u32 *rfa_backup, 3639 u32 *rfb_backup, u32 *backup_rf_reg, 3640 u32 rf_num) 3641 { 3642 struct rtl_priv *rtlpriv = rtl_priv(hw); 3643 u32 i; 3644 3645 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3646 /*Save RF Parameters*/ 3647 for (i = 0; i < rf_num; i++) { 3648 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i], 3649 BMASKDWORD); 3650 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i], 3651 BMASKDWORD); 3652 } 3653 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupRF Success!!!!\n"); 3654 } 3655 3656 static void _rtl8821ae_iqk_configure_mac( 3657 struct ieee80211_hw *hw 3658 ) 3659 { 3660 struct rtl_priv *rtlpriv = rtl_priv(hw); 3661 /* ========MAC register setting========*/ 3662 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3663 rtl_write_byte(rtlpriv, 0x522, 0x3f); 3664 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0); 3665 rtl_write_byte(rtlpriv, 0x808, 0x00); /*RX ante off*/ 3666 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/ 3667 } 3668 3669 static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw *hw, 3670 enum radio_path path, u32 tx_x, u32 tx_y) 3671 { 3672 struct rtl_priv *rtlpriv = rtl_priv(hw); 3673 switch (path) { 3674 case RF90_PATH_A: 3675 /* [31] = 1 --> Page C1 */ 3676 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); 3677 rtl_write_dword(rtlpriv, 0xc90, 0x00000080); 3678 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000); 3679 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000); 3680 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y); 3681 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x); 3682 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3683 "TX_X = %x;;TX_Y = %x =====> fill to IQC\n", 3684 tx_x, tx_y); 3685 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3686 "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", 3687 rtl_get_bbreg(hw, 0xcd4, 0x000007ff), 3688 rtl_get_bbreg(hw, 0xccc, 0x000007ff)); 3689 break; 3690 default: 3691 break; 3692 } 3693 } 3694 3695 static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw *hw, 3696 enum radio_path path, u32 rx_x, u32 rx_y) 3697 { 3698 struct rtl_priv *rtlpriv = rtl_priv(hw); 3699 switch (path) { 3700 case RF90_PATH_A: 3701 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3702 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1); 3703 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1); 3704 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3705 "rx_x = %x;;rx_y = %x ====>fill to IQC\n", 3706 rx_x >> 1, rx_y >> 1); 3707 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3708 "0xc10 = %x ====>fill to IQC\n", 3709 rtl_read_dword(rtlpriv, 0xc10)); 3710 break; 3711 default: 3712 break; 3713 } 3714 } 3715 3716 #define cal_num 10 3717 3718 static void _rtl8821ae_iqk_tx(struct ieee80211_hw *hw, enum radio_path path) 3719 { 3720 struct rtl_priv *rtlpriv = rtl_priv(hw); 3721 struct rtl_phy *rtlphy = &rtlpriv->phy; 3722 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3723 3724 u32 tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65; 3725 int tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0; 3726 int tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num], 3727 tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num], 3728 tx_dt[cal_num], rx_dt[cal_num]; 3729 bool tx0iqkok = false, rx0iqkok = false; 3730 bool vdf_enable = false; 3731 int i, k, vdf_y[3], vdf_x[3], 3732 ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0; 3733 3734 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3735 "BandWidth = %d.\n", 3736 rtlphy->current_chan_bw); 3737 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) 3738 vdf_enable = true; 3739 3740 while (cal < cal_num) { 3741 switch (path) { 3742 case RF90_PATH_A: 3743 temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff); 3744 /* Path-A LOK */ 3745 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3746 /*========Path-A AFE all on========*/ 3747 /*Port 0 DAC/ADC on*/ 3748 rtl_write_dword(rtlpriv, 0xc60, 0x77777777); 3749 rtl_write_dword(rtlpriv, 0xc64, 0x77777777); 3750 rtl_write_dword(rtlpriv, 0xc68, 0x19791979); 3751 rtl_write_dword(rtlpriv, 0xc6c, 0x19791979); 3752 rtl_write_dword(rtlpriv, 0xc70, 0x19791979); 3753 rtl_write_dword(rtlpriv, 0xc74, 0x19791979); 3754 rtl_write_dword(rtlpriv, 0xc78, 0x19791979); 3755 rtl_write_dword(rtlpriv, 0xc7c, 0x19791979); 3756 rtl_write_dword(rtlpriv, 0xc80, 0x19791979); 3757 rtl_write_dword(rtlpriv, 0xc84, 0x19791979); 3758 3759 rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/ 3760 3761 /* LOK Setting */ 3762 /* ====== LOK ====== */ 3763 /*DAC/ADC sampling rate (160 MHz)*/ 3764 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7); 3765 3766 /* 2. LoK RF Setting (at BW = 20M) */ 3767 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002); 3768 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3); /* BW 20M */ 3769 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000); 3770 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f); 3771 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3); 3772 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5); 3773 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 3774 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd); 3775 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 3776 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 3777 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); 3778 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */ 3779 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */ 3780 rtl_write_dword(rtlpriv, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */ 3781 3782 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 3783 rtl_write_dword(rtlpriv, 0xc88, 0x821403f4); 3784 3785 if (rtlhal->current_bandtype) 3786 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96); 3787 else 3788 rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96); 3789 3790 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3791 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3792 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 3793 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 3794 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 3795 3796 mdelay(10); /* Delay 10ms */ 3797 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 3798 3799 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3800 rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); /* Load LOK */ 3801 3802 switch (rtlphy->current_chan_bw) { 3803 case 1: 3804 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1); 3805 break; 3806 case 2: 3807 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0); 3808 break; 3809 default: 3810 break; 3811 } 3812 3813 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 3814 3815 /* 3. TX RF Setting */ 3816 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3817 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 3818 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000); 3819 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f); 3820 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3); 3821 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5); 3822 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 3823 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 3824 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd); */ 3825 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 3826 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 3827 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); 3828 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */ 3829 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */ 3830 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */ 3831 3832 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 3833 rtl_write_dword(rtlpriv, 0xc88, 0x821403f1); 3834 if (rtlhal->current_bandtype) 3835 rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96); 3836 else 3837 rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96); 3838 3839 if (vdf_enable) { 3840 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "VDF_enable\n"); 3841 for (k = 0; k <= 2; k++) { 3842 switch (k) { 3843 case 0: 3844 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3845 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3846 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); 3847 break; 3848 case 1: 3849 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0); 3850 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0); 3851 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); 3852 break; 3853 case 2: 3854 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3855 "vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff); 3856 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3857 "vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff); 3858 tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20); 3859 tx_dt[cal] = ((16*tx_dt[cal])*10000/15708); 3860 tx_dt[cal] = (tx_dt[cal] >> 1)+(tx_dt[cal] & BIT(0)); 3861 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3862 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3863 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); 3864 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff); 3865 break; 3866 default: 3867 break; 3868 } 3869 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 3870 cal_retry = 0; 3871 while (1) { 3872 /* one shot */ 3873 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 3874 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 3875 3876 mdelay(10); /* Delay 10ms */ 3877 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 3878 delay_count = 0; 3879 while (1) { 3880 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 3881 if ((~iqk_ready) || (delay_count > 20)) 3882 break; 3883 else{ 3884 mdelay(1); 3885 delay_count++; 3886 } 3887 } 3888 3889 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 3890 /* ============TXIQK Check============== */ 3891 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 3892 3893 if (~tx_fail) { 3894 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 3895 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3896 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 3897 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3898 tx0iqkok = true; 3899 break; 3900 } else { 3901 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0); 3902 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200); 3903 tx0iqkok = false; 3904 cal_retry++; 3905 if (cal_retry == 10) 3906 break; 3907 } 3908 } else { 3909 tx0iqkok = false; 3910 cal_retry++; 3911 if (cal_retry == 10) 3912 break; 3913 } 3914 } 3915 } 3916 if (k == 3) { 3917 tx_x0[cal] = vdf_x[k-1]; 3918 tx_y0[cal] = vdf_y[k-1]; 3919 } 3920 } else { 3921 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3922 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3923 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 3924 cal_retry = 0; 3925 while (1) { 3926 /* one shot */ 3927 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 3928 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 3929 3930 mdelay(10); /* Delay 10ms */ 3931 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 3932 delay_count = 0; 3933 while (1) { 3934 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 3935 if ((~iqk_ready) || (delay_count > 20)) 3936 break; 3937 else{ 3938 mdelay(1); 3939 delay_count++; 3940 } 3941 } 3942 3943 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 3944 /* ============TXIQK Check============== */ 3945 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 3946 3947 if (~tx_fail) { 3948 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 3949 tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3950 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 3951 tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3952 tx0iqkok = true; 3953 break; 3954 } else { 3955 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0); 3956 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200); 3957 tx0iqkok = false; 3958 cal_retry++; 3959 if (cal_retry == 10) 3960 break; 3961 } 3962 } else { 3963 tx0iqkok = false; 3964 cal_retry++; 3965 if (cal_retry == 10) 3966 break; 3967 } 3968 } 3969 } 3970 3971 if (!tx0iqkok) 3972 break; /* TXK fail, Don't do RXK */ 3973 3974 if (vdf_enable == 1) { 3975 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); /* TX VDF Disable */ 3976 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RXVDF Start\n"); 3977 for (k = 0; k <= 2; k++) { 3978 /* ====== RX mode TXK (RXK Step 1) ====== */ 3979 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3980 /* 1. TX RF Setting */ 3981 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 3982 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 3983 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029); 3984 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb); 3985 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); 3986 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 3987 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 3988 3989 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd); 3990 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */ 3991 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */ 3992 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */ 3993 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 3994 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 3995 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 3996 switch (k) { 3997 case 0: 3998 { 3999 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4000 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4001 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); 4002 } 4003 break; 4004 case 1: 4005 { 4006 rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4007 rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4008 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); 4009 } 4010 break; 4011 case 2: 4012 { 4013 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4014 "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", 4015 vdf_y[1] >> 21 & 0x00007ff, 4016 vdf_y[0] >> 21 & 0x00007ff); 4017 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4018 "VDF_X[1] = %x;;;VDF_X[0] = %x\n", 4019 vdf_x[1] >> 21 & 0x00007ff, 4020 vdf_x[0] >> 21 & 0x00007ff); 4021 rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20); 4022 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "Rx_dt = %d\n", 4023 rx_dt[cal]); 4024 rx_dt[cal] = ((16*rx_dt[cal])*10000/13823); 4025 rx_dt[cal] = (rx_dt[cal] >> 1)+(rx_dt[cal] & BIT(0)); 4026 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4027 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4028 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff); 4029 } 4030 break; 4031 default: 4032 break; 4033 } 4034 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0); 4035 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96); 4036 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4037 cal_retry = 0; 4038 while (1) { 4039 /* one shot */ 4040 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4041 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4042 4043 mdelay(10); /* Delay 10ms */ 4044 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4045 delay_count = 0; 4046 while (1) { 4047 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4048 if ((~iqk_ready) || (delay_count > 20)) 4049 break; 4050 else{ 4051 mdelay(1); 4052 delay_count++; 4053 } 4054 } 4055 4056 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4057 /* ============TXIQK Check============== */ 4058 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 4059 4060 if (~tx_fail) { 4061 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 4062 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4063 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 4064 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4065 tx0iqkok = true; 4066 break; 4067 } else{ 4068 tx0iqkok = false; 4069 cal_retry++; 4070 if (cal_retry == 10) 4071 break; 4072 } 4073 } else { 4074 tx0iqkok = false; 4075 cal_retry++; 4076 if (cal_retry == 10) 4077 break; 4078 } 4079 } 4080 4081 if (!tx0iqkok) { /* If RX mode TXK fail, then take TXK Result */ 4082 tx_x0_rxk[cal] = tx_x0[cal]; 4083 tx_y0_rxk[cal] = tx_y0[cal]; 4084 tx0iqkok = true; 4085 rtl_dbg(rtlpriv, 4086 COMP_IQK, 4087 DBG_LOUD, 4088 "RXK Step 1 fail\n"); 4089 } 4090 4091 /* ====== RX IQK ====== */ 4092 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4093 /* 1. RX RF Setting */ 4094 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 4095 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 4096 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f); 4097 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb); 4098 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001); 4099 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8); 4100 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 4101 4102 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff); 4103 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff); 4104 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); 4105 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); 4106 rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe); 4107 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 4108 rtl_write_dword(rtlpriv, 0x984, 0x0046a911); 4109 4110 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4111 rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1); 4112 rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0); 4113 rtl_write_dword(rtlpriv, 0xc88, 0x02140119); 4114 4115 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */ 4116 4117 if (k == 2) 4118 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); /* RX VDF Enable */ 4119 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4120 4121 cal_retry = 0; 4122 while (1) { 4123 /* one shot */ 4124 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4125 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4126 4127 mdelay(10); /* Delay 10ms */ 4128 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4129 delay_count = 0; 4130 while (1) { 4131 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4132 if ((~iqk_ready) || (delay_count > 20)) 4133 break; 4134 else{ 4135 mdelay(1); 4136 delay_count++; 4137 } 4138 } 4139 4140 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4141 /* ============RXIQK Check============== */ 4142 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); 4143 if (rx_fail == 0) { 4144 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000); 4145 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4146 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000); 4147 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4148 rx0iqkok = true; 4149 break; 4150 } else { 4151 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1); 4152 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1); 4153 rx0iqkok = false; 4154 cal_retry++; 4155 if (cal_retry == 10) 4156 break; 4157 4158 } 4159 } else{ 4160 rx0iqkok = false; 4161 cal_retry++; 4162 if (cal_retry == 10) 4163 break; 4164 } 4165 } 4166 4167 } 4168 if (k == 3) { 4169 rx_x0[cal] = vdf_x[k-1]; 4170 rx_y0[cal] = vdf_y[k-1]; 4171 } 4172 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); /* TX VDF Enable */ 4173 } 4174 4175 else{ 4176 /* ====== RX mode TXK (RXK Step 1) ====== */ 4177 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4178 /* 1. TX RF Setting */ 4179 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 4180 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 4181 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029); 4182 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb); 4183 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); 4184 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 4185 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 4186 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 4187 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 4188 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */ 4189 4190 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4191 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4192 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4193 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0); 4194 /* ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); */ 4195 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4196 cal_retry = 0; 4197 while (1) { 4198 /* one shot */ 4199 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4200 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4201 4202 mdelay(10); /* Delay 10ms */ 4203 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4204 delay_count = 0; 4205 while (1) { 4206 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4207 if ((~iqk_ready) || (delay_count > 20)) 4208 break; 4209 else{ 4210 mdelay(1); 4211 delay_count++; 4212 } 4213 } 4214 4215 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4216 /* ============TXIQK Check============== */ 4217 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 4218 4219 if (~tx_fail) { 4220 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 4221 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4222 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 4223 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4224 tx0iqkok = true; 4225 break; 4226 } else { 4227 tx0iqkok = false; 4228 cal_retry++; 4229 if (cal_retry == 10) 4230 break; 4231 } 4232 } else{ 4233 tx0iqkok = false; 4234 cal_retry++; 4235 if (cal_retry == 10) 4236 break; 4237 } 4238 } 4239 4240 if (!tx0iqkok) { /* If RX mode TXK fail, then take TXK Result */ 4241 tx_x0_rxk[cal] = tx_x0[cal]; 4242 tx_y0_rxk[cal] = tx_y0[cal]; 4243 tx0iqkok = true; 4244 rtl_dbg(rtlpriv, COMP_IQK, 4245 DBG_LOUD, "1"); 4246 } 4247 4248 /* ====== RX IQK ====== */ 4249 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4250 /* 1. RX RF Setting */ 4251 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 4252 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 4253 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f); 4254 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb); 4255 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001); 4256 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8); 4257 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 4258 4259 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff); 4260 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff); 4261 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); 4262 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); 4263 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe); */ 4264 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 4265 rtl_write_dword(rtlpriv, 0x984, 0x0046a911); 4266 4267 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4268 rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4269 rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4270 rtl_write_dword(rtlpriv, 0xc88, 0x02140119); 4271 4272 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/ 4273 4274 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4275 4276 cal_retry = 0; 4277 while (1) { 4278 /* one shot */ 4279 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4280 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4281 4282 mdelay(10); /* Delay 10ms */ 4283 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4284 delay_count = 0; 4285 while (1) { 4286 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4287 if ((~iqk_ready) || (delay_count > 20)) 4288 break; 4289 else{ 4290 mdelay(1); 4291 delay_count++; 4292 } 4293 } 4294 4295 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4296 /* ============RXIQK Check============== */ 4297 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); 4298 if (rx_fail == 0) { 4299 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000); 4300 rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4301 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000); 4302 rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4303 rx0iqkok = true; 4304 break; 4305 } else{ 4306 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1); 4307 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1); 4308 rx0iqkok = false; 4309 cal_retry++; 4310 if (cal_retry == 10) 4311 break; 4312 4313 } 4314 } else{ 4315 rx0iqkok = false; 4316 cal_retry++; 4317 if (cal_retry == 10) 4318 break; 4319 } 4320 } 4321 } 4322 4323 if (tx0iqkok) 4324 tx_average++; 4325 if (rx0iqkok) 4326 rx_average++; 4327 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4328 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); 4329 break; 4330 default: 4331 break; 4332 } 4333 cal++; 4334 } 4335 4336 /* FillIQK Result */ 4337 switch (path) { 4338 case RF90_PATH_A: 4339 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4340 "========Path_A =======\n"); 4341 if (tx_average == 0) 4342 break; 4343 4344 for (i = 0; i < tx_average; i++) { 4345 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4346 "TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i, 4347 (tx_x0_rxk[i]) >> 21 & 0x000007ff, i, 4348 (tx_y0_rxk[i]) >> 21 & 0x000007ff); 4349 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4350 "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, 4351 (tx_x0[i]) >> 21 & 0x000007ff, i, 4352 (tx_y0[i]) >> 21 & 0x000007ff); 4353 } 4354 for (i = 0; i < tx_average; i++) { 4355 for (ii = i+1; ii < tx_average; ii++) { 4356 dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21); 4357 if (dx < 3 && dx > -3) { 4358 dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21); 4359 if (dy < 3 && dy > -3) { 4360 tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2; 4361 tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2; 4362 tx_finish = 1; 4363 break; 4364 } 4365 } 4366 } 4367 if (tx_finish == 1) 4368 break; 4369 } 4370 4371 if (tx_finish == 1) 4372 _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); /* ? */ 4373 else 4374 _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0); 4375 4376 if (rx_average == 0) 4377 break; 4378 4379 for (i = 0; i < rx_average; i++) 4380 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4381 "RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i, 4382 (rx_x0[i])>>21&0x000007ff, i, 4383 (rx_y0[i])>>21&0x000007ff); 4384 for (i = 0; i < rx_average; i++) { 4385 for (ii = i+1; ii < rx_average; ii++) { 4386 dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21); 4387 if (dx < 4 && dx > -4) { 4388 dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21); 4389 if (dy < 4 && dy > -4) { 4390 rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2; 4391 rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2; 4392 rx_finish = 1; 4393 break; 4394 } 4395 } 4396 } 4397 if (rx_finish == 1) 4398 break; 4399 } 4400 4401 if (rx_finish == 1) 4402 _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y); 4403 else 4404 _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0); 4405 break; 4406 default: 4407 break; 4408 } 4409 } 4410 4411 static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw *hw, 4412 enum radio_path path, 4413 u32 *backup_rf_reg, 4414 u32 *rf_backup, u32 rf_reg_num) 4415 { 4416 struct rtl_priv *rtlpriv = rtl_priv(hw); 4417 u32 i; 4418 4419 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4420 for (i = 0; i < RF_REG_NUM; i++) 4421 rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK, 4422 rf_backup[i]); 4423 4424 switch (path) { 4425 case RF90_PATH_A: 4426 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4427 "RestoreRF Path A Success!!!!\n"); 4428 break; 4429 default: 4430 break; 4431 } 4432 } 4433 4434 static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw *hw, 4435 u32 *afe_backup, u32 *backup_afe_reg, 4436 u32 afe_num) 4437 { 4438 u32 i; 4439 struct rtl_priv *rtlpriv = rtl_priv(hw); 4440 4441 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4442 /* Reload AFE Parameters */ 4443 for (i = 0; i < afe_num; i++) 4444 rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]); 4445 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4446 rtl_write_dword(rtlpriv, 0xc80, 0x0); 4447 rtl_write_dword(rtlpriv, 0xc84, 0x0); 4448 rtl_write_dword(rtlpriv, 0xc88, 0x0); 4449 rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000); 4450 rtl_write_dword(rtlpriv, 0xc90, 0x00000080); 4451 rtl_write_dword(rtlpriv, 0xc94, 0x00000000); 4452 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000); 4453 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000); 4454 rtl_write_dword(rtlpriv, 0xcb8, 0x0); 4455 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreAFE Success!!!!\n"); 4456 } 4457 4458 static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw *hw, 4459 u32 *macbb_backup, 4460 u32 *backup_macbb_reg, 4461 u32 macbb_num) 4462 { 4463 u32 i; 4464 struct rtl_priv *rtlpriv = rtl_priv(hw); 4465 4466 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4467 /* Reload MacBB Parameters */ 4468 for (i = 0; i < macbb_num; i++) 4469 rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]); 4470 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreMacBB Success!!!!\n"); 4471 } 4472 4473 #undef MACBB_REG_NUM 4474 #undef AFE_REG_NUM 4475 #undef RF_REG_NUM 4476 4477 #define MACBB_REG_NUM 11 4478 #define AFE_REG_NUM 12 4479 #define RF_REG_NUM 3 4480 4481 static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw) 4482 { 4483 u32 macbb_backup[MACBB_REG_NUM]; 4484 u32 afe_backup[AFE_REG_NUM]; 4485 u32 rfa_backup[RF_REG_NUM]; 4486 u32 rfb_backup[RF_REG_NUM]; 4487 u32 backup_macbb_reg[MACBB_REG_NUM] = { 4488 0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50, 4489 0xe00, 0xe50, 0x838, 0x82c 4490 }; 4491 u32 backup_afe_reg[AFE_REG_NUM] = { 4492 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 4493 0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8 4494 }; 4495 u32 backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0}; 4496 4497 _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg, 4498 MACBB_REG_NUM); 4499 _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM); 4500 _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg, 4501 RF_REG_NUM); 4502 4503 _rtl8821ae_iqk_configure_mac(hw); 4504 _rtl8821ae_iqk_tx(hw, RF90_PATH_A); 4505 _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup, 4506 RF_REG_NUM); 4507 4508 _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM); 4509 _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg, 4510 MACBB_REG_NUM); 4511 } 4512 4513 static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main) 4514 { 4515 struct rtl_priv *rtlpriv = rtl_priv(hw); 4516 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */ 4517 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */ 4518 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 4519 4520 if (main) 4521 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1); 4522 else 4523 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2); 4524 } 4525 4526 #undef IQK_ADDA_REG_NUM 4527 #undef IQK_DELAY_TIME 4528 4529 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 4530 { 4531 } 4532 4533 void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index, 4534 u8 thermal_value, u8 threshold) 4535 { 4536 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 4537 4538 rtldm->thermalvalue_iqk = thermal_value; 4539 rtl8812ae_phy_iq_calibrate(hw, false); 4540 } 4541 4542 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 4543 { 4544 struct rtl_priv *rtlpriv = rtl_priv(hw); 4545 struct rtl_phy *rtlphy = &rtlpriv->phy; 4546 4547 if (!rtlphy->lck_inprogress) { 4548 spin_lock(&rtlpriv->locks.iqk_lock); 4549 rtlphy->lck_inprogress = true; 4550 spin_unlock(&rtlpriv->locks.iqk_lock); 4551 4552 _rtl8821ae_phy_iq_calibrate(hw); 4553 4554 spin_lock(&rtlpriv->locks.iqk_lock); 4555 rtlphy->lck_inprogress = false; 4556 spin_unlock(&rtlpriv->locks.iqk_lock); 4557 } 4558 } 4559 4560 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw) 4561 { 4562 struct rtl_priv *rtlpriv = rtl_priv(hw); 4563 struct rtl_phy *rtlphy = &rtlpriv->phy; 4564 u8 i; 4565 4566 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4567 "rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n", 4568 (int)(sizeof(rtlphy->iqk_matrix) / 4569 sizeof(struct iqk_matrix_regs)), 4570 IQK_MATRIX_SETTINGS_NUM); 4571 4572 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { 4573 rtlphy->iqk_matrix[i].value[0][0] = 0x100; 4574 rtlphy->iqk_matrix[i].value[0][2] = 0x100; 4575 rtlphy->iqk_matrix[i].value[0][4] = 0x100; 4576 rtlphy->iqk_matrix[i].value[0][6] = 0x100; 4577 4578 rtlphy->iqk_matrix[i].value[0][1] = 0x0; 4579 rtlphy->iqk_matrix[i].value[0][3] = 0x0; 4580 rtlphy->iqk_matrix[i].value[0][5] = 0x0; 4581 rtlphy->iqk_matrix[i].value[0][7] = 0x0; 4582 4583 rtlphy->iqk_matrix[i].iqk_done = false; 4584 } 4585 } 4586 4587 void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index, 4588 u8 thermal_value, u8 threshold) 4589 { 4590 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 4591 4592 rtl8821ae_reset_iqk_result(hw); 4593 4594 rtldm->thermalvalue_iqk = thermal_value; 4595 rtl8821ae_phy_iq_calibrate(hw, false); 4596 } 4597 4598 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw) 4599 { 4600 } 4601 4602 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) 4603 { 4604 } 4605 4606 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 4607 { 4608 _rtl8821ae_phy_set_rfpath_switch(hw, bmain); 4609 } 4610 4611 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 4612 { 4613 struct rtl_priv *rtlpriv = rtl_priv(hw); 4614 struct rtl_phy *rtlphy = &rtlpriv->phy; 4615 bool postprocessing = false; 4616 4617 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4618 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 4619 iotype, rtlphy->set_io_inprogress); 4620 do { 4621 switch (iotype) { 4622 case IO_CMD_RESUME_DM_BY_SCAN: 4623 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4624 "[IO CMD] Resume DM after scan.\n"); 4625 postprocessing = true; 4626 break; 4627 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 4628 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN: 4629 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4630 "[IO CMD] Pause DM before scan.\n"); 4631 postprocessing = true; 4632 break; 4633 default: 4634 pr_err("switch case %#x not processed\n", 4635 iotype); 4636 break; 4637 } 4638 } while (false); 4639 if (postprocessing && !rtlphy->set_io_inprogress) { 4640 rtlphy->set_io_inprogress = true; 4641 rtlphy->current_io_type = iotype; 4642 } else { 4643 return false; 4644 } 4645 rtl8821ae_phy_set_io(hw); 4646 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype); 4647 return true; 4648 } 4649 4650 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw) 4651 { 4652 struct rtl_priv *rtlpriv = rtl_priv(hw); 4653 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 4654 struct rtl_phy *rtlphy = &rtlpriv->phy; 4655 4656 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4657 "--->Cmd(%#x), set_io_inprogress(%d)\n", 4658 rtlphy->current_io_type, rtlphy->set_io_inprogress); 4659 switch (rtlphy->current_io_type) { 4660 case IO_CMD_RESUME_DM_BY_SCAN: 4661 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) 4662 _rtl8821ae_resume_tx_beacon(hw); 4663 rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1); 4664 rtl8821ae_dm_write_cck_cca_thres(hw, 4665 rtlphy->initgain_backup.cca); 4666 break; 4667 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 4668 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) 4669 _rtl8821ae_stop_tx_beacon(hw); 4670 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; 4671 rtl8821ae_dm_write_dig(hw, 0x17); 4672 rtlphy->initgain_backup.cca = dm_digtable->cur_cck_cca_thres; 4673 rtl8821ae_dm_write_cck_cca_thres(hw, 0x40); 4674 break; 4675 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN: 4676 break; 4677 default: 4678 pr_err("switch case %#x not processed\n", 4679 rtlphy->current_io_type); 4680 break; 4681 } 4682 rtlphy->set_io_inprogress = false; 4683 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4684 "(%#x)\n", rtlphy->current_io_type); 4685 } 4686 4687 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw) 4688 { 4689 struct rtl_priv *rtlpriv = rtl_priv(hw); 4690 4691 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 4692 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 4693 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 4694 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 4695 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 4696 } 4697 4698 static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw, 4699 enum rf_pwrstate rfpwr_state) 4700 { 4701 struct rtl_priv *rtlpriv = rtl_priv(hw); 4702 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 4703 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 4704 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 4705 bool bresult = true; 4706 u8 i, queue_id; 4707 struct rtl8192_tx_ring *ring = NULL; 4708 4709 switch (rfpwr_state) { 4710 case ERFON: 4711 if ((ppsc->rfpwr_state == ERFOFF) && 4712 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 4713 bool rtstatus = false; 4714 u32 initializecount = 0; 4715 4716 do { 4717 initializecount++; 4718 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 4719 "IPS Set eRf nic enable\n"); 4720 rtstatus = rtl_ps_enable_nic(hw); 4721 } while (!rtstatus && (initializecount < 10)); 4722 RT_CLEAR_PS_LEVEL(ppsc, 4723 RT_RF_OFF_LEVL_HALT_NIC); 4724 } else { 4725 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 4726 "Set ERFON slept:%d ms\n", 4727 jiffies_to_msecs(jiffies - 4728 ppsc->last_sleep_jiffies)); 4729 ppsc->last_awake_jiffies = jiffies; 4730 rtl8821ae_phy_set_rf_on(hw); 4731 } 4732 if (mac->link_state == MAC80211_LINKED) { 4733 rtlpriv->cfg->ops->led_control(hw, 4734 LED_CTL_LINK); 4735 } else { 4736 rtlpriv->cfg->ops->led_control(hw, 4737 LED_CTL_NO_LINK); 4738 } 4739 break; 4740 case ERFOFF: 4741 for (queue_id = 0, i = 0; 4742 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 4743 ring = &pcipriv->dev.tx_ring[queue_id]; 4744 if (queue_id == BEACON_QUEUE || 4745 skb_queue_len(&ring->queue) == 0) { 4746 queue_id++; 4747 continue; 4748 } else { 4749 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 4750 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 4751 (i + 1), queue_id, 4752 skb_queue_len(&ring->queue)); 4753 4754 udelay(10); 4755 i++; 4756 } 4757 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 4758 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 4759 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 4760 MAX_DOZE_WAITING_TIMES_9x, 4761 queue_id, 4762 skb_queue_len(&ring->queue)); 4763 break; 4764 } 4765 } 4766 4767 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 4768 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 4769 "IPS Set eRf nic disable\n"); 4770 rtl_ps_disable_nic(hw); 4771 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 4772 } else { 4773 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 4774 rtlpriv->cfg->ops->led_control(hw, 4775 LED_CTL_NO_LINK); 4776 } else { 4777 rtlpriv->cfg->ops->led_control(hw, 4778 LED_CTL_POWER_OFF); 4779 } 4780 } 4781 break; 4782 default: 4783 pr_err("switch case %#x not processed\n", 4784 rfpwr_state); 4785 bresult = false; 4786 break; 4787 } 4788 if (bresult) 4789 ppsc->rfpwr_state = rfpwr_state; 4790 return bresult; 4791 } 4792 4793 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw, 4794 enum rf_pwrstate rfpwr_state) 4795 { 4796 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 4797 4798 bool bresult = false; 4799 4800 if (rfpwr_state == ppsc->rfpwr_state) 4801 return bresult; 4802 bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state); 4803 return bresult; 4804 } 4805