1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2010 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../efuse.h" 6 #include "../base.h" 7 #include "../regd.h" 8 #include "../cam.h" 9 #include "../ps.h" 10 #include "../pci.h" 11 #include "reg.h" 12 #include "def.h" 13 #include "phy.h" 14 #include "dm.h" 15 #include "fw.h" 16 #include "led.h" 17 #include "hw.h" 18 #include "../pwrseqcmd.h" 19 #include "pwrseq.h" 20 #include "../btcoexist/rtl_btc.h" 21 22 #define LLT_CONFIG 5 23 24 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw) 25 { 26 struct rtl_priv *rtlpriv = rtl_priv(hw); 27 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 28 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 29 unsigned long flags; 30 31 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 32 while (skb_queue_len(&ring->queue)) { 33 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 34 struct sk_buff *skb = __skb_dequeue(&ring->queue); 35 36 pci_unmap_single(rtlpci->pdev, 37 rtlpriv->cfg->ops->get_desc( 38 hw, 39 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 40 skb->len, PCI_DMA_TODEVICE); 41 kfree_skb(skb); 42 ring->idx = (ring->idx + 1) % ring->entries; 43 } 44 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 45 } 46 47 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 48 u8 set_bits, u8 clear_bits) 49 { 50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 51 struct rtl_priv *rtlpriv = rtl_priv(hw); 52 53 rtlpci->reg_bcn_ctrl_val |= set_bits; 54 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 55 56 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 57 } 58 59 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw) 60 { 61 struct rtl_priv *rtlpriv = rtl_priv(hw); 62 u8 tmp1byte; 63 64 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 65 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 66 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 67 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 68 tmp1byte &= ~(BIT(0)); 69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 70 } 71 72 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw) 73 { 74 struct rtl_priv *rtlpriv = rtl_priv(hw); 75 u8 tmp1byte; 76 77 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 78 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 79 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 80 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 81 tmp1byte |= BIT(0); 82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 83 } 84 85 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw) 86 { 87 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); 88 } 89 90 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw) 91 { 92 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0); 93 } 94 95 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw, 96 u8 rpwm_val, bool b_need_turn_off_ckk) 97 { 98 struct rtl_priv *rtlpriv = rtl_priv(hw); 99 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 100 bool b_support_remote_wake_up; 101 u32 count = 0, isr_regaddr, content; 102 bool b_schedule_timer = b_need_turn_off_ckk; 103 104 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 105 (u8 *)(&b_support_remote_wake_up)); 106 107 if (!rtlhal->fw_ready) 108 return; 109 if (!rtlpriv->psc.fw_current_inpsmode) 110 return; 111 112 while (1) { 113 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 114 if (rtlhal->fw_clk_change_in_progress) { 115 while (rtlhal->fw_clk_change_in_progress) { 116 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 117 count++; 118 udelay(100); 119 if (count > 1000) 120 goto change_done; 121 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 122 } 123 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 124 } else { 125 rtlhal->fw_clk_change_in_progress = false; 126 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 127 goto change_done; 128 } 129 } 130 change_done: 131 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) { 132 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 133 (u8 *)(&rpwm_val)); 134 if (FW_PS_IS_ACK(rpwm_val)) { 135 isr_regaddr = REG_HISR; 136 content = rtl_read_dword(rtlpriv, isr_regaddr); 137 while (!(content & IMR_CPWM) && (count < 500)) { 138 udelay(50); 139 count++; 140 content = rtl_read_dword(rtlpriv, isr_regaddr); 141 } 142 143 if (content & IMR_CPWM) { 144 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 145 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE; 146 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 147 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n", 148 rtlhal->fw_ps_state); 149 } 150 } 151 152 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 153 rtlhal->fw_clk_change_in_progress = false; 154 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 155 if (b_schedule_timer) 156 mod_timer(&rtlpriv->works.fw_clockoff_timer, 157 jiffies + MSECS(10)); 158 } else { 159 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 160 rtlhal->fw_clk_change_in_progress = false; 161 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 162 } 163 } 164 165 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw, 166 u8 rpwm_val) 167 { 168 struct rtl_priv *rtlpriv = rtl_priv(hw); 169 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 170 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 171 struct rtl8192_tx_ring *ring; 172 enum rf_pwrstate rtstate; 173 bool b_schedule_timer = false; 174 u8 queue; 175 176 if (!rtlhal->fw_ready) 177 return; 178 if (!rtlpriv->psc.fw_current_inpsmode) 179 return; 180 if (!rtlhal->allow_sw_to_change_hwclc) 181 return; 182 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 183 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 184 return; 185 186 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 187 ring = &rtlpci->tx_ring[queue]; 188 if (skb_queue_len(&ring->queue)) { 189 b_schedule_timer = true; 190 break; 191 } 192 } 193 194 if (b_schedule_timer) { 195 mod_timer(&rtlpriv->works.fw_clockoff_timer, 196 jiffies + MSECS(10)); 197 return; 198 } 199 200 if (FW_PS_STATE(rtlhal->fw_ps_state) != 201 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) { 202 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 203 if (!rtlhal->fw_clk_change_in_progress) { 204 rtlhal->fw_clk_change_in_progress = true; 205 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 206 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 207 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 208 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 209 (u8 *)(&rpwm_val)); 210 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 211 rtlhal->fw_clk_change_in_progress = false; 212 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 213 } else { 214 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 215 mod_timer(&rtlpriv->works.fw_clockoff_timer, 216 jiffies + MSECS(10)); 217 } 218 } 219 } 220 221 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw) 222 { 223 u8 rpwm_val = 0; 224 225 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK); 226 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true); 227 } 228 229 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw) 230 { 231 struct rtl_priv *rtlpriv = rtl_priv(hw); 232 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 233 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 234 bool fw_current_inps = false; 235 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 236 237 if (ppsc->low_power_enable) { 238 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */ 239 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false); 240 rtlhal->allow_sw_to_change_hwclc = false; 241 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 242 (u8 *)(&fw_pwrmode)); 243 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 244 (u8 *)(&fw_current_inps)); 245 } else { 246 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */ 247 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 248 (u8 *)(&rpwm_val)); 249 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 250 (u8 *)(&fw_pwrmode)); 251 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 252 (u8 *)(&fw_current_inps)); 253 } 254 } 255 256 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw) 257 { 258 struct rtl_priv *rtlpriv = rtl_priv(hw); 259 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 260 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 261 bool fw_current_inps = true; 262 u8 rpwm_val; 263 264 if (ppsc->low_power_enable) { 265 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */ 266 rtlpriv->cfg->ops->set_hw_reg(hw, 267 HW_VAR_FW_PSMODE_STATUS, 268 (u8 *)(&fw_current_inps)); 269 rtlpriv->cfg->ops->set_hw_reg(hw, 270 HW_VAR_H2C_FW_PWRMODE, 271 (u8 *)(&ppsc->fwctrl_psmode)); 272 rtlhal->allow_sw_to_change_hwclc = true; 273 _rtl8821ae_set_fw_clock_off(hw, rpwm_val); 274 } else { 275 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */ 276 rtlpriv->cfg->ops->set_hw_reg(hw, 277 HW_VAR_FW_PSMODE_STATUS, 278 (u8 *)(&fw_current_inps)); 279 rtlpriv->cfg->ops->set_hw_reg(hw, 280 HW_VAR_H2C_FW_PWRMODE, 281 (u8 *)(&ppsc->fwctrl_psmode)); 282 rtlpriv->cfg->ops->set_hw_reg(hw, 283 HW_VAR_SET_RPWM, 284 (u8 *)(&rpwm_val)); 285 } 286 } 287 288 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw, 289 bool dl_whole_packets) 290 { 291 struct rtl_priv *rtlpriv = rtl_priv(hw); 292 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 293 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 294 u8 count = 0, dlbcn_count = 0; 295 bool send_beacon = false; 296 297 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 298 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0))); 299 300 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 301 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 302 303 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 304 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 305 tmp_reg422 & (~BIT(6))); 306 if (tmp_reg422 & BIT(6)) 307 send_beacon = true; 308 309 do { 310 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 311 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 312 (bcnvalid_reg | BIT(0))); 313 _rtl8821ae_return_beacon_queue_skb(hw); 314 315 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 316 rtl8812ae_set_fw_rsvdpagepkt(hw, false, 317 dl_whole_packets); 318 else 319 rtl8821ae_set_fw_rsvdpagepkt(hw, false, 320 dl_whole_packets); 321 322 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 323 count = 0; 324 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 325 count++; 326 udelay(10); 327 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 328 } 329 dlbcn_count++; 330 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 331 332 if (!(bcnvalid_reg & BIT(0))) 333 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 334 "Download RSVD page failed!\n"); 335 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) { 336 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0)); 337 _rtl8821ae_return_beacon_queue_skb(hw); 338 if (send_beacon) { 339 dlbcn_count = 0; 340 do { 341 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 342 bcnvalid_reg | BIT(0)); 343 344 _rtl8821ae_return_beacon_queue_skb(hw); 345 346 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 347 rtl8812ae_set_fw_rsvdpagepkt(hw, true, 348 false); 349 else 350 rtl8821ae_set_fw_rsvdpagepkt(hw, true, 351 false); 352 353 /* check rsvd page download OK. */ 354 bcnvalid_reg = rtl_read_byte(rtlpriv, 355 REG_TDECTRL + 2); 356 count = 0; 357 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 358 count++; 359 udelay(10); 360 bcnvalid_reg = 361 rtl_read_byte(rtlpriv, 362 REG_TDECTRL + 2); 363 } 364 dlbcn_count++; 365 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 366 367 if (!(bcnvalid_reg & BIT(0))) 368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 369 "2 Download RSVD page failed!\n"); 370 } 371 } 372 373 if (bcnvalid_reg & BIT(0)) 374 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); 375 376 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 377 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 378 379 if (send_beacon) 380 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 381 382 if (!rtlhal->enter_pnp_sleep) { 383 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 384 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); 385 } 386 } 387 388 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 389 { 390 struct rtl_priv *rtlpriv = rtl_priv(hw); 391 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 392 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 393 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 394 395 switch (variable) { 396 case HW_VAR_ETHER_ADDR: 397 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID); 398 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4); 399 break; 400 case HW_VAR_BSSID: 401 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID); 402 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4); 403 break; 404 case HW_VAR_MEDIA_STATUS: 405 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3; 406 break; 407 case HW_VAR_SLOT_TIME: 408 *((u8 *)(val)) = mac->slot_time; 409 break; 410 case HW_VAR_BEACON_INTERVAL: 411 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL); 412 break; 413 case HW_VAR_ATIM_WINDOW: 414 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND); 415 break; 416 case HW_VAR_RCR: 417 *((u32 *)(val)) = rtlpci->receive_config; 418 break; 419 case HW_VAR_RF_STATE: 420 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 421 break; 422 case HW_VAR_FWLPS_RF_ON:{ 423 enum rf_pwrstate rfstate; 424 u32 val_rcr; 425 426 rtlpriv->cfg->ops->get_hw_reg(hw, 427 HW_VAR_RF_STATE, 428 (u8 *)(&rfstate)); 429 if (rfstate == ERFOFF) { 430 *((bool *)(val)) = true; 431 } else { 432 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 433 val_rcr &= 0x00070000; 434 if (val_rcr) 435 *((bool *)(val)) = false; 436 else 437 *((bool *)(val)) = true; 438 } 439 break; } 440 case HW_VAR_FW_PSMODE_STATUS: 441 *((bool *)(val)) = ppsc->fw_current_inpsmode; 442 break; 443 case HW_VAR_CORRECT_TSF:{ 444 u64 tsf; 445 u32 *ptsf_low = (u32 *)&tsf; 446 u32 *ptsf_high = ((u32 *)&tsf) + 1; 447 448 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 449 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 450 451 *((u64 *)(val)) = tsf; 452 453 break; } 454 case HAL_DEF_WOWLAN: 455 if (ppsc->wo_wlan_mode) 456 *((bool *)(val)) = true; 457 else 458 *((bool *)(val)) = false; 459 break; 460 default: 461 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 462 "switch case %#x not processed\n", variable); 463 break; 464 } 465 } 466 467 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 468 { 469 struct rtl_priv *rtlpriv = rtl_priv(hw); 470 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 471 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 472 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 473 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 474 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 475 u8 idx; 476 477 switch (variable) { 478 case HW_VAR_ETHER_ADDR:{ 479 for (idx = 0; idx < ETH_ALEN; idx++) { 480 rtl_write_byte(rtlpriv, (REG_MACID + idx), 481 val[idx]); 482 } 483 break; 484 } 485 case HW_VAR_BASIC_RATE:{ 486 u16 b_rate_cfg = ((u16 *)val)[0]; 487 b_rate_cfg = b_rate_cfg & 0x15f; 488 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg); 489 break; 490 } 491 case HW_VAR_BSSID:{ 492 for (idx = 0; idx < ETH_ALEN; idx++) { 493 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 494 val[idx]); 495 } 496 break; 497 } 498 case HW_VAR_SIFS: 499 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 500 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]); 501 502 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 503 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 504 505 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 506 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]); 507 break; 508 case HW_VAR_R2T_SIFS: 509 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 510 break; 511 case HW_VAR_SLOT_TIME:{ 512 u8 e_aci; 513 514 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 515 "HW_VAR_SLOT_TIME %x\n", val[0]); 516 517 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 518 519 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 520 rtlpriv->cfg->ops->set_hw_reg(hw, 521 HW_VAR_AC_PARAM, 522 (u8 *)(&e_aci)); 523 } 524 break; } 525 case HW_VAR_ACK_PREAMBLE:{ 526 u8 reg_tmp; 527 u8 short_preamble = (bool)(*(u8 *)val); 528 529 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2); 530 if (short_preamble) { 531 reg_tmp |= BIT(1); 532 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, 533 reg_tmp); 534 } else { 535 reg_tmp &= (~BIT(1)); 536 rtl_write_byte(rtlpriv, 537 REG_TRXPTCL_CTL + 2, 538 reg_tmp); 539 } 540 break; } 541 case HW_VAR_WPA_CONFIG: 542 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 543 break; 544 case HW_VAR_AMPDU_MIN_SPACE:{ 545 u8 min_spacing_to_set; 546 u8 sec_min_space; 547 548 min_spacing_to_set = *((u8 *)val); 549 if (min_spacing_to_set <= 7) { 550 sec_min_space = 0; 551 552 if (min_spacing_to_set < sec_min_space) 553 min_spacing_to_set = sec_min_space; 554 555 mac->min_space_cfg = ((mac->min_space_cfg & 556 0xf8) | 557 min_spacing_to_set); 558 559 *val = min_spacing_to_set; 560 561 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 562 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 563 mac->min_space_cfg); 564 565 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 566 mac->min_space_cfg); 567 } 568 break; } 569 case HW_VAR_SHORTGI_DENSITY:{ 570 u8 density_to_set; 571 572 density_to_set = *((u8 *)val); 573 mac->min_space_cfg |= (density_to_set << 3); 574 575 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 576 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 577 mac->min_space_cfg); 578 579 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 580 mac->min_space_cfg); 581 582 break; } 583 case HW_VAR_AMPDU_FACTOR:{ 584 u32 ampdu_len = (*((u8 *)val)); 585 586 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 587 if (ampdu_len < VHT_AGG_SIZE_128K) 588 ampdu_len = 589 (0x2000 << (*((u8 *)val))) - 1; 590 else 591 ampdu_len = 0x1ffff; 592 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 593 if (ampdu_len < HT_AGG_SIZE_64K) 594 ampdu_len = 595 (0x2000 << (*((u8 *)val))) - 1; 596 else 597 ampdu_len = 0xffff; 598 } 599 ampdu_len |= BIT(31); 600 601 rtl_write_dword(rtlpriv, 602 REG_AMPDU_MAX_LENGTH_8812, ampdu_len); 603 break; } 604 case HW_VAR_AC_PARAM:{ 605 u8 e_aci = *((u8 *)val); 606 607 rtl8821ae_dm_init_edca_turbo(hw); 608 if (rtlpci->acm_method != EACMWAY2_SW) 609 rtlpriv->cfg->ops->set_hw_reg(hw, 610 HW_VAR_ACM_CTRL, 611 (u8 *)(&e_aci)); 612 break; } 613 case HW_VAR_ACM_CTRL:{ 614 u8 e_aci = *((u8 *)val); 615 union aci_aifsn *p_aci_aifsn = 616 (union aci_aifsn *)(&mac->ac[0].aifs); 617 u8 acm = p_aci_aifsn->f.acm; 618 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 619 620 acm_ctrl = 621 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 622 623 if (acm) { 624 switch (e_aci) { 625 case AC0_BE: 626 acm_ctrl |= ACMHW_BEQEN; 627 break; 628 case AC2_VI: 629 acm_ctrl |= ACMHW_VIQEN; 630 break; 631 case AC3_VO: 632 acm_ctrl |= ACMHW_VOQEN; 633 break; 634 default: 635 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 636 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 637 acm); 638 break; 639 } 640 } else { 641 switch (e_aci) { 642 case AC0_BE: 643 acm_ctrl &= (~ACMHW_BEQEN); 644 break; 645 case AC2_VI: 646 acm_ctrl &= (~ACMHW_VIQEN); 647 break; 648 case AC3_VO: 649 acm_ctrl &= (~ACMHW_VOQEN); 650 break; 651 default: 652 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 653 "switch case %#x not processed\n", 654 e_aci); 655 break; 656 } 657 } 658 659 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 660 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 661 acm_ctrl); 662 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 663 break; } 664 case HW_VAR_RCR: 665 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 666 rtlpci->receive_config = ((u32 *)(val))[0]; 667 break; 668 case HW_VAR_RETRY_LIMIT:{ 669 u8 retry_limit = ((u8 *)(val))[0]; 670 671 rtl_write_word(rtlpriv, REG_RL, 672 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 673 retry_limit << RETRY_LIMIT_LONG_SHIFT); 674 break; } 675 case HW_VAR_DUAL_TSF_RST: 676 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 677 break; 678 case HW_VAR_EFUSE_BYTES: 679 rtlefuse->efuse_usedbytes = *((u16 *)val); 680 break; 681 case HW_VAR_EFUSE_USAGE: 682 rtlefuse->efuse_usedpercentage = *((u8 *)val); 683 break; 684 case HW_VAR_IO_CMD: 685 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); 686 break; 687 case HW_VAR_SET_RPWM:{ 688 u8 rpwm_val; 689 690 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 691 udelay(1); 692 693 if (rpwm_val & BIT(7)) { 694 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 695 (*(u8 *)val)); 696 } else { 697 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 698 ((*(u8 *)val) | BIT(7))); 699 } 700 701 break; } 702 case HW_VAR_H2C_FW_PWRMODE: 703 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 704 break; 705 case HW_VAR_FW_PSMODE_STATUS: 706 ppsc->fw_current_inpsmode = *((bool *)val); 707 break; 708 case HW_VAR_INIT_RTS_RATE: 709 break; 710 case HW_VAR_RESUME_CLK_ON: 711 _rtl8821ae_set_fw_ps_rf_on(hw); 712 break; 713 case HW_VAR_FW_LPS_ACTION:{ 714 bool b_enter_fwlps = *((bool *)val); 715 716 if (b_enter_fwlps) 717 _rtl8821ae_fwlps_enter(hw); 718 else 719 _rtl8821ae_fwlps_leave(hw); 720 break; } 721 case HW_VAR_H2C_FW_JOINBSSRPT:{ 722 u8 mstatus = (*(u8 *)val); 723 724 if (mstatus == RT_MEDIA_CONNECT) { 725 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 726 NULL); 727 _rtl8821ae_download_rsvd_page(hw, false); 728 } 729 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus); 730 731 break; } 732 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 733 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 734 break; 735 case HW_VAR_AID:{ 736 u16 u2btmp; 737 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 738 u2btmp &= 0xC000; 739 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 740 mac->assoc_id)); 741 break; } 742 case HW_VAR_CORRECT_TSF:{ 743 u8 btype_ibss = ((u8 *)(val))[0]; 744 745 if (btype_ibss) 746 _rtl8821ae_stop_tx_beacon(hw); 747 748 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 749 750 rtl_write_dword(rtlpriv, REG_TSFTR, 751 (u32)(mac->tsf & 0xffffffff)); 752 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 753 (u32)((mac->tsf >> 32) & 0xffffffff)); 754 755 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 756 757 if (btype_ibss) 758 _rtl8821ae_resume_tx_beacon(hw); 759 break; } 760 case HW_VAR_NAV_UPPER: { 761 u32 us_nav_upper = *(u32 *)val; 762 763 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) { 764 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING, 765 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", 766 us_nav_upper, HAL_92C_NAV_UPPER_UNIT); 767 break; 768 } 769 rtl_write_byte(rtlpriv, REG_NAV_UPPER, 770 ((u8)((us_nav_upper + 771 HAL_92C_NAV_UPPER_UNIT - 1) / 772 HAL_92C_NAV_UPPER_UNIT))); 773 break; } 774 case HW_VAR_KEEP_ALIVE: { 775 u8 array[2]; 776 array[0] = 0xff; 777 array[1] = *((u8 *)val); 778 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, 779 array); 780 break; } 781 default: 782 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 783 "switch case %#x not processed\n", variable); 784 break; 785 } 786 } 787 788 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 789 { 790 struct rtl_priv *rtlpriv = rtl_priv(hw); 791 bool status = true; 792 long count = 0; 793 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 794 _LLT_OP(_LLT_WRITE_ACCESS); 795 796 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 797 798 do { 799 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 800 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 801 break; 802 803 if (count > POLLING_LLT_THRESHOLD) { 804 pr_err("Failed to polling write LLT done at address %d!\n", 805 address); 806 status = false; 807 break; 808 } 809 } while (++count); 810 811 return status; 812 } 813 814 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw) 815 { 816 struct rtl_priv *rtlpriv = rtl_priv(hw); 817 unsigned short i; 818 u8 txpktbuf_bndy; 819 u32 rqpn; 820 u8 maxpage; 821 bool status; 822 823 maxpage = 255; 824 txpktbuf_bndy = 0xF7; 825 rqpn = 0x80e60808; 826 827 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 828 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1); 829 830 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 831 832 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 833 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 834 835 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 836 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 837 838 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 839 status = _rtl8821ae_llt_write(hw, i, i + 1); 840 if (!status) 841 return status; 842 } 843 844 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 845 if (!status) 846 return status; 847 848 for (i = txpktbuf_bndy; i < maxpage; i++) { 849 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 850 if (!status) 851 return status; 852 } 853 854 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy); 855 if (!status) 856 return status; 857 858 rtl_write_dword(rtlpriv, REG_RQPN, rqpn); 859 860 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00); 861 862 return true; 863 } 864 865 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw) 866 { 867 struct rtl_priv *rtlpriv = rtl_priv(hw); 868 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 869 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 870 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 871 872 if (rtlpriv->rtlhal.up_first_time) 873 return; 874 875 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 876 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 877 rtl8812ae_sw_led_on(hw, pled0); 878 else 879 rtl8821ae_sw_led_on(hw, pled0); 880 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 881 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 882 rtl8812ae_sw_led_on(hw, pled0); 883 else 884 rtl8821ae_sw_led_on(hw, pled0); 885 else 886 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 887 rtl8812ae_sw_led_off(hw, pled0); 888 else 889 rtl8821ae_sw_led_off(hw, pled0); 890 } 891 892 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw) 893 { 894 struct rtl_priv *rtlpriv = rtl_priv(hw); 895 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 896 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 897 898 u8 bytetmp = 0; 899 u16 wordtmp = 0; 900 bool mac_func_enable = rtlhal->mac_func_enable; 901 902 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 903 904 /*Auto Power Down to CHIP-off State*/ 905 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 906 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 907 908 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 909 /* HW Power on sequence*/ 910 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 911 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 912 RTL8812_NIC_ENABLE_FLOW)) { 913 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 914 "init 8812 MAC Fail as power on failure\n"); 915 return false; 916 } 917 } else { 918 /* HW Power on sequence */ 919 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, 920 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 921 RTL8821A_NIC_ENABLE_FLOW)){ 922 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 923 "init 8821 MAC Fail as power on failure\n"); 924 return false; 925 } 926 } 927 928 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 929 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 930 931 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 932 bytetmp = 0xff; 933 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 934 mdelay(2); 935 936 bytetmp = 0xff; 937 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 938 mdelay(2); 939 940 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 941 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3); 942 if (bytetmp & BIT(0)) { 943 bytetmp = rtl_read_byte(rtlpriv, 0x7c); 944 bytetmp |= BIT(6); 945 rtl_write_byte(rtlpriv, 0x7c, bytetmp); 946 } 947 } 948 949 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 950 bytetmp &= ~BIT(4); 951 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp); 952 953 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 954 955 if (!mac_func_enable) { 956 if (!_rtl8821ae_llt_table_init(hw)) 957 return false; 958 } 959 960 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 961 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 962 963 /* Enable FW Beamformer Interrupt */ 964 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3); 965 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); 966 967 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 968 wordtmp &= 0xf; 969 wordtmp |= 0xF5B1; 970 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 971 972 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 973 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 974 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 975 /*low address*/ 976 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 977 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 978 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 979 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 980 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 981 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 982 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 983 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 984 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 985 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 986 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 987 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 988 rtl_write_dword(rtlpriv, REG_HQ_DESA, 989 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 990 rtl_write_dword(rtlpriv, REG_RX_DESA, 991 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 992 993 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 994 995 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 996 997 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0); 998 999 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3); 1000 _rtl8821ae_gen_refresh_led_state(hw); 1001 1002 return true; 1003 } 1004 1005 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw) 1006 { 1007 struct rtl_priv *rtlpriv = rtl_priv(hw); 1008 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1009 u32 reg_rrsr; 1010 1011 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 1012 1013 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 1014 /* ARFB table 9 for 11ac 5G 2SS */ 1015 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000); 1016 /* ARFB table 10 for 11ac 5G 1SS */ 1017 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000); 1018 /* ARFB table 11 for 11ac 24G 1SS */ 1019 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015); 1020 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000); 1021 /* ARFB table 12 for 11ac 24G 1SS */ 1022 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015); 1023 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000); 1024 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */ 1025 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00); 1026 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70); 1027 1028 /*Set retry limit*/ 1029 rtl_write_word(rtlpriv, REG_RL, 0x0707); 1030 1031 /* Set Data / Response auto rate fallack retry count*/ 1032 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 1033 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 1034 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 1035 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 1036 1037 rtlpci->reg_bcn_ctrl_val = 0x1d; 1038 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 1039 1040 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 1041 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1042 1043 /* AGGR_BK_TIME Reg51A 0x16 */ 1044 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 1045 1046 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 1047 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 1048 1049 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80); 1050 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 1051 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F); 1052 } 1053 1054 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr) 1055 { 1056 u16 ret = 0; 1057 u8 tmp = 0, count = 0; 1058 1059 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); 1060 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1061 count = 0; 1062 while (tmp && count < 20) { 1063 udelay(10); 1064 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1065 count++; 1066 } 1067 if (0 == tmp) 1068 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA); 1069 1070 return ret; 1071 } 1072 1073 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data) 1074 { 1075 u8 tmp = 0, count = 0; 1076 1077 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data); 1078 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); 1079 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1080 count = 0; 1081 while (tmp && count < 20) { 1082 udelay(10); 1083 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1084 count++; 1085 } 1086 } 1087 1088 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr) 1089 { 1090 u16 read_addr = addr & 0xfffc; 1091 u8 tmp = 0, count = 0, ret = 0; 1092 1093 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr); 1094 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2); 1095 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1096 count = 0; 1097 while (tmp && count < 20) { 1098 udelay(10); 1099 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1100 count++; 1101 } 1102 if (0 == tmp) { 1103 read_addr = REG_DBI_RDATA + addr % 4; 1104 ret = rtl_read_byte(rtlpriv, read_addr); 1105 } 1106 return ret; 1107 } 1108 1109 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data) 1110 { 1111 u8 tmp = 0, count = 0; 1112 u16 write_addr, remainder = addr % 4; 1113 1114 write_addr = REG_DBI_WDATA + remainder; 1115 rtl_write_byte(rtlpriv, write_addr, data); 1116 1117 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); 1118 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr); 1119 1120 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1); 1121 1122 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1123 count = 0; 1124 while (tmp && count < 20) { 1125 udelay(10); 1126 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1127 count++; 1128 } 1129 } 1130 1131 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw) 1132 { 1133 struct rtl_priv *rtlpriv = rtl_priv(hw); 1134 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1135 u8 tmp; 1136 1137 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1138 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544) 1139 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544); 1140 1141 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070) 1142 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070); 1143 } 1144 1145 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f); 1146 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) | 1147 ASPM_L1_LATENCY << 3); 1148 1149 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719); 1150 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4)); 1151 1152 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1153 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1154 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4)); 1155 } 1156 } 1157 1158 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw) 1159 { 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 u8 sec_reg_value; 1162 u8 tmp; 1163 1164 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1165 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1166 rtlpriv->sec.pairwise_enc_algorithm, 1167 rtlpriv->sec.group_enc_algorithm); 1168 1169 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1170 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1171 "not open hw encryption\n"); 1172 return; 1173 } 1174 1175 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1176 1177 if (rtlpriv->sec.use_defaultkey) { 1178 sec_reg_value |= SCR_TXUSEDK; 1179 sec_reg_value |= SCR_RXUSEDK; 1180 } 1181 1182 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1183 1184 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1185 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); 1186 1187 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1188 "The SECR-value %x\n", sec_reg_value); 1189 1190 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1191 } 1192 1193 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */ 1194 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0 1195 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1 1196 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2 1197 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3 1198 /* ----------------------------------------------------------- */ 1199 1200 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw) 1201 { 1202 struct rtl_priv *rtlpriv = rtl_priv(hw); 1203 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1, 1204 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1205 MAC_ID_STATIC_FOR_BT_CLIENT_END}; 1206 1207 rtlpriv->cfg->ops->set_hw_reg(hw, 1208 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt); 1209 1210 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1211 "Initialize MacId media status: from %d to %d\n", 1212 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1213 MAC_ID_STATIC_FOR_BT_CLIENT_END); 1214 } 1215 1216 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw) 1217 { 1218 struct rtl_priv *rtlpriv = rtl_priv(hw); 1219 u8 tmp; 1220 1221 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1222 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1223 if (!(tmp & BIT(2))) { 1224 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); 1225 mdelay(100); 1226 } 1227 1228 /* read reg 0x350 Bit[25] if 1 : RX hang */ 1229 /* read reg 0x350 Bit[24] if 1 : TX hang */ 1230 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1231 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1232 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1233 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n"); 1234 return true; 1235 } else { 1236 return false; 1237 } 1238 } 1239 1240 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw, 1241 bool mac_power_on, 1242 bool in_watchdog) 1243 { 1244 struct rtl_priv *rtlpriv = rtl_priv(hw); 1245 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1246 u8 tmp; 1247 bool release_mac_rx_pause; 1248 u8 backup_pcie_dma_pause; 1249 1250 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1251 1252 /* 1. Disable register write lock. 0x1c[1] = 0 */ 1253 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1254 tmp &= ~(BIT(1)); 1255 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1256 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1257 /* write 0xCC bit[2] = 1'b1 */ 1258 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1259 tmp |= BIT(2); 1260 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1261 } 1262 1263 /* 2. Check and pause TRX DMA */ 1264 /* write 0x284 bit[18] = 1'b1 */ 1265 /* write 0x301 = 0xFF */ 1266 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1267 if (tmp & BIT(2)) { 1268 /* Already pause before the function for another purpose. */ 1269 release_mac_rx_pause = false; 1270 } else { 1271 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1272 release_mac_rx_pause = true; 1273 } 1274 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1275 if (backup_pcie_dma_pause != 0xFF) 1276 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1277 1278 if (mac_power_on) { 1279 /* 3. reset TRX function */ 1280 /* write 0x100 = 0x00 */ 1281 rtl_write_byte(rtlpriv, REG_CR, 0); 1282 } 1283 1284 /* 4. Reset PCIe DMA. 0x3[0] = 0 */ 1285 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1286 tmp &= ~(BIT(0)); 1287 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1288 1289 /* 5. Enable PCIe DMA. 0x3[0] = 1 */ 1290 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1291 tmp |= BIT(0); 1292 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1293 1294 if (mac_power_on) { 1295 /* 6. enable TRX function */ 1296 /* write 0x100 = 0xFF */ 1297 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1298 1299 /* We should init LLT & RQPN and 1300 * prepare Tx/Rx descrptor address later 1301 * because MAC function is reset.*/ 1302 } 1303 1304 /* 7. Restore PCIe autoload down bit */ 1305 /* 8812AE does not has the defination. */ 1306 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1307 /* write 0xF8 bit[17] = 1'b1 */ 1308 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1309 tmp |= BIT(1); 1310 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1311 } 1312 1313 /* In MAC power on state, BB and RF maybe in ON state, 1314 * if we release TRx DMA here. 1315 * it will cause packets to be started to Tx/Rx, 1316 * so we release Tx/Rx DMA later.*/ 1317 if (!mac_power_on/* || in_watchdog*/) { 1318 /* 8. release TRX DMA */ 1319 /* write 0x284 bit[18] = 1'b0 */ 1320 /* write 0x301 = 0x00 */ 1321 if (release_mac_rx_pause) { 1322 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1323 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1324 tmp & (~BIT(2))); 1325 } 1326 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1327 backup_pcie_dma_pause); 1328 } 1329 1330 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1331 /* 9. lock system register */ 1332 /* write 0xCC bit[2] = 1'b0 */ 1333 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1334 tmp &= ~(BIT(2)); 1335 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1336 } 1337 return true; 1338 } 1339 1340 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw) 1341 { 1342 struct rtl_priv *rtlpriv = rtl_priv(hw); 1343 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1344 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1345 u8 fw_reason = 0; 1346 1347 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN); 1348 1349 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n", 1350 fw_reason); 1351 1352 ppsc->wakeup_reason = 0; 1353 1354 rtlhal->last_suspend_sec = ktime_get_real_seconds(); 1355 1356 switch (fw_reason) { 1357 case FW_WOW_V2_PTK_UPDATE_EVENT: 1358 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE; 1359 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1360 "It's a WOL PTK Key update event!\n"); 1361 break; 1362 case FW_WOW_V2_GTK_UPDATE_EVENT: 1363 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE; 1364 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1365 "It's a WOL GTK Key update event!\n"); 1366 break; 1367 case FW_WOW_V2_DISASSOC_EVENT: 1368 ppsc->wakeup_reason = WOL_REASON_DISASSOC; 1369 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1370 "It's a disassociation event!\n"); 1371 break; 1372 case FW_WOW_V2_DEAUTH_EVENT: 1373 ppsc->wakeup_reason = WOL_REASON_DEAUTH; 1374 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1375 "It's a deauth event!\n"); 1376 break; 1377 case FW_WOW_V2_FW_DISCONNECT_EVENT: 1378 ppsc->wakeup_reason = WOL_REASON_AP_LOST; 1379 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1380 "It's a Fw disconnect decision (AP lost) event!\n"); 1381 break; 1382 case FW_WOW_V2_MAGIC_PKT_EVENT: 1383 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT; 1384 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1385 "It's a magic packet event!\n"); 1386 break; 1387 case FW_WOW_V2_UNICAST_PKT_EVENT: 1388 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT; 1389 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1390 "It's an unicast packet event!\n"); 1391 break; 1392 case FW_WOW_V2_PATTERN_PKT_EVENT: 1393 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT; 1394 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1395 "It's a pattern match event!\n"); 1396 break; 1397 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT: 1398 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH; 1399 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1400 "It's an RTD3 Ssid match event!\n"); 1401 break; 1402 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT: 1403 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT; 1404 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1405 "It's an RealWoW wake packet event!\n"); 1406 break; 1407 case FW_WOW_V2_REALWOW_V2_ACKLOST: 1408 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST; 1409 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1410 "It's an RealWoW ack lost event!\n"); 1411 break; 1412 default: 1413 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1414 "WOL Read 0x1c7 = %02X, Unknown reason!\n", 1415 fw_reason); 1416 break; 1417 } 1418 } 1419 1420 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw) 1421 { 1422 struct rtl_priv *rtlpriv = rtl_priv(hw); 1423 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1424 1425 /*low address*/ 1426 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 1427 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 1428 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1429 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1430 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1431 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1432 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1433 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1434 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1435 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1436 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1437 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1438 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1439 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1440 rtl_write_dword(rtlpriv, REG_RX_DESA, 1441 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1442 } 1443 1444 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 1445 { 1446 bool status = true; 1447 u32 i; 1448 u32 txpktbuf_bndy = boundary; 1449 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER; 1450 1451 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) { 1452 status = _rtl8821ae_llt_write(hw, i , i + 1); 1453 if (!status) 1454 return status; 1455 } 1456 1457 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 1458 if (!status) 1459 return status; 1460 1461 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) { 1462 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 1463 if (!status) 1464 return status; 1465 } 1466 1467 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf, 1468 txpktbuf_bndy); 1469 if (!status) 1470 return status; 1471 1472 return status; 1473 } 1474 1475 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary, 1476 u16 npq_rqpn_value, u32 rqpn_val) 1477 { 1478 struct rtl_priv *rtlpriv = rtl_priv(hw); 1479 u8 tmp; 1480 bool ret = true; 1481 u16 count = 0, tmp16; 1482 bool support_remote_wakeup; 1483 1484 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1485 (u8 *)(&support_remote_wakeup)); 1486 1487 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1488 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n", 1489 boundary, npq_rqpn_value, rqpn_val); 1490 1491 /* stop PCIe DMA 1492 * 1. 0x301[7:0] = 0xFE */ 1493 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1494 1495 /* wait TXFF empty 1496 * 2. polling till 0x41A[15:0]=0x07FF */ 1497 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1498 while ((tmp16 & 0x07FF) != 0x07FF) { 1499 udelay(100); 1500 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1501 count++; 1502 if ((count % 200) == 0) { 1503 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1504 "Tx queue is not empty for 20ms!\n"); 1505 } 1506 if (count >= 1000) { 1507 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1508 "Wait for Tx FIFO empty timeout!\n"); 1509 break; 1510 } 1511 } 1512 1513 /* TX pause 1514 * 3. reg 0x522=0xFF */ 1515 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1516 1517 /* Wait TX State Machine OK 1518 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */ 1519 count = 0; 1520 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) { 1521 udelay(100); 1522 count++; 1523 if (count >= 500) { 1524 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1525 "Wait for TX State Machine ready timeout !!\n"); 1526 break; 1527 } 1528 } 1529 1530 /* stop RX DMA path 1531 * 5. 0x284[18] = 1 1532 * 6. wait till 0x284[17] == 1 1533 * wait RX DMA idle */ 1534 count = 0; 1535 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1536 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1537 do { 1538 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1539 udelay(10); 1540 count++; 1541 } while (!(tmp & BIT(1)) && count < 100); 1542 1543 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1544 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n", 1545 count, tmp); 1546 1547 /* reset BB 1548 * 7. 0x02 [0] = 0 */ 1549 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1550 tmp &= ~(BIT(0)); 1551 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp); 1552 1553 /* Reset TRX MAC 1554 * 8. 0x100 = 0x00 1555 * Delay (1ms) */ 1556 rtl_write_byte(rtlpriv, REG_CR, 0x00); 1557 udelay(1000); 1558 1559 /* Disable MAC Security Engine 1560 * 9. 0x100 bit[9]=0 */ 1561 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1562 tmp &= ~(BIT(1)); 1563 rtl_write_byte(rtlpriv, REG_CR + 1, tmp); 1564 1565 /* To avoid DD-Tim Circuit hang 1566 * 10. 0x553 bit[5]=1 */ 1567 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST); 1568 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5))); 1569 1570 /* Enable MAC Security Engine 1571 * 11. 0x100 bit[9]=1 */ 1572 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1573 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1))); 1574 1575 /* Enable TRX MAC 1576 * 12. 0x100 = 0xFF 1577 * Delay (1ms) */ 1578 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1579 udelay(1000); 1580 1581 /* Enable BB 1582 * 13. 0x02 [0] = 1 */ 1583 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1584 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0))); 1585 1586 /* beacon setting 1587 * 14,15. set beacon head page (reg 0x209 and 0x424) */ 1588 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary); 1589 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary); 1590 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary); 1591 1592 /* 16. WMAC_LBK_BF_HD 0x45D[7:0] 1593 * WMAC_LBK_BF_HD */ 1594 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, 1595 (u8)boundary); 1596 1597 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary); 1598 1599 /* init LLT 1600 * 17. init LLT */ 1601 if (!_rtl8821ae_init_llt_table(hw, boundary)) { 1602 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 1603 "Failed to init LLT table!\n"); 1604 return false; 1605 } 1606 1607 /* reallocate RQPN 1608 * 18. reallocate RQPN and init LLT */ 1609 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value); 1610 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val); 1611 1612 /* release Tx pause 1613 * 19. 0x522=0x00 */ 1614 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1615 1616 /* enable PCIE DMA 1617 * 20. 0x301[7:0] = 0x00 1618 * 21. 0x284[18] = 0 */ 1619 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1620 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1621 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2))); 1622 1623 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n"); 1624 return ret; 1625 } 1626 1627 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw) 1628 { 1629 struct rtl_priv *rtlpriv = rtl_priv(hw); 1630 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1631 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1632 1633 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 1634 /* Re-download normal Fw. */ 1635 rtl8821ae_set_fw_related_for_wowlan(hw, false); 1636 #endif 1637 1638 /* Re-Initialize LLT table. */ 1639 if (rtlhal->re_init_llt_table) { 1640 u32 rqpn = 0x80e70808; 1641 u8 rqpn_npq = 0, boundary = 0xF8; 1642 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1643 rqpn = 0x80e90808; 1644 boundary = 0xFA; 1645 } 1646 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn)) 1647 rtlhal->re_init_llt_table = false; 1648 } 1649 1650 ppsc->rfpwr_state = ERFON; 1651 } 1652 1653 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw) 1654 { 1655 u8 tmp = 0; 1656 struct rtl_priv *rtlpriv = rtl_priv(hw); 1657 1658 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1659 1660 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160); 1661 if (!(tmp & (BIT(2) | BIT(3)))) { 1662 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD, 1663 "0x160(%#x)return!!\n", tmp); 1664 return; 1665 } 1666 1667 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b); 1668 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4))); 1669 1670 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1671 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5)); 1672 1673 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1674 } 1675 1676 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw) 1677 { 1678 u8 tmp = 0; 1679 struct rtl_priv *rtlpriv = rtl_priv(hw); 1680 1681 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1682 1683 /* Check 0x98[10] */ 1684 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99); 1685 if (!(tmp & BIT(2))) { 1686 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1687 "<---0x99(%#x) return!!\n", tmp); 1688 return; 1689 } 1690 1691 /* LTR idle latency, 0x90 for 144us */ 1692 rtl_write_dword(rtlpriv, 0x798, 0x88908890); 1693 1694 /* LTR active latency, 0x3c for 60us */ 1695 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c); 1696 1697 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1698 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4))); 1699 1700 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1701 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0)))); 1702 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0))); 1703 1704 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1705 } 1706 1707 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw) 1708 { 1709 struct rtl_priv *rtlpriv = rtl_priv(hw); 1710 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1711 bool init_finished = true; 1712 u8 tmp = 0; 1713 1714 /* Get Fw wake up reason. */ 1715 _rtl8821ae_get_wakeup_reason(hw); 1716 1717 /* Patch Pcie Rx DMA hang after S3/S4 several times. 1718 * The root cause has not be found. */ 1719 if (_rtl8821ae_check_pcie_dma_hang(hw)) 1720 _rtl8821ae_reset_pcie_interface_dma(hw, true, false); 1721 1722 /* Prepare Tx/Rx Desc Hw address. */ 1723 _rtl8821ae_init_trx_desc_hw_address(hw); 1724 1725 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */ 1726 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1727 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n"); 1728 1729 /* Check wake up event. 1730 * We should check wake packet bit before disable wowlan by H2C or 1731 * Fw will clear the bit. */ 1732 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3); 1733 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1734 "Read REG_FTISR 0x13f = %#X\n", tmp); 1735 1736 /* Set the WoWLAN related function control disable. */ 1737 rtl8821ae_set_fw_wowlan_mode(hw, false); 1738 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0); 1739 1740 if (rtlhal->hw_rof_enable) { 1741 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 1742 if (tmp & BIT(1)) { 1743 /* Clear GPIO9 ISR */ 1744 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 1745 init_finished = false; 1746 } else { 1747 init_finished = true; 1748 } 1749 } 1750 1751 if (init_finished) { 1752 _rtl8821ae_simple_initialize_adapter(hw); 1753 1754 /* Release Pcie Interface Tx DMA. */ 1755 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1756 /* Release Pcie RX DMA */ 1757 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02); 1758 1759 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1760 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0)))); 1761 1762 _rtl8821ae_enable_l1off(hw); 1763 _rtl8821ae_enable_ltr(hw); 1764 } 1765 1766 return init_finished; 1767 } 1768 1769 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw) 1770 { 1771 /* BB OFDM RX Path_A */ 1772 rtl_set_bbreg(hw, 0x808, 0xff, 0x11); 1773 /* BB OFDM TX Path_A */ 1774 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111); 1775 /* BB CCK R/Rx Path_A */ 1776 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0); 1777 /* MCS support */ 1778 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4); 1779 /* RF Path_B HSSI OFF */ 1780 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4); 1781 /* RF Path_B Power Down */ 1782 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0); 1783 /* ADDA Path_B OFF */ 1784 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0); 1785 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0); 1786 } 1787 1788 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw) 1789 { 1790 struct rtl_priv *rtlpriv = rtl_priv(hw); 1791 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1792 u8 u1b_tmp; 1793 1794 rtlhal->mac_func_enable = false; 1795 1796 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1797 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1798 /* 1. Run LPS WL RFOFF flow */ 1799 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1800 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"); 1801 */ 1802 rtl_hal_pwrseqcmdparsing(rtlpriv, 1803 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1804 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW); 1805 } 1806 /* 2. 0x1F[7:0] = 0 */ 1807 /* turn off RF */ 1808 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */ 1809 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1810 rtlhal->fw_ready) { 1811 rtl8821ae_firmware_selfreset(hw); 1812 } 1813 1814 /* Reset MCU. Suggested by Filen. */ 1815 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1816 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1817 1818 /* g. MCUFWDL 0x80[1:0]=0 */ 1819 /* reset MCU ready status */ 1820 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1821 1822 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1823 /* HW card disable configuration. */ 1824 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1825 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW); 1826 } else { 1827 /* HW card disable configuration. */ 1828 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1829 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW); 1830 } 1831 1832 /* Reset MCU IO Wrapper */ 1833 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1834 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1835 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1836 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1837 1838 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1839 /* lock ISO/CLK/Power control register */ 1840 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1841 } 1842 1843 int rtl8821ae_hw_init(struct ieee80211_hw *hw) 1844 { 1845 struct rtl_priv *rtlpriv = rtl_priv(hw); 1846 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1847 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1848 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1849 bool rtstatus = true; 1850 int err; 1851 u8 tmp_u1b; 1852 bool support_remote_wakeup; 1853 u32 nav_upper = WIFI_NAV_UPPER_US; 1854 1855 rtlhal->being_init_adapter = true; 1856 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1857 (u8 *)(&support_remote_wakeup)); 1858 rtlpriv->intf_ops->disable_aspm(hw); 1859 1860 /*YP wowlan not considered*/ 1861 1862 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR); 1863 if (tmp_u1b != 0 && tmp_u1b != 0xEA) { 1864 rtlhal->mac_func_enable = true; 1865 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1866 "MAC has already power on.\n"); 1867 } else { 1868 rtlhal->mac_func_enable = false; 1869 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1870 } 1871 1872 if (support_remote_wakeup && 1873 rtlhal->wake_from_pnp_sleep && 1874 rtlhal->mac_func_enable) { 1875 if (_rtl8821ae_wowlan_initialize_adapter(hw)) { 1876 rtlhal->being_init_adapter = false; 1877 return 0; 1878 } 1879 } 1880 1881 if (_rtl8821ae_check_pcie_dma_hang(hw)) { 1882 _rtl8821ae_reset_pcie_interface_dma(hw, 1883 rtlhal->mac_func_enable, 1884 false); 1885 rtlhal->mac_func_enable = false; 1886 } 1887 1888 /* Reset MAC/BB/RF status if it is not powered off 1889 * before calling initialize Hw flow to prevent 1890 * from interface and MAC status mismatch. 1891 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */ 1892 if (rtlhal->mac_func_enable) { 1893 _rtl8821ae_poweroff_adapter(hw); 1894 rtlhal->mac_func_enable = false; 1895 } 1896 1897 rtstatus = _rtl8821ae_init_mac(hw); 1898 if (rtstatus != true) { 1899 pr_err("Init MAC failed\n"); 1900 err = 1; 1901 return err; 1902 } 1903 1904 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG); 1905 tmp_u1b &= 0x7F; 1906 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b); 1907 1908 err = rtl8821ae_download_fw(hw, false); 1909 if (err) { 1910 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1911 "Failed to download FW. Init HW without FW now\n"); 1912 err = 1; 1913 rtlhal->fw_ready = false; 1914 return err; 1915 } else { 1916 rtlhal->fw_ready = true; 1917 } 1918 ppsc->fw_current_inpsmode = false; 1919 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1920 rtlhal->fw_clk_change_in_progress = false; 1921 rtlhal->allow_sw_to_change_hwclc = false; 1922 rtlhal->last_hmeboxnum = 0; 1923 1924 /*SIC_Init(Adapter); 1925 if(rtlhal->AMPDUBurstMode) 1926 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/ 1927 1928 rtl8821ae_phy_mac_config(hw); 1929 /* because last function modify RCR, so we update 1930 * rcr var here, or TP will unstable for receive_config 1931 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1932 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1933 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 1934 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1935 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/ 1936 rtl8821ae_phy_bb_config(hw); 1937 1938 rtl8821ae_phy_rf_config(hw); 1939 1940 if (rtlpriv->phy.rf_type == RF_1T1R && 1941 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 1942 _rtl8812ae_bb8812_config_1t(hw); 1943 1944 _rtl8821ae_hw_configure(hw); 1945 1946 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); 1947 1948 /*set wireless mode*/ 1949 1950 rtlhal->mac_func_enable = true; 1951 1952 rtl_cam_reset_all_entry(hw); 1953 1954 rtl8821ae_enable_hw_security_config(hw); 1955 1956 ppsc->rfpwr_state = ERFON; 1957 1958 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1959 _rtl8821ae_enable_aspm_back_door(hw); 1960 rtlpriv->intf_ops->enable_aspm(hw); 1961 1962 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE && 1963 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5)) 1964 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302); 1965 1966 rtl8821ae_bt_hw_init(hw); 1967 rtlpriv->rtlhal.being_init_adapter = false; 1968 1969 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper); 1970 1971 /* rtl8821ae_dm_check_txpower_tracking(hw); */ 1972 /* rtl8821ae_phy_lc_calibrate(hw); */ 1973 if (support_remote_wakeup) 1974 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0); 1975 1976 /* Release Rx DMA*/ 1977 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1978 if (tmp_u1b & BIT(2)) { 1979 /* Release Rx DMA if needed*/ 1980 tmp_u1b &= ~BIT(2); 1981 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b); 1982 } 1983 1984 /* Release Tx/Rx PCIE DMA if*/ 1985 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0); 1986 1987 rtl8821ae_dm_init(hw); 1988 rtl8821ae_macid_initialize_mediastatus(hw); 1989 1990 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n"); 1991 return err; 1992 } 1993 1994 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw) 1995 { 1996 struct rtl_priv *rtlpriv = rtl_priv(hw); 1997 struct rtl_phy *rtlphy = &rtlpriv->phy; 1998 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1999 enum version_8821ae version = VERSION_UNKNOWN; 2000 u32 value32; 2001 2002 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 2003 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2004 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32); 2005 2006 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 2007 rtlphy->rf_type = RF_2T2R; 2008 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) 2009 rtlphy->rf_type = RF_1T1R; 2010 2011 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2012 "RF_Type is %x!!\n", rtlphy->rf_type); 2013 2014 if (value32 & TRP_VAUX_EN) { 2015 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2016 if (rtlphy->rf_type == RF_2T2R) 2017 version = VERSION_TEST_CHIP_2T2R_8812; 2018 else 2019 version = VERSION_TEST_CHIP_1T1R_8812; 2020 } else 2021 version = VERSION_TEST_CHIP_8821; 2022 } else { 2023 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2024 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1; 2025 2026 if (rtlphy->rf_type == RF_2T2R) 2027 version = 2028 (enum version_8821ae)(CHIP_8812 2029 | NORMAL_CHIP | 2030 RF_TYPE_2T2R); 2031 else 2032 version = (enum version_8821ae)(CHIP_8812 2033 | NORMAL_CHIP); 2034 2035 version = (enum version_8821ae)(version | (rtl_id << 12)); 2036 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2037 u32 rtl_id = value32 & CHIP_VER_RTL_MASK; 2038 2039 version = (enum version_8821ae)(CHIP_8821 2040 | NORMAL_CHIP | rtl_id); 2041 } 2042 } 2043 2044 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2045 /*WL_HWROF_EN.*/ 2046 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2047 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0); 2048 } 2049 2050 switch (version) { 2051 case VERSION_TEST_CHIP_1T1R_8812: 2052 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2053 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n"); 2054 break; 2055 case VERSION_TEST_CHIP_2T2R_8812: 2056 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2057 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n"); 2058 break; 2059 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812: 2060 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2061 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n"); 2062 break; 2063 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812: 2064 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2065 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n"); 2066 break; 2067 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT: 2068 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2069 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n"); 2070 break; 2071 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT: 2072 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2073 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n"); 2074 break; 2075 case VERSION_TEST_CHIP_8821: 2076 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2077 "Chip Version ID: VERSION_TEST_CHIP_8821\n"); 2078 break; 2079 case VERSION_NORMAL_TSMC_CHIP_8821: 2080 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2081 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n"); 2082 break; 2083 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT: 2084 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2085 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n"); 2086 break; 2087 default: 2088 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2089 "Chip Version ID: Unknown (0x%X)\n", version); 2090 break; 2091 } 2092 2093 return version; 2094 } 2095 2096 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw, 2097 enum nl80211_iftype type) 2098 { 2099 struct rtl_priv *rtlpriv = rtl_priv(hw); 2100 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 2101 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 2102 bt_msr &= 0xfc; 2103 2104 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 2105 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, 2106 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 2107 2108 if (type == NL80211_IFTYPE_UNSPECIFIED || 2109 type == NL80211_IFTYPE_STATION) { 2110 _rtl8821ae_stop_tx_beacon(hw); 2111 _rtl8821ae_enable_bcn_sub_func(hw); 2112 } else if (type == NL80211_IFTYPE_ADHOC || 2113 type == NL80211_IFTYPE_AP) { 2114 _rtl8821ae_resume_tx_beacon(hw); 2115 _rtl8821ae_disable_bcn_sub_func(hw); 2116 } else { 2117 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2118 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 2119 type); 2120 } 2121 2122 switch (type) { 2123 case NL80211_IFTYPE_UNSPECIFIED: 2124 bt_msr |= MSR_NOLINK; 2125 ledaction = LED_CTL_LINK; 2126 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2127 "Set Network type to NO LINK!\n"); 2128 break; 2129 case NL80211_IFTYPE_ADHOC: 2130 bt_msr |= MSR_ADHOC; 2131 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2132 "Set Network type to Ad Hoc!\n"); 2133 break; 2134 case NL80211_IFTYPE_STATION: 2135 bt_msr |= MSR_INFRA; 2136 ledaction = LED_CTL_LINK; 2137 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2138 "Set Network type to STA!\n"); 2139 break; 2140 case NL80211_IFTYPE_AP: 2141 bt_msr |= MSR_AP; 2142 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2143 "Set Network type to AP!\n"); 2144 break; 2145 default: 2146 pr_err("Network type %d not support!\n", type); 2147 return 1; 2148 } 2149 2150 rtl_write_byte(rtlpriv, MSR, bt_msr); 2151 rtlpriv->cfg->ops->led_control(hw, ledaction); 2152 if ((bt_msr & MSR_MASK) == MSR_AP) 2153 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 2154 else 2155 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 2156 2157 return 0; 2158 } 2159 2160 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 2161 { 2162 struct rtl_priv *rtlpriv = rtl_priv(hw); 2163 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2164 u32 reg_rcr = rtlpci->receive_config; 2165 2166 if (rtlpriv->psc.rfpwr_state != ERFON) 2167 return; 2168 2169 if (check_bssid) { 2170 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 2171 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 2172 (u8 *)(®_rcr)); 2173 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 2174 } else if (!check_bssid) { 2175 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 2176 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 2177 rtlpriv->cfg->ops->set_hw_reg(hw, 2178 HW_VAR_RCR, (u8 *)(®_rcr)); 2179 } 2180 } 2181 2182 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 2183 { 2184 struct rtl_priv *rtlpriv = rtl_priv(hw); 2185 2186 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n"); 2187 2188 if (_rtl8821ae_set_media_status(hw, type)) 2189 return -EOPNOTSUPP; 2190 2191 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 2192 if (type != NL80211_IFTYPE_AP) 2193 rtl8821ae_set_check_bssid(hw, true); 2194 } else { 2195 rtl8821ae_set_check_bssid(hw, false); 2196 } 2197 2198 return 0; 2199 } 2200 2201 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 2202 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci) 2203 { 2204 struct rtl_priv *rtlpriv = rtl_priv(hw); 2205 rtl8821ae_dm_init_edca_turbo(hw); 2206 switch (aci) { 2207 case AC1_BK: 2208 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 2209 break; 2210 case AC0_BE: 2211 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 2212 break; 2213 case AC2_VI: 2214 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 2215 break; 2216 case AC3_VO: 2217 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 2218 break; 2219 default: 2220 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci); 2221 break; 2222 } 2223 } 2224 2225 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw) 2226 { 2227 struct rtl_priv *rtlpriv = rtl_priv(hw); 2228 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR); 2229 2230 rtl_write_dword(rtlpriv, REG_HISR, tmp); 2231 2232 tmp = rtl_read_dword(rtlpriv, REG_HISRE); 2233 rtl_write_dword(rtlpriv, REG_HISRE, tmp); 2234 2235 tmp = rtl_read_dword(rtlpriv, REG_HSISR); 2236 rtl_write_dword(rtlpriv, REG_HSISR, tmp); 2237 } 2238 2239 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw) 2240 { 2241 struct rtl_priv *rtlpriv = rtl_priv(hw); 2242 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2243 2244 if (rtlpci->int_clear) 2245 rtl8821ae_clear_interrupt(hw);/*clear it here first*/ 2246 2247 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 2248 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 2249 rtlpci->irq_enabled = true; 2250 /* there are some C2H CMDs have been sent before 2251 system interrupt is enabled, e.g., C2H, CPWM. 2252 *So we need to clear all C2H events that FW has 2253 notified, otherwise FW won't schedule any commands anymore. 2254 */ 2255 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */ 2256 /*enable system interrupt*/ 2257 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF); 2258 } 2259 2260 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw) 2261 { 2262 struct rtl_priv *rtlpriv = rtl_priv(hw); 2263 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2264 2265 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 2266 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 2267 rtlpci->irq_enabled = false; 2268 /*synchronize_irq(rtlpci->pdev->irq);*/ 2269 } 2270 2271 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw) 2272 { 2273 struct rtl_priv *rtlpriv = rtl_priv(hw); 2274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2275 u16 cap_hdr; 2276 u8 cap_pointer; 2277 u8 cap_id = 0xff; 2278 u8 pmcs_reg; 2279 u8 cnt = 0; 2280 2281 /* Get the Capability pointer first, 2282 * the Capability Pointer is located at 2283 * offset 0x34 from the Function Header */ 2284 2285 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer); 2286 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2287 "PCI configuration 0x34 = 0x%2x\n", cap_pointer); 2288 2289 do { 2290 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr); 2291 cap_id = cap_hdr & 0xFF; 2292 2293 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2294 "in pci configuration, cap_pointer%x = %x\n", 2295 cap_pointer, cap_id); 2296 2297 if (cap_id == 0x01) { 2298 break; 2299 } else { 2300 /* point to next Capability */ 2301 cap_pointer = (cap_hdr >> 8) & 0xFF; 2302 /* 0: end of pci capability, 0xff: invalid value */ 2303 if (cap_pointer == 0x00 || cap_pointer == 0xff) { 2304 cap_id = 0xff; 2305 break; 2306 } 2307 } 2308 } while (cnt++ < 200); 2309 2310 if (cap_id == 0x01) { 2311 /* Get the PM CSR (Control/Status Register), 2312 * The PME_Status is located at PM Capatibility offset 5, bit 7 2313 */ 2314 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg); 2315 2316 if (pmcs_reg & BIT(7)) { 2317 /* PME event occured, clear the PM_Status by write 1 */ 2318 pmcs_reg = pmcs_reg | BIT(7); 2319 2320 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5, 2321 pmcs_reg); 2322 /* Read it back to check */ 2323 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, 2324 &pmcs_reg); 2325 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2326 "Clear PME status 0x%2x to 0x%2x\n", 2327 cap_pointer + 5, pmcs_reg); 2328 } else { 2329 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2330 "PME status(0x%2x) = 0x%2x\n", 2331 cap_pointer + 5, pmcs_reg); 2332 } 2333 } else { 2334 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 2335 "Cannot find PME Capability\n"); 2336 } 2337 } 2338 2339 void rtl8821ae_card_disable(struct ieee80211_hw *hw) 2340 { 2341 struct rtl_priv *rtlpriv = rtl_priv(hw); 2342 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2343 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 2344 struct rtl_mac *mac = rtl_mac(rtlpriv); 2345 enum nl80211_iftype opmode; 2346 bool support_remote_wakeup; 2347 u8 tmp; 2348 u32 count = 0; 2349 2350 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 2351 (u8 *)(&support_remote_wakeup)); 2352 2353 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2354 2355 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION) 2356 || !rtlhal->enter_pnp_sleep) { 2357 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n"); 2358 mac->link_state = MAC80211_NOLINK; 2359 opmode = NL80211_IFTYPE_UNSPECIFIED; 2360 _rtl8821ae_set_media_status(hw, opmode); 2361 _rtl8821ae_poweroff_adapter(hw); 2362 } else { 2363 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n"); 2364 /* 3 <1> Prepare for configuring wowlan related infomations */ 2365 /* Clear Fw WoWLAN event. */ 2366 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0); 2367 2368 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 2369 rtl8821ae_set_fw_related_for_wowlan(hw, true); 2370 #endif 2371 /* Dynamically adjust Tx packet boundary 2372 * for download reserved page packet. 2373 * reserve 30 pages for rsvd page */ 2374 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d)) 2375 rtlhal->re_init_llt_table = true; 2376 2377 /* 3 <2> Set Fw releted H2C cmd. */ 2378 2379 /* Set WoWLAN related security information. */ 2380 rtl8821ae_set_fw_global_info_cmd(hw); 2381 2382 _rtl8821ae_download_rsvd_page(hw, true); 2383 2384 /* Just enable AOAC related functions when we connect to AP. */ 2385 printk("mac->link_state = %d\n", mac->link_state); 2386 if (mac->link_state >= MAC80211_LINKED && 2387 mac->opmode == NL80211_IFTYPE_STATION) { 2388 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 2389 rtl8821ae_set_fw_media_status_rpt_cmd(hw, 2390 RT_MEDIA_CONNECT); 2391 2392 rtl8821ae_set_fw_wowlan_mode(hw, true); 2393 /* Enable Fw Keep alive mechanism. */ 2394 rtl8821ae_set_fw_keep_alive_cmd(hw, true); 2395 2396 /* Enable disconnect decision control. */ 2397 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true); 2398 } 2399 2400 /* 3 <3> Hw Configutations */ 2401 2402 /* Wait untill Rx DMA Finished before host sleep. 2403 * FW Pause Rx DMA may happens when received packet doing dma. 2404 */ 2405 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2)); 2406 2407 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2408 count = 0; 2409 while (!(tmp & BIT(1)) && (count++ < 100)) { 2410 udelay(10); 2411 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2412 } 2413 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2414 "Wait Rx DMA Finished before host sleep. count=%d\n", 2415 count); 2416 2417 /* reset trx ring */ 2418 rtlpriv->intf_ops->reset_trx_ring(hw); 2419 2420 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0); 2421 2422 _rtl8821ae_clear_pci_pme_status(hw); 2423 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 2424 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3)); 2425 /* prevent 8051 to be reset by PERST */ 2426 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20); 2427 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60); 2428 } 2429 2430 if (rtlpriv->rtlhal.driver_is_goingto_unload || 2431 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 2432 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 2433 /* For wowlan+LPS+32k. */ 2434 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) { 2435 /* Set the WoWLAN related function control enable. 2436 * It should be the last H2C cmd in the WoWLAN flow. */ 2437 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1); 2438 2439 /* Stop Pcie Interface Tx DMA. */ 2440 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); 2441 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n"); 2442 2443 /* Wait for TxDMA idle. */ 2444 count = 0; 2445 do { 2446 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG); 2447 udelay(10); 2448 count++; 2449 } while ((tmp != 0) && (count < 100)); 2450 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2451 "Wait Tx DMA Finished before host sleep. count=%d\n", 2452 count); 2453 2454 if (rtlhal->hw_rof_enable) { 2455 printk("hw_rof_enable\n"); 2456 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 2457 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 2458 } 2459 } 2460 /* after power off we should do iqk again */ 2461 rtlpriv->phy.iqk_initialized = false; 2462 } 2463 2464 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw, 2465 struct rtl_int *intvec) 2466 { 2467 struct rtl_priv *rtlpriv = rtl_priv(hw); 2468 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2469 2470 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 2471 rtl_write_dword(rtlpriv, ISR, intvec->inta); 2472 2473 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 2474 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb); 2475 } 2476 2477 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw) 2478 { 2479 struct rtl_priv *rtlpriv = rtl_priv(hw); 2480 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2481 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2482 u16 bcn_interval, atim_window; 2483 2484 bcn_interval = mac->beacon_interval; 2485 atim_window = 2; /*FIX MERGE */ 2486 rtl8821ae_disable_interrupt(hw); 2487 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 2488 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2489 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 2490 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 2491 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 2492 rtl_write_byte(rtlpriv, 0x606, 0x30); 2493 rtlpci->reg_bcn_ctrl_val |= BIT(3); 2494 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 2495 rtl8821ae_enable_interrupt(hw); 2496 } 2497 2498 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw) 2499 { 2500 struct rtl_priv *rtlpriv = rtl_priv(hw); 2501 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2502 u16 bcn_interval = mac->beacon_interval; 2503 2504 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 2505 "beacon_interval:%d\n", bcn_interval); 2506 rtl8821ae_disable_interrupt(hw); 2507 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2508 rtl8821ae_enable_interrupt(hw); 2509 } 2510 2511 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw, 2512 u32 add_msr, u32 rm_msr) 2513 { 2514 struct rtl_priv *rtlpriv = rtl_priv(hw); 2515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2516 2517 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 2518 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 2519 2520 if (add_msr) 2521 rtlpci->irq_mask[0] |= add_msr; 2522 if (rm_msr) 2523 rtlpci->irq_mask[0] &= (~rm_msr); 2524 rtl8821ae_disable_interrupt(hw); 2525 rtl8821ae_enable_interrupt(hw); 2526 } 2527 2528 static u8 _rtl8821ae_get_chnl_group(u8 chnl) 2529 { 2530 u8 group = 0; 2531 2532 if (chnl <= 14) { 2533 if (1 <= chnl && chnl <= 2) 2534 group = 0; 2535 else if (3 <= chnl && chnl <= 5) 2536 group = 1; 2537 else if (6 <= chnl && chnl <= 8) 2538 group = 2; 2539 else if (9 <= chnl && chnl <= 11) 2540 group = 3; 2541 else /*if (12 <= chnl && chnl <= 14)*/ 2542 group = 4; 2543 } else { 2544 if (36 <= chnl && chnl <= 42) 2545 group = 0; 2546 else if (44 <= chnl && chnl <= 48) 2547 group = 1; 2548 else if (50 <= chnl && chnl <= 58) 2549 group = 2; 2550 else if (60 <= chnl && chnl <= 64) 2551 group = 3; 2552 else if (100 <= chnl && chnl <= 106) 2553 group = 4; 2554 else if (108 <= chnl && chnl <= 114) 2555 group = 5; 2556 else if (116 <= chnl && chnl <= 122) 2557 group = 6; 2558 else if (124 <= chnl && chnl <= 130) 2559 group = 7; 2560 else if (132 <= chnl && chnl <= 138) 2561 group = 8; 2562 else if (140 <= chnl && chnl <= 144) 2563 group = 9; 2564 else if (149 <= chnl && chnl <= 155) 2565 group = 10; 2566 else if (157 <= chnl && chnl <= 161) 2567 group = 11; 2568 else if (165 <= chnl && chnl <= 171) 2569 group = 12; 2570 else if (173 <= chnl && chnl <= 177) 2571 group = 13; 2572 else 2573 WARN_ONCE(true, 2574 "rtl8821ae: 5G, Channel %d in Group not found\n", 2575 chnl); 2576 } 2577 return group; 2578 } 2579 2580 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw, 2581 struct txpower_info_2g *pwrinfo24g, 2582 struct txpower_info_5g *pwrinfo5g, 2583 bool autoload_fail, 2584 u8 *hwinfo) 2585 { 2586 struct rtl_priv *rtlpriv = rtl_priv(hw); 2587 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcount = 0; 2588 2589 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2590 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n", 2591 (eeaddr + 1), hwinfo[eeaddr + 1]); 2592 if (hwinfo[eeaddr + 1] == 0xFF) /*YJ,add,120316*/ 2593 autoload_fail = true; 2594 2595 if (autoload_fail) { 2596 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2597 "auto load fail : Use Default value!\n"); 2598 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 2599 /*2.4G default value*/ 2600 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2601 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D; 2602 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D; 2603 } 2604 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2605 if (txcount == 0) { 2606 pwrinfo24g->bw20_diff[rfpath][0] = 0x02; 2607 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04; 2608 } else { 2609 pwrinfo24g->bw20_diff[rfpath][txcount] = 0xFE; 2610 pwrinfo24g->bw40_diff[rfpath][txcount] = 0xFE; 2611 pwrinfo24g->cck_diff[rfpath][txcount] = 0xFE; 2612 pwrinfo24g->ofdm_diff[rfpath][txcount] = 0xFE; 2613 } 2614 } 2615 /*5G default value*/ 2616 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) 2617 pwrinfo5g->index_bw40_base[rfpath][group] = 0x2A; 2618 2619 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2620 if (txcount == 0) { 2621 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04; 2622 pwrinfo5g->bw20_diff[rfpath][0] = 0x00; 2623 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE; 2624 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE; 2625 } else { 2626 pwrinfo5g->ofdm_diff[rfpath][0] = 0xFE; 2627 pwrinfo5g->bw20_diff[rfpath][0] = 0xFE; 2628 pwrinfo5g->bw40_diff[rfpath][0] = 0xFE; 2629 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE; 2630 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE; 2631 } 2632 } 2633 } 2634 return; 2635 } 2636 2637 rtl_priv(hw)->efuse.txpwr_fromeprom = true; 2638 2639 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 2640 /*2.4G default value*/ 2641 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2642 pwrinfo24g->index_cck_base[rfpath][group] = hwinfo[eeaddr++]; 2643 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF) 2644 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D; 2645 } 2646 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { 2647 pwrinfo24g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++]; 2648 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF) 2649 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D; 2650 } 2651 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2652 if (txcount == 0) { 2653 pwrinfo24g->bw40_diff[rfpath][txcount] = 0; 2654 /*bit sign number to 8 bit sign number*/ 2655 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2656 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3)) 2657 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0; 2658 /*bit sign number to 8 bit sign number*/ 2659 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2660 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3)) 2661 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0; 2662 2663 pwrinfo24g->cck_diff[rfpath][txcount] = 0; 2664 eeaddr++; 2665 } else { 2666 pwrinfo24g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2667 if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3)) 2668 pwrinfo24g->bw40_diff[rfpath][txcount] |= 0xF0; 2669 2670 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2671 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3)) 2672 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0; 2673 2674 eeaddr++; 2675 2676 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2677 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3)) 2678 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0; 2679 2680 pwrinfo24g->cck_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2681 if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3)) 2682 pwrinfo24g->cck_diff[rfpath][txcount] |= 0xF0; 2683 2684 eeaddr++; 2685 } 2686 } 2687 2688 /*5G default value*/ 2689 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 2690 pwrinfo5g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++]; 2691 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF) 2692 pwrinfo5g->index_bw40_base[rfpath][group] = 0xFE; 2693 } 2694 2695 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2696 if (txcount == 0) { 2697 pwrinfo5g->bw40_diff[rfpath][txcount] = 0; 2698 2699 pwrinfo5g->bw20_diff[rfpath][0] = (hwinfo[eeaddr] & 0xf0) >> 4; 2700 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3)) 2701 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0; 2702 2703 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr] & 0x0f); 2704 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3)) 2705 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0; 2706 2707 eeaddr++; 2708 } else { 2709 pwrinfo5g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2710 if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3)) 2711 pwrinfo5g->bw40_diff[rfpath][txcount] |= 0xF0; 2712 2713 pwrinfo5g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2714 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3)) 2715 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0; 2716 2717 eeaddr++; 2718 } 2719 } 2720 2721 pwrinfo5g->ofdm_diff[rfpath][1] = (hwinfo[eeaddr] & 0xf0) >> 4; 2722 pwrinfo5g->ofdm_diff[rfpath][2] = (hwinfo[eeaddr] & 0x0f); 2723 2724 eeaddr++; 2725 2726 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr] & 0x0f); 2727 2728 eeaddr++; 2729 2730 for (txcount = 1; txcount < MAX_TX_COUNT; txcount++) { 2731 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3)) 2732 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0; 2733 } 2734 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { 2735 pwrinfo5g->bw80_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4; 2736 /* 4bit sign number to 8 bit sign number */ 2737 if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3)) 2738 pwrinfo5g->bw80_diff[rfpath][txcount] |= 0xF0; 2739 /* 4bit sign number to 8 bit sign number */ 2740 pwrinfo5g->bw160_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f); 2741 if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3)) 2742 pwrinfo5g->bw160_diff[rfpath][txcount] |= 0xF0; 2743 2744 eeaddr++; 2745 } 2746 } 2747 } 2748 #if 0 2749 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2750 bool autoload_fail, 2751 u8 *hwinfo) 2752 { 2753 struct rtl_priv *rtlpriv = rtl_priv(hw); 2754 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2755 struct txpower_info_2g pwrinfo24g; 2756 struct txpower_info_5g pwrinfo5g; 2757 u8 rf_path, index; 2758 u8 i; 2759 2760 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2761 &pwrinfo5g, autoload_fail, hwinfo); 2762 2763 for (rf_path = 0; rf_path < 2; rf_path++) { 2764 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2765 index = _rtl8821ae_get_chnl_group(i + 1); 2766 2767 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2768 rtlefuse->txpwrlevel_cck[rf_path][i] = 2769 pwrinfo24g.index_cck_base[rf_path][5]; 2770 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2771 pwrinfo24g.index_bw40_base[rf_path][index]; 2772 } else { 2773 rtlefuse->txpwrlevel_cck[rf_path][i] = 2774 pwrinfo24g.index_cck_base[rf_path][index]; 2775 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2776 pwrinfo24g.index_bw40_base[rf_path][index]; 2777 } 2778 } 2779 2780 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2781 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2782 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2783 pwrinfo5g.index_bw40_base[rf_path][index]; 2784 } 2785 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2786 u8 upper, lower; 2787 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2788 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2789 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2790 2791 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2792 } 2793 for (i = 0; i < MAX_TX_COUNT; i++) { 2794 rtlefuse->txpwr_cckdiff[rf_path][i] = 2795 pwrinfo24g.cck_diff[rf_path][i]; 2796 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2797 pwrinfo24g.ofdm_diff[rf_path][i]; 2798 rtlefuse->txpwr_ht20diff[rf_path][i] = 2799 pwrinfo24g.bw20_diff[rf_path][i]; 2800 rtlefuse->txpwr_ht40diff[rf_path][i] = 2801 pwrinfo24g.bw40_diff[rf_path][i]; 2802 2803 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2804 pwrinfo5g.ofdm_diff[rf_path][i]; 2805 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2806 pwrinfo5g.bw20_diff[rf_path][i]; 2807 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2808 pwrinfo5g.bw40_diff[rf_path][i]; 2809 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2810 pwrinfo5g.bw80_diff[rf_path][i]; 2811 } 2812 } 2813 2814 if (!autoload_fail) { 2815 rtlefuse->eeprom_regulatory = 2816 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/ 2817 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2818 rtlefuse->eeprom_regulatory = 0; 2819 } else { 2820 rtlefuse->eeprom_regulatory = 0; 2821 } 2822 2823 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2824 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2825 } 2826 #endif 2827 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2828 bool autoload_fail, 2829 u8 *hwinfo) 2830 { 2831 struct rtl_priv *rtlpriv = rtl_priv(hw); 2832 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2833 struct txpower_info_2g pwrinfo24g; 2834 struct txpower_info_5g pwrinfo5g; 2835 u8 rf_path, index; 2836 u8 i; 2837 2838 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2839 &pwrinfo5g, autoload_fail, hwinfo); 2840 2841 for (rf_path = 0; rf_path < 2; rf_path++) { 2842 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2843 index = _rtl8821ae_get_chnl_group(i + 1); 2844 2845 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2846 rtlefuse->txpwrlevel_cck[rf_path][i] = 2847 pwrinfo24g.index_cck_base[rf_path][5]; 2848 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2849 pwrinfo24g.index_bw40_base[rf_path][index]; 2850 } else { 2851 rtlefuse->txpwrlevel_cck[rf_path][i] = 2852 pwrinfo24g.index_cck_base[rf_path][index]; 2853 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2854 pwrinfo24g.index_bw40_base[rf_path][index]; 2855 } 2856 } 2857 2858 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2859 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2860 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2861 pwrinfo5g.index_bw40_base[rf_path][index]; 2862 } 2863 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2864 u8 upper, lower; 2865 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2866 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2867 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2868 2869 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2870 } 2871 for (i = 0; i < MAX_TX_COUNT; i++) { 2872 rtlefuse->txpwr_cckdiff[rf_path][i] = 2873 pwrinfo24g.cck_diff[rf_path][i]; 2874 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2875 pwrinfo24g.ofdm_diff[rf_path][i]; 2876 rtlefuse->txpwr_ht20diff[rf_path][i] = 2877 pwrinfo24g.bw20_diff[rf_path][i]; 2878 rtlefuse->txpwr_ht40diff[rf_path][i] = 2879 pwrinfo24g.bw40_diff[rf_path][i]; 2880 2881 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2882 pwrinfo5g.ofdm_diff[rf_path][i]; 2883 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2884 pwrinfo5g.bw20_diff[rf_path][i]; 2885 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2886 pwrinfo5g.bw40_diff[rf_path][i]; 2887 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2888 pwrinfo5g.bw80_diff[rf_path][i]; 2889 } 2890 } 2891 /*bit0~2*/ 2892 if (!autoload_fail) { 2893 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07; 2894 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2895 rtlefuse->eeprom_regulatory = 0; 2896 } else { 2897 rtlefuse->eeprom_regulatory = 0; 2898 } 2899 2900 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2901 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2902 } 2903 2904 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2905 bool autoload_fail) 2906 { 2907 struct rtl_priv *rtlpriv = rtl_priv(hw); 2908 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2909 2910 if (!autoload_fail) { 2911 rtlhal->pa_type_2g = hwinfo[0XBC]; 2912 rtlhal->lna_type_2g = hwinfo[0XBD]; 2913 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2914 rtlhal->pa_type_2g = 0; 2915 rtlhal->lna_type_2g = 0; 2916 } 2917 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) && 2918 (rtlhal->pa_type_2g & BIT(4))) ? 2919 1 : 0; 2920 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) && 2921 (rtlhal->lna_type_2g & BIT(3))) ? 2922 1 : 0; 2923 2924 rtlhal->pa_type_5g = hwinfo[0XBC]; 2925 rtlhal->lna_type_5g = hwinfo[0XBF]; 2926 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 2927 rtlhal->pa_type_5g = 0; 2928 rtlhal->lna_type_5g = 0; 2929 } 2930 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) && 2931 (rtlhal->pa_type_5g & BIT(0))) ? 2932 1 : 0; 2933 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) && 2934 (rtlhal->lna_type_5g & BIT(3))) ? 2935 1 : 0; 2936 } else { 2937 rtlhal->external_pa_2g = 0; 2938 rtlhal->external_lna_2g = 0; 2939 rtlhal->external_pa_5g = 0; 2940 rtlhal->external_lna_5g = 0; 2941 } 2942 } 2943 2944 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo, 2945 bool autoload_fail) 2946 { 2947 struct rtl_priv *rtlpriv = rtl_priv(hw); 2948 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2949 2950 u8 ext_type_pa_2g_a = (hwinfo[0XBD] & BIT(2)) >> 2; /* 0XBD[2] */ 2951 u8 ext_type_pa_2g_b = (hwinfo[0XBD] & BIT(6)) >> 6; /* 0XBD[6] */ 2952 u8 ext_type_pa_5g_a = (hwinfo[0XBF] & BIT(2)) >> 2; /* 0XBF[2] */ 2953 u8 ext_type_pa_5g_b = (hwinfo[0XBF] & BIT(6)) >> 6; /* 0XBF[6] */ 2954 /* 0XBD[1:0] */ 2955 u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0; 2956 /* 0XBD[5:4] */ 2957 u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4; 2958 /* 0XBF[1:0] */ 2959 u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0; 2960 /* 0XBF[5:4] */ 2961 u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4; 2962 2963 _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail); 2964 2965 /* [2.4G] Path A and B are both extPA */ 2966 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4))) 2967 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a; 2968 2969 /* [5G] Path A and B are both extPA */ 2970 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0))) 2971 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a; 2972 2973 /* [2.4G] Path A and B are both extLNA */ 2974 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 2975 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a; 2976 2977 /* [5G] Path A and B are both extLNA */ 2978 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 2979 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a; 2980 } 2981 2982 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2983 bool autoload_fail) 2984 { 2985 struct rtl_priv *rtlpriv = rtl_priv(hw); 2986 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2987 2988 if (!autoload_fail) { 2989 rtlhal->pa_type_2g = hwinfo[0XBC]; 2990 rtlhal->lna_type_2g = hwinfo[0XBD]; 2991 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2992 rtlhal->pa_type_2g = 0; 2993 rtlhal->lna_type_2g = 0; 2994 } 2995 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0; 2996 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0; 2997 2998 rtlhal->pa_type_5g = hwinfo[0XBC]; 2999 rtlhal->lna_type_5g = hwinfo[0XBF]; 3000 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 3001 rtlhal->pa_type_5g = 0; 3002 rtlhal->lna_type_5g = 0; 3003 } 3004 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0; 3005 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0; 3006 } else { 3007 rtlhal->external_pa_2g = 0; 3008 rtlhal->external_lna_2g = 0; 3009 rtlhal->external_pa_5g = 0; 3010 rtlhal->external_lna_5g = 0; 3011 } 3012 } 3013 3014 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo, 3015 bool autoload_fail) 3016 { 3017 struct rtl_priv *rtlpriv = rtl_priv(hw); 3018 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 3019 3020 if (!autoload_fail) { 3021 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) { 3022 if (rtlhal->external_lna_5g) { 3023 if (rtlhal->external_pa_5g) { 3024 if (rtlhal->external_lna_2g && 3025 rtlhal->external_pa_2g) 3026 rtlhal->rfe_type = 3; 3027 else 3028 rtlhal->rfe_type = 0; 3029 } else { 3030 rtlhal->rfe_type = 2; 3031 } 3032 } else { 3033 rtlhal->rfe_type = 4; 3034 } 3035 } else { 3036 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F; 3037 3038 if (rtlhal->rfe_type == 4 && 3039 (rtlhal->external_pa_5g || 3040 rtlhal->external_pa_2g || 3041 rtlhal->external_lna_5g || 3042 rtlhal->external_lna_2g)) { 3043 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 3044 rtlhal->rfe_type = 2; 3045 } 3046 } 3047 } else { 3048 rtlhal->rfe_type = 0x04; 3049 } 3050 3051 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3052 "RFE Type: 0x%2x\n", rtlhal->rfe_type); 3053 } 3054 3055 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3056 bool auto_load_fail, u8 *hwinfo) 3057 { 3058 struct rtl_priv *rtlpriv = rtl_priv(hw); 3059 u8 value; 3060 3061 if (!auto_load_fail) { 3062 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION]; 3063 if (((value & 0xe0) >> 5) == 0x1) 3064 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3065 else 3066 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3067 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3068 3069 value = hwinfo[EEPROM_RF_BT_SETTING]; 3070 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3071 } else { 3072 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3073 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3074 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3075 } 3076 /*move BT_InitHalVars() to init_sw_vars*/ 3077 } 3078 3079 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3080 bool auto_load_fail, u8 *hwinfo) 3081 { 3082 struct rtl_priv *rtlpriv = rtl_priv(hw); 3083 u8 value; 3084 u32 tmpu_32; 3085 3086 if (!auto_load_fail) { 3087 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 3088 if (tmpu_32 & BIT(18)) 3089 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3090 else 3091 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3092 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3093 3094 value = hwinfo[EEPROM_RF_BT_SETTING]; 3095 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3096 } else { 3097 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3098 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3099 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3100 } 3101 /*move BT_InitHalVars() to init_sw_vars*/ 3102 } 3103 3104 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test) 3105 { 3106 struct rtl_priv *rtlpriv = rtl_priv(hw); 3107 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3108 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3109 int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID, 3110 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 3111 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 3112 COUNTRY_CODE_WORLD_WIDE_13}; 3113 u8 *hwinfo; 3114 3115 if (b_pseudo_test) { 3116 ;/* need add */ 3117 } 3118 3119 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 3120 if (!hwinfo) 3121 return; 3122 3123 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 3124 goto exit; 3125 3126 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 3127 hwinfo); 3128 3129 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 3130 _rtl8812ae_read_amplifier_type(hw, hwinfo, 3131 rtlefuse->autoload_failflag); 3132 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw, 3133 rtlefuse->autoload_failflag, hwinfo); 3134 } else { 3135 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag); 3136 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw, 3137 rtlefuse->autoload_failflag, hwinfo); 3138 } 3139 3140 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag); 3141 /*board type*/ 3142 rtlefuse->board_type = ODM_BOARD_DEFAULT; 3143 if (rtlhal->external_lna_2g != 0) 3144 rtlefuse->board_type |= ODM_BOARD_EXT_LNA; 3145 if (rtlhal->external_lna_5g != 0) 3146 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G; 3147 if (rtlhal->external_pa_2g != 0) 3148 rtlefuse->board_type |= ODM_BOARD_EXT_PA; 3149 if (rtlhal->external_pa_5g != 0) 3150 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G; 3151 3152 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) 3153 rtlefuse->board_type |= ODM_BOARD_BT; 3154 3155 rtlhal->board_type = rtlefuse->board_type; 3156 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3157 "board_type = 0x%x\n", rtlefuse->board_type); 3158 3159 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; 3160 if (rtlefuse->eeprom_channelplan == 0xff) 3161 rtlefuse->eeprom_channelplan = 0x7F; 3162 3163 /* set channel plan from efuse */ 3164 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 3165 3166 /*parse xtal*/ 3167 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE]; 3168 if (rtlefuse->crystalcap == 0xFF) 3169 rtlefuse->crystalcap = 0x20; 3170 3171 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER]; 3172 if ((rtlefuse->eeprom_thermalmeter == 0xff) || 3173 rtlefuse->autoload_failflag) { 3174 rtlefuse->apk_thermalmeterignore = true; 3175 rtlefuse->eeprom_thermalmeter = 0xff; 3176 } 3177 3178 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 3179 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3180 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 3181 3182 if (!rtlefuse->autoload_failflag) { 3183 rtlefuse->antenna_div_cfg = 3184 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3; 3185 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff) 3186 rtlefuse->antenna_div_cfg = 0; 3187 3188 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 && 3189 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1) 3190 rtlefuse->antenna_div_cfg = 0; 3191 3192 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E]; 3193 if (rtlefuse->antenna_div_type == 0xff) 3194 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV; 3195 } else { 3196 rtlefuse->antenna_div_cfg = 0; 3197 rtlefuse->antenna_div_type = 0; 3198 } 3199 3200 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3201 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n", 3202 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type); 3203 3204 rtlpriv->ledctl.led_opendrain = true; 3205 3206 if (rtlhal->oem_id == RT_CID_DEFAULT) { 3207 switch (rtlefuse->eeprom_oemid) { 3208 case RT_CID_DEFAULT: 3209 break; 3210 case EEPROM_CID_TOSHIBA: 3211 rtlhal->oem_id = RT_CID_TOSHIBA; 3212 break; 3213 case EEPROM_CID_CCX: 3214 rtlhal->oem_id = RT_CID_CCX; 3215 break; 3216 case EEPROM_CID_QMI: 3217 rtlhal->oem_id = RT_CID_819X_QMI; 3218 break; 3219 case EEPROM_CID_WHQL: 3220 break; 3221 default: 3222 break; 3223 } 3224 } 3225 exit: 3226 kfree(hwinfo); 3227 } 3228 3229 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw) 3230 { 3231 struct rtl_priv *rtlpriv = rtl_priv(hw); 3232 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3233 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3234 3235 rtlpriv->ledctl.led_opendrain = true; 3236 switch (rtlhal->oem_id) { 3237 case RT_CID_819X_HP: 3238 rtlpriv->ledctl.led_opendrain = true; 3239 break; 3240 case RT_CID_819X_LENOVO: 3241 case RT_CID_DEFAULT: 3242 case RT_CID_TOSHIBA: 3243 case RT_CID_CCX: 3244 case RT_CID_819X_ACER: 3245 case RT_CID_WHQL: 3246 default: 3247 break; 3248 } 3249 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3250 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 3251 }*/ 3252 3253 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw) 3254 { 3255 struct rtl_priv *rtlpriv = rtl_priv(hw); 3256 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3257 struct rtl_phy *rtlphy = &rtlpriv->phy; 3258 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3259 u8 tmp_u1b; 3260 3261 rtlhal->version = _rtl8821ae_read_chip_version(hw); 3262 if (get_rf_type(rtlphy) == RF_1T1R) 3263 rtlpriv->dm.rfpath_rxenable[0] = true; 3264 else 3265 rtlpriv->dm.rfpath_rxenable[0] = 3266 rtlpriv->dm.rfpath_rxenable[1] = true; 3267 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 3268 rtlhal->version); 3269 3270 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 3271 if (tmp_u1b & BIT(4)) { 3272 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 3273 rtlefuse->epromtype = EEPROM_93C46; 3274 } else { 3275 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 3276 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 3277 } 3278 3279 if (tmp_u1b & BIT(5)) { 3280 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 3281 rtlefuse->autoload_failflag = false; 3282 _rtl8821ae_read_adapter_info(hw, false); 3283 } else { 3284 pr_err("Autoload ERR!!\n"); 3285 } 3286 /*hal_ReadRFType_8812A()*/ 3287 /* _rtl8821ae_hal_customized_behavior(hw); */ 3288 } 3289 3290 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw, 3291 struct ieee80211_sta *sta) 3292 { 3293 struct rtl_priv *rtlpriv = rtl_priv(hw); 3294 struct rtl_phy *rtlphy = &rtlpriv->phy; 3295 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3296 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3297 u32 ratr_value; 3298 u8 ratr_index = 0; 3299 u8 b_nmode = mac->ht_enable; 3300 u8 mimo_ps = IEEE80211_SMPS_OFF; 3301 u16 shortgi_rate; 3302 u32 tmp_ratr_value; 3303 u8 curtxbw_40mhz = mac->bw_40; 3304 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3305 1 : 0; 3306 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3307 1 : 0; 3308 enum wireless_mode wirelessmode = mac->mode; 3309 3310 if (rtlhal->current_bandtype == BAND_ON_5G) 3311 ratr_value = sta->supp_rates[1] << 4; 3312 else 3313 ratr_value = sta->supp_rates[0]; 3314 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3315 ratr_value = 0xfff; 3316 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3317 sta->ht_cap.mcs.rx_mask[0] << 12); 3318 switch (wirelessmode) { 3319 case WIRELESS_MODE_B: 3320 if (ratr_value & 0x0000000c) 3321 ratr_value &= 0x0000000d; 3322 else 3323 ratr_value &= 0x0000000f; 3324 break; 3325 case WIRELESS_MODE_G: 3326 ratr_value &= 0x00000FF5; 3327 break; 3328 case WIRELESS_MODE_N_24G: 3329 case WIRELESS_MODE_N_5G: 3330 b_nmode = 1; 3331 if (mimo_ps == IEEE80211_SMPS_STATIC) { 3332 ratr_value &= 0x0007F005; 3333 } else { 3334 u32 ratr_mask; 3335 3336 if (get_rf_type(rtlphy) == RF_1T2R || 3337 get_rf_type(rtlphy) == RF_1T1R) 3338 ratr_mask = 0x000ff005; 3339 else 3340 ratr_mask = 0x0f0ff005; 3341 3342 ratr_value &= ratr_mask; 3343 } 3344 break; 3345 default: 3346 if (rtlphy->rf_type == RF_1T2R) 3347 ratr_value &= 0x000ff0ff; 3348 else 3349 ratr_value &= 0x0f0ff0ff; 3350 3351 break; 3352 } 3353 3354 if ((rtlpriv->btcoexist.bt_coexistence) && 3355 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 3356 (rtlpriv->btcoexist.bt_cur_state) && 3357 (rtlpriv->btcoexist.bt_ant_isolation) && 3358 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 3359 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 3360 ratr_value &= 0x0fffcfc0; 3361 else 3362 ratr_value &= 0x0FFFFFFF; 3363 3364 if (b_nmode && ((curtxbw_40mhz && 3365 b_curshortgi_40mhz) || (!curtxbw_40mhz && 3366 b_curshortgi_20mhz))) { 3367 ratr_value |= 0x10000000; 3368 tmp_ratr_value = (ratr_value >> 12); 3369 3370 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 3371 if ((1 << shortgi_rate) & tmp_ratr_value) 3372 break; 3373 } 3374 3375 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 3376 (shortgi_rate << 4) | (shortgi_rate); 3377 } 3378 3379 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 3380 3381 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3382 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 3383 } 3384 3385 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate) 3386 { 3387 u8 i, j, tmp_rate; 3388 u32 rate_bitmap = 0; 3389 3390 for (i = j = 0; i < 4; i += 2, j += 10) { 3391 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3; 3392 3393 switch (tmp_rate) { 3394 case 2: 3395 rate_bitmap = rate_bitmap | (0x03ff << j); 3396 break; 3397 case 1: 3398 rate_bitmap = rate_bitmap | (0x01ff << j); 3399 break; 3400 case 0: 3401 rate_bitmap = rate_bitmap | (0x00ff << j); 3402 break; 3403 default: 3404 break; 3405 } 3406 } 3407 3408 return rate_bitmap; 3409 } 3410 3411 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw, 3412 enum wireless_mode wirelessmode, 3413 u32 ratr_bitmap) 3414 { 3415 struct rtl_priv *rtlpriv = rtl_priv(hw); 3416 struct rtl_phy *rtlphy = &rtlpriv->phy; 3417 u32 ret_bitmap = ratr_bitmap; 3418 3419 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 3420 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) 3421 ret_bitmap = ratr_bitmap; 3422 else if (wirelessmode == WIRELESS_MODE_AC_5G 3423 || wirelessmode == WIRELESS_MODE_AC_24G) { 3424 if (rtlphy->rf_type == RF_1T1R) 3425 ret_bitmap = ratr_bitmap & (~BIT21); 3426 else 3427 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21)); 3428 } 3429 3430 return ret_bitmap; 3431 } 3432 3433 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode, 3434 u32 ratr_bitmap) 3435 { 3436 u8 ret = 0; 3437 if (wirelessmode < WIRELESS_MODE_N_24G) 3438 ret = 0; 3439 else if (wirelessmode == WIRELESS_MODE_AC_24G) { 3440 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */ 3441 ret = 3; 3442 else /* Mix, 1SS */ 3443 ret = 2; 3444 } else if (wirelessmode == WIRELESS_MODE_AC_5G) { 3445 ret = 1; 3446 } /* VHT */ 3447 3448 return ret << 4; 3449 } 3450 3451 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw, 3452 u8 mac_id, struct rtl_sta_info *sta_entry, 3453 enum wireless_mode wirelessmode) 3454 { 3455 u8 b_ldpc = 0; 3456 /*not support ldpc, do not open*/ 3457 return b_ldpc << 2; 3458 } 3459 3460 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw, 3461 enum wireless_mode wirelessmode, 3462 u32 ratr_bitmap) 3463 { 3464 struct rtl_priv *rtlpriv = rtl_priv(hw); 3465 struct rtl_phy *rtlphy = &rtlpriv->phy; 3466 u8 rf_type = RF_1T1R; 3467 3468 if (rtlphy->rf_type == RF_1T1R) 3469 rf_type = RF_1T1R; 3470 else if (wirelessmode == WIRELESS_MODE_AC_5G 3471 || wirelessmode == WIRELESS_MODE_AC_24G 3472 || wirelessmode == WIRELESS_MODE_AC_ONLY) { 3473 if (ratr_bitmap & 0xffc00000) 3474 rf_type = RF_2T2R; 3475 } else if (wirelessmode == WIRELESS_MODE_N_5G 3476 || wirelessmode == WIRELESS_MODE_N_24G) { 3477 if (ratr_bitmap & 0xfff00000) 3478 rf_type = RF_2T2R; 3479 } 3480 3481 return rf_type; 3482 } 3483 3484 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 3485 u8 mac_id) 3486 { 3487 bool b_short_gi = false; 3488 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3489 1 : 0; 3490 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3491 1 : 0; 3492 u8 b_curshortgi_80mhz = 0; 3493 b_curshortgi_80mhz = (sta->vht_cap.cap & 3494 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0; 3495 3496 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) 3497 b_short_gi = false; 3498 3499 if (b_curshortgi_40mhz || b_curshortgi_80mhz 3500 || b_curshortgi_20mhz) 3501 b_short_gi = true; 3502 3503 return b_short_gi; 3504 } 3505 3506 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw, 3507 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 3508 { 3509 struct rtl_priv *rtlpriv = rtl_priv(hw); 3510 struct rtl_phy *rtlphy = &rtlpriv->phy; 3511 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3512 struct rtl_sta_info *sta_entry = NULL; 3513 u32 ratr_bitmap; 3514 u8 ratr_index; 3515 enum wireless_mode wirelessmode = 0; 3516 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 3517 ? 1 : 0; 3518 bool b_shortgi = false; 3519 u8 rate_mask[7]; 3520 u8 macid = 0; 3521 u8 mimo_ps = IEEE80211_SMPS_OFF; 3522 u8 rf_type; 3523 3524 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 3525 wirelessmode = sta_entry->wireless_mode; 3526 3527 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3528 "wireless mode = 0x%x\n", wirelessmode); 3529 if (mac->opmode == NL80211_IFTYPE_STATION || 3530 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 3531 curtxbw_40mhz = mac->bw_40; 3532 } else if (mac->opmode == NL80211_IFTYPE_AP || 3533 mac->opmode == NL80211_IFTYPE_ADHOC) 3534 macid = sta->aid + 1; 3535 if (wirelessmode == WIRELESS_MODE_N_5G || 3536 wirelessmode == WIRELESS_MODE_AC_5G || 3537 wirelessmode == WIRELESS_MODE_A) 3538 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4; 3539 else 3540 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ]; 3541 3542 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3543 ratr_bitmap = 0xfff; 3544 3545 if (wirelessmode == WIRELESS_MODE_N_24G 3546 || wirelessmode == WIRELESS_MODE_N_5G) 3547 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3548 sta->ht_cap.mcs.rx_mask[0] << 12); 3549 else if (wirelessmode == WIRELESS_MODE_AC_24G 3550 || wirelessmode == WIRELESS_MODE_AC_5G 3551 || wirelessmode == WIRELESS_MODE_AC_ONLY) 3552 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht( 3553 sta->vht_cap.vht_mcs.rx_mcs_map) << 12; 3554 3555 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid); 3556 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap); 3557 3558 /*mac id owner*/ 3559 switch (wirelessmode) { 3560 case WIRELESS_MODE_B: 3561 ratr_index = RATR_INX_WIRELESS_B; 3562 if (ratr_bitmap & 0x0000000c) 3563 ratr_bitmap &= 0x0000000d; 3564 else 3565 ratr_bitmap &= 0x0000000f; 3566 break; 3567 case WIRELESS_MODE_G: 3568 ratr_index = RATR_INX_WIRELESS_GB; 3569 3570 if (rssi_level == 1) 3571 ratr_bitmap &= 0x00000f00; 3572 else if (rssi_level == 2) 3573 ratr_bitmap &= 0x00000ff0; 3574 else 3575 ratr_bitmap &= 0x00000ff5; 3576 break; 3577 case WIRELESS_MODE_A: 3578 ratr_index = RATR_INX_WIRELESS_G; 3579 ratr_bitmap &= 0x00000ff0; 3580 break; 3581 case WIRELESS_MODE_N_24G: 3582 case WIRELESS_MODE_N_5G: 3583 if (wirelessmode == WIRELESS_MODE_N_24G) 3584 ratr_index = RATR_INX_WIRELESS_NGB; 3585 else 3586 ratr_index = RATR_INX_WIRELESS_NG; 3587 3588 if (mimo_ps == IEEE80211_SMPS_STATIC 3589 || mimo_ps == IEEE80211_SMPS_DYNAMIC) { 3590 if (rssi_level == 1) 3591 ratr_bitmap &= 0x000f0000; 3592 else if (rssi_level == 2) 3593 ratr_bitmap &= 0x000ff000; 3594 else 3595 ratr_bitmap &= 0x000ff005; 3596 } else { 3597 if (rf_type == RF_1T1R) { 3598 if (curtxbw_40mhz) { 3599 if (rssi_level == 1) 3600 ratr_bitmap &= 0x000f0000; 3601 else if (rssi_level == 2) 3602 ratr_bitmap &= 0x000ff000; 3603 else 3604 ratr_bitmap &= 0x000ff015; 3605 } else { 3606 if (rssi_level == 1) 3607 ratr_bitmap &= 0x000f0000; 3608 else if (rssi_level == 2) 3609 ratr_bitmap &= 0x000ff000; 3610 else 3611 ratr_bitmap &= 0x000ff005; 3612 } 3613 } else { 3614 if (curtxbw_40mhz) { 3615 if (rssi_level == 1) 3616 ratr_bitmap &= 0x0fff0000; 3617 else if (rssi_level == 2) 3618 ratr_bitmap &= 0x0ffff000; 3619 else 3620 ratr_bitmap &= 0x0ffff015; 3621 } else { 3622 if (rssi_level == 1) 3623 ratr_bitmap &= 0x0fff0000; 3624 else if (rssi_level == 2) 3625 ratr_bitmap &= 0x0ffff000; 3626 else 3627 ratr_bitmap &= 0x0ffff005; 3628 } 3629 } 3630 } 3631 break; 3632 3633 case WIRELESS_MODE_AC_24G: 3634 ratr_index = RATR_INX_WIRELESS_AC_24N; 3635 if (rssi_level == 1) 3636 ratr_bitmap &= 0xfc3f0000; 3637 else if (rssi_level == 2) 3638 ratr_bitmap &= 0xfffff000; 3639 else 3640 ratr_bitmap &= 0xffffffff; 3641 break; 3642 3643 case WIRELESS_MODE_AC_5G: 3644 ratr_index = RATR_INX_WIRELESS_AC_5N; 3645 3646 if (rf_type == RF_1T1R) { 3647 if (rssi_level == 1) /*add by Gary for ac-series*/ 3648 ratr_bitmap &= 0x003f8000; 3649 else if (rssi_level == 2) 3650 ratr_bitmap &= 0x003ff000; 3651 else 3652 ratr_bitmap &= 0x003ff010; 3653 } else { 3654 if (rssi_level == 1) 3655 ratr_bitmap &= 0xfe3f8000; 3656 else if (rssi_level == 2) 3657 ratr_bitmap &= 0xfffff000; 3658 else 3659 ratr_bitmap &= 0xfffff010; 3660 } 3661 break; 3662 3663 default: 3664 ratr_index = RATR_INX_WIRELESS_NGB; 3665 3666 if (rf_type == RF_1T2R) 3667 ratr_bitmap &= 0x000ff0ff; 3668 else 3669 ratr_bitmap &= 0x0f8ff0ff; 3670 break; 3671 } 3672 3673 ratr_index = rtl_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode); 3674 sta_entry->ratr_index = ratr_index; 3675 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode, 3676 ratr_bitmap); 3677 3678 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3679 "ratr_bitmap :%x\n", ratr_bitmap); 3680 3681 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) | 3682 (ratr_index << 28)); */ 3683 3684 rate_mask[0] = macid; 3685 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); 3686 rate_mask[2] = rtlphy->current_chan_bw | ((!update_bw) << 3) 3687 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap) 3688 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode); 3689 3690 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 3691 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 3692 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 3693 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 3694 3695 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3696 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 3697 ratr_index, ratr_bitmap, 3698 rate_mask[0], rate_mask[1], 3699 rate_mask[2], rate_mask[3], 3700 rate_mask[4], rate_mask[5], 3701 rate_mask[6]); 3702 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask); 3703 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 3704 } 3705 3706 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw, 3707 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 3708 { 3709 struct rtl_priv *rtlpriv = rtl_priv(hw); 3710 if (rtlpriv->dm.useramask) 3711 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 3712 else 3713 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD, 3714 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/ 3715 rtl8821ae_update_hal_rate_table(hw, sta); 3716 } 3717 3718 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw) 3719 { 3720 struct rtl_priv *rtlpriv = rtl_priv(hw); 3721 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3722 u16 wireless_mode = mac->mode; 3723 u8 sifs_timer, r2t_sifs; 3724 3725 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 3726 (u8 *)&mac->slot_time); 3727 if (wireless_mode == WIRELESS_MODE_G) 3728 sifs_timer = 0x0a; 3729 else 3730 sifs_timer = 0x0e; 3731 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 3732 3733 r2t_sifs = 0xa; 3734 3735 if (wireless_mode == WIRELESS_MODE_AC_5G && 3736 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) && 3737 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) { 3738 if (mac->vendor == PEER_ATH) 3739 r2t_sifs = 0x8; 3740 else 3741 r2t_sifs = 0xa; 3742 } else if (wireless_mode == WIRELESS_MODE_AC_5G) { 3743 r2t_sifs = 0xa; 3744 } 3745 3746 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs); 3747 } 3748 3749 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 3750 { 3751 struct rtl_priv *rtlpriv = rtl_priv(hw); 3752 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3753 struct rtl_phy *rtlphy = &rtlpriv->phy; 3754 enum rf_pwrstate e_rfpowerstate_toset; 3755 u8 u1tmp = 0; 3756 bool b_actuallyset = false; 3757 3758 if (rtlpriv->rtlhal.being_init_adapter) 3759 return false; 3760 3761 if (ppsc->swrf_processing) 3762 return false; 3763 3764 spin_lock(&rtlpriv->locks.rf_ps_lock); 3765 if (ppsc->rfchange_inprogress) { 3766 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3767 return false; 3768 } else { 3769 ppsc->rfchange_inprogress = true; 3770 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3771 } 3772 3773 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 3774 rtl_read_byte(rtlpriv, 3775 REG_GPIO_IO_SEL_2) & ~(BIT(1))); 3776 3777 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 3778 3779 if (rtlphy->polarity_ctl) 3780 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 3781 else 3782 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 3783 3784 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 3785 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3786 "GPIOChangeRF - HW Radio ON, RF ON\n"); 3787 3788 e_rfpowerstate_toset = ERFON; 3789 ppsc->hwradiooff = false; 3790 b_actuallyset = true; 3791 } else if ((!ppsc->hwradiooff) 3792 && (e_rfpowerstate_toset == ERFOFF)) { 3793 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3794 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 3795 3796 e_rfpowerstate_toset = ERFOFF; 3797 ppsc->hwradiooff = true; 3798 b_actuallyset = true; 3799 } 3800 3801 if (b_actuallyset) { 3802 spin_lock(&rtlpriv->locks.rf_ps_lock); 3803 ppsc->rfchange_inprogress = false; 3804 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3805 } else { 3806 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 3807 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3808 3809 spin_lock(&rtlpriv->locks.rf_ps_lock); 3810 ppsc->rfchange_inprogress = false; 3811 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3812 } 3813 3814 *valid = 1; 3815 return !ppsc->hwradiooff; 3816 } 3817 3818 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index, 3819 u8 *p_macaddr, bool is_group, u8 enc_algo, 3820 bool is_wepkey, bool clear_all) 3821 { 3822 struct rtl_priv *rtlpriv = rtl_priv(hw); 3823 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3824 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3825 u8 *macaddr = p_macaddr; 3826 u32 entry_id = 0; 3827 bool is_pairwise = false; 3828 3829 static u8 cam_const_addr[4][6] = { 3830 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 3831 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 3832 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 3833 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 3834 }; 3835 static u8 cam_const_broad[] = { 3836 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 3837 }; 3838 3839 if (clear_all) { 3840 u8 idx = 0; 3841 u8 cam_offset = 0; 3842 u8 clear_number = 5; 3843 3844 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 3845 3846 for (idx = 0; idx < clear_number; idx++) { 3847 rtl_cam_mark_invalid(hw, cam_offset + idx); 3848 rtl_cam_empty_entry(hw, cam_offset + idx); 3849 3850 if (idx < 5) { 3851 memset(rtlpriv->sec.key_buf[idx], 0, 3852 MAX_KEY_LEN); 3853 rtlpriv->sec.key_len[idx] = 0; 3854 } 3855 } 3856 } else { 3857 switch (enc_algo) { 3858 case WEP40_ENCRYPTION: 3859 enc_algo = CAM_WEP40; 3860 break; 3861 case WEP104_ENCRYPTION: 3862 enc_algo = CAM_WEP104; 3863 break; 3864 case TKIP_ENCRYPTION: 3865 enc_algo = CAM_TKIP; 3866 break; 3867 case AESCCMP_ENCRYPTION: 3868 enc_algo = CAM_AES; 3869 break; 3870 default: 3871 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 3872 "switch case %#x not processed\n", enc_algo); 3873 enc_algo = CAM_TKIP; 3874 break; 3875 } 3876 3877 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 3878 macaddr = cam_const_addr[key_index]; 3879 entry_id = key_index; 3880 } else { 3881 if (is_group) { 3882 macaddr = cam_const_broad; 3883 entry_id = key_index; 3884 } else { 3885 if (mac->opmode == NL80211_IFTYPE_AP) { 3886 entry_id = rtl_cam_get_free_entry(hw, p_macaddr); 3887 if (entry_id >= TOTAL_CAM_ENTRY) { 3888 pr_err("an not find free hwsecurity cam entry\n"); 3889 return; 3890 } 3891 } else { 3892 entry_id = CAM_PAIRWISE_KEY_POSITION; 3893 } 3894 3895 key_index = PAIRWISE_KEYIDX; 3896 is_pairwise = true; 3897 } 3898 } 3899 3900 if (rtlpriv->sec.key_len[key_index] == 0) { 3901 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3902 "delete one entry, entry_id is %d\n", 3903 entry_id); 3904 if (mac->opmode == NL80211_IFTYPE_AP) 3905 rtl_cam_del_entry(hw, p_macaddr); 3906 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 3907 } else { 3908 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3909 "add one entry\n"); 3910 if (is_pairwise) { 3911 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3912 "set Pairwise key\n"); 3913 3914 rtl_cam_add_one_entry(hw, macaddr, key_index, 3915 entry_id, enc_algo, 3916 CAM_CONFIG_NO_USEDK, 3917 rtlpriv->sec.key_buf[key_index]); 3918 } else { 3919 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3920 "set group key\n"); 3921 3922 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 3923 rtl_cam_add_one_entry(hw, 3924 rtlefuse->dev_addr, 3925 PAIRWISE_KEYIDX, 3926 CAM_PAIRWISE_KEY_POSITION, 3927 enc_algo, 3928 CAM_CONFIG_NO_USEDK, 3929 rtlpriv->sec.key_buf 3930 [entry_id]); 3931 } 3932 3933 rtl_cam_add_one_entry(hw, macaddr, key_index, 3934 entry_id, enc_algo, 3935 CAM_CONFIG_NO_USEDK, 3936 rtlpriv->sec.key_buf[entry_id]); 3937 } 3938 } 3939 } 3940 } 3941 3942 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw) 3943 { 3944 struct rtl_priv *rtlpriv = rtl_priv(hw); 3945 3946 /* 0:Low, 1:High, 2:From Efuse. */ 3947 rtlpriv->btcoexist.reg_bt_iso = 2; 3948 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 3949 rtlpriv->btcoexist.reg_bt_sco = 3; 3950 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 3951 rtlpriv->btcoexist.reg_bt_sco = 0; 3952 } 3953 3954 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw) 3955 { 3956 struct rtl_priv *rtlpriv = rtl_priv(hw); 3957 3958 if (rtlpriv->cfg->ops->get_btc_status()) 3959 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 3960 } 3961 3962 void rtl8821ae_suspend(struct ieee80211_hw *hw) 3963 { 3964 } 3965 3966 void rtl8821ae_resume(struct ieee80211_hw *hw) 3967 { 3968 } 3969 3970 /* Turn on AAP (RCR:bit 0) for promicuous mode. */ 3971 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw, 3972 bool allow_all_da, bool write_into_reg) 3973 { 3974 struct rtl_priv *rtlpriv = rtl_priv(hw); 3975 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 3976 3977 if (allow_all_da) /* Set BIT0 */ 3978 rtlpci->receive_config |= RCR_AAP; 3979 else /* Clear BIT0 */ 3980 rtlpci->receive_config &= ~RCR_AAP; 3981 3982 if (write_into_reg) 3983 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 3984 3985 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, 3986 "receive_config=0x%08X, write_into_reg=%d\n", 3987 rtlpci->receive_config, write_into_reg); 3988 } 3989 3990 /* WKFMCAMAddAllEntry8812 */ 3991 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw, 3992 struct rtl_wow_pattern *rtl_pattern, 3993 u8 index) 3994 { 3995 struct rtl_priv *rtlpriv = rtl_priv(hw); 3996 u32 cam = 0; 3997 u8 addr = 0; 3998 u16 rxbuf_addr; 3999 u8 tmp, count = 0; 4000 u16 cam_start; 4001 u16 offset; 4002 4003 /* Count the WFCAM entry start offset. */ 4004 4005 /* RX page size = 128 byte */ 4006 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128; 4007 /* We should start from the boundry */ 4008 cam_start = offset * 128; 4009 4010 /* Enable Rx packet buffer access. */ 4011 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); 4012 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) { 4013 /* Set Rx packet buffer offset. 4014 * RXBufer pointer increases 1, 4015 * we can access 8 bytes in Rx packet buffer. 4016 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE 4017 * RXBufer addr = (CAM start offset + 4018 * per entry offset of a WKFM CAM)/8 4019 * * index: The index of the wake up frame mask 4020 * * WKFMCAM_SIZE: the total size of one WKFM CAM 4021 * * per entry offset of a WKFM CAM: Addr*4 bytes 4022 */ 4023 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3; 4024 /* Set R/W start offset */ 4025 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr); 4026 4027 if (addr == 0) { 4028 cam = BIT(31) | rtl_pattern->crc; 4029 4030 if (rtl_pattern->type == UNICAST_PATTERN) 4031 cam |= BIT(24); 4032 else if (rtl_pattern->type == MULTICAST_PATTERN) 4033 cam |= BIT(25); 4034 else if (rtl_pattern->type == BROADCAST_PATTERN) 4035 cam |= BIT(26); 4036 4037 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4038 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4039 "WRITE entry[%d] 0x%x: %x\n", addr, 4040 REG_PKTBUF_DBG_DATA_L, cam); 4041 4042 /* Write to Rx packet buffer. */ 4043 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4044 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */ 4045 cam = rtl_pattern->mask[addr - 2]; 4046 4047 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4048 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4049 "WRITE entry[%d] 0x%x: %x\n", addr, 4050 REG_PKTBUF_DBG_DATA_L, cam); 4051 4052 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4053 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */ 4054 cam = rtl_pattern->mask[addr - 2]; 4055 4056 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam); 4057 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4058 "WRITE entry[%d] 0x%x: %x\n", addr, 4059 REG_PKTBUF_DBG_DATA_H, cam); 4060 4061 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001); 4062 } 4063 4064 count = 0; 4065 do { 4066 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL); 4067 udelay(2); 4068 count++; 4069 } while (tmp && count < 100); 4070 4071 WARN_ONCE((count >= 100), 4072 "rtl8821ae: Write wake up frame mask FAIL %d value!\n", 4073 tmp); 4074 } 4075 /* Disable Rx packet buffer access. */ 4076 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, 4077 DISABLE_TRXPKT_BUF_ACCESS); 4078 } 4079