1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "phy_common.h" 6 #include "../rtl8723ae/reg.h" 7 #include <linux/module.h> 8 9 /* These routines are common to RTL8723AE and RTL8723bE */ 10 11 u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw, 12 u32 regaddr, u32 bitmask) 13 { 14 struct rtl_priv *rtlpriv = rtl_priv(hw); 15 u32 returnvalue, originalvalue, bitshift; 16 17 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 18 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); 19 originalvalue = rtl_read_dword(rtlpriv, regaddr); 20 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 21 returnvalue = (originalvalue & bitmask) >> bitshift; 22 23 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 24 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, 25 regaddr, originalvalue); 26 return returnvalue; 27 } 28 EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg); 29 30 void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, 31 u32 bitmask, u32 data) 32 { 33 struct rtl_priv *rtlpriv = rtl_priv(hw); 34 u32 originalvalue, bitshift; 35 36 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 37 "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask, 38 data); 39 40 if (bitmask != MASKDWORD) { 41 originalvalue = rtl_read_dword(rtlpriv, regaddr); 42 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 43 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 44 } 45 46 rtl_write_dword(rtlpriv, regaddr, data); 47 48 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 49 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 50 regaddr, bitmask, data); 51 } 52 EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg); 53 54 u32 rtl8723_phy_calculate_bit_shift(u32 bitmask) 55 { 56 u32 i; 57 58 for (i = 0; i <= 31; i++) { 59 if (((bitmask >> i) & 0x1) == 1) 60 break; 61 } 62 return i; 63 } 64 EXPORT_SYMBOL_GPL(rtl8723_phy_calculate_bit_shift); 65 66 u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw, 67 enum radio_path rfpath, u32 offset) 68 { 69 struct rtl_priv *rtlpriv = rtl_priv(hw); 70 struct rtl_phy *rtlphy = &(rtlpriv->phy); 71 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 72 u32 newoffset; 73 u32 tmplong, tmplong2; 74 u8 rfpi_enable = 0; 75 u32 retvalue; 76 77 offset &= 0xff; 78 newoffset = offset; 79 if (RT_CANNOT_IO(hw)) { 80 pr_err("return all one\n"); 81 return 0xFFFFFFFF; 82 } 83 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 84 if (rfpath == RF90_PATH_A) 85 tmplong2 = tmplong; 86 else 87 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 88 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 89 (newoffset << 23) | BLSSIREADEDGE; 90 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 91 tmplong & (~BLSSIREADEDGE)); 92 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 93 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 94 tmplong | BLSSIREADEDGE); 95 udelay(120); 96 if (rfpath == RF90_PATH_A) 97 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 98 BIT(8)); 99 else if (rfpath == RF90_PATH_B) 100 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 101 BIT(8)); 102 if (rfpi_enable) 103 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 104 BLSSIREADBACKDATA); 105 else 106 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 107 BLSSIREADBACKDATA); 108 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 109 "RFR-%d Addr[0x%x]=0x%x\n", 110 rfpath, pphyreg->rf_rb, retvalue); 111 return retvalue; 112 } 113 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read); 114 115 void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw, 116 enum radio_path rfpath, 117 u32 offset, u32 data) 118 { 119 u32 data_and_addr; 120 u32 newoffset; 121 struct rtl_priv *rtlpriv = rtl_priv(hw); 122 struct rtl_phy *rtlphy = &(rtlpriv->phy); 123 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 124 125 if (RT_CANNOT_IO(hw)) { 126 pr_err("stop\n"); 127 return; 128 } 129 offset &= 0xff; 130 newoffset = offset; 131 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 132 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 133 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 134 "RFW-%d Addr[0x%x]=0x%x\n", 135 rfpath, pphyreg->rf3wire_offset, 136 data_and_addr); 137 } 138 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write); 139 140 long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 141 enum wireless_mode wirelessmode, 142 u8 txpwridx) 143 { 144 long offset; 145 long pwrout_dbm; 146 147 switch (wirelessmode) { 148 case WIRELESS_MODE_B: 149 offset = -7; 150 break; 151 case WIRELESS_MODE_G: 152 case WIRELESS_MODE_N_24G: 153 offset = -8; 154 break; 155 default: 156 offset = -8; 157 break; 158 } 159 pwrout_dbm = txpwridx / 2 + offset; 160 return pwrout_dbm; 161 } 162 EXPORT_SYMBOL_GPL(rtl8723_phy_txpwr_idx_to_dbm); 163 164 void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw) 165 { 166 struct rtl_priv *rtlpriv = rtl_priv(hw); 167 struct rtl_phy *rtlphy = &(rtlpriv->phy); 168 169 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 170 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 171 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 172 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 173 174 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 175 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 176 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 177 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 178 179 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 180 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 181 182 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 183 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 184 185 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 186 RFPGA0_XA_LSSIPARAMETER; 187 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 188 RFPGA0_XB_LSSIPARAMETER; 189 190 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 191 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 192 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 193 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 194 195 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 196 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 197 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 198 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 199 200 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 201 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 202 203 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 204 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 205 206 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 207 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 208 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 209 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 210 211 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 212 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 213 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 214 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 215 216 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 217 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 218 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 219 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 220 221 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 222 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 223 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE; 224 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 225 226 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 227 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 228 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 229 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 230 231 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; 232 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; 233 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; 234 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; 235 236 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; 237 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; 238 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; 239 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; 240 241 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 242 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 243 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 244 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 245 246 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; 247 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; 248 249 } 250 EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def); 251 252 bool rtl8723_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 253 u32 cmdtableidx, 254 u32 cmdtablesz, 255 enum swchnlcmd_id cmdid, 256 u32 para1, u32 para2, 257 u32 msdelay) 258 { 259 struct swchnlcmd *pcmd; 260 261 if (cmdtable == NULL) { 262 WARN_ONCE(true, "rtl8723-common: cmdtable cannot be NULL.\n"); 263 return false; 264 } 265 266 if (cmdtableidx >= cmdtablesz) 267 return false; 268 269 pcmd = cmdtable + cmdtableidx; 270 pcmd->cmdid = cmdid; 271 pcmd->para1 = para1; 272 pcmd->para2 = para2; 273 pcmd->msdelay = msdelay; 274 return true; 275 } 276 EXPORT_SYMBOL_GPL(rtl8723_phy_set_sw_chnl_cmdarray); 277 278 void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, 279 bool iqk_ok, 280 long result[][8], 281 u8 final_candidate, 282 bool btxonly) 283 { 284 u32 oldval_0, x, tx0_a, reg; 285 long y, tx0_c; 286 287 if (final_candidate == 0xFF) { 288 return; 289 } else if (iqk_ok) { 290 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 291 MASKDWORD) >> 22) & 0x3FF; 292 x = result[final_candidate][0]; 293 if ((x & 0x00000200) != 0) 294 x = x | 0xFFFFFC00; 295 tx0_a = (x * oldval_0) >> 8; 296 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); 297 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), 298 ((x * oldval_0 >> 7) & 0x1)); 299 y = result[final_candidate][1]; 300 if ((y & 0x00000200) != 0) 301 y = y | 0xFFFFFC00; 302 tx0_c = (y * oldval_0) >> 8; 303 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 304 ((tx0_c & 0x3C0) >> 6)); 305 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, 306 (tx0_c & 0x3F)); 307 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), 308 ((y * oldval_0 >> 7) & 0x1)); 309 if (btxonly) 310 return; 311 reg = result[final_candidate][2]; 312 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 313 reg = result[final_candidate][3] & 0x3F; 314 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 315 reg = (result[final_candidate][3] >> 6) & 0xF; 316 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 317 } 318 } 319 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_fill_iqk_matrix); 320 321 void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg, 322 u32 *addabackup, u32 registernum) 323 { 324 u32 i; 325 326 for (i = 0; i < registernum; i++) 327 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); 328 } 329 EXPORT_SYMBOL_GPL(rtl8723_save_adda_registers); 330 331 void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw, 332 u32 *macreg, u32 *macbackup) 333 { 334 struct rtl_priv *rtlpriv = rtl_priv(hw); 335 u32 i; 336 337 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 338 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 339 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 340 } 341 EXPORT_SYMBOL_GPL(rtl8723_phy_save_mac_registers); 342 343 void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw, 344 u32 *addareg, u32 *addabackup, 345 u32 regiesternum) 346 { 347 u32 i; 348 349 for (i = 0; i < regiesternum; i++) 350 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); 351 } 352 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_adda_registers); 353 354 void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw, 355 u32 *macreg, u32 *macbackup) 356 { 357 struct rtl_priv *rtlpriv = rtl_priv(hw); 358 u32 i; 359 360 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 361 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 362 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); 363 } 364 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_mac_registers); 365 366 void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg, 367 bool is_patha_on, bool is2t) 368 { 369 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 370 u32 pathon; 371 u32 i; 372 373 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 374 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; 375 if (!is2t) { 376 pathon = 0x0bdb25a0; 377 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); 378 } else { 379 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); 380 } 381 } else { 382 /* rtl8723be */ 383 pathon = 0x01c00014; 384 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); 385 } 386 387 for (i = 1; i < IQK_ADDA_REG_NUM; i++) 388 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); 389 } 390 EXPORT_SYMBOL_GPL(rtl8723_phy_path_adda_on); 391 392 void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw, 393 u32 *macreg, u32 *macbackup) 394 { 395 struct rtl_priv *rtlpriv = rtl_priv(hw); 396 u32 i = 0; 397 398 rtl_write_byte(rtlpriv, macreg[i], 0x3F); 399 400 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 401 rtl_write_byte(rtlpriv, macreg[i], 402 (u8) (macbackup[i] & (~BIT(3)))); 403 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 404 } 405 EXPORT_SYMBOL_GPL(rtl8723_phy_mac_setting_calibration); 406 407 void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw) 408 { 409 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 410 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 411 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 412 } 413 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_standby); 414 415 void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) 416 { 417 u32 mode; 418 419 mode = pi_mode ? 0x01000100 : 0x01000000; 420 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 421 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 422 } 423 EXPORT_SYMBOL_GPL(rtl8723_phy_pi_mode_switch); 424