xref: /linux/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c (revision 2b0cfa6e49566c8fa6759734cf821aa6e8271a9e)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "phy_common.h"
6 #include "../rtl8723ae/reg.h"
7 #include <linux/module.h>
8 
9 /* These routines are common to RTL8723AE and RTL8723bE */
10 
11 u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw,
12 			     u32 regaddr, u32 bitmask)
13 {
14 	struct rtl_priv *rtlpriv = rtl_priv(hw);
15 	u32 returnvalue, originalvalue, bitshift;
16 
17 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
18 		"regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
19 	originalvalue = rtl_read_dword(rtlpriv, regaddr);
20 	bitshift = calculate_bit_shift(bitmask);
21 	returnvalue = (originalvalue & bitmask) >> bitshift;
22 
23 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
24 		"BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
25 		regaddr, originalvalue);
26 	return returnvalue;
27 }
28 EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg);
29 
30 void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
31 			      u32 bitmask, u32 data)
32 {
33 	struct rtl_priv *rtlpriv = rtl_priv(hw);
34 	u32 originalvalue, bitshift;
35 
36 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
37 		"regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
38 		data);
39 
40 	if (bitmask != MASKDWORD) {
41 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
42 		bitshift = calculate_bit_shift(bitmask);
43 		data = ((originalvalue & (~bitmask)) | (data << bitshift));
44 	}
45 
46 	rtl_write_dword(rtlpriv, regaddr, data);
47 
48 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
49 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
50 		regaddr, bitmask, data);
51 }
52 EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg);
53 
54 u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
55 			       enum radio_path rfpath, u32 offset)
56 {
57 	struct rtl_priv *rtlpriv = rtl_priv(hw);
58 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
59 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
60 	u32 newoffset;
61 	u32 tmplong, tmplong2;
62 	u8 rfpi_enable = 0;
63 	u32 retvalue;
64 
65 	offset &= 0xff;
66 	newoffset = offset;
67 	if (RT_CANNOT_IO(hw)) {
68 		pr_err("return all one\n");
69 		return 0xFFFFFFFF;
70 	}
71 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
72 	if (rfpath == RF90_PATH_A)
73 		tmplong2 = tmplong;
74 	else
75 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
76 	tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
77 	    (newoffset << 23) | BLSSIREADEDGE;
78 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
79 		      tmplong & (~BLSSIREADEDGE));
80 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
81 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
82 		      tmplong | BLSSIREADEDGE);
83 	udelay(120);
84 	if (rfpath == RF90_PATH_A)
85 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
86 						 BIT(8));
87 	else if (rfpath == RF90_PATH_B)
88 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
89 						 BIT(8));
90 	if (rfpi_enable)
91 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
92 					 BLSSIREADBACKDATA);
93 	else
94 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
95 					 BLSSIREADBACKDATA);
96 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
97 		"RFR-%d Addr[0x%x]=0x%x\n",
98 		rfpath, pphyreg->rf_rb, retvalue);
99 	return retvalue;
100 }
101 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read);
102 
103 void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
104 				 enum radio_path rfpath,
105 				 u32 offset, u32 data)
106 {
107 	u32 data_and_addr;
108 	u32 newoffset;
109 	struct rtl_priv *rtlpriv = rtl_priv(hw);
110 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
111 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
112 
113 	if (RT_CANNOT_IO(hw)) {
114 		pr_err("stop\n");
115 		return;
116 	}
117 	offset &= 0xff;
118 	newoffset = offset;
119 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
120 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
121 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
122 		"RFW-%d Addr[0x%x]=0x%x\n",
123 		rfpath, pphyreg->rf3wire_offset,
124 		data_and_addr);
125 }
126 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write);
127 
128 long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
129 				  enum wireless_mode wirelessmode,
130 				  u8 txpwridx)
131 {
132 	long offset;
133 	long pwrout_dbm;
134 
135 	switch (wirelessmode) {
136 	case WIRELESS_MODE_B:
137 		offset = -7;
138 		break;
139 	case WIRELESS_MODE_G:
140 	case WIRELESS_MODE_N_24G:
141 		offset = -8;
142 		break;
143 	default:
144 		offset = -8;
145 		break;
146 	}
147 	pwrout_dbm = txpwridx / 2 + offset;
148 	return pwrout_dbm;
149 }
150 EXPORT_SYMBOL_GPL(rtl8723_phy_txpwr_idx_to_dbm);
151 
152 void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
153 {
154 	struct rtl_priv *rtlpriv = rtl_priv(hw);
155 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
156 
157 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
158 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
159 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
160 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
161 
162 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
163 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
164 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
165 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
166 
167 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
168 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
169 
170 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
171 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
172 
173 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
174 	    RFPGA0_XA_LSSIPARAMETER;
175 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
176 	    RFPGA0_XB_LSSIPARAMETER;
177 
178 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
179 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
180 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
181 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
182 
183 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
184 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
185 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
186 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
187 
188 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
189 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
190 
191 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
192 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
193 
194 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
195 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
196 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
197 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
198 
199 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
200 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
201 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
202 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
203 
204 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
205 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
206 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
207 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
208 
209 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
210 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
211 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
212 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
213 
214 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
215 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
216 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
217 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
218 
219 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
220 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
221 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
222 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
223 
224 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
225 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
226 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
227 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
228 
229 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
230 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
231 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
232 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
233 
234 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
235 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
236 
237 }
238 EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def);
239 
240 bool rtl8723_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
241 				      u32 cmdtableidx,
242 				      u32 cmdtablesz,
243 				      enum swchnlcmd_id cmdid,
244 				      u32 para1, u32 para2,
245 				      u32 msdelay)
246 {
247 	struct swchnlcmd *pcmd;
248 
249 	if (cmdtable == NULL) {
250 		WARN_ONCE(true, "rtl8723-common: cmdtable cannot be NULL.\n");
251 		return false;
252 	}
253 
254 	if (cmdtableidx >= cmdtablesz)
255 		return false;
256 
257 	pcmd = cmdtable + cmdtableidx;
258 	pcmd->cmdid = cmdid;
259 	pcmd->para1 = para1;
260 	pcmd->para2 = para2;
261 	pcmd->msdelay = msdelay;
262 	return true;
263 }
264 EXPORT_SYMBOL_GPL(rtl8723_phy_set_sw_chnl_cmdarray);
265 
266 void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
267 					bool iqk_ok,
268 					long result[][8],
269 					u8 final_candidate,
270 					bool btxonly)
271 {
272 	u32 oldval_0, x, tx0_a, reg;
273 	long y, tx0_c;
274 
275 	if (final_candidate == 0xFF) {
276 		return;
277 	} else if (iqk_ok) {
278 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
279 					  MASKDWORD) >> 22) & 0x3FF;
280 		x = result[final_candidate][0];
281 		if ((x & 0x00000200) != 0)
282 			x = x | 0xFFFFFC00;
283 		tx0_a = (x * oldval_0) >> 8;
284 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
285 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
286 			      ((x * oldval_0 >> 7) & 0x1));
287 		y = result[final_candidate][1];
288 		if ((y & 0x00000200) != 0)
289 			y = y | 0xFFFFFC00;
290 		tx0_c = (y * oldval_0) >> 8;
291 		rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
292 			      ((tx0_c & 0x3C0) >> 6));
293 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
294 			      (tx0_c & 0x3F));
295 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
296 			      ((y * oldval_0 >> 7) & 0x1));
297 		if (btxonly)
298 			return;
299 		reg = result[final_candidate][2];
300 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
301 		reg = result[final_candidate][3] & 0x3F;
302 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
303 		reg = (result[final_candidate][3] >> 6) & 0xF;
304 		rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
305 	}
306 }
307 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_fill_iqk_matrix);
308 
309 void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg,
310 				 u32 *addabackup, u32 registernum)
311 {
312 	u32 i;
313 
314 	for (i = 0; i < registernum; i++)
315 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
316 }
317 EXPORT_SYMBOL_GPL(rtl8723_save_adda_registers);
318 
319 void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw,
320 				    u32 *macreg, u32 *macbackup)
321 {
322 	struct rtl_priv *rtlpriv = rtl_priv(hw);
323 	u32 i;
324 
325 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
326 		macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
327 	macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
328 }
329 EXPORT_SYMBOL_GPL(rtl8723_phy_save_mac_registers);
330 
331 void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw,
332 				       u32 *addareg, u32 *addabackup,
333 				       u32 regiesternum)
334 {
335 	u32 i;
336 
337 	for (i = 0; i < regiesternum; i++)
338 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
339 }
340 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_adda_registers);
341 
342 void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw,
343 				      u32 *macreg, u32 *macbackup)
344 {
345 	struct rtl_priv *rtlpriv = rtl_priv(hw);
346 	u32 i;
347 
348 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
349 		rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
350 	rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
351 }
352 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_mac_registers);
353 
354 void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
355 			      bool is_patha_on, bool is2t)
356 {
357 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
358 	u32 pathon;
359 	u32 i;
360 
361 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
362 		pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
363 		if (!is2t) {
364 			pathon = 0x0bdb25a0;
365 			rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
366 		} else {
367 			rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
368 		}
369 	} else {
370 		/* rtl8723be */
371 		pathon = 0x01c00014;
372 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
373 	}
374 
375 	for (i = 1; i < IQK_ADDA_REG_NUM; i++)
376 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
377 }
378 EXPORT_SYMBOL_GPL(rtl8723_phy_path_adda_on);
379 
380 void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw,
381 					 u32 *macreg, u32 *macbackup)
382 {
383 	struct rtl_priv *rtlpriv = rtl_priv(hw);
384 	u32 i = 0;
385 
386 	rtl_write_byte(rtlpriv, macreg[i], 0x3F);
387 
388 	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
389 		rtl_write_byte(rtlpriv, macreg[i],
390 			       (u8) (macbackup[i] & (~BIT(3))));
391 	rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
392 }
393 EXPORT_SYMBOL_GPL(rtl8723_phy_mac_setting_calibration);
394 
395 void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw)
396 {
397 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
398 	rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
399 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
400 }
401 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_standby);
402 
403 void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
404 {
405 	u32 mode;
406 
407 	mode = pi_mode ? 0x01000100 : 0x01000000;
408 	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
409 	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
410 }
411 EXPORT_SYMBOL_GPL(rtl8723_phy_pi_mode_switch);
412