1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../efuse.h" 6 #include "../base.h" 7 #include "../regd.h" 8 #include "../cam.h" 9 #include "../ps.h" 10 #include "../pci.h" 11 #include "reg.h" 12 #include "def.h" 13 #include "phy.h" 14 #include "../rtl8723com/phy_common.h" 15 #include "dm.h" 16 #include "../rtl8723com/dm_common.h" 17 #include "fw.h" 18 #include "../rtl8723com/fw_common.h" 19 #include "led.h" 20 #include "hw.h" 21 #include "../pwrseqcmd.h" 22 #include "pwrseq.h" 23 #include "../btcoexist/rtl_btc.h" 24 #include <linux/kernel.h> 25 26 #define LLT_CONFIG 5 27 28 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw) 29 { 30 struct rtl_priv *rtlpriv = rtl_priv(hw); 31 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 32 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 33 unsigned long flags; 34 35 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 36 while (skb_queue_len(&ring->queue)) { 37 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 38 struct sk_buff *skb = __skb_dequeue(&ring->queue); 39 40 dma_unmap_single(&rtlpci->pdev->dev, 41 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 42 true, HW_DESC_TXBUFF_ADDR), 43 skb->len, DMA_TO_DEVICE); 44 kfree_skb(skb); 45 ring->idx = (ring->idx + 1) % ring->entries; 46 } 47 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 48 } 49 50 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 51 u8 set_bits, u8 clear_bits) 52 { 53 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 54 struct rtl_priv *rtlpriv = rtl_priv(hw); 55 56 rtlpci->reg_bcn_ctrl_val |= set_bits; 57 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 58 59 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 60 } 61 62 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw) 63 { 64 struct rtl_priv *rtlpriv = rtl_priv(hw); 65 u8 tmp1byte; 66 67 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 68 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 70 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 71 tmp1byte &= ~(BIT(0)); 72 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 73 } 74 75 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw) 76 { 77 struct rtl_priv *rtlpriv = rtl_priv(hw); 78 u8 tmp1byte; 79 80 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 81 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 83 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 84 tmp1byte |= BIT(1); 85 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 86 } 87 88 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw) 89 { 90 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1)); 91 } 92 93 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw) 94 { 95 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0); 96 } 97 98 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val, 99 bool b_need_turn_off_ckk) 100 { 101 struct rtl_priv *rtlpriv = rtl_priv(hw); 102 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 103 bool b_support_remote_wake_up; 104 u32 count = 0, isr_regaddr, content; 105 bool b_schedule_timer = b_need_turn_off_ckk; 106 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 107 (u8 *)(&b_support_remote_wake_up)); 108 109 if (!rtlhal->fw_ready) 110 return; 111 if (!rtlpriv->psc.fw_current_inpsmode) 112 return; 113 114 while (1) { 115 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 116 if (rtlhal->fw_clk_change_in_progress) { 117 while (rtlhal->fw_clk_change_in_progress) { 118 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 119 count++; 120 udelay(100); 121 if (count > 1000) 122 return; 123 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 124 } 125 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 126 } else { 127 rtlhal->fw_clk_change_in_progress = false; 128 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 129 break; 130 } 131 } 132 133 if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) { 134 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 135 (u8 *)(&rpwm_val)); 136 if (FW_PS_IS_ACK(rpwm_val)) { 137 isr_regaddr = REG_HISR; 138 content = rtl_read_dword(rtlpriv, isr_regaddr); 139 while (!(content & IMR_CPWM) && (count < 500)) { 140 udelay(50); 141 count++; 142 content = rtl_read_dword(rtlpriv, isr_regaddr); 143 } 144 145 if (content & IMR_CPWM) { 146 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 147 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON; 148 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 149 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n", 150 rtlhal->fw_ps_state); 151 } 152 } 153 154 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 155 rtlhal->fw_clk_change_in_progress = false; 156 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 157 if (b_schedule_timer) 158 mod_timer(&rtlpriv->works.fw_clockoff_timer, 159 jiffies + MSECS(10)); 160 } else { 161 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 162 rtlhal->fw_clk_change_in_progress = false; 163 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 164 } 165 } 166 167 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val) 168 { 169 struct rtl_priv *rtlpriv = rtl_priv(hw); 170 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 171 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 172 struct rtl8192_tx_ring *ring; 173 enum rf_pwrstate rtstate; 174 bool b_schedule_timer = false; 175 u8 queue; 176 177 if (!rtlhal->fw_ready) 178 return; 179 if (!rtlpriv->psc.fw_current_inpsmode) 180 return; 181 if (!rtlhal->allow_sw_to_change_hwclc) 182 return; 183 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 184 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 185 return; 186 187 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 188 ring = &rtlpci->tx_ring[queue]; 189 if (skb_queue_len(&ring->queue)) { 190 b_schedule_timer = true; 191 break; 192 } 193 } 194 195 if (b_schedule_timer) { 196 mod_timer(&rtlpriv->works.fw_clockoff_timer, 197 jiffies + MSECS(10)); 198 return; 199 } 200 201 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) { 202 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 203 if (!rtlhal->fw_clk_change_in_progress) { 204 rtlhal->fw_clk_change_in_progress = true; 205 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 206 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 207 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 208 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 209 (u8 *)(&rpwm_val)); 210 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 211 rtlhal->fw_clk_change_in_progress = false; 212 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 213 } else { 214 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 215 mod_timer(&rtlpriv->works.fw_clockoff_timer, 216 jiffies + MSECS(10)); 217 } 218 } 219 220 } 221 222 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw) 223 { 224 u8 rpwm_val = 0; 225 rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK); 226 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true); 227 } 228 229 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw) 230 { 231 struct rtl_priv *rtlpriv = rtl_priv(hw); 232 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 233 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 234 bool fw_current_inps = false; 235 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 236 237 if (ppsc->low_power_enable) { 238 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */ 239 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false); 240 rtlhal->allow_sw_to_change_hwclc = false; 241 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 242 (u8 *)(&fw_pwrmode)); 243 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 244 (u8 *)(&fw_current_inps)); 245 } else { 246 rpwm_val = FW_PS_STATE_ALL_ON; /* RF on */ 247 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 248 (u8 *)(&rpwm_val)); 249 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 250 (u8 *)(&fw_pwrmode)); 251 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 252 (u8 *)(&fw_current_inps)); 253 } 254 255 } 256 257 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw) 258 { 259 struct rtl_priv *rtlpriv = rtl_priv(hw); 260 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 261 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 262 bool fw_current_inps = true; 263 u8 rpwm_val; 264 265 if (ppsc->low_power_enable) { 266 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */ 267 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 268 (u8 *)(&fw_current_inps)); 269 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 270 (u8 *)(&ppsc->fwctrl_psmode)); 271 rtlhal->allow_sw_to_change_hwclc = true; 272 _rtl8723be_set_fw_clock_off(hw, rpwm_val); 273 } else { 274 rpwm_val = FW_PS_STATE_RF_OFF; /* RF off */ 275 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 276 (u8 *)(&fw_current_inps)); 277 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 278 (u8 *)(&ppsc->fwctrl_psmode)); 279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 280 (u8 *)(&rpwm_val)); 281 } 282 283 } 284 285 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 286 { 287 struct rtl_priv *rtlpriv = rtl_priv(hw); 288 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 289 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 290 291 switch (variable) { 292 case HW_VAR_RCR: 293 *((u32 *)(val)) = rtlpci->receive_config; 294 break; 295 case HW_VAR_RF_STATE: 296 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 297 break; 298 case HW_VAR_FWLPS_RF_ON:{ 299 enum rf_pwrstate rfstate; 300 u32 val_rcr; 301 302 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 303 (u8 *)(&rfstate)); 304 if (rfstate == ERFOFF) { 305 *((bool *)(val)) = true; 306 } else { 307 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 308 val_rcr &= 0x00070000; 309 if (val_rcr) 310 *((bool *)(val)) = false; 311 else 312 *((bool *)(val)) = true; 313 } 314 } 315 break; 316 case HW_VAR_FW_PSMODE_STATUS: 317 *((bool *)(val)) = ppsc->fw_current_inpsmode; 318 break; 319 case HW_VAR_CORRECT_TSF:{ 320 u64 tsf; 321 u32 *ptsf_low = (u32 *)&tsf; 322 u32 *ptsf_high = ((u32 *)&tsf) + 1; 323 324 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 325 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 326 327 *((u64 *)(val)) = tsf; 328 } 329 break; 330 case HAL_DEF_WOWLAN: 331 break; 332 default: 333 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 334 "switch case %#x not processed\n", variable); 335 break; 336 } 337 } 338 339 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw) 340 { 341 struct rtl_priv *rtlpriv = rtl_priv(hw); 342 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 343 u8 count = 0, dlbcn_count = 0; 344 bool b_recover = false; 345 346 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 347 rtl_write_byte(rtlpriv, REG_CR + 1, 348 (tmp_regcr | BIT(0))); 349 350 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3)); 351 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0); 352 353 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 354 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6))); 355 if (tmp_reg422 & BIT(6)) 356 b_recover = true; 357 358 do { 359 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 360 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 361 (bcnvalid_reg | BIT(0))); 362 _rtl8723be_return_beacon_queue_skb(hw); 363 364 rtl8723be_set_fw_rsvdpagepkt(hw, 0); 365 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 366 count = 0; 367 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 368 count++; 369 udelay(10); 370 bcnvalid_reg = rtl_read_byte(rtlpriv, 371 REG_TDECTRL + 2); 372 } 373 dlbcn_count++; 374 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 375 376 if (bcnvalid_reg & BIT(0)) 377 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); 378 379 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); 380 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4)); 381 382 if (b_recover) 383 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 384 385 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 386 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); 387 } 388 389 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 390 { 391 struct rtl_priv *rtlpriv = rtl_priv(hw); 392 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 393 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 394 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 395 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 396 u8 idx; 397 398 switch (variable) { 399 case HW_VAR_ETHER_ADDR: 400 for (idx = 0; idx < ETH_ALEN; idx++) 401 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]); 402 break; 403 case HW_VAR_BASIC_RATE:{ 404 u16 b_rate_cfg = ((u16 *)val)[0]; 405 u8 rate_index = 0; 406 b_rate_cfg = b_rate_cfg & 0x15f; 407 b_rate_cfg |= 0x01; 408 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 409 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff); 410 while (b_rate_cfg > 0x1) { 411 b_rate_cfg = (b_rate_cfg >> 1); 412 rate_index++; 413 } 414 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index); 415 } 416 break; 417 case HW_VAR_BSSID: 418 for (idx = 0; idx < ETH_ALEN; idx++) 419 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]); 420 421 break; 422 case HW_VAR_SIFS: 423 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 424 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 425 426 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 427 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 428 429 if (!mac->ht_enable) 430 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e); 431 else 432 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 433 *((u16 *)val)); 434 break; 435 case HW_VAR_SLOT_TIME:{ 436 u8 e_aci; 437 438 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 439 "HW_VAR_SLOT_TIME %x\n", val[0]); 440 441 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 442 443 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 444 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 445 (u8 *)(&e_aci)); 446 } 447 } 448 break; 449 case HW_VAR_ACK_PREAMBLE:{ 450 u8 reg_tmp; 451 u8 short_preamble = (bool)(*(u8 *)val); 452 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2); 453 if (short_preamble) { 454 reg_tmp |= 0x02; 455 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp); 456 } else { 457 reg_tmp &= 0xFD; 458 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp); 459 } 460 } 461 break; 462 case HW_VAR_WPA_CONFIG: 463 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 464 break; 465 case HW_VAR_AMPDU_MIN_SPACE:{ 466 u8 min_spacing_to_set; 467 u8 sec_min_space; 468 469 min_spacing_to_set = *((u8 *)val); 470 if (min_spacing_to_set <= 7) { 471 sec_min_space = 0; 472 473 if (min_spacing_to_set < sec_min_space) 474 min_spacing_to_set = sec_min_space; 475 476 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | 477 min_spacing_to_set); 478 479 *val = min_spacing_to_set; 480 481 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 482 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 483 mac->min_space_cfg); 484 485 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 486 mac->min_space_cfg); 487 } 488 } 489 break; 490 case HW_VAR_SHORTGI_DENSITY:{ 491 u8 density_to_set; 492 493 density_to_set = *((u8 *)val); 494 mac->min_space_cfg |= (density_to_set << 3); 495 496 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 497 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 498 mac->min_space_cfg); 499 500 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 501 mac->min_space_cfg); 502 } 503 break; 504 case HW_VAR_AMPDU_FACTOR:{ 505 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 506 u8 factor_toset; 507 u8 *p_regtoset = NULL; 508 u8 index = 0; 509 510 p_regtoset = regtoset_normal; 511 512 factor_toset = *((u8 *)val); 513 if (factor_toset <= 3) { 514 factor_toset = (1 << (factor_toset + 2)); 515 if (factor_toset > 0xf) 516 factor_toset = 0xf; 517 518 for (index = 0; index < 4; index++) { 519 if ((p_regtoset[index] & 0xf0) > 520 (factor_toset << 4)) 521 p_regtoset[index] = 522 (p_regtoset[index] & 0x0f) | 523 (factor_toset << 4); 524 525 if ((p_regtoset[index] & 0x0f) > factor_toset) 526 p_regtoset[index] = 527 (p_regtoset[index] & 0xf0) | 528 (factor_toset); 529 530 rtl_write_byte(rtlpriv, 531 (REG_AGGLEN_LMT + index), 532 p_regtoset[index]); 533 534 } 535 536 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 537 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 538 factor_toset); 539 } 540 } 541 break; 542 case HW_VAR_AC_PARAM:{ 543 u8 e_aci = *((u8 *)val); 544 rtl8723_dm_init_edca_turbo(hw); 545 546 if (rtlpci->acm_method != EACMWAY2_SW) 547 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, 548 (u8 *)(&e_aci)); 549 } 550 break; 551 case HW_VAR_ACM_CTRL:{ 552 u8 e_aci = *((u8 *)val); 553 union aci_aifsn *p_aci_aifsn = 554 (union aci_aifsn *)(&(mac->ac[0].aifs)); 555 u8 acm = p_aci_aifsn->f.acm; 556 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 557 558 acm_ctrl = 559 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 560 561 if (acm) { 562 switch (e_aci) { 563 case AC0_BE: 564 acm_ctrl |= ACMHW_BEQEN; 565 break; 566 case AC2_VI: 567 acm_ctrl |= ACMHW_VIQEN; 568 break; 569 case AC3_VO: 570 acm_ctrl |= ACMHW_VOQEN; 571 break; 572 default: 573 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 574 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 575 acm); 576 break; 577 } 578 } else { 579 switch (e_aci) { 580 case AC0_BE: 581 acm_ctrl &= (~ACMHW_BEQEN); 582 break; 583 case AC2_VI: 584 acm_ctrl &= (~ACMHW_VIQEN); 585 break; 586 case AC3_VO: 587 acm_ctrl &= (~ACMHW_VOQEN); 588 break; 589 default: 590 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 591 "switch case %#x not processed\n", 592 e_aci); 593 break; 594 } 595 } 596 597 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, 598 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 599 acm_ctrl); 600 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 601 } 602 break; 603 case HW_VAR_RCR: 604 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 605 rtlpci->receive_config = ((u32 *)(val))[0]; 606 break; 607 case HW_VAR_RETRY_LIMIT:{ 608 u8 retry_limit = ((u8 *)(val))[0]; 609 610 rtl_write_word(rtlpriv, REG_RL, 611 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 612 retry_limit << RETRY_LIMIT_LONG_SHIFT); 613 } 614 break; 615 case HW_VAR_DUAL_TSF_RST: 616 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 617 break; 618 case HW_VAR_EFUSE_BYTES: 619 rtlefuse->efuse_usedbytes = *((u16 *)val); 620 break; 621 case HW_VAR_EFUSE_USAGE: 622 rtlefuse->efuse_usedpercentage = *((u8 *)val); 623 break; 624 case HW_VAR_IO_CMD: 625 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val)); 626 break; 627 case HW_VAR_SET_RPWM:{ 628 u8 rpwm_val; 629 630 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 631 udelay(1); 632 633 if (rpwm_val & BIT(7)) { 634 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val)); 635 } else { 636 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 637 ((*(u8 *)val) | BIT(7))); 638 } 639 } 640 break; 641 case HW_VAR_H2C_FW_PWRMODE: 642 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 643 break; 644 case HW_VAR_FW_PSMODE_STATUS: 645 ppsc->fw_current_inpsmode = *((bool *)val); 646 break; 647 case HW_VAR_RESUME_CLK_ON: 648 _rtl8723be_set_fw_ps_rf_on(hw); 649 break; 650 case HW_VAR_FW_LPS_ACTION:{ 651 bool b_enter_fwlps = *((bool *)val); 652 653 if (b_enter_fwlps) 654 _rtl8723be_fwlps_enter(hw); 655 else 656 _rtl8723be_fwlps_leave(hw); 657 } 658 break; 659 case HW_VAR_H2C_FW_JOINBSSRPT:{ 660 u8 mstatus = (*(u8 *)val); 661 662 if (mstatus == RT_MEDIA_CONNECT) { 663 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 664 _rtl8723be_download_rsvd_page(hw); 665 } 666 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus); 667 } 668 break; 669 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 670 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 671 break; 672 case HW_VAR_AID:{ 673 u16 u2btmp; 674 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 675 u2btmp &= 0xC000; 676 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 677 (u2btmp | mac->assoc_id)); 678 } 679 break; 680 case HW_VAR_CORRECT_TSF:{ 681 u8 btype_ibss = ((u8 *)(val))[0]; 682 683 if (btype_ibss) 684 _rtl8723be_stop_tx_beacon(hw); 685 686 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3)); 687 688 rtl_write_dword(rtlpriv, REG_TSFTR, 689 (u32) (mac->tsf & 0xffffffff)); 690 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 691 (u32) ((mac->tsf >> 32) & 0xffffffff)); 692 693 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); 694 695 if (btype_ibss) 696 _rtl8723be_resume_tx_beacon(hw); 697 } 698 break; 699 case HW_VAR_KEEP_ALIVE:{ 700 u8 array[2]; 701 array[0] = 0xff; 702 array[1] = *((u8 *)val); 703 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array); 704 } 705 break; 706 default: 707 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 708 "switch case %#x not processed\n", variable); 709 break; 710 } 711 } 712 713 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 714 { 715 struct rtl_priv *rtlpriv = rtl_priv(hw); 716 bool status = true; 717 long count = 0; 718 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 719 _LLT_OP(_LLT_WRITE_ACCESS); 720 721 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 722 723 do { 724 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 725 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 726 break; 727 728 if (count > POLLING_LLT_THRESHOLD) { 729 pr_err("Failed to polling write LLT done at address %d!\n", 730 address); 731 status = false; 732 break; 733 } 734 } while (++count); 735 736 return status; 737 } 738 739 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw) 740 { 741 struct rtl_priv *rtlpriv = rtl_priv(hw); 742 unsigned short i; 743 u8 txpktbuf_bndy; 744 u8 maxpage; 745 bool status; 746 747 maxpage = 255; 748 txpktbuf_bndy = 245; 749 750 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, 751 (0x27FF0000 | txpktbuf_bndy)); 752 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 753 754 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 755 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 756 757 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 758 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 759 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 760 761 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 762 status = _rtl8723be_llt_write(hw, i, i + 1); 763 if (!status) 764 return status; 765 } 766 767 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 768 769 if (!status) 770 return status; 771 772 for (i = txpktbuf_bndy; i < maxpage; i++) { 773 status = _rtl8723be_llt_write(hw, i, (i + 1)); 774 if (!status) 775 return status; 776 } 777 778 status = _rtl8723be_llt_write(hw, maxpage, txpktbuf_bndy); 779 if (!status) 780 return status; 781 782 rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808); 783 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00); 784 785 return true; 786 } 787 788 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw) 789 { 790 struct rtl_priv *rtlpriv = rtl_priv(hw); 791 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 792 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 793 794 if (rtlpriv->rtlhal.up_first_time) 795 return; 796 797 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 798 rtl8723be_sw_led_on(hw, pled0); 799 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 800 rtl8723be_sw_led_on(hw, pled0); 801 else 802 rtl8723be_sw_led_off(hw, pled0); 803 } 804 805 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw) 806 { 807 struct rtl_priv *rtlpriv = rtl_priv(hw); 808 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 809 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 810 unsigned char bytetmp; 811 unsigned short wordtmp; 812 813 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 814 815 /*Auto Power Down to CHIP-off State*/ 816 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 817 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 818 819 /* HW Power on sequence */ 820 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 821 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 822 RTL8723_NIC_ENABLE_FLOW)) { 823 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 824 "init MAC Fail as power on failure\n"); 825 return false; 826 } 827 828 if (rtlpriv->cfg->ops->get_btc_status()) 829 rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv); 830 831 bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL); 832 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3)); 833 834 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 835 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 836 837 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 838 bytetmp = 0xff; 839 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 840 mdelay(2); 841 842 bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL); 843 bytetmp |= 0x7f; 844 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 845 mdelay(2); 846 847 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3); 848 if (bytetmp & BIT(0)) { 849 bytetmp = rtl_read_byte(rtlpriv, 0x7c); 850 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6)); 851 } 852 853 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 854 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3)); 855 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 856 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4))); 857 858 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 859 860 if (!rtlhal->mac_func_enable) { 861 if (!_rtl8723be_llt_table_init(hw)) 862 return false; 863 } 864 865 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 866 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 867 868 /* Enable FW Beamformer Interrupt */ 869 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3); 870 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); 871 872 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 873 wordtmp &= 0xf; 874 wordtmp |= 0xF5B1; 875 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 876 877 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 878 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 879 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 880 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 881 882 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 883 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 884 DMA_BIT_MASK(32)); 885 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 886 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 887 DMA_BIT_MASK(32)); 888 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 889 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 890 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 891 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 892 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 893 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 894 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 895 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 896 rtl_write_dword(rtlpriv, REG_HQ_DESA, 897 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 898 DMA_BIT_MASK(32)); 899 rtl_write_dword(rtlpriv, REG_RX_DESA, 900 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 901 DMA_BIT_MASK(32)); 902 903 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3); 904 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77); 905 906 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 907 908 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 909 910 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3); 911 912 /* <20130114, Kordan> The following setting is 913 * only for DPDT and Fixed board type. 914 * TODO: A better solution is configure it 915 * according EFUSE during the run-time. 916 */ 917 rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */ 918 rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */ 919 rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */; 920 rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */; 921 rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */; 922 rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */; 923 rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */; 924 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */; 925 926 bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 927 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2))); 928 929 _rtl8723be_gen_refresh_led_state(hw); 930 return true; 931 } 932 933 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw) 934 { 935 struct rtl_priv *rtlpriv = rtl_priv(hw); 936 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 937 u32 reg_rrsr; 938 939 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 940 /* Init value for RRSR. */ 941 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 942 943 /* ARFB table 9 for 11ac 5G 2SS */ 944 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000); 945 946 /* ARFB table 10 for 11ac 5G 1SS */ 947 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000); 948 949 /* CF-End setting. */ 950 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00); 951 952 /* 0x456 = 0x70, sugguested by Zhilin */ 953 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70); 954 955 /* Set retry limit */ 956 rtl_write_word(rtlpriv, REG_RL, 0x0707); 957 958 /* Set Data / Response auto rate fallack retry count */ 959 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 960 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 961 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 962 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 963 964 rtlpci->reg_bcn_ctrl_val = 0x1d; 965 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 966 967 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 968 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */ 969 970 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 971 972 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 973 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 974 975 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80); 976 977 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 978 979 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F); 980 } 981 982 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr) 983 { 984 u16 read_addr = addr & 0xfffc; 985 u8 ret = 0, tmp = 0, count = 0; 986 987 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr); 988 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2); 989 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 990 count = 0; 991 while (tmp && count < 20) { 992 udelay(10); 993 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 994 count++; 995 } 996 if (0 == tmp) { 997 read_addr = REG_DBI_RDATA + addr % 4; 998 ret = rtl_read_byte(rtlpriv, read_addr); 999 } 1000 1001 return ret; 1002 } 1003 1004 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data) 1005 { 1006 u8 tmp = 0, count = 0; 1007 u16 write_addr = 0, remainder = addr % 4; 1008 1009 /* Write DBI 1Byte Data */ 1010 write_addr = REG_DBI_WDATA + remainder; 1011 rtl_write_byte(rtlpriv, write_addr, data); 1012 1013 /* Write DBI 2Byte Address & Write Enable */ 1014 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); 1015 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr); 1016 1017 /* Write DBI Write Flag */ 1018 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1); 1019 1020 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1021 count = 0; 1022 while (tmp && count < 20) { 1023 udelay(10); 1024 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1025 count++; 1026 } 1027 } 1028 1029 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr) 1030 { 1031 u16 ret = 0; 1032 u8 tmp = 0, count = 0; 1033 1034 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); 1035 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1036 count = 0; 1037 while (tmp && count < 20) { 1038 udelay(10); 1039 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1040 count++; 1041 } 1042 1043 if (0 == tmp) 1044 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA); 1045 1046 return ret; 1047 } 1048 1049 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data) 1050 { 1051 u8 tmp = 0, count = 0; 1052 1053 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data); 1054 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); 1055 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1056 count = 0; 1057 while (tmp && count < 20) { 1058 udelay(10); 1059 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1060 count++; 1061 } 1062 } 1063 1064 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw) 1065 { 1066 struct rtl_priv *rtlpriv = rtl_priv(hw); 1067 u8 tmp8 = 0; 1068 u16 tmp16 = 0; 1069 1070 /* <Roger_Notes> Overwrite following ePHY parameter for 1071 * some platform compatibility issue, 1072 * especially when CLKReq is enabled, 2012.11.09. 1073 */ 1074 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01); 1075 if (tmp16 != 0x0663) 1076 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663); 1077 1078 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04); 1079 if (tmp16 != 0x7544) 1080 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544); 1081 1082 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06); 1083 if (tmp16 != 0xB880) 1084 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880); 1085 1086 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07); 1087 if (tmp16 != 0x4000) 1088 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000); 1089 1090 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08); 1091 if (tmp16 != 0x9003) 1092 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003); 1093 1094 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09); 1095 if (tmp16 != 0x0D03) 1096 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03); 1097 1098 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A); 1099 if (tmp16 != 0x4037) 1100 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037); 1101 1102 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B); 1103 if (tmp16 != 0x0070) 1104 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070); 1105 1106 /* Configuration Space offset 0x70f BIT7 is used to control L0S */ 1107 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f); 1108 _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) | 1109 ASPM_L1_LATENCY << 3); 1110 1111 /* Configuration Space offset 0x719 Bit3 is for L1 1112 * BIT4 is for clock request 1113 */ 1114 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719); 1115 _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4)); 1116 } 1117 1118 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw) 1119 { 1120 struct rtl_priv *rtlpriv = rtl_priv(hw); 1121 u8 sec_reg_value; 1122 1123 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1124 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1125 rtlpriv->sec.pairwise_enc_algorithm, 1126 rtlpriv->sec.group_enc_algorithm); 1127 1128 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1129 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 1130 "not open hw encryption\n"); 1131 return; 1132 } 1133 1134 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1135 1136 if (rtlpriv->sec.use_defaultkey) { 1137 sec_reg_value |= SCR_TXUSEDK; 1138 sec_reg_value |= SCR_RXUSEDK; 1139 } 1140 1141 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1142 1143 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1144 1145 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 1146 "The SECR-value %x\n", sec_reg_value); 1147 1148 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1149 } 1150 1151 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw) 1152 { 1153 struct rtl_priv *rtlpriv = rtl_priv(hw); 1154 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1155 u8 u1b_tmp; 1156 1157 rtlhal->mac_func_enable = false; 1158 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1159 /* 1. Run LPS WL RFOFF flow */ 1160 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1161 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW); 1162 1163 /* 2. 0x1F[7:0] = 0 */ 1164 /* turn off RF */ 1165 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */ 1166 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1167 rtlhal->fw_ready) { 1168 rtl8723be_firmware_selfreset(hw); 1169 } 1170 1171 /* Reset MCU. Suggested by Filen. */ 1172 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1173 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); 1174 1175 /* g. MCUFWDL 0x80[1:0]=0 */ 1176 /* reset MCU ready status */ 1177 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1178 1179 /* HW card disable configuration. */ 1180 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1181 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW); 1182 1183 /* Reset MCU IO Wrapper */ 1184 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1185 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1186 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1187 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1188 1189 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1190 /* lock ISO/CLK/Power control register */ 1191 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1192 } 1193 1194 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv) 1195 { 1196 u8 tmp; 1197 1198 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1199 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1200 if (!(tmp & BIT(2))) { 1201 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); 1202 mdelay(100); /* Suggested by DD Justin_tsai. */ 1203 } 1204 1205 /* read reg 0x350 Bit[25] if 1 : RX hang 1206 * read reg 0x350 Bit[24] if 1 : TX hang 1207 */ 1208 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1209 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1210 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1211 "CheckPcieDMAHang8723BE(): true!!\n"); 1212 return true; 1213 } 1214 return false; 1215 } 1216 1217 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv, 1218 bool mac_power_on) 1219 { 1220 u8 tmp; 1221 bool release_mac_rx_pause; 1222 u8 backup_pcie_dma_pause; 1223 1224 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1225 "ResetPcieInterfaceDMA8723BE()\n"); 1226 1227 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03" 1228 * released by SD1 Alan. 1229 * 2013.05.07, by tynli. 1230 */ 1231 1232 /* 1. disable register write lock 1233 * write 0x1C bit[1:0] = 2'h0 1234 * write 0xCC bit[2] = 1'b1 1235 */ 1236 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1237 tmp &= ~(BIT(1) | BIT(0)); 1238 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1239 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1240 tmp |= BIT(2); 1241 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1242 1243 /* 2. Check and pause TRX DMA 1244 * write 0x284 bit[18] = 1'b1 1245 * write 0x301 = 0xFF 1246 */ 1247 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1248 if (tmp & BIT(2)) { 1249 /* Already pause before the function for another purpose. */ 1250 release_mac_rx_pause = false; 1251 } else { 1252 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1253 release_mac_rx_pause = true; 1254 } 1255 1256 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1257 if (backup_pcie_dma_pause != 0xFF) 1258 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1259 1260 if (mac_power_on) { 1261 /* 3. reset TRX function 1262 * write 0x100 = 0x00 1263 */ 1264 rtl_write_byte(rtlpriv, REG_CR, 0); 1265 } 1266 1267 /* 4. Reset PCIe DMA 1268 * write 0x003 bit[0] = 0 1269 */ 1270 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1271 tmp &= ~(BIT(0)); 1272 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1273 1274 /* 5. Enable PCIe DMA 1275 * write 0x003 bit[0] = 1 1276 */ 1277 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1278 tmp |= BIT(0); 1279 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1280 1281 if (mac_power_on) { 1282 /* 6. enable TRX function 1283 * write 0x100 = 0xFF 1284 */ 1285 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1286 1287 /* We should init LLT & RQPN and 1288 * prepare Tx/Rx descrptor address later 1289 * because MAC function is reset. 1290 */ 1291 } 1292 1293 /* 7. Restore PCIe autoload down bit 1294 * write 0xF8 bit[17] = 1'b1 1295 */ 1296 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1297 tmp |= BIT(1); 1298 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1299 1300 /* In MAC power on state, BB and RF maybe in ON state, 1301 * if we release TRx DMA here 1302 * it will cause packets to be started to Tx/Rx, 1303 * so we release Tx/Rx DMA later. 1304 */ 1305 if (!mac_power_on) { 1306 /* 8. release TRX DMA 1307 * write 0x284 bit[18] = 1'b0 1308 * write 0x301 = 0x00 1309 */ 1310 if (release_mac_rx_pause) { 1311 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1312 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1313 (tmp & (~BIT(2)))); 1314 } 1315 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1316 backup_pcie_dma_pause); 1317 } 1318 1319 /* 9. lock system register 1320 * write 0xCC bit[2] = 1'b0 1321 */ 1322 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1323 tmp &= ~(BIT(2)); 1324 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1325 } 1326 1327 int rtl8723be_hw_init(struct ieee80211_hw *hw) 1328 { 1329 struct rtl_priv *rtlpriv = rtl_priv(hw); 1330 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1331 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1332 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1333 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1335 bool rtstatus = true; 1336 int err; 1337 u8 tmp_u1b; 1338 unsigned long flags; 1339 1340 /* reenable interrupts to not interfere with other devices */ 1341 local_save_flags(flags); 1342 local_irq_enable(); 1343 1344 rtlhal->fw_ready = false; 1345 rtlpriv->rtlhal.being_init_adapter = true; 1346 rtlpriv->intf_ops->disable_aspm(hw); 1347 1348 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR); 1349 if (tmp_u1b != 0 && tmp_u1b != 0xea) { 1350 rtlhal->mac_func_enable = true; 1351 } else { 1352 rtlhal->mac_func_enable = false; 1353 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON; 1354 } 1355 1356 if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) { 1357 _rtl8723be_reset_pcie_interface_dma(rtlpriv, 1358 rtlhal->mac_func_enable); 1359 rtlhal->mac_func_enable = false; 1360 } 1361 if (rtlhal->mac_func_enable) { 1362 _rtl8723be_poweroff_adapter(hw); 1363 rtlhal->mac_func_enable = false; 1364 } 1365 rtstatus = _rtl8723be_init_mac(hw); 1366 if (!rtstatus) { 1367 pr_err("Init MAC failed\n"); 1368 err = 1; 1369 goto exit; 1370 } 1371 1372 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG); 1373 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F); 1374 1375 err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT); 1376 if (err) { 1377 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1378 "Failed to download FW. Init HW without FW now..\n"); 1379 err = 1; 1380 goto exit; 1381 } 1382 rtlhal->fw_ready = true; 1383 1384 rtlhal->last_hmeboxnum = 0; 1385 rtl8723be_phy_mac_config(hw); 1386 /* because last function modify RCR, so we update 1387 * rcr var here, or TP will unstable for receive_config 1388 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx 1389 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1390 */ 1391 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 1392 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1393 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 1394 1395 rtl8723be_phy_bb_config(hw); 1396 rtl8723be_phy_rf_config(hw); 1397 1398 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1399 RF_CHNLBW, RFREG_OFFSET_MASK); 1400 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1401 RF_CHNLBW, RFREG_OFFSET_MASK); 1402 rtlphy->rfreg_chnlval[0] &= 0xFFF03FF; 1403 rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11)); 1404 1405 _rtl8723be_hw_configure(hw); 1406 rtlhal->mac_func_enable = true; 1407 rtl_cam_reset_all_entry(hw); 1408 rtl8723be_enable_hw_security_config(hw); 1409 1410 ppsc->rfpwr_state = ERFON; 1411 1412 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1413 _rtl8723be_enable_aspm_back_door(hw); 1414 rtlpriv->intf_ops->enable_aspm(hw); 1415 1416 rtl8723be_bt_hw_init(hw); 1417 1418 if (ppsc->rfpwr_state == ERFON) { 1419 rtl8723be_phy_set_rfpath_switch(hw, 1); 1420 /* when use 1ant NIC, iqk will disturb BT music 1421 * root cause is not clear now, is something 1422 * related with 'mdelay' and Reg[0x948] 1423 */ 1424 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 || 1425 !rtlpriv->cfg->ops->get_btc_status()) { 1426 rtl8723be_phy_iq_calibrate(hw, 1427 (rtlphy->iqk_initialized ? 1428 true : false)); 1429 rtlphy->iqk_initialized = true; 1430 } 1431 rtl8723be_dm_check_txpower_tracking(hw); 1432 rtl8723be_phy_lc_calibrate(hw); 1433 } 1434 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128)); 1435 1436 /* Release Rx DMA. */ 1437 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1438 if (tmp_u1b & BIT(2)) { 1439 /* Release Rx DMA if needed */ 1440 tmp_u1b &= (~BIT(2)); 1441 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b); 1442 } 1443 /* Release Tx/Rx PCIE DMA. */ 1444 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0); 1445 1446 rtl8723be_dm_init(hw); 1447 exit: 1448 local_irq_restore(flags); 1449 rtlpriv->rtlhal.being_init_adapter = false; 1450 return err; 1451 } 1452 1453 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw) 1454 { 1455 struct rtl_priv *rtlpriv = rtl_priv(hw); 1456 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1457 enum version_8723e version = VERSION_UNKNOWN; 1458 u32 value32; 1459 1460 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1); 1461 if ((value32 & (CHIP_8723B)) != CHIP_8723B) 1462 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n"); 1463 else 1464 version = (enum version_8723e)CHIP_8723B; 1465 1466 rtlphy->rf_type = RF_1T1R; 1467 1468 /* treat rtl8723be chip as MP version in default */ 1469 version = (enum version_8723e)(version | NORMAL_CHIP); 1470 1471 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1472 /* cut version */ 1473 version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK); 1474 /* Manufacture */ 1475 if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01) 1476 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC); 1477 1478 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1479 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ? 1480 "RF_2T2R" : "RF_1T1R"); 1481 1482 return version; 1483 } 1484 1485 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw, 1486 enum nl80211_iftype type) 1487 { 1488 struct rtl_priv *rtlpriv = rtl_priv(hw); 1489 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1490 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1491 u8 mode = MSR_NOLINK; 1492 1493 switch (type) { 1494 case NL80211_IFTYPE_UNSPECIFIED: 1495 mode = MSR_NOLINK; 1496 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1497 "Set Network type to NO LINK!\n"); 1498 break; 1499 case NL80211_IFTYPE_ADHOC: 1500 case NL80211_IFTYPE_MESH_POINT: 1501 mode = MSR_ADHOC; 1502 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1503 "Set Network type to Ad Hoc!\n"); 1504 break; 1505 case NL80211_IFTYPE_STATION: 1506 mode = MSR_INFRA; 1507 ledaction = LED_CTL_LINK; 1508 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1509 "Set Network type to STA!\n"); 1510 break; 1511 case NL80211_IFTYPE_AP: 1512 mode = MSR_AP; 1513 ledaction = LED_CTL_LINK; 1514 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1515 "Set Network type to AP!\n"); 1516 break; 1517 default: 1518 pr_err("Network type %d not support!\n", type); 1519 return 1; 1520 } 1521 1522 /* MSR_INFRA == Link in infrastructure network; 1523 * MSR_ADHOC == Link in ad hoc network; 1524 * Therefore, check link state is necessary. 1525 * 1526 * MSR_AP == AP mode; link state is not cared here. 1527 */ 1528 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1529 mode = MSR_NOLINK; 1530 ledaction = LED_CTL_NO_LINK; 1531 } 1532 1533 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1534 _rtl8723be_stop_tx_beacon(hw); 1535 _rtl8723be_enable_bcn_sub_func(hw); 1536 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1537 _rtl8723be_resume_tx_beacon(hw); 1538 _rtl8723be_disable_bcn_sub_func(hw); 1539 } else { 1540 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1541 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1542 mode); 1543 } 1544 1545 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1546 rtlpriv->cfg->ops->led_control(hw, ledaction); 1547 if (mode == MSR_AP) 1548 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1549 else 1550 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1551 return 0; 1552 } 1553 1554 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1555 { 1556 struct rtl_priv *rtlpriv = rtl_priv(hw); 1557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1558 u32 reg_rcr = rtlpci->receive_config; 1559 1560 if (rtlpriv->psc.rfpwr_state != ERFON) 1561 return; 1562 1563 if (check_bssid) { 1564 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1565 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1566 (u8 *)(®_rcr)); 1567 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1568 } else if (!check_bssid) { 1569 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1570 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0); 1571 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1572 (u8 *)(®_rcr)); 1573 } 1574 1575 } 1576 1577 int rtl8723be_set_network_type(struct ieee80211_hw *hw, 1578 enum nl80211_iftype type) 1579 { 1580 struct rtl_priv *rtlpriv = rtl_priv(hw); 1581 1582 if (_rtl8723be_set_media_status(hw, type)) 1583 return -EOPNOTSUPP; 1584 1585 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1586 if (type != NL80211_IFTYPE_AP) 1587 rtl8723be_set_check_bssid(hw, true); 1588 } else { 1589 rtl8723be_set_check_bssid(hw, false); 1590 } 1591 1592 return 0; 1593 } 1594 1595 /* don't set REG_EDCA_BE_PARAM here 1596 * because mac80211 will send pkt when scan 1597 */ 1598 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci) 1599 { 1600 struct rtl_priv *rtlpriv = rtl_priv(hw); 1601 1602 rtl8723_dm_init_edca_turbo(hw); 1603 switch (aci) { 1604 case AC1_BK: 1605 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1606 break; 1607 case AC0_BE: 1608 break; 1609 case AC2_VI: 1610 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1611 break; 1612 case AC3_VO: 1613 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1614 break; 1615 default: 1616 WARN_ONCE(true, "rtl8723be: invalid aci: %d !\n", aci); 1617 break; 1618 } 1619 } 1620 1621 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw) 1622 { 1623 struct rtl_priv *rtlpriv = rtl_priv(hw); 1624 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1625 1626 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1627 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1628 rtlpci->irq_enabled = true; 1629 1630 /*enable system interrupt*/ 1631 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF); 1632 } 1633 1634 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw) 1635 { 1636 struct rtl_priv *rtlpriv = rtl_priv(hw); 1637 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1638 1639 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 1640 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 1641 rtlpci->irq_enabled = false; 1642 /*synchronize_irq(rtlpci->pdev->irq);*/ 1643 } 1644 1645 void rtl8723be_card_disable(struct ieee80211_hw *hw) 1646 { 1647 struct rtl_priv *rtlpriv = rtl_priv(hw); 1648 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1649 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1650 enum nl80211_iftype opmode; 1651 1652 mac->link_state = MAC80211_NOLINK; 1653 opmode = NL80211_IFTYPE_UNSPECIFIED; 1654 _rtl8723be_set_media_status(hw, opmode); 1655 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1656 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1657 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1658 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1659 _rtl8723be_poweroff_adapter(hw); 1660 1661 /* after power off we should do iqk again */ 1662 if (!rtlpriv->cfg->ops->get_btc_status()) 1663 rtlpriv->phy.iqk_initialized = false; 1664 } 1665 1666 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw, 1667 struct rtl_int *intvec) 1668 { 1669 struct rtl_priv *rtlpriv = rtl_priv(hw); 1670 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1671 1672 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1673 rtl_write_dword(rtlpriv, ISR, intvec->inta); 1674 1675 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & 1676 rtlpci->irq_mask[1]; 1677 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb); 1678 } 1679 1680 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw) 1681 { 1682 struct rtl_priv *rtlpriv = rtl_priv(hw); 1683 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1684 u16 bcn_interval, atim_window; 1685 1686 bcn_interval = mac->beacon_interval; 1687 atim_window = 2; /*FIX MERGE */ 1688 rtl8723be_disable_interrupt(hw); 1689 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1690 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1691 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1692 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1693 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1694 rtl_write_byte(rtlpriv, 0x606, 0x30); 1695 rtl8723be_enable_interrupt(hw); 1696 } 1697 1698 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw) 1699 { 1700 struct rtl_priv *rtlpriv = rtl_priv(hw); 1701 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1702 u16 bcn_interval = mac->beacon_interval; 1703 1704 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, 1705 "beacon_interval:%d\n", bcn_interval); 1706 rtl8723be_disable_interrupt(hw); 1707 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1708 rtl8723be_enable_interrupt(hw); 1709 } 1710 1711 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw, 1712 u32 add_msr, u32 rm_msr) 1713 { 1714 struct rtl_priv *rtlpriv = rtl_priv(hw); 1715 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1716 1717 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 1718 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1719 1720 if (add_msr) 1721 rtlpci->irq_mask[0] |= add_msr; 1722 if (rm_msr) 1723 rtlpci->irq_mask[0] &= (~rm_msr); 1724 rtl8723be_disable_interrupt(hw); 1725 rtl8723be_enable_interrupt(hw); 1726 } 1727 1728 static u8 _rtl8723be_get_chnl_group(u8 chnl) 1729 { 1730 u8 group; 1731 1732 if (chnl < 3) 1733 group = 0; 1734 else if (chnl < 9) 1735 group = 1; 1736 else 1737 group = 2; 1738 return group; 1739 } 1740 1741 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw, 1742 struct txpower_info_2g *pw2g, 1743 struct txpower_info_5g *pw5g, 1744 bool autoload_fail, u8 *hwinfo) 1745 { 1746 struct rtl_priv *rtlpriv = rtl_priv(hw); 1747 u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0; 1748 1749 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1750 "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n", 1751 (addr + 1), hwinfo[addr + 1]); 1752 if (0xFF == hwinfo[addr + 1]) /*YJ,add,120316*/ 1753 autoload_fail = true; 1754 1755 if (autoload_fail) { 1756 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1757 "auto load fail : Use Default value!\n"); 1758 for (path = 0; path < MAX_RF_PATH; path++) { 1759 /* 2.4G default value */ 1760 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1761 pw2g->index_cck_base[path][group] = 0x2D; 1762 pw2g->index_bw40_base[path][group] = 0x2D; 1763 } 1764 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) { 1765 if (cnt == 0) { 1766 pw2g->bw20_diff[path][0] = 0x02; 1767 pw2g->ofdm_diff[path][0] = 0x04; 1768 } else { 1769 pw2g->bw20_diff[path][cnt] = 0xFE; 1770 pw2g->bw40_diff[path][cnt] = 0xFE; 1771 pw2g->cck_diff[path][cnt] = 0xFE; 1772 pw2g->ofdm_diff[path][cnt] = 0xFE; 1773 } 1774 } 1775 } 1776 return; 1777 } 1778 1779 for (path = 0; path < MAX_RF_PATH; path++) { 1780 /*2.4G default value*/ 1781 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { 1782 pw2g->index_cck_base[path][group] = hwinfo[addr++]; 1783 if (pw2g->index_cck_base[path][group] == 0xFF) 1784 pw2g->index_cck_base[path][group] = 0x2D; 1785 1786 } 1787 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { 1788 pw2g->index_bw40_base[path][group] = hwinfo[addr++]; 1789 if (pw2g->index_bw40_base[path][group] == 0xFF) 1790 pw2g->index_bw40_base[path][group] = 0x2D; 1791 } 1792 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) { 1793 if (cnt == 0) { 1794 pw2g->bw40_diff[path][cnt] = 0; 1795 if (hwinfo[addr] == 0xFF) { 1796 pw2g->bw20_diff[path][cnt] = 0x02; 1797 } else { 1798 pw2g->bw20_diff[path][cnt] = 1799 (hwinfo[addr] & 0xf0) >> 4; 1800 /*bit sign number to 8 bit sign number*/ 1801 if (pw2g->bw20_diff[path][cnt] & BIT(3)) 1802 pw2g->bw20_diff[path][cnt] |= 1803 0xF0; 1804 } 1805 1806 if (hwinfo[addr] == 0xFF) { 1807 pw2g->ofdm_diff[path][cnt] = 0x04; 1808 } else { 1809 pw2g->ofdm_diff[path][cnt] = 1810 (hwinfo[addr] & 0x0f); 1811 /*bit sign number to 8 bit sign number*/ 1812 if (pw2g->ofdm_diff[path][cnt] & BIT(3)) 1813 pw2g->ofdm_diff[path][cnt] |= 1814 0xF0; 1815 } 1816 pw2g->cck_diff[path][cnt] = 0; 1817 addr++; 1818 } else { 1819 if (hwinfo[addr] == 0xFF) { 1820 pw2g->bw40_diff[path][cnt] = 0xFE; 1821 } else { 1822 pw2g->bw40_diff[path][cnt] = 1823 (hwinfo[addr] & 0xf0) >> 4; 1824 if (pw2g->bw40_diff[path][cnt] & BIT(3)) 1825 pw2g->bw40_diff[path][cnt] |= 1826 0xF0; 1827 } 1828 1829 if (hwinfo[addr] == 0xFF) { 1830 pw2g->bw20_diff[path][cnt] = 0xFE; 1831 } else { 1832 pw2g->bw20_diff[path][cnt] = 1833 (hwinfo[addr] & 0x0f); 1834 if (pw2g->bw20_diff[path][cnt] & BIT(3)) 1835 pw2g->bw20_diff[path][cnt] |= 1836 0xF0; 1837 } 1838 addr++; 1839 1840 if (hwinfo[addr] == 0xFF) { 1841 pw2g->ofdm_diff[path][cnt] = 0xFE; 1842 } else { 1843 pw2g->ofdm_diff[path][cnt] = 1844 (hwinfo[addr] & 0xf0) >> 4; 1845 if (pw2g->ofdm_diff[path][cnt] & BIT(3)) 1846 pw2g->ofdm_diff[path][cnt] |= 1847 0xF0; 1848 } 1849 1850 if (hwinfo[addr] == 0xFF) 1851 pw2g->cck_diff[path][cnt] = 0xFE; 1852 else { 1853 pw2g->cck_diff[path][cnt] = 1854 (hwinfo[addr] & 0x0f); 1855 if (pw2g->cck_diff[path][cnt] & BIT(3)) 1856 pw2g->cck_diff[path][cnt] |= 1857 0xF0; 1858 } 1859 addr++; 1860 } 1861 } 1862 1863 /*5G default value*/ 1864 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) { 1865 pw5g->index_bw40_base[path][group] = hwinfo[addr++]; 1866 if (pw5g->index_bw40_base[path][group] == 0xFF) 1867 pw5g->index_bw40_base[path][group] = 0xFE; 1868 } 1869 1870 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) { 1871 if (cnt == 0) { 1872 pw5g->bw40_diff[path][cnt] = 0; 1873 1874 if (hwinfo[addr] == 0xFF) { 1875 pw5g->bw20_diff[path][cnt] = 0; 1876 } else { 1877 pw5g->bw20_diff[path][0] = 1878 (hwinfo[addr] & 0xf0) >> 4; 1879 if (pw5g->bw20_diff[path][cnt] & BIT(3)) 1880 pw5g->bw20_diff[path][cnt] |= 1881 0xF0; 1882 } 1883 1884 if (hwinfo[addr] == 0xFF) 1885 pw5g->ofdm_diff[path][cnt] = 0x04; 1886 else { 1887 pw5g->ofdm_diff[path][0] = 1888 (hwinfo[addr] & 0x0f); 1889 if (pw5g->ofdm_diff[path][cnt] & BIT(3)) 1890 pw5g->ofdm_diff[path][cnt] |= 1891 0xF0; 1892 } 1893 addr++; 1894 } else { 1895 if (hwinfo[addr] == 0xFF) { 1896 pw5g->bw40_diff[path][cnt] = 0xFE; 1897 } else { 1898 pw5g->bw40_diff[path][cnt] = 1899 (hwinfo[addr] & 0xf0) >> 4; 1900 if (pw5g->bw40_diff[path][cnt] & BIT(3)) 1901 pw5g->bw40_diff[path][cnt] |= 0xF0; 1902 } 1903 1904 if (hwinfo[addr] == 0xFF) { 1905 pw5g->bw20_diff[path][cnt] = 0xFE; 1906 } else { 1907 pw5g->bw20_diff[path][cnt] = 1908 (hwinfo[addr] & 0x0f); 1909 if (pw5g->bw20_diff[path][cnt] & BIT(3)) 1910 pw5g->bw20_diff[path][cnt] |= 0xF0; 1911 } 1912 addr++; 1913 } 1914 } 1915 1916 if (hwinfo[addr] == 0xFF) { 1917 pw5g->ofdm_diff[path][1] = 0xFE; 1918 pw5g->ofdm_diff[path][2] = 0xFE; 1919 } else { 1920 pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4; 1921 pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f); 1922 } 1923 addr++; 1924 1925 if (hwinfo[addr] == 0xFF) 1926 pw5g->ofdm_diff[path][3] = 0xFE; 1927 else 1928 pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f); 1929 addr++; 1930 1931 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) { 1932 if (pw5g->ofdm_diff[path][cnt] == 0xFF) 1933 pw5g->ofdm_diff[path][cnt] = 0xFE; 1934 else if (pw5g->ofdm_diff[path][cnt] & BIT(3)) 1935 pw5g->ofdm_diff[path][cnt] |= 0xF0; 1936 } 1937 } 1938 } 1939 1940 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1941 bool autoload_fail, 1942 u8 *hwinfo) 1943 { 1944 struct rtl_priv *rtlpriv = rtl_priv(hw); 1945 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1946 struct txpower_info_2g pw2g; 1947 struct txpower_info_5g pw5g; 1948 u8 rf_path, index; 1949 u8 i; 1950 1951 _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail, 1952 hwinfo); 1953 1954 for (rf_path = 0; rf_path < 2; rf_path++) { 1955 for (i = 0; i < 14; i++) { 1956 index = _rtl8723be_get_chnl_group(i+1); 1957 1958 rtlefuse->txpwrlevel_cck[rf_path][i] = 1959 pw2g.index_cck_base[rf_path][index]; 1960 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1961 pw2g.index_bw40_base[rf_path][index]; 1962 } 1963 for (i = 0; i < MAX_TX_COUNT; i++) { 1964 rtlefuse->txpwr_ht20diff[rf_path][i] = 1965 pw2g.bw20_diff[rf_path][i]; 1966 rtlefuse->txpwr_ht40diff[rf_path][i] = 1967 pw2g.bw40_diff[rf_path][i]; 1968 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 1969 pw2g.ofdm_diff[rf_path][i]; 1970 } 1971 1972 for (i = 0; i < 14; i++) { 1973 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1974 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n", 1975 rf_path, i, 1976 rtlefuse->txpwrlevel_cck[rf_path][i], 1977 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]); 1978 } 1979 } 1980 1981 if (!autoload_fail) 1982 rtlefuse->eeprom_thermalmeter = 1983 hwinfo[EEPROM_THERMAL_METER_88E]; 1984 else 1985 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1986 1987 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) { 1988 rtlefuse->apk_thermalmeterignore = true; 1989 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1990 } 1991 1992 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1993 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1994 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1995 1996 if (!autoload_fail) { 1997 rtlefuse->eeprom_regulatory = 1998 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/ 1999 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) 2000 rtlefuse->eeprom_regulatory = 0; 2001 } else { 2002 rtlefuse->eeprom_regulatory = 0; 2003 } 2004 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2005 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2006 } 2007 2008 static u8 _rtl8723be_read_package_type(struct ieee80211_hw *hw) 2009 { 2010 u8 package_type; 2011 u8 value; 2012 2013 efuse_power_switch(hw, false, true); 2014 if (!efuse_one_byte_read(hw, 0x1FB, &value)) 2015 value = 0; 2016 efuse_power_switch(hw, false, false); 2017 2018 switch (value & 0x7) { 2019 case 0x4: 2020 package_type = PACKAGE_TFBGA79; 2021 break; 2022 case 0x5: 2023 package_type = PACKAGE_TFBGA90; 2024 break; 2025 case 0x6: 2026 package_type = PACKAGE_QFN68; 2027 break; 2028 case 0x7: 2029 package_type = PACKAGE_TFBGA80; 2030 break; 2031 default: 2032 package_type = PACKAGE_DEFAULT; 2033 break; 2034 } 2035 2036 return package_type; 2037 } 2038 2039 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw, 2040 bool pseudo_test) 2041 { 2042 struct rtl_priv *rtlpriv = rtl_priv(hw); 2043 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2044 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2045 int params[] = {RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID, 2046 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 2047 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 2048 COUNTRY_CODE_WORLD_WIDE_13}; 2049 u8 *hwinfo; 2050 int i; 2051 bool is_toshiba_smid1 = false; 2052 bool is_toshiba_smid2 = false; 2053 bool is_samsung_smid = false; 2054 bool is_lenovo_smid = false; 2055 u16 toshiba_smid1[] = { 2056 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180, 2057 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180, 2058 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185, 2059 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185 2060 }; 2061 u16 toshiba_smid2[] = { 2062 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181, 2063 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185 2064 }; 2065 u16 samsung_smid[] = { 2066 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192, 2067 0x8193, 0x9191, 0x9192, 0x9193 2068 }; 2069 u16 lenovo_smid[] = { 2070 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200 2071 }; 2072 2073 if (pseudo_test) { 2074 /* needs to be added */ 2075 return; 2076 } 2077 2078 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 2079 if (!hwinfo) 2080 return; 2081 2082 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 2083 goto exit; 2084 2085 /*parse xtal*/ 2086 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE]; 2087 if (rtlefuse->crystalcap == 0xFF) 2088 rtlefuse->crystalcap = 0x20; 2089 2090 _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 2091 hwinfo); 2092 2093 rtl8723be_read_bt_coexist_info_from_hwpg(hw, 2094 rtlefuse->autoload_failflag, 2095 hwinfo); 2096 2097 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) 2098 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */ 2099 2100 rtlhal->board_type = rtlefuse->board_type; 2101 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2102 "board_type = 0x%x\n", rtlefuse->board_type); 2103 2104 rtlhal->package_type = _rtl8723be_read_package_type(hw); 2105 2106 /* set channel plan from efuse */ 2107 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 2108 2109 if (rtlhal->oem_id == RT_CID_DEFAULT) { 2110 /* Does this one have a Toshiba SMID from group 1? */ 2111 for (i = 0; i < ARRAY_SIZE(toshiba_smid1); i++) { 2112 if (rtlefuse->eeprom_smid == toshiba_smid1[i]) { 2113 is_toshiba_smid1 = true; 2114 break; 2115 } 2116 } 2117 /* Does this one have a Toshiba SMID from group 2? */ 2118 for (i = 0; i < ARRAY_SIZE(toshiba_smid2); i++) { 2119 if (rtlefuse->eeprom_smid == toshiba_smid2[i]) { 2120 is_toshiba_smid2 = true; 2121 break; 2122 } 2123 } 2124 /* Does this one have a Samsung SMID? */ 2125 for (i = 0; i < ARRAY_SIZE(samsung_smid); i++) { 2126 if (rtlefuse->eeprom_smid == samsung_smid[i]) { 2127 is_samsung_smid = true; 2128 break; 2129 } 2130 } 2131 /* Does this one have a Lenovo SMID? */ 2132 for (i = 0; i < ARRAY_SIZE(lenovo_smid); i++) { 2133 if (rtlefuse->eeprom_smid == lenovo_smid[i]) { 2134 is_lenovo_smid = true; 2135 break; 2136 } 2137 } 2138 switch (rtlefuse->eeprom_oemid) { 2139 case EEPROM_CID_DEFAULT: 2140 if (rtlefuse->eeprom_did == 0x8176) { 2141 if (rtlefuse->eeprom_svid == 0x10EC && 2142 is_toshiba_smid1) { 2143 rtlhal->oem_id = RT_CID_TOSHIBA; 2144 } else if (rtlefuse->eeprom_svid == 0x1025) { 2145 rtlhal->oem_id = RT_CID_819X_ACER; 2146 } else if (rtlefuse->eeprom_svid == 0x10EC && 2147 is_samsung_smid) { 2148 rtlhal->oem_id = RT_CID_819X_SAMSUNG; 2149 } else if (rtlefuse->eeprom_svid == 0x10EC && 2150 is_lenovo_smid) { 2151 rtlhal->oem_id = RT_CID_819X_LENOVO; 2152 } else if ((rtlefuse->eeprom_svid == 0x10EC && 2153 rtlefuse->eeprom_smid == 0x8197) || 2154 (rtlefuse->eeprom_svid == 0x10EC && 2155 rtlefuse->eeprom_smid == 0x9196)) { 2156 rtlhal->oem_id = RT_CID_819X_CLEVO; 2157 } else if ((rtlefuse->eeprom_svid == 0x1028 && 2158 rtlefuse->eeprom_smid == 0x8194) || 2159 (rtlefuse->eeprom_svid == 0x1028 && 2160 rtlefuse->eeprom_smid == 0x8198) || 2161 (rtlefuse->eeprom_svid == 0x1028 && 2162 rtlefuse->eeprom_smid == 0x9197) || 2163 (rtlefuse->eeprom_svid == 0x1028 && 2164 rtlefuse->eeprom_smid == 0x9198)) { 2165 rtlhal->oem_id = RT_CID_819X_DELL; 2166 } else if ((rtlefuse->eeprom_svid == 0x103C && 2167 rtlefuse->eeprom_smid == 0x1629)) { 2168 rtlhal->oem_id = RT_CID_819X_HP; 2169 } else if ((rtlefuse->eeprom_svid == 0x1A32 && 2170 rtlefuse->eeprom_smid == 0x2315)) { 2171 rtlhal->oem_id = RT_CID_819X_QMI; 2172 } else if ((rtlefuse->eeprom_svid == 0x10EC && 2173 rtlefuse->eeprom_smid == 0x8203)) { 2174 rtlhal->oem_id = RT_CID_819X_PRONETS; 2175 } else if ((rtlefuse->eeprom_svid == 0x1043 && 2176 rtlefuse->eeprom_smid == 0x84B5)) { 2177 rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS; 2178 } else { 2179 rtlhal->oem_id = RT_CID_DEFAULT; 2180 } 2181 } else if (rtlefuse->eeprom_did == 0x8178) { 2182 if (rtlefuse->eeprom_svid == 0x10EC && 2183 is_toshiba_smid2) 2184 rtlhal->oem_id = RT_CID_TOSHIBA; 2185 else if (rtlefuse->eeprom_svid == 0x1025) 2186 rtlhal->oem_id = RT_CID_819X_ACER; 2187 else if ((rtlefuse->eeprom_svid == 0x10EC && 2188 rtlefuse->eeprom_smid == 0x8186)) 2189 rtlhal->oem_id = RT_CID_819X_PRONETS; 2190 else if ((rtlefuse->eeprom_svid == 0x1043 && 2191 rtlefuse->eeprom_smid == 0x84B6)) 2192 rtlhal->oem_id = 2193 RT_CID_819X_EDIMAX_ASUS; 2194 else 2195 rtlhal->oem_id = RT_CID_DEFAULT; 2196 } else { 2197 rtlhal->oem_id = RT_CID_DEFAULT; 2198 } 2199 break; 2200 case EEPROM_CID_TOSHIBA: 2201 rtlhal->oem_id = RT_CID_TOSHIBA; 2202 break; 2203 case EEPROM_CID_CCX: 2204 rtlhal->oem_id = RT_CID_CCX; 2205 break; 2206 case EEPROM_CID_QMI: 2207 rtlhal->oem_id = RT_CID_819X_QMI; 2208 break; 2209 case EEPROM_CID_WHQL: 2210 break; 2211 default: 2212 rtlhal->oem_id = RT_CID_DEFAULT; 2213 break; 2214 } 2215 } 2216 exit: 2217 kfree(hwinfo); 2218 } 2219 2220 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw) 2221 { 2222 struct rtl_priv *rtlpriv = rtl_priv(hw); 2223 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2224 2225 rtlpriv->ledctl.led_opendrain = true; 2226 switch (rtlhal->oem_id) { 2227 case RT_CID_819X_HP: 2228 rtlpriv->ledctl.led_opendrain = true; 2229 break; 2230 case RT_CID_819X_LENOVO: 2231 case RT_CID_DEFAULT: 2232 case RT_CID_TOSHIBA: 2233 case RT_CID_CCX: 2234 case RT_CID_819X_ACER: 2235 case RT_CID_WHQL: 2236 default: 2237 break; 2238 } 2239 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2240 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 2241 } 2242 2243 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw) 2244 { 2245 struct rtl_priv *rtlpriv = rtl_priv(hw); 2246 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2247 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2248 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2249 u8 tmp_u1b; 2250 2251 rtlhal->version = _rtl8723be_read_chip_version(hw); 2252 if (get_rf_type(rtlphy) == RF_1T1R) 2253 rtlpriv->dm.rfpath_rxenable[0] = true; 2254 else 2255 rtlpriv->dm.rfpath_rxenable[0] = 2256 rtlpriv->dm.rfpath_rxenable[1] = true; 2257 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 2258 rtlhal->version); 2259 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 2260 if (tmp_u1b & BIT(4)) { 2261 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 2262 rtlefuse->epromtype = EEPROM_93C46; 2263 } else { 2264 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 2265 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 2266 } 2267 if (tmp_u1b & BIT(5)) { 2268 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 2269 rtlefuse->autoload_failflag = false; 2270 _rtl8723be_read_adapter_info(hw, false); 2271 } else { 2272 pr_err("Autoload ERR!!\n"); 2273 } 2274 _rtl8723be_hal_customized_behavior(hw); 2275 } 2276 2277 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, 2278 u8 rate_index) 2279 { 2280 u8 ret = 0; 2281 switch (rate_index) { 2282 case RATR_INX_WIRELESS_NGB: 2283 ret = 1; 2284 break; 2285 case RATR_INX_WIRELESS_N: 2286 case RATR_INX_WIRELESS_NG: 2287 ret = 5; 2288 break; 2289 case RATR_INX_WIRELESS_NB: 2290 ret = 3; 2291 break; 2292 case RATR_INX_WIRELESS_GB: 2293 ret = 6; 2294 break; 2295 case RATR_INX_WIRELESS_G: 2296 ret = 7; 2297 break; 2298 case RATR_INX_WIRELESS_B: 2299 ret = 8; 2300 break; 2301 default: 2302 ret = 0; 2303 break; 2304 } 2305 return ret; 2306 } 2307 2308 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw, 2309 struct ieee80211_sta *sta, 2310 u8 rssi_level, bool update_bw) 2311 { 2312 struct rtl_priv *rtlpriv = rtl_priv(hw); 2313 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2314 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2315 struct rtl_sta_info *sta_entry = NULL; 2316 u32 ratr_bitmap; 2317 u8 ratr_index; 2318 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & 2319 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0; 2320 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2321 1 : 0; 2322 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2323 1 : 0; 2324 enum wireless_mode wirelessmode = 0; 2325 bool shortgi = false; 2326 u8 rate_mask[7]; 2327 u8 macid = 0; 2328 2329 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 2330 wirelessmode = sta_entry->wireless_mode; 2331 if (mac->opmode == NL80211_IFTYPE_STATION || 2332 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2333 curtxbw_40mhz = mac->bw_40; 2334 else if (mac->opmode == NL80211_IFTYPE_AP || 2335 mac->opmode == NL80211_IFTYPE_ADHOC) 2336 macid = sta->aid + 1; 2337 2338 ratr_bitmap = sta->deflink.supp_rates[0]; 2339 2340 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2341 ratr_bitmap = 0xfff; 2342 2343 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 2344 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 2345 switch (wirelessmode) { 2346 case WIRELESS_MODE_B: 2347 ratr_index = RATR_INX_WIRELESS_B; 2348 if (ratr_bitmap & 0x0000000c) 2349 ratr_bitmap &= 0x0000000d; 2350 else 2351 ratr_bitmap &= 0x0000000f; 2352 break; 2353 case WIRELESS_MODE_G: 2354 ratr_index = RATR_INX_WIRELESS_GB; 2355 2356 if (rssi_level == 1) 2357 ratr_bitmap &= 0x00000f00; 2358 else if (rssi_level == 2) 2359 ratr_bitmap &= 0x00000ff0; 2360 else 2361 ratr_bitmap &= 0x00000ff5; 2362 break; 2363 case WIRELESS_MODE_N_24G: 2364 case WIRELESS_MODE_N_5G: 2365 ratr_index = RATR_INX_WIRELESS_NGB; 2366 if (rtlphy->rf_type == RF_1T1R) { 2367 if (curtxbw_40mhz) { 2368 if (rssi_level == 1) 2369 ratr_bitmap &= 0x000f0000; 2370 else if (rssi_level == 2) 2371 ratr_bitmap &= 0x000ff000; 2372 else 2373 ratr_bitmap &= 0x000ff015; 2374 } else { 2375 if (rssi_level == 1) 2376 ratr_bitmap &= 0x000f0000; 2377 else if (rssi_level == 2) 2378 ratr_bitmap &= 0x000ff000; 2379 else 2380 ratr_bitmap &= 0x000ff005; 2381 } 2382 } else { 2383 if (curtxbw_40mhz) { 2384 if (rssi_level == 1) 2385 ratr_bitmap &= 0x0f8f0000; 2386 else if (rssi_level == 2) 2387 ratr_bitmap &= 0x0f8ff000; 2388 else 2389 ratr_bitmap &= 0x0f8ff015; 2390 } else { 2391 if (rssi_level == 1) 2392 ratr_bitmap &= 0x0f8f0000; 2393 else if (rssi_level == 2) 2394 ratr_bitmap &= 0x0f8ff000; 2395 else 2396 ratr_bitmap &= 0x0f8ff005; 2397 } 2398 } 2399 if ((curtxbw_40mhz && curshortgi_40mhz) || 2400 (!curtxbw_40mhz && curshortgi_20mhz)) { 2401 if (macid == 0) 2402 shortgi = true; 2403 else if (macid == 1) 2404 shortgi = false; 2405 } 2406 break; 2407 default: 2408 ratr_index = RATR_INX_WIRELESS_NGB; 2409 2410 if (rtlphy->rf_type == RF_1T2R) 2411 ratr_bitmap &= 0x000ff0ff; 2412 else 2413 ratr_bitmap &= 0x0f0ff0ff; 2414 break; 2415 } 2416 2417 sta_entry->ratr_index = ratr_index; 2418 2419 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 2420 "ratr_bitmap :%x\n", ratr_bitmap); 2421 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2422 (ratr_index << 28); 2423 rate_mask[0] = macid; 2424 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) | 2425 (shortgi ? 0x80 : 0x00); 2426 rate_mask[2] = curtxbw_40mhz | ((!update_bw) << 3); 2427 2428 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 2429 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 2430 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 2431 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 2432 2433 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 2434 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 2435 ratr_index, ratr_bitmap, 2436 rate_mask[0], rate_mask[1], 2437 rate_mask[2], rate_mask[3], 2438 rate_mask[4], rate_mask[5], 2439 rate_mask[6]); 2440 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask); 2441 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); 2442 } 2443 2444 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw, 2445 struct ieee80211_sta *sta, 2446 u8 rssi_level, bool update_bw) 2447 { 2448 struct rtl_priv *rtlpriv = rtl_priv(hw); 2449 if (rtlpriv->dm.useramask) 2450 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2451 } 2452 2453 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw) 2454 { 2455 struct rtl_priv *rtlpriv = rtl_priv(hw); 2456 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2457 u16 sifs_timer; 2458 2459 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); 2460 if (!mac->ht_enable) 2461 sifs_timer = 0x0a0a; 2462 else 2463 sifs_timer = 0x0e0e; 2464 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2465 } 2466 2467 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2468 { 2469 struct rtl_priv *rtlpriv = rtl_priv(hw); 2470 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2471 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2472 enum rf_pwrstate e_rfpowerstate_toset; 2473 u8 u1tmp; 2474 bool b_actuallyset = false; 2475 2476 if (rtlpriv->rtlhal.being_init_adapter) 2477 return false; 2478 2479 if (ppsc->swrf_processing) 2480 return false; 2481 2482 spin_lock(&rtlpriv->locks.rf_ps_lock); 2483 if (ppsc->rfchange_inprogress) { 2484 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2485 return false; 2486 } else { 2487 ppsc->rfchange_inprogress = true; 2488 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2489 } 2490 2491 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 2492 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1))); 2493 2494 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 2495 2496 if (rtlphy->polarity_ctl) 2497 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 2498 else 2499 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 2500 2501 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2502 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2503 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2504 2505 e_rfpowerstate_toset = ERFON; 2506 ppsc->hwradiooff = false; 2507 b_actuallyset = true; 2508 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2509 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2510 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2511 2512 e_rfpowerstate_toset = ERFOFF; 2513 ppsc->hwradiooff = true; 2514 b_actuallyset = true; 2515 } 2516 2517 if (b_actuallyset) { 2518 spin_lock(&rtlpriv->locks.rf_ps_lock); 2519 ppsc->rfchange_inprogress = false; 2520 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2521 } else { 2522 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2523 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2524 2525 spin_lock(&rtlpriv->locks.rf_ps_lock); 2526 ppsc->rfchange_inprogress = false; 2527 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2528 } 2529 2530 *valid = 1; 2531 return !ppsc->hwradiooff; 2532 2533 } 2534 2535 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index, 2536 u8 *p_macaddr, bool is_group, u8 enc_algo, 2537 bool is_wepkey, bool clear_all) 2538 { 2539 struct rtl_priv *rtlpriv = rtl_priv(hw); 2540 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2541 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2542 u8 *macaddr = p_macaddr; 2543 u32 entry_id = 0; 2544 bool is_pairwise = false; 2545 2546 static u8 cam_const_addr[4][6] = { 2547 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2548 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2549 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2550 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2551 }; 2552 static u8 cam_const_broad[] = { 2553 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2554 }; 2555 2556 if (clear_all) { 2557 u8 idx = 0; 2558 u8 cam_offset = 0; 2559 u8 clear_number = 5; 2560 2561 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2562 2563 for (idx = 0; idx < clear_number; idx++) { 2564 rtl_cam_mark_invalid(hw, cam_offset + idx); 2565 rtl_cam_empty_entry(hw, cam_offset + idx); 2566 2567 if (idx < 5) { 2568 memset(rtlpriv->sec.key_buf[idx], 0, 2569 MAX_KEY_LEN); 2570 rtlpriv->sec.key_len[idx] = 0; 2571 } 2572 } 2573 2574 } else { 2575 switch (enc_algo) { 2576 case WEP40_ENCRYPTION: 2577 enc_algo = CAM_WEP40; 2578 break; 2579 case WEP104_ENCRYPTION: 2580 enc_algo = CAM_WEP104; 2581 break; 2582 case TKIP_ENCRYPTION: 2583 enc_algo = CAM_TKIP; 2584 break; 2585 case AESCCMP_ENCRYPTION: 2586 enc_algo = CAM_AES; 2587 break; 2588 default: 2589 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 2590 "switch case %#x not processed\n", enc_algo); 2591 enc_algo = CAM_TKIP; 2592 break; 2593 } 2594 2595 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2596 macaddr = cam_const_addr[key_index]; 2597 entry_id = key_index; 2598 } else { 2599 if (is_group) { 2600 macaddr = cam_const_broad; 2601 entry_id = key_index; 2602 } else { 2603 if (mac->opmode == NL80211_IFTYPE_AP) { 2604 entry_id = rtl_cam_get_free_entry(hw, 2605 p_macaddr); 2606 if (entry_id >= TOTAL_CAM_ENTRY) { 2607 pr_err("Can not find free hw security cam entry\n"); 2608 return; 2609 } 2610 } else { 2611 entry_id = CAM_PAIRWISE_KEY_POSITION; 2612 } 2613 2614 key_index = PAIRWISE_KEYIDX; 2615 is_pairwise = true; 2616 } 2617 } 2618 2619 if (rtlpriv->sec.key_len[key_index] == 0) { 2620 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2621 "delete one entry, entry_id is %d\n", 2622 entry_id); 2623 if (mac->opmode == NL80211_IFTYPE_AP) 2624 rtl_cam_del_entry(hw, p_macaddr); 2625 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2626 } else { 2627 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2628 "add one entry\n"); 2629 if (is_pairwise) { 2630 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2631 "set Pairwise key\n"); 2632 2633 rtl_cam_add_one_entry(hw, macaddr, key_index, 2634 entry_id, enc_algo, 2635 CAM_CONFIG_NO_USEDK, 2636 rtlpriv->sec.key_buf[key_index]); 2637 } else { 2638 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2639 "set group key\n"); 2640 2641 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2642 rtl_cam_add_one_entry(hw, 2643 rtlefuse->dev_addr, 2644 PAIRWISE_KEYIDX, 2645 CAM_PAIRWISE_KEY_POSITION, 2646 enc_algo, 2647 CAM_CONFIG_NO_USEDK, 2648 rtlpriv->sec.key_buf 2649 [entry_id]); 2650 } 2651 2652 rtl_cam_add_one_entry(hw, macaddr, key_index, 2653 entry_id, enc_algo, 2654 CAM_CONFIG_NO_USEDK, 2655 rtlpriv->sec.key_buf[entry_id]); 2656 } 2657 } 2658 } 2659 } 2660 2661 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2662 bool auto_load_fail, u8 *hwinfo) 2663 { 2664 struct rtl_priv *rtlpriv = rtl_priv(hw); 2665 struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params; 2666 u8 value; 2667 u32 tmpu_32; 2668 2669 if (!auto_load_fail) { 2670 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2671 if (tmpu_32 & BIT(18)) 2672 rtlpriv->btcoexist.btc_info.btcoexist = 1; 2673 else 2674 rtlpriv->btcoexist.btc_info.btcoexist = 0; 2675 value = hwinfo[EEPROM_RF_BT_SETTING_8723B]; 2676 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B; 2677 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 2678 rtlpriv->btcoexist.btc_info.single_ant_path = 2679 (value & 0x40 ? ANT_AUX : ANT_MAIN); /*0xc3[6]*/ 2680 } else { 2681 rtlpriv->btcoexist.btc_info.btcoexist = 0; 2682 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B; 2683 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 2684 rtlpriv->btcoexist.btc_info.single_ant_path = ANT_MAIN; 2685 } 2686 2687 /* override ant_num / ant_path */ 2688 if (mod_params->ant_sel) { 2689 rtlpriv->btcoexist.btc_info.ant_num = 2690 (mod_params->ant_sel == 1 ? ANT_X1 : ANT_X2); 2691 2692 rtlpriv->btcoexist.btc_info.single_ant_path = 2693 (mod_params->ant_sel == 1 ? ANT_AUX : ANT_MAIN); 2694 } 2695 } 2696 2697 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw) 2698 { 2699 struct rtl_priv *rtlpriv = rtl_priv(hw); 2700 2701 /* 0:Low, 1:High, 2:From Efuse. */ 2702 rtlpriv->btcoexist.reg_bt_iso = 2; 2703 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2704 rtlpriv->btcoexist.reg_bt_sco = 3; 2705 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2706 rtlpriv->btcoexist.reg_bt_sco = 0; 2707 } 2708 2709 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw) 2710 { 2711 struct rtl_priv *rtlpriv = rtl_priv(hw); 2712 2713 if (rtlpriv->cfg->ops->get_btc_status()) 2714 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 2715 2716 } 2717 2718 void rtl8723be_suspend(struct ieee80211_hw *hw) 2719 { 2720 } 2721 2722 void rtl8723be_resume(struct ieee80211_hw *hw) 2723 { 2724 } 2725