1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../base.h" 28 #include "../pci.h" 29 #include "../core.h" 30 #include "reg.h" 31 #include "def.h" 32 #include "phy.h" 33 #include "dm.h" 34 #include "../rtl8723com/dm_common.h" 35 #include "fw.h" 36 #include "hal_btc.h" 37 38 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = { 39 0x7f8001fe, 40 0x788001e2, 41 0x71c001c7, 42 0x6b8001ae, 43 0x65400195, 44 0x5fc0017f, 45 0x5a400169, 46 0x55400155, 47 0x50800142, 48 0x4c000130, 49 0x47c0011f, 50 0x43c0010f, 51 0x40000100, 52 0x3c8000f2, 53 0x390000e4, 54 0x35c000d7, 55 0x32c000cb, 56 0x300000c0, 57 0x2d4000b5, 58 0x2ac000ab, 59 0x288000a2, 60 0x26000098, 61 0x24000090, 62 0x22000088, 63 0x20000080, 64 0x1e400079, 65 0x1c800072, 66 0x1b00006c, 67 0x19800066, 68 0x18000060, 69 0x16c0005b, 70 0x15800056, 71 0x14400051, 72 0x1300004c, 73 0x12000048, 74 0x11000044, 75 0x10000040, 76 }; 77 78 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { 79 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, 80 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, 81 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, 82 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, 83 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, 84 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, 85 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, 86 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, 87 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, 88 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, 89 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, 90 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, 91 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, 92 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, 93 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, 94 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, 95 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, 96 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, 97 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, 98 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 99 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 100 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, 101 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, 102 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, 103 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, 104 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, 105 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, 106 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, 107 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, 108 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, 109 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, 110 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, 111 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} 112 }; 113 114 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { 115 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, 116 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, 117 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, 118 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, 119 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, 120 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, 121 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, 122 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, 123 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, 124 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, 125 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, 126 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, 127 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, 128 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, 129 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, 130 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, 131 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, 132 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, 133 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, 134 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 135 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 136 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, 137 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, 138 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 139 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 140 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, 141 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 142 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 143 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 144 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 145 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 146 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 147 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} 148 }; 149 150 static u8 rtl8723e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) 151 { 152 struct rtl_priv *rtlpriv = rtl_priv(hw); 153 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 154 struct rtl_mac *mac = rtl_mac(rtlpriv); 155 long rssi_val_min = 0; 156 157 if (mac->link_state == MAC80211_LINKED && 158 mac->opmode == NL80211_IFTYPE_STATION && 159 rtlpriv->link_info.bcn_rx_inperiod == 0) 160 return 0; 161 162 if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) && 163 (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) { 164 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0) 165 rssi_val_min = 166 (rtlpriv->dm.entry_min_undec_sm_pwdb > 167 rtlpriv->dm.undec_sm_pwdb) ? 168 rtlpriv->dm.undec_sm_pwdb : 169 rtlpriv->dm.entry_min_undec_sm_pwdb; 170 else 171 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 172 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT || 173 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) { 174 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 175 } else if (dm_digtable->curmultista_cstate == 176 DIG_MULTISTA_CONNECT) { 177 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; 178 } 179 180 return (u8) rssi_val_min; 181 } 182 183 static void rtl8723e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 184 { 185 u32 ret_value; 186 struct rtl_priv *rtlpriv = rtl_priv(hw); 187 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 188 189 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); 190 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 191 192 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); 193 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 194 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 195 196 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); 197 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 198 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 199 falsealm_cnt->cnt_rate_illegal + 200 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail; 201 202 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); 203 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); 204 falsealm_cnt->cnt_cck_fail = ret_value; 205 206 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); 207 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; 208 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail + 209 falsealm_cnt->cnt_rate_illegal + 210 falsealm_cnt->cnt_crc8_fail + 211 falsealm_cnt->cnt_mcs_fail + 212 falsealm_cnt->cnt_cck_fail); 213 214 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); 215 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); 216 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); 217 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); 218 219 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 220 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n", 221 falsealm_cnt->cnt_parity_fail, 222 falsealm_cnt->cnt_rate_illegal, 223 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail); 224 225 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 226 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n", 227 falsealm_cnt->cnt_ofdm_fail, 228 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all); 229 } 230 231 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw) 232 { 233 struct rtl_priv *rtlpriv = rtl_priv(hw); 234 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 235 u8 value_igi = dm_digtable->cur_igvalue; 236 237 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0) 238 value_igi--; 239 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1) 240 value_igi += 0; 241 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2) 242 value_igi++; 243 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2) 244 value_igi += 2; 245 if (value_igi > DM_DIG_FA_UPPER) 246 value_igi = DM_DIG_FA_UPPER; 247 else if (value_igi < DM_DIG_FA_LOWER) 248 value_igi = DM_DIG_FA_LOWER; 249 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 250 value_igi = 0x32; 251 252 dm_digtable->cur_igvalue = value_igi; 253 rtl8723e_dm_write_dig(hw); 254 } 255 256 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw) 257 { 258 struct rtl_priv *rtlpriv = rtl_priv(hw); 259 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 260 261 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) { 262 if ((dm_digtable->back_val - 2) < 263 dm_digtable->back_range_min) 264 dm_digtable->back_val = 265 dm_digtable->back_range_min; 266 else 267 dm_digtable->back_val -= 2; 268 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) { 269 if ((dm_digtable->back_val + 2) > 270 dm_digtable->back_range_max) 271 dm_digtable->back_val = 272 dm_digtable->back_range_max; 273 else 274 dm_digtable->back_val += 2; 275 } 276 277 if ((dm_digtable->rssi_val_min + 10 - dm_digtable->back_val) > 278 dm_digtable->rx_gain_max) 279 dm_digtable->cur_igvalue = dm_digtable->rx_gain_max; 280 else if ((dm_digtable->rssi_val_min + 10 - 281 dm_digtable->back_val) < dm_digtable->rx_gain_min) 282 dm_digtable->cur_igvalue = dm_digtable->rx_gain_min; 283 else 284 dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 - 285 dm_digtable->back_val; 286 287 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 288 "rssi_val_min = %x back_val %x\n", 289 dm_digtable->rssi_val_min, dm_digtable->back_val); 290 291 rtl8723e_dm_write_dig(hw); 292 } 293 294 static void rtl8723e_dm_initial_gain_multi_sta(struct ieee80211_hw *hw) 295 { 296 static u8 binitialized; 297 struct rtl_priv *rtlpriv = rtl_priv(hw); 298 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 299 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 300 long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb; 301 bool multi_sta = false; 302 303 if (mac->opmode == NL80211_IFTYPE_ADHOC) 304 multi_sta = true; 305 306 if (!multi_sta || (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) { 307 binitialized = false; 308 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 309 return; 310 } else if (!binitialized) { 311 binitialized = true; 312 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 313 dm_digtable->cur_igvalue = 0x20; 314 rtl8723e_dm_write_dig(hw); 315 } 316 317 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 318 if ((rssi_strength < dm_digtable->rssi_lowthresh) && 319 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) { 320 321 if (dm_digtable->dig_ext_port_stage == 322 DIG_EXT_PORT_STAGE_2) { 323 dm_digtable->cur_igvalue = 0x20; 324 rtl8723e_dm_write_dig(hw); 325 } 326 327 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1; 328 } else if (rssi_strength > dm_digtable->rssi_highthresh) { 329 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2; 330 rtl92c_dm_ctrl_initgain_by_fa(hw); 331 } 332 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) { 333 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 334 dm_digtable->cur_igvalue = 0x20; 335 rtl8723e_dm_write_dig(hw); 336 } 337 338 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 339 "curmultista_cstate = %x dig_ext_port_stage %x\n", 340 dm_digtable->curmultista_cstate, 341 dm_digtable->dig_ext_port_stage); 342 } 343 344 static void rtl8723e_dm_initial_gain_sta(struct ieee80211_hw *hw) 345 { 346 struct rtl_priv *rtlpriv = rtl_priv(hw); 347 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 348 349 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 350 "presta_cstate = %x, cursta_cstate = %x\n", 351 dm_digtable->presta_cstate, 352 dm_digtable->cursta_cstate); 353 354 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate || 355 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT || 356 dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 357 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { 358 dm_digtable->rssi_val_min = 359 rtl8723e_dm_initial_gain_min_pwdb(hw); 360 rtl92c_dm_ctrl_initgain_by_rssi(hw); 361 } 362 } else { 363 dm_digtable->rssi_val_min = 0; 364 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 365 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT; 366 dm_digtable->cur_igvalue = 0x20; 367 dm_digtable->pre_igvalue = 0; 368 rtl8723e_dm_write_dig(hw); 369 } 370 } 371 372 static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 373 { 374 struct rtl_priv *rtlpriv = rtl_priv(hw); 375 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 376 377 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 378 dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw); 379 380 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 381 if (dm_digtable->rssi_val_min <= 25) 382 dm_digtable->cur_cck_pd_state = 383 CCK_PD_STAGE_LOWRSSI; 384 else 385 dm_digtable->cur_cck_pd_state = 386 CCK_PD_STAGE_HIGHRSSI; 387 } else { 388 if (dm_digtable->rssi_val_min <= 20) 389 dm_digtable->cur_cck_pd_state = 390 CCK_PD_STAGE_LOWRSSI; 391 else 392 dm_digtable->cur_cck_pd_state = 393 CCK_PD_STAGE_HIGHRSSI; 394 } 395 } else { 396 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; 397 } 398 399 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { 400 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 401 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800) 402 dm_digtable->cur_cck_fa_state = 403 CCK_FA_STAGE_HIGH; 404 else 405 dm_digtable->cur_cck_fa_state = 406 CCK_FA_STAGE_LOW; 407 if (dm_digtable->pre_cck_fa_state != 408 dm_digtable->cur_cck_fa_state) { 409 if (dm_digtable->cur_cck_fa_state == 410 CCK_FA_STAGE_LOW) 411 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 412 0x83); 413 else 414 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 415 0xcd); 416 417 dm_digtable->pre_cck_fa_state = 418 dm_digtable->cur_cck_fa_state; 419 } 420 421 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40); 422 423 } else { 424 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 425 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47); 426 dm_digtable->pre_cck_fa_state = 0; 427 dm_digtable->cur_cck_fa_state = 0; 428 429 } 430 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state; 431 } 432 433 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 434 "CCKPDStage=%x\n", dm_digtable->cur_cck_pd_state); 435 436 } 437 438 static void rtl8723e_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) 439 { 440 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 441 struct rtl_priv *rtlpriv = rtl_priv(hw); 442 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 443 444 if (mac->act_scanning) 445 return; 446 447 if (mac->link_state >= MAC80211_LINKED) 448 dm_digtable->cursta_cstate = DIG_STA_CONNECT; 449 else 450 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT; 451 452 rtl8723e_dm_initial_gain_sta(hw); 453 rtl8723e_dm_initial_gain_multi_sta(hw); 454 rtl8723e_dm_cck_packet_detection_thresh(hw); 455 456 dm_digtable->presta_cstate = dm_digtable->cursta_cstate; 457 458 } 459 460 static void rtl8723e_dm_dig(struct ieee80211_hw *hw) 461 { 462 struct rtl_priv *rtlpriv = rtl_priv(hw); 463 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 464 465 if (!rtlpriv->dm.dm_initialgain_enable) 466 return; 467 if (!dm_digtable->dig_enable_flag) 468 return; 469 470 rtl8723e_dm_ctrl_initgain_by_twoport(hw); 471 472 } 473 474 static void rtl8723e_dm_dynamic_txpower(struct ieee80211_hw *hw) 475 { 476 struct rtl_priv *rtlpriv = rtl_priv(hw); 477 struct rtl_phy *rtlphy = &(rtlpriv->phy); 478 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 479 long undec_sm_pwdb; 480 481 if (!rtlpriv->dm.dynamic_txpower_enable) 482 return; 483 484 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 485 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 486 return; 487 } 488 489 if ((mac->link_state < MAC80211_LINKED) && 490 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 491 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 492 "Not connected to any\n"); 493 494 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 495 496 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 497 return; 498 } 499 500 if (mac->link_state >= MAC80211_LINKED) { 501 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 502 undec_sm_pwdb = 503 rtlpriv->dm.entry_min_undec_sm_pwdb; 504 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 505 "AP Client PWDB = 0x%lx\n", 506 undec_sm_pwdb); 507 } else { 508 undec_sm_pwdb = 509 rtlpriv->dm.undec_sm_pwdb; 510 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 511 "STA Default Port PWDB = 0x%lx\n", 512 undec_sm_pwdb); 513 } 514 } else { 515 undec_sm_pwdb = 516 rtlpriv->dm.entry_min_undec_sm_pwdb; 517 518 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 519 "AP Ext Port PWDB = 0x%lx\n", 520 undec_sm_pwdb); 521 } 522 523 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { 524 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 525 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 526 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); 527 } else if ((undec_sm_pwdb < 528 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && 529 (undec_sm_pwdb >= 530 TX_POWER_NEAR_FIELD_THRESH_LVL1)) { 531 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 532 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 533 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"); 534 } else if (undec_sm_pwdb < 535 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { 536 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 537 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 538 "TXHIGHPWRLEVEL_NORMAL\n"); 539 } 540 541 if (rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl) { 542 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 543 "PHY_SetTxPowerLevel8192S() Channel = %d\n", 544 rtlphy->current_channel); 545 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel); 546 } 547 548 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 549 } 550 551 void rtl8723e_dm_write_dig(struct ieee80211_hw *hw) 552 { 553 struct rtl_priv *rtlpriv = rtl_priv(hw); 554 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 555 556 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 557 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", 558 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, 559 dm_digtable->back_val); 560 561 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) { 562 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, 563 dm_digtable->cur_igvalue); 564 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, 565 dm_digtable->cur_igvalue); 566 567 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue; 568 } 569 } 570 571 static void rtl8723e_dm_pwdb_monitor(struct ieee80211_hw *hw) 572 { 573 } 574 575 static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw) 576 { 577 struct rtl_priv *rtlpriv = rtl_priv(hw); 578 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 579 580 static u64 last_txok_cnt; 581 static u64 last_rxok_cnt; 582 static u32 last_bt_edca_ul; 583 static u32 last_bt_edca_dl; 584 u64 cur_txok_cnt = 0; 585 u64 cur_rxok_cnt = 0; 586 u32 edca_be_ul = 0x5ea42b; 587 u32 edca_be_dl = 0x5ea42b; 588 bool bt_change_edca = false; 589 590 if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) || 591 (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) { 592 rtlpriv->dm.current_turbo_edca = false; 593 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul; 594 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl; 595 } 596 597 if (rtlpriv->btcoexist.bt_edca_ul != 0) { 598 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul; 599 bt_change_edca = true; 600 } 601 602 if (rtlpriv->btcoexist.bt_edca_dl != 0) { 603 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; 604 bt_change_edca = true; 605 } 606 607 if (mac->link_state != MAC80211_LINKED) { 608 rtlpriv->dm.current_turbo_edca = false; 609 return; 610 } 611 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) && 612 (!rtlpriv->dm.disable_framebursting))) { 613 614 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 615 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 616 617 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 618 if (!rtlpriv->dm.is_cur_rdlstate || 619 !rtlpriv->dm.current_turbo_edca) { 620 rtl_write_dword(rtlpriv, 621 REG_EDCA_BE_PARAM, 622 edca_be_dl); 623 rtlpriv->dm.is_cur_rdlstate = true; 624 } 625 } else { 626 if (rtlpriv->dm.is_cur_rdlstate || 627 !rtlpriv->dm.current_turbo_edca) { 628 rtl_write_dword(rtlpriv, 629 REG_EDCA_BE_PARAM, 630 edca_be_ul); 631 rtlpriv->dm.is_cur_rdlstate = false; 632 } 633 } 634 rtlpriv->dm.current_turbo_edca = true; 635 } else { 636 if (rtlpriv->dm.current_turbo_edca) { 637 u8 tmp = AC0_BE; 638 rtlpriv->cfg->ops->set_hw_reg(hw, 639 HW_VAR_AC_PARAM, 640 (u8 *)(&tmp)); 641 rtlpriv->dm.current_turbo_edca = false; 642 } 643 } 644 645 rtlpriv->dm.is_any_nonbepkts = false; 646 last_txok_cnt = rtlpriv->stats.txbytesunicast; 647 last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 648 } 649 650 static void rtl8723e_dm_initialize_txpower_tracking_thermalmeter( 651 struct ieee80211_hw *hw) 652 { 653 struct rtl_priv *rtlpriv = rtl_priv(hw); 654 655 rtlpriv->dm.txpower_tracking = true; 656 rtlpriv->dm.txpower_trackinginit = false; 657 658 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 659 "pMgntInfo->txpower_tracking = %d\n", 660 rtlpriv->dm.txpower_tracking); 661 } 662 663 static void rtl8723e_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) 664 { 665 rtl8723e_dm_initialize_txpower_tracking_thermalmeter(hw); 666 } 667 668 void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw) 669 { 670 return; 671 } 672 673 void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 674 { 675 struct rtl_priv *rtlpriv = rtl_priv(hw); 676 struct rate_adaptive *p_ra = &rtlpriv->ra; 677 678 p_ra->ratr_state = DM_RATR_STA_INIT; 679 p_ra->pre_ratr_state = DM_RATR_STA_INIT; 680 681 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) 682 rtlpriv->dm.useramask = true; 683 else 684 rtlpriv->dm.useramask = false; 685 686 } 687 688 void rtl8723e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw) 689 { 690 struct rtl_priv *rtlpriv = rtl_priv(hw); 691 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 692 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 693 struct rate_adaptive *p_ra = &rtlpriv->ra; 694 u32 low_rssithresh_for_ra, high_rssithresh_for_ra; 695 struct ieee80211_sta *sta = NULL; 696 697 if (is_hal_stop(rtlhal)) { 698 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 699 " driver is going to unload\n"); 700 return; 701 } 702 703 if (!rtlpriv->dm.useramask) { 704 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 705 " driver does not control rate adaptive mask\n"); 706 return; 707 } 708 709 if (mac->link_state == MAC80211_LINKED && 710 mac->opmode == NL80211_IFTYPE_STATION) { 711 switch (p_ra->pre_ratr_state) { 712 case DM_RATR_STA_HIGH: 713 high_rssithresh_for_ra = 50; 714 low_rssithresh_for_ra = 20; 715 break; 716 case DM_RATR_STA_MIDDLE: 717 high_rssithresh_for_ra = 55; 718 low_rssithresh_for_ra = 20; 719 break; 720 case DM_RATR_STA_LOW: 721 high_rssithresh_for_ra = 60; 722 low_rssithresh_for_ra = 25; 723 break; 724 default: 725 high_rssithresh_for_ra = 50; 726 low_rssithresh_for_ra = 20; 727 break; 728 } 729 730 if (rtlpriv->link_info.bcn_rx_inperiod == 0) 731 switch (p_ra->pre_ratr_state) { 732 case DM_RATR_STA_HIGH: 733 default: 734 p_ra->ratr_state = DM_RATR_STA_MIDDLE; 735 break; 736 case DM_RATR_STA_MIDDLE: 737 case DM_RATR_STA_LOW: 738 p_ra->ratr_state = DM_RATR_STA_LOW; 739 break; 740 } 741 else if (rtlpriv->dm.undec_sm_pwdb > high_rssithresh_for_ra) 742 p_ra->ratr_state = DM_RATR_STA_HIGH; 743 else if (rtlpriv->dm.undec_sm_pwdb > low_rssithresh_for_ra) 744 p_ra->ratr_state = DM_RATR_STA_MIDDLE; 745 else 746 p_ra->ratr_state = DM_RATR_STA_LOW; 747 748 if (p_ra->pre_ratr_state != p_ra->ratr_state) { 749 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 750 "RSSI = %ld\n", 751 rtlpriv->dm.undec_sm_pwdb); 752 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 753 "RSSI_LEVEL = %d\n", p_ra->ratr_state); 754 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 755 "PreState = %d, CurState = %d\n", 756 p_ra->pre_ratr_state, p_ra->ratr_state); 757 758 rcu_read_lock(); 759 sta = rtl_find_sta(hw, mac->bssid); 760 if (sta) 761 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 762 p_ra->ratr_state, 763 true); 764 rcu_read_unlock(); 765 766 p_ra->pre_ratr_state = p_ra->ratr_state; 767 } 768 } 769 } 770 771 void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal) 772 { 773 struct rtl_priv *rtlpriv = rtl_priv(hw); 774 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 775 static u8 initialize; 776 static u32 reg_874, reg_c70, reg_85c, reg_a74; 777 778 if (initialize == 0) { 779 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 780 MASKDWORD) & 0x1CC000) >> 14; 781 782 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, 783 MASKDWORD) & BIT(3)) >> 3; 784 785 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 786 MASKDWORD) & 0xFF000000) >> 24; 787 788 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12; 789 790 initialize = 1; 791 } 792 793 if (!bforce_in_normal) { 794 if (dm_pstable->rssi_val_min != 0) { 795 if (dm_pstable->pre_rfstate == RF_NORMAL) { 796 if (dm_pstable->rssi_val_min >= 30) 797 dm_pstable->cur_rfstate = RF_SAVE; 798 else 799 dm_pstable->cur_rfstate = RF_NORMAL; 800 } else { 801 if (dm_pstable->rssi_val_min <= 25) 802 dm_pstable->cur_rfstate = RF_NORMAL; 803 else 804 dm_pstable->cur_rfstate = RF_SAVE; 805 } 806 } else { 807 dm_pstable->cur_rfstate = RF_MAX; 808 } 809 } else { 810 dm_pstable->cur_rfstate = RF_NORMAL; 811 } 812 813 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) { 814 if (dm_pstable->cur_rfstate == RF_SAVE) { 815 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 816 BIT(5), 0x1); 817 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 818 0x1C0000, 0x2); 819 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); 820 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 821 0xFF000000, 0x63); 822 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 823 0xC000, 0x2); 824 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3); 825 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 826 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); 827 } else { 828 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 829 0x1CC000, reg_874); 830 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 831 reg_c70); 832 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, 833 reg_85c); 834 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74); 835 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 836 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 837 BIT(5), 0x0); 838 } 839 840 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate; 841 } 842 } 843 844 static void rtl8723e_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw) 845 { 846 struct rtl_priv *rtlpriv = rtl_priv(hw); 847 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 848 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 849 850 if (((mac->link_state == MAC80211_NOLINK)) && 851 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 852 dm_pstable->rssi_val_min = 0; 853 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 854 "Not connected to any\n"); 855 } 856 857 if (mac->link_state == MAC80211_LINKED) { 858 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 859 dm_pstable->rssi_val_min = 860 rtlpriv->dm.entry_min_undec_sm_pwdb; 861 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 862 "AP Client PWDB = 0x%lx\n", 863 dm_pstable->rssi_val_min); 864 } else { 865 dm_pstable->rssi_val_min = 866 rtlpriv->dm.undec_sm_pwdb; 867 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 868 "STA Default Port PWDB = 0x%lx\n", 869 dm_pstable->rssi_val_min); 870 } 871 } else { 872 dm_pstable->rssi_val_min = 873 rtlpriv->dm.entry_min_undec_sm_pwdb; 874 875 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 876 "AP Ext Port PWDB = 0x%lx\n", 877 dm_pstable->rssi_val_min); 878 } 879 880 rtl8723e_dm_rf_saving(hw, false); 881 } 882 883 void rtl8723e_dm_init(struct ieee80211_hw *hw) 884 { 885 struct rtl_priv *rtlpriv = rtl_priv(hw); 886 887 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 888 rtl_dm_diginit(hw, 0x20); 889 rtl8723_dm_init_dynamic_txpower(hw); 890 rtl8723_dm_init_edca_turbo(hw); 891 rtl8723e_dm_init_rate_adaptive_mask(hw); 892 rtl8723e_dm_initialize_txpower_tracking(hw); 893 rtl8723_dm_init_dynamic_bb_powersaving(hw); 894 } 895 896 void rtl8723e_dm_watchdog(struct ieee80211_hw *hw) 897 { 898 struct rtl_priv *rtlpriv = rtl_priv(hw); 899 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 900 bool fw_current_inpsmode = false; 901 bool fw_ps_awake = true; 902 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 903 (u8 *)(&fw_current_inpsmode)); 904 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, 905 (u8 *)(&fw_ps_awake)); 906 907 if (ppsc->p2p_ps_info.p2p_ps_mode) 908 fw_ps_awake = false; 909 910 spin_lock(&rtlpriv->locks.rf_ps_lock); 911 if ((ppsc->rfpwr_state == ERFON) && 912 ((!fw_current_inpsmode) && fw_ps_awake) && 913 (!ppsc->rfchange_inprogress)) { 914 rtl8723e_dm_pwdb_monitor(hw); 915 rtl8723e_dm_dig(hw); 916 rtl8723e_dm_false_alarm_counter_statistics(hw); 917 rtl8723e_dm_dynamic_bb_powersaving(hw); 918 rtl8723e_dm_dynamic_txpower(hw); 919 rtl8723e_dm_check_txpower_tracking(hw); 920 rtl8723e_dm_refresh_rate_adaptive_mask(hw); 921 rtl8723e_dm_bt_coexist(hw); 922 rtl8723e_dm_check_edca_turbo(hw); 923 } 924 spin_unlock(&rtlpriv->locks.rf_ps_lock); 925 if (rtlpriv->btcoexist.init_set) 926 rtl_write_byte(rtlpriv, 0x76e, 0xc); 927 } 928 929 static void rtl8723e_dm_init_bt_coexist(struct ieee80211_hw *hw) 930 { 931 struct rtl_priv *rtlpriv = rtl_priv(hw); 932 933 rtlpriv->btcoexist.bt_rfreg_origin_1e 934 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff); 935 rtlpriv->btcoexist.bt_rfreg_origin_1f 936 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0); 937 938 rtlpriv->btcoexist.cstate = 0; 939 rtlpriv->btcoexist.previous_state = 0; 940 rtlpriv->btcoexist.cstate_h = 0; 941 rtlpriv->btcoexist.previous_state_h = 0; 942 rtlpriv->btcoexist.lps_counter = 0; 943 944 /* Enable counter statistics */ 945 rtl_write_byte(rtlpriv, 0x76e, 0x4); 946 rtl_write_byte(rtlpriv, 0x778, 0x3); 947 rtl_write_byte(rtlpriv, 0x40, 0x20); 948 949 rtlpriv->btcoexist.init_set = true; 950 } 951 952 void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw) 953 { 954 struct rtl_priv *rtlpriv = rtl_priv(hw); 955 u8 tmp_byte = 0; 956 if (!rtlpriv->btcoexist.bt_coexistence) { 957 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 958 "[DM]{BT], BT not exist!!\n"); 959 return; 960 } 961 962 if (!rtlpriv->btcoexist.init_set) { 963 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 964 "[DM][BT], rtl8723e_dm_bt_coexist()\n"); 965 rtl8723e_dm_init_bt_coexist(hw); 966 } 967 968 tmp_byte = rtl_read_byte(rtlpriv, 0x40); 969 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 970 "[DM][BT], 0x40 is 0x%x\n", tmp_byte); 971 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 972 "[DM][BT], bt_dm_coexist start\n"); 973 rtl8723e_dm_bt_coexist_8723(hw); 974 } 975