xref: /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c (revision dd5b2498d845f925904cb2afabb6ba11bfc317c5)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../base.h"
7 #include "../pci.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "dm.h"
12 #include "fw.h"
13 #include "hw.h"
14 #include "sw.h"
15 #include "trx.h"
16 #include "led.h"
17 
18 #include <linux/module.h>
19 
20 static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
21 {
22 	struct rtl_priv *rtlpriv = rtl_priv(hw);
23 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
24 
25 	/*close ASPM for AMD defaultly */
26 	rtlpci->const_amdpci_aspm = 0;
27 
28 	/* ASPM PS mode.
29 	 * 0 - Disable ASPM,
30 	 * 1 - Enable ASPM without Clock Req,
31 	 * 2 - Enable ASPM with Clock Req,
32 	 * 3 - Alwyas Enable ASPM with Clock Req,
33 	 * 4 - Always Enable ASPM without Clock Req.
34 	 * set defult to RTL8192CE:3 RTL8192E:2
35 	 * */
36 	rtlpci->const_pci_aspm = 2;
37 
38 	/*Setting for PCI-E device */
39 	rtlpci->const_devicepci_aspm_setting = 0x03;
40 
41 	/*Setting for PCI-E bridge */
42 	rtlpci->const_hostpci_aspm_setting = 0x02;
43 
44 	/* In Hw/Sw Radio Off situation.
45 	 * 0 - Default,
46 	 * 1 - From ASPM setting without low Mac Pwr,
47 	 * 2 - From ASPM setting with low Mac Pwr,
48 	 * 3 - Bus D3
49 	 * set default to RTL8192CE:0 RTL8192SE:2
50 	 */
51 	rtlpci->const_hwsw_rfoff_d3 = 2;
52 
53 	/* This setting works for those device with
54 	 * backdoor ASPM setting such as EPHY setting.
55 	 * 0 - Not support ASPM,
56 	 * 1 - Support ASPM,
57 	 * 2 - According to chipset.
58 	 */
59 	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
60 }
61 
62 static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
63 {
64 	struct ieee80211_hw *hw = context;
65 	struct rtl_priv *rtlpriv = rtl_priv(hw);
66 	struct rt_firmware *pfirmware = NULL;
67 	char *fw_name = "rtlwifi/rtl8192sefw.bin";
68 
69 	RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
70 			 "Firmware callback routine entered!\n");
71 	complete(&rtlpriv->firmware_loading_complete);
72 	if (!firmware) {
73 		pr_err("Firmware %s not available\n", fw_name);
74 		rtlpriv->max_fw_size = 0;
75 		return;
76 	}
77 	if (firmware->size > rtlpriv->max_fw_size) {
78 		pr_err("Firmware is too big!\n");
79 		rtlpriv->max_fw_size = 0;
80 		release_firmware(firmware);
81 		return;
82 	}
83 	pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
84 	memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
85 	pfirmware->sz_fw_tmpbufferlen = firmware->size;
86 	release_firmware(firmware);
87 }
88 
89 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
90 {
91 	struct rtl_priv *rtlpriv = rtl_priv(hw);
92 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
93 	int err = 0;
94 	u16 earlyrxthreshold = 7;
95 	char *fw_name = "rtlwifi/rtl8192sefw.bin";
96 
97 	rtlpriv->dm.dm_initialgain_enable = true;
98 	rtlpriv->dm.dm_flag = 0;
99 	rtlpriv->dm.disable_framebursting = false;
100 	rtlpriv->dm.thermalvalue = 0;
101 	rtlpriv->dm.useramask = true;
102 
103 	/* compatible 5G band 91se just 2.4G band & smsp */
104 	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
105 	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
106 	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
107 
108 	rtlpci->transmit_config = 0;
109 
110 	rtlpci->receive_config =
111 			RCR_APPFCS |
112 			RCR_APWRMGT |
113 			/*RCR_ADD3 |*/
114 			RCR_AMF	|
115 			RCR_ADF |
116 			RCR_APP_MIC |
117 			RCR_APP_ICV |
118 			RCR_AICV |
119 			/* Accept ICV error, CRC32 Error */
120 			RCR_ACRC32 |
121 			RCR_AB |
122 			/* Accept Broadcast, Multicast */
123 			RCR_AM	|
124 			/* Accept Physical match */
125 			RCR_APM |
126 			/* Accept Destination Address packets */
127 			/*RCR_AAP |*/
128 			RCR_APP_PHYST_STAFF |
129 			/* Accept PHY status */
130 			RCR_APP_PHYST_RXFF |
131 			(earlyrxthreshold << RCR_FIFO_OFFSET);
132 
133 	rtlpci->irq_mask[0] = (u32)
134 			(IMR_ROK |
135 			IMR_VODOK |
136 			IMR_VIDOK |
137 			IMR_BEDOK |
138 			IMR_BKDOK |
139 			IMR_HCCADOK |
140 			IMR_MGNTDOK |
141 			IMR_COMDOK |
142 			IMR_HIGHDOK |
143 			IMR_BDOK |
144 			IMR_RXCMDOK |
145 			/*IMR_TIMEOUT0 |*/
146 			IMR_RDU |
147 			IMR_RXFOVW	|
148 			IMR_BCNINT
149 			/*| IMR_TXFOVW*/
150 			/*| IMR_TBDOK |
151 			IMR_TBDER*/);
152 
153 	rtlpci->irq_mask[1] = (u32) 0;
154 
155 	rtlpci->shortretry_limit = 0x30;
156 	rtlpci->longretry_limit = 0x30;
157 
158 	rtlpci->first_init = true;
159 
160 	/* for LPS & IPS */
161 	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
162 	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
163 	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
164 	rtlpriv->cfg->mod_params->sw_crypto =
165 		rtlpriv->cfg->mod_params->sw_crypto;
166 	if (!rtlpriv->psc.inactiveps)
167 		pr_info("Power Save off (module option)\n");
168 	if (!rtlpriv->psc.fwctrl_lps)
169 		pr_info("FW Power Save off (module option)\n");
170 	rtlpriv->psc.reg_fwctrl_lps = 3;
171 	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
172 	/* for ASPM, you can close aspm through
173 	 * set const_support_pciaspm = 0 */
174 	rtl92s_init_aspm_vars(hw);
175 
176 	if (rtlpriv->psc.reg_fwctrl_lps == 1)
177 		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
178 	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
179 		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
180 	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
181 		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
182 
183 	/* for firmware buf */
184 	rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
185 	if (!rtlpriv->rtlhal.pfirmware)
186 		return 1;
187 
188 	rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 +
189 			       sizeof(struct fw_hdr);
190 	pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
191 		"Loading firmware %s\n", fw_name);
192 	/* request fw */
193 	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
194 				      rtlpriv->io.dev, GFP_KERNEL, hw,
195 				      rtl92se_fw_cb);
196 	if (err) {
197 		pr_err("Failed to request firmware!\n");
198 		vfree(rtlpriv->rtlhal.pfirmware);
199 		rtlpriv->rtlhal.pfirmware = NULL;
200 		return 1;
201 	}
202 
203 	return err;
204 }
205 
206 static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
207 {
208 	struct rtl_priv *rtlpriv = rtl_priv(hw);
209 
210 	if (rtlpriv->rtlhal.pfirmware) {
211 		vfree(rtlpriv->rtlhal.pfirmware);
212 		rtlpriv->rtlhal.pfirmware = NULL;
213 	}
214 }
215 
216 static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
217 				      u16 index)
218 {
219 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
221 	u8 *entry = (u8 *)(&ring->desc[ring->idx]);
222 	u8 own = (u8)rtl92se_get_desc(hw, entry, true, HW_DESC_OWN);
223 
224 	if (own)
225 		return false;
226 	return true;
227 }
228 
229 static struct rtl_hal_ops rtl8192se_hal_ops = {
230 	.init_sw_vars = rtl92s_init_sw_vars,
231 	.deinit_sw_vars = rtl92s_deinit_sw_vars,
232 	.read_eeprom_info = rtl92se_read_eeprom_info,
233 	.interrupt_recognized = rtl92se_interrupt_recognized,
234 	.hw_init = rtl92se_hw_init,
235 	.hw_disable = rtl92se_card_disable,
236 	.hw_suspend = rtl92se_suspend,
237 	.hw_resume = rtl92se_resume,
238 	.enable_interrupt = rtl92se_enable_interrupt,
239 	.disable_interrupt = rtl92se_disable_interrupt,
240 	.set_network_type = rtl92se_set_network_type,
241 	.set_chk_bssid = rtl92se_set_check_bssid,
242 	.set_qos = rtl92se_set_qos,
243 	.set_bcn_reg = rtl92se_set_beacon_related_registers,
244 	.set_bcn_intv = rtl92se_set_beacon_interval,
245 	.update_interrupt_mask = rtl92se_update_interrupt_mask,
246 	.get_hw_reg = rtl92se_get_hw_reg,
247 	.set_hw_reg = rtl92se_set_hw_reg,
248 	.update_rate_tbl = rtl92se_update_hal_rate_tbl,
249 	.fill_tx_desc = rtl92se_tx_fill_desc,
250 	.fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
251 	.query_rx_desc = rtl92se_rx_query_desc,
252 	.set_channel_access = rtl92se_update_channel_access_setting,
253 	.radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
254 	.set_bw_mode = rtl92s_phy_set_bw_mode,
255 	.switch_channel = rtl92s_phy_sw_chnl,
256 	.dm_watchdog = rtl92s_dm_watchdog,
257 	.scan_operation_backup = rtl92s_phy_scan_operation_backup,
258 	.set_rf_power_state = rtl92s_phy_set_rf_power_state,
259 	.led_control = rtl92se_led_control,
260 	.set_desc = rtl92se_set_desc,
261 	.get_desc = rtl92se_get_desc,
262 	.is_tx_desc_closed = rtl92se_is_tx_desc_closed,
263 	.tx_polling = rtl92se_tx_polling,
264 	.enable_hw_sec = rtl92se_enable_hw_security_config,
265 	.set_key = rtl92se_set_key,
266 	.init_sw_leds = rtl92se_init_sw_leds,
267 	.get_bbreg = rtl92s_phy_query_bb_reg,
268 	.set_bbreg = rtl92s_phy_set_bb_reg,
269 	.get_rfreg = rtl92s_phy_query_rf_reg,
270 	.set_rfreg = rtl92s_phy_set_rf_reg,
271 	.get_btc_status = rtl_btc_status_false,
272 };
273 
274 static struct rtl_mod_params rtl92se_mod_params = {
275 	.sw_crypto = false,
276 	.inactiveps = true,
277 	.swctrl_lps = true,
278 	.fwctrl_lps = false,
279 	.aspm_support = 2,
280 	.debug_level = 0,
281 	.debug_mask = 0,
282 };
283 
284 /* Because memory R/W bursting will cause system hang/crash
285  * for 92se, so we don't read back after every write action */
286 static const struct rtl_hal_cfg rtl92se_hal_cfg = {
287 	.bar_id = 1,
288 	.write_readback = false,
289 	.name = "rtl92s_pci",
290 	.ops = &rtl8192se_hal_ops,
291 	.mod_params = &rtl92se_mod_params,
292 
293 	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
294 	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
295 	.maps[SYS_CLK] = SYS_CLKR,
296 	.maps[MAC_RCR_AM] = RCR_AM,
297 	.maps[MAC_RCR_AB] = RCR_AB,
298 	.maps[MAC_RCR_ACRC32] = RCR_ACRC32,
299 	.maps[MAC_RCR_ACF] = RCR_ACF,
300 	.maps[MAC_RCR_AAP] = RCR_AAP,
301 	.maps[MAC_HIMR] = INTA_MASK,
302 	.maps[MAC_HIMRE] = INTA_MASK + 4,
303 
304 	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
305 	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
306 	.maps[EFUSE_CLK] = REG_EFUSE_CLK,
307 	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
308 	.maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
309 	.maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
310 	.maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
311 	.maps[EFUSE_ANA8M] = EFUSE_ANA8M,
312 	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
313 	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
314 	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
315 	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
316 
317 	.maps[RWCAM] = REG_RWCAM,
318 	.maps[WCAMI] = REG_WCAMI,
319 	.maps[RCAMO] = REG_RCAMO,
320 	.maps[CAMDBG] = REG_CAMDBG,
321 	.maps[SECR] = REG_SECR,
322 	.maps[SEC_CAM_NONE] = CAM_NONE,
323 	.maps[SEC_CAM_WEP40] = CAM_WEP40,
324 	.maps[SEC_CAM_TKIP] = CAM_TKIP,
325 	.maps[SEC_CAM_AES] = CAM_AES,
326 	.maps[SEC_CAM_WEP104] = CAM_WEP104,
327 
328 	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
329 	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
330 	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
331 	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
332 	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
333 	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
334 	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
335 	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
336 	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
337 	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
338 	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
339 	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
340 	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
341 	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
342 	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
343 	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
344 
345 	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
346 	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
347 	.maps[RTL_IMR_BCNINT] = IMR_BCNINT,
348 	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
349 	.maps[RTL_IMR_RDU] = IMR_RDU,
350 	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
351 	.maps[RTL_IMR_BDOK] = IMR_BDOK,
352 	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
353 	.maps[RTL_IMR_TBDER] = IMR_TBDER,
354 	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
355 	.maps[RTL_IMR_COMDOK] = IMR_COMDOK,
356 	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
357 	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
358 	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
359 	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
360 	.maps[RTL_IMR_VODOK] = IMR_VODOK,
361 	.maps[RTL_IMR_ROK] = IMR_ROK,
362 	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
363 
364 	.maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
365 	.maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
366 	.maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
367 	.maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
368 	.maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
369 	.maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
370 	.maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
371 	.maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
372 	.maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
373 	.maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
374 	.maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
375 	.maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
376 
377 	.maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
378 	.maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
379 };
380 
381 static const struct pci_device_id rtl92se_pci_ids[] = {
382 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
383 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
384 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
385 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
386 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
387 	{},
388 };
389 
390 MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
391 
392 MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
393 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
394 MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
395 MODULE_LICENSE("GPL");
396 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
397 MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
398 
399 module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
400 module_param_named(debug_level, rtl92se_mod_params.debug_level, int, 0644);
401 module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);
402 module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
403 module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
404 module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
405 module_param_named(aspm, rtl92se_mod_params.aspm_support, int, 0444);
406 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
407 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
408 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
409 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
410 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
411 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
412 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
413 
414 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
415 
416 static struct pci_driver rtl92se_driver = {
417 	.name = KBUILD_MODNAME,
418 	.id_table = rtl92se_pci_ids,
419 	.probe = rtl_pci_probe,
420 	.remove = rtl_pci_disconnect,
421 	.driver.pm = &rtlwifi_pm_ops,
422 };
423 
424 module_pci_driver(rtl92se_driver);
425