1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../pci.h" 6 #include "../ps.h" 7 #include "../core.h" 8 #include "reg.h" 9 #include "def.h" 10 #include "phy.h" 11 #include "rf.h" 12 #include "dm.h" 13 #include "fw.h" 14 #include "hw.h" 15 #include "table.h" 16 17 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask) 18 { 19 u32 i = ffs(bitmask); 20 21 return i ? i - 1 : 32; 22 } 23 24 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 25 { 26 struct rtl_priv *rtlpriv = rtl_priv(hw); 27 u32 returnvalue = 0, originalvalue, bitshift; 28 29 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 30 regaddr, bitmask); 31 32 originalvalue = rtl_read_dword(rtlpriv, regaddr); 33 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 34 returnvalue = (originalvalue & bitmask) >> bitshift; 35 36 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 37 bitmask, regaddr, originalvalue); 38 39 return returnvalue; 40 41 } 42 43 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 44 u32 data) 45 { 46 struct rtl_priv *rtlpriv = rtl_priv(hw); 47 u32 originalvalue, bitshift; 48 49 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 50 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 51 regaddr, bitmask, data); 52 53 if (bitmask != MASKDWORD) { 54 originalvalue = rtl_read_dword(rtlpriv, regaddr); 55 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 56 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 57 } 58 59 rtl_write_dword(rtlpriv, regaddr, data); 60 61 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 62 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 63 regaddr, bitmask, data); 64 65 } 66 67 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw, 68 enum radio_path rfpath, u32 offset) 69 { 70 71 struct rtl_priv *rtlpriv = rtl_priv(hw); 72 struct rtl_phy *rtlphy = &(rtlpriv->phy); 73 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 74 u32 newoffset; 75 u32 tmplong, tmplong2; 76 u8 rfpi_enable = 0; 77 u32 retvalue = 0; 78 79 offset &= 0x3f; 80 newoffset = offset; 81 82 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 83 84 if (rfpath == RF90_PATH_A) 85 tmplong2 = tmplong; 86 else 87 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 88 89 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) | 90 BLSSI_READEDGE; 91 92 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 93 tmplong & (~BLSSI_READEDGE)); 94 95 mdelay(1); 96 97 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 98 mdelay(1); 99 100 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong | 101 BLSSI_READEDGE); 102 mdelay(1); 103 104 if (rfpath == RF90_PATH_A) 105 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 106 BIT(8)); 107 else if (rfpath == RF90_PATH_B) 108 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 109 BIT(8)); 110 111 if (rfpi_enable) 112 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 113 BLSSI_READBACK_DATA); 114 else 115 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 116 BLSSI_READBACK_DATA); 117 118 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 119 BLSSI_READBACK_DATA); 120 121 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", 122 rfpath, pphyreg->rf_rb, retvalue); 123 124 return retvalue; 125 126 } 127 128 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw, 129 enum radio_path rfpath, u32 offset, 130 u32 data) 131 { 132 struct rtl_priv *rtlpriv = rtl_priv(hw); 133 struct rtl_phy *rtlphy = &(rtlpriv->phy); 134 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 135 u32 data_and_addr = 0; 136 u32 newoffset; 137 138 offset &= 0x3f; 139 newoffset = offset; 140 141 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 142 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 143 144 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 145 rfpath, pphyreg->rf3wire_offset, data_and_addr); 146 } 147 148 149 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 150 u32 regaddr, u32 bitmask) 151 { 152 struct rtl_priv *rtlpriv = rtl_priv(hw); 153 u32 original_value, readback_value, bitshift; 154 155 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 156 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 157 regaddr, rfpath, bitmask); 158 159 spin_lock(&rtlpriv->locks.rf_lock); 160 161 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr); 162 163 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 164 readback_value = (original_value & bitmask) >> bitshift; 165 166 spin_unlock(&rtlpriv->locks.rf_lock); 167 168 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 169 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 170 regaddr, rfpath, bitmask, original_value); 171 172 return readback_value; 173 } 174 175 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 176 u32 regaddr, u32 bitmask, u32 data) 177 { 178 struct rtl_priv *rtlpriv = rtl_priv(hw); 179 struct rtl_phy *rtlphy = &(rtlpriv->phy); 180 u32 original_value, bitshift; 181 182 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1)) 183 return; 184 185 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 186 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 187 regaddr, bitmask, data, rfpath); 188 189 spin_lock(&rtlpriv->locks.rf_lock); 190 191 if (bitmask != RFREG_OFFSET_MASK) { 192 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, 193 regaddr); 194 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 195 data = ((original_value & (~bitmask)) | (data << bitshift)); 196 } 197 198 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data); 199 200 spin_unlock(&rtlpriv->locks.rf_lock); 201 202 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 203 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 204 regaddr, bitmask, data, rfpath); 205 206 } 207 208 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, 209 u8 operation) 210 { 211 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 212 213 if (!is_hal_stop(rtlhal)) { 214 switch (operation) { 215 case SCAN_OPT_BACKUP: 216 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN); 217 break; 218 case SCAN_OPT_RESTORE: 219 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN); 220 break; 221 default: 222 pr_err("Unknown operation\n"); 223 break; 224 } 225 } 226 } 227 228 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw, 229 enum nl80211_channel_type ch_type) 230 { 231 struct rtl_priv *rtlpriv = rtl_priv(hw); 232 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 233 struct rtl_phy *rtlphy = &(rtlpriv->phy); 234 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 235 u8 reg_bw_opmode; 236 237 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 238 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 239 "20MHz" : "40MHz"); 240 241 if (rtlphy->set_bwmode_inprogress) 242 return; 243 if (is_hal_stop(rtlhal)) 244 return; 245 246 rtlphy->set_bwmode_inprogress = true; 247 248 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE); 249 /* dummy read */ 250 rtl_read_byte(rtlpriv, RRSR + 2); 251 252 switch (rtlphy->current_chan_bw) { 253 case HT_CHANNEL_WIDTH_20: 254 reg_bw_opmode |= BW_OPMODE_20MHZ; 255 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 256 break; 257 case HT_CHANNEL_WIDTH_20_40: 258 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 259 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 260 break; 261 default: 262 pr_err("unknown bandwidth: %#X\n", 263 rtlphy->current_chan_bw); 264 break; 265 } 266 267 switch (rtlphy->current_chan_bw) { 268 case HT_CHANNEL_WIDTH_20: 269 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 270 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 271 272 if (rtlhal->version >= VERSION_8192S_BCUT) 273 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58); 274 break; 275 case HT_CHANNEL_WIDTH_20_40: 276 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 277 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 278 279 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 280 (mac->cur_40_prime_sc >> 1)); 281 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 282 283 if (rtlhal->version >= VERSION_8192S_BCUT) 284 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18); 285 break; 286 default: 287 pr_err("unknown bandwidth: %#X\n", 288 rtlphy->current_chan_bw); 289 break; 290 } 291 292 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 293 rtlphy->set_bwmode_inprogress = false; 294 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 295 } 296 297 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 298 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 299 u32 para1, u32 para2, u32 msdelay) 300 { 301 struct swchnlcmd *pcmd; 302 303 if (cmdtable == NULL) { 304 WARN_ONCE(true, "rtl8192se: cmdtable cannot be NULL\n"); 305 return false; 306 } 307 308 if (cmdtableidx >= cmdtablesz) 309 return false; 310 311 pcmd = cmdtable + cmdtableidx; 312 pcmd->cmdid = cmdid; 313 pcmd->para1 = para1; 314 pcmd->para2 = para2; 315 pcmd->msdelay = msdelay; 316 317 return true; 318 } 319 320 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 321 u8 channel, u8 *stage, u8 *step, u32 *delay) 322 { 323 struct rtl_priv *rtlpriv = rtl_priv(hw); 324 struct rtl_phy *rtlphy = &(rtlpriv->phy); 325 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 326 u32 precommoncmdcnt; 327 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 328 u32 postcommoncmdcnt; 329 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 330 u32 rfdependcmdcnt; 331 struct swchnlcmd *currentcmd = NULL; 332 u8 rfpath; 333 u8 num_total_rfpath = rtlphy->num_total_rfpath; 334 335 precommoncmdcnt = 0; 336 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 337 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 338 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 339 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 340 341 postcommoncmdcnt = 0; 342 343 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 344 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 345 346 rfdependcmdcnt = 0; 347 348 WARN_ONCE((channel < 1 || channel > 14), 349 "rtl8192se: invalid channel for Zebra: %d\n", channel); 350 351 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 352 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 353 RF_CHNLBW, channel, 10); 354 355 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 356 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0); 357 358 do { 359 switch (*stage) { 360 case 0: 361 currentcmd = &precommoncmd[*step]; 362 break; 363 case 1: 364 currentcmd = &rfdependcmd[*step]; 365 break; 366 case 2: 367 currentcmd = &postcommoncmd[*step]; 368 break; 369 default: 370 return true; 371 } 372 373 if (currentcmd->cmdid == CMDID_END) { 374 if ((*stage) == 2) { 375 return true; 376 } else { 377 (*stage)++; 378 (*step) = 0; 379 continue; 380 } 381 } 382 383 switch (currentcmd->cmdid) { 384 case CMDID_SET_TXPOWEROWER_LEVEL: 385 rtl92s_phy_set_txpower(hw, channel); 386 break; 387 case CMDID_WRITEPORT_ULONG: 388 rtl_write_dword(rtlpriv, currentcmd->para1, 389 currentcmd->para2); 390 break; 391 case CMDID_WRITEPORT_USHORT: 392 rtl_write_word(rtlpriv, currentcmd->para1, 393 (u16)currentcmd->para2); 394 break; 395 case CMDID_WRITEPORT_UCHAR: 396 rtl_write_byte(rtlpriv, currentcmd->para1, 397 (u8)currentcmd->para2); 398 break; 399 case CMDID_RF_WRITEREG: 400 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 401 rtlphy->rfreg_chnlval[rfpath] = 402 ((rtlphy->rfreg_chnlval[rfpath] & 403 0xfffffc00) | currentcmd->para2); 404 rtl_set_rfreg(hw, (enum radio_path)rfpath, 405 currentcmd->para1, 406 RFREG_OFFSET_MASK, 407 rtlphy->rfreg_chnlval[rfpath]); 408 } 409 break; 410 default: 411 pr_err("switch case %#x not processed\n", 412 currentcmd->cmdid); 413 break; 414 } 415 416 break; 417 } while (true); 418 419 (*delay) = currentcmd->msdelay; 420 (*step)++; 421 return false; 422 } 423 424 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw) 425 { 426 struct rtl_priv *rtlpriv = rtl_priv(hw); 427 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 428 struct rtl_phy *rtlphy = &(rtlpriv->phy); 429 u32 delay; 430 bool ret; 431 432 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n", 433 rtlphy->current_channel); 434 435 if (rtlphy->sw_chnl_inprogress) 436 return 0; 437 438 if (rtlphy->set_bwmode_inprogress) 439 return 0; 440 441 if (is_hal_stop(rtlhal)) 442 return 0; 443 444 rtlphy->sw_chnl_inprogress = true; 445 rtlphy->sw_chnl_stage = 0; 446 rtlphy->sw_chnl_step = 0; 447 448 do { 449 if (!rtlphy->sw_chnl_inprogress) 450 break; 451 452 ret = _rtl92s_phy_sw_chnl_step_by_step(hw, 453 rtlphy->current_channel, 454 &rtlphy->sw_chnl_stage, 455 &rtlphy->sw_chnl_step, &delay); 456 if (!ret) { 457 if (delay > 0) 458 mdelay(delay); 459 else 460 continue; 461 } else { 462 rtlphy->sw_chnl_inprogress = false; 463 } 464 break; 465 } while (true); 466 467 rtlphy->sw_chnl_inprogress = false; 468 469 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 470 471 return 1; 472 } 473 474 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw) 475 { 476 struct rtl_priv *rtlpriv = rtl_priv(hw); 477 u8 u1btmp; 478 479 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 480 u1btmp |= BIT(0); 481 482 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 483 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 484 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 485 rtl_write_word(rtlpriv, CMDR, 0x57FC); 486 udelay(100); 487 488 rtl_write_word(rtlpriv, CMDR, 0x77FC); 489 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 490 udelay(10); 491 492 rtl_write_word(rtlpriv, CMDR, 0x37FC); 493 udelay(10); 494 495 rtl_write_word(rtlpriv, CMDR, 0x77FC); 496 udelay(10); 497 498 rtl_write_word(rtlpriv, CMDR, 0x57FC); 499 500 /* we should chnge GPIO to input mode 501 * this will drop away current about 25mA*/ 502 rtl8192se_gpiobit3_cfg_inputmode(hw); 503 } 504 505 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw, 506 enum rf_pwrstate rfpwr_state) 507 { 508 struct rtl_priv *rtlpriv = rtl_priv(hw); 509 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 510 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 511 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 512 bool bresult = true; 513 u8 i, queue_id; 514 struct rtl8192_tx_ring *ring = NULL; 515 516 if (rfpwr_state == ppsc->rfpwr_state) 517 return false; 518 519 switch (rfpwr_state) { 520 case ERFON:{ 521 if ((ppsc->rfpwr_state == ERFOFF) && 522 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 523 524 bool rtstatus; 525 u32 initializecount = 0; 526 do { 527 initializecount++; 528 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 529 "IPS Set eRf nic enable\n"); 530 rtstatus = rtl_ps_enable_nic(hw); 531 } while (!rtstatus && (initializecount < 10)); 532 533 RT_CLEAR_PS_LEVEL(ppsc, 534 RT_RF_OFF_LEVL_HALT_NIC); 535 } else { 536 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 537 "awake, slept:%d ms state_inap:%x\n", 538 jiffies_to_msecs(jiffies - 539 ppsc->last_sleep_jiffies), 540 rtlpriv->psc.state_inap); 541 ppsc->last_awake_jiffies = jiffies; 542 rtl_write_word(rtlpriv, CMDR, 0x37FC); 543 rtl_write_byte(rtlpriv, TXPAUSE, 0x00); 544 rtl_write_byte(rtlpriv, PHY_CCA, 0x3); 545 } 546 547 if (mac->link_state == MAC80211_LINKED) 548 rtlpriv->cfg->ops->led_control(hw, 549 LED_CTL_LINK); 550 else 551 rtlpriv->cfg->ops->led_control(hw, 552 LED_CTL_NO_LINK); 553 break; 554 } 555 case ERFOFF:{ 556 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 557 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 558 "IPS Set eRf nic disable\n"); 559 rtl_ps_disable_nic(hw); 560 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 561 } else { 562 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 563 rtlpriv->cfg->ops->led_control(hw, 564 LED_CTL_NO_LINK); 565 else 566 rtlpriv->cfg->ops->led_control(hw, 567 LED_CTL_POWER_OFF); 568 } 569 break; 570 } 571 case ERFSLEEP: 572 if (ppsc->rfpwr_state == ERFOFF) 573 return false; 574 575 for (queue_id = 0, i = 0; 576 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 577 ring = &pcipriv->dev.tx_ring[queue_id]; 578 if (skb_queue_len(&ring->queue) == 0 || 579 queue_id == BEACON_QUEUE) { 580 queue_id++; 581 continue; 582 } else { 583 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 584 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n", 585 i + 1, queue_id, 586 skb_queue_len(&ring->queue)); 587 588 udelay(10); 589 i++; 590 } 591 592 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 593 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 594 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 595 MAX_DOZE_WAITING_TIMES_9x, 596 queue_id, 597 skb_queue_len(&ring->queue)); 598 break; 599 } 600 } 601 602 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 603 "Set ERFSLEEP awaked:%d ms\n", 604 jiffies_to_msecs(jiffies - 605 ppsc->last_awake_jiffies)); 606 607 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 608 "sleep awaked:%d ms state_inap:%x\n", 609 jiffies_to_msecs(jiffies - 610 ppsc->last_awake_jiffies), 611 rtlpriv->psc.state_inap); 612 ppsc->last_sleep_jiffies = jiffies; 613 _rtl92se_phy_set_rf_sleep(hw); 614 break; 615 default: 616 pr_err("switch case %#x not processed\n", 617 rfpwr_state); 618 bresult = false; 619 break; 620 } 621 622 if (bresult) 623 ppsc->rfpwr_state = rfpwr_state; 624 625 return bresult; 626 } 627 628 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw, 629 enum radio_path rfpath) 630 { 631 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 632 bool rtstatus = true; 633 u32 tmpval = 0; 634 635 /* If inferiority IC, we have to increase the PA bias current */ 636 if (rtlhal->ic_class != IC_INFERIORITY_A) { 637 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf); 638 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1); 639 } 640 641 return rtstatus; 642 } 643 644 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 645 u32 reg_addr, u32 bitmask, u32 data) 646 { 647 struct rtl_priv *rtlpriv = rtl_priv(hw); 648 struct rtl_phy *rtlphy = &(rtlpriv->phy); 649 int index; 650 651 if (reg_addr == RTXAGC_RATE18_06) 652 index = 0; 653 else if (reg_addr == RTXAGC_RATE54_24) 654 index = 1; 655 else if (reg_addr == RTXAGC_CCK_MCS32) 656 index = 6; 657 else if (reg_addr == RTXAGC_MCS03_MCS00) 658 index = 2; 659 else if (reg_addr == RTXAGC_MCS07_MCS04) 660 index = 3; 661 else if (reg_addr == RTXAGC_MCS11_MCS08) 662 index = 4; 663 else if (reg_addr == RTXAGC_MCS15_MCS12) 664 index = 5; 665 else 666 return; 667 668 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 669 if (index == 5) 670 rtlphy->pwrgroup_cnt++; 671 } 672 673 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw) 674 { 675 struct rtl_priv *rtlpriv = rtl_priv(hw); 676 struct rtl_phy *rtlphy = &(rtlpriv->phy); 677 678 /*RF Interface Sowrtware Control */ 679 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 680 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 681 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 682 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 683 684 /* RF Interface Readback Value */ 685 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 686 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 687 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 688 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 689 690 /* RF Interface Output (and Enable) */ 691 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 692 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 693 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE; 694 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE; 695 696 /* RF Interface (Output and) Enable */ 697 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 698 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 699 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE; 700 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE; 701 702 /* Addr of LSSI. Wirte RF register by driver */ 703 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 704 RFPGA0_XA_LSSIPARAMETER; 705 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 706 RFPGA0_XB_LSSIPARAMETER; 707 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset = 708 RFPGA0_XC_LSSIPARAMETER; 709 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset = 710 RFPGA0_XD_LSSIPARAMETER; 711 712 /* RF parameter */ 713 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 714 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 715 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 716 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 717 718 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 719 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 720 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 721 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 722 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 723 724 /* Tranceiver A~D HSSI Parameter-1 */ 725 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 726 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 727 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1; 728 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1; 729 730 /* Tranceiver A~D HSSI Parameter-2 */ 731 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 732 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 733 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2; 734 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2; 735 736 /* RF switch Control */ 737 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 738 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 739 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 740 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 741 742 /* AGC control 1 */ 743 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 744 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 745 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 746 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 747 748 /* AGC control 2 */ 749 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 750 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 751 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 752 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 753 754 /* RX AFE control 1 */ 755 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 756 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 757 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; 758 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 759 760 /* RX AFE control 1 */ 761 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 762 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 763 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 764 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 765 766 /* Tx AFE control 1 */ 767 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; 768 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; 769 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; 770 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; 771 772 /* Tx AFE control 2 */ 773 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; 774 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; 775 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; 776 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; 777 778 /* Tranceiver LSSI Readback */ 779 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 780 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 781 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 782 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 783 784 /* Tranceiver LSSI Readback PI mode */ 785 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; 786 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; 787 } 788 789 790 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) 791 { 792 int i; 793 u32 *phy_reg_table; 794 u32 *agc_table; 795 u16 phy_reg_len, agc_len; 796 797 agc_len = AGCTAB_ARRAYLENGTH; 798 agc_table = rtl8192seagctab_array; 799 /* Default RF_type: 2T2R */ 800 phy_reg_len = PHY_REG_2T2RARRAYLENGTH; 801 phy_reg_table = rtl8192sephy_reg_2t2rarray; 802 803 if (configtype == BASEBAND_CONFIG_PHY_REG) { 804 for (i = 0; i < phy_reg_len; i = i + 2) { 805 rtl_addr_delay(phy_reg_table[i]); 806 807 /* Add delay for ECS T20 & LG malow platform, */ 808 udelay(1); 809 810 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD, 811 phy_reg_table[i + 1]); 812 } 813 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 814 for (i = 0; i < agc_len; i = i + 2) { 815 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD, 816 agc_table[i + 1]); 817 818 /* Add delay for ECS T20 & LG malow platform */ 819 udelay(1); 820 } 821 } 822 823 return true; 824 } 825 826 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw, 827 u8 configtype) 828 { 829 struct rtl_priv *rtlpriv = rtl_priv(hw); 830 struct rtl_phy *rtlphy = &(rtlpriv->phy); 831 u32 *phy_regarray2xtxr_table; 832 u16 phy_regarray2xtxr_len; 833 int i; 834 835 if (rtlphy->rf_type == RF_1T1R) { 836 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray; 837 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH; 838 } else if (rtlphy->rf_type == RF_1T2R) { 839 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray; 840 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH; 841 } else { 842 return false; 843 } 844 845 if (configtype == BASEBAND_CONFIG_PHY_REG) { 846 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) { 847 rtl_addr_delay(phy_regarray2xtxr_table[i]); 848 849 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i], 850 phy_regarray2xtxr_table[i + 1], 851 phy_regarray2xtxr_table[i + 2]); 852 } 853 } 854 855 return true; 856 } 857 858 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw, 859 u8 configtype) 860 { 861 int i; 862 u32 *phy_table_pg; 863 u16 phy_pg_len; 864 865 phy_pg_len = PHY_REG_ARRAY_PGLENGTH; 866 phy_table_pg = rtl8192sephy_reg_array_pg; 867 868 if (configtype == BASEBAND_CONFIG_PHY_REG) { 869 for (i = 0; i < phy_pg_len; i = i + 3) { 870 rtl_addr_delay(phy_table_pg[i]); 871 872 _rtl92s_store_pwrindex_diffrate_offset(hw, 873 phy_table_pg[i], 874 phy_table_pg[i + 1], 875 phy_table_pg[i + 2]); 876 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i], 877 phy_table_pg[i + 1], 878 phy_table_pg[i + 2]); 879 } 880 } 881 882 return true; 883 } 884 885 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw) 886 { 887 struct rtl_priv *rtlpriv = rtl_priv(hw); 888 struct rtl_phy *rtlphy = &(rtlpriv->phy); 889 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 890 bool rtstatus = true; 891 892 /* 1. Read PHY_REG.TXT BB INIT!! */ 893 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */ 894 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R || 895 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) { 896 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG); 897 898 if (rtlphy->rf_type != RF_2T2R && 899 rtlphy->rf_type != RF_2T2R_GREEN) 900 /* so we should reconfig BB reg with the right 901 * PHY parameters. */ 902 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw, 903 BASEBAND_CONFIG_PHY_REG); 904 } else { 905 rtstatus = false; 906 } 907 908 if (!rtstatus) { 909 pr_err("Write BB Reg Fail!!\n"); 910 goto phy_bb8190_config_parafile_fail; 911 } 912 913 /* 2. If EEPROM or EFUSE autoload OK, We must config by 914 * PHY_REG_PG.txt */ 915 if (rtlefuse->autoload_failflag == false) { 916 rtlphy->pwrgroup_cnt = 0; 917 918 rtstatus = _rtl92s_phy_config_bb_with_pg(hw, 919 BASEBAND_CONFIG_PHY_REG); 920 } 921 if (!rtstatus) { 922 pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n"); 923 goto phy_bb8190_config_parafile_fail; 924 } 925 926 /* 3. BB AGC table Initialization */ 927 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); 928 929 if (!rtstatus) { 930 pr_err("%s(): AGC Table Fail\n", __func__); 931 goto phy_bb8190_config_parafile_fail; 932 } 933 934 /* Check if the CCK HighPower is turned ON. */ 935 /* This is used to calculate PWDB. */ 936 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw, 937 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 938 939 phy_bb8190_config_parafile_fail: 940 return rtstatus; 941 } 942 943 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) 944 { 945 struct rtl_priv *rtlpriv = rtl_priv(hw); 946 struct rtl_phy *rtlphy = &(rtlpriv->phy); 947 int i; 948 bool rtstatus = true; 949 u32 *radio_a_table; 950 u32 *radio_b_table; 951 u16 radio_a_tblen, radio_b_tblen; 952 953 radio_a_tblen = RADIOA_1T_ARRAYLENGTH; 954 radio_a_table = rtl8192seradioa_1t_array; 955 956 /* Using Green mode array table for RF_2T2R_GREEN */ 957 if (rtlphy->rf_type == RF_2T2R_GREEN) { 958 radio_b_table = rtl8192seradiob_gm_array; 959 radio_b_tblen = RADIOB_GM_ARRAYLENGTH; 960 } else { 961 radio_b_table = rtl8192seradiob_array; 962 radio_b_tblen = RADIOB_ARRAYLENGTH; 963 } 964 965 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 966 rtstatus = true; 967 968 switch (rfpath) { 969 case RF90_PATH_A: 970 for (i = 0; i < radio_a_tblen; i = i + 2) { 971 rtl_rfreg_delay(hw, rfpath, radio_a_table[i], 972 MASK20BITS, radio_a_table[i + 1]); 973 974 } 975 976 /* PA Bias current for inferiority IC */ 977 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath); 978 break; 979 case RF90_PATH_B: 980 for (i = 0; i < radio_b_tblen; i = i + 2) { 981 rtl_rfreg_delay(hw, rfpath, radio_b_table[i], 982 MASK20BITS, radio_b_table[i + 1]); 983 } 984 break; 985 case RF90_PATH_C: 986 ; 987 break; 988 case RF90_PATH_D: 989 ; 990 break; 991 default: 992 break; 993 } 994 995 return rtstatus; 996 } 997 998 999 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw) 1000 { 1001 struct rtl_priv *rtlpriv = rtl_priv(hw); 1002 u32 i; 1003 u32 arraylength; 1004 u32 *ptrarray; 1005 1006 arraylength = MAC_2T_ARRAYLENGTH; 1007 ptrarray = rtl8192semac_2t_array; 1008 1009 for (i = 0; i < arraylength; i = i + 2) 1010 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); 1011 1012 return true; 1013 } 1014 1015 1016 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw) 1017 { 1018 struct rtl_priv *rtlpriv = rtl_priv(hw); 1019 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1020 bool rtstatus; 1021 u8 pathmap, index, rf_num = 0; 1022 u8 path1, path2; 1023 1024 _rtl92s_phy_init_register_definition(hw); 1025 1026 /* Config BB and AGC */ 1027 rtstatus = _rtl92s_phy_bb_config_parafile(hw); 1028 1029 1030 /* Check BB/RF confiuration setting. */ 1031 /* We only need to configure RF which is turned on. */ 1032 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf)); 1033 mdelay(10); 1034 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf)); 1035 pathmap = path1 | path2; 1036 1037 rtlphy->rf_pathmap = pathmap; 1038 for (index = 0; index < 4; index++) { 1039 if ((pathmap >> index) & 0x1) 1040 rf_num++; 1041 } 1042 1043 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) || 1044 (rtlphy->rf_type == RF_1T2R && rf_num != 2) || 1045 (rtlphy->rf_type == RF_2T2R && rf_num != 2) || 1046 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) { 1047 pr_err("RF_Type(%x) does not match RF_Num(%x)!!\n", 1048 rtlphy->rf_type, rf_num); 1049 pr_err("path1 0x%x, path2 0x%x, pathmap 0x%x\n", 1050 path1, path2, pathmap); 1051 } 1052 1053 return rtstatus; 1054 } 1055 1056 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw) 1057 { 1058 struct rtl_priv *rtlpriv = rtl_priv(hw); 1059 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1060 1061 /* Initialize general global value */ 1062 if (rtlphy->rf_type == RF_1T1R) 1063 rtlphy->num_total_rfpath = 1; 1064 else 1065 rtlphy->num_total_rfpath = 2; 1066 1067 /* Config BB and RF */ 1068 return rtl92s_phy_rf6052_config(hw); 1069 } 1070 1071 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 1072 { 1073 struct rtl_priv *rtlpriv = rtl_priv(hw); 1074 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1075 1076 /* read rx initial gain */ 1077 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, 1078 ROFDM0_XAAGCCORE1, MASKBYTE0); 1079 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, 1080 ROFDM0_XBAGCCORE1, MASKBYTE0); 1081 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, 1082 ROFDM0_XCAGCCORE1, MASKBYTE0); 1083 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, 1084 ROFDM0_XDAGCCORE1, MASKBYTE0); 1085 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1086 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 1087 rtlphy->default_initialgain[0], 1088 rtlphy->default_initialgain[1], 1089 rtlphy->default_initialgain[2], 1090 rtlphy->default_initialgain[3]); 1091 1092 /* read framesync */ 1093 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0); 1094 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 1095 MASKDWORD); 1096 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1097 "Default framesync (0x%x) = 0x%x\n", 1098 ROFDM0_RXDETECTOR3, rtlphy->framesync); 1099 1100 } 1101 1102 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 1103 u8 *cckpowerlevel, u8 *ofdmpowerlevel) 1104 { 1105 struct rtl_priv *rtlpriv = rtl_priv(hw); 1106 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1107 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1108 u8 index = (channel - 1); 1109 1110 /* 1. CCK */ 1111 /* RF-A */ 1112 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index]; 1113 /* RF-B */ 1114 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index]; 1115 1116 /* 2. OFDM for 1T or 2T */ 1117 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { 1118 /* Read HT 40 OFDM TX power */ 1119 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index]; 1120 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index]; 1121 } else if (rtlphy->rf_type == RF_2T2R) { 1122 /* Read HT 40 OFDM TX power */ 1123 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index]; 1124 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index]; 1125 } else { 1126 ofdmpowerlevel[0] = 0; 1127 ofdmpowerlevel[1] = 0; 1128 } 1129 } 1130 1131 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw, 1132 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) 1133 { 1134 struct rtl_priv *rtlpriv = rtl_priv(hw); 1135 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1136 1137 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 1138 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 1139 } 1140 1141 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel) 1142 { 1143 struct rtl_priv *rtlpriv = rtl_priv(hw); 1144 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1145 /* [0]:RF-A, [1]:RF-B */ 1146 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 1147 1148 if (!rtlefuse->txpwr_fromeprom) 1149 return; 1150 1151 /* Mainly we use RF-A Tx Power to write the Tx Power registers, 1152 * but the RF-B Tx Power must be calculated by the antenna diff. 1153 * So we have to rewrite Antenna gain offset register here. 1154 * Please refer to BB register 0x80c 1155 * 1. For CCK. 1156 * 2. For OFDM 1T or 2T */ 1157 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0], 1158 &ofdmpowerlevel[0]); 1159 1160 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 1161 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", 1162 channel, cckpowerlevel[0], cckpowerlevel[1], 1163 ofdmpowerlevel[0], ofdmpowerlevel[1]); 1164 1165 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0], 1166 &ofdmpowerlevel[0]); 1167 1168 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]); 1169 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel); 1170 1171 } 1172 1173 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw) 1174 { 1175 struct rtl_priv *rtlpriv = rtl_priv(hw); 1176 u16 pollingcnt = 10000; 1177 u32 tmpvalue; 1178 1179 /* Make sure that CMD IO has be accepted by FW. */ 1180 do { 1181 udelay(10); 1182 1183 tmpvalue = rtl_read_dword(rtlpriv, WFM5); 1184 if (tmpvalue == 0) 1185 break; 1186 } while (--pollingcnt); 1187 1188 if (pollingcnt == 0) 1189 pr_err("Set FW Cmd fail!!\n"); 1190 } 1191 1192 1193 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw) 1194 { 1195 struct rtl_priv *rtlpriv = rtl_priv(hw); 1196 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1197 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1198 u32 input, current_aid = 0; 1199 1200 if (is_hal_stop(rtlhal)) 1201 return; 1202 1203 if (hal_get_firmwareversion(rtlpriv) < 0x34) 1204 goto skip; 1205 /* We re-map RA related CMD IO to combinational ones */ 1206 /* if FW version is v.52 or later. */ 1207 switch (rtlhal->current_fwcmd_io) { 1208 case FW_CMD_RA_REFRESH_N: 1209 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB; 1210 break; 1211 case FW_CMD_RA_REFRESH_BG: 1212 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB; 1213 break; 1214 default: 1215 break; 1216 } 1217 1218 skip: 1219 switch (rtlhal->current_fwcmd_io) { 1220 case FW_CMD_RA_RESET: 1221 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n"); 1222 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1223 rtl92s_phy_chk_fwcmd_iodone(hw); 1224 break; 1225 case FW_CMD_RA_ACTIVE: 1226 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n"); 1227 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1228 rtl92s_phy_chk_fwcmd_iodone(hw); 1229 break; 1230 case FW_CMD_RA_REFRESH_N: 1231 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n"); 1232 input = FW_RA_REFRESH; 1233 rtl_write_dword(rtlpriv, WFM5, input); 1234 rtl92s_phy_chk_fwcmd_iodone(hw); 1235 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK); 1236 rtl92s_phy_chk_fwcmd_iodone(hw); 1237 break; 1238 case FW_CMD_RA_REFRESH_BG: 1239 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, 1240 "FW_CMD_RA_REFRESH_BG\n"); 1241 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1242 rtl92s_phy_chk_fwcmd_iodone(hw); 1243 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK); 1244 rtl92s_phy_chk_fwcmd_iodone(hw); 1245 break; 1246 case FW_CMD_RA_REFRESH_N_COMB: 1247 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, 1248 "FW_CMD_RA_REFRESH_N_COMB\n"); 1249 input = FW_RA_IOT_N_COMB; 1250 rtl_write_dword(rtlpriv, WFM5, input); 1251 rtl92s_phy_chk_fwcmd_iodone(hw); 1252 break; 1253 case FW_CMD_RA_REFRESH_BG_COMB: 1254 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, 1255 "FW_CMD_RA_REFRESH_BG_COMB\n"); 1256 input = FW_RA_IOT_BG_COMB; 1257 rtl_write_dword(rtlpriv, WFM5, input); 1258 rtl92s_phy_chk_fwcmd_iodone(hw); 1259 break; 1260 case FW_CMD_IQK_ENABLE: 1261 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n"); 1262 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE); 1263 rtl92s_phy_chk_fwcmd_iodone(hw); 1264 break; 1265 case FW_CMD_PAUSE_DM_BY_SCAN: 1266 /* Lower initial gain */ 1267 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1268 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1269 /* CCA threshold */ 1270 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1271 break; 1272 case FW_CMD_RESUME_DM_BY_SCAN: 1273 /* CCA threshold */ 1274 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1275 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1276 break; 1277 case FW_CMD_HIGH_PWR_DISABLE: 1278 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) 1279 break; 1280 1281 /* Lower initial gain */ 1282 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1283 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1284 /* CCA threshold */ 1285 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1286 break; 1287 case FW_CMD_HIGH_PWR_ENABLE: 1288 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1289 rtlpriv->dm.dynamic_txpower_enable) 1290 break; 1291 1292 /* CCA threshold */ 1293 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1294 break; 1295 case FW_CMD_LPS_ENTER: 1296 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n"); 1297 current_aid = rtlpriv->mac80211.assoc_id; 1298 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER | 1299 ((current_aid | 0xc000) << 8))); 1300 rtl92s_phy_chk_fwcmd_iodone(hw); 1301 /* FW set TXOP disable here, so disable EDCA 1302 * turbo mode until driver leave LPS */ 1303 break; 1304 case FW_CMD_LPS_LEAVE: 1305 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n"); 1306 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE); 1307 rtl92s_phy_chk_fwcmd_iodone(hw); 1308 break; 1309 case FW_CMD_ADD_A2_ENTRY: 1310 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n"); 1311 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY); 1312 rtl92s_phy_chk_fwcmd_iodone(hw); 1313 break; 1314 case FW_CMD_CTRL_DM_BY_DRIVER: 1315 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1316 "FW_CMD_CTRL_DM_BY_DRIVER\n"); 1317 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER); 1318 rtl92s_phy_chk_fwcmd_iodone(hw); 1319 break; 1320 1321 default: 1322 break; 1323 } 1324 1325 rtl92s_phy_chk_fwcmd_iodone(hw); 1326 1327 /* Clear FW CMD operation flag. */ 1328 rtlhal->set_fwcmd_inprogress = false; 1329 } 1330 1331 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio) 1332 { 1333 struct rtl_priv *rtlpriv = rtl_priv(hw); 1334 struct dig_t *digtable = &rtlpriv->dm_digtable; 1335 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1336 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1337 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv); 1338 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv); 1339 bool postprocessing = false; 1340 1341 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1342 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n", 1343 fw_cmdio, rtlhal->set_fwcmd_inprogress); 1344 1345 do { 1346 /* We re-map to combined FW CMD ones if firmware version */ 1347 /* is v.53 or later. */ 1348 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1349 switch (fw_cmdio) { 1350 case FW_CMD_RA_REFRESH_N: 1351 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB; 1352 break; 1353 case FW_CMD_RA_REFRESH_BG: 1354 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB; 1355 break; 1356 default: 1357 break; 1358 } 1359 } else { 1360 if ((fw_cmdio == FW_CMD_IQK_ENABLE) || 1361 (fw_cmdio == FW_CMD_RA_REFRESH_N) || 1362 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) { 1363 postprocessing = true; 1364 break; 1365 } 1366 } 1367 1368 /* If firmware version is v.62 or later, 1369 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */ 1370 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) { 1371 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER) 1372 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW; 1373 } 1374 1375 1376 /* We shall revise all FW Cmd IO into Reg0x364 1377 * DM map table in the future. */ 1378 switch (fw_cmdio) { 1379 case FW_CMD_RA_INIT: 1380 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n"); 1381 fw_cmdmap |= FW_RA_INIT_CTL; 1382 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1383 /* Clear control flag to sync with FW. */ 1384 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL); 1385 break; 1386 case FW_CMD_DIG_DISABLE: 1387 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1388 "Set DIG disable!!\n"); 1389 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1390 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1391 break; 1392 case FW_CMD_DIG_ENABLE: 1393 case FW_CMD_DIG_RESUME: 1394 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) { 1395 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1396 "Set DIG enable or resume!!\n"); 1397 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL); 1398 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1399 } 1400 break; 1401 case FW_CMD_DIG_HALT: 1402 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1403 "Set DIG halt!!\n"); 1404 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL); 1405 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1406 break; 1407 case FW_CMD_TXPWR_TRACK_THERMAL: { 1408 u8 thermalval = 0; 1409 fw_cmdmap |= FW_PWR_TRK_CTL; 1410 1411 /* Clear FW parameter in terms of thermal parts. */ 1412 fw_param &= FW_PWR_TRK_PARAM_CLR; 1413 1414 thermalval = rtlpriv->dm.thermalvalue; 1415 fw_param |= ((thermalval << 24) | 1416 (rtlefuse->thermalmeter[0] << 16)); 1417 1418 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1419 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n", 1420 fw_cmdmap, fw_param); 1421 1422 FW_CMD_PARA_SET(rtlpriv, fw_param); 1423 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1424 1425 /* Clear control flag to sync with FW. */ 1426 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL); 1427 } 1428 break; 1429 /* The following FW CMDs are only compatible to 1430 * v.53 or later. */ 1431 case FW_CMD_RA_REFRESH_N_COMB: 1432 fw_cmdmap |= FW_RA_N_CTL; 1433 1434 /* Clear RA BG mode control. */ 1435 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL); 1436 1437 /* Clear FW parameter in terms of RA parts. */ 1438 fw_param &= FW_RA_PARAM_CLR; 1439 1440 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1441 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n", 1442 fw_cmdmap, fw_param); 1443 1444 FW_CMD_PARA_SET(rtlpriv, fw_param); 1445 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1446 1447 /* Clear control flag to sync with FW. */ 1448 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL); 1449 break; 1450 case FW_CMD_RA_REFRESH_BG_COMB: 1451 fw_cmdmap |= FW_RA_BG_CTL; 1452 1453 /* Clear RA n-mode control. */ 1454 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL); 1455 /* Clear FW parameter in terms of RA parts. */ 1456 fw_param &= FW_RA_PARAM_CLR; 1457 1458 FW_CMD_PARA_SET(rtlpriv, fw_param); 1459 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1460 1461 /* Clear control flag to sync with FW. */ 1462 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL); 1463 break; 1464 case FW_CMD_IQK_ENABLE: 1465 fw_cmdmap |= FW_IQK_CTL; 1466 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1467 /* Clear control flag to sync with FW. */ 1468 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL); 1469 break; 1470 /* The following FW CMD is compatible to v.62 or later. */ 1471 case FW_CMD_CTRL_DM_BY_DRIVER_NEW: 1472 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL; 1473 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1474 break; 1475 /* The followed FW Cmds needs post-processing later. */ 1476 case FW_CMD_RESUME_DM_BY_SCAN: 1477 fw_cmdmap |= (FW_DIG_ENABLE_CTL | 1478 FW_HIGH_PWR_ENABLE_CTL | 1479 FW_SS_CTL); 1480 1481 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE || 1482 !digtable->dig_enable_flag) 1483 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1484 1485 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1486 rtlpriv->dm.dynamic_txpower_enable) 1487 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1488 1489 if ((digtable->dig_ext_port_stage == 1490 DIG_EXT_PORT_STAGE_0) || 1491 (digtable->dig_ext_port_stage == 1492 DIG_EXT_PORT_STAGE_1)) 1493 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1494 1495 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1496 postprocessing = true; 1497 break; 1498 case FW_CMD_PAUSE_DM_BY_SCAN: 1499 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | 1500 FW_HIGH_PWR_ENABLE_CTL | 1501 FW_SS_CTL); 1502 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1503 postprocessing = true; 1504 break; 1505 case FW_CMD_HIGH_PWR_DISABLE: 1506 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1507 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1508 postprocessing = true; 1509 break; 1510 case FW_CMD_HIGH_PWR_ENABLE: 1511 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) && 1512 !rtlpriv->dm.dynamic_txpower_enable) { 1513 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL | 1514 FW_SS_CTL); 1515 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1516 postprocessing = true; 1517 } 1518 break; 1519 case FW_CMD_DIG_MODE_FA: 1520 fw_cmdmap |= FW_FA_CTL; 1521 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1522 break; 1523 case FW_CMD_DIG_MODE_SS: 1524 fw_cmdmap &= ~FW_FA_CTL; 1525 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1526 break; 1527 case FW_CMD_PAPE_CONTROL: 1528 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1529 "[FW CMD] Set PAPE Control\n"); 1530 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW; 1531 1532 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1533 break; 1534 default: 1535 /* Pass to original FW CMD processing callback 1536 * routine. */ 1537 postprocessing = true; 1538 break; 1539 } 1540 } while (false); 1541 1542 /* We shall post processing these FW CMD if 1543 * variable postprocessing is set. 1544 */ 1545 if (postprocessing && !rtlhal->set_fwcmd_inprogress) { 1546 rtlhal->set_fwcmd_inprogress = true; 1547 /* Update current FW Cmd for callback use. */ 1548 rtlhal->current_fwcmd_io = fw_cmdio; 1549 } else { 1550 return false; 1551 } 1552 1553 _rtl92s_phy_set_fwcmd_io(hw); 1554 return true; 1555 } 1556 1557 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw) 1558 { 1559 struct rtl_priv *rtlpriv = rtl_priv(hw); 1560 u32 delay = 100; 1561 u8 regu1; 1562 1563 regu1 = rtl_read_byte(rtlpriv, 0x554); 1564 while ((regu1 & BIT(5)) && (delay > 0)) { 1565 regu1 = rtl_read_byte(rtlpriv, 0x554); 1566 delay--; 1567 /* We delay only 50us to prevent 1568 * being scheduled out. */ 1569 udelay(50); 1570 } 1571 } 1572 1573 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw) 1574 { 1575 struct rtl_priv *rtlpriv = rtl_priv(hw); 1576 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1577 1578 /* The way to be capable to switch clock request 1579 * when the PG setting does not support clock request. 1580 * This is the backdoor solution to switch clock 1581 * request before ASPM or D3. */ 1582 rtl_write_dword(rtlpriv, 0x540, 0x73c11); 1583 rtl_write_dword(rtlpriv, 0x548, 0x2407c); 1584 1585 /* Switch EPHY parameter!!!! */ 1586 rtl_write_word(rtlpriv, 0x550, 0x1000); 1587 rtl_write_byte(rtlpriv, 0x554, 0x20); 1588 _rtl92s_phy_check_ephy_switchready(hw); 1589 1590 rtl_write_word(rtlpriv, 0x550, 0xa0eb); 1591 rtl_write_byte(rtlpriv, 0x554, 0x3e); 1592 _rtl92s_phy_check_ephy_switchready(hw); 1593 1594 rtl_write_word(rtlpriv, 0x550, 0xff80); 1595 rtl_write_byte(rtlpriv, 0x554, 0x39); 1596 _rtl92s_phy_check_ephy_switchready(hw); 1597 1598 /* Delay L1 enter time */ 1599 if (ppsc->support_aspm && !ppsc->support_backdoor) 1600 rtl_write_byte(rtlpriv, 0x560, 0x40); 1601 else 1602 rtl_write_byte(rtlpriv, 0x560, 0x00); 1603 1604 } 1605 1606 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval) 1607 { 1608 struct rtl_priv *rtlpriv = rtl_priv(hw); 1609 u32 new_bcn_num = 0; 1610 1611 if (hal_get_firmwareversion(rtlpriv) >= 0x33) { 1612 /* Fw v.51 and later. */ 1613 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | 1614 (beaconinterval << 8)); 1615 } else { 1616 new_bcn_num = beaconinterval * 32 - 64; 1617 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num); 1618 rtl_write_dword(rtlpriv, WFM3, 0xB026007C); 1619 } 1620 } 1621