xref: /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../rtl8192d/reg.h"
6 #include "../rtl8192d/def.h"
7 #include "../rtl8192d/phy_common.h"
8 #include "phy.h"
9 #include "rf.h"
10 #include "dm.h"
11 #include "hw.h"
12 
13 bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0)
14 {
15 	struct rtl_priv *rtlpriv = rtl_priv(hw);
16 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
17 	u8 u1btmp;
18 	u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3);
19 	u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0;
20 	u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON;
21 	bool bresult = true; /* true: need to enable BB/RF power */
22 
23 	rtlhal->during_mac0init_radiob = false;
24 	rtlhal->during_mac1init_radioa = false;
25 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "===>\n");
26 	/* MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write. */
27 	u1btmp = rtl_read_byte(rtlpriv, mac_reg);
28 	if (!(u1btmp & mac_on_bit)) {
29 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable BB & RF\n");
30 		/* Enable BB and RF power */
31 		rtl92de_write_dword_dbi(hw, REG_SYS_ISO_CTRL,
32 			rtl92de_read_dword_dbi(hw, REG_SYS_ISO_CTRL, direct) |
33 				BIT(29) | BIT(16) | BIT(17), direct);
34 	} else {
35 		/* We think if MAC1 is ON,then radio_a.txt
36 		 * and radio_b.txt has been load. */
37 		bresult = false;
38 	}
39 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<===\n");
40 	return bresult;
41 
42 }
43 
44 void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0)
45 {
46 	struct rtl_priv *rtlpriv = rtl_priv(hw);
47 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
48 	u8 u1btmp;
49 	u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3);
50 	u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0;
51 	u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON;
52 
53 	rtlhal->during_mac0init_radiob = false;
54 	rtlhal->during_mac1init_radioa = false;
55 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
56 	/* check MAC0 enable or not again now, if
57 	 * enabled, not power down radio A. */
58 	u1btmp = rtl_read_byte(rtlpriv, mac_reg);
59 	if (!(u1btmp & mac_on_bit)) {
60 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "power down\n");
61 		/* power down RF radio A according to YuNan's advice. */
62 		rtl92de_write_dword_dbi(hw, RFPGA0_XA_LSSIPARAMETER,
63 					0x00000000, direct);
64 	}
65 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
66 }
67 
68 bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw)
69 {
70 	struct rtl_priv *rtlpriv = rtl_priv(hw);
71 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
72 	bool rtstatus = true;
73 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
74 	u32 u4_regvalue = 0;
75 	u8 rfpath;
76 	struct bb_reg_def *pphyreg;
77 	bool mac1_initradioa_first = false, mac0_initradiob_first = false;
78 	bool need_pwrdown_radioa = false, need_pwrdown_radiob = false;
79 	bool true_bpath = false;
80 
81 	if (rtlphy->rf_type == RF_1T1R)
82 		rtlphy->num_total_rfpath = 1;
83 	else
84 		rtlphy->num_total_rfpath = 2;
85 
86 	/* Single phy mode: use radio_a radio_b config path_A path_B */
87 	/* seperately by MAC0, and MAC1 needn't configure RF; */
88 	/* Dual PHY mode:MAC0 use radio_a config 1st phy path_A, */
89 	/* MAC1 use radio_b config 2nd PHY path_A. */
90 	/* DMDP,MAC0 on G band,MAC1 on A band. */
91 	if (rtlhal->macphymode == DUALMAC_DUALPHY) {
92 		if (rtlhal->current_bandtype == BAND_ON_2_4G &&
93 		    rtlhal->interfaceindex == 0) {
94 			/* MAC0 needs PHY1 load radio_b.txt.
95 			 * Driver use DBI to write. */
96 			if (rtl92d_phy_enable_anotherphy(hw, true)) {
97 				rtlphy->num_total_rfpath = 2;
98 				mac0_initradiob_first = true;
99 			} else {
100 				/* We think if MAC1 is ON,then radio_a.txt and
101 				 * radio_b.txt has been load. */
102 				return rtstatus;
103 			}
104 		} else if (rtlhal->current_bandtype == BAND_ON_5G &&
105 			   rtlhal->interfaceindex == 1) {
106 			/* MAC1 needs PHY0 load radio_a.txt.
107 			 * Driver use DBI to write. */
108 			if (rtl92d_phy_enable_anotherphy(hw, false)) {
109 				rtlphy->num_total_rfpath = 2;
110 				mac1_initradioa_first = true;
111 			} else {
112 				/* We think if MAC0 is ON,then radio_a.txt and
113 				 * radio_b.txt has been load. */
114 				return rtstatus;
115 			}
116 		} else if (rtlhal->interfaceindex == 1) {
117 			/* MAC0 enabled, only init radia B.   */
118 			true_bpath = true;
119 		}
120 	}
121 
122 	for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
123 		/* Mac1 use PHY0 write */
124 		if (mac1_initradioa_first) {
125 			if (rfpath == RF90_PATH_A) {
126 				rtlhal->during_mac1init_radioa = true;
127 				need_pwrdown_radioa = true;
128 			} else if (rfpath == RF90_PATH_B) {
129 				rtlhal->during_mac1init_radioa = false;
130 				mac1_initradioa_first = false;
131 				rfpath = RF90_PATH_A;
132 				true_bpath = true;
133 				rtlphy->num_total_rfpath = 1;
134 			}
135 		} else if (mac0_initradiob_first) {
136 			/* Mac0 use PHY1 write */
137 			if (rfpath == RF90_PATH_A)
138 				rtlhal->during_mac0init_radiob = false;
139 			if (rfpath == RF90_PATH_B) {
140 				rtlhal->during_mac0init_radiob = true;
141 				mac0_initradiob_first = false;
142 				need_pwrdown_radiob = true;
143 				rfpath = RF90_PATH_A;
144 				true_bpath = true;
145 				rtlphy->num_total_rfpath = 1;
146 			}
147 		}
148 		pphyreg = &rtlphy->phyreg_def[rfpath];
149 		switch (rfpath) {
150 		case RF90_PATH_A:
151 		case RF90_PATH_C:
152 			u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
153 						    BRFSI_RFENV);
154 			break;
155 		case RF90_PATH_B:
156 		case RF90_PATH_D:
157 			u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
158 				BRFSI_RFENV << 16);
159 			break;
160 		}
161 		rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
162 		udelay(1);
163 		rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
164 		udelay(1);
165 		/* Set bit number of Address and Data for RF register */
166 		/* Set 1 to 4 bits for 8255 */
167 		rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
168 			      B3WIREADDRESSLENGTH, 0x0);
169 		udelay(1);
170 		/* Set 0 to 12  bits for 8255 */
171 		rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
172 		udelay(1);
173 		switch (rfpath) {
174 		case RF90_PATH_A:
175 			if (true_bpath)
176 				rtstatus = rtl92d_phy_config_rf_with_headerfile(
177 						hw, radiob_txt,
178 						(enum radio_path)rfpath);
179 			else
180 				rtstatus = rtl92d_phy_config_rf_with_headerfile(
181 					     hw, radioa_txt,
182 					     (enum radio_path)rfpath);
183 			break;
184 		case RF90_PATH_B:
185 			rtstatus =
186 			    rtl92d_phy_config_rf_with_headerfile(hw, radiob_txt,
187 						(enum radio_path) rfpath);
188 			break;
189 		case RF90_PATH_C:
190 			break;
191 		case RF90_PATH_D:
192 			break;
193 		}
194 		switch (rfpath) {
195 		case RF90_PATH_A:
196 		case RF90_PATH_C:
197 			rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV,
198 				      u4_regvalue);
199 			break;
200 		case RF90_PATH_B:
201 		case RF90_PATH_D:
202 			rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
203 				      u4_regvalue);
204 			break;
205 		}
206 		if (!rtstatus) {
207 			rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
208 				"Radio[%d] Fail!!\n", rfpath);
209 			goto phy_rf_cfg_fail;
210 		}
211 
212 	}
213 
214 	/* check MAC0 enable or not again, if enabled,
215 	 * not power down radio A. */
216 	/* check MAC1 enable or not again, if enabled,
217 	 * not power down radio B. */
218 	if (need_pwrdown_radioa)
219 		rtl92d_phy_powerdown_anotherphy(hw, false);
220 	else if (need_pwrdown_radiob)
221 		rtl92d_phy_powerdown_anotherphy(hw, true);
222 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n");
223 	return rtstatus;
224 
225 phy_rf_cfg_fail:
226 	return rtstatus;
227 }
228