1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #ifndef __RTL92CU_TRX_H__ 5 #define __RTL92CU_TRX_H__ 6 7 #define RTL92C_NUM_RX_URBS 8 8 #define RTL92C_NUM_TX_URBS 32 9 10 #define RTL92C_SIZE_MAX_RX_BUFFER 15360 /* 8192 */ 11 #define RX_DRV_INFO_SIZE_UNIT 8 12 13 enum usb_rx_agg_mode { 14 USB_RX_AGG_DISABLE, 15 USB_RX_AGG_DMA, 16 USB_RX_AGG_USB, 17 USB_RX_AGG_DMA_USB 18 }; 19 20 #define TX_SELE_HQ BIT(0) /* High Queue */ 21 #define TX_SELE_LQ BIT(1) /* Low Queue */ 22 #define TX_SELE_NQ BIT(2) /* Normal Queue */ 23 24 #define RTL_USB_TX_AGG_NUM_DESC 5 25 26 #define RTL_USB_RX_AGG_PAGE_NUM 4 27 #define RTL_USB_RX_AGG_PAGE_TIMEOUT 3 28 29 #define RTL_USB_RX_AGG_BLOCK_NUM 5 30 #define RTL_USB_RX_AGG_BLOCK_TIMEOUT 3 31 32 /*======================== rx status =========================================*/ 33 34 struct rx_drv_info_92c { 35 /* 36 * Driver info contain PHY status and other variabel size info 37 * PHY Status content as below 38 */ 39 40 /* DWORD 0 */ 41 u8 gain_trsw[4]; 42 43 /* DWORD 1 */ 44 u8 pwdb_all; 45 u8 cfosho[4]; 46 47 /* DWORD 2 */ 48 u8 cfotail[4]; 49 50 /* DWORD 3 */ 51 s8 rxevm[2]; 52 s8 rxsnr[4]; 53 54 /* DWORD 4 */ 55 u8 pdsnr[2]; 56 57 /* DWORD 5 */ 58 u8 csi_current[2]; 59 u8 csi_target[2]; 60 61 /* DWORD 6 */ 62 u8 sigevm; 63 u8 max_ex_pwr; 64 u8 ex_intf_flag:1; 65 u8 sgi_en:1; 66 u8 rxsc:2; 67 u8 reserve:4; 68 } __packed; 69 70 /* macros to read various fields in RX descriptor */ 71 72 /* DWORD 0 */ 73 static inline u32 get_rx_desc_pkt_len(__le32 *__rxdesc) 74 { 75 return le32_get_bits(*__rxdesc, GENMASK(13, 0)); 76 } 77 78 static inline u32 get_rx_desc_crc32(__le32 *__rxdesc) 79 { 80 return le32_get_bits(*__rxdesc, BIT(14)); 81 } 82 83 static inline u32 get_rx_desc_icv(__le32 *__rxdesc) 84 { 85 return le32_get_bits(*__rxdesc, BIT(15)); 86 } 87 88 static inline u32 get_rx_desc_drvinfo_size(__le32 *__rxdesc) 89 { 90 return le32_get_bits(*__rxdesc, GENMASK(19, 16)); 91 } 92 93 static inline u32 get_rx_desc_shift(__le32 *__rxdesc) 94 { 95 return le32_get_bits(*__rxdesc, GENMASK(25, 24)); 96 } 97 98 static inline u32 get_rx_desc_phy_status(__le32 *__rxdesc) 99 { 100 return le32_get_bits(*__rxdesc, BIT(26)); 101 } 102 103 static inline u32 get_rx_desc_swdec(__le32 *__rxdesc) 104 { 105 return le32_get_bits(*__rxdesc, BIT(27)); 106 } 107 108 109 /* DWORD 1 */ 110 static inline u32 get_rx_desc_paggr(__le32 *__rxdesc) 111 { 112 return le32_get_bits(*(__rxdesc + 1), BIT(14)); 113 } 114 115 static inline u32 get_rx_desc_faggr(__le32 *__rxdesc) 116 { 117 return le32_get_bits(*(__rxdesc + 1), BIT(15)); 118 } 119 120 121 /* DWORD 3 */ 122 static inline u32 get_rx_desc_rx_mcs(__le32 *__rxdesc) 123 { 124 return le32_get_bits(*(__rxdesc + 3), GENMASK(5, 0)); 125 } 126 127 static inline u32 get_rx_desc_rx_ht(__le32 *__rxdesc) 128 { 129 return le32_get_bits(*(__rxdesc + 3), BIT(6)); 130 } 131 132 static inline u32 get_rx_desc_splcp(__le32 *__rxdesc) 133 { 134 return le32_get_bits(*(__rxdesc + 3), BIT(8)); 135 } 136 137 static inline u32 get_rx_desc_bw(__le32 *__rxdesc) 138 { 139 return le32_get_bits(*(__rxdesc + 3), BIT(9)); 140 } 141 142 143 /* DWORD 5 */ 144 static inline u32 get_rx_desc_tsfl(__le32 *__rxdesc) 145 { 146 return le32_to_cpu(*((__rxdesc + 5))); 147 } 148 149 150 /*======================= tx desc ============================================*/ 151 152 /* macros to set various fields in TX descriptor */ 153 154 /* Dword 0 */ 155 static inline void set_tx_desc_pkt_size(__le32 *__txdesc, u32 __value) 156 { 157 le32p_replace_bits(__txdesc, __value, GENMASK(15, 0)); 158 } 159 160 static inline void set_tx_desc_offset(__le32 *__txdesc, u32 __value) 161 { 162 le32p_replace_bits(__txdesc, __value, GENMASK(23, 16)); 163 } 164 165 static inline void set_tx_desc_bmc(__le32 *__txdesc, u32 __value) 166 { 167 le32p_replace_bits(__txdesc, __value, BIT(24)); 168 } 169 170 static inline void set_tx_desc_htc(__le32 *__txdesc, u32 __value) 171 { 172 le32p_replace_bits(__txdesc, __value, BIT(25)); 173 } 174 175 static inline void set_tx_desc_last_seg(__le32 *__txdesc, u32 __value) 176 { 177 le32p_replace_bits(__txdesc, __value, BIT(26)); 178 } 179 180 static inline void set_tx_desc_first_seg(__le32 *__txdesc, u32 __value) 181 { 182 le32p_replace_bits(__txdesc, __value, BIT(27)); 183 } 184 185 static inline void set_tx_desc_linip(__le32 *__txdesc, u32 __value) 186 { 187 le32p_replace_bits(__txdesc, __value, BIT(28)); 188 } 189 190 static inline void set_tx_desc_own(__le32 *__txdesc, u32 __value) 191 { 192 le32p_replace_bits(__txdesc, __value, BIT(31)); 193 } 194 195 196 /* Dword 1 */ 197 static inline void set_tx_desc_macid(__le32 *__txdesc, u32 __value) 198 { 199 le32p_replace_bits((__txdesc + 1), __value, GENMASK(4, 0)); 200 } 201 202 static inline void set_tx_desc_agg_enable(__le32 *__txdesc, u32 __value) 203 { 204 le32p_replace_bits((__txdesc + 1), __value, BIT(5)); 205 } 206 207 static inline void set_tx_desc_agg_break(__le32 *__txdesc, u32 __value) 208 { 209 le32p_replace_bits((__txdesc + 1), __value, BIT(6)); 210 } 211 212 static inline void set_tx_desc_rdg_enable(__le32 *__txdesc, u32 __value) 213 { 214 le32p_replace_bits((__txdesc + 1), __value, BIT(7)); 215 } 216 217 static inline void set_tx_desc_queue_sel(__le32 *__txdesc, u32 __value) 218 { 219 le32p_replace_bits((__txdesc + 1), __value, GENMASK(12, 8)); 220 } 221 222 static inline void set_tx_desc_rate_id(__le32 *__txdesc, u32 __value) 223 { 224 le32p_replace_bits((__txdesc + 1), __value, GENMASK(19, 16)); 225 } 226 227 static inline void set_tx_desc_nav_use_hdr(__le32 *__txdesc, u32 __value) 228 { 229 le32p_replace_bits((__txdesc + 1), __value, BIT(20)); 230 } 231 232 static inline void set_tx_desc_sec_type(__le32 *__txdesc, u32 __value) 233 { 234 le32p_replace_bits((__txdesc + 1), __value, GENMASK(23, 22)); 235 } 236 237 static inline void set_tx_desc_pkt_offset(__le32 *__txdesc, u32 __value) 238 { 239 le32p_replace_bits((__txdesc + 1), __value, GENMASK(30, 26)); 240 } 241 242 243 /* Dword 2 */ 244 static inline void set_tx_desc_more_frag(__le32 *__txdesc, u32 __value) 245 { 246 le32p_replace_bits((__txdesc + 2), __value, BIT(17)); 247 } 248 249 static inline void set_tx_desc_ampdu_density(__le32 *__txdesc, u32 __value) 250 { 251 le32p_replace_bits((__txdesc + 2), __value, GENMASK(22, 20)); 252 } 253 254 255 /* Dword 3 */ 256 static inline void set_tx_desc_seq(__le32 *__txdesc, u32 __value) 257 { 258 le32p_replace_bits((__txdesc + 3), __value, GENMASK(27, 16)); 259 } 260 261 static inline void set_tx_desc_pkt_id(__le32 *__txdesc, u32 __value) 262 { 263 le32p_replace_bits((__txdesc + 3), __value, GENMASK(31, 28)); 264 } 265 266 267 /* Dword 4 */ 268 static inline void set_tx_desc_rts_rate(__le32 *__txdesc, u32 __value) 269 { 270 le32p_replace_bits((__txdesc + 4), __value, GENMASK(4, 0)); 271 } 272 273 static inline void set_tx_desc_qos(__le32 *__txdesc, u32 __value) 274 { 275 le32p_replace_bits((__txdesc + 4), __value, BIT(6)); 276 } 277 278 static inline void set_tx_desc_hwseq_en(__le32 *__txdesc, u32 __value) 279 { 280 le32p_replace_bits((__txdesc + 4), __value, BIT(7)); 281 } 282 283 static inline void set_tx_desc_use_rate(__le32 *__txdesc, u32 __value) 284 { 285 le32p_replace_bits((__txdesc + 4), __value, BIT(8)); 286 } 287 288 static inline void set_tx_desc_disable_fb(__le32 *__txdesc, u32 __value) 289 { 290 le32p_replace_bits((__txdesc + 4), __value, BIT(10)); 291 } 292 293 static inline void set_tx_desc_cts2self(__le32 *__txdesc, u32 __value) 294 { 295 le32p_replace_bits((__txdesc + 4), __value, BIT(11)); 296 } 297 298 static inline void set_tx_desc_rts_enable(__le32 *__txdesc, u32 __value) 299 { 300 le32p_replace_bits((__txdesc + 4), __value, BIT(12)); 301 } 302 303 static inline void set_tx_desc_hw_rts_enable(__le32 *__txdesc, u32 __value) 304 { 305 le32p_replace_bits((__txdesc + 4), __value, BIT(13)); 306 } 307 308 static inline void set_tx_desc_data_sc(__le32 *__txdesc, u32 __value) 309 { 310 le32p_replace_bits((__txdesc + 4), __value, GENMASK(21, 20)); 311 } 312 313 static inline void set_tx_desc_data_bw(__le32 *__txdesc, u32 __value) 314 { 315 le32p_replace_bits((__txdesc + 4), __value, BIT(25)); 316 } 317 318 static inline void set_tx_desc_rts_short(__le32 *__txdesc, u32 __value) 319 { 320 le32p_replace_bits((__txdesc + 4), __value, BIT(26)); 321 } 322 323 static inline void set_tx_desc_rts_bw(__le32 *__txdesc, u32 __value) 324 { 325 le32p_replace_bits((__txdesc + 4), __value, BIT(27)); 326 } 327 328 static inline void set_tx_desc_rts_sc(__le32 *__txdesc, u32 __value) 329 { 330 le32p_replace_bits((__txdesc + 4), __value, GENMASK(29, 28)); 331 } 332 333 static inline void set_tx_desc_rts_stbc(__le32 *__txdesc, u32 __value) 334 { 335 le32p_replace_bits((__txdesc + 4), __value, GENMASK(31, 30)); 336 } 337 338 339 /* Dword 5 */ 340 static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) 341 { 342 le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); 343 } 344 345 static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val) 346 { 347 le32p_replace_bits((__pdesc + 5), __val, BIT(6)); 348 } 349 350 static inline void set_tx_desc_data_rate_fb_limit(__le32 *__txdesc, u32 __value) 351 { 352 le32p_replace_bits((__txdesc + 5), __value, GENMASK(12, 8)); 353 } 354 355 static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__txdesc, u32 __value) 356 { 357 le32p_replace_bits((__txdesc + 5), __value, GENMASK(16, 13)); 358 } 359 360 361 /* Dword 6 */ 362 static inline void set_tx_desc_max_agg_num(__le32 *__txdesc, u32 __value) 363 { 364 le32p_replace_bits((__txdesc + 6), __value, GENMASK(15, 11)); 365 } 366 367 368 /* Dword 7 */ 369 static inline void set_tx_desc_tx_desc_checksum(__le32 *__txdesc, u32 __value) 370 { 371 le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0)); 372 } 373 374 375 int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw); 376 u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index); 377 bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw, 378 struct rtl_stats *stats, 379 struct ieee80211_rx_status *rx_status, 380 u8 *p_desc, struct sk_buff *skb); 381 void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb); 382 void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb); 383 int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb, 384 struct sk_buff *skb); 385 struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *, 386 struct sk_buff_head *); 387 void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw, 388 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 389 u8 *pbd_desc_tx, struct ieee80211_tx_info *info, 390 struct ieee80211_sta *sta, 391 struct sk_buff *skb, 392 u8 queue_index, 393 struct rtl_tcb_desc *tcb_desc); 394 void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, 395 struct sk_buff *skb); 396 397 #endif 398