1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #ifndef __RTL92CU_TRX_H__ 5 #define __RTL92CU_TRX_H__ 6 7 #define RTL92C_NUM_RX_URBS 8 8 #define RTL92C_NUM_TX_URBS 32 9 10 #define RTL92C_SIZE_MAX_RX_BUFFER 15360 /* 8192 */ 11 #define RX_DRV_INFO_SIZE_UNIT 8 12 13 #define RTL_AGG_ON 1 14 15 enum usb_rx_agg_mode { 16 USB_RX_AGG_DISABLE, 17 USB_RX_AGG_DMA, 18 USB_RX_AGG_USB, 19 USB_RX_AGG_DMA_USB 20 }; 21 22 #define TX_SELE_HQ BIT(0) /* High Queue */ 23 #define TX_SELE_LQ BIT(1) /* Low Queue */ 24 #define TX_SELE_NQ BIT(2) /* Normal Queue */ 25 26 #define RTL_USB_TX_AGG_NUM_DESC 5 27 28 #define RTL_USB_RX_AGG_PAGE_NUM 4 29 #define RTL_USB_RX_AGG_PAGE_TIMEOUT 3 30 31 #define RTL_USB_RX_AGG_BLOCK_NUM 5 32 #define RTL_USB_RX_AGG_BLOCK_TIMEOUT 3 33 34 /*======================== rx status =========================================*/ 35 36 struct rx_drv_info_92c { 37 /* 38 * Driver info contain PHY status and other variabel size info 39 * PHY Status content as below 40 */ 41 42 /* DWORD 0 */ 43 u8 gain_trsw[4]; 44 45 /* DWORD 1 */ 46 u8 pwdb_all; 47 u8 cfosho[4]; 48 49 /* DWORD 2 */ 50 u8 cfotail[4]; 51 52 /* DWORD 3 */ 53 s8 rxevm[2]; 54 s8 rxsnr[4]; 55 56 /* DWORD 4 */ 57 u8 pdsnr[2]; 58 59 /* DWORD 5 */ 60 u8 csi_current[2]; 61 u8 csi_target[2]; 62 63 /* DWORD 6 */ 64 u8 sigevm; 65 u8 max_ex_pwr; 66 u8 ex_intf_flag:1; 67 u8 sgi_en:1; 68 u8 rxsc:2; 69 u8 reserve:4; 70 } __packed; 71 72 /* macros to read various fields in RX descriptor */ 73 74 /* DWORD 0 */ 75 static inline u32 get_rx_desc_pkt_len(__le32 *__rxdesc) 76 { 77 return le32_get_bits(*__rxdesc, GENMASK(13, 0)); 78 } 79 80 static inline u32 get_rx_desc_crc32(__le32 *__rxdesc) 81 { 82 return le32_get_bits(*__rxdesc, BIT(14)); 83 } 84 85 static inline u32 get_rx_desc_icv(__le32 *__rxdesc) 86 { 87 return le32_get_bits(*__rxdesc, BIT(15)); 88 } 89 90 static inline u32 get_rx_desc_drvinfo_size(__le32 *__rxdesc) 91 { 92 return le32_get_bits(*__rxdesc, GENMASK(19, 16)); 93 } 94 95 static inline u32 get_rx_desc_shift(__le32 *__rxdesc) 96 { 97 return le32_get_bits(*__rxdesc, GENMASK(25, 24)); 98 } 99 100 static inline u32 get_rx_desc_phy_status(__le32 *__rxdesc) 101 { 102 return le32_get_bits(*__rxdesc, BIT(26)); 103 } 104 105 static inline u32 get_rx_desc_swdec(__le32 *__rxdesc) 106 { 107 return le32_get_bits(*__rxdesc, BIT(27)); 108 } 109 110 111 /* DWORD 1 */ 112 static inline u32 get_rx_desc_paggr(__le32 *__rxdesc) 113 { 114 return le32_get_bits(*(__rxdesc + 1), BIT(14)); 115 } 116 117 static inline u32 get_rx_desc_faggr(__le32 *__rxdesc) 118 { 119 return le32_get_bits(*(__rxdesc + 1), BIT(15)); 120 } 121 122 123 /* DWORD 3 */ 124 static inline u32 get_rx_desc_rx_mcs(__le32 *__rxdesc) 125 { 126 return le32_get_bits(*(__rxdesc + 3), GENMASK(5, 0)); 127 } 128 129 static inline u32 get_rx_desc_rx_ht(__le32 *__rxdesc) 130 { 131 return le32_get_bits(*(__rxdesc + 3), BIT(6)); 132 } 133 134 static inline u32 get_rx_desc_splcp(__le32 *__rxdesc) 135 { 136 return le32_get_bits(*(__rxdesc + 3), BIT(8)); 137 } 138 139 static inline u32 get_rx_desc_bw(__le32 *__rxdesc) 140 { 141 return le32_get_bits(*(__rxdesc + 3), BIT(9)); 142 } 143 144 145 /* DWORD 5 */ 146 static inline u32 get_rx_desc_tsfl(__le32 *__rxdesc) 147 { 148 return le32_to_cpu(*((__rxdesc + 5))); 149 } 150 151 152 /*======================= tx desc ============================================*/ 153 154 /* macros to set various fields in TX descriptor */ 155 156 /* Dword 0 */ 157 static inline void set_tx_desc_pkt_size(__le32 *__txdesc, u32 __value) 158 { 159 le32p_replace_bits(__txdesc, __value, GENMASK(15, 0)); 160 } 161 162 static inline void set_tx_desc_offset(__le32 *__txdesc, u32 __value) 163 { 164 le32p_replace_bits(__txdesc, __value, GENMASK(23, 16)); 165 } 166 167 static inline void set_tx_desc_bmc(__le32 *__txdesc, u32 __value) 168 { 169 le32p_replace_bits(__txdesc, __value, BIT(24)); 170 } 171 172 static inline void set_tx_desc_htc(__le32 *__txdesc, u32 __value) 173 { 174 le32p_replace_bits(__txdesc, __value, BIT(25)); 175 } 176 177 static inline void set_tx_desc_last_seg(__le32 *__txdesc, u32 __value) 178 { 179 le32p_replace_bits(__txdesc, __value, BIT(26)); 180 } 181 182 static inline void set_tx_desc_first_seg(__le32 *__txdesc, u32 __value) 183 { 184 le32p_replace_bits(__txdesc, __value, BIT(27)); 185 } 186 187 static inline void set_tx_desc_linip(__le32 *__txdesc, u32 __value) 188 { 189 le32p_replace_bits(__txdesc, __value, BIT(28)); 190 } 191 192 static inline void set_tx_desc_own(__le32 *__txdesc, u32 __value) 193 { 194 le32p_replace_bits(__txdesc, __value, BIT(31)); 195 } 196 197 198 /* Dword 1 */ 199 static inline void set_tx_desc_macid(__le32 *__txdesc, u32 __value) 200 { 201 le32p_replace_bits((__txdesc + 1), __value, GENMASK(4, 0)); 202 } 203 204 static inline void set_tx_desc_agg_enable(__le32 *__txdesc, u32 __value) 205 { 206 le32p_replace_bits((__txdesc + 1), __value, BIT(5)); 207 } 208 209 static inline void set_tx_desc_agg_break(__le32 *__txdesc, u32 __value) 210 { 211 le32p_replace_bits((__txdesc + 1), __value, BIT(6)); 212 } 213 214 static inline void set_tx_desc_rdg_enable(__le32 *__txdesc, u32 __value) 215 { 216 le32p_replace_bits((__txdesc + 1), __value, BIT(7)); 217 } 218 219 static inline void set_tx_desc_queue_sel(__le32 *__txdesc, u32 __value) 220 { 221 le32p_replace_bits((__txdesc + 1), __value, GENMASK(12, 8)); 222 } 223 224 static inline void set_tx_desc_rate_id(__le32 *__txdesc, u32 __value) 225 { 226 le32p_replace_bits((__txdesc + 1), __value, GENMASK(19, 16)); 227 } 228 229 static inline void set_tx_desc_nav_use_hdr(__le32 *__txdesc, u32 __value) 230 { 231 le32p_replace_bits((__txdesc + 1), __value, BIT(20)); 232 } 233 234 static inline void set_tx_desc_sec_type(__le32 *__txdesc, u32 __value) 235 { 236 le32p_replace_bits((__txdesc + 1), __value, GENMASK(23, 22)); 237 } 238 239 static inline void set_tx_desc_pkt_offset(__le32 *__txdesc, u32 __value) 240 { 241 le32p_replace_bits((__txdesc + 1), __value, GENMASK(30, 26)); 242 } 243 244 245 /* Dword 2 */ 246 static inline void set_tx_desc_more_frag(__le32 *__txdesc, u32 __value) 247 { 248 le32p_replace_bits((__txdesc + 2), __value, BIT(17)); 249 } 250 251 static inline void set_tx_desc_ampdu_density(__le32 *__txdesc, u32 __value) 252 { 253 le32p_replace_bits((__txdesc + 2), __value, GENMASK(22, 20)); 254 } 255 256 257 /* Dword 3 */ 258 static inline void set_tx_desc_seq(__le32 *__txdesc, u32 __value) 259 { 260 le32p_replace_bits((__txdesc + 3), __value, GENMASK(27, 16)); 261 } 262 263 static inline void set_tx_desc_pkt_id(__le32 *__txdesc, u32 __value) 264 { 265 le32p_replace_bits((__txdesc + 3), __value, GENMASK(31, 28)); 266 } 267 268 269 /* Dword 4 */ 270 static inline void set_tx_desc_rts_rate(__le32 *__txdesc, u32 __value) 271 { 272 le32p_replace_bits((__txdesc + 4), __value, GENMASK(4, 0)); 273 } 274 275 static inline void set_tx_desc_qos(__le32 *__txdesc, u32 __value) 276 { 277 le32p_replace_bits((__txdesc + 4), __value, BIT(6)); 278 } 279 280 static inline void set_tx_desc_hwseq_en(__le32 *__txdesc, u32 __value) 281 { 282 le32p_replace_bits((__txdesc + 4), __value, BIT(7)); 283 } 284 285 static inline void set_tx_desc_use_rate(__le32 *__txdesc, u32 __value) 286 { 287 le32p_replace_bits((__txdesc + 4), __value, BIT(8)); 288 } 289 290 static inline void set_tx_desc_disable_fb(__le32 *__txdesc, u32 __value) 291 { 292 le32p_replace_bits((__txdesc + 4), __value, BIT(10)); 293 } 294 295 static inline void set_tx_desc_cts2self(__le32 *__txdesc, u32 __value) 296 { 297 le32p_replace_bits((__txdesc + 4), __value, BIT(11)); 298 } 299 300 static inline void set_tx_desc_rts_enable(__le32 *__txdesc, u32 __value) 301 { 302 le32p_replace_bits((__txdesc + 4), __value, BIT(12)); 303 } 304 305 static inline void set_tx_desc_hw_rts_enable(__le32 *__txdesc, u32 __value) 306 { 307 le32p_replace_bits((__txdesc + 4), __value, BIT(13)); 308 } 309 310 static inline void set_tx_desc_data_sc(__le32 *__txdesc, u32 __value) 311 { 312 le32p_replace_bits((__txdesc + 4), __value, GENMASK(21, 20)); 313 } 314 315 static inline void set_tx_desc_data_bw(__le32 *__txdesc, u32 __value) 316 { 317 le32p_replace_bits((__txdesc + 4), __value, BIT(25)); 318 } 319 320 static inline void set_tx_desc_rts_short(__le32 *__txdesc, u32 __value) 321 { 322 le32p_replace_bits((__txdesc + 4), __value, BIT(26)); 323 } 324 325 static inline void set_tx_desc_rts_bw(__le32 *__txdesc, u32 __value) 326 { 327 le32p_replace_bits((__txdesc + 4), __value, BIT(27)); 328 } 329 330 static inline void set_tx_desc_rts_sc(__le32 *__txdesc, u32 __value) 331 { 332 le32p_replace_bits((__txdesc + 4), __value, GENMASK(29, 28)); 333 } 334 335 static inline void set_tx_desc_rts_stbc(__le32 *__txdesc, u32 __value) 336 { 337 le32p_replace_bits((__txdesc + 4), __value, GENMASK(31, 30)); 338 } 339 340 341 /* Dword 5 */ 342 static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) 343 { 344 le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); 345 } 346 347 static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val) 348 { 349 le32p_replace_bits((__pdesc + 5), __val, BIT(6)); 350 } 351 352 static inline void set_tx_desc_data_rate_fb_limit(__le32 *__txdesc, u32 __value) 353 { 354 le32p_replace_bits((__txdesc + 5), __value, GENMASK(12, 8)); 355 } 356 357 static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__txdesc, u32 __value) 358 { 359 le32p_replace_bits((__txdesc + 5), __value, GENMASK(16, 13)); 360 } 361 362 363 /* Dword 6 */ 364 static inline void set_tx_desc_max_agg_num(__le32 *__txdesc, u32 __value) 365 { 366 le32p_replace_bits((__txdesc + 6), __value, GENMASK(15, 11)); 367 } 368 369 370 /* Dword 7 */ 371 static inline void set_tx_desc_tx_desc_checksum(__le32 *__txdesc, u32 __value) 372 { 373 le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0)); 374 } 375 376 377 int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw); 378 u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index); 379 bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw, 380 struct rtl_stats *stats, 381 struct ieee80211_rx_status *rx_status, 382 u8 *p_desc, struct sk_buff *skb); 383 void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb); 384 void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb); 385 int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb, 386 struct sk_buff *skb); 387 struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *, 388 struct sk_buff_head *); 389 void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw, 390 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 391 u8 *pbd_desc_tx, struct ieee80211_tx_info *info, 392 struct ieee80211_sta *sta, 393 struct sk_buff *skb, 394 u8 queue_index, 395 struct rtl_tcb_desc *tcb_desc); 396 void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, 397 struct sk_buff *skb); 398 399 #endif 400