1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../pci.h" 6 #include "../usb.h" 7 #include "../ps.h" 8 #include "../cam.h" 9 #include "../stats.h" 10 #include "reg.h" 11 #include "def.h" 12 #include "phy.h" 13 #include "rf.h" 14 #include "dm.h" 15 #include "mac.h" 16 #include "trx.h" 17 #include "../rtl8192c/fw_common.h" 18 19 #include <linux/module.h> 20 21 /* macro to shorten lines */ 22 23 #define LINK_Q ui_link_quality 24 #define RX_EVM rx_evm_percentage 25 #define RX_SIGQ rx_mimo_sig_qual 26 27 void rtl92c_read_chip_version(struct ieee80211_hw *hw) 28 { 29 struct rtl_priv *rtlpriv = rtl_priv(hw); 30 struct rtl_phy *rtlphy = &(rtlpriv->phy); 31 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 32 enum version_8192c chip_version = VERSION_UNKNOWN; 33 const char *versionid; 34 u32 value32; 35 36 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 37 if (value32 & TRP_VAUX_EN) { 38 chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C : 39 VERSION_TEST_CHIP_88C; 40 } else { 41 /* Normal mass production chip. */ 42 chip_version = NORMAL_CHIP; 43 chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0); 44 chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); 45 if (IS_VENDOR_UMC(chip_version)) 46 chip_version |= ((value32 & CHIP_VER_RTL_MASK) ? 47 CHIP_VENDOR_UMC_B_CUT : 0); 48 if (IS_92C_SERIAL(chip_version)) { 49 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 50 chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) == 51 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0); 52 } 53 } 54 rtlhal->version = (enum version_8192c)chip_version; 55 pr_info("Chip version 0x%x\n", chip_version); 56 switch (rtlhal->version) { 57 case VERSION_NORMAL_TSMC_CHIP_92C_1T2R: 58 versionid = "NORMAL_B_CHIP_92C"; 59 break; 60 case VERSION_NORMAL_TSMC_CHIP_92C: 61 versionid = "NORMAL_TSMC_CHIP_92C"; 62 break; 63 case VERSION_NORMAL_TSMC_CHIP_88C: 64 versionid = "NORMAL_TSMC_CHIP_88C"; 65 break; 66 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 67 versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT"; 68 break; 69 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 70 versionid = "NORMAL_UMC_CHIP_92C_A_CUT"; 71 break; 72 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 73 versionid = "NORMAL_UMC_CHIP_88C_A_CUT"; 74 break; 75 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 76 versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT"; 77 break; 78 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 79 versionid = "NORMAL_UMC_CHIP_92C_B_CUT"; 80 break; 81 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 82 versionid = "NORMAL_UMC_CHIP_88C_B_CUT"; 83 break; 84 case VERSION_TEST_CHIP_92C: 85 versionid = "TEST_CHIP_92C"; 86 break; 87 case VERSION_TEST_CHIP_88C: 88 versionid = "TEST_CHIP_88C"; 89 break; 90 default: 91 versionid = "UNKNOWN"; 92 break; 93 } 94 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 95 "Chip Version ID: %s\n", versionid); 96 97 if (IS_92C_SERIAL(rtlhal->version)) 98 rtlphy->rf_type = 99 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R; 100 else 101 rtlphy->rf_type = RF_1T1R; 102 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 103 "Chip RF Type: %s\n", 104 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 105 if (get_rf_type(rtlphy) == RF_1T1R) 106 rtlpriv->dm.rfpath_rxenable[0] = true; 107 else 108 rtlpriv->dm.rfpath_rxenable[0] = 109 rtlpriv->dm.rfpath_rxenable[1] = true; 110 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 111 rtlhal->version); 112 } 113 114 /** 115 * rtl92c_llt_write - LLT table write access 116 * @hw: Pointer to the ieee80211_hw structure. 117 * @address: LLT logical address. 118 * @data: LLT data content 119 * 120 * Realtek hardware access function. 121 * 122 */ 123 bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 124 { 125 struct rtl_priv *rtlpriv = rtl_priv(hw); 126 bool status = true; 127 long count = 0; 128 u32 value = _LLT_INIT_ADDR(address) | 129 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 130 131 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 132 do { 133 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 134 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 135 break; 136 if (count > POLLING_LLT_THRESHOLD) { 137 pr_err("Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n", 138 address, _LLT_OP_VALUE(value)); 139 status = false; 140 break; 141 } 142 } while (++count); 143 return status; 144 } 145 146 /** 147 * rtl92c_init_llt_table - Init LLT table 148 * @hw: Pointer to the ieee80211_hw structure. 149 * @boundary: Page boundary. 150 * 151 * Realtek hardware access function. 152 */ 153 bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 154 { 155 bool rst = true; 156 u32 i; 157 158 for (i = 0; i < (boundary - 1); i++) { 159 rst = rtl92c_llt_write(hw, i , i + 1); 160 if (!rst) { 161 pr_err("===> %s #1 fail\n", __func__); 162 return rst; 163 } 164 } 165 /* end of list */ 166 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF); 167 if (!rst) { 168 pr_err("===> %s #2 fail\n", __func__); 169 return rst; 170 } 171 /* Make the other pages as ring buffer 172 * This ring buffer is used as beacon buffer if we config this MAC 173 * as two MAC transfer. 174 * Otherwise used as local loopback buffer. 175 */ 176 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) { 177 rst = rtl92c_llt_write(hw, i, (i + 1)); 178 if (!rst) { 179 pr_err("===> %s #3 fail\n", __func__); 180 return rst; 181 } 182 } 183 /* Let last entry point to the start entry of ring buffer */ 184 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary); 185 if (!rst) { 186 pr_err("===> %s #4 fail\n", __func__); 187 return rst; 188 } 189 return rst; 190 } 191 192 void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index, 193 u8 *p_macaddr, bool is_group, u8 enc_algo, 194 bool is_wepkey, bool clear_all) 195 { 196 struct rtl_priv *rtlpriv = rtl_priv(hw); 197 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 198 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 199 u8 *macaddr = p_macaddr; 200 u32 entry_id = 0; 201 bool is_pairwise = false; 202 static u8 cam_const_addr[4][6] = { 203 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 204 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 205 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 206 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 207 }; 208 static u8 cam_const_broad[] = { 209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 210 }; 211 212 if (clear_all) { 213 u8 idx = 0; 214 u8 cam_offset = 0; 215 u8 clear_number = 5; 216 217 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 218 for (idx = 0; idx < clear_number; idx++) { 219 rtl_cam_mark_invalid(hw, cam_offset + idx); 220 rtl_cam_empty_entry(hw, cam_offset + idx); 221 if (idx < 5) { 222 memset(rtlpriv->sec.key_buf[idx], 0, 223 MAX_KEY_LEN); 224 rtlpriv->sec.key_len[idx] = 0; 225 } 226 } 227 } else { 228 switch (enc_algo) { 229 case WEP40_ENCRYPTION: 230 enc_algo = CAM_WEP40; 231 break; 232 case WEP104_ENCRYPTION: 233 enc_algo = CAM_WEP104; 234 break; 235 case TKIP_ENCRYPTION: 236 enc_algo = CAM_TKIP; 237 break; 238 case AESCCMP_ENCRYPTION: 239 enc_algo = CAM_AES; 240 break; 241 default: 242 pr_err("illegal switch case\n"); 243 enc_algo = CAM_TKIP; 244 break; 245 } 246 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 247 macaddr = cam_const_addr[key_index]; 248 entry_id = key_index; 249 } else { 250 if (is_group) { 251 macaddr = cam_const_broad; 252 entry_id = key_index; 253 } else { 254 if (mac->opmode == NL80211_IFTYPE_AP || 255 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 256 entry_id = rtl_cam_get_free_entry(hw, 257 p_macaddr); 258 if (entry_id >= TOTAL_CAM_ENTRY) { 259 pr_err("Can not find free hw security cam entry\n"); 260 return; 261 } 262 } else { 263 entry_id = CAM_PAIRWISE_KEY_POSITION; 264 } 265 266 key_index = PAIRWISE_KEYIDX; 267 is_pairwise = true; 268 } 269 } 270 if (rtlpriv->sec.key_len[key_index] == 0) { 271 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 272 "delete one entry\n"); 273 if (mac->opmode == NL80211_IFTYPE_AP || 274 mac->opmode == NL80211_IFTYPE_MESH_POINT) 275 rtl_cam_del_entry(hw, p_macaddr); 276 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 277 } else { 278 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, 279 "The insert KEY length is %d\n", 280 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 281 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, 282 "The insert KEY is %x %x\n", 283 rtlpriv->sec.key_buf[0][0], 284 rtlpriv->sec.key_buf[0][1]); 285 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 286 "add one entry\n"); 287 if (is_pairwise) { 288 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 289 "Pairwise Key content", 290 rtlpriv->sec.pairwise_key, 291 rtlpriv->sec. 292 key_len[PAIRWISE_KEYIDX]); 293 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 294 "set Pairwise key\n"); 295 296 rtl_cam_add_one_entry(hw, macaddr, key_index, 297 entry_id, enc_algo, 298 CAM_CONFIG_NO_USEDK, 299 rtlpriv->sec. 300 key_buf[key_index]); 301 } else { 302 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 303 "set group key\n"); 304 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 305 rtl_cam_add_one_entry(hw, 306 rtlefuse->dev_addr, 307 PAIRWISE_KEYIDX, 308 CAM_PAIRWISE_KEY_POSITION, 309 enc_algo, 310 CAM_CONFIG_NO_USEDK, 311 rtlpriv->sec.key_buf 312 [entry_id]); 313 } 314 rtl_cam_add_one_entry(hw, macaddr, key_index, 315 entry_id, enc_algo, 316 CAM_CONFIG_NO_USEDK, 317 rtlpriv->sec.key_buf[entry_id]); 318 } 319 } 320 } 321 } 322 323 u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw) 324 { 325 struct rtl_priv *rtlpriv = rtl_priv(hw); 326 327 return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS); 328 } 329 330 void rtl92c_enable_interrupt(struct ieee80211_hw *hw) 331 { 332 struct rtl_priv *rtlpriv = rtl_priv(hw); 333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 334 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 335 336 if (IS_HARDWARE_TYPE_8192CE(rtlpriv)) { 337 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 338 0xFFFFFFFF); 339 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 340 0xFFFFFFFF); 341 } else { 342 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] & 343 0xFFFFFFFF); 344 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] & 345 0xFFFFFFFF); 346 } 347 } 348 349 void rtl92c_init_interrupt(struct ieee80211_hw *hw) 350 { 351 rtl92c_enable_interrupt(hw); 352 } 353 354 void rtl92c_disable_interrupt(struct ieee80211_hw *hw) 355 { 356 struct rtl_priv *rtlpriv = rtl_priv(hw); 357 358 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 359 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 360 } 361 362 void rtl92c_set_qos(struct ieee80211_hw *hw, int aci) 363 { 364 struct rtl_priv *rtlpriv = rtl_priv(hw); 365 366 rtl92c_dm_init_edca_turbo(hw); 367 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci); 368 } 369 370 void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size) 371 { 372 struct rtl_priv *rtlpriv = rtl_priv(hw); 373 374 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size); 375 } 376 377 int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 378 { 379 u8 value; 380 struct rtl_priv *rtlpriv = rtl_priv(hw); 381 382 switch (type) { 383 case NL80211_IFTYPE_UNSPECIFIED: 384 value = NT_NO_LINK; 385 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 386 "Set Network type to NO LINK!\n"); 387 break; 388 case NL80211_IFTYPE_ADHOC: 389 value = NT_LINK_AD_HOC; 390 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 391 "Set Network type to Ad Hoc!\n"); 392 break; 393 case NL80211_IFTYPE_STATION: 394 value = NT_LINK_AP; 395 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 396 "Set Network type to STA!\n"); 397 break; 398 case NL80211_IFTYPE_AP: 399 value = NT_AS_AP; 400 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 401 "Set Network type to AP!\n"); 402 break; 403 default: 404 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 405 "Network type %d not supported!\n", type); 406 return -EOPNOTSUPP; 407 } 408 rtl_write_byte(rtlpriv, MSR, value); 409 return 0; 410 } 411 412 void rtl92c_init_network_type(struct ieee80211_hw *hw) 413 { 414 rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED); 415 } 416 417 void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw) 418 { 419 u16 value16; 420 u32 value32; 421 struct rtl_priv *rtlpriv = rtl_priv(hw); 422 423 /* Response Rate Set */ 424 value32 = rtl_read_dword(rtlpriv, REG_RRSR); 425 value32 &= ~RATE_BITMAP_ALL; 426 value32 |= RATE_RRSR_CCK_ONLY_1M; 427 rtl_write_dword(rtlpriv, REG_RRSR, value32); 428 /* SIFS (used in NAV) */ 429 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); 430 rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16); 431 /* Retry Limit */ 432 value16 = _LRL(0x30) | _SRL(0x30); 433 rtl_write_dword(rtlpriv, REG_RL, value16); 434 } 435 436 void rtl92c_init_rate_fallback(struct ieee80211_hw *hw) 437 { 438 struct rtl_priv *rtlpriv = rtl_priv(hw); 439 440 /* Set Data Auto Rate Fallback Retry Count register. */ 441 rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000); 442 rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404); 443 rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201); 444 rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605); 445 } 446 447 static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 448 u8 ctx_sifs) 449 { 450 struct rtl_priv *rtlpriv = rtl_priv(hw); 451 452 rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs); 453 rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs); 454 } 455 456 static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 457 u8 ctx_sifs) 458 { 459 struct rtl_priv *rtlpriv = rtl_priv(hw); 460 461 rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs); 462 rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs); 463 } 464 465 void rtl92c_init_edca_param(struct ieee80211_hw *hw, 466 u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs) 467 { 468 /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design. 469 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function. 470 */ 471 u32 value; 472 struct rtl_priv *rtlpriv = rtl_priv(hw); 473 474 value = (u32)aifs; 475 value |= ((u32)cw_min & 0xF) << 8; 476 value |= ((u32)cw_max & 0xF) << 12; 477 value |= (u32)txop << 16; 478 /* 92C hardware register sequence is the same as queue number. */ 479 rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value); 480 } 481 482 void rtl92c_init_edca(struct ieee80211_hw *hw) 483 { 484 u16 value16; 485 struct rtl_priv *rtlpriv = rtl_priv(hw); 486 487 /* disable EDCCA count down, to reduce collison and retry */ 488 value16 = rtl_read_word(rtlpriv, REG_RD_CTRL); 489 value16 |= DIS_EDCA_CNT_DWN; 490 rtl_write_word(rtlpriv, REG_RD_CTRL, value16); 491 /* Update SIFS timing. ?????????? 492 * pHalData->SifsTime = 0x0e0e0a0a; */ 493 rtl92c_set_cck_sifs(hw, 0xa, 0xa); 494 rtl92c_set_ofdm_sifs(hw, 0xe, 0xe); 495 /* Set CCK/OFDM SIFS to be 10us. */ 496 rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a); 497 rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010); 498 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204); 499 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004); 500 /* TXOP */ 501 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B); 502 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F); 503 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324); 504 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226); 505 /* PIFS */ 506 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 507 /* AGGR BREAK TIME Register */ 508 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 509 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 510 rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02); 511 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02); 512 } 513 514 void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw) 515 { 516 struct rtl_priv *rtlpriv = rtl_priv(hw); 517 518 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631); 519 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 520 /* init AMPDU aggregation number, tuning for Tx's TP, */ 521 rtl_write_word(rtlpriv, 0x4CA, 0x0708); 522 } 523 524 void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw) 525 { 526 struct rtl_priv *rtlpriv = rtl_priv(hw); 527 528 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF); 529 } 530 531 void rtl92c_init_rdg_setting(struct ieee80211_hw *hw) 532 { 533 struct rtl_priv *rtlpriv = rtl_priv(hw); 534 535 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF); 536 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); 537 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); 538 } 539 540 void rtl92c_init_retry_function(struct ieee80211_hw *hw) 541 { 542 u8 value8; 543 struct rtl_priv *rtlpriv = rtl_priv(hw); 544 545 value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL); 546 value8 |= EN_AMPDU_RTY_NEW; 547 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8); 548 /* Set ACK timeout */ 549 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 550 } 551 552 void rtl92c_disable_fast_edca(struct ieee80211_hw *hw) 553 { 554 struct rtl_priv *rtlpriv = rtl_priv(hw); 555 556 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0); 557 } 558 559 void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T) 560 { 561 struct rtl_priv *rtlpriv = rtl_priv(hw); 562 u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T; 563 564 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value); 565 } 566 567 /*==============================================================*/ 568 569 static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw, 570 struct rtl_stats *pstats, 571 struct rx_desc_92c *p_desc, 572 struct rx_fwinfo_92c *p_drvinfo, 573 bool packet_match_bssid, 574 bool packet_toself, 575 bool packet_beacon) 576 { 577 struct rtl_priv *rtlpriv = rtl_priv(hw); 578 struct rtl_phy *rtlphy = &(rtlpriv->phy); 579 struct phy_sts_cck_8192s_t *cck_buf; 580 s8 rx_pwr_all = 0, rx_pwr[4]; 581 u8 rf_rx_num = 0, evm, pwdb_all; 582 u8 i, max_spatial_stream; 583 u32 rssi, total_rssi = 0; 584 bool in_powersavemode = false; 585 bool is_cck_rate; 586 __le32 *pdesc = (__le32 *)p_desc; 587 588 is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs); 589 pstats->packet_matchbssid = packet_match_bssid; 590 pstats->packet_toself = packet_toself; 591 pstats->packet_beacon = packet_beacon; 592 pstats->is_cck = is_cck_rate; 593 pstats->RX_SIGQ[0] = -1; 594 pstats->RX_SIGQ[1] = -1; 595 if (is_cck_rate) { 596 u8 report, cck_highpwr; 597 598 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo; 599 if (!in_powersavemode) 600 cck_highpwr = rtlphy->cck_high_power; 601 else 602 cck_highpwr = false; 603 if (!cck_highpwr) { 604 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 605 606 report = cck_buf->cck_agc_rpt & 0xc0; 607 report = report >> 6; 608 switch (report) { 609 case 0x3: 610 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); 611 break; 612 case 0x2: 613 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); 614 break; 615 case 0x1: 616 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); 617 break; 618 case 0x0: 619 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); 620 break; 621 } 622 } else { 623 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 624 625 report = p_drvinfo->cfosho[0] & 0x60; 626 report = report >> 5; 627 switch (report) { 628 case 0x3: 629 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); 630 break; 631 case 0x2: 632 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); 633 break; 634 case 0x1: 635 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); 636 break; 637 case 0x0: 638 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); 639 break; 640 } 641 } 642 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); 643 pstats->rx_pwdb_all = pwdb_all; 644 pstats->recvsignalpower = rx_pwr_all; 645 if (packet_match_bssid) { 646 u8 sq; 647 648 if (pstats->rx_pwdb_all > 40) 649 sq = 100; 650 else { 651 sq = cck_buf->sq_rpt; 652 if (sq > 64) 653 sq = 0; 654 else if (sq < 20) 655 sq = 100; 656 else 657 sq = ((64 - sq) * 100) / 44; 658 } 659 pstats->signalquality = sq; 660 pstats->RX_SIGQ[0] = sq; 661 pstats->RX_SIGQ[1] = -1; 662 } 663 } else { 664 rtlpriv->dm.rfpath_rxenable[0] = 665 rtlpriv->dm.rfpath_rxenable[1] = true; 666 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { 667 if (rtlpriv->dm.rfpath_rxenable[i]) 668 rf_rx_num++; 669 rx_pwr[i] = 670 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110; 671 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); 672 total_rssi += rssi; 673 rtlpriv->stats.rx_snr_db[i] = 674 (long)(p_drvinfo->rxsnr[i] / 2); 675 676 if (packet_match_bssid) 677 pstats->rx_mimo_signalstrength[i] = (u8) rssi; 678 } 679 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110; 680 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); 681 pstats->rx_pwdb_all = pwdb_all; 682 pstats->rxpower = rx_pwr_all; 683 pstats->recvsignalpower = rx_pwr_all; 684 if (get_rx_desc_rx_mcs(pdesc) && 685 get_rx_desc_rx_mcs(pdesc) >= DESC_RATEMCS8 && 686 get_rx_desc_rx_mcs(pdesc) <= DESC_RATEMCS15) 687 max_spatial_stream = 2; 688 else 689 max_spatial_stream = 1; 690 for (i = 0; i < max_spatial_stream; i++) { 691 evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]); 692 if (packet_match_bssid) { 693 if (i == 0) 694 pstats->signalquality = 695 (u8) (evm & 0xff); 696 pstats->RX_SIGQ[i] = 697 (u8) (evm & 0xff); 698 } 699 } 700 } 701 if (is_cck_rate) 702 pstats->signalstrength = 703 (u8)(rtl_signal_scale_mapping(hw, pwdb_all)); 704 else if (rf_rx_num != 0) 705 pstats->signalstrength = 706 (u8)(rtl_signal_scale_mapping(hw, total_rssi /= rf_rx_num)); 707 } 708 709 void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw, 710 struct sk_buff *skb, 711 struct rtl_stats *pstats, 712 struct rx_desc_92c *pdesc, 713 struct rx_fwinfo_92c *p_drvinfo) 714 { 715 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 716 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 717 struct ieee80211_hdr *hdr; 718 u8 *tmp_buf; 719 u8 *praddr; 720 __le16 fc; 721 u16 type, cpu_fc; 722 bool packet_matchbssid, packet_toself, packet_beacon = false; 723 724 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; 725 hdr = (struct ieee80211_hdr *)tmp_buf; 726 fc = hdr->frame_control; 727 cpu_fc = le16_to_cpu(fc); 728 type = WLAN_FC_GET_TYPE(fc); 729 praddr = hdr->addr1; 730 packet_matchbssid = 731 ((IEEE80211_FTYPE_CTL != type) && 732 ether_addr_equal(mac->bssid, 733 (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : 734 (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : 735 hdr->addr3) && 736 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); 737 738 packet_toself = packet_matchbssid && 739 ether_addr_equal(praddr, rtlefuse->dev_addr); 740 if (ieee80211_is_beacon(fc)) 741 packet_beacon = true; 742 _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, 743 packet_matchbssid, packet_toself, 744 packet_beacon); 745 rtl_process_phyinfo(hw, tmp_buf, pstats); 746 } 747