1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #include "../wifi.h" 31 #include "../efuse.h" 32 #include "../base.h" 33 #include "../cam.h" 34 #include "../ps.h" 35 #include "../usb.h" 36 #include "reg.h" 37 #include "def.h" 38 #include "phy.h" 39 #include "../rtl8192c/phy_common.h" 40 #include "mac.h" 41 #include "dm.h" 42 #include "../rtl8192c/dm_common.h" 43 #include "../rtl8192c/fw_common.h" 44 #include "hw.h" 45 #include "../rtl8192ce/hw.h" 46 #include "trx.h" 47 #include "led.h" 48 #include "table.h" 49 50 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw) 51 { 52 struct rtl_priv *rtlpriv = rtl_priv(hw); 53 struct rtl_phy *rtlphy = &(rtlpriv->phy); 54 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 55 56 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH; 57 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY; 58 if (IS_HIGHT_PA(rtlefuse->board_type)) { 59 rtlphy->hwparam_tables[PHY_REG_PG].length = 60 RTL8192CUPHY_REG_Array_PG_HPLength; 61 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 62 RTL8192CUPHY_REG_Array_PG_HP; 63 } else { 64 rtlphy->hwparam_tables[PHY_REG_PG].length = 65 RTL8192CUPHY_REG_ARRAY_PGLENGTH; 66 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 67 RTL8192CUPHY_REG_ARRAY_PG; 68 } 69 /* 2T */ 70 rtlphy->hwparam_tables[PHY_REG_2T].length = 71 RTL8192CUPHY_REG_2TARRAY_LENGTH; 72 rtlphy->hwparam_tables[PHY_REG_2T].pdata = 73 RTL8192CUPHY_REG_2TARRAY; 74 rtlphy->hwparam_tables[RADIOA_2T].length = 75 RTL8192CURADIOA_2TARRAYLENGTH; 76 rtlphy->hwparam_tables[RADIOA_2T].pdata = 77 RTL8192CURADIOA_2TARRAY; 78 rtlphy->hwparam_tables[RADIOB_2T].length = 79 RTL8192CURADIOB_2TARRAYLENGTH; 80 rtlphy->hwparam_tables[RADIOB_2T].pdata = 81 RTL8192CU_RADIOB_2TARRAY; 82 rtlphy->hwparam_tables[AGCTAB_2T].length = 83 RTL8192CUAGCTAB_2TARRAYLENGTH; 84 rtlphy->hwparam_tables[AGCTAB_2T].pdata = 85 RTL8192CUAGCTAB_2TARRAY; 86 /* 1T */ 87 if (IS_HIGHT_PA(rtlefuse->board_type)) { 88 rtlphy->hwparam_tables[PHY_REG_1T].length = 89 RTL8192CUPHY_REG_1T_HPArrayLength; 90 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 91 RTL8192CUPHY_REG_1T_HPArray; 92 rtlphy->hwparam_tables[RADIOA_1T].length = 93 RTL8192CURadioA_1T_HPArrayLength; 94 rtlphy->hwparam_tables[RADIOA_1T].pdata = 95 RTL8192CURadioA_1T_HPArray; 96 rtlphy->hwparam_tables[RADIOB_1T].length = 97 RTL8192CURADIOB_1TARRAYLENGTH; 98 rtlphy->hwparam_tables[RADIOB_1T].pdata = 99 RTL8192CU_RADIOB_1TARRAY; 100 rtlphy->hwparam_tables[AGCTAB_1T].length = 101 RTL8192CUAGCTAB_1T_HPArrayLength; 102 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 103 Rtl8192CUAGCTAB_1T_HPArray; 104 } else { 105 rtlphy->hwparam_tables[PHY_REG_1T].length = 106 RTL8192CUPHY_REG_1TARRAY_LENGTH; 107 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 108 RTL8192CUPHY_REG_1TARRAY; 109 rtlphy->hwparam_tables[RADIOA_1T].length = 110 RTL8192CURADIOA_1TARRAYLENGTH; 111 rtlphy->hwparam_tables[RADIOA_1T].pdata = 112 RTL8192CU_RADIOA_1TARRAY; 113 rtlphy->hwparam_tables[RADIOB_1T].length = 114 RTL8192CURADIOB_1TARRAYLENGTH; 115 rtlphy->hwparam_tables[RADIOB_1T].pdata = 116 RTL8192CU_RADIOB_1TARRAY; 117 rtlphy->hwparam_tables[AGCTAB_1T].length = 118 RTL8192CUAGCTAB_1TARRAYLENGTH; 119 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 120 RTL8192CUAGCTAB_1TARRAY; 121 } 122 } 123 124 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 125 bool autoload_fail, 126 u8 *hwinfo) 127 { 128 struct rtl_priv *rtlpriv = rtl_priv(hw); 129 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 130 u8 rf_path, index, tempval; 131 u16 i; 132 133 for (rf_path = 0; rf_path < 2; rf_path++) { 134 for (i = 0; i < 3; i++) { 135 if (!autoload_fail) { 136 rtlefuse-> 137 eeprom_chnlarea_txpwr_cck[rf_path][i] = 138 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 139 rtlefuse-> 140 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 141 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 142 i]; 143 } else { 144 rtlefuse-> 145 eeprom_chnlarea_txpwr_cck[rf_path][i] = 146 EEPROM_DEFAULT_TXPOWERLEVEL; 147 rtlefuse-> 148 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 149 EEPROM_DEFAULT_TXPOWERLEVEL; 150 } 151 } 152 } 153 for (i = 0; i < 3; i++) { 154 if (!autoload_fail) 155 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 156 else 157 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 158 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 159 (tempval & 0xf); 160 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 161 ((tempval & 0xf0) >> 4); 162 } 163 for (rf_path = 0; rf_path < 2; rf_path++) 164 for (i = 0; i < 3; i++) 165 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 166 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 167 rf_path, i, 168 rtlefuse-> 169 eeprom_chnlarea_txpwr_cck[rf_path][i]); 170 for (rf_path = 0; rf_path < 2; rf_path++) 171 for (i = 0; i < 3; i++) 172 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 173 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 174 rf_path, i, 175 rtlefuse-> 176 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 177 for (rf_path = 0; rf_path < 2; rf_path++) 178 for (i = 0; i < 3; i++) 179 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 180 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 181 rf_path, i, 182 rtlefuse-> 183 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 184 for (rf_path = 0; rf_path < 2; rf_path++) { 185 for (i = 0; i < 14; i++) { 186 index = rtl92c_get_chnl_group((u8)i); 187 rtlefuse->txpwrlevel_cck[rf_path][i] = 188 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 189 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 190 rtlefuse-> 191 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 192 if ((rtlefuse-> 193 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 194 rtlefuse-> 195 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 196 > 0) { 197 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 198 rtlefuse-> 199 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 200 [index] - rtlefuse-> 201 eprom_chnl_txpwr_ht40_2sdf[rf_path] 202 [index]; 203 } else { 204 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 205 } 206 } 207 for (i = 0; i < 14; i++) { 208 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 209 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i, 210 rtlefuse->txpwrlevel_cck[rf_path][i], 211 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 212 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 213 } 214 } 215 for (i = 0; i < 3; i++) { 216 if (!autoload_fail) { 217 rtlefuse->eeprom_pwrlimit_ht40[i] = 218 hwinfo[EEPROM_TXPWR_GROUP + i]; 219 rtlefuse->eeprom_pwrlimit_ht20[i] = 220 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 221 } else { 222 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 223 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 224 } 225 } 226 for (rf_path = 0; rf_path < 2; rf_path++) { 227 for (i = 0; i < 14; i++) { 228 index = rtl92c_get_chnl_group((u8)i); 229 if (rf_path == RF90_PATH_A) { 230 rtlefuse->pwrgroup_ht20[rf_path][i] = 231 (rtlefuse->eeprom_pwrlimit_ht20[index] 232 & 0xf); 233 rtlefuse->pwrgroup_ht40[rf_path][i] = 234 (rtlefuse->eeprom_pwrlimit_ht40[index] 235 & 0xf); 236 } else if (rf_path == RF90_PATH_B) { 237 rtlefuse->pwrgroup_ht20[rf_path][i] = 238 ((rtlefuse->eeprom_pwrlimit_ht20[index] 239 & 0xf0) >> 4); 240 rtlefuse->pwrgroup_ht40[rf_path][i] = 241 ((rtlefuse->eeprom_pwrlimit_ht40[index] 242 & 0xf0) >> 4); 243 } 244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 245 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 246 rf_path, i, 247 rtlefuse->pwrgroup_ht20[rf_path][i]); 248 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 249 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 250 rf_path, i, 251 rtlefuse->pwrgroup_ht40[rf_path][i]); 252 } 253 } 254 for (i = 0; i < 14; i++) { 255 index = rtl92c_get_chnl_group((u8)i); 256 if (!autoload_fail) 257 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 258 else 259 tempval = EEPROM_DEFAULT_HT20_DIFF; 260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 261 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 262 ((tempval >> 4) & 0xF); 263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 264 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 265 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 266 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 267 index = rtl92c_get_chnl_group((u8)i); 268 if (!autoload_fail) 269 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 270 else 271 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 272 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 274 ((tempval >> 4) & 0xF); 275 } 276 rtlefuse->legacy_ht_txpowerdiff = 277 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 278 for (i = 0; i < 14; i++) 279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 280 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 281 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 282 for (i = 0; i < 14; i++) 283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 284 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 285 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 286 for (i = 0; i < 14; i++) 287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 288 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 289 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 290 for (i = 0; i < 14; i++) 291 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 292 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 293 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 294 if (!autoload_fail) 295 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 296 else 297 rtlefuse->eeprom_regulatory = 0; 298 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 299 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 300 if (!autoload_fail) { 301 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 302 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 303 } else { 304 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 305 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 306 } 307 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 308 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 309 rtlefuse->eeprom_tssi[RF90_PATH_A], 310 rtlefuse->eeprom_tssi[RF90_PATH_B]); 311 if (!autoload_fail) 312 tempval = hwinfo[EEPROM_THERMAL_METER]; 313 else 314 tempval = EEPROM_DEFAULT_THERMALMETER; 315 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 316 if (rtlefuse->eeprom_thermalmeter < 0x06 || 317 rtlefuse->eeprom_thermalmeter > 0x1c) 318 rtlefuse->eeprom_thermalmeter = 0x12; 319 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 320 rtlefuse->apk_thermalmeterignore = true; 321 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 322 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 323 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 324 } 325 326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents) 327 { 328 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 329 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 330 u8 boardType; 331 332 if (IS_NORMAL_CHIP(rtlhal->version)) { 333 boardType = ((contents[EEPROM_RF_OPT1]) & 334 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/ 335 } else { 336 boardType = contents[EEPROM_RF_OPT4]; 337 boardType &= BOARD_TYPE_TEST_MASK; 338 } 339 rtlefuse->board_type = boardType; 340 if (IS_HIGHT_PA(rtlefuse->board_type)) 341 rtlefuse->external_pa = 1; 342 pr_info("Board Type %x\n", rtlefuse->board_type); 343 } 344 345 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw) 346 { 347 struct rtl_priv *rtlpriv = rtl_priv(hw); 348 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 349 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 350 u16 i, usvalue; 351 u8 hwinfo[HWSET_MAX_SIZE] = {0}; 352 u16 eeprom_id; 353 354 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { 355 rtl_efuse_shadow_map_update(hw); 356 memcpy((void *)hwinfo, 357 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], 358 HWSET_MAX_SIZE); 359 } else if (rtlefuse->epromtype == EEPROM_93C46) { 360 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 361 "RTL819X Not boot from eeprom, check it !!\n"); 362 } 363 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP", 364 hwinfo, HWSET_MAX_SIZE); 365 eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0])); 366 if (eeprom_id != RTL8190_EEPROM_ID) { 367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 368 "EEPROM ID(%#x) is invalid!!\n", eeprom_id); 369 rtlefuse->autoload_failflag = true; 370 } else { 371 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 372 rtlefuse->autoload_failflag = false; 373 } 374 if (rtlefuse->autoload_failflag) 375 return; 376 for (i = 0; i < 6; i += 2) { 377 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; 378 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 379 } 380 pr_info("MAC address: %pM\n", rtlefuse->dev_addr); 381 _rtl92cu_read_txpower_info_from_hwpg(hw, 382 rtlefuse->autoload_failflag, hwinfo); 383 rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]); 384 rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]); 385 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n", 386 rtlefuse->eeprom_vid, rtlefuse->eeprom_did); 387 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN]; 388 rtlefuse->eeprom_version = 389 le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]); 390 rtlefuse->txpwr_fromeprom = true; 391 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID]; 392 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n", 393 rtlefuse->eeprom_oemid); 394 if (rtlhal->oem_id == RT_CID_DEFAULT) { 395 switch (rtlefuse->eeprom_oemid) { 396 case EEPROM_CID_DEFAULT: 397 if (rtlefuse->eeprom_did == 0x8176) { 398 if ((rtlefuse->eeprom_svid == 0x103C && 399 rtlefuse->eeprom_smid == 0x1629)) 400 rtlhal->oem_id = RT_CID_819X_HP; 401 else 402 rtlhal->oem_id = RT_CID_DEFAULT; 403 } else { 404 rtlhal->oem_id = RT_CID_DEFAULT; 405 } 406 break; 407 case EEPROM_CID_TOSHIBA: 408 rtlhal->oem_id = RT_CID_TOSHIBA; 409 break; 410 case EEPROM_CID_QMI: 411 rtlhal->oem_id = RT_CID_819X_QMI; 412 break; 413 case EEPROM_CID_WHQL: 414 default: 415 rtlhal->oem_id = RT_CID_DEFAULT; 416 break; 417 } 418 } 419 _rtl92cu_read_board_type(hw, hwinfo); 420 } 421 422 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw) 423 { 424 struct rtl_priv *rtlpriv = rtl_priv(hw); 425 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 426 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 427 428 switch (rtlhal->oem_id) { 429 case RT_CID_819X_HP: 430 usb_priv->ledctl.led_opendrain = true; 431 break; 432 case RT_CID_819X_LENOVO: 433 case RT_CID_DEFAULT: 434 case RT_CID_TOSHIBA: 435 case RT_CID_CCX: 436 case RT_CID_819X_ACER: 437 case RT_CID_WHQL: 438 default: 439 break; 440 } 441 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", 442 rtlhal->oem_id); 443 } 444 445 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw) 446 { 447 448 struct rtl_priv *rtlpriv = rtl_priv(hw); 449 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 450 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 451 u8 tmp_u1b; 452 453 if (!IS_NORMAL_CHIP(rtlhal->version)) 454 return; 455 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 456 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ? 457 EEPROM_93C46 : EEPROM_BOOT_EFUSE; 458 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n", 459 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE"); 460 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true; 461 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n", 462 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!"); 463 _rtl92cu_read_adapter_info(hw); 464 _rtl92cu_hal_customized_behavior(hw); 465 return; 466 } 467 468 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw) 469 { 470 struct rtl_priv *rtlpriv = rtl_priv(hw); 471 int status = 0; 472 u16 value16; 473 u8 value8; 474 /* polling autoload done. */ 475 u32 pollingCount = 0; 476 477 do { 478 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) { 479 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 480 "Autoload Done!\n"); 481 break; 482 } 483 if (pollingCount++ > 100) { 484 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 485 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"); 486 return -ENODEV; 487 } 488 } while (true); 489 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */ 490 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 491 /* Power on when re-enter from IPS/Radio off/card disable */ 492 /* enable SPS into PWM mode */ 493 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 494 udelay(100); 495 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 496 if (0 == (value8 & LDV12_EN)) { 497 value8 |= LDV12_EN; 498 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 499 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 500 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n", 501 value8); 502 udelay(100); 503 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 504 value8 &= ~ISO_MD2PP; 505 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8); 506 } 507 /* auto enable WLAN */ 508 pollingCount = 0; 509 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO); 510 value16 |= APFM_ONMAC; 511 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16); 512 do { 513 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) { 514 pr_info("MAC auto ON okay!\n"); 515 break; 516 } 517 if (pollingCount++ > 1000) { 518 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 519 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"); 520 return -ENODEV; 521 } 522 } while (true); 523 /* Enable Radio ,GPIO ,and LED function */ 524 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812); 525 /* release RF digital isolation */ 526 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 527 value16 &= ~ISO_DIOR; 528 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16); 529 /* Reconsider when to do this operation after asking HWSD. */ 530 pollingCount = 0; 531 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv, 532 REG_APSD_CTRL) & ~BIT(6))); 533 do { 534 pollingCount++; 535 } while ((pollingCount < 200) && 536 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7))); 537 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 538 value16 = rtl_read_word(rtlpriv, REG_CR); 539 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | 540 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC); 541 rtl_write_word(rtlpriv, REG_CR, value16); 542 return status; 543 } 544 545 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw, 546 bool wmm_enable, 547 u8 out_ep_num, 548 u8 queue_sel) 549 { 550 struct rtl_priv *rtlpriv = rtl_priv(hw); 551 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 552 bool isChipN = IS_NORMAL_CHIP(rtlhal->version); 553 u32 outEPNum = (u32)out_ep_num; 554 u32 numHQ = 0; 555 u32 numLQ = 0; 556 u32 numNQ = 0; 557 u32 numPubQ; 558 u32 value32; 559 u8 value8; 560 u32 txQPageNum, txQPageUnit, txQRemainPage; 561 562 if (!wmm_enable) { 563 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ : 564 CHIP_A_PAGE_NUM_PUBQ; 565 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ; 566 567 txQPageUnit = txQPageNum/outEPNum; 568 txQRemainPage = txQPageNum % outEPNum; 569 if (queue_sel & TX_SELE_HQ) 570 numHQ = txQPageUnit; 571 if (queue_sel & TX_SELE_LQ) 572 numLQ = txQPageUnit; 573 /* HIGH priority queue always present in the configuration of 574 * 2 out-ep. Remainder pages have assigned to High queue */ 575 if ((outEPNum > 1) && (txQRemainPage)) 576 numHQ += txQRemainPage; 577 /* NOTE: This step done before writting REG_RQPN. */ 578 if (isChipN) { 579 if (queue_sel & TX_SELE_NQ) 580 numNQ = txQPageUnit; 581 value8 = (u8)_NPQ(numNQ); 582 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 583 } 584 } else { 585 /* for WMM ,number of out-ep must more than or equal to 2! */ 586 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ : 587 WMM_CHIP_A_PAGE_NUM_PUBQ; 588 if (queue_sel & TX_SELE_HQ) { 589 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ : 590 WMM_CHIP_A_PAGE_NUM_HPQ; 591 } 592 if (queue_sel & TX_SELE_LQ) { 593 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ : 594 WMM_CHIP_A_PAGE_NUM_LPQ; 595 } 596 /* NOTE: This step done before writting REG_RQPN. */ 597 if (isChipN) { 598 if (queue_sel & TX_SELE_NQ) 599 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ; 600 value8 = (u8)_NPQ(numNQ); 601 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 602 } 603 } 604 /* TX DMA */ 605 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; 606 rtl_write_dword(rtlpriv, REG_RQPN, value32); 607 } 608 609 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable) 610 { 611 struct rtl_priv *rtlpriv = rtl_priv(hw); 612 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 613 u8 txpktbuf_bndy; 614 u8 value8; 615 616 if (!wmm_enable) 617 txpktbuf_bndy = TX_PAGE_BOUNDARY; 618 else /* for WMM */ 619 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version)) 620 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 621 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 622 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 623 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 624 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); 625 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 626 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy); 627 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 628 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128); 629 rtl_write_byte(rtlpriv, REG_PBP, value8); 630 } 631 632 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ, 633 u16 bkQ, u16 viQ, u16 voQ, 634 u16 mgtQ, u16 hiQ) 635 { 636 struct rtl_priv *rtlpriv = rtl_priv(hw); 637 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7); 638 639 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | 640 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | 641 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); 642 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); 643 } 644 645 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw, 646 bool wmm_enable, 647 u8 queue_sel) 648 { 649 u16 uninitialized_var(value); 650 651 switch (queue_sel) { 652 case TX_SELE_HQ: 653 value = QUEUE_HIGH; 654 break; 655 case TX_SELE_LQ: 656 value = QUEUE_LOW; 657 break; 658 case TX_SELE_NQ: 659 value = QUEUE_NORMAL; 660 break; 661 default: 662 WARN_ON(1); /* Shall not reach here! */ 663 break; 664 } 665 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value, 666 value, value); 667 pr_info("Tx queue select: 0x%02x\n", queue_sel); 668 } 669 670 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw, 671 bool wmm_enable, 672 u8 queue_sel) 673 { 674 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 675 u16 uninitialized_var(valueHi); 676 u16 uninitialized_var(valueLow); 677 678 switch (queue_sel) { 679 case (TX_SELE_HQ | TX_SELE_LQ): 680 valueHi = QUEUE_HIGH; 681 valueLow = QUEUE_LOW; 682 break; 683 case (TX_SELE_NQ | TX_SELE_LQ): 684 valueHi = QUEUE_NORMAL; 685 valueLow = QUEUE_LOW; 686 break; 687 case (TX_SELE_HQ | TX_SELE_NQ): 688 valueHi = QUEUE_HIGH; 689 valueLow = QUEUE_NORMAL; 690 break; 691 default: 692 WARN_ON(1); 693 break; 694 } 695 if (!wmm_enable) { 696 beQ = valueLow; 697 bkQ = valueLow; 698 viQ = valueHi; 699 voQ = valueHi; 700 mgtQ = valueHi; 701 hiQ = valueHi; 702 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ 703 beQ = valueHi; 704 bkQ = valueLow; 705 viQ = valueLow; 706 voQ = valueHi; 707 mgtQ = valueHi; 708 hiQ = valueHi; 709 } 710 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 711 pr_info("Tx queue select: 0x%02x\n", queue_sel); 712 } 713 714 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw, 715 bool wmm_enable, 716 u8 queue_sel) 717 { 718 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 719 struct rtl_priv *rtlpriv = rtl_priv(hw); 720 721 if (!wmm_enable) { /* typical setting */ 722 beQ = QUEUE_LOW; 723 bkQ = QUEUE_LOW; 724 viQ = QUEUE_NORMAL; 725 voQ = QUEUE_HIGH; 726 mgtQ = QUEUE_HIGH; 727 hiQ = QUEUE_HIGH; 728 } else { /* for WMM */ 729 beQ = QUEUE_LOW; 730 bkQ = QUEUE_NORMAL; 731 viQ = QUEUE_NORMAL; 732 voQ = QUEUE_HIGH; 733 mgtQ = QUEUE_HIGH; 734 hiQ = QUEUE_HIGH; 735 } 736 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 737 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n", 738 queue_sel); 739 } 740 741 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw, 742 bool wmm_enable, 743 u8 out_ep_num, 744 u8 queue_sel) 745 { 746 switch (out_ep_num) { 747 case 1: 748 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable, 749 queue_sel); 750 break; 751 case 2: 752 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable, 753 queue_sel); 754 break; 755 case 3: 756 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable, 757 queue_sel); 758 break; 759 default: 760 WARN_ON(1); /* Shall not reach here! */ 761 break; 762 } 763 } 764 765 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw, 766 bool wmm_enable, 767 u8 out_ep_num, 768 u8 queue_sel) 769 { 770 u8 hq_sele = 0; 771 struct rtl_priv *rtlpriv = rtl_priv(hw); 772 773 switch (out_ep_num) { 774 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */ 775 if (!wmm_enable) /* typical setting */ 776 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | 777 HQSEL_HIQ; 778 else /* for WMM */ 779 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ | 780 HQSEL_HIQ; 781 break; 782 case 1: 783 if (TX_SELE_LQ == queue_sel) { 784 /* map all endpoint to Low queue */ 785 hq_sele = 0; 786 } else if (TX_SELE_HQ == queue_sel) { 787 /* map all endpoint to High queue */ 788 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ | 789 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ; 790 } 791 break; 792 default: 793 WARN_ON(1); /* Shall not reach here! */ 794 break; 795 } 796 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele); 797 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n", 798 hq_sele); 799 } 800 801 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw, 802 bool wmm_enable, 803 u8 out_ep_num, 804 u8 queue_sel) 805 { 806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 807 if (IS_NORMAL_CHIP(rtlhal->version)) 808 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num, 809 queue_sel); 810 else 811 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num, 812 queue_sel); 813 } 814 815 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw) 816 { 817 } 818 819 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw) 820 { 821 u16 value16; 822 u32 value32; 823 struct rtl_priv *rtlpriv = rtl_priv(hw); 824 825 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS | 826 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | 827 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32); 828 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32)); 829 /* Accept all multicast address */ 830 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF); 831 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF); 832 /* Accept all management frames */ 833 value16 = 0xFFFF; 834 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER, 835 (u8 *)(&value16)); 836 /* Reject all control frame - default value is 0 */ 837 value16 = 0x0; 838 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER, 839 (u8 *)(&value16)); 840 /* Accept all data frames */ 841 value16 = 0xFFFF; 842 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER, 843 (u8 *)(&value16)); 844 } 845 846 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw) 847 { 848 struct rtl_priv *rtlpriv = rtl_priv(hw); 849 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 850 851 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); 852 853 /* TODO: Remove these magic number */ 854 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404); 855 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME); 856 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); 857 /* Change beacon AIFS to the largest number 858 * beacause test chip does not contension before sending beacon. 859 */ 860 if (IS_NORMAL_CHIP(rtlhal->version)) 861 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F); 862 else 863 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF); 864 } 865 866 static int _rtl92cu_init_mac(struct ieee80211_hw *hw) 867 { 868 struct rtl_priv *rtlpriv = rtl_priv(hw); 869 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 870 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 871 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); 872 int err = 0; 873 u32 boundary = 0; 874 u8 wmm_enable = false; /* TODO */ 875 u8 out_ep_nums = rtlusb->out_ep_nums; 876 u8 queue_sel = rtlusb->out_queue_sel; 877 err = _rtl92cu_init_power_on(hw); 878 879 if (err) { 880 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 881 "Failed to init power on!\n"); 882 return err; 883 } 884 if (!wmm_enable) { 885 boundary = TX_PAGE_BOUNDARY; 886 } else { /* for WMM */ 887 boundary = (IS_NORMAL_CHIP(rtlhal->version)) 888 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 889 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 890 } 891 if (false == rtl92c_init_llt_table(hw, boundary)) { 892 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 893 "Failed to init LLT Table!\n"); 894 return -EINVAL; 895 } 896 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums, 897 queue_sel); 898 _rtl92c_init_trx_buffer(hw, wmm_enable); 899 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums, 900 queue_sel); 901 /* Get Rx PHY status in order to report RSSI and others. */ 902 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE); 903 rtl92c_init_interrupt(hw); 904 rtl92c_init_network_type(hw); 905 _rtl92cu_init_wmac_setting(hw); 906 rtl92c_init_adaptive_ctrl(hw); 907 rtl92c_init_edca(hw); 908 rtl92c_init_rate_fallback(hw); 909 rtl92c_init_retry_function(hw); 910 _rtl92cu_init_usb_aggregation(hw); 911 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20); 912 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version)); 913 _rtl92cu_init_beacon_parameters(hw); 914 rtl92c_init_ampdu_aggregation(hw); 915 rtl92c_init_beacon_max_error(hw); 916 return err; 917 } 918 919 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw) 920 { 921 struct rtl_priv *rtlpriv = rtl_priv(hw); 922 u8 sec_reg_value = 0x0; 923 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 924 925 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 926 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 927 rtlpriv->sec.pairwise_enc_algorithm, 928 rtlpriv->sec.group_enc_algorithm); 929 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 930 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 931 "not open sw encryption\n"); 932 return; 933 } 934 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 935 if (rtlpriv->sec.use_defaultkey) { 936 sec_reg_value |= SCR_TxUseDK; 937 sec_reg_value |= SCR_RxUseDK; 938 } 939 if (IS_NORMAL_CHIP(rtlhal->version)) 940 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 941 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 942 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 943 sec_reg_value); 944 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 945 } 946 947 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw) 948 { 949 struct rtl_priv *rtlpriv = rtl_priv(hw); 950 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 951 952 /* To Fix MAC loopback mode fail. */ 953 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); 954 rtl_write_byte(rtlpriv, 0x15, 0xe9); 955 /* HW SEQ CTRL */ 956 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 957 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 958 /* fixed USB interface interference issue */ 959 rtl_write_byte(rtlpriv, 0xfe40, 0xe0); 960 rtl_write_byte(rtlpriv, 0xfe41, 0x8d); 961 rtl_write_byte(rtlpriv, 0xfe42, 0x80); 962 rtlusb->reg_bcn_ctrl_val = 0x18; 963 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 964 } 965 966 static void _InitPABias(struct ieee80211_hw *hw) 967 { 968 struct rtl_priv *rtlpriv = rtl_priv(hw); 969 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 970 u8 pa_setting; 971 972 /* FIXED PA current issue */ 973 pa_setting = efuse_read_1byte(hw, 0x1FA); 974 if (!(pa_setting & BIT(0))) { 975 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); 976 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); 977 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); 978 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); 979 } 980 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) && 981 IS_92C_SERIAL(rtlhal->version)) { 982 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); 983 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); 984 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); 985 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); 986 } 987 if (!(pa_setting & BIT(4))) { 988 pa_setting = rtl_read_byte(rtlpriv, 0x16); 989 pa_setting &= 0x0F; 990 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90); 991 } 992 } 993 994 int rtl92cu_hw_init(struct ieee80211_hw *hw) 995 { 996 struct rtl_priv *rtlpriv = rtl_priv(hw); 997 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 998 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 999 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1000 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1001 int err = 0; 1002 unsigned long flags; 1003 1004 /* As this function can take a very long time (up to 350 ms) 1005 * and can be called with irqs disabled, reenable the irqs 1006 * to let the other devices continue being serviced. 1007 * 1008 * It is safe doing so since our own interrupts will only be enabled 1009 * in a subsequent step. 1010 */ 1011 local_save_flags(flags); 1012 local_irq_enable(); 1013 1014 rtlhal->fw_ready = false; 1015 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU; 1016 err = _rtl92cu_init_mac(hw); 1017 if (err) { 1018 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n"); 1019 goto exit; 1020 } 1021 err = rtl92c_download_fw(hw); 1022 if (err) { 1023 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1024 "Failed to download FW. Init HW without FW now..\n"); 1025 err = 1; 1026 goto exit; 1027 } 1028 1029 rtlhal->fw_ready = true; 1030 rtlhal->last_hmeboxnum = 0; /* h2c */ 1031 _rtl92cu_phy_param_tab_init(hw); 1032 rtl92cu_phy_mac_config(hw); 1033 rtl92cu_phy_bb_config(hw); 1034 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1035 rtl92c_phy_rf_config(hw); 1036 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 1037 !IS_92C_SERIAL(rtlhal->version)) { 1038 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 1039 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 1040 } 1041 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1042 RF_CHNLBW, RFREG_OFFSET_MASK); 1043 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1044 RF_CHNLBW, RFREG_OFFSET_MASK); 1045 rtl92cu_bb_block_on(hw); 1046 rtl_cam_reset_all_entry(hw); 1047 rtl92cu_enable_hw_security_config(hw); 1048 ppsc->rfpwr_state = ERFON; 1049 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1050 if (ppsc->rfpwr_state == ERFON) { 1051 rtl92c_phy_set_rfpath_switch(hw, 1); 1052 if (rtlphy->iqk_initialized) { 1053 rtl92c_phy_iq_calibrate(hw, true); 1054 } else { 1055 rtl92c_phy_iq_calibrate(hw, false); 1056 rtlphy->iqk_initialized = true; 1057 } 1058 rtl92c_dm_check_txpower_tracking(hw); 1059 rtl92c_phy_lc_calibrate(hw); 1060 } 1061 _rtl92cu_hw_configure(hw); 1062 _InitPABias(hw); 1063 rtl92c_dm_init(hw); 1064 exit: 1065 local_irq_restore(flags); 1066 return err; 1067 } 1068 1069 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw) 1070 { 1071 struct rtl_priv *rtlpriv = rtl_priv(hw); 1072 /************************************** 1073 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue 1074 b. RF path 0 offset 0x00 = 0x00 disable RF 1075 c. APSD_CTRL 0x600[7:0] = 0x40 1076 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine 1077 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine 1078 ***************************************/ 1079 u8 eRFPath = 0, value8 = 0; 1080 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1081 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0); 1082 1083 value8 |= APSDOFF; 1084 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/ 1085 value8 = 0; 1086 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); 1087 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/ 1088 value8 &= (~FEN_BB_GLB_RSTn); 1089 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/ 1090 } 1091 1092 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM) 1093 { 1094 struct rtl_priv *rtlpriv = rtl_priv(hw); 1095 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1096 1097 if (rtlhal->fw_version <= 0x20) { 1098 /***************************** 1099 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status 1100 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset) 1101 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE 1102 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable) 1103 ******************************/ 1104 u16 valu16 = 0; 1105 1106 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1107 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1108 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 & 1109 (~FEN_CPUEN))); /* reset MCU ,8051 */ 1110 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF; 1111 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1112 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */ 1113 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1114 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1115 FEN_CPUEN)); /* enable MCU ,8051 */ 1116 } else { 1117 u8 retry_cnts = 0; 1118 1119 /* IF fw in RAM code, do reset */ 1120 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) { 1121 /* reset MCU ready status */ 1122 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1123 /* 8051 reset by self */ 1124 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20); 1125 while ((retry_cnts++ < 100) && 1126 (FEN_CPUEN & rtl_read_word(rtlpriv, 1127 REG_SYS_FUNC_EN))) { 1128 udelay(50); 1129 } 1130 if (retry_cnts >= 100) { 1131 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1132 "#####=> 8051 reset failed!.........................\n"); 1133 /* if 8051 reset fail, reset MAC. */ 1134 rtl_write_byte(rtlpriv, 1135 REG_SYS_FUNC_EN + 1, 1136 0x50); 1137 udelay(100); 1138 } 1139 } 1140 /* Reset MAC and Enable 8051 */ 1141 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); 1142 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1143 } 1144 if (bWithoutHWSM) { 1145 /***************************** 1146 Without HW auto state machine 1147 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock 1148 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL 1149 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK 1150 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON 1151 ******************************/ 1152 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1153 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1154 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F); 1155 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9); 1156 } 1157 } 1158 1159 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw) 1160 { 1161 struct rtl_priv *rtlpriv = rtl_priv(hw); 1162 /***************************** 1163 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction 1164 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock 1165 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON 1166 ******************************/ 1167 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1168 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82); 1169 } 1170 1171 static void _DisableGPIO(struct ieee80211_hw *hw) 1172 { 1173 struct rtl_priv *rtlpriv = rtl_priv(hw); 1174 /*************************************** 1175 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 1176 k. Value = GPIO_PIN_CTRL[7:0] 1177 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level 1178 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 1179 n. LEDCFG 0x4C[15:0] = 0x8080 1180 ***************************************/ 1181 u8 value8; 1182 u16 value16; 1183 u32 value32; 1184 1185 /* 1. Disable GPIO[7:0] */ 1186 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000); 1187 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; 1188 value8 = (u8)(value32&0x000000FF); 1189 value32 |= ((value8<<8) | 0x00FF0000); 1190 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32); 1191 /* 2. Disable GPIO[10:8] */ 1192 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00); 1193 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F; 1194 value8 = (u8)(value16&0x000F); 1195 value16 |= ((value8<<4) | 0x0780); 1196 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16); 1197 /* 3. Disable LED0 & 1 */ 1198 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1199 } 1200 1201 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM) 1202 { 1203 struct rtl_priv *rtlpriv = rtl_priv(hw); 1204 u16 value16 = 0; 1205 u8 value8 = 0; 1206 1207 if (bWithoutHWSM) { 1208 /***************************** 1209 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power 1210 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power 1211 r. When driver call disable, the ASIC will turn off remaining 1212 clock automatically 1213 ******************************/ 1214 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1215 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 1216 value8 &= (~LDV12_EN); 1217 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 1218 } 1219 1220 /***************************** 1221 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode 1222 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend 1223 ******************************/ 1224 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1225 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); 1226 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16); 1227 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1228 } 1229 1230 static void _CardDisableHWSM(struct ieee80211_hw *hw) 1231 { 1232 /* ==== RF Off Sequence ==== */ 1233 _DisableRFAFEAndResetBB(hw); 1234 /* ==== Reset digital sequence ====== */ 1235 _ResetDigitalProcedure1(hw, false); 1236 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1237 _DisableGPIO(hw); 1238 /* ==== Disable analog sequence === */ 1239 _DisableAnalog(hw, false); 1240 } 1241 1242 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw) 1243 { 1244 /*==== RF Off Sequence ==== */ 1245 _DisableRFAFEAndResetBB(hw); 1246 /* ==== Reset digital sequence ====== */ 1247 _ResetDigitalProcedure1(hw, true); 1248 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1249 _DisableGPIO(hw); 1250 /* ==== Reset digital sequence ====== */ 1251 _ResetDigitalProcedure2(hw); 1252 /* ==== Disable analog sequence === */ 1253 _DisableAnalog(hw, true); 1254 } 1255 1256 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 1257 u8 set_bits, u8 clear_bits) 1258 { 1259 struct rtl_priv *rtlpriv = rtl_priv(hw); 1260 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1261 1262 rtlusb->reg_bcn_ctrl_val |= set_bits; 1263 rtlusb->reg_bcn_ctrl_val &= ~clear_bits; 1264 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 1265 } 1266 1267 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw) 1268 { 1269 struct rtl_priv *rtlpriv = rtl_priv(hw); 1270 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1271 u8 tmp1byte = 0; 1272 if (IS_NORMAL_CHIP(rtlhal->version)) { 1273 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1274 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1275 tmp1byte & (~BIT(6))); 1276 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 1277 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1278 tmp1byte &= ~(BIT(0)); 1279 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1280 } else { 1281 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1282 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6)); 1283 } 1284 } 1285 1286 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw) 1287 { 1288 struct rtl_priv *rtlpriv = rtl_priv(hw); 1289 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1290 u8 tmp1byte = 0; 1291 1292 if (IS_NORMAL_CHIP(rtlhal->version)) { 1293 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1294 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1295 tmp1byte | BIT(6)); 1296 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1297 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1298 tmp1byte |= BIT(0); 1299 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1300 } else { 1301 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1302 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6))); 1303 } 1304 } 1305 1306 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw) 1307 { 1308 struct rtl_priv *rtlpriv = rtl_priv(hw); 1309 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1310 1311 if (IS_NORMAL_CHIP(rtlhal->version)) 1312 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); 1313 else 1314 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1315 } 1316 1317 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw) 1318 { 1319 struct rtl_priv *rtlpriv = rtl_priv(hw); 1320 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1321 1322 if (IS_NORMAL_CHIP(rtlhal->version)) 1323 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); 1324 else 1325 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1326 } 1327 1328 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw, 1329 enum nl80211_iftype type) 1330 { 1331 struct rtl_priv *rtlpriv = rtl_priv(hw); 1332 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1333 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1334 1335 bt_msr &= 0xfc; 1336 if (type == NL80211_IFTYPE_UNSPECIFIED || type == 1337 NL80211_IFTYPE_STATION) { 1338 _rtl92cu_stop_tx_beacon(hw); 1339 _rtl92cu_enable_bcn_sub_func(hw); 1340 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) { 1341 _rtl92cu_resume_tx_beacon(hw); 1342 _rtl92cu_disable_bcn_sub_func(hw); 1343 } else { 1344 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1345 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n", 1346 type); 1347 } 1348 switch (type) { 1349 case NL80211_IFTYPE_UNSPECIFIED: 1350 bt_msr |= MSR_NOLINK; 1351 ledaction = LED_CTL_LINK; 1352 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1353 "Set Network type to NO LINK!\n"); 1354 break; 1355 case NL80211_IFTYPE_ADHOC: 1356 bt_msr |= MSR_ADHOC; 1357 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1358 "Set Network type to Ad Hoc!\n"); 1359 break; 1360 case NL80211_IFTYPE_STATION: 1361 bt_msr |= MSR_INFRA; 1362 ledaction = LED_CTL_LINK; 1363 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1364 "Set Network type to STA!\n"); 1365 break; 1366 case NL80211_IFTYPE_AP: 1367 bt_msr |= MSR_AP; 1368 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1369 "Set Network type to AP!\n"); 1370 break; 1371 default: 1372 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1373 "Network type %d not supported!\n", type); 1374 goto error_out; 1375 } 1376 rtl_write_byte(rtlpriv, MSR, bt_msr); 1377 rtlpriv->cfg->ops->led_control(hw, ledaction); 1378 if ((bt_msr & MSR_MASK) == MSR_AP) 1379 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1380 else 1381 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1382 return 0; 1383 error_out: 1384 return 1; 1385 } 1386 1387 void rtl92cu_card_disable(struct ieee80211_hw *hw) 1388 { 1389 struct rtl_priv *rtlpriv = rtl_priv(hw); 1390 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1391 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1392 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1393 enum nl80211_iftype opmode; 1394 1395 mac->link_state = MAC80211_NOLINK; 1396 opmode = NL80211_IFTYPE_UNSPECIFIED; 1397 _rtl92cu_set_media_status(hw, opmode); 1398 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1399 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1400 if (rtlusb->disableHWSM) 1401 _CardDisableHWSM(hw); 1402 else 1403 _CardDisableWithoutHWSM(hw); 1404 1405 /* after power off we should do iqk again */ 1406 rtlpriv->phy.iqk_initialized = false; 1407 } 1408 1409 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1410 { 1411 struct rtl_priv *rtlpriv = rtl_priv(hw); 1412 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1413 u32 reg_rcr; 1414 1415 if (rtlpriv->psc.rfpwr_state != ERFON) 1416 return; 1417 1418 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1419 1420 if (check_bssid) { 1421 u8 tmp; 1422 if (IS_NORMAL_CHIP(rtlhal->version)) { 1423 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1424 tmp = BIT(4); 1425 } else { 1426 reg_rcr |= RCR_CBSSID; 1427 tmp = BIT(4) | BIT(5); 1428 } 1429 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1430 (u8 *) (®_rcr)); 1431 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp); 1432 } else { 1433 u8 tmp; 1434 if (IS_NORMAL_CHIP(rtlhal->version)) { 1435 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1436 tmp = BIT(4); 1437 } else { 1438 reg_rcr &= ~RCR_CBSSID; 1439 tmp = BIT(4) | BIT(5); 1440 } 1441 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1442 rtlpriv->cfg->ops->set_hw_reg(hw, 1443 HW_VAR_RCR, (u8 *) (®_rcr)); 1444 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0); 1445 } 1446 } 1447 1448 /*========================================================================== */ 1449 1450 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1451 { 1452 struct rtl_priv *rtlpriv = rtl_priv(hw); 1453 1454 if (_rtl92cu_set_media_status(hw, type)) 1455 return -EOPNOTSUPP; 1456 1457 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1458 if (type != NL80211_IFTYPE_AP) 1459 rtl92cu_set_check_bssid(hw, true); 1460 } else { 1461 rtl92cu_set_check_bssid(hw, false); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static void _beacon_function_enable(struct ieee80211_hw *hw) 1468 { 1469 struct rtl_priv *rtlpriv = rtl_priv(hw); 1470 1471 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); 1472 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F); 1473 } 1474 1475 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw) 1476 { 1477 1478 struct rtl_priv *rtlpriv = rtl_priv(hw); 1479 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1480 u16 bcn_interval, atim_window; 1481 u32 value32; 1482 1483 bcn_interval = mac->beacon_interval; 1484 atim_window = 2; /*FIX MERGE */ 1485 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1486 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1487 _rtl92cu_init_beacon_parameters(hw); 1488 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 1489 /* 1490 * Force beacon frame transmission even after receiving beacon frame 1491 * from other ad hoc STA 1492 * 1493 * 1494 * Reset TSF Timer to zero, added by Roger. 2008.06.24 1495 */ 1496 value32 = rtl_read_dword(rtlpriv, REG_TCR); 1497 value32 &= ~TSFRST; 1498 rtl_write_dword(rtlpriv, REG_TCR, value32); 1499 value32 |= TSFRST; 1500 rtl_write_dword(rtlpriv, REG_TCR, value32); 1501 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD, 1502 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n", 1503 value32); 1504 /* TODO: Modify later (Find the right parameters) 1505 * NOTE: Fix test chip's bug (about contention windows's randomness) */ 1506 if ((mac->opmode == NL80211_IFTYPE_ADHOC) || 1507 (mac->opmode == NL80211_IFTYPE_MESH_POINT) || 1508 (mac->opmode == NL80211_IFTYPE_AP)) { 1509 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50); 1510 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50); 1511 } 1512 _beacon_function_enable(hw); 1513 } 1514 1515 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw) 1516 { 1517 struct rtl_priv *rtlpriv = rtl_priv(hw); 1518 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1519 u16 bcn_interval = mac->beacon_interval; 1520 1521 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n", 1522 bcn_interval); 1523 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1524 } 1525 1526 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw, 1527 u32 add_msr, u32 rm_msr) 1528 { 1529 } 1530 1531 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1532 { 1533 struct rtl_priv *rtlpriv = rtl_priv(hw); 1534 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1535 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1536 1537 switch (variable) { 1538 case HW_VAR_RCR: 1539 *((u32 *)(val)) = mac->rx_conf; 1540 break; 1541 case HW_VAR_RF_STATE: 1542 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 1543 break; 1544 case HW_VAR_FWLPS_RF_ON:{ 1545 enum rf_pwrstate rfState; 1546 u32 val_rcr; 1547 1548 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 1549 (u8 *)(&rfState)); 1550 if (rfState == ERFOFF) { 1551 *((bool *) (val)) = true; 1552 } else { 1553 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 1554 val_rcr &= 0x00070000; 1555 if (val_rcr) 1556 *((bool *) (val)) = false; 1557 else 1558 *((bool *) (val)) = true; 1559 } 1560 break; 1561 } 1562 case HW_VAR_FW_PSMODE_STATUS: 1563 *((bool *) (val)) = ppsc->fw_current_inpsmode; 1564 break; 1565 case HW_VAR_CORRECT_TSF:{ 1566 u64 tsf; 1567 u32 *ptsf_low = (u32 *)&tsf; 1568 u32 *ptsf_high = ((u32 *)&tsf) + 1; 1569 1570 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 1571 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 1572 *((u64 *)(val)) = tsf; 1573 break; 1574 } 1575 case HW_VAR_MGT_FILTER: 1576 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0); 1577 break; 1578 case HW_VAR_CTRL_FILTER: 1579 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1); 1580 break; 1581 case HW_VAR_DATA_FILTER: 1582 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2); 1583 break; 1584 case HAL_DEF_WOWLAN: 1585 break; 1586 default: 1587 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1588 "switch case not processed\n"); 1589 break; 1590 } 1591 } 1592 1593 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) 1594 { 1595 /* Currently nothing happens here. 1596 * Traffic stops after some seconds in WPA2 802.11n mode. 1597 * Maybe because rtl8192cu chip should be set from here? 1598 * If I understand correctly, the realtek vendor driver sends some urbs 1599 * if its "here". 1600 * 1601 * This is maybe necessary: 1602 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb); 1603 */ 1604 return true; 1605 } 1606 1607 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1608 { 1609 struct rtl_priv *rtlpriv = rtl_priv(hw); 1610 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1611 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1612 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1613 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1614 enum wireless_mode wirelessmode = mac->mode; 1615 u8 idx = 0; 1616 1617 switch (variable) { 1618 case HW_VAR_ETHER_ADDR:{ 1619 for (idx = 0; idx < ETH_ALEN; idx++) { 1620 rtl_write_byte(rtlpriv, (REG_MACID + idx), 1621 val[idx]); 1622 } 1623 break; 1624 } 1625 case HW_VAR_BASIC_RATE:{ 1626 u16 rate_cfg = ((u16 *) val)[0]; 1627 u8 rate_index = 0; 1628 1629 rate_cfg &= 0x15f; 1630 /* TODO */ 1631 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO 1632 * && ((rate_cfg & 0x150) == 0)) { 1633 * rate_cfg |= 0x010; 1634 * } */ 1635 rate_cfg |= 0x01; 1636 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 1637 rtl_write_byte(rtlpriv, REG_RRSR + 1, 1638 (rate_cfg >> 8) & 0xff); 1639 while (rate_cfg > 0x1) { 1640 rate_cfg >>= 1; 1641 rate_index++; 1642 } 1643 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 1644 rate_index); 1645 break; 1646 } 1647 case HW_VAR_BSSID:{ 1648 for (idx = 0; idx < ETH_ALEN; idx++) { 1649 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 1650 val[idx]); 1651 } 1652 break; 1653 } 1654 case HW_VAR_SIFS:{ 1655 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); 1656 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]); 1657 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 1658 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 1659 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); 1660 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); 1661 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n"); 1662 break; 1663 } 1664 case HW_VAR_SLOT_TIME:{ 1665 u8 e_aci; 1666 u8 QOS_MODE = 1; 1667 1668 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 1669 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1670 "HW_VAR_SLOT_TIME %x\n", val[0]); 1671 if (QOS_MODE) { 1672 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 1673 rtlpriv->cfg->ops->set_hw_reg(hw, 1674 HW_VAR_AC_PARAM, 1675 &e_aci); 1676 } else { 1677 u8 sifstime = 0; 1678 u8 u1bAIFS; 1679 1680 if (IS_WIRELESS_MODE_A(wirelessmode) || 1681 IS_WIRELESS_MODE_N_24G(wirelessmode) || 1682 IS_WIRELESS_MODE_N_5G(wirelessmode)) 1683 sifstime = 16; 1684 else 1685 sifstime = 10; 1686 u1bAIFS = sifstime + (2 * val[0]); 1687 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM, 1688 u1bAIFS); 1689 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM, 1690 u1bAIFS); 1691 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM, 1692 u1bAIFS); 1693 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM, 1694 u1bAIFS); 1695 } 1696 break; 1697 } 1698 case HW_VAR_ACK_PREAMBLE:{ 1699 u8 reg_tmp; 1700 u8 short_preamble = (bool)*val; 1701 reg_tmp = 0; 1702 if (short_preamble) 1703 reg_tmp |= 0x80; 1704 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 1705 break; 1706 } 1707 case HW_VAR_AMPDU_MIN_SPACE:{ 1708 u8 min_spacing_to_set; 1709 u8 sec_min_space; 1710 1711 min_spacing_to_set = *val; 1712 if (min_spacing_to_set <= 7) { 1713 switch (rtlpriv->sec.pairwise_enc_algorithm) { 1714 case NO_ENCRYPTION: 1715 case AESCCMP_ENCRYPTION: 1716 sec_min_space = 0; 1717 break; 1718 case WEP40_ENCRYPTION: 1719 case WEP104_ENCRYPTION: 1720 case TKIP_ENCRYPTION: 1721 sec_min_space = 6; 1722 break; 1723 default: 1724 sec_min_space = 7; 1725 break; 1726 } 1727 if (min_spacing_to_set < sec_min_space) 1728 min_spacing_to_set = sec_min_space; 1729 mac->min_space_cfg = ((mac->min_space_cfg & 1730 0xf8) | 1731 min_spacing_to_set); 1732 *val = min_spacing_to_set; 1733 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1734 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 1735 mac->min_space_cfg); 1736 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1737 mac->min_space_cfg); 1738 } 1739 break; 1740 } 1741 case HW_VAR_SHORTGI_DENSITY:{ 1742 u8 density_to_set; 1743 1744 density_to_set = *val; 1745 density_to_set &= 0x1f; 1746 mac->min_space_cfg &= 0x07; 1747 mac->min_space_cfg |= (density_to_set << 3); 1748 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1749 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 1750 mac->min_space_cfg); 1751 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1752 mac->min_space_cfg); 1753 break; 1754 } 1755 case HW_VAR_AMPDU_FACTOR:{ 1756 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 1757 u8 factor_toset; 1758 u8 *p_regtoset = NULL; 1759 u8 index = 0; 1760 1761 p_regtoset = regtoset_normal; 1762 factor_toset = *val; 1763 if (factor_toset <= 3) { 1764 factor_toset = (1 << (factor_toset + 2)); 1765 if (factor_toset > 0xf) 1766 factor_toset = 0xf; 1767 for (index = 0; index < 4; index++) { 1768 if ((p_regtoset[index] & 0xf0) > 1769 (factor_toset << 4)) 1770 p_regtoset[index] = 1771 (p_regtoset[index] & 0x0f) 1772 | (factor_toset << 4); 1773 if ((p_regtoset[index] & 0x0f) > 1774 factor_toset) 1775 p_regtoset[index] = 1776 (p_regtoset[index] & 0xf0) 1777 | (factor_toset); 1778 rtl_write_byte(rtlpriv, 1779 (REG_AGGLEN_LMT + index), 1780 p_regtoset[index]); 1781 } 1782 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1783 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 1784 factor_toset); 1785 } 1786 break; 1787 } 1788 case HW_VAR_AC_PARAM:{ 1789 u8 e_aci = *val; 1790 u32 u4b_ac_param; 1791 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min); 1792 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max); 1793 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op); 1794 1795 u4b_ac_param = (u32) mac->ac[e_aci].aifs; 1796 u4b_ac_param |= (u32) ((cw_min & 0xF) << 1797 AC_PARAM_ECW_MIN_OFFSET); 1798 u4b_ac_param |= (u32) ((cw_max & 0xF) << 1799 AC_PARAM_ECW_MAX_OFFSET); 1800 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET; 1801 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1802 "queue:%x, ac_param:%x\n", 1803 e_aci, u4b_ac_param); 1804 switch (e_aci) { 1805 case AC1_BK: 1806 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 1807 u4b_ac_param); 1808 break; 1809 case AC0_BE: 1810 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 1811 u4b_ac_param); 1812 break; 1813 case AC2_VI: 1814 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 1815 u4b_ac_param); 1816 break; 1817 case AC3_VO: 1818 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 1819 u4b_ac_param); 1820 break; 1821 default: 1822 RT_ASSERT(false, "invalid aci: %d !\n", 1823 e_aci); 1824 break; 1825 } 1826 break; 1827 } 1828 case HW_VAR_RCR:{ 1829 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 1830 mac->rx_conf = ((u32 *) (val))[0]; 1831 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, 1832 "### Set RCR(0x%08x) ###\n", mac->rx_conf); 1833 break; 1834 } 1835 case HW_VAR_RETRY_LIMIT:{ 1836 u8 retry_limit = val[0]; 1837 1838 rtl_write_word(rtlpriv, REG_RL, 1839 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 1840 retry_limit << RETRY_LIMIT_LONG_SHIFT); 1841 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, 1842 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n", 1843 retry_limit); 1844 break; 1845 } 1846 case HW_VAR_DUAL_TSF_RST: 1847 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 1848 break; 1849 case HW_VAR_EFUSE_BYTES: 1850 rtlefuse->efuse_usedbytes = *((u16 *) val); 1851 break; 1852 case HW_VAR_EFUSE_USAGE: 1853 rtlefuse->efuse_usedpercentage = *val; 1854 break; 1855 case HW_VAR_IO_CMD: 1856 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 1857 break; 1858 case HW_VAR_WPA_CONFIG: 1859 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 1860 break; 1861 case HW_VAR_SET_RPWM:{ 1862 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM); 1863 1864 if (rpwm_val & BIT(7)) 1865 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val); 1866 else 1867 rtl_write_byte(rtlpriv, REG_USB_HRPWM, 1868 *val | BIT(7)); 1869 break; 1870 } 1871 case HW_VAR_H2C_FW_PWRMODE:{ 1872 u8 psmode = *val; 1873 1874 if ((psmode != FW_PS_ACTIVE_MODE) && 1875 (!IS_92C_SERIAL(rtlhal->version))) 1876 rtl92c_dm_rf_saving(hw, true); 1877 rtl92c_set_fw_pwrmode_cmd(hw, (*val)); 1878 break; 1879 } 1880 case HW_VAR_FW_PSMODE_STATUS: 1881 ppsc->fw_current_inpsmode = *((bool *) val); 1882 break; 1883 case HW_VAR_H2C_FW_JOINBSSRPT:{ 1884 u8 mstatus = *val; 1885 u8 tmp_reg422; 1886 bool recover = false; 1887 1888 if (mstatus == RT_MEDIA_CONNECT) { 1889 rtlpriv->cfg->ops->set_hw_reg(hw, 1890 HW_VAR_AID, NULL); 1891 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03); 1892 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1893 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1894 tmp_reg422 = rtl_read_byte(rtlpriv, 1895 REG_FWHW_TXQ_CTRL + 2); 1896 if (tmp_reg422 & BIT(6)) 1897 recover = true; 1898 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1899 tmp_reg422 & (~BIT(6))); 1900 rtl92c_set_fw_rsvdpagepkt(hw, 1901 &usb_cmd_send_packet); 1902 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1903 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1904 if (recover) 1905 rtl_write_byte(rtlpriv, 1906 REG_FWHW_TXQ_CTRL + 2, 1907 tmp_reg422 | BIT(6)); 1908 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1909 } 1910 rtl92c_set_fw_joinbss_report_cmd(hw, (*val)); 1911 break; 1912 } 1913 case HW_VAR_AID:{ 1914 u16 u2btmp; 1915 1916 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 1917 u2btmp &= 0xC000; 1918 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 1919 (u2btmp | mac->assoc_id)); 1920 break; 1921 } 1922 case HW_VAR_CORRECT_TSF:{ 1923 u8 btype_ibss = val[0]; 1924 1925 if (btype_ibss) 1926 _rtl92cu_stop_tx_beacon(hw); 1927 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1928 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf & 1929 0xffffffff)); 1930 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 1931 (u32)((mac->tsf >> 32) & 0xffffffff)); 1932 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1933 if (btype_ibss) 1934 _rtl92cu_resume_tx_beacon(hw); 1935 break; 1936 } 1937 case HW_VAR_MGT_FILTER: 1938 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val); 1939 mac->rx_mgt_filter = *(u16 *)val; 1940 break; 1941 case HW_VAR_CTRL_FILTER: 1942 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val); 1943 mac->rx_ctrl_filter = *(u16 *)val; 1944 break; 1945 case HW_VAR_DATA_FILTER: 1946 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val); 1947 mac->rx_data_filter = *(u16 *)val; 1948 break; 1949 case HW_VAR_KEEP_ALIVE:{ 1950 u8 array[2]; 1951 array[0] = 0xff; 1952 array[1] = *((u8 *)val); 1953 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, 1954 array); 1955 break; 1956 } 1957 default: 1958 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1959 "switch case not processed\n"); 1960 break; 1961 } 1962 } 1963 1964 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw, 1965 struct ieee80211_sta *sta) 1966 { 1967 struct rtl_priv *rtlpriv = rtl_priv(hw); 1968 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1969 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1970 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1971 u32 ratr_value; 1972 u8 ratr_index = 0; 1973 u8 nmode = mac->ht_enable; 1974 u8 mimo_ps = IEEE80211_SMPS_OFF; 1975 u16 shortgi_rate; 1976 u32 tmp_ratr_value; 1977 u8 curtxbw_40mhz = mac->bw_40; 1978 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1979 1 : 0; 1980 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1981 1 : 0; 1982 enum wireless_mode wirelessmode = mac->mode; 1983 1984 if (rtlhal->current_bandtype == BAND_ON_5G) 1985 ratr_value = sta->supp_rates[1] << 4; 1986 else 1987 ratr_value = sta->supp_rates[0]; 1988 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1989 ratr_value = 0xfff; 1990 1991 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1992 sta->ht_cap.mcs.rx_mask[0] << 12); 1993 switch (wirelessmode) { 1994 case WIRELESS_MODE_B: 1995 if (ratr_value & 0x0000000c) 1996 ratr_value &= 0x0000000d; 1997 else 1998 ratr_value &= 0x0000000f; 1999 break; 2000 case WIRELESS_MODE_G: 2001 ratr_value &= 0x00000FF5; 2002 break; 2003 case WIRELESS_MODE_N_24G: 2004 case WIRELESS_MODE_N_5G: 2005 nmode = 1; 2006 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2007 ratr_value &= 0x0007F005; 2008 } else { 2009 u32 ratr_mask; 2010 2011 if (get_rf_type(rtlphy) == RF_1T2R || 2012 get_rf_type(rtlphy) == RF_1T1R) 2013 ratr_mask = 0x000ff005; 2014 else 2015 ratr_mask = 0x0f0ff005; 2016 2017 ratr_value &= ratr_mask; 2018 } 2019 break; 2020 default: 2021 if (rtlphy->rf_type == RF_1T2R) 2022 ratr_value &= 0x000ff0ff; 2023 else 2024 ratr_value &= 0x0f0ff0ff; 2025 2026 break; 2027 } 2028 2029 ratr_value &= 0x0FFFFFFF; 2030 2031 if (nmode && ((curtxbw_40mhz && 2032 curshortgi_40mhz) || (!curtxbw_40mhz && 2033 curshortgi_20mhz))) { 2034 2035 ratr_value |= 0x10000000; 2036 tmp_ratr_value = (ratr_value >> 12); 2037 2038 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2039 if ((1 << shortgi_rate) & tmp_ratr_value) 2040 break; 2041 } 2042 2043 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2044 (shortgi_rate << 4) | (shortgi_rate); 2045 } 2046 2047 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 2048 2049 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2050 rtl_read_dword(rtlpriv, REG_ARFR0)); 2051 } 2052 2053 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, 2054 struct ieee80211_sta *sta, 2055 u8 rssi_level) 2056 { 2057 struct rtl_priv *rtlpriv = rtl_priv(hw); 2058 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2059 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2060 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2061 struct rtl_sta_info *sta_entry = NULL; 2062 u32 ratr_bitmap; 2063 u8 ratr_index; 2064 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2065 u8 curshortgi_40mhz = curtxbw_40mhz && 2066 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2067 1 : 0; 2068 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2069 1 : 0; 2070 enum wireless_mode wirelessmode = 0; 2071 bool shortgi = false; 2072 u8 rate_mask[5]; 2073 u8 macid = 0; 2074 u8 mimo_ps = IEEE80211_SMPS_OFF; 2075 2076 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2077 wirelessmode = sta_entry->wireless_mode; 2078 if (mac->opmode == NL80211_IFTYPE_STATION || 2079 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2080 curtxbw_40mhz = mac->bw_40; 2081 else if (mac->opmode == NL80211_IFTYPE_AP || 2082 mac->opmode == NL80211_IFTYPE_ADHOC) 2083 macid = sta->aid + 1; 2084 2085 if (rtlhal->current_bandtype == BAND_ON_5G) 2086 ratr_bitmap = sta->supp_rates[1] << 4; 2087 else 2088 ratr_bitmap = sta->supp_rates[0]; 2089 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2090 ratr_bitmap = 0xfff; 2091 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2092 sta->ht_cap.mcs.rx_mask[0] << 12); 2093 switch (wirelessmode) { 2094 case WIRELESS_MODE_B: 2095 ratr_index = RATR_INX_WIRELESS_B; 2096 if (ratr_bitmap & 0x0000000c) 2097 ratr_bitmap &= 0x0000000d; 2098 else 2099 ratr_bitmap &= 0x0000000f; 2100 break; 2101 case WIRELESS_MODE_G: 2102 ratr_index = RATR_INX_WIRELESS_GB; 2103 2104 if (rssi_level == 1) 2105 ratr_bitmap &= 0x00000f00; 2106 else if (rssi_level == 2) 2107 ratr_bitmap &= 0x00000ff0; 2108 else 2109 ratr_bitmap &= 0x00000ff5; 2110 break; 2111 case WIRELESS_MODE_A: 2112 ratr_index = RATR_INX_WIRELESS_A; 2113 ratr_bitmap &= 0x00000ff0; 2114 break; 2115 case WIRELESS_MODE_N_24G: 2116 case WIRELESS_MODE_N_5G: 2117 ratr_index = RATR_INX_WIRELESS_NGB; 2118 2119 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2120 if (rssi_level == 1) 2121 ratr_bitmap &= 0x00070000; 2122 else if (rssi_level == 2) 2123 ratr_bitmap &= 0x0007f000; 2124 else 2125 ratr_bitmap &= 0x0007f005; 2126 } else { 2127 if (rtlphy->rf_type == RF_1T2R || 2128 rtlphy->rf_type == RF_1T1R) { 2129 if (curtxbw_40mhz) { 2130 if (rssi_level == 1) 2131 ratr_bitmap &= 0x000f0000; 2132 else if (rssi_level == 2) 2133 ratr_bitmap &= 0x000ff000; 2134 else 2135 ratr_bitmap &= 0x000ff015; 2136 } else { 2137 if (rssi_level == 1) 2138 ratr_bitmap &= 0x000f0000; 2139 else if (rssi_level == 2) 2140 ratr_bitmap &= 0x000ff000; 2141 else 2142 ratr_bitmap &= 0x000ff005; 2143 } 2144 } else { 2145 if (curtxbw_40mhz) { 2146 if (rssi_level == 1) 2147 ratr_bitmap &= 0x0f0f0000; 2148 else if (rssi_level == 2) 2149 ratr_bitmap &= 0x0f0ff000; 2150 else 2151 ratr_bitmap &= 0x0f0ff015; 2152 } else { 2153 if (rssi_level == 1) 2154 ratr_bitmap &= 0x0f0f0000; 2155 else if (rssi_level == 2) 2156 ratr_bitmap &= 0x0f0ff000; 2157 else 2158 ratr_bitmap &= 0x0f0ff005; 2159 } 2160 } 2161 } 2162 2163 if ((curtxbw_40mhz && curshortgi_40mhz) || 2164 (!curtxbw_40mhz && curshortgi_20mhz)) { 2165 2166 if (macid == 0) 2167 shortgi = true; 2168 else if (macid == 1) 2169 shortgi = false; 2170 } 2171 break; 2172 default: 2173 ratr_index = RATR_INX_WIRELESS_NGB; 2174 2175 if (rtlphy->rf_type == RF_1T2R) 2176 ratr_bitmap &= 0x000ff0ff; 2177 else 2178 ratr_bitmap &= 0x0f0ff0ff; 2179 break; 2180 } 2181 sta_entry->ratr_index = ratr_index; 2182 2183 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2184 "ratr_bitmap :%x\n", ratr_bitmap); 2185 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2186 (ratr_index << 28); 2187 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2188 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2189 "Rate_index:%x, ratr_val:%x, %5phC\n", 2190 ratr_index, ratr_bitmap, rate_mask); 2191 memcpy(rtlpriv->rate_mask, rate_mask, 5); 2192 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a 2193 * "scheduled while atomic" if called directly */ 2194 schedule_work(&rtlpriv->works.fill_h2c_cmd); 2195 2196 if (macid != 0) 2197 sta_entry->ratr_index = ratr_index; 2198 } 2199 2200 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw, 2201 struct ieee80211_sta *sta, 2202 u8 rssi_level) 2203 { 2204 struct rtl_priv *rtlpriv = rtl_priv(hw); 2205 2206 if (rtlpriv->dm.useramask) 2207 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level); 2208 else 2209 rtl92cu_update_hal_rate_table(hw, sta); 2210 } 2211 2212 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw) 2213 { 2214 struct rtl_priv *rtlpriv = rtl_priv(hw); 2215 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2216 u16 sifs_timer; 2217 2218 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2219 &mac->slot_time); 2220 if (!mac->ht_enable) 2221 sifs_timer = 0x0a0a; 2222 else 2223 sifs_timer = 0x0e0e; 2224 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2225 } 2226 2227 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid) 2228 { 2229 struct rtl_priv *rtlpriv = rtl_priv(hw); 2230 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2231 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2232 u8 u1tmp = 0; 2233 bool actuallyset = false; 2234 unsigned long flag = 0; 2235 /* to do - usb autosuspend */ 2236 u8 usb_autosuspend = 0; 2237 2238 if (ppsc->swrf_processing) 2239 return false; 2240 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2241 if (ppsc->rfchange_inprogress) { 2242 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2243 return false; 2244 } else { 2245 ppsc->rfchange_inprogress = true; 2246 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2247 } 2248 cur_rfstate = ppsc->rfpwr_state; 2249 if (usb_autosuspend) { 2250 /* to do................... */ 2251 } else { 2252 if (ppsc->pwrdown_mode) { 2253 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR); 2254 e_rfpowerstate_toset = (u1tmp & BIT(7)) ? 2255 ERFOFF : ERFON; 2256 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2257 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); 2258 } else { 2259 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 2260 rtl_read_byte(rtlpriv, 2261 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2262 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2263 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? 2264 ERFON : ERFOFF; 2265 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2266 "GPIO_IN=%02x\n", u1tmp); 2267 } 2268 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n", 2269 e_rfpowerstate_toset); 2270 } 2271 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2272 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2273 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2274 ppsc->hwradiooff = false; 2275 actuallyset = true; 2276 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset == 2277 ERFOFF)) { 2278 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2279 "GPIOChangeRF - HW Radio OFF\n"); 2280 ppsc->hwradiooff = true; 2281 actuallyset = true; 2282 } else { 2283 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2284 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n", 2285 ppsc->hwradiooff, e_rfpowerstate_toset); 2286 } 2287 if (actuallyset) { 2288 ppsc->hwradiooff = true; 2289 if (e_rfpowerstate_toset == ERFON) { 2290 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 2291 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) 2292 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2293 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2294 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3)) 2295 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2296 } 2297 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2298 ppsc->rfchange_inprogress = false; 2299 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2300 /* For power down module, we need to enable register block 2301 * contrl reg at 0x1c. Then enable power down control bit 2302 * of register 0x04 BIT4 and BIT15 as 1. 2303 */ 2304 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) { 2305 /* Enable register area 0x0-0xc. */ 2306 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 2307 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812); 2308 } 2309 if (e_rfpowerstate_toset == ERFOFF) { 2310 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2311 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2312 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2313 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2314 } 2315 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) { 2316 /* Enter D3 or ASPM after GPIO had been done. */ 2317 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2318 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2319 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2320 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2321 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2322 ppsc->rfchange_inprogress = false; 2323 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2324 } else { 2325 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2326 ppsc->rfchange_inprogress = false; 2327 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2328 } 2329 *valid = 1; 2330 return !ppsc->hwradiooff; 2331 } 2332