xref: /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c (revision 73aea586d6c58f55799f6130e19321ff7b574c3d)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "../rtl8192c/dm_common.h"
15 #include "../rtl8192c/fw_common.h"
16 #include "../rtl8192c/phy_common.h"
17 #include "dm.h"
18 #include "led.h"
19 #include "hw.h"
20 
21 #define LLT_CONFIG	5
22 
23 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
24 				      u8 set_bits, u8 clear_bits)
25 {
26 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
27 	struct rtl_priv *rtlpriv = rtl_priv(hw);
28 
29 	rtlpci->reg_bcn_ctrl_val |= set_bits;
30 	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
31 
32 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
33 }
34 
35 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
36 {
37 	struct rtl_priv *rtlpriv = rtl_priv(hw);
38 	u8 tmp1byte;
39 
40 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
41 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
42 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
43 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
44 	tmp1byte &= ~(BIT(0));
45 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
46 }
47 
48 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
49 {
50 	struct rtl_priv *rtlpriv = rtl_priv(hw);
51 	u8 tmp1byte;
52 
53 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
54 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
55 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
56 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
57 	tmp1byte |= BIT(0);
58 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
59 }
60 
61 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
62 {
63 	_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
64 }
65 
66 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
67 {
68 	_rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
69 }
70 
71 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
72 {
73 	struct rtl_priv *rtlpriv = rtl_priv(hw);
74 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 
77 	switch (variable) {
78 	case HW_VAR_RCR:
79 		*((u32 *) (val)) = rtlpci->receive_config;
80 		break;
81 	case HW_VAR_RF_STATE:
82 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
83 		break;
84 	case HW_VAR_FWLPS_RF_ON:{
85 			enum rf_pwrstate rfstate;
86 			u32 val_rcr;
87 
88 			rtlpriv->cfg->ops->get_hw_reg(hw,
89 						      HW_VAR_RF_STATE,
90 						      (u8 *)(&rfstate));
91 			if (rfstate == ERFOFF) {
92 				*((bool *) (val)) = true;
93 			} else {
94 				val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
95 				val_rcr &= 0x00070000;
96 				if (val_rcr)
97 					*((bool *) (val)) = false;
98 				else
99 					*((bool *) (val)) = true;
100 			}
101 			break;
102 		}
103 	case HW_VAR_FW_PSMODE_STATUS:
104 		*((bool *) (val)) = ppsc->fw_current_inpsmode;
105 		break;
106 	case HW_VAR_CORRECT_TSF:{
107 		u64 tsf;
108 		u32 *ptsf_low = (u32 *)&tsf;
109 		u32 *ptsf_high = ((u32 *)&tsf) + 1;
110 
111 		*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
112 		*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
113 
114 		*((u64 *) (val)) = tsf;
115 
116 		break;
117 		}
118 	case HAL_DEF_WOWLAN:
119 		break;
120 	default:
121 		pr_err("switch case %#x not processed\n", variable);
122 		break;
123 	}
124 }
125 
126 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
127 {
128 	struct rtl_priv *rtlpriv = rtl_priv(hw);
129 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
130 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
131 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
132 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
133 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
134 	u8 idx;
135 
136 	switch (variable) {
137 	case HW_VAR_ETHER_ADDR:{
138 			for (idx = 0; idx < ETH_ALEN; idx++) {
139 				rtl_write_byte(rtlpriv, (REG_MACID + idx),
140 					       val[idx]);
141 			}
142 			break;
143 		}
144 	case HW_VAR_BASIC_RATE:{
145 			u16 rate_cfg = ((u16 *) val)[0];
146 			u8 rate_index = 0;
147 
148 			rate_cfg &= 0x15f;
149 			rate_cfg |= 0x01;
150 			rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
151 			rtl_write_byte(rtlpriv, REG_RRSR + 1,
152 				       (rate_cfg >> 8) & 0xff);
153 			while (rate_cfg > 0x1) {
154 				rate_cfg = (rate_cfg >> 1);
155 				rate_index++;
156 			}
157 			rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
158 				       rate_index);
159 			break;
160 		}
161 	case HW_VAR_BSSID:{
162 			for (idx = 0; idx < ETH_ALEN; idx++) {
163 				rtl_write_byte(rtlpriv, (REG_BSSID + idx),
164 					       val[idx]);
165 			}
166 			break;
167 		}
168 	case HW_VAR_SIFS:{
169 			rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
170 			rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
171 
172 			rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
173 			rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
174 
175 			if (!mac->ht_enable)
176 				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
177 					       0x0e0e);
178 			else
179 				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
180 					       *((u16 *) val));
181 			break;
182 		}
183 	case HW_VAR_SLOT_TIME:{
184 			u8 e_aci;
185 
186 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
187 				"HW_VAR_SLOT_TIME %x\n", val[0]);
188 
189 			rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
190 
191 			for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
192 				rtlpriv->cfg->ops->set_hw_reg(hw,
193 							      HW_VAR_AC_PARAM,
194 							      &e_aci);
195 			}
196 			break;
197 		}
198 	case HW_VAR_ACK_PREAMBLE:{
199 			u8 reg_tmp;
200 			u8 short_preamble = (bool)*val;
201 
202 			reg_tmp = (mac->cur_40_prime_sc) << 5;
203 			if (short_preamble)
204 				reg_tmp |= 0x80;
205 
206 			rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
207 			break;
208 		}
209 	case HW_VAR_AMPDU_MIN_SPACE:{
210 			u8 min_spacing_to_set;
211 
212 			min_spacing_to_set = *val;
213 			if (min_spacing_to_set <= 7) {
214 
215 				mac->min_space_cfg = ((mac->min_space_cfg &
216 						       0xf8) |
217 						      min_spacing_to_set);
218 
219 				*val = min_spacing_to_set;
220 
221 				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
222 					"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
223 					mac->min_space_cfg);
224 
225 				rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
226 					       mac->min_space_cfg);
227 			}
228 			break;
229 		}
230 	case HW_VAR_SHORTGI_DENSITY:{
231 			u8 density_to_set;
232 
233 			density_to_set = *val;
234 			mac->min_space_cfg |= (density_to_set << 3);
235 
236 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
237 				"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
238 				mac->min_space_cfg);
239 
240 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
241 				       mac->min_space_cfg);
242 
243 			break;
244 		}
245 	case HW_VAR_AMPDU_FACTOR:{
246 			u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
247 			u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
248 
249 			u8 factor_toset;
250 			u8 *p_regtoset = NULL;
251 			u8 index = 0;
252 
253 			if ((rtlpriv->btcoexist.bt_coexistence) &&
254 			    (rtlpriv->btcoexist.bt_coexist_type ==
255 			    BT_CSR_BC4))
256 				p_regtoset = regtoset_bt;
257 			else
258 				p_regtoset = regtoset_normal;
259 
260 			factor_toset = *(val);
261 			if (factor_toset <= 3) {
262 				factor_toset = (1 << (factor_toset + 2));
263 				if (factor_toset > 0xf)
264 					factor_toset = 0xf;
265 
266 				for (index = 0; index < 4; index++) {
267 					if ((p_regtoset[index] & 0xf0) >
268 					    (factor_toset << 4))
269 						p_regtoset[index] =
270 						    (p_regtoset[index] & 0x0f) |
271 						    (factor_toset << 4);
272 
273 					if ((p_regtoset[index] & 0x0f) >
274 					    factor_toset)
275 						p_regtoset[index] =
276 						    (p_regtoset[index] & 0xf0) |
277 						    (factor_toset);
278 
279 					rtl_write_byte(rtlpriv,
280 						       (REG_AGGLEN_LMT + index),
281 						       p_regtoset[index]);
282 
283 				}
284 
285 				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
286 					"Set HW_VAR_AMPDU_FACTOR: %#x\n",
287 					factor_toset);
288 			}
289 			break;
290 		}
291 	case HW_VAR_AC_PARAM:{
292 			u8 e_aci = *(val);
293 
294 			rtl92c_dm_init_edca_turbo(hw);
295 
296 			if (rtlpci->acm_method != EACMWAY2_SW)
297 				rtlpriv->cfg->ops->set_hw_reg(hw,
298 							      HW_VAR_ACM_CTRL,
299 							      (&e_aci));
300 			break;
301 		}
302 	case HW_VAR_ACM_CTRL:{
303 			u8 e_aci = *(val);
304 			union aci_aifsn *p_aci_aifsn =
305 			    (union aci_aifsn *)(&(mac->ac[0].aifs));
306 			u8 acm = p_aci_aifsn->f.acm;
307 			u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
308 
309 			acm_ctrl =
310 			    acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
311 
312 			if (acm) {
313 				switch (e_aci) {
314 				case AC0_BE:
315 					acm_ctrl |= ACMHW_BEQEN;
316 					break;
317 				case AC2_VI:
318 					acm_ctrl |= ACMHW_VIQEN;
319 					break;
320 				case AC3_VO:
321 					acm_ctrl |= ACMHW_VOQEN;
322 					break;
323 				default:
324 					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
325 						"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
326 						acm);
327 					break;
328 				}
329 			} else {
330 				switch (e_aci) {
331 				case AC0_BE:
332 					acm_ctrl &= (~ACMHW_BEQEN);
333 					break;
334 				case AC2_VI:
335 					acm_ctrl &= (~ACMHW_VIQEN);
336 					break;
337 				case AC3_VO:
338 					acm_ctrl &= (~ACMHW_VOQEN);
339 					break;
340 				default:
341 					pr_err("switch case %#x not processed\n",
342 					       e_aci);
343 					break;
344 				}
345 			}
346 
347 			rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
348 				"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
349 				acm_ctrl);
350 			rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
351 			break;
352 		}
353 	case HW_VAR_RCR:{
354 			rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
355 			rtlpci->receive_config = ((u32 *) (val))[0];
356 			break;
357 		}
358 	case HW_VAR_RETRY_LIMIT:{
359 			u8 retry_limit = val[0];
360 
361 			rtl_write_word(rtlpriv, REG_RL,
362 				       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
363 				       retry_limit << RETRY_LIMIT_LONG_SHIFT);
364 			break;
365 		}
366 	case HW_VAR_DUAL_TSF_RST:
367 		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
368 		break;
369 	case HW_VAR_EFUSE_BYTES:
370 		rtlefuse->efuse_usedbytes = *((u16 *) val);
371 		break;
372 	case HW_VAR_EFUSE_USAGE:
373 		rtlefuse->efuse_usedpercentage = *val;
374 		break;
375 	case HW_VAR_IO_CMD:
376 		rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
377 		break;
378 	case HW_VAR_WPA_CONFIG:
379 		rtl_write_byte(rtlpriv, REG_SECCFG, *val);
380 		break;
381 	case HW_VAR_SET_RPWM:{
382 			u8 rpwm_val;
383 
384 			rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
385 			udelay(1);
386 
387 			if (rpwm_val & BIT(7)) {
388 				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
389 			} else {
390 				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
391 					       *val | BIT(7));
392 			}
393 
394 			break;
395 		}
396 	case HW_VAR_H2C_FW_PWRMODE:{
397 			u8 psmode = *val;
398 
399 			if ((psmode != FW_PS_ACTIVE_MODE) &&
400 			    (!IS_92C_SERIAL(rtlhal->version))) {
401 				rtl92c_dm_rf_saving(hw, true);
402 			}
403 
404 			rtl92c_set_fw_pwrmode_cmd(hw, *val);
405 			break;
406 		}
407 	case HW_VAR_FW_PSMODE_STATUS:
408 		ppsc->fw_current_inpsmode = *((bool *) val);
409 		break;
410 	case HW_VAR_H2C_FW_JOINBSSRPT:{
411 			u8 mstatus = *val;
412 			u8 tmp_regcr, tmp_reg422;
413 			bool recover = false;
414 
415 			if (mstatus == RT_MEDIA_CONNECT) {
416 				rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
417 							      NULL);
418 
419 				tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
420 				rtl_write_byte(rtlpriv, REG_CR + 1,
421 					       (tmp_regcr | BIT(0)));
422 
423 				_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
424 				_rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
425 
426 				tmp_reg422 =
427 				    rtl_read_byte(rtlpriv,
428 						  REG_FWHW_TXQ_CTRL + 2);
429 				if (tmp_reg422 & BIT(6))
430 					recover = true;
431 				rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
432 					       tmp_reg422 & (~BIT(6)));
433 
434 				rtl92c_set_fw_rsvdpagepkt(hw, NULL);
435 
436 				_rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
437 				_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
438 
439 				if (recover) {
440 					rtl_write_byte(rtlpriv,
441 						       REG_FWHW_TXQ_CTRL + 2,
442 						       tmp_reg422);
443 				}
444 
445 				rtl_write_byte(rtlpriv, REG_CR + 1,
446 					       (tmp_regcr & ~(BIT(0))));
447 			}
448 			rtl92c_set_fw_joinbss_report_cmd(hw, *val);
449 
450 			break;
451 		}
452 	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
453 		rtl92c_set_p2p_ps_offload_cmd(hw, *val);
454 		break;
455 	case HW_VAR_AID:{
456 			u16 u2btmp;
457 
458 			u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
459 			u2btmp &= 0xC000;
460 			rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
461 						mac->assoc_id));
462 
463 			break;
464 		}
465 	case HW_VAR_CORRECT_TSF:{
466 			u8 btype_ibss = val[0];
467 
468 			if (btype_ibss)
469 				_rtl92ce_stop_tx_beacon(hw);
470 
471 			_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
472 
473 			rtl_write_dword(rtlpriv, REG_TSFTR,
474 					(u32) (mac->tsf & 0xffffffff));
475 			rtl_write_dword(rtlpriv, REG_TSFTR + 4,
476 					(u32) ((mac->tsf >> 32) & 0xffffffff));
477 
478 			_rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
479 
480 			if (btype_ibss)
481 				_rtl92ce_resume_tx_beacon(hw);
482 
483 			break;
484 
485 		}
486 	case HW_VAR_FW_LPS_ACTION: {
487 			bool enter_fwlps = *((bool *)val);
488 			u8 rpwm_val, fw_pwrmode;
489 			bool fw_current_inps;
490 
491 			if (enter_fwlps) {
492 				rpwm_val = 0x02;	/* RF off */
493 				fw_current_inps = true;
494 				rtlpriv->cfg->ops->set_hw_reg(hw,
495 						HW_VAR_FW_PSMODE_STATUS,
496 						(u8 *)(&fw_current_inps));
497 				rtlpriv->cfg->ops->set_hw_reg(hw,
498 						HW_VAR_H2C_FW_PWRMODE,
499 						&ppsc->fwctrl_psmode);
500 
501 				rtlpriv->cfg->ops->set_hw_reg(hw,
502 							      HW_VAR_SET_RPWM,
503 							      &rpwm_val);
504 			} else {
505 				rpwm_val = 0x0C;	/* RF on */
506 				fw_pwrmode = FW_PS_ACTIVE_MODE;
507 				fw_current_inps = false;
508 				rtlpriv->cfg->ops->set_hw_reg(hw,
509 							      HW_VAR_SET_RPWM,
510 							      &rpwm_val);
511 				rtlpriv->cfg->ops->set_hw_reg(hw,
512 						HW_VAR_H2C_FW_PWRMODE,
513 						&fw_pwrmode);
514 
515 				rtlpriv->cfg->ops->set_hw_reg(hw,
516 						HW_VAR_FW_PSMODE_STATUS,
517 						(u8 *)(&fw_current_inps));
518 			}
519 		break; }
520 	case HW_VAR_KEEP_ALIVE: {
521 		u8 array[2];
522 
523 		array[0] = 0xff;
524 		array[1] = *((u8 *)val);
525 		rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array);
526 		break; }
527 	default:
528 		pr_err("switch case %d not processed\n", variable);
529 		break;
530 	}
531 }
532 
533 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
534 {
535 	struct rtl_priv *rtlpriv = rtl_priv(hw);
536 	bool status = true;
537 	long count = 0;
538 	u32 value = _LLT_INIT_ADDR(address) |
539 	    _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
540 
541 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
542 
543 	do {
544 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
545 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
546 			break;
547 
548 		if (count > POLLING_LLT_THRESHOLD) {
549 			pr_err("Failed to polling write LLT done at address %d!\n",
550 			       address);
551 			status = false;
552 			break;
553 		}
554 	} while (++count);
555 
556 	return status;
557 }
558 
559 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
560 {
561 	struct rtl_priv *rtlpriv = rtl_priv(hw);
562 	unsigned short i;
563 	u8 txpktbuf_bndy;
564 	u8 maxpage;
565 	bool status;
566 
567 #if LLT_CONFIG == 1
568 	maxpage = 255;
569 	txpktbuf_bndy = 252;
570 #elif LLT_CONFIG == 2
571 	maxpage = 127;
572 	txpktbuf_bndy = 124;
573 #elif LLT_CONFIG == 3
574 	maxpage = 255;
575 	txpktbuf_bndy = 174;
576 #elif LLT_CONFIG == 4
577 	maxpage = 255;
578 	txpktbuf_bndy = 246;
579 #elif LLT_CONFIG == 5
580 	maxpage = 255;
581 	txpktbuf_bndy = 246;
582 #endif
583 
584 #if LLT_CONFIG == 1
585 	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
586 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
587 #elif LLT_CONFIG == 2
588 	rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
589 #elif LLT_CONFIG == 3
590 	rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
591 #elif LLT_CONFIG == 4
592 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
593 #elif LLT_CONFIG == 5
594 	rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
595 
596 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
597 #endif
598 
599 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
600 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
601 
602 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
603 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
604 
605 	rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
606 	rtl_write_byte(rtlpriv, REG_PBP, 0x11);
607 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
608 
609 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
610 		status = _rtl92ce_llt_write(hw, i, i + 1);
611 		if (!status)
612 			return status;
613 	}
614 
615 	status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
616 	if (!status)
617 		return status;
618 
619 	for (i = txpktbuf_bndy; i < maxpage; i++) {
620 		status = _rtl92ce_llt_write(hw, i, (i + 1));
621 		if (!status)
622 			return status;
623 	}
624 
625 	status = _rtl92ce_llt_write(hw, maxpage, txpktbuf_bndy);
626 	if (!status)
627 		return status;
628 
629 	return true;
630 }
631 
632 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
633 {
634 	struct rtl_priv *rtlpriv = rtl_priv(hw);
635 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
636 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
637 	enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
638 
639 	if (rtlpci->up_first_time)
640 		return;
641 
642 	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
643 		rtl92ce_sw_led_on(hw, pin0);
644 	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
645 		rtl92ce_sw_led_on(hw, pin0);
646 	else
647 		rtl92ce_sw_led_off(hw, pin0);
648 }
649 
650 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
651 {
652 	struct rtl_priv *rtlpriv = rtl_priv(hw);
653 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
654 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
655 
656 	unsigned char bytetmp;
657 	unsigned short wordtmp;
658 	u16 retry;
659 
660 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
661 	if (rtlpriv->btcoexist.bt_coexistence) {
662 		u32 value32;
663 
664 		value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
665 		value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
666 		rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
667 	}
668 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
669 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
670 
671 	if (rtlpriv->btcoexist.bt_coexistence) {
672 		u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
673 
674 		u4b_tmp &= (~0x00024800);
675 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
676 	}
677 
678 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
679 	udelay(2);
680 
681 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
682 	udelay(2);
683 
684 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
685 	udelay(2);
686 
687 	retry = 0;
688 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
689 		rtl_read_dword(rtlpriv, 0xEC), bytetmp);
690 
691 	while ((bytetmp & BIT(0)) && retry < 1000) {
692 		retry++;
693 		udelay(50);
694 		bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
695 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
696 			rtl_read_dword(rtlpriv, 0xEC), bytetmp);
697 		udelay(50);
698 	}
699 
700 	rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
701 
702 	rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
703 	udelay(2);
704 
705 	if (rtlpriv->btcoexist.bt_coexistence) {
706 		bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
707 		rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
708 	}
709 
710 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
711 
712 	if (!_rtl92ce_llt_table_init(hw))
713 		return false;
714 
715 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
716 	rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
717 
718 	rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
719 
720 	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
721 	wordtmp &= 0xf;
722 	wordtmp |= 0xF771;
723 	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
724 
725 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
726 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
727 	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
728 
729 	rtl_write_byte(rtlpriv, 0x4d0, 0x0);
730 
731 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
732 			((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
733 			DMA_BIT_MASK(32));
734 	rtl_write_dword(rtlpriv, REG_MGQ_DESA,
735 			(u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
736 			DMA_BIT_MASK(32));
737 	rtl_write_dword(rtlpriv, REG_VOQ_DESA,
738 			(u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
739 	rtl_write_dword(rtlpriv, REG_VIQ_DESA,
740 			(u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
741 	rtl_write_dword(rtlpriv, REG_BEQ_DESA,
742 			(u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
743 	rtl_write_dword(rtlpriv, REG_BKQ_DESA,
744 			(u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
745 	rtl_write_dword(rtlpriv, REG_HQ_DESA,
746 			(u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
747 			DMA_BIT_MASK(32));
748 	rtl_write_dword(rtlpriv, REG_RX_DESA,
749 			(u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
750 			DMA_BIT_MASK(32));
751 
752 	if (IS_92C_SERIAL(rtlhal->version))
753 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
754 	else
755 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
756 
757 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
758 
759 	bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
760 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
761 	do {
762 		retry++;
763 		bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
764 	} while ((retry < 200) && (bytetmp & BIT(7)));
765 
766 	_rtl92ce_gen_refresh_led_state(hw);
767 
768 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
769 
770 	return true;
771 }
772 
773 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
774 {
775 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
776 	struct rtl_priv *rtlpriv = rtl_priv(hw);
777 	u8 reg_bw_opmode;
778 	u32 reg_prsr;
779 
780 	reg_bw_opmode = BW_OPMODE_20MHZ;
781 	reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
782 
783 	rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
784 
785 	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
786 
787 	rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
788 
789 	rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
790 
791 	rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
792 
793 	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
794 
795 	rtl_write_word(rtlpriv, REG_RL, 0x0707);
796 
797 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
798 
799 	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
800 
801 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
802 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
803 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
804 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
805 
806 	if ((rtlpriv->btcoexist.bt_coexistence) &&
807 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
808 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
809 	else
810 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
811 
812 	rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
813 
814 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
815 
816 	rtlpci->reg_bcn_ctrl_val = 0x1f;
817 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
818 
819 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
820 
821 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
822 
823 	rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
824 	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
825 
826 	if ((rtlpriv->btcoexist.bt_coexistence) &&
827 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
828 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
829 		rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
830 	} else {
831 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
832 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
833 	}
834 
835 	if ((rtlpriv->btcoexist.bt_coexistence) &&
836 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
837 		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
838 	else
839 		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
840 
841 	rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
842 
843 	rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
844 	rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
845 
846 	rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
847 
848 	rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
849 
850 	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
851 	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
852 
853 }
854 
855 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
856 {
857 	struct rtl_priv *rtlpriv = rtl_priv(hw);
858 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
859 
860 	rtl_write_byte(rtlpriv, 0x34b, 0x93);
861 	rtl_write_word(rtlpriv, 0x350, 0x870c);
862 	rtl_write_byte(rtlpriv, 0x352, 0x1);
863 
864 	if (ppsc->support_backdoor)
865 		rtl_write_byte(rtlpriv, 0x349, 0x1b);
866 	else
867 		rtl_write_byte(rtlpriv, 0x349, 0x03);
868 
869 	rtl_write_word(rtlpriv, 0x350, 0x2718);
870 	rtl_write_byte(rtlpriv, 0x352, 0x1);
871 }
872 
873 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
874 {
875 	struct rtl_priv *rtlpriv = rtl_priv(hw);
876 	u8 sec_reg_value;
877 
878 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
879 		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
880 		rtlpriv->sec.pairwise_enc_algorithm,
881 		rtlpriv->sec.group_enc_algorithm);
882 
883 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
884 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
885 			"not open hw encryption\n");
886 		return;
887 	}
888 
889 	sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
890 
891 	if (rtlpriv->sec.use_defaultkey) {
892 		sec_reg_value |= SCR_TXUSEDK;
893 		sec_reg_value |= SCR_RXUSEDK;
894 	}
895 
896 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
897 
898 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
899 
900 	rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
901 		"The SECR-value %x\n", sec_reg_value);
902 
903 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
904 
905 }
906 
907 int rtl92ce_hw_init(struct ieee80211_hw *hw)
908 {
909 	struct rtl_priv *rtlpriv = rtl_priv(hw);
910 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
911 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
912 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
913 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
914 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
915 	bool rtstatus = true;
916 	bool is92c;
917 	int err;
918 	u8 tmp_u1b;
919 	unsigned long flags;
920 
921 	rtlpci->being_init_adapter = true;
922 
923 	/* Since this function can take a very long time (up to 350 ms)
924 	 * and can be called with irqs disabled, reenable the irqs
925 	 * to let the other devices continue being serviced.
926 	 *
927 	 * It is safe doing so since our own interrupts will only be enabled
928 	 * in a subsequent step.
929 	 */
930 	local_save_flags(flags);
931 	local_irq_enable();
932 
933 	rtlhal->fw_ready = false;
934 	rtlpriv->intf_ops->disable_aspm(hw);
935 	rtstatus = _rtl92ce_init_mac(hw);
936 	if (!rtstatus) {
937 		pr_err("Init MAC failed\n");
938 		err = 1;
939 		goto exit;
940 	}
941 
942 	err = rtl92c_download_fw(hw);
943 	if (err) {
944 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
945 			"Failed to download FW. Init HW without FW now..\n");
946 		err = 1;
947 		goto exit;
948 	}
949 
950 	rtlhal->fw_ready = true;
951 	rtlhal->last_hmeboxnum = 0;
952 	rtl92c_phy_mac_config(hw);
953 	/* because last function modify RCR, so we update
954 	 * rcr var here, or TP will unstable for receive_config
955 	 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
956 	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
957 	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
958 	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
959 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
960 	rtl92c_phy_bb_config(hw);
961 	rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
962 	rtl92c_phy_rf_config(hw);
963 	if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
964 	    !IS_92C_SERIAL(rtlhal->version)) {
965 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
966 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
967 	} else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
968 		rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
969 		rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
970 		rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
971 		rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
972 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
973 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
974 	}
975 	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
976 						 RF_CHNLBW, RFREG_OFFSET_MASK);
977 	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
978 						 RF_CHNLBW, RFREG_OFFSET_MASK);
979 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
980 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
981 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
982 	_rtl92ce_hw_configure(hw);
983 	rtl_cam_reset_all_entry(hw);
984 	rtl92ce_enable_hw_security_config(hw);
985 
986 	ppsc->rfpwr_state = ERFON;
987 
988 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
989 	_rtl92ce_enable_aspm_back_door(hw);
990 	rtlpriv->intf_ops->enable_aspm(hw);
991 
992 	rtl8192ce_bt_hw_init(hw);
993 
994 	if (ppsc->rfpwr_state == ERFON) {
995 		rtl92c_phy_set_rfpath_switch(hw, 1);
996 		if (rtlphy->iqk_initialized) {
997 			rtl92c_phy_iq_calibrate(hw, true);
998 		} else {
999 			rtl92c_phy_iq_calibrate(hw, false);
1000 			rtlphy->iqk_initialized = true;
1001 		}
1002 
1003 		rtl92c_dm_check_txpower_tracking(hw);
1004 		rtl92c_phy_lc_calibrate(hw);
1005 	}
1006 
1007 	is92c = IS_92C_SERIAL(rtlhal->version);
1008 	tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1009 	if (!(tmp_u1b & BIT(0))) {
1010 		rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1011 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1012 	}
1013 
1014 	if (!(tmp_u1b & BIT(1)) && is92c) {
1015 		rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1016 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1017 	}
1018 
1019 	if (!(tmp_u1b & BIT(4))) {
1020 		tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1021 		tmp_u1b &= 0x0F;
1022 		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1023 		udelay(10);
1024 		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1025 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1026 	}
1027 	rtl92c_dm_init(hw);
1028 exit:
1029 	local_irq_restore(flags);
1030 	rtlpci->being_init_adapter = false;
1031 	return err;
1032 }
1033 
1034 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1035 {
1036 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1037 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1038 	enum version_8192c version = VERSION_UNKNOWN;
1039 	u32 value32;
1040 	const char *versionid;
1041 
1042 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1043 	if (value32 & TRP_VAUX_EN) {
1044 		version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1045 			   VERSION_A_CHIP_88C;
1046 	} else {
1047 		version = (enum version_8192c) (CHIP_VER_B |
1048 				((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1049 				((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1050 		if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1051 		     CHIP_VER_RTL_MASK)) {
1052 			version = (enum version_8192c)(version |
1053 				   ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1054 				   ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1055 				   CHIP_VENDOR_UMC));
1056 		}
1057 		if (IS_92C_SERIAL(version)) {
1058 			value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1059 			version = (enum version_8192c)(version |
1060 				   ((CHIP_BONDING_IDENTIFIER(value32)
1061 				   == CHIP_BONDING_92C_1T2R) ?
1062 				   RF_TYPE_1T2R : 0));
1063 		}
1064 	}
1065 
1066 	switch (version) {
1067 	case VERSION_B_CHIP_92C:
1068 		versionid = "B_CHIP_92C";
1069 		break;
1070 	case VERSION_B_CHIP_88C:
1071 		versionid = "B_CHIP_88C";
1072 		break;
1073 	case VERSION_A_CHIP_92C:
1074 		versionid = "A_CHIP_92C";
1075 		break;
1076 	case VERSION_A_CHIP_88C:
1077 		versionid = "A_CHIP_88C";
1078 		break;
1079 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1080 		versionid = "A_CUT_92C_1T2R";
1081 		break;
1082 	case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1083 		versionid = "A_CUT_92C";
1084 		break;
1085 	case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1086 		versionid = "A_CUT_88C";
1087 		break;
1088 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1089 		versionid = "B_CUT_92C_1T2R";
1090 		break;
1091 	case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1092 		versionid = "B_CUT_92C";
1093 		break;
1094 	case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1095 		versionid = "B_CUT_88C";
1096 		break;
1097 	default:
1098 		versionid = "Unknown. Bug?";
1099 		break;
1100 	}
1101 
1102 	pr_info("Chip Version ID: %s\n", versionid);
1103 
1104 	switch (version & 0x3) {
1105 	case CHIP_88C:
1106 		rtlphy->rf_type = RF_1T1R;
1107 		break;
1108 	case CHIP_92C:
1109 		rtlphy->rf_type = RF_2T2R;
1110 		break;
1111 	case CHIP_92C_1T2R:
1112 		rtlphy->rf_type = RF_1T2R;
1113 		break;
1114 	default:
1115 		rtlphy->rf_type = RF_1T1R;
1116 		pr_err("ERROR RF_Type is set!!\n");
1117 		break;
1118 	}
1119 
1120 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1121 		rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1122 
1123 	return version;
1124 }
1125 
1126 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1127 				     enum nl80211_iftype type)
1128 {
1129 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1130 	u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1131 	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1132 	u8 mode = MSR_NOLINK;
1133 
1134 	bt_msr &= 0xfc;
1135 
1136 	switch (type) {
1137 	case NL80211_IFTYPE_UNSPECIFIED:
1138 		mode = MSR_NOLINK;
1139 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1140 			"Set Network type to NO LINK!\n");
1141 		break;
1142 	case NL80211_IFTYPE_ADHOC:
1143 		mode = MSR_ADHOC;
1144 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1145 			"Set Network type to Ad Hoc!\n");
1146 		break;
1147 	case NL80211_IFTYPE_STATION:
1148 		mode = MSR_INFRA;
1149 		ledaction = LED_CTL_LINK;
1150 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1151 			"Set Network type to STA!\n");
1152 		break;
1153 	case NL80211_IFTYPE_AP:
1154 		mode = MSR_AP;
1155 		ledaction = LED_CTL_LINK;
1156 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1157 			"Set Network type to AP!\n");
1158 		break;
1159 	case NL80211_IFTYPE_MESH_POINT:
1160 		mode = MSR_ADHOC;
1161 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1162 			"Set Network type to Mesh Point!\n");
1163 		break;
1164 	default:
1165 		pr_err("Network type %d not supported!\n", type);
1166 		return 1;
1167 
1168 	}
1169 
1170 	/* MSR_INFRA == Link in infrastructure network;
1171 	 * MSR_ADHOC == Link in ad hoc network;
1172 	 * Therefore, check link state is necessary.
1173 	 *
1174 	 * MSR_AP == AP mode; link state does not matter here.
1175 	 */
1176 	if (mode != MSR_AP &&
1177 	    rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1178 		mode = MSR_NOLINK;
1179 		ledaction = LED_CTL_NO_LINK;
1180 	}
1181 	if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1182 		_rtl92ce_stop_tx_beacon(hw);
1183 		_rtl92ce_enable_bcn_sub_func(hw);
1184 	} else if (mode == MSR_ADHOC || mode == MSR_AP) {
1185 		_rtl92ce_resume_tx_beacon(hw);
1186 		_rtl92ce_disable_bcn_sub_func(hw);
1187 	} else {
1188 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1189 			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1190 			mode);
1191 	}
1192 	rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1193 
1194 	rtlpriv->cfg->ops->led_control(hw, ledaction);
1195 	if (mode == MSR_AP)
1196 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1197 	else
1198 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1199 	return 0;
1200 }
1201 
1202 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1203 {
1204 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1205 	u32 reg_rcr;
1206 
1207 	if (rtlpriv->psc.rfpwr_state != ERFON)
1208 		return;
1209 
1210 	rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1211 
1212 	if (check_bssid) {
1213 		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1214 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1215 					      (u8 *) (&reg_rcr));
1216 		_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1217 	} else if (!check_bssid) {
1218 		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1219 		_rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1220 		rtlpriv->cfg->ops->set_hw_reg(hw,
1221 					      HW_VAR_RCR, (u8 *) (&reg_rcr));
1222 	}
1223 
1224 }
1225 
1226 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1227 {
1228 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1229 
1230 	if (_rtl92ce_set_media_status(hw, type))
1231 		return -EOPNOTSUPP;
1232 
1233 	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1234 		if (type != NL80211_IFTYPE_AP &&
1235 		    type != NL80211_IFTYPE_MESH_POINT)
1236 			rtl92ce_set_check_bssid(hw, true);
1237 	} else {
1238 		rtl92ce_set_check_bssid(hw, false);
1239 	}
1240 
1241 	return 0;
1242 }
1243 
1244 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1245 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1246 {
1247 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 
1249 	rtl92c_dm_init_edca_turbo(hw);
1250 	switch (aci) {
1251 	case AC1_BK:
1252 		rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1253 		break;
1254 	case AC0_BE:
1255 		/* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1256 		break;
1257 	case AC2_VI:
1258 		rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1259 		break;
1260 	case AC3_VO:
1261 		rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1262 		break;
1263 	default:
1264 		WARN_ONCE(true, "rtl8192ce: invalid aci: %d !\n", aci);
1265 		break;
1266 	}
1267 }
1268 
1269 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1270 {
1271 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1272 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1273 
1274 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1275 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1276 	rtlpci->irq_enabled = true;
1277 }
1278 
1279 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1280 {
1281 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1282 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1283 
1284 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1285 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1286 	rtlpci->irq_enabled = false;
1287 }
1288 
1289 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1290 {
1291 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1292 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1293 	u8 u1b_tmp;
1294 	u32 u4b_tmp;
1295 
1296 	rtlpriv->intf_ops->enable_aspm(hw);
1297 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1298 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1299 	rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1300 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1301 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1302 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1303 	if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1304 		rtl92c_firmware_selfreset(hw);
1305 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1306 	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1307 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1308 	u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1309 	if ((rtlpriv->btcoexist.bt_coexistence) &&
1310 	    ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
1311 	     (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8))) {
1312 		rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1313 				(u1b_tmp << 8));
1314 	} else {
1315 		rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1316 				(u1b_tmp << 8));
1317 	}
1318 	rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1319 	rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1320 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1321 	if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1322 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1323 	if (rtlpriv->btcoexist.bt_coexistence) {
1324 		u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1325 		u4b_tmp |= 0x03824800;
1326 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1327 	} else {
1328 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1329 	}
1330 
1331 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1332 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1333 }
1334 
1335 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1336 {
1337 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1338 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1339 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1340 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1341 	enum nl80211_iftype opmode;
1342 
1343 	mac->link_state = MAC80211_NOLINK;
1344 	opmode = NL80211_IFTYPE_UNSPECIFIED;
1345 	_rtl92ce_set_media_status(hw, opmode);
1346 	if (rtlpci->driver_is_goingto_unload ||
1347 	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1348 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1349 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1350 	_rtl92ce_poweroff_adapter(hw);
1351 
1352 	/* after power off we should do iqk again */
1353 	rtlpriv->phy.iqk_initialized = false;
1354 }
1355 
1356 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1357 				  struct rtl_int *intvec)
1358 {
1359 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1360 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1361 
1362 	intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1363 	rtl_write_dword(rtlpriv, ISR, intvec->inta);
1364 }
1365 
1366 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1367 {
1368 
1369 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1370 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1371 	u16 bcn_interval, atim_window;
1372 
1373 	bcn_interval = mac->beacon_interval;
1374 	atim_window = 2;	/*FIX MERGE */
1375 	rtl92ce_disable_interrupt(hw);
1376 	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1377 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1378 	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1379 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1380 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1381 	rtl_write_byte(rtlpriv, 0x606, 0x30);
1382 	rtl92ce_enable_interrupt(hw);
1383 }
1384 
1385 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1386 {
1387 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1389 	u16 bcn_interval = mac->beacon_interval;
1390 
1391 	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1392 		"beacon_interval:%d\n", bcn_interval);
1393 	rtl92ce_disable_interrupt(hw);
1394 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1395 	rtl92ce_enable_interrupt(hw);
1396 }
1397 
1398 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1399 				   u32 add_msr, u32 rm_msr)
1400 {
1401 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1402 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1403 
1404 	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1405 		add_msr, rm_msr);
1406 
1407 	if (add_msr)
1408 		rtlpci->irq_mask[0] |= add_msr;
1409 	if (rm_msr)
1410 		rtlpci->irq_mask[0] &= (~rm_msr);
1411 	rtl92ce_disable_interrupt(hw);
1412 	rtl92ce_enable_interrupt(hw);
1413 }
1414 
1415 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1416 						 bool autoload_fail,
1417 						 u8 *hwinfo)
1418 {
1419 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1420 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1421 	u8 rf_path, index, tempval;
1422 	u16 i;
1423 
1424 	for (rf_path = 0; rf_path < 2; rf_path++) {
1425 		for (i = 0; i < 3; i++) {
1426 			if (!autoload_fail &&
1427 			    hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i] != 0xff &&
1428 			    hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i] != 0xff) {
1429 				rtlefuse->
1430 				    eeprom_chnlarea_txpwr_cck[rf_path][i] =
1431 				    hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1432 				rtlefuse->
1433 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1434 				    hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1435 					   i];
1436 			} else {
1437 				rtlefuse->
1438 				    eeprom_chnlarea_txpwr_cck[rf_path][i] =
1439 				    EEPROM_DEFAULT_TXPOWERLEVEL;
1440 				rtlefuse->
1441 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1442 				    EEPROM_DEFAULT_TXPOWERLEVEL;
1443 			}
1444 		}
1445 	}
1446 
1447 	for (i = 0; i < 3; i++) {
1448 		if (!autoload_fail &&
1449 		    hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i] != 0xff)
1450 			tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1451 		else
1452 			tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1453 		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1454 		    (tempval & 0xf);
1455 		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1456 		    ((tempval & 0xf0) >> 4);
1457 	}
1458 
1459 	for (rf_path = 0; rf_path < 2; rf_path++)
1460 		for (i = 0; i < 3; i++)
1461 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1462 				"RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1463 				rf_path, i,
1464 				rtlefuse->
1465 				eeprom_chnlarea_txpwr_cck[rf_path][i]);
1466 	for (rf_path = 0; rf_path < 2; rf_path++)
1467 		for (i = 0; i < 3; i++)
1468 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1469 				"RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1470 				rf_path, i,
1471 				rtlefuse->
1472 				eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1473 	for (rf_path = 0; rf_path < 2; rf_path++)
1474 		for (i = 0; i < 3; i++)
1475 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1476 				"RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1477 				rf_path, i,
1478 				rtlefuse->
1479 				eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1480 
1481 	for (rf_path = 0; rf_path < 2; rf_path++) {
1482 		for (i = 0; i < 14; i++) {
1483 			index = rtl92c_get_chnl_group((u8)i);
1484 
1485 			rtlefuse->txpwrlevel_cck[rf_path][i] =
1486 			    rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1487 			rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1488 			    rtlefuse->
1489 			    eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1490 
1491 			if ((rtlefuse->
1492 			     eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1493 			     rtlefuse->
1494 			     eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1495 			    > 0) {
1496 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1497 				    rtlefuse->
1498 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1499 				    [index] -
1500 				    rtlefuse->
1501 				    eprom_chnl_txpwr_ht40_2sdf[rf_path]
1502 				    [index];
1503 			} else {
1504 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1505 			}
1506 		}
1507 
1508 		for (i = 0; i < 14; i++) {
1509 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1510 				"RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1511 				rf_path, i,
1512 				rtlefuse->txpwrlevel_cck[rf_path][i],
1513 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1514 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1515 		}
1516 	}
1517 
1518 	for (i = 0; i < 3; i++) {
1519 		if (!autoload_fail &&
1520 		    hwinfo[EEPROM_TXPWR_GROUP + i] != 0xff &&
1521 		    hwinfo[EEPROM_TXPWR_GROUP + 3 + i] != 0xff) {
1522 			rtlefuse->eeprom_pwrlimit_ht40[i] =
1523 			    hwinfo[EEPROM_TXPWR_GROUP + i];
1524 			rtlefuse->eeprom_pwrlimit_ht20[i] =
1525 			    hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1526 		} else {
1527 			rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1528 			rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1529 		}
1530 	}
1531 
1532 	for (rf_path = 0; rf_path < 2; rf_path++) {
1533 		for (i = 0; i < 14; i++) {
1534 			index = rtl92c_get_chnl_group((u8)i);
1535 
1536 			if (rf_path == RF90_PATH_A) {
1537 				rtlefuse->pwrgroup_ht20[rf_path][i] =
1538 				    (rtlefuse->eeprom_pwrlimit_ht20[index]
1539 				     & 0xf);
1540 				rtlefuse->pwrgroup_ht40[rf_path][i] =
1541 				    (rtlefuse->eeprom_pwrlimit_ht40[index]
1542 				     & 0xf);
1543 			} else if (rf_path == RF90_PATH_B) {
1544 				rtlefuse->pwrgroup_ht20[rf_path][i] =
1545 				    ((rtlefuse->eeprom_pwrlimit_ht20[index]
1546 				      & 0xf0) >> 4);
1547 				rtlefuse->pwrgroup_ht40[rf_path][i] =
1548 				    ((rtlefuse->eeprom_pwrlimit_ht40[index]
1549 				      & 0xf0) >> 4);
1550 			}
1551 
1552 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1553 				"RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1554 				rf_path, i,
1555 				rtlefuse->pwrgroup_ht20[rf_path][i]);
1556 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1557 				"RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1558 				rf_path, i,
1559 				rtlefuse->pwrgroup_ht40[rf_path][i]);
1560 		}
1561 	}
1562 
1563 	for (i = 0; i < 14; i++) {
1564 		index = rtl92c_get_chnl_group((u8)i);
1565 
1566 		if (!autoload_fail &&
1567 		    hwinfo[EEPROM_TXPOWERHT20DIFF + index] != 0xff)
1568 			tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1569 		else
1570 			tempval = EEPROM_DEFAULT_HT20_DIFF;
1571 
1572 		rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1573 		rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1574 		    ((tempval >> 4) & 0xF);
1575 
1576 		if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1577 			rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1578 
1579 		if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1580 			rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1581 
1582 		index = rtl92c_get_chnl_group((u8)i);
1583 
1584 		if (!autoload_fail &&
1585 		    hwinfo[EEPROM_TXPOWER_OFDMDIFF + index] != 0xff)
1586 			tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1587 		else
1588 			tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1589 
1590 		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1591 		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1592 		    ((tempval >> 4) & 0xF);
1593 	}
1594 
1595 	rtlefuse->legacy_ht_txpowerdiff =
1596 	    rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1597 
1598 	for (i = 0; i < 14; i++)
1599 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1600 			"RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1601 			i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1602 	for (i = 0; i < 14; i++)
1603 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1604 			"RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1605 			i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1606 	for (i = 0; i < 14; i++)
1607 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1608 			"RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1609 			i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1610 	for (i = 0; i < 14; i++)
1611 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1612 			"RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1613 			i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1614 
1615 	if (!autoload_fail && hwinfo[RF_OPTION1] != 0xff)
1616 		rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1617 	else
1618 		rtlefuse->eeprom_regulatory = 0;
1619 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1620 		"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1621 
1622 	if (!autoload_fail &&
1623 	    hwinfo[EEPROM_TSSI_A] != 0xff &&
1624 	    hwinfo[EEPROM_TSSI_B] != 0xff) {
1625 		rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1626 		rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1627 	} else {
1628 		rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1629 		rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1630 	}
1631 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1632 		rtlefuse->eeprom_tssi[RF90_PATH_A],
1633 		rtlefuse->eeprom_tssi[RF90_PATH_B]);
1634 
1635 	if (!autoload_fail && hwinfo[EEPROM_THERMAL_METER] != 0xff)
1636 		tempval = hwinfo[EEPROM_THERMAL_METER];
1637 	else
1638 		tempval = EEPROM_DEFAULT_THERMALMETER;
1639 	rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1640 
1641 	if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1642 		rtlefuse->apk_thermalmeterignore = true;
1643 
1644 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1645 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1646 		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1647 }
1648 
1649 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1650 {
1651 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1652 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1653 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1654 	int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1655 			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1656 			EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1657 			COUNTRY_CODE_WORLD_WIDE_13};
1658 	u8 *hwinfo;
1659 
1660 	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1661 	if (!hwinfo)
1662 		return;
1663 
1664 	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1665 		goto exit;
1666 
1667 	_rtl92ce_read_txpower_info_from_hwpg(hw,
1668 					     rtlefuse->autoload_failflag,
1669 					     hwinfo);
1670 
1671 	rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1672 						 rtlefuse->autoload_failflag,
1673 						 hwinfo);
1674 	if (rtlhal->oem_id == RT_CID_DEFAULT) {
1675 		switch (rtlefuse->eeprom_oemid) {
1676 		case EEPROM_CID_DEFAULT:
1677 			if (rtlefuse->eeprom_did == 0x8176) {
1678 				if ((rtlefuse->eeprom_svid == 0x103C &&
1679 				     rtlefuse->eeprom_smid == 0x1629))
1680 					rtlhal->oem_id = RT_CID_819X_HP;
1681 				else
1682 					rtlhal->oem_id = RT_CID_DEFAULT;
1683 			} else {
1684 				rtlhal->oem_id = RT_CID_DEFAULT;
1685 			}
1686 			break;
1687 		case EEPROM_CID_TOSHIBA:
1688 			rtlhal->oem_id = RT_CID_TOSHIBA;
1689 			break;
1690 		case EEPROM_CID_QMI:
1691 			rtlhal->oem_id = RT_CID_819X_QMI;
1692 			break;
1693 		case EEPROM_CID_WHQL:
1694 		default:
1695 			rtlhal->oem_id = RT_CID_DEFAULT;
1696 			break;
1697 		}
1698 	}
1699 exit:
1700 	kfree(hwinfo);
1701 }
1702 
1703 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1704 {
1705 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1706 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1707 
1708 	switch (rtlhal->oem_id) {
1709 	case RT_CID_819X_HP:
1710 		rtlpriv->ledctl.led_opendrain = true;
1711 		break;
1712 	case RT_CID_819X_LENOVO:
1713 	case RT_CID_DEFAULT:
1714 	case RT_CID_TOSHIBA:
1715 	case RT_CID_CCX:
1716 	case RT_CID_819X_ACER:
1717 	case RT_CID_WHQL:
1718 	default:
1719 		break;
1720 	}
1721 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1722 		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1723 }
1724 
1725 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1726 {
1727 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1728 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1729 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1730 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1731 	u8 tmp_u1b;
1732 
1733 	rtlhal->version = _rtl92ce_read_chip_version(hw);
1734 	if (get_rf_type(rtlphy) == RF_1T1R)
1735 		rtlpriv->dm.rfpath_rxenable[0] = true;
1736 	else
1737 		rtlpriv->dm.rfpath_rxenable[0] =
1738 		    rtlpriv->dm.rfpath_rxenable[1] = true;
1739 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1740 		rtlhal->version);
1741 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1742 	if (tmp_u1b & BIT(4)) {
1743 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1744 		rtlefuse->epromtype = EEPROM_93C46;
1745 	} else {
1746 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1747 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1748 	}
1749 	if (tmp_u1b & BIT(5)) {
1750 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1751 		rtlefuse->autoload_failflag = false;
1752 		_rtl92ce_read_adapter_info(hw);
1753 	} else {
1754 		pr_err("Autoload ERR!!\n");
1755 	}
1756 	_rtl92ce_hal_customized_behavior(hw);
1757 }
1758 
1759 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1760 		struct ieee80211_sta *sta)
1761 {
1762 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1763 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1764 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1765 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1766 	u32 ratr_value;
1767 	u8 ratr_index = 0;
1768 	u8 nmode = mac->ht_enable;
1769 	u16 shortgi_rate;
1770 	u32 tmp_ratr_value;
1771 	u8 curtxbw_40mhz = mac->bw_40;
1772 	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1773 			       1 : 0;
1774 	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1775 			       1 : 0;
1776 	enum wireless_mode wirelessmode = mac->mode;
1777 	u32 ratr_mask;
1778 
1779 	if (rtlhal->current_bandtype == BAND_ON_5G)
1780 		ratr_value = sta->deflink.supp_rates[1] << 4;
1781 	else
1782 		ratr_value = sta->deflink.supp_rates[0];
1783 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1784 		ratr_value = 0xfff;
1785 
1786 	ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1787 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1788 	switch (wirelessmode) {
1789 	case WIRELESS_MODE_B:
1790 		if (ratr_value & 0x0000000c)
1791 			ratr_value &= 0x0000000d;
1792 		else
1793 			ratr_value &= 0x0000000f;
1794 		break;
1795 	case WIRELESS_MODE_G:
1796 		ratr_value &= 0x00000FF5;
1797 		break;
1798 	case WIRELESS_MODE_N_24G:
1799 	case WIRELESS_MODE_N_5G:
1800 		nmode = 1;
1801 		if (get_rf_type(rtlphy) == RF_1T2R ||
1802 		    get_rf_type(rtlphy) == RF_1T1R)
1803 			ratr_mask = 0x000ff005;
1804 		else
1805 			ratr_mask = 0x0f0ff005;
1806 
1807 		ratr_value &= ratr_mask;
1808 		break;
1809 	default:
1810 		if (rtlphy->rf_type == RF_1T2R)
1811 			ratr_value &= 0x000ff0ff;
1812 		else
1813 			ratr_value &= 0x0f0ff0ff;
1814 
1815 		break;
1816 	}
1817 
1818 	if ((rtlpriv->btcoexist.bt_coexistence) &&
1819 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1820 	    (rtlpriv->btcoexist.bt_cur_state) &&
1821 	    (rtlpriv->btcoexist.bt_ant_isolation) &&
1822 	    ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1823 	    (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1824 		ratr_value &= 0x0fffcfc0;
1825 	else
1826 		ratr_value &= 0x0FFFFFFF;
1827 
1828 	if (nmode && ((curtxbw_40mhz &&
1829 			 curshortgi_40mhz) || (!curtxbw_40mhz &&
1830 					       curshortgi_20mhz))) {
1831 
1832 		ratr_value |= 0x10000000;
1833 		tmp_ratr_value = (ratr_value >> 12);
1834 
1835 		for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1836 			if ((1 << shortgi_rate) & tmp_ratr_value)
1837 				break;
1838 		}
1839 
1840 		shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1841 		    (shortgi_rate << 4) | (shortgi_rate);
1842 	}
1843 
1844 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1845 
1846 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1847 		rtl_read_dword(rtlpriv, REG_ARFR0));
1848 }
1849 
1850 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1851 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1852 {
1853 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1854 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1855 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1856 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1857 	struct rtl_sta_info *sta_entry = NULL;
1858 	u32 ratr_bitmap;
1859 	u8 ratr_index;
1860 	u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap &
1861 			    IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
1862 	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap &
1863 			       IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
1864 	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1865 				1 : 0;
1866 	enum wireless_mode wirelessmode = 0;
1867 	bool shortgi = false;
1868 	u8 rate_mask[5];
1869 	u8 macid = 0;
1870 
1871 	sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1872 	wirelessmode = sta_entry->wireless_mode;
1873 	if (mac->opmode == NL80211_IFTYPE_STATION ||
1874 	    mac->opmode == NL80211_IFTYPE_MESH_POINT)
1875 		curtxbw_40mhz = mac->bw_40;
1876 	else if (mac->opmode == NL80211_IFTYPE_AP ||
1877 		mac->opmode == NL80211_IFTYPE_ADHOC)
1878 		macid = sta->aid + 1;
1879 
1880 	if (rtlhal->current_bandtype == BAND_ON_5G)
1881 		ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1882 	else
1883 		ratr_bitmap = sta->deflink.supp_rates[0];
1884 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1885 		ratr_bitmap = 0xfff;
1886 	ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1887 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1888 	switch (wirelessmode) {
1889 	case WIRELESS_MODE_B:
1890 		ratr_index = RATR_INX_WIRELESS_B;
1891 		if (ratr_bitmap & 0x0000000c)
1892 			ratr_bitmap &= 0x0000000d;
1893 		else
1894 			ratr_bitmap &= 0x0000000f;
1895 		break;
1896 	case WIRELESS_MODE_G:
1897 		ratr_index = RATR_INX_WIRELESS_GB;
1898 
1899 		if (rssi_level == 1)
1900 			ratr_bitmap &= 0x00000f00;
1901 		else if (rssi_level == 2)
1902 			ratr_bitmap &= 0x00000ff0;
1903 		else
1904 			ratr_bitmap &= 0x00000ff5;
1905 		break;
1906 	case WIRELESS_MODE_A:
1907 		ratr_index = RATR_INX_WIRELESS_A;
1908 		ratr_bitmap &= 0x00000ff0;
1909 		break;
1910 	case WIRELESS_MODE_N_24G:
1911 	case WIRELESS_MODE_N_5G:
1912 		ratr_index = RATR_INX_WIRELESS_NGB;
1913 
1914 		if (rtlphy->rf_type == RF_1T2R ||
1915 		    rtlphy->rf_type == RF_1T1R) {
1916 			if (curtxbw_40mhz) {
1917 				if (rssi_level == 1)
1918 					ratr_bitmap &= 0x000f0000;
1919 				else if (rssi_level == 2)
1920 					ratr_bitmap &= 0x000ff000;
1921 				else
1922 					ratr_bitmap &= 0x000ff015;
1923 			} else {
1924 				if (rssi_level == 1)
1925 					ratr_bitmap &= 0x000f0000;
1926 				else if (rssi_level == 2)
1927 					ratr_bitmap &= 0x000ff000;
1928 				else
1929 					ratr_bitmap &= 0x000ff005;
1930 			}
1931 		} else {
1932 			if (curtxbw_40mhz) {
1933 				if (rssi_level == 1)
1934 					ratr_bitmap &= 0x0f0f0000;
1935 				else if (rssi_level == 2)
1936 					ratr_bitmap &= 0x0f0ff000;
1937 				else
1938 					ratr_bitmap &= 0x0f0ff015;
1939 			} else {
1940 				if (rssi_level == 1)
1941 					ratr_bitmap &= 0x0f0f0000;
1942 				else if (rssi_level == 2)
1943 					ratr_bitmap &= 0x0f0ff000;
1944 				else
1945 					ratr_bitmap &= 0x0f0ff005;
1946 			}
1947 		}
1948 
1949 		if ((curtxbw_40mhz && curshortgi_40mhz) ||
1950 		    (!curtxbw_40mhz && curshortgi_20mhz)) {
1951 
1952 			if (macid == 0)
1953 				shortgi = true;
1954 			else if (macid == 1)
1955 				shortgi = false;
1956 		}
1957 		break;
1958 	default:
1959 		ratr_index = RATR_INX_WIRELESS_NGB;
1960 
1961 		if (rtlphy->rf_type == RF_1T2R)
1962 			ratr_bitmap &= 0x000ff0ff;
1963 		else
1964 			ratr_bitmap &= 0x0f0ff0ff;
1965 		break;
1966 	}
1967 	sta_entry->ratr_index = ratr_index;
1968 
1969 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1970 		"ratr_bitmap :%x\n", ratr_bitmap);
1971 	*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1972 				     (ratr_index << 28);
1973 	rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1974 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1975 		"Rate_index:%x, ratr_val:%x, %5phC\n",
1976 		ratr_index, ratr_bitmap, rate_mask);
1977 	rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1978 }
1979 
1980 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1981 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1982 {
1983 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1984 
1985 	if (rtlpriv->dm.useramask)
1986 		rtl92ce_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
1987 	else
1988 		rtl92ce_update_hal_rate_table(hw, sta);
1989 }
1990 
1991 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1992 {
1993 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1994 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1995 	u16 sifs_timer;
1996 
1997 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1998 				      &mac->slot_time);
1999 	if (!mac->ht_enable)
2000 		sifs_timer = 0x0a0a;
2001 	else
2002 		sifs_timer = 0x1010;
2003 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2004 }
2005 
2006 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2007 {
2008 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2009 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2010 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2011 	enum rf_pwrstate e_rfpowerstate_toset;
2012 	u8 u1tmp;
2013 	bool actuallyset = false;
2014 	unsigned long flag;
2015 
2016 	if (rtlpci->being_init_adapter)
2017 		return false;
2018 
2019 	if (ppsc->swrf_processing)
2020 		return false;
2021 
2022 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2023 	if (ppsc->rfchange_inprogress) {
2024 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2025 		return false;
2026 	} else {
2027 		ppsc->rfchange_inprogress = true;
2028 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2029 	}
2030 
2031 	rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2032 		       REG_MAC_PINMUX_CFG)&~(BIT(3)));
2033 
2034 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2035 	e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2036 
2037 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2038 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2039 			"GPIOChangeRF  - HW Radio ON, RF ON\n");
2040 
2041 		e_rfpowerstate_toset = ERFON;
2042 		ppsc->hwradiooff = false;
2043 		actuallyset = true;
2044 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2045 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2046 			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2047 
2048 		e_rfpowerstate_toset = ERFOFF;
2049 		ppsc->hwradiooff = true;
2050 		actuallyset = true;
2051 	}
2052 
2053 	if (actuallyset) {
2054 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2055 		ppsc->rfchange_inprogress = false;
2056 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2057 	} else {
2058 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2059 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2060 
2061 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2062 		ppsc->rfchange_inprogress = false;
2063 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2064 	}
2065 
2066 	*valid = 1;
2067 	return !ppsc->hwradiooff;
2068 
2069 }
2070 
2071 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2072 		     u8 *p_macaddr, bool is_group, u8 enc_algo,
2073 		     bool is_wepkey, bool clear_all)
2074 {
2075 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2076 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2077 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2078 	u8 *macaddr = p_macaddr;
2079 	u32 entry_id = 0;
2080 	bool is_pairwise = false;
2081 
2082 	static u8 cam_const_addr[4][6] = {
2083 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2084 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2085 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2086 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2087 	};
2088 	static u8 cam_const_broad[] = {
2089 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2090 	};
2091 
2092 	if (clear_all) {
2093 		u8 idx = 0;
2094 		u8 cam_offset = 0;
2095 		u8 clear_number = 5;
2096 
2097 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2098 
2099 		for (idx = 0; idx < clear_number; idx++) {
2100 			rtl_cam_mark_invalid(hw, cam_offset + idx);
2101 			rtl_cam_empty_entry(hw, cam_offset + idx);
2102 
2103 			if (idx < 5) {
2104 				memset(rtlpriv->sec.key_buf[idx], 0,
2105 				       MAX_KEY_LEN);
2106 				rtlpriv->sec.key_len[idx] = 0;
2107 			}
2108 		}
2109 
2110 	} else {
2111 		switch (enc_algo) {
2112 		case WEP40_ENCRYPTION:
2113 			enc_algo = CAM_WEP40;
2114 			break;
2115 		case WEP104_ENCRYPTION:
2116 			enc_algo = CAM_WEP104;
2117 			break;
2118 		case TKIP_ENCRYPTION:
2119 			enc_algo = CAM_TKIP;
2120 			break;
2121 		case AESCCMP_ENCRYPTION:
2122 			enc_algo = CAM_AES;
2123 			break;
2124 		default:
2125 			pr_err("switch case %#x not processed\n",
2126 			       enc_algo);
2127 			enc_algo = CAM_TKIP;
2128 			break;
2129 		}
2130 
2131 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2132 			macaddr = cam_const_addr[key_index];
2133 			entry_id = key_index;
2134 		} else {
2135 			if (is_group) {
2136 				macaddr = cam_const_broad;
2137 				entry_id = key_index;
2138 			} else {
2139 				if (mac->opmode == NL80211_IFTYPE_AP ||
2140 				    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2141 					entry_id = rtl_cam_get_free_entry(hw,
2142 								 p_macaddr);
2143 					if (entry_id >=  TOTAL_CAM_ENTRY) {
2144 						pr_err("Can not find free hw security cam entry\n");
2145 						return;
2146 					}
2147 				} else {
2148 					entry_id = CAM_PAIRWISE_KEY_POSITION;
2149 				}
2150 
2151 				key_index = PAIRWISE_KEYIDX;
2152 				is_pairwise = true;
2153 			}
2154 		}
2155 
2156 		if (rtlpriv->sec.key_len[key_index] == 0) {
2157 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2158 				"delete one entry, entry_id is %d\n",
2159 				 entry_id);
2160 			if (mac->opmode == NL80211_IFTYPE_AP ||
2161 			    mac->opmode == NL80211_IFTYPE_MESH_POINT)
2162 				rtl_cam_del_entry(hw, p_macaddr);
2163 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2164 		} else {
2165 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2166 				"The insert KEY length is %d\n",
2167 				rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2168 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2169 				"The insert KEY is %x %x\n",
2170 				rtlpriv->sec.key_buf[0][0],
2171 				rtlpriv->sec.key_buf[0][1]);
2172 
2173 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2174 				"add one entry\n");
2175 			if (is_pairwise) {
2176 				RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2177 					      "Pairwise Key content",
2178 					      rtlpriv->sec.pairwise_key,
2179 					      rtlpriv->sec.
2180 					      key_len[PAIRWISE_KEYIDX]);
2181 
2182 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2183 					"set Pairwise key\n");
2184 
2185 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2186 						      entry_id, enc_algo,
2187 						      CAM_CONFIG_NO_USEDK,
2188 						      rtlpriv->sec.
2189 						      key_buf[key_index]);
2190 			} else {
2191 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2192 					"set group key\n");
2193 
2194 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2195 					rtl_cam_add_one_entry(hw,
2196 						rtlefuse->dev_addr,
2197 						PAIRWISE_KEYIDX,
2198 						CAM_PAIRWISE_KEY_POSITION,
2199 						enc_algo,
2200 						CAM_CONFIG_NO_USEDK,
2201 						rtlpriv->sec.key_buf
2202 						[entry_id]);
2203 				}
2204 
2205 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2206 						entry_id, enc_algo,
2207 						CAM_CONFIG_NO_USEDK,
2208 						rtlpriv->sec.key_buf[entry_id]);
2209 			}
2210 
2211 		}
2212 	}
2213 }
2214 
2215 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2216 {
2217 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2218 
2219 	rtlpriv->btcoexist.bt_coexistence =
2220 			rtlpriv->btcoexist.eeprom_bt_coexist;
2221 	rtlpriv->btcoexist.bt_ant_num =
2222 			rtlpriv->btcoexist.eeprom_bt_ant_num;
2223 	rtlpriv->btcoexist.bt_coexist_type =
2224 			rtlpriv->btcoexist.eeprom_bt_type;
2225 
2226 	if (rtlpriv->btcoexist.reg_bt_iso == 2)
2227 		rtlpriv->btcoexist.bt_ant_isolation =
2228 			rtlpriv->btcoexist.eeprom_bt_ant_isol;
2229 	else
2230 		rtlpriv->btcoexist.bt_ant_isolation =
2231 			rtlpriv->btcoexist.reg_bt_iso;
2232 
2233 	rtlpriv->btcoexist.bt_radio_shared_type =
2234 			rtlpriv->btcoexist.eeprom_bt_radio_shared;
2235 
2236 	if (rtlpriv->btcoexist.bt_coexistence) {
2237 		if (rtlpriv->btcoexist.reg_bt_sco == 1)
2238 			rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2239 		else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2240 			rtlpriv->btcoexist.bt_service = BT_SCO;
2241 		else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2242 			rtlpriv->btcoexist.bt_service = BT_BUSY;
2243 		else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2244 			rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2245 		else
2246 			rtlpriv->btcoexist.bt_service = BT_IDLE;
2247 
2248 		rtlpriv->btcoexist.bt_edca_ul = 0;
2249 		rtlpriv->btcoexist.bt_edca_dl = 0;
2250 		rtlpriv->btcoexist.bt_rssi_state = 0xff;
2251 	}
2252 }
2253 
2254 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2255 					      bool auto_load_fail, u8 *hwinfo)
2256 {
2257 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2258 	u8 val;
2259 
2260 	if (!auto_load_fail) {
2261 		rtlpriv->btcoexist.eeprom_bt_coexist =
2262 					((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2263 		val = hwinfo[RF_OPTION4];
2264 		rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1);
2265 		rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1);
2266 		rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2267 		rtlpriv->btcoexist.eeprom_bt_radio_shared =
2268 							 ((val & 0x20) >> 5);
2269 	} else {
2270 		rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2271 		rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2272 		rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2273 		rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2274 		rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2275 	}
2276 
2277 	rtl8192ce_bt_var_init(hw);
2278 }
2279 
2280 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2281 {
2282 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2283 
2284 	/* 0:Low, 1:High, 2:From Efuse. */
2285 	rtlpriv->btcoexist.reg_bt_iso = 2;
2286 	/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2287 	rtlpriv->btcoexist.reg_bt_sco = 3;
2288 	/* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2289 	rtlpriv->btcoexist.reg_bt_sco = 0;
2290 }
2291 
2292 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2293 {
2294 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2295 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2296 
2297 	u8 u1_tmp;
2298 
2299 	if (rtlpriv->btcoexist.bt_coexistence &&
2300 	    ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2301 	      rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2302 
2303 		if (rtlpriv->btcoexist.bt_ant_isolation)
2304 			rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2305 
2306 		u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0);
2307 		u1_tmp = u1_tmp |
2308 			 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2309 			 0 : BIT(1)) |
2310 			 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2311 			 0 : BIT(2));
2312 		rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2313 
2314 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2315 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2316 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2317 
2318 		/* Config to 1T1R. */
2319 		if (rtlphy->rf_type == RF_1T1R) {
2320 			u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2321 			u1_tmp &= ~(BIT(1));
2322 			rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2323 
2324 			u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2325 			u1_tmp &= ~(BIT(1));
2326 			rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2327 		}
2328 	}
2329 }
2330 
2331 void rtl92ce_suspend(struct ieee80211_hw *hw)
2332 {
2333 }
2334 
2335 void rtl92ce_resume(struct ieee80211_hw *hw)
2336 {
2337 }
2338