xref: /linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c (revision 4b660dbd9ee2059850fd30e0df420ca7a38a1856)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2013  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../pci.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "dm.h"
11 #include "hw.h"
12 #include "trx.h"
13 #include "led.h"
14 #include "table.h"
15 
16 #include <linux/vmalloc.h>
17 #include <linux/module.h>
18 
19 static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
20 {
21 	struct rtl_priv *rtlpriv = rtl_priv(hw);
22 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
23 
24 	/* ASPM PS mode.
25 	 * 0 - Disable ASPM,
26 	 * 1 - Enable ASPM without Clock Req,
27 	 * 2 - Enable ASPM with Clock Req,
28 	 * 3 - Alwyas Enable ASPM with Clock Req,
29 	 * 4 - Always Enable ASPM without Clock Req.
30 	 * set defult to RTL8192CE:3 RTL8192E:2
31 	 */
32 	rtlpci->const_pci_aspm = 3;
33 
34 	/*Setting for PCI-E device */
35 	rtlpci->const_devicepci_aspm_setting = 0x03;
36 
37 	/*Setting for PCI-E bridge */
38 	rtlpci->const_hostpci_aspm_setting = 0x02;
39 
40 	/* In Hw/Sw Radio Off situation.
41 	 * 0 - Default,
42 	 * 1 - From ASPM setting without low Mac Pwr,
43 	 * 2 - From ASPM setting with low Mac Pwr,
44 	 * 3 - Bus D3
45 	 * set default to RTL8192CE:0 RTL8192SE:2
46 	 */
47 	rtlpci->const_hwsw_rfoff_d3 = 0;
48 
49 	/* This setting works for those device with
50 	 * backdoor ASPM setting such as EPHY setting.
51 	 * 0 - Not support ASPM,
52 	 * 1 - Support ASPM,
53 	 * 2 - According to chipset.
54 	 */
55 	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
56 }
57 
58 static int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
59 {
60 	int err = 0;
61 	struct rtl_priv *rtlpriv = rtl_priv(hw);
62 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
63 	u8 tid;
64 	char *fw_name;
65 
66 	rtl8188ee_bt_reg_init(hw);
67 	rtlpriv->dm.dm_initialgain_enable = true;
68 	rtlpriv->dm.dm_flag = 0;
69 	rtlpriv->dm.disable_framebursting = false;
70 	rtlpriv->dm.thermalvalue = 0;
71 	rtlpci->transmit_config = CFENDFORM | BIT(15);
72 
73 	/* compatible 5G band 88ce just 2.4G band & smsp */
74 	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
75 	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
76 	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
77 
78 	rtlpci->receive_config = (RCR_APPFCS |
79 				  RCR_APP_MIC |
80 				  RCR_APP_ICV |
81 				  RCR_APP_PHYST_RXFF |
82 				  RCR_HTC_LOC_CTRL |
83 				  RCR_AMF |
84 				  RCR_ACF |
85 				  RCR_ADF |
86 				  RCR_AICV |
87 				  RCR_ACRC32 |
88 				  RCR_AB |
89 				  RCR_AM |
90 				  RCR_APM |
91 				  0);
92 
93 	rtlpci->irq_mask[0] =
94 				(u32)(IMR_PSTIMEOUT	|
95 				IMR_HSISR_IND_ON_INT	|
96 				IMR_C2HCMD		|
97 				IMR_HIGHDOK		|
98 				IMR_MGNTDOK		|
99 				IMR_BKDOK		|
100 				IMR_BEDOK		|
101 				IMR_VIDOK		|
102 				IMR_VODOK		|
103 				IMR_RDU			|
104 				IMR_ROK			|
105 				0);
106 	rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
107 	rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
108 
109 	/* for LPS & IPS */
110 	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
111 	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
112 	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
113 	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
114 	if (rtlpriv->cfg->mod_params->disable_watchdog)
115 		pr_info("watchdog disabled\n");
116 	if (!rtlpriv->psc.inactiveps)
117 		pr_info("rtl8188ee: Power Save off (module option)\n");
118 	if (!rtlpriv->psc.fwctrl_lps)
119 		pr_info("rtl8188ee: FW Power Save off (module option)\n");
120 	rtlpriv->psc.reg_fwctrl_lps = 3;
121 	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
122 	/* for ASPM, you can close aspm through
123 	 * set const_support_pciaspm = 0
124 	 */
125 	rtl88e_init_aspm_vars(hw);
126 
127 	if (rtlpriv->psc.reg_fwctrl_lps == 1)
128 		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
129 	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
130 		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
131 	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
132 		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
133 
134 	/* for firmware buf */
135 	rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
136 	if (!rtlpriv->rtlhal.pfirmware) {
137 		pr_info("Can't alloc buffer for fw.\n");
138 		return 1;
139 	}
140 
141 	fw_name = "rtlwifi/rtl8188efw.bin";
142 	rtlpriv->max_fw_size = 0x8000;
143 	pr_info("Using firmware %s\n", fw_name);
144 	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
145 				      rtlpriv->io.dev, GFP_KERNEL, hw,
146 				      rtl_fw_cb);
147 	if (err) {
148 		pr_info("Failed to request firmware!\n");
149 		vfree(rtlpriv->rtlhal.pfirmware);
150 		rtlpriv->rtlhal.pfirmware = NULL;
151 		return 1;
152 	}
153 
154 	/* for early mode */
155 	rtlpriv->rtlhal.earlymode_enable = false;
156 	rtlpriv->rtlhal.max_earlymode_num = 10;
157 	for (tid = 0; tid < 8; tid++)
158 		skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
159 
160 	/*low power */
161 	rtlpriv->psc.low_power_enable = false;
162 	if (rtlpriv->psc.low_power_enable) {
163 		timer_setup(&rtlpriv->works.fw_clockoff_timer,
164 			    rtl88ee_fw_clk_off_timer_callback, 0);
165 	}
166 
167 	timer_setup(&rtlpriv->works.fast_antenna_training_timer,
168 		    rtl88e_dm_fast_antenna_training_callback, 0);
169 	return err;
170 }
171 
172 static void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
173 {
174 	struct rtl_priv *rtlpriv = rtl_priv(hw);
175 
176 	if (rtlpriv->rtlhal.pfirmware) {
177 		vfree(rtlpriv->rtlhal.pfirmware);
178 		rtlpriv->rtlhal.pfirmware = NULL;
179 	}
180 
181 	if (rtlpriv->psc.low_power_enable)
182 		del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
183 
184 	del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
185 }
186 
187 /* get bt coexist status */
188 static bool rtl88e_get_btc_status(void)
189 {
190 	return false;
191 }
192 
193 static struct rtl_hal_ops rtl8188ee_hal_ops = {
194 	.init_sw_vars = rtl88e_init_sw_vars,
195 	.deinit_sw_vars = rtl88e_deinit_sw_vars,
196 	.read_eeprom_info = rtl88ee_read_eeprom_info,
197 	.interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
198 	.hw_init = rtl88ee_hw_init,
199 	.hw_disable = rtl88ee_card_disable,
200 	.hw_suspend = rtl88ee_suspend,
201 	.hw_resume = rtl88ee_resume,
202 	.enable_interrupt = rtl88ee_enable_interrupt,
203 	.disable_interrupt = rtl88ee_disable_interrupt,
204 	.set_network_type = rtl88ee_set_network_type,
205 	.set_chk_bssid = rtl88ee_set_check_bssid,
206 	.set_qos = rtl88ee_set_qos,
207 	.set_bcn_reg = rtl88ee_set_beacon_related_registers,
208 	.set_bcn_intv = rtl88ee_set_beacon_interval,
209 	.update_interrupt_mask = rtl88ee_update_interrupt_mask,
210 	.get_hw_reg = rtl88ee_get_hw_reg,
211 	.set_hw_reg = rtl88ee_set_hw_reg,
212 	.update_rate_tbl = rtl88ee_update_hal_rate_tbl,
213 	.fill_tx_desc = rtl88ee_tx_fill_desc,
214 	.fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
215 	.query_rx_desc = rtl88ee_rx_query_desc,
216 	.set_channel_access = rtl88ee_update_channel_access_setting,
217 	.radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
218 	.set_bw_mode = rtl88e_phy_set_bw_mode,
219 	.switch_channel = rtl88e_phy_sw_chnl,
220 	.dm_watchdog = rtl88e_dm_watchdog,
221 	.scan_operation_backup = rtl88e_phy_scan_operation_backup,
222 	.set_rf_power_state = rtl88e_phy_set_rf_power_state,
223 	.led_control = rtl88ee_led_control,
224 	.set_desc = rtl88ee_set_desc,
225 	.get_desc = rtl88ee_get_desc,
226 	.is_tx_desc_closed = rtl88ee_is_tx_desc_closed,
227 	.tx_polling = rtl88ee_tx_polling,
228 	.enable_hw_sec = rtl88ee_enable_hw_security_config,
229 	.set_key = rtl88ee_set_key,
230 	.get_bbreg = rtl88e_phy_query_bb_reg,
231 	.set_bbreg = rtl88e_phy_set_bb_reg,
232 	.get_rfreg = rtl88e_phy_query_rf_reg,
233 	.set_rfreg = rtl88e_phy_set_rf_reg,
234 	.get_btc_status = rtl88e_get_btc_status,
235 };
236 
237 static struct rtl_mod_params rtl88ee_mod_params = {
238 	.sw_crypto = false,
239 	.inactiveps = true,
240 	.swctrl_lps = false,
241 	.fwctrl_lps = false,
242 	.msi_support = true,
243 	.aspm_support = 1,
244 	.debug_level = 0,
245 	.debug_mask = 0,
246 };
247 
248 static const struct rtl_hal_cfg rtl88ee_hal_cfg = {
249 	.bar_id = 2,
250 	.write_readback = true,
251 	.name = "rtl88e_pci",
252 	.ops = &rtl8188ee_hal_ops,
253 	.mod_params = &rtl88ee_mod_params,
254 
255 	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
256 	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
257 	.maps[SYS_CLK] = REG_SYS_CLKR,
258 	.maps[MAC_RCR_AM] = AM,
259 	.maps[MAC_RCR_AB] = AB,
260 	.maps[MAC_RCR_ACRC32] = ACRC32,
261 	.maps[MAC_RCR_ACF] = ACF,
262 	.maps[MAC_RCR_AAP] = AAP,
263 	.maps[MAC_HIMR] = REG_HIMR,
264 	.maps[MAC_HIMRE] = REG_HIMRE,
265 	.maps[MAC_HSISR] = REG_HSISR,
266 
267 	.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
268 
269 	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
270 	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
271 	.maps[EFUSE_CLK] = 0,
272 	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
273 	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
274 	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
275 	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
276 	.maps[EFUSE_ANA8M] = ANA8M,
277 	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
278 	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
279 	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
280 	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
281 
282 	.maps[RWCAM] = REG_CAMCMD,
283 	.maps[WCAMI] = REG_CAMWRITE,
284 	.maps[RCAMO] = REG_CAMREAD,
285 	.maps[CAMDBG] = REG_CAMDBG,
286 	.maps[SECR] = REG_SECCFG,
287 	.maps[SEC_CAM_NONE] = CAM_NONE,
288 	.maps[SEC_CAM_WEP40] = CAM_WEP40,
289 	.maps[SEC_CAM_TKIP] = CAM_TKIP,
290 	.maps[SEC_CAM_AES] = CAM_AES,
291 	.maps[SEC_CAM_WEP104] = CAM_WEP104,
292 
293 	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
294 	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
295 	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
296 	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
297 	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
298 	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
299 /*	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */   /*need check*/
300 	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
301 	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
302 	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
303 	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
304 	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
305 	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
306 	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
307 /*	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
308 /*	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
309 
310 	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
311 	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
312 	.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
313 	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
314 	.maps[RTL_IMR_RDU] = IMR_RDU,
315 	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
316 	.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
317 	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
318 	.maps[RTL_IMR_TBDER] = IMR_TBDER,
319 	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
320 	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
321 	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
322 	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
323 	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
324 	.maps[RTL_IMR_VODOK] = IMR_VODOK,
325 	.maps[RTL_IMR_ROK] = IMR_ROK,
326 	.maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
327 	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
328 
329 	.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
330 	.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
331 	.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
332 	.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
333 	.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
334 	.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
335 	.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
336 	.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
337 	.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
338 	.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
339 	.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
340 	.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
341 
342 	.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
343 	.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
344 };
345 
346 static const struct pci_device_id rtl88ee_pci_ids[] = {
347 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
348 	{},
349 };
350 
351 MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
352 
353 MODULE_AUTHOR("zhiyuan_yang	<zhiyuan_yang@realsil.com.cn>");
354 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
355 MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
356 MODULE_LICENSE("GPL");
357 MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
358 MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
359 
360 module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
361 module_param_named(debug_level, rtl88ee_mod_params.debug_level, int, 0644);
362 module_param_named(debug_mask, rtl88ee_mod_params.debug_mask, ullong, 0644);
363 module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
364 module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
365 module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
366 module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
367 module_param_named(aspm, rtl88ee_mod_params.aspm_support, int, 0444);
368 module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog,
369 		   bool, 0444);
370 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
371 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
372 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
373 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
374 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
375 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
376 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
377 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
378 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
379 
380 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
381 
382 static struct pci_driver rtl88ee_driver = {
383 	.name = KBUILD_MODNAME,
384 	.id_table = rtl88ee_pci_ids,
385 	.probe = rtl_pci_probe,
386 	.remove = rtl_pci_disconnect,
387 	.driver.pm = &rtlwifi_pm_ops,
388 };
389 
390 module_pci_driver(rtl88ee_driver);
391