1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2013 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "../pwrseqcmd.h" 34 #include "reg.h" 35 #include "def.h" 36 #include "phy.h" 37 #include "dm.h" 38 #include "fw.h" 39 #include "led.h" 40 #include "hw.h" 41 #include "pwrseq.h" 42 43 #define LLT_CONFIG 5 44 45 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 46 u8 set_bits, u8 clear_bits) 47 { 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_priv *rtlpriv = rtl_priv(hw); 50 51 rtlpci->reg_bcn_ctrl_val |= set_bits; 52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 53 54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 55 } 56 57 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw) 58 { 59 struct rtl_priv *rtlpriv = rtl_priv(hw); 60 u8 tmp1byte; 61 62 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 65 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 66 tmp1byte &= ~(BIT(0)); 67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 68 } 69 70 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw) 71 { 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 u8 tmp1byte; 74 75 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 78 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 79 tmp1byte |= BIT(0); 80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 81 } 82 83 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw) 84 { 85 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); 86 } 87 88 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw) 89 { 90 struct rtl_priv *rtlpriv = rtl_priv(hw); 91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 92 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 93 unsigned long flags; 94 95 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 96 while (skb_queue_len(&ring->queue)) { 97 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 98 struct sk_buff *skb = __skb_dequeue(&ring->queue); 99 100 pci_unmap_single(rtlpci->pdev, 101 rtlpriv->cfg->ops->get_desc( 102 hw, 103 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 104 skb->len, PCI_DMA_TODEVICE); 105 kfree_skb(skb); 106 ring->idx = (ring->idx + 1) % ring->entries; 107 } 108 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 109 } 110 111 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw) 112 { 113 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0); 114 } 115 116 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw, 117 u8 rpwm_val, bool b_need_turn_off_ckk) 118 { 119 struct rtl_priv *rtlpriv = rtl_priv(hw); 120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 121 bool b_support_remote_wake_up; 122 u32 count = 0, isr_regaddr, content; 123 bool schedule_timer = b_need_turn_off_ckk; 124 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 125 (u8 *)(&b_support_remote_wake_up)); 126 127 if (!rtlhal->fw_ready) 128 return; 129 if (!rtlpriv->psc.fw_current_inpsmode) 130 return; 131 132 while (1) { 133 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 134 if (rtlhal->fw_clk_change_in_progress) { 135 while (rtlhal->fw_clk_change_in_progress) { 136 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 137 count++; 138 udelay(100); 139 if (count > 1000) 140 return; 141 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 142 } 143 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 144 } else { 145 rtlhal->fw_clk_change_in_progress = false; 146 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 147 break; 148 } 149 } 150 151 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) { 152 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 153 if (FW_PS_IS_ACK(rpwm_val)) { 154 isr_regaddr = REG_HISR; 155 content = rtl_read_dword(rtlpriv, isr_regaddr); 156 while (!(content & IMR_CPWM) && (count < 500)) { 157 udelay(50); 158 count++; 159 content = rtl_read_dword(rtlpriv, isr_regaddr); 160 } 161 162 if (content & IMR_CPWM) { 163 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 164 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E; 165 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 166 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n", 167 rtlhal->fw_ps_state); 168 } 169 } 170 171 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 172 rtlhal->fw_clk_change_in_progress = false; 173 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 174 if (schedule_timer) { 175 mod_timer(&rtlpriv->works.fw_clockoff_timer, 176 jiffies + MSECS(10)); 177 } 178 179 } else { 180 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 181 rtlhal->fw_clk_change_in_progress = false; 182 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 183 } 184 } 185 186 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw, 187 u8 rpwm_val) 188 { 189 struct rtl_priv *rtlpriv = rtl_priv(hw); 190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 192 struct rtl8192_tx_ring *ring; 193 enum rf_pwrstate rtstate; 194 bool schedule_timer = false; 195 u8 queue; 196 197 if (!rtlhal->fw_ready) 198 return; 199 if (!rtlpriv->psc.fw_current_inpsmode) 200 return; 201 if (!rtlhal->allow_sw_to_change_hwclc) 202 return; 203 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 204 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 205 return; 206 207 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 208 ring = &rtlpci->tx_ring[queue]; 209 if (skb_queue_len(&ring->queue)) { 210 schedule_timer = true; 211 break; 212 } 213 } 214 215 if (schedule_timer) { 216 mod_timer(&rtlpriv->works.fw_clockoff_timer, 217 jiffies + MSECS(10)); 218 return; 219 } 220 221 if (FW_PS_STATE(rtlhal->fw_ps_state) != 222 FW_PS_STATE_RF_OFF_LOW_PWR_88E) { 223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 224 if (!rtlhal->fw_clk_change_in_progress) { 225 rtlhal->fw_clk_change_in_progress = true; 226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 228 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 230 &rpwm_val); 231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 232 rtlhal->fw_clk_change_in_progress = false; 233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 234 } else { 235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 236 mod_timer(&rtlpriv->works.fw_clockoff_timer, 237 jiffies + MSECS(10)); 238 } 239 } 240 } 241 242 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw) 243 { 244 u8 rpwm_val = 0; 245 246 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK); 247 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true); 248 } 249 250 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw) 251 { 252 u8 rpwm_val = 0; 253 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E; 254 _rtl88ee_set_fw_clock_off(hw, rpwm_val); 255 } 256 void rtl88ee_fw_clk_off_timer_callback(unsigned long data) 257 { 258 struct ieee80211_hw *hw = (struct ieee80211_hw *)data; 259 260 _rtl88ee_set_fw_ps_rf_off_low_power(hw); 261 } 262 263 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw) 264 { 265 struct rtl_priv *rtlpriv = rtl_priv(hw); 266 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 267 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 268 bool fw_current_inps = false; 269 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 270 271 if (ppsc->low_power_enable) { 272 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */ 273 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false); 274 rtlhal->allow_sw_to_change_hwclc = false; 275 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 276 &fw_pwrmode); 277 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 278 (u8 *)(&fw_current_inps)); 279 } else { 280 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */ 281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 282 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 283 &fw_pwrmode); 284 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 285 (u8 *)(&fw_current_inps)); 286 } 287 } 288 289 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw) 290 { 291 struct rtl_priv *rtlpriv = rtl_priv(hw); 292 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 293 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 294 bool fw_current_inps = true; 295 u8 rpwm_val; 296 297 if (ppsc->low_power_enable) { 298 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */ 299 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 300 (u8 *)(&fw_current_inps)); 301 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 302 &ppsc->fwctrl_psmode); 303 rtlhal->allow_sw_to_change_hwclc = true; 304 _rtl88ee_set_fw_clock_off(hw, rpwm_val); 305 } else { 306 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */ 307 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 308 (u8 *)(&fw_current_inps)); 309 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 310 &ppsc->fwctrl_psmode); 311 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 312 } 313 } 314 315 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 316 { 317 struct rtl_priv *rtlpriv = rtl_priv(hw); 318 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 319 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 320 321 switch (variable) { 322 case HW_VAR_RCR: 323 *((u32 *)(val)) = rtlpci->receive_config; 324 break; 325 case HW_VAR_RF_STATE: 326 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 327 break; 328 case HW_VAR_FWLPS_RF_ON:{ 329 enum rf_pwrstate rfstate; 330 u32 val_rcr; 331 332 rtlpriv->cfg->ops->get_hw_reg(hw, 333 HW_VAR_RF_STATE, 334 (u8 *)(&rfstate)); 335 if (rfstate == ERFOFF) { 336 *((bool *)(val)) = true; 337 } else { 338 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 339 val_rcr &= 0x00070000; 340 if (val_rcr) 341 *((bool *)(val)) = false; 342 else 343 *((bool *)(val)) = true; 344 } 345 break; } 346 case HW_VAR_FW_PSMODE_STATUS: 347 *((bool *)(val)) = ppsc->fw_current_inpsmode; 348 break; 349 case HW_VAR_CORRECT_TSF:{ 350 u64 tsf; 351 u32 *ptsf_low = (u32 *)&tsf; 352 u32 *ptsf_high = ((u32 *)&tsf) + 1; 353 354 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 355 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 356 357 *((u64 *)(val)) = tsf; 358 break; } 359 case HAL_DEF_WOWLAN: 360 break; 361 default: 362 pr_err("switch case %#x not processed\n", variable); 363 break; 364 } 365 } 366 367 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 368 { 369 struct rtl_priv *rtlpriv = rtl_priv(hw); 370 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 371 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 372 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 373 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 374 u8 idx; 375 376 switch (variable) { 377 case HW_VAR_ETHER_ADDR: 378 for (idx = 0; idx < ETH_ALEN; idx++) { 379 rtl_write_byte(rtlpriv, (REG_MACID + idx), 380 val[idx]); 381 } 382 break; 383 case HW_VAR_BASIC_RATE:{ 384 u16 b_rate_cfg = ((u16 *)val)[0]; 385 u8 rate_index = 0; 386 b_rate_cfg = b_rate_cfg & 0x15f; 387 b_rate_cfg |= 0x01; 388 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 389 rtl_write_byte(rtlpriv, REG_RRSR + 1, 390 (b_rate_cfg >> 8) & 0xff); 391 while (b_rate_cfg > 0x1) { 392 b_rate_cfg = (b_rate_cfg >> 1); 393 rate_index++; 394 } 395 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 396 rate_index); 397 break; 398 } 399 case HW_VAR_BSSID: 400 for (idx = 0; idx < ETH_ALEN; idx++) { 401 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 402 val[idx]); 403 } 404 break; 405 case HW_VAR_SIFS: 406 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 407 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 408 409 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 410 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 411 412 if (!mac->ht_enable) 413 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 414 0x0e0e); 415 else 416 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 417 *((u16 *)val)); 418 break; 419 case HW_VAR_SLOT_TIME:{ 420 u8 e_aci; 421 422 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 423 "HW_VAR_SLOT_TIME %x\n", val[0]); 424 425 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 426 427 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 428 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 429 &e_aci); 430 } 431 break; 432 } 433 case HW_VAR_ACK_PREAMBLE:{ 434 u8 reg_tmp; 435 u8 short_preamble = (bool)*val; 436 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2); 437 if (short_preamble) { 438 reg_tmp |= 0x02; 439 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 440 2, reg_tmp); 441 } else { 442 reg_tmp |= 0xFD; 443 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 444 2, reg_tmp); 445 } 446 break; } 447 case HW_VAR_WPA_CONFIG: 448 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 449 break; 450 case HW_VAR_AMPDU_MIN_SPACE:{ 451 u8 min_spacing_to_set; 452 u8 sec_min_space; 453 454 min_spacing_to_set = *val; 455 if (min_spacing_to_set <= 7) { 456 sec_min_space = 0; 457 458 if (min_spacing_to_set < sec_min_space) 459 min_spacing_to_set = sec_min_space; 460 461 mac->min_space_cfg = ((mac->min_space_cfg & 462 0xf8) | 463 min_spacing_to_set); 464 465 *val = min_spacing_to_set; 466 467 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 468 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 469 mac->min_space_cfg); 470 471 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 472 mac->min_space_cfg); 473 } 474 break; } 475 case HW_VAR_SHORTGI_DENSITY:{ 476 u8 density_to_set; 477 478 density_to_set = *val; 479 mac->min_space_cfg |= (density_to_set << 3); 480 481 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 482 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 483 mac->min_space_cfg); 484 485 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 486 mac->min_space_cfg); 487 break; 488 } 489 case HW_VAR_AMPDU_FACTOR:{ 490 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 491 u8 factor_toset; 492 u8 *p_regtoset = NULL; 493 u8 index = 0; 494 495 p_regtoset = regtoset_normal; 496 497 factor_toset = *val; 498 if (factor_toset <= 3) { 499 factor_toset = (1 << (factor_toset + 2)); 500 if (factor_toset > 0xf) 501 factor_toset = 0xf; 502 503 for (index = 0; index < 4; index++) { 504 if ((p_regtoset[index] & 0xf0) > 505 (factor_toset << 4)) 506 p_regtoset[index] = 507 (p_regtoset[index] & 0x0f) | 508 (factor_toset << 4); 509 510 if ((p_regtoset[index] & 0x0f) > 511 factor_toset) 512 p_regtoset[index] = 513 (p_regtoset[index] & 0xf0) | 514 (factor_toset); 515 516 rtl_write_byte(rtlpriv, 517 (REG_AGGLEN_LMT + index), 518 p_regtoset[index]); 519 520 } 521 522 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 523 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 524 factor_toset); 525 } 526 break; } 527 case HW_VAR_AC_PARAM:{ 528 u8 e_aci = *val; 529 rtl88e_dm_init_edca_turbo(hw); 530 531 if (rtlpci->acm_method != EACMWAY2_SW) 532 rtlpriv->cfg->ops->set_hw_reg(hw, 533 HW_VAR_ACM_CTRL, 534 &e_aci); 535 break; } 536 case HW_VAR_ACM_CTRL:{ 537 u8 e_aci = *val; 538 union aci_aifsn *p_aci_aifsn = 539 (union aci_aifsn *)(&(mac->ac[0].aifs)); 540 u8 acm = p_aci_aifsn->f.acm; 541 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 542 543 acm_ctrl = acm_ctrl | 544 ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 545 546 if (acm) { 547 switch (e_aci) { 548 case AC0_BE: 549 acm_ctrl |= ACMHW_BEQEN; 550 break; 551 case AC2_VI: 552 acm_ctrl |= ACMHW_VIQEN; 553 break; 554 case AC3_VO: 555 acm_ctrl |= ACMHW_VOQEN; 556 break; 557 default: 558 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 559 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 560 acm); 561 break; 562 } 563 } else { 564 switch (e_aci) { 565 case AC0_BE: 566 acm_ctrl &= (~ACMHW_BEQEN); 567 break; 568 case AC2_VI: 569 acm_ctrl &= (~ACMHW_VIQEN); 570 break; 571 case AC3_VO: 572 acm_ctrl &= (~ACMHW_VOQEN); 573 break; 574 default: 575 pr_err("switch case %#x not processed\n", 576 e_aci); 577 break; 578 } 579 } 580 581 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 582 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 583 acm_ctrl); 584 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 585 break; } 586 case HW_VAR_RCR: 587 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 588 rtlpci->receive_config = ((u32 *)(val))[0]; 589 break; 590 case HW_VAR_RETRY_LIMIT:{ 591 u8 retry_limit = *val; 592 593 rtl_write_word(rtlpriv, REG_RL, 594 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 595 retry_limit << RETRY_LIMIT_LONG_SHIFT); 596 break; } 597 case HW_VAR_DUAL_TSF_RST: 598 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 599 break; 600 case HW_VAR_EFUSE_BYTES: 601 rtlefuse->efuse_usedbytes = *((u16 *)val); 602 break; 603 case HW_VAR_EFUSE_USAGE: 604 rtlefuse->efuse_usedpercentage = *val; 605 break; 606 case HW_VAR_IO_CMD: 607 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val)); 608 break; 609 case HW_VAR_SET_RPWM:{ 610 u8 rpwm_val; 611 612 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 613 udelay(1); 614 615 if (rpwm_val & BIT(7)) { 616 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 617 } else { 618 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7)); 619 } 620 break; } 621 case HW_VAR_H2C_FW_PWRMODE: 622 rtl88e_set_fw_pwrmode_cmd(hw, *val); 623 break; 624 case HW_VAR_FW_PSMODE_STATUS: 625 ppsc->fw_current_inpsmode = *((bool *)val); 626 break; 627 case HW_VAR_RESUME_CLK_ON: 628 _rtl88ee_set_fw_ps_rf_on(hw); 629 break; 630 case HW_VAR_FW_LPS_ACTION:{ 631 bool enter_fwlps = *((bool *)val); 632 633 if (enter_fwlps) 634 _rtl88ee_fwlps_enter(hw); 635 else 636 _rtl88ee_fwlps_leave(hw); 637 638 break; } 639 case HW_VAR_H2C_FW_JOINBSSRPT:{ 640 u8 mstatus = *val; 641 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 642 u8 count = 0, dlbcn_count = 0; 643 bool b_recover = false; 644 645 if (mstatus == RT_MEDIA_CONNECT) { 646 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 647 NULL); 648 649 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 650 rtl_write_byte(rtlpriv, REG_CR + 1, 651 (tmp_regcr | BIT(0))); 652 653 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 654 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 655 656 tmp_reg422 = 657 rtl_read_byte(rtlpriv, 658 REG_FWHW_TXQ_CTRL + 2); 659 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 660 tmp_reg422 & (~BIT(6))); 661 if (tmp_reg422 & BIT(6)) 662 b_recover = true; 663 664 do { 665 bcnvalid_reg = rtl_read_byte(rtlpriv, 666 REG_TDECTRL+2); 667 rtl_write_byte(rtlpriv, REG_TDECTRL+2, 668 (bcnvalid_reg | BIT(0))); 669 _rtl88ee_return_beacon_queue_skb(hw); 670 671 rtl88e_set_fw_rsvdpagepkt(hw, 0); 672 bcnvalid_reg = rtl_read_byte(rtlpriv, 673 REG_TDECTRL+2); 674 count = 0; 675 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 676 count++; 677 udelay(10); 678 bcnvalid_reg = 679 rtl_read_byte(rtlpriv, REG_TDECTRL+2); 680 } 681 dlbcn_count++; 682 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 683 684 if (bcnvalid_reg & BIT(0)) 685 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0)); 686 687 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 688 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 689 690 if (b_recover) { 691 rtl_write_byte(rtlpriv, 692 REG_FWHW_TXQ_CTRL + 2, 693 tmp_reg422); 694 } 695 696 rtl_write_byte(rtlpriv, REG_CR + 1, 697 (tmp_regcr & ~(BIT(0)))); 698 } 699 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); 700 break; } 701 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 702 rtl88e_set_p2p_ps_offload_cmd(hw, *val); 703 break; 704 case HW_VAR_AID:{ 705 u16 u2btmp; 706 707 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 708 u2btmp &= 0xC000; 709 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 710 mac->assoc_id)); 711 break; } 712 case HW_VAR_CORRECT_TSF:{ 713 u8 btype_ibss = *val; 714 715 if (btype_ibss) 716 _rtl88ee_stop_tx_beacon(hw); 717 718 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 719 720 rtl_write_dword(rtlpriv, REG_TSFTR, 721 (u32)(mac->tsf & 0xffffffff)); 722 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 723 (u32)((mac->tsf >> 32) & 0xffffffff)); 724 725 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 726 727 if (btype_ibss) 728 _rtl88ee_resume_tx_beacon(hw); 729 break; } 730 case HW_VAR_KEEP_ALIVE: { 731 u8 array[2]; 732 733 array[0] = 0xff; 734 array[1] = *((u8 *)val); 735 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL, 736 2, array); 737 break; } 738 default: 739 pr_err("switch case %#x not processed\n", variable); 740 break; 741 } 742 } 743 744 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 745 { 746 struct rtl_priv *rtlpriv = rtl_priv(hw); 747 bool status = true; 748 long count = 0; 749 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 750 _LLT_OP(_LLT_WRITE_ACCESS); 751 752 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 753 754 do { 755 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 756 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 757 break; 758 759 if (count > POLLING_LLT_THRESHOLD) { 760 pr_err("Failed to polling write LLT done at address %d!\n", 761 address); 762 status = false; 763 break; 764 } 765 } while (++count); 766 767 return status; 768 } 769 770 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw) 771 { 772 struct rtl_priv *rtlpriv = rtl_priv(hw); 773 unsigned short i; 774 u8 txpktbuf_bndy; 775 u8 maxpage; 776 bool status; 777 778 maxpage = 0xAF; 779 txpktbuf_bndy = 0xAB; 780 781 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01); 782 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29); 783 784 /*0x2600 MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */ 785 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy)); 786 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 787 788 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 789 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 790 791 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 792 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 793 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 794 795 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 796 status = _rtl88ee_llt_write(hw, i, i + 1); 797 if (true != status) 798 return status; 799 } 800 801 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 802 if (true != status) 803 return status; 804 805 for (i = txpktbuf_bndy; i < maxpage; i++) { 806 status = _rtl88ee_llt_write(hw, i, (i + 1)); 807 if (true != status) 808 return status; 809 } 810 811 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy); 812 if (true != status) 813 return status; 814 815 return true; 816 } 817 818 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw) 819 { 820 struct rtl_priv *rtlpriv = rtl_priv(hw); 821 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 822 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 823 824 if (rtlpriv->rtlhal.up_first_time) 825 return; 826 827 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 828 rtl88ee_sw_led_on(hw, pled0); 829 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 830 rtl88ee_sw_led_on(hw, pled0); 831 else 832 rtl88ee_sw_led_off(hw, pled0); 833 } 834 835 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw) 836 { 837 struct rtl_priv *rtlpriv = rtl_priv(hw); 838 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 839 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 840 841 u8 bytetmp; 842 u16 wordtmp; 843 844 /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */ 845 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0)); 846 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp); 847 /*Auto Power Down to CHIP-off State*/ 848 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 849 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 850 851 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 852 /* HW Power on sequence */ 853 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 854 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 855 RTL8188EE_NIC_ENABLE_FLOW)) { 856 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 857 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n"); 858 return false; 859 } 860 861 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 862 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 863 864 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2); 865 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2)); 866 867 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1); 868 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7)); 869 870 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1); 871 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1)); 872 873 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL); 874 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0)); 875 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2); 876 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0); 877 878 /*Add for wake up online*/ 879 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 880 881 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3)); 882 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1); 883 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4)))); 884 rtl_write_byte(rtlpriv, 0x367, 0x80); 885 886 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 887 rtl_write_byte(rtlpriv, REG_CR+1, 0x06); 888 rtl_write_byte(rtlpriv, MSR, 0x00); 889 890 if (!rtlhal->mac_func_enable) { 891 if (_rtl88ee_llt_table_init(hw) == false) { 892 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 893 "LLT table init fail\n"); 894 return false; 895 } 896 } 897 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 898 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 899 900 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 901 wordtmp &= 0xf; 902 wordtmp |= 0xE771; 903 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 904 905 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 906 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff); 907 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 908 909 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 910 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 911 DMA_BIT_MASK(32)); 912 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 913 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 914 DMA_BIT_MASK(32)); 915 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 916 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 917 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 918 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 919 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 920 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 921 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 922 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 923 rtl_write_dword(rtlpriv, REG_HQ_DESA, 924 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 925 DMA_BIT_MASK(32)); 926 rtl_write_dword(rtlpriv, REG_RX_DESA, 927 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 928 DMA_BIT_MASK(32)); 929 930 /* if we want to support 64 bit DMA, we should set it here, 931 * but now we do not support 64 bit DMA 932 */ 933 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 934 935 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 936 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */ 937 938 if (rtlhal->earlymode_enable) {/*Early mode enable*/ 939 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL); 940 bytetmp |= 0x1f; 941 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp); 942 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81); 943 } 944 _rtl88ee_gen_refresh_led_state(hw); 945 return true; 946 } 947 948 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw) 949 { 950 struct rtl_priv *rtlpriv = rtl_priv(hw); 951 u8 reg_bw_opmode; 952 u32 reg_ratr, reg_prsr; 953 954 reg_bw_opmode = BW_OPMODE_20MHZ; 955 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG | 956 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; 957 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 958 959 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 960 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 961 } 962 963 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw) 964 { 965 struct rtl_priv *rtlpriv = rtl_priv(hw); 966 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 967 u8 tmp1byte = 0; 968 u32 tmp4byte = 0, count = 0; 969 970 rtl_write_word(rtlpriv, 0x354, 0x8104); 971 rtl_write_word(rtlpriv, 0x358, 0x24); 972 973 rtl_write_word(rtlpriv, 0x350, 0x70c); 974 rtl_write_byte(rtlpriv, 0x352, 0x2); 975 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 976 count = 0; 977 while (tmp1byte && count < 20) { 978 udelay(10); 979 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 980 count++; 981 } 982 if (0 == tmp1byte) { 983 tmp4byte = rtl_read_dword(rtlpriv, 0x34c); 984 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31)); 985 rtl_write_word(rtlpriv, 0x350, 0xf70c); 986 rtl_write_byte(rtlpriv, 0x352, 0x1); 987 } 988 989 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 990 count = 0; 991 while (tmp1byte && count < 20) { 992 udelay(10); 993 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 994 count++; 995 } 996 997 rtl_write_word(rtlpriv, 0x350, 0x718); 998 rtl_write_byte(rtlpriv, 0x352, 0x2); 999 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 1000 count = 0; 1001 while (tmp1byte && count < 20) { 1002 udelay(10); 1003 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 1004 count++; 1005 } 1006 1007 if (ppsc->support_backdoor || (0 == tmp1byte)) { 1008 tmp4byte = rtl_read_dword(rtlpriv, 0x34c); 1009 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12)); 1010 rtl_write_word(rtlpriv, 0x350, 0xf718); 1011 rtl_write_byte(rtlpriv, 0x352, 0x1); 1012 } 1013 1014 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 1015 count = 0; 1016 while (tmp1byte && count < 20) { 1017 udelay(10); 1018 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 1019 count++; 1020 } 1021 } 1022 1023 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw) 1024 { 1025 struct rtl_priv *rtlpriv = rtl_priv(hw); 1026 u8 sec_reg_value; 1027 1028 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1029 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1030 rtlpriv->sec.pairwise_enc_algorithm, 1031 rtlpriv->sec.group_enc_algorithm); 1032 1033 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1034 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1035 "not open hw encryption\n"); 1036 return; 1037 } 1038 1039 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1040 1041 if (rtlpriv->sec.use_defaultkey) { 1042 sec_reg_value |= SCR_TXUSEDK; 1043 sec_reg_value |= SCR_RXUSEDK; 1044 } 1045 1046 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1047 1048 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1049 1050 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1051 "The SECR-value %x\n", sec_reg_value); 1052 1053 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1054 } 1055 1056 int rtl88ee_hw_init(struct ieee80211_hw *hw) 1057 { 1058 struct rtl_priv *rtlpriv = rtl_priv(hw); 1059 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1060 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1061 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1062 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1063 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1064 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1065 bool rtstatus = true; 1066 int err = 0; 1067 u8 tmp_u1b, u1byte; 1068 unsigned long flags; 1069 1070 rtlpriv->rtlhal.being_init_adapter = true; 1071 /* As this function can take a very long time (up to 350 ms) 1072 * and can be called with irqs disabled, reenable the irqs 1073 * to let the other devices continue being serviced. 1074 * 1075 * It is safe doing so since our own interrupts will only be enabled 1076 * in a subsequent step. 1077 */ 1078 local_save_flags(flags); 1079 local_irq_enable(); 1080 rtlhal->fw_ready = false; 1081 1082 rtlpriv->intf_ops->disable_aspm(hw); 1083 1084 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1); 1085 u1byte = rtl_read_byte(rtlpriv, REG_CR); 1086 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) { 1087 rtlhal->mac_func_enable = true; 1088 } else { 1089 rtlhal->mac_func_enable = false; 1090 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E; 1091 } 1092 1093 rtstatus = _rtl88ee_init_mac(hw); 1094 if (rtstatus != true) { 1095 pr_info("Init MAC failed\n"); 1096 err = 1; 1097 goto exit; 1098 } 1099 1100 err = rtl88e_download_fw(hw, false); 1101 if (err) { 1102 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1103 "Failed to download FW. Init HW without FW now..\n"); 1104 err = 1; 1105 goto exit; 1106 } 1107 rtlhal->fw_ready = true; 1108 /*fw related variable initialize */ 1109 rtlhal->last_hmeboxnum = 0; 1110 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E; 1111 rtlhal->fw_clk_change_in_progress = false; 1112 rtlhal->allow_sw_to_change_hwclc = false; 1113 ppsc->fw_current_inpsmode = false; 1114 1115 rtl88e_phy_mac_config(hw); 1116 /* because last function modify RCR, so we update 1117 * rcr var here, or TP will unstable for receive_config 1118 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1119 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1120 */ 1121 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1122 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 1123 1124 rtl88e_phy_bb_config(hw); 1125 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1126 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1127 1128 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1129 rtl88e_phy_rf_config(hw); 1130 1131 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1132 RF_CHNLBW, RFREG_OFFSET_MASK); 1133 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff; 1134 1135 _rtl88ee_hw_configure(hw); 1136 rtl_cam_reset_all_entry(hw); 1137 rtl88ee_enable_hw_security_config(hw); 1138 1139 rtlhal->mac_func_enable = true; 1140 ppsc->rfpwr_state = ERFON; 1141 1142 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1143 _rtl88ee_enable_aspm_back_door(hw); 1144 rtlpriv->intf_ops->enable_aspm(hw); 1145 1146 if (ppsc->rfpwr_state == ERFON) { 1147 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) || 1148 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) && 1149 (rtlhal->oem_id == RT_CID_819X_HP))) { 1150 rtl88e_phy_set_rfpath_switch(hw, true); 1151 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT; 1152 } else { 1153 rtl88e_phy_set_rfpath_switch(hw, false); 1154 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT; 1155 } 1156 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n", 1157 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ? 1158 ("MAIN_ANT") : ("AUX_ANT")); 1159 1160 if (rtlphy->iqk_initialized) { 1161 rtl88e_phy_iq_calibrate(hw, true); 1162 } else { 1163 rtl88e_phy_iq_calibrate(hw, false); 1164 rtlphy->iqk_initialized = true; 1165 } 1166 1167 rtl88e_dm_check_txpower_tracking(hw); 1168 rtl88e_phy_lc_calibrate(hw); 1169 } 1170 1171 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1172 if (!(tmp_u1b & BIT(0))) { 1173 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1174 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n"); 1175 } 1176 1177 if (!(tmp_u1b & BIT(4))) { 1178 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1179 tmp_u1b &= 0x0F; 1180 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1181 udelay(10); 1182 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1183 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n"); 1184 } 1185 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128)); 1186 rtl88e_dm_init(hw); 1187 exit: 1188 local_irq_restore(flags); 1189 rtlpriv->rtlhal.being_init_adapter = false; 1190 return err; 1191 } 1192 1193 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw) 1194 { 1195 struct rtl_priv *rtlpriv = rtl_priv(hw); 1196 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1197 enum version_8188e version = VERSION_UNKNOWN; 1198 u32 value32; 1199 1200 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1201 if (value32 & TRP_VAUX_EN) { 1202 version = (enum version_8188e) VERSION_TEST_CHIP_88E; 1203 } else { 1204 version = NORMAL_CHIP; 1205 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0); 1206 version = version | ((value32 & VENDOR_ID) ? 1207 CHIP_VENDOR_UMC : 0); 1208 } 1209 1210 rtlphy->rf_type = RF_1T1R; 1211 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1212 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ? 1213 "RF_2T2R" : "RF_1T1R"); 1214 1215 return version; 1216 } 1217 1218 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw, 1219 enum nl80211_iftype type) 1220 { 1221 struct rtl_priv *rtlpriv = rtl_priv(hw); 1222 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1223 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1224 u8 mode = MSR_NOLINK; 1225 1226 switch (type) { 1227 case NL80211_IFTYPE_UNSPECIFIED: 1228 mode = MSR_NOLINK; 1229 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1230 "Set Network type to NO LINK!\n"); 1231 break; 1232 case NL80211_IFTYPE_ADHOC: 1233 case NL80211_IFTYPE_MESH_POINT: 1234 mode = MSR_ADHOC; 1235 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1236 "Set Network type to Ad Hoc!\n"); 1237 break; 1238 case NL80211_IFTYPE_STATION: 1239 mode = MSR_INFRA; 1240 ledaction = LED_CTL_LINK; 1241 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1242 "Set Network type to STA!\n"); 1243 break; 1244 case NL80211_IFTYPE_AP: 1245 mode = MSR_AP; 1246 ledaction = LED_CTL_LINK; 1247 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1248 "Set Network type to AP!\n"); 1249 break; 1250 default: 1251 pr_err("Network type %d not support!\n", type); 1252 return 1; 1253 break; 1254 } 1255 1256 /* MSR_INFRA == Link in infrastructure network; 1257 * MSR_ADHOC == Link in ad hoc network; 1258 * Therefore, check link state is necessary. 1259 * 1260 * MSR_AP == AP mode; link state is not cared here. 1261 */ 1262 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1263 mode = MSR_NOLINK; 1264 ledaction = LED_CTL_NO_LINK; 1265 } 1266 1267 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1268 _rtl88ee_stop_tx_beacon(hw); 1269 _rtl88ee_enable_bcn_sub_func(hw); 1270 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1271 _rtl88ee_resume_tx_beacon(hw); 1272 _rtl88ee_disable_bcn_sub_func(hw); 1273 } else { 1274 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1275 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1276 mode); 1277 } 1278 1279 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1280 rtlpriv->cfg->ops->led_control(hw, ledaction); 1281 if (mode == MSR_AP) 1282 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1283 else 1284 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1285 return 0; 1286 } 1287 1288 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1289 { 1290 struct rtl_priv *rtlpriv = rtl_priv(hw); 1291 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1292 u32 reg_rcr = rtlpci->receive_config; 1293 1294 if (rtlpriv->psc.rfpwr_state != ERFON) 1295 return; 1296 1297 if (check_bssid == true) { 1298 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1299 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1300 (u8 *)(®_rcr)); 1301 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1302 } else if (check_bssid == false) { 1303 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1304 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 1305 rtlpriv->cfg->ops->set_hw_reg(hw, 1306 HW_VAR_RCR, (u8 *)(®_rcr)); 1307 } 1308 1309 } 1310 1311 int rtl88ee_set_network_type(struct ieee80211_hw *hw, 1312 enum nl80211_iftype type) 1313 { 1314 struct rtl_priv *rtlpriv = rtl_priv(hw); 1315 1316 if (_rtl88ee_set_media_status(hw, type)) 1317 return -EOPNOTSUPP; 1318 1319 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1320 if (type != NL80211_IFTYPE_AP && 1321 type != NL80211_IFTYPE_MESH_POINT) 1322 rtl88ee_set_check_bssid(hw, true); 1323 } else { 1324 rtl88ee_set_check_bssid(hw, false); 1325 } 1326 1327 return 0; 1328 } 1329 1330 /* don't set REG_EDCA_BE_PARAM here 1331 * because mac80211 will send pkt when scan 1332 */ 1333 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci) 1334 { 1335 struct rtl_priv *rtlpriv = rtl_priv(hw); 1336 rtl88e_dm_init_edca_turbo(hw); 1337 switch (aci) { 1338 case AC1_BK: 1339 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1340 break; 1341 case AC0_BE: 1342 break; 1343 case AC2_VI: 1344 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1345 break; 1346 case AC3_VO: 1347 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1348 break; 1349 default: 1350 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci); 1351 break; 1352 } 1353 } 1354 1355 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw) 1356 { 1357 struct rtl_priv *rtlpriv = rtl_priv(hw); 1358 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1359 1360 rtl_write_dword(rtlpriv, REG_HIMR, 1361 rtlpci->irq_mask[0] & 0xFFFFFFFF); 1362 rtl_write_dword(rtlpriv, REG_HIMRE, 1363 rtlpci->irq_mask[1] & 0xFFFFFFFF); 1364 rtlpci->irq_enabled = true; 1365 /* there are some C2H CMDs have been sent 1366 * before system interrupt is enabled, e.g., C2H, CPWM. 1367 * So we need to clear all C2H events that FW has notified, 1368 * otherwise FW won't schedule any commands anymore. 1369 */ 1370 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); 1371 /*enable system interrupt*/ 1372 rtl_write_dword(rtlpriv, REG_HSIMR, 1373 rtlpci->sys_irq_mask & 0xFFFFFFFF); 1374 } 1375 1376 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw) 1377 { 1378 struct rtl_priv *rtlpriv = rtl_priv(hw); 1379 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1380 1381 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 1382 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 1383 rtlpci->irq_enabled = false; 1384 /*synchronize_irq(rtlpci->pdev->irq);*/ 1385 } 1386 1387 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw) 1388 { 1389 struct rtl_priv *rtlpriv = rtl_priv(hw); 1390 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1391 u8 u1b_tmp; 1392 u32 count = 0; 1393 rtlhal->mac_func_enable = false; 1394 rtlpriv->intf_ops->enable_aspm(hw); 1395 1396 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n"); 1397 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL); 1398 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1))); 1399 1400 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1401 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) { 1402 udelay(10); 1403 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1404 count++; 1405 } 1406 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF); 1407 1408 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1409 PWR_INTF_PCI_MSK, 1410 RTL8188EE_NIC_LPS_ENTER_FLOW); 1411 1412 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1413 1414 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) 1415 rtl88e_firmware_selfreset(hw); 1416 1417 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1418 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); 1419 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1420 1421 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL); 1422 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0)))); 1423 1424 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1425 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW); 1426 1427 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); 1428 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3)))); 1429 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); 1430 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3))); 1431 1432 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1433 1434 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN); 1435 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp); 1436 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F); 1437 1438 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 1439 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp); 1440 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1); 1441 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F); 1442 1443 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808); 1444 } 1445 1446 void rtl88ee_card_disable(struct ieee80211_hw *hw) 1447 { 1448 struct rtl_priv *rtlpriv = rtl_priv(hw); 1449 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1450 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1451 enum nl80211_iftype opmode; 1452 1453 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n"); 1454 1455 mac->link_state = MAC80211_NOLINK; 1456 opmode = NL80211_IFTYPE_UNSPECIFIED; 1457 1458 _rtl88ee_set_media_status(hw, opmode); 1459 1460 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1461 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1462 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1463 1464 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1465 _rtl88ee_poweroff_adapter(hw); 1466 1467 /* after power off we should do iqk again */ 1468 rtlpriv->phy.iqk_initialized = false; 1469 } 1470 1471 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw, 1472 u32 *p_inta, u32 *p_intb) 1473 { 1474 struct rtl_priv *rtlpriv = rtl_priv(hw); 1475 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1476 1477 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1478 rtl_write_dword(rtlpriv, ISR, *p_inta); 1479 1480 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1481 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb); 1482 1483 } 1484 1485 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw) 1486 { 1487 struct rtl_priv *rtlpriv = rtl_priv(hw); 1488 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1489 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1490 u16 bcn_interval, atim_window; 1491 1492 bcn_interval = mac->beacon_interval; 1493 atim_window = 2; /*FIX MERGE */ 1494 rtl88ee_disable_interrupt(hw); 1495 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1496 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1497 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1498 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1499 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1500 rtl_write_byte(rtlpriv, 0x606, 0x30); 1501 rtlpci->reg_bcn_ctrl_val |= BIT(3); 1502 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 1503 /*rtl88ee_enable_interrupt(hw);*/ 1504 } 1505 1506 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw) 1507 { 1508 struct rtl_priv *rtlpriv = rtl_priv(hw); 1509 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1510 u16 bcn_interval = mac->beacon_interval; 1511 1512 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1513 "beacon_interval:%d\n", bcn_interval); 1514 /*rtl88ee_disable_interrupt(hw);*/ 1515 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1516 /*rtl88ee_enable_interrupt(hw);*/ 1517 } 1518 1519 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw, 1520 u32 add_msr, u32 rm_msr) 1521 { 1522 struct rtl_priv *rtlpriv = rtl_priv(hw); 1523 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1524 1525 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1526 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1527 1528 if (add_msr) 1529 rtlpci->irq_mask[0] |= add_msr; 1530 if (rm_msr) 1531 rtlpci->irq_mask[0] &= (~rm_msr); 1532 rtl88ee_disable_interrupt(hw); 1533 rtl88ee_enable_interrupt(hw); 1534 } 1535 1536 static u8 _rtl88e_get_chnl_group(u8 chnl) 1537 { 1538 u8 group = 0; 1539 1540 if (chnl < 3) 1541 group = 0; 1542 else if (chnl < 6) 1543 group = 1; 1544 else if (chnl < 9) 1545 group = 2; 1546 else if (chnl < 12) 1547 group = 3; 1548 else if (chnl < 14) 1549 group = 4; 1550 else if (chnl == 14) 1551 group = 5; 1552 1553 return group; 1554 } 1555 1556 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath) 1557 { 1558 int group, txcnt; 1559 1560 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1561 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D; 1562 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D; 1563 } 1564 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) { 1565 if (txcnt == 0) { 1566 pwrinfo24g->bw20_diff[rfpath][0] = 0x02; 1567 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04; 1568 } else { 1569 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE; 1570 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE; 1571 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE; 1572 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE; 1573 } 1574 } 1575 } 1576 1577 static void read_power_value_fromprom(struct ieee80211_hw *hw, 1578 struct txpower_info_2g *pwrinfo24g, 1579 struct txpower_info_5g *pwrinfo5g, 1580 bool autoload_fail, u8 *hwinfo) 1581 { 1582 struct rtl_priv *rtlpriv = rtl_priv(hw); 1583 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0; 1584 1585 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1586 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n", 1587 (eeaddr+1), hwinfo[eeaddr+1]); 1588 if (0xFF == hwinfo[eeaddr+1]) /*YJ,add,120316*/ 1589 autoload_fail = true; 1590 1591 if (autoload_fail) { 1592 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1593 "auto load fail : Use Default value!\n"); 1594 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 1595 /* 2.4G default value */ 1596 set_24g_base(pwrinfo24g, rfpath); 1597 } 1598 return; 1599 } 1600 1601 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 1602 /*2.4G default value*/ 1603 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1604 pwrinfo24g->index_cck_base[rfpath][group] = 1605 hwinfo[eeaddr++]; 1606 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF) 1607 pwrinfo24g->index_cck_base[rfpath][group] = 1608 0x2D; 1609 } 1610 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) { 1611 pwrinfo24g->index_bw40_base[rfpath][group] = 1612 hwinfo[eeaddr++]; 1613 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF) 1614 pwrinfo24g->index_bw40_base[rfpath][group] = 1615 0x2D; 1616 } 1617 pwrinfo24g->bw40_diff[rfpath][0] = 0; 1618 if (hwinfo[eeaddr] == 0xFF) { 1619 pwrinfo24g->bw20_diff[rfpath][0] = 0x02; 1620 } else { 1621 pwrinfo24g->bw20_diff[rfpath][0] = 1622 (hwinfo[eeaddr]&0xf0)>>4; 1623 /*bit sign number to 8 bit sign number*/ 1624 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3)) 1625 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0; 1626 } 1627 1628 if (hwinfo[eeaddr] == 0xFF) { 1629 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04; 1630 } else { 1631 pwrinfo24g->ofdm_diff[rfpath][0] = 1632 (hwinfo[eeaddr]&0x0f); 1633 /*bit sign number to 8 bit sign number*/ 1634 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3)) 1635 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0; 1636 } 1637 pwrinfo24g->cck_diff[rfpath][0] = 0; 1638 eeaddr++; 1639 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) { 1640 if (hwinfo[eeaddr] == 0xFF) { 1641 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE; 1642 } else { 1643 pwrinfo24g->bw40_diff[rfpath][txcnt] = 1644 (hwinfo[eeaddr]&0xf0)>>4; 1645 if (pwrinfo24g->bw40_diff[rfpath][txcnt] & 1646 BIT(3)) 1647 pwrinfo24g->bw40_diff[rfpath][txcnt] |= 1648 0xF0; 1649 } 1650 1651 if (hwinfo[eeaddr] == 0xFF) { 1652 pwrinfo24g->bw20_diff[rfpath][txcnt] = 1653 0xFE; 1654 } else { 1655 pwrinfo24g->bw20_diff[rfpath][txcnt] = 1656 (hwinfo[eeaddr]&0x0f); 1657 if (pwrinfo24g->bw20_diff[rfpath][txcnt] & 1658 BIT(3)) 1659 pwrinfo24g->bw20_diff[rfpath][txcnt] |= 1660 0xF0; 1661 } 1662 eeaddr++; 1663 1664 if (hwinfo[eeaddr] == 0xFF) { 1665 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE; 1666 } else { 1667 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 1668 (hwinfo[eeaddr]&0xf0)>>4; 1669 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] & 1670 BIT(3)) 1671 pwrinfo24g->ofdm_diff[rfpath][txcnt] |= 1672 0xF0; 1673 } 1674 1675 if (hwinfo[eeaddr] == 0xFF) { 1676 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE; 1677 } else { 1678 pwrinfo24g->cck_diff[rfpath][txcnt] = 1679 (hwinfo[eeaddr]&0x0f); 1680 if (pwrinfo24g->cck_diff[rfpath][txcnt] & 1681 BIT(3)) 1682 pwrinfo24g->cck_diff[rfpath][txcnt] |= 1683 0xF0; 1684 } 1685 eeaddr++; 1686 } 1687 1688 /*5G default value*/ 1689 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 1690 pwrinfo5g->index_bw40_base[rfpath][group] = 1691 hwinfo[eeaddr++]; 1692 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF) 1693 pwrinfo5g->index_bw40_base[rfpath][group] = 1694 0xFE; 1695 } 1696 1697 pwrinfo5g->bw40_diff[rfpath][0] = 0; 1698 1699 if (hwinfo[eeaddr] == 0xFF) { 1700 pwrinfo5g->bw20_diff[rfpath][0] = 0; 1701 } else { 1702 pwrinfo5g->bw20_diff[rfpath][0] = 1703 (hwinfo[eeaddr]&0xf0)>>4; 1704 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3)) 1705 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0; 1706 } 1707 1708 if (hwinfo[eeaddr] == 0xFF) { 1709 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04; 1710 } else { 1711 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f); 1712 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3)) 1713 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0; 1714 } 1715 eeaddr++; 1716 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) { 1717 if (hwinfo[eeaddr] == 0xFF) { 1718 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE; 1719 } else { 1720 pwrinfo5g->bw40_diff[rfpath][txcnt] = 1721 (hwinfo[eeaddr]&0xf0)>>4; 1722 if (pwrinfo5g->bw40_diff[rfpath][txcnt] & 1723 BIT(3)) 1724 pwrinfo5g->bw40_diff[rfpath][txcnt] |= 1725 0xF0; 1726 } 1727 1728 if (hwinfo[eeaddr] == 0xFF) { 1729 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE; 1730 } else { 1731 pwrinfo5g->bw20_diff[rfpath][txcnt] = 1732 (hwinfo[eeaddr]&0x0f); 1733 if (pwrinfo5g->bw20_diff[rfpath][txcnt] & 1734 BIT(3)) 1735 pwrinfo5g->bw20_diff[rfpath][txcnt] |= 1736 0xF0; 1737 } 1738 eeaddr++; 1739 } 1740 1741 if (hwinfo[eeaddr] == 0xFF) { 1742 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE; 1743 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE; 1744 } else { 1745 pwrinfo5g->ofdm_diff[rfpath][1] = 1746 (hwinfo[eeaddr]&0xf0)>>4; 1747 pwrinfo5g->ofdm_diff[rfpath][2] = 1748 (hwinfo[eeaddr]&0x0f); 1749 } 1750 eeaddr++; 1751 1752 if (hwinfo[eeaddr] == 0xFF) 1753 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE; 1754 else 1755 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f); 1756 eeaddr++; 1757 1758 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) { 1759 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF) 1760 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE; 1761 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3)) 1762 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0; 1763 } 1764 } 1765 } 1766 1767 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1768 bool autoload_fail, 1769 u8 *hwinfo) 1770 { 1771 struct rtl_priv *rtlpriv = rtl_priv(hw); 1772 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1773 struct txpower_info_2g pwrinfo24g; 1774 struct txpower_info_5g pwrinfo5g; 1775 u8 rf_path, index; 1776 u8 i; 1777 1778 read_power_value_fromprom(hw, &pwrinfo24g, 1779 &pwrinfo5g, autoload_fail, hwinfo); 1780 1781 for (rf_path = 0; rf_path < 2; rf_path++) { 1782 for (i = 0; i < 14; i++) { 1783 index = _rtl88e_get_chnl_group(i+1); 1784 1785 rtlefuse->txpwrlevel_cck[rf_path][i] = 1786 pwrinfo24g.index_cck_base[rf_path][index]; 1787 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1788 pwrinfo24g.index_bw40_base[rf_path][index]; 1789 rtlefuse->txpwr_ht20diff[rf_path][i] = 1790 pwrinfo24g.bw20_diff[rf_path][0]; 1791 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 1792 pwrinfo24g.ofdm_diff[rf_path][0]; 1793 } 1794 1795 for (i = 0; i < 14; i++) { 1796 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1797 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n", 1798 rf_path, i, 1799 rtlefuse->txpwrlevel_cck[rf_path][i], 1800 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]); 1801 } 1802 } 1803 1804 if (!autoload_fail) 1805 rtlefuse->eeprom_thermalmeter = 1806 hwinfo[EEPROM_THERMAL_METER_88E]; 1807 else 1808 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1809 1810 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) { 1811 rtlefuse->apk_thermalmeterignore = true; 1812 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1813 } 1814 1815 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1816 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1817 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1818 1819 if (!autoload_fail) { 1820 rtlefuse->eeprom_regulatory = 1821 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/ 1822 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) 1823 rtlefuse->eeprom_regulatory = 0; 1824 } else { 1825 rtlefuse->eeprom_regulatory = 0; 1826 } 1827 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1828 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1829 } 1830 1831 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw) 1832 { 1833 struct rtl_priv *rtlpriv = rtl_priv(hw); 1834 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1835 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1836 int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1837 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1838 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1839 COUNTRY_CODE_WORLD_WIDE_13}; 1840 u8 *hwinfo; 1841 1842 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1843 if (!hwinfo) 1844 return; 1845 1846 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1847 goto exit; 1848 1849 if (rtlefuse->eeprom_oemid == 0xFF) 1850 rtlefuse->eeprom_oemid = 0; 1851 1852 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1853 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); 1854 /* set channel plan from efuse */ 1855 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 1856 /*tx power*/ 1857 _rtl88ee_read_txpower_info_from_hwpg(hw, 1858 rtlefuse->autoload_failflag, 1859 hwinfo); 1860 rtlefuse->txpwr_fromeprom = true; 1861 1862 rtl8188ee_read_bt_coexist_info_from_hwpg(hw, 1863 rtlefuse->autoload_failflag, 1864 hwinfo); 1865 1866 /*board type*/ 1867 rtlefuse->board_type = 1868 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5); 1869 rtlhal->board_type = rtlefuse->board_type; 1870 /*Wake on wlan*/ 1871 rtlefuse->wowlan_enable = 1872 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6); 1873 /*parse xtal*/ 1874 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E]; 1875 if (hwinfo[EEPROM_XTAL_88E]) 1876 rtlefuse->crystalcap = 0x20; 1877 /*antenna diversity*/ 1878 rtlefuse->antenna_div_cfg = 1879 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3; 1880 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) 1881 rtlefuse->antenna_div_cfg = 0; 1882 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 && 1883 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1) 1884 rtlefuse->antenna_div_cfg = 0; 1885 1886 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E]; 1887 if (rtlefuse->antenna_div_type == 0xFF) 1888 rtlefuse->antenna_div_type = 0x01; 1889 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV || 1890 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1891 rtlefuse->antenna_div_cfg = 1; 1892 1893 if (rtlhal->oem_id == RT_CID_DEFAULT) { 1894 switch (rtlefuse->eeprom_oemid) { 1895 case EEPROM_CID_DEFAULT: 1896 if (rtlefuse->eeprom_did == 0x8179) { 1897 if (rtlefuse->eeprom_svid == 0x1025) { 1898 rtlhal->oem_id = RT_CID_819X_ACER; 1899 } else if ((rtlefuse->eeprom_svid == 0x10EC && 1900 rtlefuse->eeprom_smid == 0x0179) || 1901 (rtlefuse->eeprom_svid == 0x17AA && 1902 rtlefuse->eeprom_smid == 0x0179)) { 1903 rtlhal->oem_id = RT_CID_819X_LENOVO; 1904 } else if (rtlefuse->eeprom_svid == 0x103c && 1905 rtlefuse->eeprom_smid == 0x197d) { 1906 rtlhal->oem_id = RT_CID_819X_HP; 1907 } else { 1908 rtlhal->oem_id = RT_CID_DEFAULT; 1909 } 1910 } else { 1911 rtlhal->oem_id = RT_CID_DEFAULT; 1912 } 1913 break; 1914 case EEPROM_CID_TOSHIBA: 1915 rtlhal->oem_id = RT_CID_TOSHIBA; 1916 break; 1917 case EEPROM_CID_QMI: 1918 rtlhal->oem_id = RT_CID_819X_QMI; 1919 break; 1920 case EEPROM_CID_WHQL: 1921 default: 1922 rtlhal->oem_id = RT_CID_DEFAULT; 1923 break; 1924 1925 } 1926 } 1927 exit: 1928 kfree(hwinfo); 1929 } 1930 1931 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw) 1932 { 1933 struct rtl_priv *rtlpriv = rtl_priv(hw); 1934 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1935 1936 rtlpriv->ledctl.led_opendrain = true; 1937 1938 switch (rtlhal->oem_id) { 1939 case RT_CID_819X_HP: 1940 rtlpriv->ledctl.led_opendrain = true; 1941 break; 1942 case RT_CID_819X_LENOVO: 1943 case RT_CID_DEFAULT: 1944 case RT_CID_TOSHIBA: 1945 case RT_CID_CCX: 1946 case RT_CID_819X_ACER: 1947 case RT_CID_WHQL: 1948 default: 1949 break; 1950 } 1951 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1952 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1953 } 1954 1955 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw) 1956 { 1957 struct rtl_priv *rtlpriv = rtl_priv(hw); 1958 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1959 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1960 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1961 u8 tmp_u1b; 1962 1963 rtlhal->version = _rtl88ee_read_chip_version(hw); 1964 if (get_rf_type(rtlphy) == RF_1T1R) 1965 rtlpriv->dm.rfpath_rxenable[0] = true; 1966 else 1967 rtlpriv->dm.rfpath_rxenable[0] = 1968 rtlpriv->dm.rfpath_rxenable[1] = true; 1969 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1970 rtlhal->version); 1971 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1972 if (tmp_u1b & BIT(4)) { 1973 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1974 rtlefuse->epromtype = EEPROM_93C46; 1975 } else { 1976 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1977 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1978 } 1979 if (tmp_u1b & BIT(5)) { 1980 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1981 rtlefuse->autoload_failflag = false; 1982 _rtl88ee_read_adapter_info(hw); 1983 } else { 1984 pr_err("Autoload ERR!!\n"); 1985 } 1986 _rtl88ee_hal_customized_behavior(hw); 1987 } 1988 1989 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw, 1990 struct ieee80211_sta *sta) 1991 { 1992 struct rtl_priv *rtlpriv = rtl_priv(hw); 1993 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1994 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1995 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1996 u32 ratr_value; 1997 u8 ratr_index = 0; 1998 u8 b_nmode = mac->ht_enable; 1999 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 2000 u16 shortgi_rate; 2001 u32 tmp_ratr_value; 2002 u8 curtxbw_40mhz = mac->bw_40; 2003 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2004 1 : 0; 2005 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2006 1 : 0; 2007 enum wireless_mode wirelessmode = mac->mode; 2008 u32 ratr_mask; 2009 2010 if (rtlhal->current_bandtype == BAND_ON_5G) 2011 ratr_value = sta->supp_rates[1] << 4; 2012 else 2013 ratr_value = sta->supp_rates[0]; 2014 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2015 ratr_value = 0xfff; 2016 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2017 sta->ht_cap.mcs.rx_mask[0] << 12); 2018 switch (wirelessmode) { 2019 case WIRELESS_MODE_B: 2020 if (ratr_value & 0x0000000c) 2021 ratr_value &= 0x0000000d; 2022 else 2023 ratr_value &= 0x0000000f; 2024 break; 2025 case WIRELESS_MODE_G: 2026 ratr_value &= 0x00000FF5; 2027 break; 2028 case WIRELESS_MODE_N_24G: 2029 case WIRELESS_MODE_N_5G: 2030 b_nmode = 1; 2031 if (get_rf_type(rtlphy) == RF_1T2R || 2032 get_rf_type(rtlphy) == RF_1T1R) 2033 ratr_mask = 0x000ff005; 2034 else 2035 ratr_mask = 0x0f0ff005; 2036 2037 ratr_value &= ratr_mask; 2038 break; 2039 default: 2040 if (rtlphy->rf_type == RF_1T2R) 2041 ratr_value &= 0x000ff0ff; 2042 else 2043 ratr_value &= 0x0f0ff0ff; 2044 2045 break; 2046 } 2047 2048 if ((rtlpriv->btcoexist.bt_coexistence) && 2049 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 2050 (rtlpriv->btcoexist.bt_cur_state) && 2051 (rtlpriv->btcoexist.bt_ant_isolation) && 2052 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 2053 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 2054 ratr_value &= 0x0fffcfc0; 2055 else 2056 ratr_value &= 0x0FFFFFFF; 2057 2058 if (b_nmode && 2059 ((curtxbw_40mhz && curshortgi_40mhz) || 2060 (!curtxbw_40mhz && curshortgi_20mhz))) { 2061 ratr_value |= 0x10000000; 2062 tmp_ratr_value = (ratr_value >> 12); 2063 2064 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2065 if ((1 << shortgi_rate) & tmp_ratr_value) 2066 break; 2067 } 2068 2069 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2070 (shortgi_rate << 4) | (shortgi_rate); 2071 } 2072 2073 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 2074 2075 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2076 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 2077 } 2078 2079 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw, 2080 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2081 { 2082 struct rtl_priv *rtlpriv = rtl_priv(hw); 2083 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2084 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2085 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2086 struct rtl_sta_info *sta_entry = NULL; 2087 u32 ratr_bitmap; 2088 u8 ratr_index; 2089 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 2090 ? 1 : 0; 2091 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2092 1 : 0; 2093 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2094 1 : 0; 2095 enum wireless_mode wirelessmode = 0; 2096 bool b_shortgi = false; 2097 u8 rate_mask[5]; 2098 u8 macid = 0; 2099 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 2100 2101 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 2102 wirelessmode = sta_entry->wireless_mode; 2103 if (mac->opmode == NL80211_IFTYPE_STATION || 2104 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2105 curtxbw_40mhz = mac->bw_40; 2106 else if (mac->opmode == NL80211_IFTYPE_AP || 2107 mac->opmode == NL80211_IFTYPE_ADHOC) 2108 macid = sta->aid + 1; 2109 2110 if (rtlhal->current_bandtype == BAND_ON_5G) 2111 ratr_bitmap = sta->supp_rates[1] << 4; 2112 else 2113 ratr_bitmap = sta->supp_rates[0]; 2114 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2115 ratr_bitmap = 0xfff; 2116 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2117 sta->ht_cap.mcs.rx_mask[0] << 12); 2118 switch (wirelessmode) { 2119 case WIRELESS_MODE_B: 2120 ratr_index = RATR_INX_WIRELESS_B; 2121 if (ratr_bitmap & 0x0000000c) 2122 ratr_bitmap &= 0x0000000d; 2123 else 2124 ratr_bitmap &= 0x0000000f; 2125 break; 2126 case WIRELESS_MODE_G: 2127 ratr_index = RATR_INX_WIRELESS_GB; 2128 2129 if (rssi_level == 1) 2130 ratr_bitmap &= 0x00000f00; 2131 else if (rssi_level == 2) 2132 ratr_bitmap &= 0x00000ff0; 2133 else 2134 ratr_bitmap &= 0x00000ff5; 2135 break; 2136 case WIRELESS_MODE_N_24G: 2137 case WIRELESS_MODE_N_5G: 2138 ratr_index = RATR_INX_WIRELESS_NGB; 2139 if (rtlphy->rf_type == RF_1T2R || 2140 rtlphy->rf_type == RF_1T1R) { 2141 if (curtxbw_40mhz) { 2142 if (rssi_level == 1) 2143 ratr_bitmap &= 0x000f0000; 2144 else if (rssi_level == 2) 2145 ratr_bitmap &= 0x000ff000; 2146 else 2147 ratr_bitmap &= 0x000ff015; 2148 } else { 2149 if (rssi_level == 1) 2150 ratr_bitmap &= 0x000f0000; 2151 else if (rssi_level == 2) 2152 ratr_bitmap &= 0x000ff000; 2153 else 2154 ratr_bitmap &= 0x000ff005; 2155 } 2156 } else { 2157 if (curtxbw_40mhz) { 2158 if (rssi_level == 1) 2159 ratr_bitmap &= 0x0f8f0000; 2160 else if (rssi_level == 2) 2161 ratr_bitmap &= 0x0f8ff000; 2162 else 2163 ratr_bitmap &= 0x0f8ff015; 2164 } else { 2165 if (rssi_level == 1) 2166 ratr_bitmap &= 0x0f8f0000; 2167 else if (rssi_level == 2) 2168 ratr_bitmap &= 0x0f8ff000; 2169 else 2170 ratr_bitmap &= 0x0f8ff005; 2171 } 2172 } 2173 /*}*/ 2174 2175 if ((curtxbw_40mhz && curshortgi_40mhz) || 2176 (!curtxbw_40mhz && curshortgi_20mhz)) { 2177 2178 if (macid == 0) 2179 b_shortgi = true; 2180 else if (macid == 1) 2181 b_shortgi = false; 2182 } 2183 break; 2184 default: 2185 ratr_index = RATR_INX_WIRELESS_NGB; 2186 2187 if (rtlphy->rf_type == RF_1T2R) 2188 ratr_bitmap &= 0x000ff0ff; 2189 else 2190 ratr_bitmap &= 0x0f0ff0ff; 2191 break; 2192 } 2193 sta_entry->ratr_index = ratr_index; 2194 2195 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2196 "ratr_bitmap :%x\n", ratr_bitmap); 2197 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2198 (ratr_index << 28); 2199 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80; 2200 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2201 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n", 2202 ratr_index, ratr_bitmap, 2203 rate_mask[0], rate_mask[1], 2204 rate_mask[2], rate_mask[3], 2205 rate_mask[4]); 2206 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask); 2207 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 2208 } 2209 2210 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw, 2211 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2212 { 2213 struct rtl_priv *rtlpriv = rtl_priv(hw); 2214 2215 if (rtlpriv->dm.useramask) 2216 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2217 else 2218 rtl88ee_update_hal_rate_table(hw, sta); 2219 } 2220 2221 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw) 2222 { 2223 struct rtl_priv *rtlpriv = rtl_priv(hw); 2224 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2225 u16 sifs_timer; 2226 2227 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); 2228 if (!mac->ht_enable) 2229 sifs_timer = 0x0a0a; 2230 else 2231 sifs_timer = 0x0e0e; 2232 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2233 } 2234 2235 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2236 { 2237 struct rtl_priv *rtlpriv = rtl_priv(hw); 2238 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2239 enum rf_pwrstate e_rfpowerstate_toset; 2240 u32 u4tmp; 2241 bool b_actuallyset = false; 2242 2243 if (rtlpriv->rtlhal.being_init_adapter) 2244 return false; 2245 2246 if (ppsc->swrf_processing) 2247 return false; 2248 2249 spin_lock(&rtlpriv->locks.rf_ps_lock); 2250 if (ppsc->rfchange_inprogress) { 2251 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2252 return false; 2253 } else { 2254 ppsc->rfchange_inprogress = true; 2255 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2256 } 2257 2258 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT); 2259 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF; 2260 2261 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { 2262 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2263 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2264 2265 e_rfpowerstate_toset = ERFON; 2266 ppsc->hwradiooff = false; 2267 b_actuallyset = true; 2268 } else if ((!ppsc->hwradiooff) && 2269 (e_rfpowerstate_toset == ERFOFF)) { 2270 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2271 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2272 2273 e_rfpowerstate_toset = ERFOFF; 2274 ppsc->hwradiooff = true; 2275 b_actuallyset = true; 2276 } 2277 2278 if (b_actuallyset) { 2279 spin_lock(&rtlpriv->locks.rf_ps_lock); 2280 ppsc->rfchange_inprogress = false; 2281 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2282 } else { 2283 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2284 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2285 2286 spin_lock(&rtlpriv->locks.rf_ps_lock); 2287 ppsc->rfchange_inprogress = false; 2288 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2289 } 2290 2291 *valid = 1; 2292 return !ppsc->hwradiooff; 2293 2294 } 2295 2296 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index, 2297 u8 *p_macaddr, bool is_group, u8 enc_algo, 2298 bool is_wepkey, bool clear_all) 2299 { 2300 struct rtl_priv *rtlpriv = rtl_priv(hw); 2301 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2302 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2303 u8 *macaddr = p_macaddr; 2304 u32 entry_id = 0; 2305 bool is_pairwise = false; 2306 static u8 cam_const_addr[4][6] = { 2307 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2308 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2309 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2310 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2311 }; 2312 static u8 cam_const_broad[] = { 2313 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2314 }; 2315 2316 if (clear_all) { 2317 u8 idx = 0; 2318 u8 cam_offset = 0; 2319 u8 clear_number = 5; 2320 2321 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2322 2323 for (idx = 0; idx < clear_number; idx++) { 2324 rtl_cam_mark_invalid(hw, cam_offset + idx); 2325 rtl_cam_empty_entry(hw, cam_offset + idx); 2326 2327 if (idx < 5) { 2328 memset(rtlpriv->sec.key_buf[idx], 0, 2329 MAX_KEY_LEN); 2330 rtlpriv->sec.key_len[idx] = 0; 2331 } 2332 } 2333 2334 } else { 2335 switch (enc_algo) { 2336 case WEP40_ENCRYPTION: 2337 enc_algo = CAM_WEP40; 2338 break; 2339 case WEP104_ENCRYPTION: 2340 enc_algo = CAM_WEP104; 2341 break; 2342 case TKIP_ENCRYPTION: 2343 enc_algo = CAM_TKIP; 2344 break; 2345 case AESCCMP_ENCRYPTION: 2346 enc_algo = CAM_AES; 2347 break; 2348 default: 2349 pr_err("switch case %#x not processed\n", 2350 enc_algo); 2351 enc_algo = CAM_TKIP; 2352 break; 2353 } 2354 2355 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2356 macaddr = cam_const_addr[key_index]; 2357 entry_id = key_index; 2358 } else { 2359 if (is_group) { 2360 macaddr = cam_const_broad; 2361 entry_id = key_index; 2362 } else { 2363 if (mac->opmode == NL80211_IFTYPE_AP || 2364 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2365 entry_id = 2366 rtl_cam_get_free_entry(hw, p_macaddr); 2367 if (entry_id >= TOTAL_CAM_ENTRY) { 2368 pr_err("Can not find free hw security cam entry\n"); 2369 return; 2370 } 2371 } else { 2372 entry_id = CAM_PAIRWISE_KEY_POSITION; 2373 } 2374 key_index = PAIRWISE_KEYIDX; 2375 is_pairwise = true; 2376 } 2377 } 2378 2379 if (rtlpriv->sec.key_len[key_index] == 0) { 2380 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2381 "delete one entry, entry_id is %d\n", 2382 entry_id); 2383 if (mac->opmode == NL80211_IFTYPE_AP || 2384 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2385 rtl_cam_del_entry(hw, p_macaddr); 2386 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2387 } else { 2388 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2389 "add one entry\n"); 2390 if (is_pairwise) { 2391 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2392 "set Pairwise key\n"); 2393 2394 rtl_cam_add_one_entry(hw, macaddr, key_index, 2395 entry_id, enc_algo, 2396 CAM_CONFIG_NO_USEDK, 2397 rtlpriv->sec.key_buf[key_index]); 2398 } else { 2399 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2400 "set group key\n"); 2401 2402 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2403 rtl_cam_add_one_entry(hw, 2404 rtlefuse->dev_addr, 2405 PAIRWISE_KEYIDX, 2406 CAM_PAIRWISE_KEY_POSITION, 2407 enc_algo, 2408 CAM_CONFIG_NO_USEDK, 2409 rtlpriv->sec.key_buf 2410 [entry_id]); 2411 } 2412 2413 rtl_cam_add_one_entry(hw, macaddr, key_index, 2414 entry_id, enc_algo, 2415 CAM_CONFIG_NO_USEDK, 2416 rtlpriv->sec.key_buf[entry_id]); 2417 } 2418 2419 } 2420 } 2421 } 2422 2423 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw) 2424 { 2425 struct rtl_priv *rtlpriv = rtl_priv(hw); 2426 2427 rtlpriv->btcoexist.bt_coexistence = 2428 rtlpriv->btcoexist.eeprom_bt_coexist; 2429 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num; 2430 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type; 2431 2432 if (rtlpriv->btcoexist.reg_bt_iso == 2) 2433 rtlpriv->btcoexist.bt_ant_isolation = 2434 rtlpriv->btcoexist.eeprom_bt_ant_isol; 2435 else 2436 rtlpriv->btcoexist.bt_ant_isolation = 2437 rtlpriv->btcoexist.reg_bt_iso; 2438 2439 rtlpriv->btcoexist.bt_radio_shared_type = 2440 rtlpriv->btcoexist.eeprom_bt_radio_shared; 2441 2442 if (rtlpriv->btcoexist.bt_coexistence) { 2443 if (rtlpriv->btcoexist.reg_bt_sco == 1) 2444 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION; 2445 else if (rtlpriv->btcoexist.reg_bt_sco == 2) 2446 rtlpriv->btcoexist.bt_service = BT_SCO; 2447 else if (rtlpriv->btcoexist.reg_bt_sco == 4) 2448 rtlpriv->btcoexist.bt_service = BT_BUSY; 2449 else if (rtlpriv->btcoexist.reg_bt_sco == 5) 2450 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY; 2451 else 2452 rtlpriv->btcoexist.bt_service = BT_IDLE; 2453 2454 rtlpriv->btcoexist.bt_edca_ul = 0; 2455 rtlpriv->btcoexist.bt_edca_dl = 0; 2456 rtlpriv->btcoexist.bt_rssi_state = 0xff; 2457 } 2458 } 2459 2460 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2461 bool auto_load_fail, u8 *hwinfo) 2462 { 2463 struct rtl_priv *rtlpriv = rtl_priv(hw); 2464 u8 value; 2465 2466 if (!auto_load_fail) { 2467 rtlpriv->btcoexist.eeprom_bt_coexist = 2468 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5); 2469 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF) 2470 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2471 value = hwinfo[EEPROM_RF_BT_SETTING_88E]; 2472 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1); 2473 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1); 2474 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4); 2475 rtlpriv->btcoexist.eeprom_bt_radio_shared = 2476 ((value & 0x20) >> 5); 2477 } else { 2478 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2479 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE; 2480 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2; 2481 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0; 2482 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2483 } 2484 2485 rtl8188ee_bt_var_init(hw); 2486 } 2487 2488 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw) 2489 { 2490 struct rtl_priv *rtlpriv = rtl_priv(hw); 2491 2492 /* 0:Low, 1:High, 2:From Efuse. */ 2493 rtlpriv->btcoexist.reg_bt_iso = 2; 2494 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2495 rtlpriv->btcoexist.reg_bt_sco = 3; 2496 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2497 rtlpriv->btcoexist.reg_bt_sco = 0; 2498 } 2499 2500 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw) 2501 { 2502 struct rtl_priv *rtlpriv = rtl_priv(hw); 2503 struct rtl_phy *rtlphy = &rtlpriv->phy; 2504 u8 u1_tmp; 2505 2506 if (rtlpriv->btcoexist.bt_coexistence && 2507 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) || 2508 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) { 2509 if (rtlpriv->btcoexist.bt_ant_isolation) 2510 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 2511 2512 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & 2513 BIT_OFFSET_LEN_MASK_32(0, 1); 2514 u1_tmp = u1_tmp | 2515 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ? 2516 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 2517 ((rtlpriv->btcoexist.bt_service == BT_SCO) ? 2518 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); 2519 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); 2520 2521 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); 2522 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); 2523 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); 2524 2525 /* Config to 1T1R. */ 2526 if (rtlphy->rf_type == RF_1T1R) { 2527 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); 2528 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2529 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); 2530 2531 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); 2532 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2533 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); 2534 } 2535 } 2536 } 2537 2538 void rtl88ee_suspend(struct ieee80211_hw *hw) 2539 { 2540 } 2541 2542 void rtl88ee_resume(struct ieee80211_hw *hw) 2543 { 2544 } 2545