xref: /linux/drivers/net/wireless/realtek/rtlwifi/pci.c (revision 79ac11393328fb1717d17c12e3c0eef0e9fa0647)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13 
14 MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger	<Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19 
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 	INTEL_VENDOR_ID,
22 	ATI_VENDOR_ID,
23 	AMD_VENDOR_ID,
24 	SIS_VENDOR_ID
25 };
26 
27 static const u8 ac_to_hwq[] = {
28 	VO_QUEUE,
29 	VI_QUEUE,
30 	BE_QUEUE,
31 	BK_QUEUE
32 };
33 
34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 	__le16 fc = rtl_get_fc(skb);
38 	u8 queue_index = skb_get_queue_mapping(skb);
39 	struct ieee80211_hdr *hdr;
40 
41 	if (unlikely(ieee80211_is_beacon(fc)))
42 		return BEACON_QUEUE;
43 	if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 		return MGNT_QUEUE;
45 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 		if (ieee80211_is_nullfunc(fc))
47 			return HIGH_QUEUE;
48 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 		hdr = rtl_get_hdr(skb);
50 
51 		if (is_multicast_ether_addr(hdr->addr1) ||
52 		    is_broadcast_ether_addr(hdr->addr1))
53 			return HIGH_QUEUE;
54 	}
55 
56 	return ac_to_hwq[queue_index];
57 }
58 
59 /* Update PCI dependent default settings*/
60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 	struct rtl_priv *rtlpriv = rtl_priv(hw);
63 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 	u8 init_aspm;
68 
69 	ppsc->reg_rfps_level = 0;
70 	ppsc->support_aspm = false;
71 
72 	/*Update PCI ASPM setting */
73 	switch (rtlpci->const_pci_aspm) {
74 	case 0:
75 		/*No ASPM */
76 		break;
77 
78 	case 1:
79 		/*ASPM dynamically enabled/disable. */
80 		ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
81 		break;
82 
83 	case 2:
84 		/*ASPM with Clock Req dynamically enabled/disable. */
85 		ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
86 					 RT_RF_OFF_LEVL_CLK_REQ);
87 		break;
88 
89 	case 3:
90 		/* Always enable ASPM and Clock Req
91 		 * from initialization to halt.
92 		 */
93 		ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
94 		ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
95 					 RT_RF_OFF_LEVL_CLK_REQ);
96 		break;
97 
98 	case 4:
99 		/* Always enable ASPM without Clock Req
100 		 * from initialization to halt.
101 		 */
102 		ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
103 					  RT_RF_OFF_LEVL_CLK_REQ);
104 		ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
105 		break;
106 	}
107 
108 	ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
109 
110 	/*Update Radio OFF setting */
111 	switch (rtlpci->const_hwsw_rfoff_d3) {
112 	case 1:
113 		if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
114 			ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
115 		break;
116 
117 	case 2:
118 		if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
119 			ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
120 		ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
121 		break;
122 
123 	case 3:
124 		ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
125 		break;
126 	}
127 
128 	/*Set HW definition to determine if it supports ASPM. */
129 	switch (rtlpci->const_support_pciaspm) {
130 	case 0:
131 		/*Not support ASPM. */
132 		ppsc->support_aspm = false;
133 		break;
134 	case 1:
135 		/*Support ASPM. */
136 		ppsc->support_aspm = true;
137 		ppsc->support_backdoor = true;
138 		break;
139 	case 2:
140 		/*ASPM value set by chipset. */
141 		if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
142 			ppsc->support_aspm = true;
143 		break;
144 	default:
145 		pr_err("switch case %#x not processed\n",
146 		       rtlpci->const_support_pciaspm);
147 		break;
148 	}
149 
150 	/* toshiba aspm issue, toshiba will set aspm selfly
151 	 * so we should not set aspm in driver
152 	 */
153 	pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
154 	if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
155 	    init_aspm == 0x43)
156 		ppsc->support_aspm = false;
157 }
158 
159 static bool _rtl_pci_platform_switch_device_pci_aspm(
160 			struct ieee80211_hw *hw,
161 			u8 value)
162 {
163 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
164 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
165 
166 	if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
167 		value |= 0x40;
168 
169 	pci_write_config_byte(rtlpci->pdev, 0x80, value);
170 
171 	return false;
172 }
173 
174 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
175 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
176 {
177 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
178 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
179 
180 	pci_write_config_byte(rtlpci->pdev, 0x81, value);
181 
182 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
183 		udelay(100);
184 }
185 
186 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
187 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
188 {
189 	struct rtl_priv *rtlpriv = rtl_priv(hw);
190 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
191 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
192 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
193 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
194 	u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
195 	/*Retrieve original configuration settings. */
196 	u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
197 	u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
198 				pcibridge_linkctrlreg;
199 	u16 aspmlevel = 0;
200 	u8 tmp_u1b = 0;
201 
202 	if (!ppsc->support_aspm)
203 		return;
204 
205 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
206 		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
207 			"PCI(Bridge) UNKNOWN\n");
208 
209 		return;
210 	}
211 
212 	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
213 		RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
214 		_rtl_pci_switch_clk_req(hw, 0x0);
215 	}
216 
217 	/*for promising device will in L0 state after an I/O. */
218 	pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
219 
220 	/*Set corresponding value. */
221 	aspmlevel |= BIT(0) | BIT(1);
222 	linkctrl_reg &= ~aspmlevel;
223 	pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
224 
225 	_rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
226 	udelay(50);
227 
228 	/*4 Disable Pci Bridge ASPM */
229 	pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
230 			      pcibridge_linkctrlreg);
231 
232 	udelay(50);
233 }
234 
235 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
236  *power saving We should follow the sequence to enable
237  *RTL8192SE first then enable Pci Bridge ASPM
238  *or the system will show bluescreen.
239  */
240 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
241 {
242 	struct rtl_priv *rtlpriv = rtl_priv(hw);
243 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
244 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
245 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
246 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
247 	u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
248 	u16 aspmlevel;
249 	u8 u_pcibridge_aspmsetting;
250 	u8 u_device_aspmsetting;
251 
252 	if (!ppsc->support_aspm)
253 		return;
254 
255 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
256 		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
257 			"PCI(Bridge) UNKNOWN\n");
258 		return;
259 	}
260 
261 	/*4 Enable Pci Bridge ASPM */
262 
263 	u_pcibridge_aspmsetting =
264 	    pcipriv->ndis_adapter.pcibridge_linkctrlreg |
265 	    rtlpci->const_hostpci_aspm_setting;
266 
267 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
268 		u_pcibridge_aspmsetting &= ~BIT(0);
269 
270 	pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
271 			      u_pcibridge_aspmsetting);
272 
273 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
274 		"PlatformEnableASPM(): Write reg[%x] = %x\n",
275 		(pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
276 		u_pcibridge_aspmsetting);
277 
278 	udelay(50);
279 
280 	/*Get ASPM level (with/without Clock Req) */
281 	aspmlevel = rtlpci->const_devicepci_aspm_setting;
282 	u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
283 
284 	/*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
285 	/*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
286 
287 	u_device_aspmsetting |= aspmlevel;
288 
289 	_rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
290 
291 	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
292 		_rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
293 					     RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
294 		RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
295 	}
296 	udelay(100);
297 }
298 
299 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
300 {
301 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
302 
303 	bool status = false;
304 	u8 offset_e0;
305 	unsigned int offset_e4;
306 
307 	pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
308 
309 	pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
310 
311 	if (offset_e0 == 0xA0) {
312 		pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
313 		if (offset_e4 & BIT(23))
314 			status = true;
315 	}
316 
317 	return status;
318 }
319 
320 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
321 				     struct rtl_priv **buddy_priv)
322 {
323 	struct rtl_priv *rtlpriv = rtl_priv(hw);
324 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
325 	struct rtl_priv *tpriv = NULL, *iter;
326 	struct rtl_pci_priv *tpcipriv = NULL;
327 
328 	if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
329 		list_for_each_entry(iter, &rtlpriv->glb_var->glb_priv_list,
330 				    list) {
331 			tpcipriv = (struct rtl_pci_priv *)iter->priv;
332 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
333 				"pcipriv->ndis_adapter.funcnumber %x\n",
334 				pcipriv->ndis_adapter.funcnumber);
335 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
336 				"tpcipriv->ndis_adapter.funcnumber %x\n",
337 				tpcipriv->ndis_adapter.funcnumber);
338 
339 			if (pcipriv->ndis_adapter.busnumber ==
340 			    tpcipriv->ndis_adapter.busnumber &&
341 			    pcipriv->ndis_adapter.devnumber ==
342 			    tpcipriv->ndis_adapter.devnumber &&
343 			    pcipriv->ndis_adapter.funcnumber !=
344 			    tpcipriv->ndis_adapter.funcnumber) {
345 				tpriv = iter;
346 				break;
347 			}
348 		}
349 	}
350 
351 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
352 		"find_buddy_priv %d\n", tpriv != NULL);
353 
354 	if (tpriv)
355 		*buddy_priv = tpriv;
356 
357 	return tpriv != NULL;
358 }
359 
360 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
361 {
362 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
363 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
364 	u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
365 	u8 linkctrl_reg;
366 	u8 num4bbytes;
367 
368 	num4bbytes = (capabilityoffset + 0x10) / 4;
369 
370 	/*Read  Link Control Register */
371 	pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
372 
373 	pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
374 }
375 
376 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
377 					struct ieee80211_hw *hw)
378 {
379 	struct rtl_priv *rtlpriv = rtl_priv(hw);
380 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
381 
382 	u8 tmp;
383 	u16 linkctrl_reg;
384 
385 	/*Link Control Register */
386 	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
387 	pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
388 
389 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
390 		pcipriv->ndis_adapter.linkctrl_reg);
391 
392 	pci_read_config_byte(pdev, 0x98, &tmp);
393 	tmp |= BIT(4);
394 	pci_write_config_byte(pdev, 0x98, tmp);
395 
396 	tmp = 0x17;
397 	pci_write_config_byte(pdev, 0x70f, tmp);
398 }
399 
400 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
401 {
402 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
403 
404 	_rtl_pci_update_default_setting(hw);
405 
406 	if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
407 		/*Always enable ASPM & Clock Req. */
408 		rtl_pci_enable_aspm(hw);
409 		RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
410 	}
411 }
412 
413 static void _rtl_pci_io_handler_init(struct device *dev,
414 				     struct ieee80211_hw *hw)
415 {
416 	struct rtl_priv *rtlpriv = rtl_priv(hw);
417 
418 	rtlpriv->io.dev = dev;
419 
420 	rtlpriv->io.write8_async = pci_write8_async;
421 	rtlpriv->io.write16_async = pci_write16_async;
422 	rtlpriv->io.write32_async = pci_write32_async;
423 
424 	rtlpriv->io.read8_sync = pci_read8_sync;
425 	rtlpriv->io.read16_sync = pci_read16_sync;
426 	rtlpriv->io.read32_sync = pci_read32_sync;
427 }
428 
429 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
430 				       struct sk_buff *skb,
431 				       struct rtl_tcb_desc *tcb_desc, u8 tid)
432 {
433 	struct rtl_priv *rtlpriv = rtl_priv(hw);
434 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
435 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
436 	struct sk_buff *next_skb;
437 	u8 additionlen = FCS_LEN;
438 
439 	/* here open is 4, wep/tkip is 8, aes is 12*/
440 	if (info->control.hw_key)
441 		additionlen += info->control.hw_key->icv_len;
442 
443 	/* The most skb num is 6 */
444 	tcb_desc->empkt_num = 0;
445 	spin_lock_bh(&rtlpriv->locks.waitq_lock);
446 	skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
447 		struct ieee80211_tx_info *next_info;
448 
449 		next_info = IEEE80211_SKB_CB(next_skb);
450 		if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
451 			tcb_desc->empkt_len[tcb_desc->empkt_num] =
452 				next_skb->len + additionlen;
453 			tcb_desc->empkt_num++;
454 		} else {
455 			break;
456 		}
457 
458 		if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
459 				      next_skb))
460 			break;
461 
462 		if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
463 			break;
464 	}
465 	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
466 
467 	return true;
468 }
469 
470 /* just for early mode now */
471 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
472 {
473 	struct rtl_priv *rtlpriv = rtl_priv(hw);
474 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
475 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
476 	struct sk_buff *skb = NULL;
477 	struct ieee80211_tx_info *info = NULL;
478 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
479 	int tid;
480 
481 	if (!rtlpriv->rtlhal.earlymode_enable)
482 		return;
483 
484 	/* we just use em for BE/BK/VI/VO */
485 	for (tid = 7; tid >= 0; tid--) {
486 		u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
487 		struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
488 
489 		while (!mac->act_scanning &&
490 		       rtlpriv->psc.rfpwr_state == ERFON) {
491 			struct rtl_tcb_desc tcb_desc;
492 
493 			memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
494 
495 			spin_lock(&rtlpriv->locks.waitq_lock);
496 			if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
497 			    (ring->entries - skb_queue_len(&ring->queue) >
498 			     rtlhal->max_earlymode_num)) {
499 				skb = skb_dequeue(&mac->skb_waitq[tid]);
500 			} else {
501 				spin_unlock(&rtlpriv->locks.waitq_lock);
502 				break;
503 			}
504 			spin_unlock(&rtlpriv->locks.waitq_lock);
505 
506 			/* Some macaddr can't do early mode. like
507 			 * multicast/broadcast/no_qos data
508 			 */
509 			info = IEEE80211_SKB_CB(skb);
510 			if (info->flags & IEEE80211_TX_CTL_AMPDU)
511 				_rtl_update_earlymode_info(hw, skb,
512 							   &tcb_desc, tid);
513 
514 			rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
515 		}
516 	}
517 }
518 
519 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
520 {
521 	struct rtl_priv *rtlpriv = rtl_priv(hw);
522 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
523 
524 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
525 
526 	while (skb_queue_len(&ring->queue)) {
527 		struct sk_buff *skb;
528 		struct ieee80211_tx_info *info;
529 		__le16 fc;
530 		u8 tid;
531 		u8 *entry;
532 
533 		if (rtlpriv->use_new_trx_flow)
534 			entry = (u8 *)(&ring->buffer_desc[ring->idx]);
535 		else
536 			entry = (u8 *)(&ring->desc[ring->idx]);
537 
538 		if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
539 			return;
540 		ring->idx = (ring->idx + 1) % ring->entries;
541 
542 		skb = __skb_dequeue(&ring->queue);
543 		dma_unmap_single(&rtlpci->pdev->dev,
544 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
545 						true, HW_DESC_TXBUFF_ADDR),
546 				 skb->len, DMA_TO_DEVICE);
547 
548 		/* remove early mode header */
549 		if (rtlpriv->rtlhal.earlymode_enable)
550 			skb_pull(skb, EM_HDR_LEN);
551 
552 		rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
553 			"new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
554 			ring->idx,
555 			skb_queue_len(&ring->queue),
556 			*(u16 *)(skb->data + 22));
557 
558 		if (prio == TXCMD_QUEUE) {
559 			dev_kfree_skb(skb);
560 			goto tx_status_ok;
561 		}
562 
563 		/* for sw LPS, just after NULL skb send out, we can
564 		 * sure AP knows we are sleeping, we should not let
565 		 * rf sleep
566 		 */
567 		fc = rtl_get_fc(skb);
568 		if (ieee80211_is_nullfunc(fc)) {
569 			if (ieee80211_has_pm(fc)) {
570 				rtlpriv->mac80211.offchan_delay = true;
571 				rtlpriv->psc.state_inap = true;
572 			} else {
573 				rtlpriv->psc.state_inap = false;
574 			}
575 		}
576 		if (ieee80211_is_action(fc)) {
577 			struct ieee80211_mgmt *action_frame =
578 				(struct ieee80211_mgmt *)skb->data;
579 			if (action_frame->u.action.u.ht_smps.action ==
580 			    WLAN_HT_ACTION_SMPS) {
581 				dev_kfree_skb(skb);
582 				goto tx_status_ok;
583 			}
584 		}
585 
586 		/* update tid tx pkt num */
587 		tid = rtl_get_tid(skb);
588 		if (tid <= 7)
589 			rtlpriv->link_info.tidtx_inperiod[tid]++;
590 
591 		info = IEEE80211_SKB_CB(skb);
592 
593 		if (likely(!ieee80211_is_nullfunc(fc))) {
594 			ieee80211_tx_info_clear_status(info);
595 			info->flags |= IEEE80211_TX_STAT_ACK;
596 			/*info->status.rates[0].count = 1; */
597 			ieee80211_tx_status_irqsafe(hw, skb);
598 		} else {
599 			rtl_tx_ackqueue(hw, skb);
600 		}
601 
602 		if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
603 			rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
604 				"more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
605 				prio, ring->idx,
606 				skb_queue_len(&ring->queue));
607 
608 			ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
609 		}
610 tx_status_ok:
611 		skb = NULL;
612 	}
613 
614 	if (((rtlpriv->link_info.num_rx_inperiod +
615 	      rtlpriv->link_info.num_tx_inperiod) > 8) ||
616 	      rtlpriv->link_info.num_rx_inperiod > 2)
617 		rtl_lps_leave(hw, false);
618 }
619 
620 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
621 				    struct sk_buff *new_skb, u8 *entry,
622 				    int rxring_idx, int desc_idx)
623 {
624 	struct rtl_priv *rtlpriv = rtl_priv(hw);
625 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
626 	u32 bufferaddress;
627 	u8 tmp_one = 1;
628 	struct sk_buff *skb;
629 
630 	if (likely(new_skb)) {
631 		skb = new_skb;
632 		goto remap;
633 	}
634 	skb = dev_alloc_skb(rtlpci->rxbuffersize);
635 	if (!skb)
636 		return 0;
637 
638 remap:
639 	/* just set skb->cb to mapping addr for pci_unmap_single use */
640 	*((dma_addr_t *)skb->cb) =
641 		dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
642 			       rtlpci->rxbuffersize, DMA_FROM_DEVICE);
643 	bufferaddress = *((dma_addr_t *)skb->cb);
644 	if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
645 		return 0;
646 	rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
647 	if (rtlpriv->use_new_trx_flow) {
648 		/* skb->cb may be 64 bit address */
649 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
650 					    HW_DESC_RX_PREPARE,
651 					    (u8 *)(dma_addr_t *)skb->cb);
652 	} else {
653 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
654 					    HW_DESC_RXBUFF_ADDR,
655 					    (u8 *)&bufferaddress);
656 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
657 					    HW_DESC_RXPKT_LEN,
658 					    (u8 *)&rtlpci->rxbuffersize);
659 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
660 					    HW_DESC_RXOWN,
661 					    (u8 *)&tmp_one);
662 	}
663 	return 1;
664 }
665 
666 /* inorder to receive 8K AMSDU we have set skb to
667  * 9100bytes in init rx ring, but if this packet is
668  * not a AMSDU, this large packet will be sent to
669  * TCP/IP directly, this cause big packet ping fail
670  * like: "ping -s 65507", so here we will realloc skb
671  * based on the true size of packet, Mac80211
672  * Probably will do it better, but does not yet.
673  *
674  * Some platform will fail when alloc skb sometimes.
675  * in this condition, we will send the old skb to
676  * mac80211 directly, this will not cause any other
677  * issues, but only this packet will be lost by TCP/IP
678  */
679 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
680 				    struct sk_buff *skb,
681 				    struct ieee80211_rx_status rx_status)
682 {
683 	if (unlikely(!rtl_action_proc(hw, skb, false))) {
684 		dev_kfree_skb_any(skb);
685 	} else {
686 		struct sk_buff *uskb = NULL;
687 
688 		uskb = dev_alloc_skb(skb->len + 128);
689 		if (likely(uskb)) {
690 			memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
691 			       sizeof(rx_status));
692 			skb_put_data(uskb, skb->data, skb->len);
693 			dev_kfree_skb_any(skb);
694 			ieee80211_rx_irqsafe(hw, uskb);
695 		} else {
696 			ieee80211_rx_irqsafe(hw, skb);
697 		}
698 	}
699 }
700 
701 /*hsisr interrupt handler*/
702 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
703 {
704 	struct rtl_priv *rtlpriv = rtl_priv(hw);
705 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
706 
707 	rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
708 		       rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
709 		       rtlpci->sys_irq_mask);
710 }
711 
712 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
713 {
714 	struct rtl_priv *rtlpriv = rtl_priv(hw);
715 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
716 	int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
717 	struct ieee80211_rx_status rx_status = { 0 };
718 	unsigned int count = rtlpci->rxringcount;
719 	u8 own;
720 	u8 tmp_one;
721 	bool unicast = false;
722 	u8 hw_queue = 0;
723 	unsigned int rx_remained_cnt = 0;
724 	struct rtl_stats stats = {
725 		.signal = 0,
726 		.rate = 0,
727 	};
728 
729 	/*RX NORMAL PKT */
730 	while (count--) {
731 		struct ieee80211_hdr *hdr;
732 		__le16 fc;
733 		u16 len;
734 		/*rx buffer descriptor */
735 		struct rtl_rx_buffer_desc *buffer_desc = NULL;
736 		/*if use new trx flow, it means wifi info */
737 		struct rtl_rx_desc *pdesc = NULL;
738 		/*rx pkt */
739 		struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
740 				      rtlpci->rx_ring[rxring_idx].idx];
741 		struct sk_buff *new_skb;
742 
743 		if (rtlpriv->use_new_trx_flow) {
744 			if (rx_remained_cnt == 0)
745 				rx_remained_cnt =
746 				rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
747 								      hw_queue);
748 			if (rx_remained_cnt == 0)
749 				return;
750 			buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
751 				rtlpci->rx_ring[rxring_idx].idx];
752 			pdesc = (struct rtl_rx_desc *)skb->data;
753 		} else {	/* rx descriptor */
754 			pdesc = &rtlpci->rx_ring[rxring_idx].desc[
755 				rtlpci->rx_ring[rxring_idx].idx];
756 
757 			own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
758 							      false,
759 							      HW_DESC_OWN);
760 			if (own) /* wait data to be filled by hardware */
761 				return;
762 		}
763 
764 		/* Reaching this point means: data is filled already
765 		 * AAAAAAttention !!!
766 		 * We can NOT access 'skb' before 'pci_unmap_single'
767 		 */
768 		dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
769 				 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
770 
771 		/* get a new skb - if fail, old one will be reused */
772 		new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
773 		if (unlikely(!new_skb))
774 			goto no_new;
775 		memset(&rx_status, 0, sizeof(rx_status));
776 		rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
777 						 &rx_status, (u8 *)pdesc, skb);
778 
779 		if (rtlpriv->use_new_trx_flow)
780 			rtlpriv->cfg->ops->rx_check_dma_ok(hw,
781 							   (u8 *)buffer_desc,
782 							   hw_queue);
783 
784 		len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
785 						  HW_DESC_RXPKT_LEN);
786 
787 		if (skb->end - skb->tail > len) {
788 			skb_put(skb, len);
789 			if (rtlpriv->use_new_trx_flow)
790 				skb_reserve(skb, stats.rx_drvinfo_size +
791 					    stats.rx_bufshift + 24);
792 			else
793 				skb_reserve(skb, stats.rx_drvinfo_size +
794 					    stats.rx_bufshift);
795 		} else {
796 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
797 				"skb->end - skb->tail = %d, len is %d\n",
798 				skb->end - skb->tail, len);
799 			dev_kfree_skb_any(skb);
800 			goto new_trx_end;
801 		}
802 		/* handle command packet here */
803 		if (stats.packet_report_type == C2H_PACKET) {
804 			rtl_c2hcmd_enqueue(hw, skb);
805 			goto new_trx_end;
806 		}
807 
808 		/* NOTICE This can not be use for mac80211,
809 		 * this is done in mac80211 code,
810 		 * if done here sec DHCP will fail
811 		 * skb_trim(skb, skb->len - 4);
812 		 */
813 
814 		hdr = rtl_get_hdr(skb);
815 		fc = rtl_get_fc(skb);
816 
817 		if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
818 			memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
819 			       sizeof(rx_status));
820 
821 			if (is_broadcast_ether_addr(hdr->addr1)) {
822 				;/*TODO*/
823 			} else if (is_multicast_ether_addr(hdr->addr1)) {
824 				;/*TODO*/
825 			} else {
826 				unicast = true;
827 				rtlpriv->stats.rxbytesunicast += skb->len;
828 			}
829 			rtl_is_special_data(hw, skb, false, true);
830 
831 			if (ieee80211_is_data(fc)) {
832 				rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
833 				if (unicast)
834 					rtlpriv->link_info.num_rx_inperiod++;
835 			}
836 
837 			rtl_collect_scan_list(hw, skb);
838 
839 			/* static bcn for roaming */
840 			rtl_beacon_statistic(hw, skb);
841 			rtl_p2p_info(hw, (void *)skb->data, skb->len);
842 			/* for sw lps */
843 			rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
844 			rtl_recognize_peer(hw, (void *)skb->data, skb->len);
845 			if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
846 			    rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
847 			    (ieee80211_is_beacon(fc) ||
848 			     ieee80211_is_probe_resp(fc))) {
849 				dev_kfree_skb_any(skb);
850 			} else {
851 				_rtl_pci_rx_to_mac80211(hw, skb, rx_status);
852 			}
853 		} else {
854 			/* drop packets with errors or those too short */
855 			dev_kfree_skb_any(skb);
856 		}
857 new_trx_end:
858 		if (rtlpriv->use_new_trx_flow) {
859 			rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
860 			rtlpci->rx_ring[hw_queue].next_rx_rp %=
861 					RTL_PCI_MAX_RX_COUNT;
862 
863 			rx_remained_cnt--;
864 			rtl_write_word(rtlpriv, 0x3B4,
865 				       rtlpci->rx_ring[hw_queue].next_rx_rp);
866 		}
867 		if (((rtlpriv->link_info.num_rx_inperiod +
868 		      rtlpriv->link_info.num_tx_inperiod) > 8) ||
869 		      rtlpriv->link_info.num_rx_inperiod > 2)
870 			rtl_lps_leave(hw, false);
871 		skb = new_skb;
872 no_new:
873 		if (rtlpriv->use_new_trx_flow) {
874 			_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
875 						 rxring_idx,
876 						 rtlpci->rx_ring[rxring_idx].idx);
877 		} else {
878 			_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
879 						 rxring_idx,
880 						 rtlpci->rx_ring[rxring_idx].idx);
881 			if (rtlpci->rx_ring[rxring_idx].idx ==
882 			    rtlpci->rxringcount - 1)
883 				rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
884 							    false,
885 							    HW_DESC_RXERO,
886 							    (u8 *)&tmp_one);
887 		}
888 		rtlpci->rx_ring[rxring_idx].idx =
889 				(rtlpci->rx_ring[rxring_idx].idx + 1) %
890 				rtlpci->rxringcount;
891 	}
892 }
893 
894 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
895 {
896 	struct ieee80211_hw *hw = dev_id;
897 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
898 	struct rtl_priv *rtlpriv = rtl_priv(hw);
899 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
900 	unsigned long flags;
901 	struct rtl_int intvec = {0};
902 
903 	irqreturn_t ret = IRQ_HANDLED;
904 
905 	if (rtlpci->irq_enabled == 0)
906 		return ret;
907 
908 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
909 	rtlpriv->cfg->ops->disable_interrupt(hw);
910 
911 	/*read ISR: 4/8bytes */
912 	rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
913 
914 	/*Shared IRQ or HW disappeared */
915 	if (!intvec.inta || intvec.inta == 0xffff)
916 		goto done;
917 
918 	/*<1> beacon related */
919 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
920 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
921 			"beacon ok interrupt!\n");
922 
923 	if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
924 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
925 			"beacon err interrupt!\n");
926 
927 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
928 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
929 
930 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
931 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
932 			"prepare beacon for interrupt!\n");
933 		tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
934 	}
935 
936 	/*<2> Tx related */
937 	if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
938 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
939 
940 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
941 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
942 			"Manage ok interrupt!\n");
943 		_rtl_pci_tx_isr(hw, MGNT_QUEUE);
944 	}
945 
946 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
947 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
948 			"HIGH_QUEUE ok interrupt!\n");
949 		_rtl_pci_tx_isr(hw, HIGH_QUEUE);
950 	}
951 
952 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
953 		rtlpriv->link_info.num_tx_inperiod++;
954 
955 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
956 			"BK Tx OK interrupt!\n");
957 		_rtl_pci_tx_isr(hw, BK_QUEUE);
958 	}
959 
960 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
961 		rtlpriv->link_info.num_tx_inperiod++;
962 
963 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
964 			"BE TX OK interrupt!\n");
965 		_rtl_pci_tx_isr(hw, BE_QUEUE);
966 	}
967 
968 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
969 		rtlpriv->link_info.num_tx_inperiod++;
970 
971 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
972 			"VI TX OK interrupt!\n");
973 		_rtl_pci_tx_isr(hw, VI_QUEUE);
974 	}
975 
976 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
977 		rtlpriv->link_info.num_tx_inperiod++;
978 
979 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
980 			"Vo TX OK interrupt!\n");
981 		_rtl_pci_tx_isr(hw, VO_QUEUE);
982 	}
983 
984 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
985 		if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
986 			rtlpriv->link_info.num_tx_inperiod++;
987 
988 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
989 				"H2C TX OK interrupt!\n");
990 			_rtl_pci_tx_isr(hw, H2C_QUEUE);
991 		}
992 	}
993 
994 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
995 		if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
996 			rtlpriv->link_info.num_tx_inperiod++;
997 
998 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
999 				"CMD TX OK interrupt!\n");
1000 			_rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1001 		}
1002 	}
1003 
1004 	/*<3> Rx related */
1005 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1006 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1007 		_rtl_pci_rx_interrupt(hw);
1008 	}
1009 
1010 	if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1011 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1012 			"rx descriptor unavailable!\n");
1013 		_rtl_pci_rx_interrupt(hw);
1014 	}
1015 
1016 	if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1017 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1018 		_rtl_pci_rx_interrupt(hw);
1019 	}
1020 
1021 	/*<4> fw related*/
1022 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1023 		if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1024 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1025 				"firmware interrupt!\n");
1026 			queue_delayed_work(rtlpriv->works.rtl_wq,
1027 					   &rtlpriv->works.fwevt_wq, 0);
1028 		}
1029 	}
1030 
1031 	/*<5> hsisr related*/
1032 	/* Only 8188EE & 8723BE Supported.
1033 	 * If Other ICs Come in, System will corrupt,
1034 	 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1035 	 * are not initialized
1036 	 */
1037 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1038 	    rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1039 		if (unlikely(intvec.inta &
1040 		    rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1041 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1042 				"hsisr interrupt!\n");
1043 			_rtl_pci_hs_interrupt(hw);
1044 		}
1045 	}
1046 
1047 	if (rtlpriv->rtlhal.earlymode_enable)
1048 		tasklet_schedule(&rtlpriv->works.irq_tasklet);
1049 
1050 done:
1051 	rtlpriv->cfg->ops->enable_interrupt(hw);
1052 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1053 	return ret;
1054 }
1055 
1056 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
1057 {
1058 	struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1059 	struct ieee80211_hw *hw = rtlpriv->hw;
1060 	_rtl_pci_tx_chk_waitq(hw);
1061 }
1062 
1063 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
1064 {
1065 	struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1066 						works.irq_prepare_bcn_tasklet);
1067 	struct ieee80211_hw *hw = rtlpriv->hw;
1068 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1069 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1070 	struct rtl8192_tx_ring *ring = NULL;
1071 	struct ieee80211_hdr *hdr = NULL;
1072 	struct ieee80211_tx_info *info = NULL;
1073 	struct sk_buff *pskb = NULL;
1074 	struct rtl_tx_desc *pdesc = NULL;
1075 	struct rtl_tcb_desc tcb_desc;
1076 	/*This is for new trx flow*/
1077 	struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1078 	u8 temp_one = 1;
1079 	u8 *entry;
1080 
1081 	memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1082 	ring = &rtlpci->tx_ring[BEACON_QUEUE];
1083 	pskb = __skb_dequeue(&ring->queue);
1084 	if (rtlpriv->use_new_trx_flow)
1085 		entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1086 	else
1087 		entry = (u8 *)(&ring->desc[ring->idx]);
1088 	if (pskb) {
1089 		dma_unmap_single(&rtlpci->pdev->dev,
1090 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1091 						true, HW_DESC_TXBUFF_ADDR),
1092 				 pskb->len, DMA_TO_DEVICE);
1093 		kfree_skb(pskb);
1094 	}
1095 
1096 	/*NB: the beacon data buffer must be 32-bit aligned. */
1097 	pskb = ieee80211_beacon_get(hw, mac->vif, 0);
1098 	if (!pskb)
1099 		return;
1100 	hdr = rtl_get_hdr(pskb);
1101 	info = IEEE80211_SKB_CB(pskb);
1102 	pdesc = &ring->desc[0];
1103 	if (rtlpriv->use_new_trx_flow)
1104 		pbuffer_desc = &ring->buffer_desc[0];
1105 
1106 	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1107 					(u8 *)pbuffer_desc, info, NULL, pskb,
1108 					BEACON_QUEUE, &tcb_desc);
1109 
1110 	__skb_queue_tail(&ring->queue, pskb);
1111 
1112 	if (rtlpriv->use_new_trx_flow) {
1113 		temp_one = 4;
1114 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1115 					    HW_DESC_OWN, (u8 *)&temp_one);
1116 	} else {
1117 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1118 					    &temp_one);
1119 	}
1120 }
1121 
1122 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1123 {
1124 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1125 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1126 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1127 	u8 i;
1128 	u16 desc_num;
1129 
1130 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1131 		desc_num = TX_DESC_NUM_92E;
1132 	else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1133 		desc_num = TX_DESC_NUM_8822B;
1134 	else
1135 		desc_num = RT_TXDESC_NUM;
1136 
1137 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1138 		rtlpci->txringcount[i] = desc_num;
1139 
1140 	/*we just alloc 2 desc for beacon queue,
1141 	 *because we just need first desc in hw beacon.
1142 	 */
1143 	rtlpci->txringcount[BEACON_QUEUE] = 2;
1144 
1145 	/*BE queue need more descriptor for performance
1146 	 *consideration or, No more tx desc will happen,
1147 	 *and may cause mac80211 mem leakage.
1148 	 */
1149 	if (!rtl_priv(hw)->use_new_trx_flow)
1150 		rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1151 
1152 	rtlpci->rxbuffersize = 9100;	/*2048/1024; */
1153 	rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;	/*64; */
1154 }
1155 
1156 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1157 				 struct pci_dev *pdev)
1158 {
1159 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1160 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1161 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1162 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1163 
1164 	rtlpci->up_first_time = true;
1165 	rtlpci->being_init_adapter = false;
1166 
1167 	rtlhal->hw = hw;
1168 	rtlpci->pdev = pdev;
1169 
1170 	/*Tx/Rx related var */
1171 	_rtl_pci_init_trx_var(hw);
1172 
1173 	/*IBSS*/
1174 	mac->beacon_interval = 100;
1175 
1176 	/*AMPDU*/
1177 	mac->min_space_cfg = 0;
1178 	mac->max_mss_density = 0;
1179 	/*set sane AMPDU defaults */
1180 	mac->current_ampdu_density = 7;
1181 	mac->current_ampdu_factor = 3;
1182 
1183 	/*Retry Limit*/
1184 	mac->retry_short = 7;
1185 	mac->retry_long = 7;
1186 
1187 	/*QOS*/
1188 	rtlpci->acm_method = EACMWAY2_SW;
1189 
1190 	/*task */
1191 	tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1192 	tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1193 		     _rtl_pci_prepare_bcn_tasklet);
1194 	INIT_WORK(&rtlpriv->works.lps_change_work,
1195 		  rtl_lps_change_work_callback);
1196 }
1197 
1198 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1199 				 unsigned int prio, unsigned int entries)
1200 {
1201 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1202 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1203 	struct rtl_tx_buffer_desc *buffer_desc;
1204 	struct rtl_tx_desc *desc;
1205 	dma_addr_t buffer_desc_dma, desc_dma;
1206 	u32 nextdescaddress;
1207 	int i;
1208 
1209 	/* alloc tx buffer desc for new trx flow*/
1210 	if (rtlpriv->use_new_trx_flow) {
1211 		buffer_desc =
1212 		   dma_alloc_coherent(&rtlpci->pdev->dev,
1213 				      sizeof(*buffer_desc) * entries,
1214 				      &buffer_desc_dma, GFP_KERNEL);
1215 
1216 		if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1217 			pr_err("Cannot allocate TX ring (prio = %d)\n",
1218 			       prio);
1219 			return -ENOMEM;
1220 		}
1221 
1222 		rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1223 		rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1224 
1225 		rtlpci->tx_ring[prio].cur_tx_rp = 0;
1226 		rtlpci->tx_ring[prio].cur_tx_wp = 0;
1227 	}
1228 
1229 	/* alloc dma for this ring */
1230 	desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1231 				  &desc_dma, GFP_KERNEL);
1232 
1233 	if (!desc || (unsigned long)desc & 0xFF) {
1234 		pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1235 		return -ENOMEM;
1236 	}
1237 
1238 	rtlpci->tx_ring[prio].desc = desc;
1239 	rtlpci->tx_ring[prio].dma = desc_dma;
1240 
1241 	rtlpci->tx_ring[prio].idx = 0;
1242 	rtlpci->tx_ring[prio].entries = entries;
1243 	skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1244 
1245 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1246 		prio, desc);
1247 
1248 	/* init every desc in this ring */
1249 	if (!rtlpriv->use_new_trx_flow) {
1250 		for (i = 0; i < entries; i++) {
1251 			nextdescaddress = (u32)desc_dma +
1252 					  ((i +	1) % entries) *
1253 					  sizeof(*desc);
1254 
1255 			rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1256 						    true,
1257 						    HW_DESC_TX_NEXTDESC_ADDR,
1258 						    (u8 *)&nextdescaddress);
1259 		}
1260 	}
1261 	return 0;
1262 }
1263 
1264 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1265 {
1266 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1267 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1268 	int i;
1269 
1270 	if (rtlpriv->use_new_trx_flow) {
1271 		struct rtl_rx_buffer_desc *entry = NULL;
1272 		/* alloc dma for this ring */
1273 		rtlpci->rx_ring[rxring_idx].buffer_desc =
1274 		    dma_alloc_coherent(&rtlpci->pdev->dev,
1275 				       sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1276 				       rtlpci->rxringcount,
1277 				       &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1278 		if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1279 		    (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1280 			pr_err("Cannot allocate RX ring\n");
1281 			return -ENOMEM;
1282 		}
1283 
1284 		/* init every desc in this ring */
1285 		rtlpci->rx_ring[rxring_idx].idx = 0;
1286 		for (i = 0; i < rtlpci->rxringcount; i++) {
1287 			entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1288 			if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1289 						      rxring_idx, i))
1290 				return -ENOMEM;
1291 		}
1292 	} else {
1293 		struct rtl_rx_desc *entry = NULL;
1294 		u8 tmp_one = 1;
1295 		/* alloc dma for this ring */
1296 		rtlpci->rx_ring[rxring_idx].desc =
1297 		    dma_alloc_coherent(&rtlpci->pdev->dev,
1298 				       sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1299 				       rtlpci->rxringcount,
1300 				       &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1301 		if (!rtlpci->rx_ring[rxring_idx].desc ||
1302 		    (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1303 			pr_err("Cannot allocate RX ring\n");
1304 			return -ENOMEM;
1305 		}
1306 
1307 		/* init every desc in this ring */
1308 		rtlpci->rx_ring[rxring_idx].idx = 0;
1309 
1310 		for (i = 0; i < rtlpci->rxringcount; i++) {
1311 			entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1312 			if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1313 						      rxring_idx, i))
1314 				return -ENOMEM;
1315 		}
1316 
1317 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1318 					    HW_DESC_RXERO, &tmp_one);
1319 	}
1320 	return 0;
1321 }
1322 
1323 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1324 				  unsigned int prio)
1325 {
1326 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1327 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1328 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1329 
1330 	/* free every desc in this ring */
1331 	while (skb_queue_len(&ring->queue)) {
1332 		u8 *entry;
1333 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
1334 
1335 		if (rtlpriv->use_new_trx_flow)
1336 			entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1337 		else
1338 			entry = (u8 *)(&ring->desc[ring->idx]);
1339 
1340 		dma_unmap_single(&rtlpci->pdev->dev,
1341 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1342 						true, HW_DESC_TXBUFF_ADDR),
1343 				 skb->len, DMA_TO_DEVICE);
1344 		kfree_skb(skb);
1345 		ring->idx = (ring->idx + 1) % ring->entries;
1346 	}
1347 
1348 	/* free dma of this ring */
1349 	dma_free_coherent(&rtlpci->pdev->dev,
1350 			  sizeof(*ring->desc) * ring->entries, ring->desc,
1351 			  ring->dma);
1352 	ring->desc = NULL;
1353 	if (rtlpriv->use_new_trx_flow) {
1354 		dma_free_coherent(&rtlpci->pdev->dev,
1355 				  sizeof(*ring->buffer_desc) * ring->entries,
1356 				  ring->buffer_desc, ring->buffer_desc_dma);
1357 		ring->buffer_desc = NULL;
1358 	}
1359 }
1360 
1361 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1362 {
1363 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1364 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1365 	int i;
1366 
1367 	/* free every desc in this ring */
1368 	for (i = 0; i < rtlpci->rxringcount; i++) {
1369 		struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1370 
1371 		if (!skb)
1372 			continue;
1373 		dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1374 				 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1375 		kfree_skb(skb);
1376 	}
1377 
1378 	/* free dma of this ring */
1379 	if (rtlpriv->use_new_trx_flow) {
1380 		dma_free_coherent(&rtlpci->pdev->dev,
1381 				  sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1382 				  rtlpci->rxringcount,
1383 				  rtlpci->rx_ring[rxring_idx].buffer_desc,
1384 				  rtlpci->rx_ring[rxring_idx].dma);
1385 		rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1386 	} else {
1387 		dma_free_coherent(&rtlpci->pdev->dev,
1388 				  sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1389 				  rtlpci->rxringcount,
1390 				  rtlpci->rx_ring[rxring_idx].desc,
1391 				  rtlpci->rx_ring[rxring_idx].dma);
1392 		rtlpci->rx_ring[rxring_idx].desc = NULL;
1393 	}
1394 }
1395 
1396 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1397 {
1398 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1399 	int ret;
1400 	int i, rxring_idx;
1401 
1402 	/* rxring_idx 0:RX_MPDU_QUEUE
1403 	 * rxring_idx 1:RX_CMD_QUEUE
1404 	 */
1405 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1406 		ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1407 		if (ret)
1408 			return ret;
1409 	}
1410 
1411 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1412 		ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1413 		if (ret)
1414 			goto err_free_rings;
1415 	}
1416 
1417 	return 0;
1418 
1419 err_free_rings:
1420 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1421 		_rtl_pci_free_rx_ring(hw, rxring_idx);
1422 
1423 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1424 		if (rtlpci->tx_ring[i].desc ||
1425 		    rtlpci->tx_ring[i].buffer_desc)
1426 			_rtl_pci_free_tx_ring(hw, i);
1427 
1428 	return 1;
1429 }
1430 
1431 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1432 {
1433 	u32 i, rxring_idx;
1434 
1435 	/*free rx rings */
1436 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1437 		_rtl_pci_free_rx_ring(hw, rxring_idx);
1438 
1439 	/*free tx rings */
1440 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1441 		_rtl_pci_free_tx_ring(hw, i);
1442 
1443 	return 0;
1444 }
1445 
1446 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1447 {
1448 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1449 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1450 	int i, rxring_idx;
1451 	unsigned long flags;
1452 	u8 tmp_one = 1;
1453 	u32 bufferaddress;
1454 	/* rxring_idx 0:RX_MPDU_QUEUE */
1455 	/* rxring_idx 1:RX_CMD_QUEUE */
1456 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1457 		/* force the rx_ring[RX_MPDU_QUEUE/
1458 		 * RX_CMD_QUEUE].idx to the first one
1459 		 *new trx flow, do nothing
1460 		 */
1461 		if (!rtlpriv->use_new_trx_flow &&
1462 		    rtlpci->rx_ring[rxring_idx].desc) {
1463 			struct rtl_rx_desc *entry = NULL;
1464 
1465 			rtlpci->rx_ring[rxring_idx].idx = 0;
1466 			for (i = 0; i < rtlpci->rxringcount; i++) {
1467 				entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1468 				bufferaddress =
1469 				  rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1470 				  false, HW_DESC_RXBUFF_ADDR);
1471 				memset((u8 *)entry, 0,
1472 				       sizeof(*rtlpci->rx_ring
1473 				       [rxring_idx].desc));/*clear one entry*/
1474 				if (rtlpriv->use_new_trx_flow) {
1475 					rtlpriv->cfg->ops->set_desc(hw,
1476 					    (u8 *)entry, false,
1477 					    HW_DESC_RX_PREPARE,
1478 					    (u8 *)&bufferaddress);
1479 				} else {
1480 					rtlpriv->cfg->ops->set_desc(hw,
1481 					    (u8 *)entry, false,
1482 					    HW_DESC_RXBUFF_ADDR,
1483 					    (u8 *)&bufferaddress);
1484 					rtlpriv->cfg->ops->set_desc(hw,
1485 					    (u8 *)entry, false,
1486 					    HW_DESC_RXPKT_LEN,
1487 					    (u8 *)&rtlpci->rxbuffersize);
1488 					rtlpriv->cfg->ops->set_desc(hw,
1489 					    (u8 *)entry, false,
1490 					    HW_DESC_RXOWN,
1491 					    (u8 *)&tmp_one);
1492 				}
1493 			}
1494 			rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1495 					    HW_DESC_RXERO, (u8 *)&tmp_one);
1496 		}
1497 		rtlpci->rx_ring[rxring_idx].idx = 0;
1498 	}
1499 
1500 	/*after reset, release previous pending packet,
1501 	 *and force the  tx idx to the first one
1502 	 */
1503 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1504 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1505 		if (rtlpci->tx_ring[i].desc ||
1506 		    rtlpci->tx_ring[i].buffer_desc) {
1507 			struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1508 
1509 			while (skb_queue_len(&ring->queue)) {
1510 				u8 *entry;
1511 				struct sk_buff *skb =
1512 					__skb_dequeue(&ring->queue);
1513 				if (rtlpriv->use_new_trx_flow)
1514 					entry = (u8 *)(&ring->buffer_desc
1515 								[ring->idx]);
1516 				else
1517 					entry = (u8 *)(&ring->desc[ring->idx]);
1518 
1519 				dma_unmap_single(&rtlpci->pdev->dev,
1520 						 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1521 								true, HW_DESC_TXBUFF_ADDR),
1522 						 skb->len, DMA_TO_DEVICE);
1523 				dev_kfree_skb_irq(skb);
1524 				ring->idx = (ring->idx + 1) % ring->entries;
1525 			}
1526 
1527 			if (rtlpriv->use_new_trx_flow) {
1528 				rtlpci->tx_ring[i].cur_tx_rp = 0;
1529 				rtlpci->tx_ring[i].cur_tx_wp = 0;
1530 			}
1531 
1532 			ring->idx = 0;
1533 			ring->entries = rtlpci->txringcount[i];
1534 		}
1535 	}
1536 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1537 
1538 	return 0;
1539 }
1540 
1541 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1542 					struct ieee80211_sta *sta,
1543 					struct sk_buff *skb)
1544 {
1545 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1546 	struct rtl_sta_info *sta_entry = NULL;
1547 	u8 tid = rtl_get_tid(skb);
1548 	__le16 fc = rtl_get_fc(skb);
1549 
1550 	if (!sta)
1551 		return false;
1552 	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1553 
1554 	if (!rtlpriv->rtlhal.earlymode_enable)
1555 		return false;
1556 	if (ieee80211_is_nullfunc(fc))
1557 		return false;
1558 	if (ieee80211_is_qos_nullfunc(fc))
1559 		return false;
1560 	if (ieee80211_is_pspoll(fc))
1561 		return false;
1562 	if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1563 		return false;
1564 	if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1565 		return false;
1566 	if (tid > 7)
1567 		return false;
1568 
1569 	/* maybe every tid should be checked */
1570 	if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1571 		return false;
1572 
1573 	spin_lock_bh(&rtlpriv->locks.waitq_lock);
1574 	skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1575 	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1576 
1577 	return true;
1578 }
1579 
1580 static int rtl_pci_tx(struct ieee80211_hw *hw,
1581 		      struct ieee80211_sta *sta,
1582 		      struct sk_buff *skb,
1583 		      struct rtl_tcb_desc *ptcb_desc)
1584 {
1585 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1586 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1587 	struct rtl8192_tx_ring *ring;
1588 	struct rtl_tx_desc *pdesc;
1589 	struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1590 	u16 idx;
1591 	u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1592 	unsigned long flags;
1593 	struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1594 	__le16 fc = rtl_get_fc(skb);
1595 	u8 *pda_addr = hdr->addr1;
1596 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1597 	u8 own;
1598 	u8 temp_one = 1;
1599 
1600 	if (ieee80211_is_mgmt(fc))
1601 		rtl_tx_mgmt_proc(hw, skb);
1602 
1603 	if (rtlpriv->psc.sw_ps_enabled) {
1604 		if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1605 		    !ieee80211_has_pm(fc))
1606 			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1607 	}
1608 
1609 	rtl_action_proc(hw, skb, true);
1610 
1611 	if (is_multicast_ether_addr(pda_addr))
1612 		rtlpriv->stats.txbytesmulticast += skb->len;
1613 	else if (is_broadcast_ether_addr(pda_addr))
1614 		rtlpriv->stats.txbytesbroadcast += skb->len;
1615 	else
1616 		rtlpriv->stats.txbytesunicast += skb->len;
1617 
1618 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1619 	ring = &rtlpci->tx_ring[hw_queue];
1620 	if (hw_queue != BEACON_QUEUE) {
1621 		if (rtlpriv->use_new_trx_flow)
1622 			idx = ring->cur_tx_wp;
1623 		else
1624 			idx = (ring->idx + skb_queue_len(&ring->queue)) %
1625 			      ring->entries;
1626 	} else {
1627 		idx = 0;
1628 	}
1629 
1630 	pdesc = &ring->desc[idx];
1631 	if (rtlpriv->use_new_trx_flow) {
1632 		ptx_bd_desc = &ring->buffer_desc[idx];
1633 	} else {
1634 		own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1635 				true, HW_DESC_OWN);
1636 
1637 		if (own == 1 && hw_queue != BEACON_QUEUE) {
1638 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1639 				"No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1640 				hw_queue, ring->idx, idx,
1641 				skb_queue_len(&ring->queue));
1642 
1643 			spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1644 					       flags);
1645 			return skb->len;
1646 		}
1647 	}
1648 
1649 	if (rtlpriv->cfg->ops->get_available_desc &&
1650 	    rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1651 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1652 			"get_available_desc fail\n");
1653 		spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1654 		return skb->len;
1655 	}
1656 
1657 	if (ieee80211_is_data(fc))
1658 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1659 
1660 	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1661 			(u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1662 
1663 	__skb_queue_tail(&ring->queue, skb);
1664 
1665 	if (rtlpriv->use_new_trx_flow) {
1666 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1667 					    HW_DESC_OWN, &hw_queue);
1668 	} else {
1669 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1670 					    HW_DESC_OWN, &temp_one);
1671 	}
1672 
1673 	if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1674 	    hw_queue != BEACON_QUEUE) {
1675 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1676 			"less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1677 			 hw_queue, ring->idx, idx,
1678 			 skb_queue_len(&ring->queue));
1679 
1680 		ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1681 	}
1682 
1683 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1684 
1685 	rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1686 
1687 	return 0;
1688 }
1689 
1690 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1691 {
1692 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1693 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1694 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1695 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1696 	u16 i = 0;
1697 	int queue_id;
1698 	struct rtl8192_tx_ring *ring;
1699 
1700 	if (mac->skip_scan)
1701 		return;
1702 
1703 	for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1704 		u32 queue_len;
1705 
1706 		if (((queues >> queue_id) & 0x1) == 0) {
1707 			queue_id--;
1708 			continue;
1709 		}
1710 		ring = &pcipriv->dev.tx_ring[queue_id];
1711 		queue_len = skb_queue_len(&ring->queue);
1712 		if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1713 		    queue_id == TXCMD_QUEUE) {
1714 			queue_id--;
1715 			continue;
1716 		} else {
1717 			msleep(20);
1718 			i++;
1719 		}
1720 
1721 		/* we just wait 1s for all queues */
1722 		if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1723 		    is_hal_stop(rtlhal) || i >= 200)
1724 			return;
1725 	}
1726 }
1727 
1728 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1729 {
1730 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1731 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1732 
1733 	_rtl_pci_deinit_trx_ring(hw);
1734 
1735 	synchronize_irq(rtlpci->pdev->irq);
1736 	tasklet_kill(&rtlpriv->works.irq_tasklet);
1737 	cancel_work_sync(&rtlpriv->works.lps_change_work);
1738 
1739 	destroy_workqueue(rtlpriv->works.rtl_wq);
1740 }
1741 
1742 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1743 {
1744 	int err;
1745 
1746 	_rtl_pci_init_struct(hw, pdev);
1747 
1748 	err = _rtl_pci_init_trx_ring(hw);
1749 	if (err) {
1750 		pr_err("tx ring initialization failed\n");
1751 		return err;
1752 	}
1753 
1754 	return 0;
1755 }
1756 
1757 static int rtl_pci_start(struct ieee80211_hw *hw)
1758 {
1759 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1760 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1761 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1762 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1763 	struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1764 	struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1765 
1766 	int err;
1767 
1768 	rtl_pci_reset_trx_ring(hw);
1769 
1770 	rtlpci->driver_is_goingto_unload = false;
1771 	if (rtlpriv->cfg->ops->get_btc_status &&
1772 	    rtlpriv->cfg->ops->get_btc_status()) {
1773 		rtlpriv->btcoexist.btc_info.ap_num = 36;
1774 		btc_ops->btc_init_variables(rtlpriv);
1775 		btc_ops->btc_init_hal_vars(rtlpriv);
1776 	} else if (btc_ops) {
1777 		btc_ops->btc_init_variables_wifi_only(rtlpriv);
1778 	}
1779 
1780 	err = rtlpriv->cfg->ops->hw_init(hw);
1781 	if (err) {
1782 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1783 			"Failed to config hardware!\n");
1784 		kfree(rtlpriv->btcoexist.btc_context);
1785 		kfree(rtlpriv->btcoexist.wifi_only_context);
1786 		return err;
1787 	}
1788 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1789 			&rtlmac->retry_long);
1790 
1791 	rtlpriv->cfg->ops->enable_interrupt(hw);
1792 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1793 
1794 	rtl_init_rx_config(hw);
1795 
1796 	/*should be after adapter start and interrupt enable. */
1797 	set_hal_start(rtlhal);
1798 
1799 	RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1800 
1801 	rtlpci->up_first_time = false;
1802 
1803 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1804 	return 0;
1805 }
1806 
1807 static void rtl_pci_stop(struct ieee80211_hw *hw)
1808 {
1809 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1810 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1811 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1812 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1813 	unsigned long flags;
1814 	u8 rf_timeout = 0;
1815 
1816 	if (rtlpriv->cfg->ops->get_btc_status())
1817 		rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1818 
1819 	if (rtlpriv->btcoexist.btc_ops)
1820 		rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1821 
1822 	/*should be before disable interrupt&adapter
1823 	 *and will do it immediately.
1824 	 */
1825 	set_hal_stop(rtlhal);
1826 
1827 	rtlpci->driver_is_goingto_unload = true;
1828 	rtlpriv->cfg->ops->disable_interrupt(hw);
1829 	cancel_work_sync(&rtlpriv->works.lps_change_work);
1830 
1831 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1832 	while (ppsc->rfchange_inprogress) {
1833 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1834 		if (rf_timeout > 100) {
1835 			spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1836 			break;
1837 		}
1838 		mdelay(1);
1839 		rf_timeout++;
1840 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1841 	}
1842 	ppsc->rfchange_inprogress = true;
1843 	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1844 
1845 	rtlpriv->cfg->ops->hw_disable(hw);
1846 	/* some things are not needed if firmware not available */
1847 	if (!rtlpriv->max_fw_size)
1848 		return;
1849 	rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1850 
1851 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1852 	ppsc->rfchange_inprogress = false;
1853 	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1854 
1855 	rtl_pci_enable_aspm(hw);
1856 }
1857 
1858 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1859 				  struct ieee80211_hw *hw)
1860 {
1861 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1862 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1863 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1864 	struct pci_dev *bridge_pdev = pdev->bus->self;
1865 	u16 venderid;
1866 	u16 deviceid;
1867 	u8 revisionid;
1868 	u16 irqline;
1869 	u8 tmp;
1870 
1871 	pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1872 	venderid = pdev->vendor;
1873 	deviceid = pdev->device;
1874 	pci_read_config_byte(pdev, 0x8, &revisionid);
1875 	pci_read_config_word(pdev, 0x3C, &irqline);
1876 
1877 	/* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1878 	 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1879 	 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1880 	 * the correct driver is r8192e_pci, thus this routine should
1881 	 * return false.
1882 	 */
1883 	if (deviceid == RTL_PCI_8192SE_DID &&
1884 	    revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1885 		return false;
1886 
1887 	if (deviceid == RTL_PCI_8192_DID ||
1888 	    deviceid == RTL_PCI_0044_DID ||
1889 	    deviceid == RTL_PCI_0047_DID ||
1890 	    deviceid == RTL_PCI_8192SE_DID ||
1891 	    deviceid == RTL_PCI_8174_DID ||
1892 	    deviceid == RTL_PCI_8173_DID ||
1893 	    deviceid == RTL_PCI_8172_DID ||
1894 	    deviceid == RTL_PCI_8171_DID) {
1895 		switch (revisionid) {
1896 		case RTL_PCI_REVISION_ID_8192PCIE:
1897 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1898 				"8192 PCI-E is found - vid/did=%x/%x\n",
1899 				venderid, deviceid);
1900 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1901 			return false;
1902 		case RTL_PCI_REVISION_ID_8192SE:
1903 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1904 				"8192SE is found - vid/did=%x/%x\n",
1905 				venderid, deviceid);
1906 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1907 			break;
1908 		default:
1909 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1910 				"Err: Unknown device - vid/did=%x/%x\n",
1911 				venderid, deviceid);
1912 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1913 			break;
1914 		}
1915 	} else if (deviceid == RTL_PCI_8723AE_DID) {
1916 		rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1917 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1918 			"8723AE PCI-E is found - vid/did=%x/%x\n",
1919 			venderid, deviceid);
1920 	} else if (deviceid == RTL_PCI_8192CET_DID ||
1921 		   deviceid == RTL_PCI_8192CE_DID ||
1922 		   deviceid == RTL_PCI_8191CE_DID ||
1923 		   deviceid == RTL_PCI_8188CE_DID) {
1924 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1925 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1926 			"8192C PCI-E is found - vid/did=%x/%x\n",
1927 			venderid, deviceid);
1928 	} else if (deviceid == RTL_PCI_8192DE_DID ||
1929 		   deviceid == RTL_PCI_8192DE_DID2) {
1930 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1931 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1932 			"8192D PCI-E is found - vid/did=%x/%x\n",
1933 			venderid, deviceid);
1934 	} else if (deviceid == RTL_PCI_8188EE_DID) {
1935 		rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1936 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1937 			"Find adapter, Hardware type is 8188EE\n");
1938 	} else if (deviceid == RTL_PCI_8723BE_DID) {
1939 		rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1940 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1941 			"Find adapter, Hardware type is 8723BE\n");
1942 	} else if (deviceid == RTL_PCI_8192EE_DID) {
1943 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1944 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1945 			"Find adapter, Hardware type is 8192EE\n");
1946 	} else if (deviceid == RTL_PCI_8821AE_DID) {
1947 		rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1948 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1949 			"Find adapter, Hardware type is 8821AE\n");
1950 	} else if (deviceid == RTL_PCI_8812AE_DID) {
1951 		rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1952 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1953 			"Find adapter, Hardware type is 8812AE\n");
1954 	} else if (deviceid == RTL_PCI_8822BE_DID) {
1955 		rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1956 		rtlhal->bandset = BAND_ON_BOTH;
1957 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1958 			"Find adapter, Hardware type is 8822BE\n");
1959 	} else {
1960 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1961 			"Err: Unknown device - vid/did=%x/%x\n",
1962 			 venderid, deviceid);
1963 
1964 		rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1965 	}
1966 
1967 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1968 		if (revisionid == 0 || revisionid == 1) {
1969 			if (revisionid == 0) {
1970 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1971 					"Find 92DE MAC0\n");
1972 				rtlhal->interfaceindex = 0;
1973 			} else if (revisionid == 1) {
1974 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1975 					"Find 92DE MAC1\n");
1976 				rtlhal->interfaceindex = 1;
1977 			}
1978 		} else {
1979 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1980 				"Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1981 				 venderid, deviceid, revisionid);
1982 			rtlhal->interfaceindex = 0;
1983 		}
1984 	}
1985 
1986 	switch (rtlhal->hw_type) {
1987 	case HARDWARE_TYPE_RTL8192EE:
1988 	case HARDWARE_TYPE_RTL8822BE:
1989 		/* use new trx flow */
1990 		rtlpriv->use_new_trx_flow = true;
1991 		break;
1992 
1993 	default:
1994 		rtlpriv->use_new_trx_flow = false;
1995 		break;
1996 	}
1997 
1998 	/*find bus info */
1999 	pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2000 	pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2001 	pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2002 
2003 	/*find bridge info */
2004 	pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2005 	/* some ARM have no bridge_pdev and will crash here
2006 	 * so we should check if bridge_pdev is NULL
2007 	 */
2008 	if (bridge_pdev) {
2009 		/*find bridge info if available */
2010 		pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2011 		for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2012 			if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2013 				pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2014 				rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2015 					"Pci Bridge Vendor is found index: %d\n",
2016 					tmp);
2017 				break;
2018 			}
2019 		}
2020 	}
2021 
2022 	if (pcipriv->ndis_adapter.pcibridge_vendor !=
2023 		PCI_BRIDGE_VENDOR_UNKNOWN) {
2024 		pcipriv->ndis_adapter.pcibridge_busnum =
2025 		    bridge_pdev->bus->number;
2026 		pcipriv->ndis_adapter.pcibridge_devnum =
2027 		    PCI_SLOT(bridge_pdev->devfn);
2028 		pcipriv->ndis_adapter.pcibridge_funcnum =
2029 		    PCI_FUNC(bridge_pdev->devfn);
2030 		pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2031 		    pci_pcie_cap(bridge_pdev);
2032 		pcipriv->ndis_adapter.num4bytes =
2033 		    (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2034 
2035 		rtl_pci_get_linkcontrol_field(hw);
2036 
2037 		if (pcipriv->ndis_adapter.pcibridge_vendor ==
2038 		    PCI_BRIDGE_VENDOR_AMD) {
2039 			pcipriv->ndis_adapter.amd_l1_patch =
2040 			    rtl_pci_get_amd_l1_patch(hw);
2041 		}
2042 	}
2043 
2044 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2045 		"pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2046 		pcipriv->ndis_adapter.busnumber,
2047 		pcipriv->ndis_adapter.devnumber,
2048 		pcipriv->ndis_adapter.funcnumber,
2049 		pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2050 
2051 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2052 		"pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2053 		pcipriv->ndis_adapter.pcibridge_busnum,
2054 		pcipriv->ndis_adapter.pcibridge_devnum,
2055 		pcipriv->ndis_adapter.pcibridge_funcnum,
2056 		pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2057 		pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2058 		pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2059 		pcipriv->ndis_adapter.amd_l1_patch);
2060 
2061 	rtl_pci_parse_configuration(pdev, hw);
2062 	list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2063 
2064 	return true;
2065 }
2066 
2067 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2068 {
2069 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2070 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2071 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2072 	int ret;
2073 
2074 	ret = pci_enable_msi(rtlpci->pdev);
2075 	if (ret < 0)
2076 		return ret;
2077 
2078 	ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2079 			  IRQF_SHARED, KBUILD_MODNAME, hw);
2080 	if (ret < 0) {
2081 		pci_disable_msi(rtlpci->pdev);
2082 		return ret;
2083 	}
2084 
2085 	rtlpci->using_msi = true;
2086 
2087 	rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2088 		"MSI Interrupt Mode!\n");
2089 	return 0;
2090 }
2091 
2092 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2093 {
2094 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2095 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2096 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2097 	int ret;
2098 
2099 	ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2100 			  IRQF_SHARED, KBUILD_MODNAME, hw);
2101 	if (ret < 0)
2102 		return ret;
2103 
2104 	rtlpci->using_msi = false;
2105 	rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2106 		"Pin-based Interrupt Mode!\n");
2107 	return 0;
2108 }
2109 
2110 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2111 {
2112 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2113 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2114 	int ret;
2115 
2116 	if (rtlpci->msi_support) {
2117 		ret = rtl_pci_intr_mode_msi(hw);
2118 		if (ret < 0)
2119 			ret = rtl_pci_intr_mode_legacy(hw);
2120 	} else {
2121 		ret = rtl_pci_intr_mode_legacy(hw);
2122 	}
2123 	return ret;
2124 }
2125 
2126 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2127 {
2128 	u8	value;
2129 
2130 	pci_read_config_byte(pdev, 0x719, &value);
2131 
2132 	/* 0x719 Bit5 is DMA64 bit fetch. */
2133 	if (dma64)
2134 		value |= BIT(5);
2135 	else
2136 		value &= ~BIT(5);
2137 
2138 	pci_write_config_byte(pdev, 0x719, value);
2139 }
2140 
2141 int rtl_pci_probe(struct pci_dev *pdev,
2142 		  const struct pci_device_id *id)
2143 {
2144 	struct ieee80211_hw *hw = NULL;
2145 
2146 	struct rtl_priv *rtlpriv = NULL;
2147 	struct rtl_pci_priv *pcipriv = NULL;
2148 	struct rtl_pci *rtlpci;
2149 	unsigned long pmem_start, pmem_len, pmem_flags;
2150 	int err;
2151 
2152 	err = pci_enable_device(pdev);
2153 	if (err) {
2154 		WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2155 			  pci_name(pdev));
2156 		return err;
2157 	}
2158 
2159 	if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2160 	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2161 		if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2162 			WARN_ONCE(true,
2163 				  "Unable to obtain 64bit DMA for consistent allocations\n");
2164 			err = -ENOMEM;
2165 			goto fail1;
2166 		}
2167 
2168 		platform_enable_dma64(pdev, true);
2169 	} else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2170 		if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2171 			WARN_ONCE(true,
2172 				  "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2173 			err = -ENOMEM;
2174 			goto fail1;
2175 		}
2176 
2177 		platform_enable_dma64(pdev, false);
2178 	}
2179 
2180 	pci_set_master(pdev);
2181 
2182 	hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2183 				sizeof(struct rtl_priv), &rtl_ops);
2184 	if (!hw) {
2185 		WARN_ONCE(true,
2186 			  "%s : ieee80211 alloc failed\n", pci_name(pdev));
2187 		err = -ENOMEM;
2188 		goto fail1;
2189 	}
2190 
2191 	SET_IEEE80211_DEV(hw, &pdev->dev);
2192 	pci_set_drvdata(pdev, hw);
2193 
2194 	rtlpriv = hw->priv;
2195 	rtlpriv->hw = hw;
2196 	pcipriv = (void *)rtlpriv->priv;
2197 	pcipriv->dev.pdev = pdev;
2198 	init_completion(&rtlpriv->firmware_loading_complete);
2199 	/*proximity init here*/
2200 	rtlpriv->proximity.proxim_on = false;
2201 
2202 	pcipriv = (void *)rtlpriv->priv;
2203 	pcipriv->dev.pdev = pdev;
2204 
2205 	/* init cfg & intf_ops */
2206 	rtlpriv->rtlhal.interface = INTF_PCI;
2207 	rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2208 	rtlpriv->intf_ops = &rtl_pci_ops;
2209 	rtlpriv->glb_var = &rtl_global_var;
2210 	rtl_efuse_ops_init(hw);
2211 
2212 	/* MEM map */
2213 	err = pci_request_regions(pdev, KBUILD_MODNAME);
2214 	if (err) {
2215 		WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2216 		goto fail1;
2217 	}
2218 
2219 	pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2220 	pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2221 	pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2222 
2223 	/*shared mem start */
2224 	rtlpriv->io.pci_mem_start =
2225 			(unsigned long)pci_iomap(pdev,
2226 			rtlpriv->cfg->bar_id, pmem_len);
2227 	if (rtlpriv->io.pci_mem_start == 0) {
2228 		WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2229 		err = -ENOMEM;
2230 		goto fail2;
2231 	}
2232 
2233 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2234 		"mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2235 		pmem_start, pmem_len, pmem_flags,
2236 		rtlpriv->io.pci_mem_start);
2237 
2238 	/* Disable Clk Request */
2239 	pci_write_config_byte(pdev, 0x81, 0);
2240 	/* leave D3 mode */
2241 	pci_write_config_byte(pdev, 0x44, 0);
2242 	pci_write_config_byte(pdev, 0x04, 0x06);
2243 	pci_write_config_byte(pdev, 0x04, 0x07);
2244 
2245 	/* find adapter */
2246 	if (!_rtl_pci_find_adapter(pdev, hw)) {
2247 		err = -ENODEV;
2248 		goto fail2;
2249 	}
2250 
2251 	/* Init IO handler */
2252 	_rtl_pci_io_handler_init(&pdev->dev, hw);
2253 
2254 	/*like read eeprom and so on */
2255 	rtlpriv->cfg->ops->read_eeprom_info(hw);
2256 
2257 	if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2258 		pr_err("Can't init_sw_vars\n");
2259 		err = -ENODEV;
2260 		goto fail3;
2261 	}
2262 	rtl_init_sw_leds(hw);
2263 
2264 	/*aspm */
2265 	rtl_pci_init_aspm(hw);
2266 
2267 	/* Init mac80211 sw */
2268 	err = rtl_init_core(hw);
2269 	if (err) {
2270 		pr_err("Can't allocate sw for mac80211\n");
2271 		goto fail3;
2272 	}
2273 
2274 	/* Init PCI sw */
2275 	err = rtl_pci_init(hw, pdev);
2276 	if (err) {
2277 		pr_err("Failed to init PCI\n");
2278 		goto fail3;
2279 	}
2280 
2281 	err = ieee80211_register_hw(hw);
2282 	if (err) {
2283 		pr_err("Can't register mac80211 hw.\n");
2284 		err = -ENODEV;
2285 		goto fail3;
2286 	}
2287 	rtlpriv->mac80211.mac80211_registered = 1;
2288 
2289 	/* add for debug */
2290 	rtl_debug_add_one(hw);
2291 
2292 	/*init rfkill */
2293 	rtl_init_rfkill(hw);	/* Init PCI sw */
2294 
2295 	rtlpci = rtl_pcidev(pcipriv);
2296 	err = rtl_pci_intr_mode_decide(hw);
2297 	if (err) {
2298 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2299 			"%s: failed to register IRQ handler\n",
2300 			wiphy_name(hw->wiphy));
2301 		goto fail3;
2302 	}
2303 	rtlpci->irq_alloc = 1;
2304 
2305 	set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2306 	return 0;
2307 
2308 fail3:
2309 	pci_set_drvdata(pdev, NULL);
2310 	rtl_deinit_core(hw);
2311 
2312 fail2:
2313 	if (rtlpriv->io.pci_mem_start != 0)
2314 		pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2315 
2316 	pci_release_regions(pdev);
2317 	complete(&rtlpriv->firmware_loading_complete);
2318 
2319 fail1:
2320 	if (hw)
2321 		ieee80211_free_hw(hw);
2322 	pci_disable_device(pdev);
2323 
2324 	return err;
2325 }
2326 EXPORT_SYMBOL(rtl_pci_probe);
2327 
2328 void rtl_pci_disconnect(struct pci_dev *pdev)
2329 {
2330 	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2331 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2332 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2333 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2334 	struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2335 
2336 	/* just in case driver is removed before firmware callback */
2337 	wait_for_completion(&rtlpriv->firmware_loading_complete);
2338 	clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2339 
2340 	/* remove form debug */
2341 	rtl_debug_remove_one(hw);
2342 
2343 	/*ieee80211_unregister_hw will call ops_stop */
2344 	if (rtlmac->mac80211_registered == 1) {
2345 		ieee80211_unregister_hw(hw);
2346 		rtlmac->mac80211_registered = 0;
2347 	} else {
2348 		rtl_deinit_deferred_work(hw, false);
2349 		rtlpriv->intf_ops->adapter_stop(hw);
2350 	}
2351 	rtlpriv->cfg->ops->disable_interrupt(hw);
2352 
2353 	/*deinit rfkill */
2354 	rtl_deinit_rfkill(hw);
2355 
2356 	rtl_pci_deinit(hw);
2357 	rtl_deinit_core(hw);
2358 	rtlpriv->cfg->ops->deinit_sw_vars(hw);
2359 
2360 	if (rtlpci->irq_alloc) {
2361 		free_irq(rtlpci->pdev->irq, hw);
2362 		rtlpci->irq_alloc = 0;
2363 	}
2364 
2365 	if (rtlpci->using_msi)
2366 		pci_disable_msi(rtlpci->pdev);
2367 
2368 	list_del(&rtlpriv->list);
2369 	if (rtlpriv->io.pci_mem_start != 0) {
2370 		pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2371 		pci_release_regions(pdev);
2372 	}
2373 
2374 	pci_disable_device(pdev);
2375 
2376 	rtl_pci_disable_aspm(hw);
2377 
2378 	pci_set_drvdata(pdev, NULL);
2379 
2380 	ieee80211_free_hw(hw);
2381 }
2382 EXPORT_SYMBOL(rtl_pci_disconnect);
2383 
2384 #ifdef CONFIG_PM_SLEEP
2385 /***************************************
2386  * kernel pci power state define:
2387  * PCI_D0         ((pci_power_t __force) 0)
2388  * PCI_D1         ((pci_power_t __force) 1)
2389  * PCI_D2         ((pci_power_t __force) 2)
2390  * PCI_D3hot      ((pci_power_t __force) 3)
2391  * PCI_D3cold     ((pci_power_t __force) 4)
2392  * PCI_UNKNOWN    ((pci_power_t __force) 5)
2393 
2394  * This function is called when system
2395  * goes into suspend state mac80211 will
2396  * call rtl_mac_stop() from the mac80211
2397  * suspend function first, So there is
2398  * no need to call hw_disable here.
2399  ****************************************/
2400 int rtl_pci_suspend(struct device *dev)
2401 {
2402 	struct ieee80211_hw *hw = dev_get_drvdata(dev);
2403 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2404 
2405 	rtlpriv->cfg->ops->hw_suspend(hw);
2406 	rtl_deinit_rfkill(hw);
2407 
2408 	return 0;
2409 }
2410 EXPORT_SYMBOL(rtl_pci_suspend);
2411 
2412 int rtl_pci_resume(struct device *dev)
2413 {
2414 	struct ieee80211_hw *hw = dev_get_drvdata(dev);
2415 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2416 
2417 	rtlpriv->cfg->ops->hw_resume(hw);
2418 	rtl_init_rfkill(hw);
2419 	return 0;
2420 }
2421 EXPORT_SYMBOL(rtl_pci_resume);
2422 #endif /* CONFIG_PM_SLEEP */
2423 
2424 const struct rtl_intf_ops rtl_pci_ops = {
2425 	.read_efuse_byte = read_efuse_byte,
2426 	.adapter_start = rtl_pci_start,
2427 	.adapter_stop = rtl_pci_stop,
2428 	.check_buddy_priv = rtl_pci_check_buddy_priv,
2429 	.adapter_tx = rtl_pci_tx,
2430 	.flush = rtl_pci_flush,
2431 	.reset_trx_ring = rtl_pci_reset_trx_ring,
2432 	.waitq_insert = rtl_pci_tx_chk_waitq_insert,
2433 
2434 	.disable_aspm = rtl_pci_disable_aspm,
2435 	.enable_aspm = rtl_pci_enable_aspm,
2436 };
2437