1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "wifi.h" 5 #include "core.h" 6 #include "pci.h" 7 #include "base.h" 8 #include "ps.h" 9 #include "efuse.h" 10 #include <linux/interrupt.h> 11 #include <linux/export.h> 12 #include <linux/module.h> 13 14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 17 MODULE_LICENSE("GPL"); 18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 19 20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 21 INTEL_VENDOR_ID, 22 ATI_VENDOR_ID, 23 AMD_VENDOR_ID, 24 SIS_VENDOR_ID 25 }; 26 27 static const u8 ac_to_hwq[] = { 28 VO_QUEUE, 29 VI_QUEUE, 30 BE_QUEUE, 31 BK_QUEUE 32 }; 33 34 static const struct pci_device_id rtl_aspm_quirks[] = { 35 /* ASUSTek F441U/X555UQ */ 36 { PCI_DEVICE_SUB(PCI_VENDOR_ID_REALTEK, 0xb723, 0x11ad, 0x1723) }, 37 /* Razer Blade 14 2017 */ 38 { PCI_DEVICE_SUB(PCI_VENDOR_ID_REALTEK, 0xb723, 0x17aa, 0xb736) }, 39 {} 40 }; 41 42 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 43 { 44 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 45 __le16 fc = rtl_get_fc(skb); 46 u8 queue_index = skb_get_queue_mapping(skb); 47 struct ieee80211_hdr *hdr; 48 49 if (unlikely(ieee80211_is_beacon(fc))) 50 return BEACON_QUEUE; 51 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 52 return MGNT_QUEUE; 53 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 54 if (ieee80211_is_nullfunc(fc)) 55 return HIGH_QUEUE; 56 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 57 hdr = rtl_get_hdr(skb); 58 59 if (is_multicast_ether_addr(hdr->addr1) || 60 is_broadcast_ether_addr(hdr->addr1)) 61 return HIGH_QUEUE; 62 } 63 64 return ac_to_hwq[queue_index]; 65 } 66 67 /* Update PCI dependent default settings*/ 68 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 69 { 70 struct rtl_priv *rtlpriv = rtl_priv(hw); 71 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 72 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 73 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 74 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 75 u16 init_aspm; 76 77 ppsc->reg_rfps_level = 0; 78 ppsc->support_aspm = false; 79 80 /*Update PCI ASPM setting */ 81 switch (rtlpci->const_pci_aspm) { 82 case 0: 83 /*No ASPM */ 84 break; 85 86 case 1: 87 /*ASPM dynamically enabled/disable. */ 88 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 89 break; 90 91 case 2: 92 /*ASPM with Clock Req dynamically enabled/disable. */ 93 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 94 RT_RF_OFF_LEVL_CLK_REQ); 95 break; 96 97 case 3: 98 /* Always enable ASPM and Clock Req 99 * from initialization to halt. 100 */ 101 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 102 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 103 RT_RF_OFF_LEVL_CLK_REQ); 104 break; 105 106 case 4: 107 /* Always enable ASPM without Clock Req 108 * from initialization to halt. 109 */ 110 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 111 RT_RF_OFF_LEVL_CLK_REQ); 112 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 113 break; 114 } 115 116 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 117 118 /*Update Radio OFF setting */ 119 switch (rtlpci->const_hwsw_rfoff_d3) { 120 case 1: 121 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 122 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 123 break; 124 125 case 2: 126 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 128 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 129 break; 130 131 case 3: 132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 133 break; 134 } 135 136 /*Set HW definition to determine if it supports ASPM. */ 137 switch (rtlpci->const_support_pciaspm) { 138 case 0: 139 /*Not support ASPM. */ 140 ppsc->support_aspm = false; 141 break; 142 case 1: 143 /*Support ASPM. */ 144 ppsc->support_aspm = true; 145 ppsc->support_backdoor = true; 146 break; 147 case 2: 148 /*ASPM value set by chipset. */ 149 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 150 ppsc->support_aspm = true; 151 break; 152 default: 153 pr_err("switch case %#x not processed\n", 154 rtlpci->const_support_pciaspm); 155 break; 156 } 157 158 /* toshiba aspm issue, toshiba will set aspm selfly 159 * so we should not set aspm in driver 160 */ 161 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &init_aspm); 162 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 163 ((u8)init_aspm) == (PCI_EXP_LNKCTL_ASPM_L0S | 164 PCI_EXP_LNKCTL_ASPM_L1 | PCI_EXP_LNKCTL_CCC)) 165 ppsc->support_aspm = false; 166 167 } 168 169 static bool _rtl_pci_platform_switch_device_pci_aspm( 170 struct ieee80211_hw *hw, 171 u8 value) 172 { 173 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 174 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 175 176 value &= PCI_EXP_LNKCTL_ASPMC; 177 178 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 179 value |= PCI_EXP_LNKCTL_CCC; 180 181 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 182 PCI_EXP_LNKCTL_ASPMC | value, 183 value); 184 185 return false; 186 } 187 188 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */ 189 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value) 190 { 191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 192 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 193 194 value &= PCI_EXP_LNKCTL_CLKREQ_EN; 195 196 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 197 PCI_EXP_LNKCTL_CLKREQ_EN, 198 value); 199 200 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 201 udelay(100); 202 } 203 204 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 205 static void __rtl_pci_disable_aspm(struct ieee80211_hw *hw) 206 { 207 struct rtl_priv *rtlpriv = rtl_priv(hw); 208 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 209 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 210 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 211 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 212 /*Retrieve original configuration settings. */ 213 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 214 u16 aspmlevel = 0; 215 u16 tmp_u1b = 0; 216 217 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 218 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 219 "PCI(Bridge) UNKNOWN\n"); 220 221 return; 222 } 223 224 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 225 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 226 _rtl_pci_switch_clk_req(hw, 0x0); 227 } 228 229 /*for promising device will in L0 state after an I/O. */ 230 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &tmp_u1b); 231 232 /*Set corresponding value. */ 233 aspmlevel |= PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1; 234 linkctrl_reg &= ~aspmlevel; 235 236 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 237 } 238 239 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 240 { 241 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 242 243 if (!ppsc->support_aspm) 244 return; 245 246 __rtl_pci_disable_aspm(hw); 247 } 248 249 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 250 *power saving We should follow the sequence to enable 251 *RTL8192SE first then enable Pci Bridge ASPM 252 *or the system will show bluescreen. 253 */ 254 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 255 { 256 struct rtl_priv *rtlpriv = rtl_priv(hw); 257 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 258 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 259 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 260 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 261 u16 aspmlevel; 262 u8 u_device_aspmsetting; 263 264 if (!ppsc->support_aspm) 265 return; 266 267 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 268 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 269 "PCI(Bridge) UNKNOWN\n"); 270 return; 271 } 272 273 /*Get ASPM level (with/without Clock Req) */ 274 aspmlevel = rtlpci->const_devicepci_aspm_setting; 275 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 276 277 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 278 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 279 280 u_device_aspmsetting |= aspmlevel; 281 282 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 283 284 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 285 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 286 RT_RF_OFF_LEVL_CLK_REQ) ? 287 PCI_EXP_LNKCTL_CLKREQ_EN : 0); 288 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 289 } 290 udelay(100); 291 } 292 293 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 294 { 295 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 296 297 bool status = false; 298 u8 offset_e0; 299 unsigned int offset_e4; 300 301 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 302 303 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 304 305 if (offset_e0 == 0xA0) { 306 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 307 if (offset_e4 & BIT(23)) 308 status = true; 309 } 310 311 return status; 312 } 313 314 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 315 struct ieee80211_hw *hw) 316 { 317 struct rtl_priv *rtlpriv = rtl_priv(hw); 318 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 319 320 u8 tmp; 321 u16 linkctrl_reg; 322 323 /*Link Control Register */ 324 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 325 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 326 327 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 328 pcipriv->ndis_adapter.linkctrl_reg); 329 330 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 331 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 332 333 tmp = 0x17; 334 pci_write_config_byte(pdev, 0x70f, tmp); 335 } 336 337 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 338 { 339 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 340 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 341 342 _rtl_pci_update_default_setting(hw); 343 344 /* 345 * Certain pci devices are known to output large 346 * amounts of PCIe AER errors during and after boot up, causing 347 * heavy lags, poor network throughput, and occasional lock-ups. 348 */ 349 if (pci_match_id(rtl_aspm_quirks, rtlpci->pdev)) { 350 __rtl_pci_disable_aspm(hw); 351 ppsc->support_aspm = false; 352 } 353 354 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 355 /*Always enable ASPM & Clock Req. */ 356 rtl_pci_enable_aspm(hw); 357 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 358 } 359 } 360 361 static void _rtl_pci_io_handler_init(struct device *dev, 362 struct ieee80211_hw *hw) 363 { 364 struct rtl_priv *rtlpriv = rtl_priv(hw); 365 366 rtlpriv->io.dev = dev; 367 368 rtlpriv->io.write8 = pci_write8_async; 369 rtlpriv->io.write16 = pci_write16_async; 370 rtlpriv->io.write32 = pci_write32_async; 371 372 rtlpriv->io.read8 = pci_read8_sync; 373 rtlpriv->io.read16 = pci_read16_sync; 374 rtlpriv->io.read32 = pci_read32_sync; 375 } 376 377 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 378 struct sk_buff *skb, 379 struct rtl_tcb_desc *tcb_desc, u8 tid) 380 { 381 struct rtl_priv *rtlpriv = rtl_priv(hw); 382 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 383 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 384 struct sk_buff *next_skb; 385 u8 additionlen = FCS_LEN; 386 387 /* here open is 4, wep/tkip is 8, aes is 12*/ 388 if (info->control.hw_key) 389 additionlen += info->control.hw_key->icv_len; 390 391 /* The most skb num is 6 */ 392 tcb_desc->empkt_num = 0; 393 spin_lock_bh(&rtlpriv->locks.waitq_lock); 394 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 395 struct ieee80211_tx_info *next_info; 396 397 next_info = IEEE80211_SKB_CB(next_skb); 398 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 399 tcb_desc->empkt_len[tcb_desc->empkt_num] = 400 next_skb->len + additionlen; 401 tcb_desc->empkt_num++; 402 } else { 403 break; 404 } 405 406 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 407 next_skb)) 408 break; 409 410 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 411 break; 412 } 413 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 414 415 return true; 416 } 417 418 /* just for early mode now */ 419 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 420 { 421 struct rtl_priv *rtlpriv = rtl_priv(hw); 422 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 423 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 424 struct sk_buff *skb = NULL; 425 struct ieee80211_tx_info *info = NULL; 426 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 427 int tid; 428 429 if (!rtlpriv->rtlhal.earlymode_enable) 430 return; 431 432 /* we just use em for BE/BK/VI/VO */ 433 for (tid = 7; tid >= 0; tid--) { 434 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 435 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 436 437 while (!mac->act_scanning && 438 rtlpriv->psc.rfpwr_state == ERFON) { 439 struct rtl_tcb_desc tcb_desc; 440 441 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 442 443 spin_lock(&rtlpriv->locks.waitq_lock); 444 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 445 (ring->entries - skb_queue_len(&ring->queue) > 446 rtlhal->max_earlymode_num)) { 447 skb = skb_dequeue(&mac->skb_waitq[tid]); 448 } else { 449 spin_unlock(&rtlpriv->locks.waitq_lock); 450 break; 451 } 452 spin_unlock(&rtlpriv->locks.waitq_lock); 453 454 /* Some macaddr can't do early mode. like 455 * multicast/broadcast/no_qos data 456 */ 457 info = IEEE80211_SKB_CB(skb); 458 if (info->flags & IEEE80211_TX_CTL_AMPDU) 459 _rtl_update_earlymode_info(hw, skb, 460 &tcb_desc, tid); 461 462 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 463 } 464 } 465 } 466 467 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 468 { 469 struct rtl_priv *rtlpriv = rtl_priv(hw); 470 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 471 472 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 473 474 while (skb_queue_len(&ring->queue)) { 475 struct sk_buff *skb; 476 struct ieee80211_tx_info *info; 477 __le16 fc; 478 u8 tid; 479 u8 *entry; 480 481 if (rtlpriv->use_new_trx_flow) 482 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 483 else 484 entry = (u8 *)(&ring->desc[ring->idx]); 485 486 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 487 return; 488 ring->idx = (ring->idx + 1) % ring->entries; 489 490 skb = __skb_dequeue(&ring->queue); 491 dma_unmap_single(&rtlpci->pdev->dev, 492 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 493 true, HW_DESC_TXBUFF_ADDR), 494 skb->len, DMA_TO_DEVICE); 495 496 /* remove early mode header */ 497 if (rtlpriv->rtlhal.earlymode_enable) 498 skb_pull(skb, EM_HDR_LEN); 499 500 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 501 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 502 ring->idx, 503 skb_queue_len(&ring->queue), 504 *(u16 *)(skb->data + 22)); 505 506 if (prio == TXCMD_QUEUE) { 507 dev_kfree_skb(skb); 508 goto tx_status_ok; 509 } 510 511 /* for sw LPS, just after NULL skb send out, we can 512 * sure AP knows we are sleeping, we should not let 513 * rf sleep 514 */ 515 fc = rtl_get_fc(skb); 516 if (ieee80211_is_nullfunc(fc)) { 517 if (ieee80211_has_pm(fc)) { 518 rtlpriv->mac80211.offchan_delay = true; 519 rtlpriv->psc.state_inap = true; 520 } else { 521 rtlpriv->psc.state_inap = false; 522 } 523 } 524 if (ieee80211_is_action(fc)) { 525 struct ieee80211_mgmt *action_frame = (void *)skb->data; 526 527 if (skb->len >= IEEE80211_MIN_ACTION_SIZE(action_code) && 528 action_frame->u.action.action_code == 529 WLAN_HT_ACTION_SMPS) { 530 dev_kfree_skb(skb); 531 goto tx_status_ok; 532 } 533 } 534 535 /* update tid tx pkt num */ 536 tid = rtl_get_tid(skb); 537 if (tid <= 7) 538 rtlpriv->link_info.tidtx_inperiod[tid]++; 539 540 info = IEEE80211_SKB_CB(skb); 541 542 if (likely(!ieee80211_is_nullfunc(fc))) { 543 ieee80211_tx_info_clear_status(info); 544 info->flags |= IEEE80211_TX_STAT_ACK; 545 /*info->status.rates[0].count = 1; */ 546 ieee80211_tx_status_irqsafe(hw, skb); 547 } else { 548 rtl_tx_ackqueue(hw, skb); 549 } 550 551 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 552 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, 553 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 554 prio, ring->idx, 555 skb_queue_len(&ring->queue)); 556 557 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 558 } 559 tx_status_ok: 560 skb = NULL; 561 } 562 563 if (((rtlpriv->link_info.num_rx_inperiod + 564 rtlpriv->link_info.num_tx_inperiod) > 8) || 565 rtlpriv->link_info.num_rx_inperiod > 2) 566 rtl_lps_leave(hw, false); 567 } 568 569 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 570 struct sk_buff *new_skb, u8 *entry, 571 int rxring_idx, int desc_idx) 572 { 573 struct rtl_priv *rtlpriv = rtl_priv(hw); 574 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 575 u32 bufferaddress; 576 u8 tmp_one = 1; 577 struct sk_buff *skb; 578 579 if (likely(new_skb)) { 580 skb = new_skb; 581 goto remap; 582 } 583 skb = dev_alloc_skb(rtlpci->rxbuffersize); 584 if (!skb) 585 return 0; 586 587 remap: 588 /* just set skb->cb to mapping addr for pci_unmap_single use */ 589 *((dma_addr_t *)skb->cb) = 590 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb), 591 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 592 bufferaddress = *((dma_addr_t *)skb->cb); 593 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress)) { 594 if (!new_skb) 595 kfree_skb(skb); 596 return 0; 597 } 598 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 599 if (rtlpriv->use_new_trx_flow) { 600 /* skb->cb may be 64 bit address */ 601 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 602 HW_DESC_RX_PREPARE, 603 (u8 *)(dma_addr_t *)skb->cb); 604 } else { 605 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 606 HW_DESC_RXBUFF_ADDR, 607 (u8 *)&bufferaddress); 608 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 609 HW_DESC_RXPKT_LEN, 610 (u8 *)&rtlpci->rxbuffersize); 611 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 612 HW_DESC_RXOWN, 613 (u8 *)&tmp_one); 614 } 615 return 1; 616 } 617 618 /* inorder to receive 8K AMSDU we have set skb to 619 * 9100bytes in init rx ring, but if this packet is 620 * not a AMSDU, this large packet will be sent to 621 * TCP/IP directly, this cause big packet ping fail 622 * like: "ping -s 65507", so here we will realloc skb 623 * based on the true size of packet, Mac80211 624 * Probably will do it better, but does not yet. 625 * 626 * Some platform will fail when alloc skb sometimes. 627 * in this condition, we will send the old skb to 628 * mac80211 directly, this will not cause any other 629 * issues, but only this packet will be lost by TCP/IP 630 */ 631 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 632 struct sk_buff *skb, 633 struct ieee80211_rx_status rx_status) 634 { 635 if (unlikely(!rtl_action_proc(hw, skb, false))) { 636 dev_kfree_skb_any(skb); 637 } else { 638 struct sk_buff *uskb = NULL; 639 640 uskb = dev_alloc_skb(skb->len + 128); 641 if (likely(uskb)) { 642 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 643 sizeof(rx_status)); 644 skb_put_data(uskb, skb->data, skb->len); 645 dev_kfree_skb_any(skb); 646 ieee80211_rx_irqsafe(hw, uskb); 647 } else { 648 ieee80211_rx_irqsafe(hw, skb); 649 } 650 } 651 } 652 653 /*hsisr interrupt handler*/ 654 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 655 { 656 struct rtl_priv *rtlpriv = rtl_priv(hw); 657 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 658 659 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 660 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 661 rtlpci->sys_irq_mask); 662 } 663 664 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 665 { 666 struct rtl_priv *rtlpriv = rtl_priv(hw); 667 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 668 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 669 struct ieee80211_rx_status rx_status = { 0 }; 670 unsigned int count = rtlpci->rxringcount; 671 u8 own; 672 u8 tmp_one; 673 bool unicast = false; 674 u8 hw_queue = 0; 675 unsigned int rx_remained_cnt = 0; 676 struct rtl_stats stats = { 677 .signal = 0, 678 .rate = 0, 679 }; 680 681 /*RX NORMAL PKT */ 682 while (count--) { 683 struct ieee80211_hdr *hdr; 684 __le16 fc; 685 u16 len; 686 /*rx buffer descriptor */ 687 struct rtl_rx_buffer_desc *buffer_desc = NULL; 688 /*if use new trx flow, it means wifi info */ 689 struct rtl_rx_desc *pdesc = NULL; 690 /*rx pkt */ 691 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 692 rtlpci->rx_ring[rxring_idx].idx]; 693 struct sk_buff *new_skb; 694 695 if (rtlpriv->use_new_trx_flow) { 696 if (rx_remained_cnt == 0) 697 rx_remained_cnt = 698 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 699 hw_queue); 700 if (rx_remained_cnt == 0) 701 return; 702 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 703 rtlpci->rx_ring[rxring_idx].idx]; 704 pdesc = (struct rtl_rx_desc *)skb->data; 705 } else { /* rx descriptor */ 706 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 707 rtlpci->rx_ring[rxring_idx].idx]; 708 709 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 710 false, 711 HW_DESC_OWN); 712 if (own) /* wait data to be filled by hardware */ 713 return; 714 } 715 716 /* Reaching this point means: data is filled already 717 * AAAAAAttention !!! 718 * We can NOT access 'skb' before 'pci_unmap_single' 719 */ 720 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 721 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 722 723 /* get a new skb - if fail, old one will be reused */ 724 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 725 if (unlikely(!new_skb)) 726 goto no_new; 727 memset(&rx_status, 0, sizeof(rx_status)); 728 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 729 &rx_status, (u8 *)pdesc, skb); 730 731 if (rtlpriv->use_new_trx_flow) 732 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 733 (u8 *)buffer_desc, 734 hw_queue); 735 736 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 737 HW_DESC_RXPKT_LEN); 738 739 if (skb->end - skb->tail > len) { 740 skb_put(skb, len); 741 if (rtlpriv->use_new_trx_flow) 742 skb_reserve(skb, stats.rx_drvinfo_size + 743 stats.rx_bufshift + 24); 744 else 745 skb_reserve(skb, stats.rx_drvinfo_size + 746 stats.rx_bufshift); 747 } else { 748 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 749 "skb->end - skb->tail = %d, len is %d\n", 750 skb->end - skb->tail, len); 751 dev_kfree_skb_any(skb); 752 goto new_trx_end; 753 } 754 /* handle command packet here */ 755 if (stats.packet_report_type == C2H_PACKET) { 756 rtl_c2hcmd_enqueue(hw, skb); 757 goto new_trx_end; 758 } 759 760 /* NOTICE This can not be use for mac80211, 761 * this is done in mac80211 code, 762 * if done here sec DHCP will fail 763 * skb_trim(skb, skb->len - 4); 764 */ 765 766 hdr = rtl_get_hdr(skb); 767 fc = rtl_get_fc(skb); 768 769 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) { 770 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 771 sizeof(rx_status)); 772 773 if (is_broadcast_ether_addr(hdr->addr1)) { 774 ;/*TODO*/ 775 } else if (is_multicast_ether_addr(hdr->addr1)) { 776 ;/*TODO*/ 777 } else { 778 unicast = true; 779 rtlpriv->stats.rxbytesunicast += skb->len; 780 } 781 rtl_is_special_data(hw, skb, false, true); 782 783 if (ieee80211_is_data(fc)) { 784 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 785 if (unicast) 786 rtlpriv->link_info.num_rx_inperiod++; 787 } 788 789 rtl_collect_scan_list(hw, skb); 790 791 /* static bcn for roaming */ 792 rtl_beacon_statistic(hw, skb); 793 rtl_p2p_info(hw, (void *)skb->data, skb->len); 794 /* for sw lps */ 795 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 796 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 797 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 798 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 799 (ieee80211_is_beacon(fc) || 800 ieee80211_is_probe_resp(fc))) { 801 dev_kfree_skb_any(skb); 802 } else { 803 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 804 } 805 } else { 806 /* drop packets with errors or those too short */ 807 dev_kfree_skb_any(skb); 808 } 809 new_trx_end: 810 if (rtlpriv->use_new_trx_flow) { 811 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 812 rtlpci->rx_ring[hw_queue].next_rx_rp %= 813 RTL_PCI_MAX_RX_COUNT; 814 815 rx_remained_cnt--; 816 rtl_write_word(rtlpriv, 0x3B4, 817 rtlpci->rx_ring[hw_queue].next_rx_rp); 818 } 819 if (((rtlpriv->link_info.num_rx_inperiod + 820 rtlpriv->link_info.num_tx_inperiod) > 8) || 821 rtlpriv->link_info.num_rx_inperiod > 2) 822 rtl_lps_leave(hw, false); 823 skb = new_skb; 824 no_new: 825 if (rtlpriv->use_new_trx_flow) { 826 if (!_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 827 rxring_idx, 828 rtlpci->rx_ring[rxring_idx].idx)) { 829 if (new_skb) 830 dev_kfree_skb_any(skb); 831 } 832 } else { 833 if (!_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 834 rxring_idx, 835 rtlpci->rx_ring[rxring_idx].idx)) { 836 if (new_skb) 837 dev_kfree_skb_any(skb); 838 } 839 if (rtlpci->rx_ring[rxring_idx].idx == 840 rtlpci->rxringcount - 1) 841 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 842 false, 843 HW_DESC_RXERO, 844 (u8 *)&tmp_one); 845 } 846 rtlpci->rx_ring[rxring_idx].idx = 847 (rtlpci->rx_ring[rxring_idx].idx + 1) % 848 rtlpci->rxringcount; 849 } 850 } 851 852 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 853 { 854 struct ieee80211_hw *hw = dev_id; 855 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 856 struct rtl_priv *rtlpriv = rtl_priv(hw); 857 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 858 unsigned long flags; 859 struct rtl_int intvec = {0}; 860 861 irqreturn_t ret = IRQ_HANDLED; 862 863 if (rtlpci->irq_enabled == 0) 864 return ret; 865 866 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 867 rtlpriv->cfg->ops->disable_interrupt(hw); 868 869 /*read ISR: 4/8bytes */ 870 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 871 872 /*Shared IRQ or HW disappeared */ 873 if (!intvec.inta || intvec.inta == 0xffff) 874 goto done; 875 876 /*<1> beacon related */ 877 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 878 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 879 "beacon ok interrupt!\n"); 880 881 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 882 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 883 "beacon err interrupt!\n"); 884 885 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 886 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 887 888 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 889 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 890 "prepare beacon for interrupt!\n"); 891 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 892 } 893 894 /*<2> Tx related */ 895 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 896 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 897 898 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 899 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 900 "Manage ok interrupt!\n"); 901 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 902 } 903 904 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 905 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 906 "HIGH_QUEUE ok interrupt!\n"); 907 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 908 } 909 910 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 911 rtlpriv->link_info.num_tx_inperiod++; 912 913 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 914 "BK Tx OK interrupt!\n"); 915 _rtl_pci_tx_isr(hw, BK_QUEUE); 916 } 917 918 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 919 rtlpriv->link_info.num_tx_inperiod++; 920 921 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 922 "BE TX OK interrupt!\n"); 923 _rtl_pci_tx_isr(hw, BE_QUEUE); 924 } 925 926 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 927 rtlpriv->link_info.num_tx_inperiod++; 928 929 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 930 "VI TX OK interrupt!\n"); 931 _rtl_pci_tx_isr(hw, VI_QUEUE); 932 } 933 934 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 935 rtlpriv->link_info.num_tx_inperiod++; 936 937 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 938 "Vo TX OK interrupt!\n"); 939 _rtl_pci_tx_isr(hw, VO_QUEUE); 940 } 941 942 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 943 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 944 rtlpriv->link_info.num_tx_inperiod++; 945 946 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 947 "H2C TX OK interrupt!\n"); 948 _rtl_pci_tx_isr(hw, H2C_QUEUE); 949 } 950 } 951 952 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 953 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 954 rtlpriv->link_info.num_tx_inperiod++; 955 956 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 957 "CMD TX OK interrupt!\n"); 958 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 959 } 960 } 961 962 /*<3> Rx related */ 963 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 964 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 965 _rtl_pci_rx_interrupt(hw); 966 } 967 968 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 969 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 970 "rx descriptor unavailable!\n"); 971 _rtl_pci_rx_interrupt(hw); 972 } 973 974 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 975 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 976 _rtl_pci_rx_interrupt(hw); 977 } 978 979 /*<4> fw related*/ 980 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 981 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 982 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 983 "firmware interrupt!\n"); 984 queue_delayed_work(rtlpriv->works.rtl_wq, 985 &rtlpriv->works.fwevt_wq, 0); 986 } 987 } 988 989 /*<5> hsisr related*/ 990 /* Only 8188EE & 8723BE Supported. 991 * If Other ICs Come in, System will corrupt, 992 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 993 * are not initialized 994 */ 995 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 996 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 997 if (unlikely(intvec.inta & 998 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 999 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 1000 "hsisr interrupt!\n"); 1001 _rtl_pci_hs_interrupt(hw); 1002 } 1003 } 1004 1005 if (rtlpriv->rtlhal.earlymode_enable) 1006 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1007 1008 done: 1009 rtlpriv->cfg->ops->enable_interrupt(hw); 1010 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1011 return ret; 1012 } 1013 1014 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t) 1015 { 1016 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet); 1017 struct ieee80211_hw *hw = rtlpriv->hw; 1018 _rtl_pci_tx_chk_waitq(hw); 1019 } 1020 1021 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t) 1022 { 1023 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, 1024 works.irq_prepare_bcn_tasklet); 1025 struct ieee80211_hw *hw = rtlpriv->hw; 1026 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1027 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1028 struct rtl8192_tx_ring *ring = NULL; 1029 struct ieee80211_hdr *hdr = NULL; 1030 struct ieee80211_tx_info *info = NULL; 1031 struct sk_buff *pskb = NULL; 1032 struct rtl_tx_desc *pdesc = NULL; 1033 struct rtl_tcb_desc tcb_desc; 1034 /*This is for new trx flow*/ 1035 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1036 u8 temp_one = 1; 1037 u8 *entry; 1038 1039 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1040 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1041 pskb = __skb_dequeue(&ring->queue); 1042 if (rtlpriv->use_new_trx_flow) 1043 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1044 else 1045 entry = (u8 *)(&ring->desc[ring->idx]); 1046 if (pskb) { 1047 dma_unmap_single(&rtlpci->pdev->dev, 1048 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1049 true, HW_DESC_TXBUFF_ADDR), 1050 pskb->len, DMA_TO_DEVICE); 1051 kfree_skb(pskb); 1052 } 1053 1054 /*NB: the beacon data buffer must be 32-bit aligned. */ 1055 pskb = ieee80211_beacon_get(hw, mac->vif, 0); 1056 if (!pskb) 1057 return; 1058 hdr = rtl_get_hdr(pskb); 1059 info = IEEE80211_SKB_CB(pskb); 1060 pdesc = &ring->desc[0]; 1061 if (rtlpriv->use_new_trx_flow) 1062 pbuffer_desc = &ring->buffer_desc[0]; 1063 1064 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1065 (u8 *)pbuffer_desc, info, NULL, pskb, 1066 BEACON_QUEUE, &tcb_desc); 1067 1068 __skb_queue_tail(&ring->queue, pskb); 1069 1070 if (rtlpriv->use_new_trx_flow) { 1071 temp_one = 4; 1072 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1073 HW_DESC_OWN, (u8 *)&temp_one); 1074 } else { 1075 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1076 &temp_one); 1077 } 1078 } 1079 1080 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1081 { 1082 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1083 struct rtl_priv *rtlpriv = rtl_priv(hw); 1084 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1085 u8 i; 1086 u16 desc_num; 1087 1088 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1089 desc_num = TX_DESC_NUM_92E; 1090 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1091 desc_num = TX_DESC_NUM_8822B; 1092 else 1093 desc_num = RT_TXDESC_NUM; 1094 1095 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1096 rtlpci->txringcount[i] = desc_num; 1097 1098 /*we just alloc 2 desc for beacon queue, 1099 *because we just need first desc in hw beacon. 1100 */ 1101 rtlpci->txringcount[BEACON_QUEUE] = 2; 1102 1103 /*BE queue need more descriptor for performance 1104 *consideration or, No more tx desc will happen, 1105 *and may cause mac80211 mem leakage. 1106 */ 1107 if (!rtl_priv(hw)->use_new_trx_flow) 1108 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1109 1110 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1111 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1112 } 1113 1114 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1115 struct pci_dev *pdev) 1116 { 1117 struct rtl_priv *rtlpriv = rtl_priv(hw); 1118 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1119 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1121 1122 rtlpci->up_first_time = true; 1123 rtlpci->being_init_adapter = false; 1124 1125 rtlhal->hw = hw; 1126 rtlpci->pdev = pdev; 1127 1128 /*Tx/Rx related var */ 1129 _rtl_pci_init_trx_var(hw); 1130 1131 /*IBSS*/ 1132 mac->beacon_interval = 100; 1133 1134 /*AMPDU*/ 1135 mac->min_space_cfg = 0; 1136 mac->max_mss_density = 0; 1137 /*set sane AMPDU defaults */ 1138 mac->current_ampdu_density = 7; 1139 mac->current_ampdu_factor = 3; 1140 1141 /*Retry Limit*/ 1142 mac->retry_short = 7; 1143 mac->retry_long = 7; 1144 1145 /*QOS*/ 1146 rtlpci->acm_method = EACMWAY2_SW; 1147 1148 /*task */ 1149 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet); 1150 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet, 1151 _rtl_pci_prepare_bcn_tasklet); 1152 INIT_WORK(&rtlpriv->works.lps_change_work, 1153 rtl_lps_change_work_callback); 1154 } 1155 1156 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1157 unsigned int prio, unsigned int entries) 1158 { 1159 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 struct rtl_tx_buffer_desc *buffer_desc; 1162 struct rtl_tx_desc *desc; 1163 dma_addr_t buffer_desc_dma, desc_dma; 1164 u32 nextdescaddress; 1165 int i; 1166 1167 /* alloc tx buffer desc for new trx flow*/ 1168 if (rtlpriv->use_new_trx_flow) { 1169 buffer_desc = 1170 dma_alloc_coherent(&rtlpci->pdev->dev, 1171 sizeof(*buffer_desc) * entries, 1172 &buffer_desc_dma, GFP_KERNEL); 1173 1174 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1175 pr_err("Cannot allocate TX ring (prio = %d)\n", 1176 prio); 1177 return -ENOMEM; 1178 } 1179 1180 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1181 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1182 1183 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1184 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1185 } 1186 1187 /* alloc dma for this ring */ 1188 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries, 1189 &desc_dma, GFP_KERNEL); 1190 1191 if (!desc || (unsigned long)desc & 0xFF) { 1192 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1193 return -ENOMEM; 1194 } 1195 1196 rtlpci->tx_ring[prio].desc = desc; 1197 rtlpci->tx_ring[prio].dma = desc_dma; 1198 1199 rtlpci->tx_ring[prio].idx = 0; 1200 rtlpci->tx_ring[prio].entries = entries; 1201 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1202 1203 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1204 prio, desc); 1205 1206 /* init every desc in this ring */ 1207 if (!rtlpriv->use_new_trx_flow) { 1208 for (i = 0; i < entries; i++) { 1209 nextdescaddress = (u32)desc_dma + 1210 ((i + 1) % entries) * 1211 sizeof(*desc); 1212 1213 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1214 true, 1215 HW_DESC_TX_NEXTDESC_ADDR, 1216 (u8 *)&nextdescaddress); 1217 } 1218 } 1219 return 0; 1220 } 1221 1222 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1223 { 1224 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1225 struct rtl_priv *rtlpriv = rtl_priv(hw); 1226 int i; 1227 1228 if (rtlpriv->use_new_trx_flow) { 1229 struct rtl_rx_buffer_desc *entry = NULL; 1230 /* alloc dma for this ring */ 1231 rtlpci->rx_ring[rxring_idx].buffer_desc = 1232 dma_alloc_coherent(&rtlpci->pdev->dev, 1233 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1234 rtlpci->rxringcount, 1235 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1236 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1237 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1238 pr_err("Cannot allocate RX ring\n"); 1239 return -ENOMEM; 1240 } 1241 1242 /* init every desc in this ring */ 1243 rtlpci->rx_ring[rxring_idx].idx = 0; 1244 for (i = 0; i < rtlpci->rxringcount; i++) { 1245 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1246 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1247 rxring_idx, i)) 1248 return -ENOMEM; 1249 } 1250 } else { 1251 struct rtl_rx_desc *entry = NULL; 1252 u8 tmp_one = 1; 1253 /* alloc dma for this ring */ 1254 rtlpci->rx_ring[rxring_idx].desc = 1255 dma_alloc_coherent(&rtlpci->pdev->dev, 1256 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1257 rtlpci->rxringcount, 1258 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1259 if (!rtlpci->rx_ring[rxring_idx].desc || 1260 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1261 pr_err("Cannot allocate RX ring\n"); 1262 return -ENOMEM; 1263 } 1264 1265 /* init every desc in this ring */ 1266 rtlpci->rx_ring[rxring_idx].idx = 0; 1267 1268 for (i = 0; i < rtlpci->rxringcount; i++) { 1269 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1270 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1271 rxring_idx, i)) 1272 return -ENOMEM; 1273 } 1274 1275 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1276 HW_DESC_RXERO, &tmp_one); 1277 } 1278 return 0; 1279 } 1280 1281 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1282 unsigned int prio) 1283 { 1284 struct rtl_priv *rtlpriv = rtl_priv(hw); 1285 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1286 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1287 1288 /* free every desc in this ring */ 1289 while (skb_queue_len(&ring->queue)) { 1290 u8 *entry; 1291 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1292 1293 if (rtlpriv->use_new_trx_flow) 1294 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1295 else 1296 entry = (u8 *)(&ring->desc[ring->idx]); 1297 1298 dma_unmap_single(&rtlpci->pdev->dev, 1299 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1300 true, HW_DESC_TXBUFF_ADDR), 1301 skb->len, DMA_TO_DEVICE); 1302 kfree_skb(skb); 1303 ring->idx = (ring->idx + 1) % ring->entries; 1304 } 1305 1306 /* free dma of this ring */ 1307 dma_free_coherent(&rtlpci->pdev->dev, 1308 sizeof(*ring->desc) * ring->entries, ring->desc, 1309 ring->dma); 1310 ring->desc = NULL; 1311 if (rtlpriv->use_new_trx_flow) { 1312 dma_free_coherent(&rtlpci->pdev->dev, 1313 sizeof(*ring->buffer_desc) * ring->entries, 1314 ring->buffer_desc, ring->buffer_desc_dma); 1315 ring->buffer_desc = NULL; 1316 } 1317 } 1318 1319 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1320 { 1321 struct rtl_priv *rtlpriv = rtl_priv(hw); 1322 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1323 int i; 1324 1325 /* free every desc in this ring */ 1326 for (i = 0; i < rtlpci->rxringcount; i++) { 1327 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1328 1329 if (!skb) 1330 continue; 1331 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 1332 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 1333 kfree_skb(skb); 1334 } 1335 1336 /* free dma of this ring */ 1337 if (rtlpriv->use_new_trx_flow) { 1338 dma_free_coherent(&rtlpci->pdev->dev, 1339 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1340 rtlpci->rxringcount, 1341 rtlpci->rx_ring[rxring_idx].buffer_desc, 1342 rtlpci->rx_ring[rxring_idx].dma); 1343 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1344 } else { 1345 dma_free_coherent(&rtlpci->pdev->dev, 1346 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1347 rtlpci->rxringcount, 1348 rtlpci->rx_ring[rxring_idx].desc, 1349 rtlpci->rx_ring[rxring_idx].dma); 1350 rtlpci->rx_ring[rxring_idx].desc = NULL; 1351 } 1352 } 1353 1354 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1355 { 1356 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1357 int ret; 1358 int i, rxring_idx; 1359 1360 /* rxring_idx 0:RX_MPDU_QUEUE 1361 * rxring_idx 1:RX_CMD_QUEUE 1362 */ 1363 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1364 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1365 if (ret) 1366 return ret; 1367 } 1368 1369 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1370 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1371 if (ret) 1372 goto err_free_rings; 1373 } 1374 1375 return 0; 1376 1377 err_free_rings: 1378 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1379 _rtl_pci_free_rx_ring(hw, rxring_idx); 1380 1381 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1382 if (rtlpci->tx_ring[i].desc || 1383 rtlpci->tx_ring[i].buffer_desc) 1384 _rtl_pci_free_tx_ring(hw, i); 1385 1386 return 1; 1387 } 1388 1389 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1390 { 1391 u32 i, rxring_idx; 1392 1393 /*free rx rings */ 1394 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1395 _rtl_pci_free_rx_ring(hw, rxring_idx); 1396 1397 /*free tx rings */ 1398 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1399 _rtl_pci_free_tx_ring(hw, i); 1400 1401 return 0; 1402 } 1403 1404 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1405 { 1406 struct rtl_priv *rtlpriv = rtl_priv(hw); 1407 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1408 int i, rxring_idx; 1409 unsigned long flags; 1410 u8 tmp_one = 1; 1411 u32 bufferaddress; 1412 /* rxring_idx 0:RX_MPDU_QUEUE */ 1413 /* rxring_idx 1:RX_CMD_QUEUE */ 1414 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1415 /* force the rx_ring[RX_MPDU_QUEUE/ 1416 * RX_CMD_QUEUE].idx to the first one 1417 *new trx flow, do nothing 1418 */ 1419 if (!rtlpriv->use_new_trx_flow && 1420 rtlpci->rx_ring[rxring_idx].desc) { 1421 struct rtl_rx_desc *entry = NULL; 1422 1423 rtlpci->rx_ring[rxring_idx].idx = 0; 1424 for (i = 0; i < rtlpci->rxringcount; i++) { 1425 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1426 bufferaddress = 1427 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1428 false, HW_DESC_RXBUFF_ADDR); 1429 memset((u8 *)entry, 0, 1430 sizeof(*rtlpci->rx_ring 1431 [rxring_idx].desc));/*clear one entry*/ 1432 if (rtlpriv->use_new_trx_flow) { 1433 rtlpriv->cfg->ops->set_desc(hw, 1434 (u8 *)entry, false, 1435 HW_DESC_RX_PREPARE, 1436 (u8 *)&bufferaddress); 1437 } else { 1438 rtlpriv->cfg->ops->set_desc(hw, 1439 (u8 *)entry, false, 1440 HW_DESC_RXBUFF_ADDR, 1441 (u8 *)&bufferaddress); 1442 rtlpriv->cfg->ops->set_desc(hw, 1443 (u8 *)entry, false, 1444 HW_DESC_RXPKT_LEN, 1445 (u8 *)&rtlpci->rxbuffersize); 1446 rtlpriv->cfg->ops->set_desc(hw, 1447 (u8 *)entry, false, 1448 HW_DESC_RXOWN, 1449 (u8 *)&tmp_one); 1450 } 1451 } 1452 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1453 HW_DESC_RXERO, (u8 *)&tmp_one); 1454 } 1455 rtlpci->rx_ring[rxring_idx].idx = 0; 1456 } 1457 1458 /*after reset, release previous pending packet, 1459 *and force the tx idx to the first one 1460 */ 1461 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1462 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1463 if (rtlpci->tx_ring[i].desc || 1464 rtlpci->tx_ring[i].buffer_desc) { 1465 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1466 1467 while (skb_queue_len(&ring->queue)) { 1468 u8 *entry; 1469 struct sk_buff *skb = 1470 __skb_dequeue(&ring->queue); 1471 if (rtlpriv->use_new_trx_flow) 1472 entry = (u8 *)(&ring->buffer_desc 1473 [ring->idx]); 1474 else 1475 entry = (u8 *)(&ring->desc[ring->idx]); 1476 1477 dma_unmap_single(&rtlpci->pdev->dev, 1478 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1479 true, HW_DESC_TXBUFF_ADDR), 1480 skb->len, DMA_TO_DEVICE); 1481 dev_kfree_skb_irq(skb); 1482 ring->idx = (ring->idx + 1) % ring->entries; 1483 } 1484 1485 if (rtlpriv->use_new_trx_flow) { 1486 rtlpci->tx_ring[i].cur_tx_rp = 0; 1487 rtlpci->tx_ring[i].cur_tx_wp = 0; 1488 } 1489 1490 ring->idx = 0; 1491 ring->entries = rtlpci->txringcount[i]; 1492 } 1493 } 1494 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1495 1496 return 0; 1497 } 1498 1499 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1500 struct ieee80211_sta *sta, 1501 struct sk_buff *skb) 1502 { 1503 struct rtl_priv *rtlpriv = rtl_priv(hw); 1504 struct rtl_sta_info *sta_entry = NULL; 1505 u8 tid = rtl_get_tid(skb); 1506 __le16 fc = rtl_get_fc(skb); 1507 1508 if (!sta) 1509 return false; 1510 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1511 1512 if (!rtlpriv->rtlhal.earlymode_enable) 1513 return false; 1514 if (ieee80211_is_nullfunc(fc)) 1515 return false; 1516 if (ieee80211_is_qos_nullfunc(fc)) 1517 return false; 1518 if (ieee80211_is_pspoll(fc)) 1519 return false; 1520 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1521 return false; 1522 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1523 return false; 1524 if (tid > 7) 1525 return false; 1526 1527 /* maybe every tid should be checked */ 1528 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1529 return false; 1530 1531 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1532 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1533 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1534 1535 return true; 1536 } 1537 1538 static int rtl_pci_tx(struct ieee80211_hw *hw, 1539 struct ieee80211_sta *sta, 1540 struct sk_buff *skb, 1541 struct rtl_tcb_desc *ptcb_desc) 1542 { 1543 struct rtl_priv *rtlpriv = rtl_priv(hw); 1544 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1545 struct rtl8192_tx_ring *ring; 1546 struct rtl_tx_desc *pdesc; 1547 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1548 u16 idx; 1549 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1550 unsigned long flags; 1551 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1552 __le16 fc = rtl_get_fc(skb); 1553 u8 *pda_addr = hdr->addr1; 1554 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1555 u8 own; 1556 u8 temp_one = 1; 1557 1558 if (ieee80211_is_mgmt(fc)) 1559 rtl_tx_mgmt_proc(hw, skb); 1560 1561 if (rtlpriv->psc.sw_ps_enabled) { 1562 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1563 !ieee80211_has_pm(fc)) 1564 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1565 } 1566 1567 rtl_action_proc(hw, skb, true); 1568 1569 if (is_multicast_ether_addr(pda_addr)) 1570 rtlpriv->stats.txbytesmulticast += skb->len; 1571 else if (is_broadcast_ether_addr(pda_addr)) 1572 rtlpriv->stats.txbytesbroadcast += skb->len; 1573 else 1574 rtlpriv->stats.txbytesunicast += skb->len; 1575 1576 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1577 ring = &rtlpci->tx_ring[hw_queue]; 1578 if (hw_queue != BEACON_QUEUE) { 1579 if (rtlpriv->use_new_trx_flow) 1580 idx = ring->cur_tx_wp; 1581 else 1582 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1583 ring->entries; 1584 } else { 1585 idx = 0; 1586 } 1587 1588 pdesc = &ring->desc[idx]; 1589 if (rtlpriv->use_new_trx_flow) { 1590 ptx_bd_desc = &ring->buffer_desc[idx]; 1591 } else { 1592 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1593 true, HW_DESC_OWN); 1594 1595 if (own == 1 && hw_queue != BEACON_QUEUE) { 1596 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1597 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1598 hw_queue, ring->idx, idx, 1599 skb_queue_len(&ring->queue)); 1600 1601 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1602 flags); 1603 return skb->len; 1604 } 1605 } 1606 1607 if (rtlpriv->cfg->ops->get_available_desc && 1608 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1609 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1610 "get_available_desc fail\n"); 1611 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1612 return skb->len; 1613 } 1614 1615 if (ieee80211_is_data(fc)) 1616 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1617 1618 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1619 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1620 1621 __skb_queue_tail(&ring->queue, skb); 1622 1623 if (rtlpriv->use_new_trx_flow) { 1624 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1625 HW_DESC_OWN, &hw_queue); 1626 } else { 1627 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1628 HW_DESC_OWN, &temp_one); 1629 } 1630 1631 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1632 hw_queue != BEACON_QUEUE) { 1633 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1634 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1635 hw_queue, ring->idx, idx, 1636 skb_queue_len(&ring->queue)); 1637 1638 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1639 } 1640 1641 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1642 1643 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1644 1645 return 0; 1646 } 1647 1648 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1649 { 1650 struct rtl_priv *rtlpriv = rtl_priv(hw); 1651 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1652 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1653 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1654 u16 i = 0; 1655 int queue_id; 1656 struct rtl8192_tx_ring *ring; 1657 1658 if (mac->skip_scan) 1659 return; 1660 1661 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1662 u32 queue_len; 1663 1664 if (((queues >> queue_id) & 0x1) == 0) { 1665 queue_id--; 1666 continue; 1667 } 1668 ring = &pcipriv->dev.tx_ring[queue_id]; 1669 queue_len = skb_queue_len(&ring->queue); 1670 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1671 queue_id == TXCMD_QUEUE) { 1672 queue_id--; 1673 continue; 1674 } else { 1675 msleep(20); 1676 i++; 1677 } 1678 1679 /* we just wait 1s for all queues */ 1680 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1681 is_hal_stop(rtlhal) || i >= 200) 1682 return; 1683 } 1684 } 1685 1686 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1687 { 1688 struct rtl_priv *rtlpriv = rtl_priv(hw); 1689 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1690 1691 _rtl_pci_deinit_trx_ring(hw); 1692 1693 synchronize_irq(rtlpci->pdev->irq); 1694 tasklet_kill(&rtlpriv->works.irq_tasklet); 1695 tasklet_kill(&rtlpriv->works.irq_prepare_bcn_tasklet); 1696 cancel_work_sync(&rtlpriv->works.lps_change_work); 1697 } 1698 1699 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1700 { 1701 int err; 1702 1703 _rtl_pci_init_struct(hw, pdev); 1704 1705 err = _rtl_pci_init_trx_ring(hw); 1706 if (err) { 1707 pr_err("tx ring initialization failed\n"); 1708 return err; 1709 } 1710 1711 return 0; 1712 } 1713 1714 static int rtl_pci_start(struct ieee80211_hw *hw) 1715 { 1716 struct rtl_priv *rtlpriv = rtl_priv(hw); 1717 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1718 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1719 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1720 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1721 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1722 1723 int err; 1724 1725 rtl_pci_reset_trx_ring(hw); 1726 1727 rtlpci->driver_is_goingto_unload = false; 1728 if (rtlpriv->cfg->ops->get_btc_status && 1729 rtlpriv->cfg->ops->get_btc_status()) { 1730 rtlpriv->btcoexist.btc_info.ap_num = 36; 1731 btc_ops->btc_init_variables(rtlpriv); 1732 btc_ops->btc_init_hal_vars(rtlpriv); 1733 } else if (btc_ops) { 1734 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1735 } 1736 1737 err = rtlpriv->cfg->ops->hw_init(hw); 1738 if (err) { 1739 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1740 "Failed to config hardware!\n"); 1741 kfree(rtlpriv->btcoexist.btc_context); 1742 kfree(rtlpriv->btcoexist.wifi_only_context); 1743 return err; 1744 } 1745 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1746 &rtlmac->retry_long); 1747 1748 rtlpriv->cfg->ops->enable_interrupt(hw); 1749 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1750 1751 rtl_init_rx_config(hw); 1752 1753 /*should be after adapter start and interrupt enable. */ 1754 set_hal_start(rtlhal); 1755 1756 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1757 1758 rtlpci->up_first_time = false; 1759 1760 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1761 return 0; 1762 } 1763 1764 static void rtl_pci_stop(struct ieee80211_hw *hw) 1765 { 1766 struct rtl_priv *rtlpriv = rtl_priv(hw); 1767 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1768 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1769 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1770 unsigned long flags; 1771 u8 rf_timeout = 0; 1772 1773 if (rtlpriv->cfg->ops->get_btc_status()) 1774 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1775 1776 if (rtlpriv->btcoexist.btc_ops) 1777 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1778 1779 /*should be before disable interrupt&adapter 1780 *and will do it immediately. 1781 */ 1782 set_hal_stop(rtlhal); 1783 1784 rtlpci->driver_is_goingto_unload = true; 1785 rtlpriv->cfg->ops->disable_interrupt(hw); 1786 cancel_work_sync(&rtlpriv->works.lps_change_work); 1787 1788 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1789 while (ppsc->rfchange_inprogress) { 1790 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1791 if (rf_timeout > 100) { 1792 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1793 break; 1794 } 1795 mdelay(1); 1796 rf_timeout++; 1797 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1798 } 1799 ppsc->rfchange_inprogress = true; 1800 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1801 1802 rtlpriv->cfg->ops->hw_disable(hw); 1803 /* some things are not needed if firmware not available */ 1804 if (!rtlpriv->max_fw_size) 1805 return; 1806 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1807 1808 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1809 ppsc->rfchange_inprogress = false; 1810 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1811 1812 rtl_pci_enable_aspm(hw); 1813 } 1814 1815 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1816 struct ieee80211_hw *hw) 1817 { 1818 struct rtl_priv *rtlpriv = rtl_priv(hw); 1819 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1820 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1821 struct pci_dev *bridge_pdev = pdev->bus->self; 1822 u16 venderid; 1823 u16 deviceid; 1824 u8 revisionid; 1825 u16 irqline; 1826 u8 tmp; 1827 1828 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1829 venderid = pdev->vendor; 1830 deviceid = pdev->device; 1831 pci_read_config_byte(pdev, 0x8, &revisionid); 1832 pci_read_config_word(pdev, 0x3C, &irqline); 1833 1834 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1835 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1836 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1837 * the correct driver is r8192e_pci, thus this routine should 1838 * return false. 1839 */ 1840 if (deviceid == RTL_PCI_8192SE_DID && 1841 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1842 return false; 1843 1844 if (deviceid == RTL_PCI_8192_DID || 1845 deviceid == RTL_PCI_0044_DID || 1846 deviceid == RTL_PCI_0047_DID || 1847 deviceid == RTL_PCI_8192SE_DID || 1848 deviceid == RTL_PCI_8174_DID || 1849 deviceid == RTL_PCI_8173_DID || 1850 deviceid == RTL_PCI_8172_DID || 1851 deviceid == RTL_PCI_8171_DID) { 1852 switch (revisionid) { 1853 case RTL_PCI_REVISION_ID_8192PCIE: 1854 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1855 "8192 PCI-E is found - vid/did=%x/%x\n", 1856 venderid, deviceid); 1857 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1858 return false; 1859 case RTL_PCI_REVISION_ID_8192SE: 1860 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1861 "8192SE is found - vid/did=%x/%x\n", 1862 venderid, deviceid); 1863 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1864 break; 1865 default: 1866 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1867 "Err: Unknown device - vid/did=%x/%x\n", 1868 venderid, deviceid); 1869 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1870 break; 1871 } 1872 } else if (deviceid == RTL_PCI_8723AE_DID) { 1873 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1874 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1875 "8723AE PCI-E is found - vid/did=%x/%x\n", 1876 venderid, deviceid); 1877 } else if (deviceid == RTL_PCI_8192CET_DID || 1878 deviceid == RTL_PCI_8192CE_DID || 1879 deviceid == RTL_PCI_8191CE_DID || 1880 deviceid == RTL_PCI_8188CE_DID) { 1881 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1882 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1883 "8192C PCI-E is found - vid/did=%x/%x\n", 1884 venderid, deviceid); 1885 } else if (deviceid == RTL_PCI_8192DE_DID || 1886 deviceid == RTL_PCI_8192DE_DID2) { 1887 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1888 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1889 "8192D PCI-E is found - vid/did=%x/%x\n", 1890 venderid, deviceid); 1891 } else if (deviceid == RTL_PCI_8188EE_DID) { 1892 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1893 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1894 "Find adapter, Hardware type is 8188EE\n"); 1895 } else if (deviceid == RTL_PCI_8723BE_DID) { 1896 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1897 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1898 "Find adapter, Hardware type is 8723BE\n"); 1899 } else if (deviceid == RTL_PCI_8192EE_DID) { 1900 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1901 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1902 "Find adapter, Hardware type is 8192EE\n"); 1903 } else if (deviceid == RTL_PCI_8821AE_DID) { 1904 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1905 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1906 "Find adapter, Hardware type is 8821AE\n"); 1907 } else if (deviceid == RTL_PCI_8812AE_DID) { 1908 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1909 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1910 "Find adapter, Hardware type is 8812AE\n"); 1911 } else if (deviceid == RTL_PCI_8822BE_DID) { 1912 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1913 rtlhal->bandset = BAND_ON_BOTH; 1914 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1915 "Find adapter, Hardware type is 8822BE\n"); 1916 } else { 1917 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1918 "Err: Unknown device - vid/did=%x/%x\n", 1919 venderid, deviceid); 1920 1921 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1922 } 1923 1924 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1925 if (revisionid == 0 || revisionid == 1) { 1926 if (revisionid == 0) { 1927 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1928 "Find 92DE MAC0\n"); 1929 rtlhal->interfaceindex = 0; 1930 } else if (revisionid == 1) { 1931 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1932 "Find 92DE MAC1\n"); 1933 rtlhal->interfaceindex = 1; 1934 } 1935 } else { 1936 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1937 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 1938 venderid, deviceid, revisionid); 1939 rtlhal->interfaceindex = 0; 1940 } 1941 } 1942 1943 switch (rtlhal->hw_type) { 1944 case HARDWARE_TYPE_RTL8192EE: 1945 case HARDWARE_TYPE_RTL8822BE: 1946 /* use new trx flow */ 1947 rtlpriv->use_new_trx_flow = true; 1948 break; 1949 1950 default: 1951 rtlpriv->use_new_trx_flow = false; 1952 break; 1953 } 1954 1955 /*find bus info */ 1956 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 1957 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 1958 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 1959 1960 /*find bridge info */ 1961 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1962 /* some ARM have no bridge_pdev and will crash here 1963 * so we should check if bridge_pdev is NULL 1964 */ 1965 if (bridge_pdev) { 1966 /*find bridge info if available */ 1967 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 1968 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 1969 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 1970 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1971 "Pci Bridge Vendor is found index: %d\n", 1972 tmp); 1973 break; 1974 } 1975 } 1976 } 1977 1978 if (pcipriv->ndis_adapter.pcibridge_vendor != 1979 PCI_BRIDGE_VENDOR_UNKNOWN) { 1980 pcipriv->ndis_adapter.pcibridge_busnum = 1981 bridge_pdev->bus->number; 1982 pcipriv->ndis_adapter.pcibridge_devnum = 1983 PCI_SLOT(bridge_pdev->devfn); 1984 pcipriv->ndis_adapter.pcibridge_funcnum = 1985 PCI_FUNC(bridge_pdev->devfn); 1986 1987 if (pcipriv->ndis_adapter.pcibridge_vendor == 1988 PCI_BRIDGE_VENDOR_AMD) { 1989 pcipriv->ndis_adapter.amd_l1_patch = 1990 rtl_pci_get_amd_l1_patch(hw); 1991 } 1992 } 1993 1994 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1995 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 1996 pcipriv->ndis_adapter.busnumber, 1997 pcipriv->ndis_adapter.devnumber, 1998 pcipriv->ndis_adapter.funcnumber, 1999 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2000 2001 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2002 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n", 2003 pcipriv->ndis_adapter.pcibridge_busnum, 2004 pcipriv->ndis_adapter.pcibridge_devnum, 2005 pcipriv->ndis_adapter.pcibridge_funcnum, 2006 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2007 pcipriv->ndis_adapter.amd_l1_patch); 2008 2009 rtl_pci_parse_configuration(pdev, hw); 2010 2011 return true; 2012 } 2013 2014 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2015 { 2016 struct rtl_priv *rtlpriv = rtl_priv(hw); 2017 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2018 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2019 int ret; 2020 2021 ret = pci_enable_msi(rtlpci->pdev); 2022 if (ret < 0) 2023 return ret; 2024 2025 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2026 IRQF_SHARED, KBUILD_MODNAME, hw); 2027 if (ret < 0) { 2028 pci_disable_msi(rtlpci->pdev); 2029 return ret; 2030 } 2031 2032 rtlpci->using_msi = true; 2033 2034 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2035 "MSI Interrupt Mode!\n"); 2036 return 0; 2037 } 2038 2039 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2040 { 2041 struct rtl_priv *rtlpriv = rtl_priv(hw); 2042 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2043 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2044 int ret; 2045 2046 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2047 IRQF_SHARED, KBUILD_MODNAME, hw); 2048 if (ret < 0) 2049 return ret; 2050 2051 rtlpci->using_msi = false; 2052 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2053 "Pin-based Interrupt Mode!\n"); 2054 return 0; 2055 } 2056 2057 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2058 { 2059 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2060 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2061 int ret; 2062 2063 if (rtlpci->msi_support) { 2064 ret = rtl_pci_intr_mode_msi(hw); 2065 if (ret < 0) 2066 ret = rtl_pci_intr_mode_legacy(hw); 2067 } else { 2068 ret = rtl_pci_intr_mode_legacy(hw); 2069 } 2070 return ret; 2071 } 2072 2073 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2074 { 2075 u8 value; 2076 2077 pci_read_config_byte(pdev, 0x719, &value); 2078 2079 /* 0x719 Bit5 is DMA64 bit fetch. */ 2080 if (dma64) 2081 value |= BIT(5); 2082 else 2083 value &= ~BIT(5); 2084 2085 pci_write_config_byte(pdev, 0x719, value); 2086 } 2087 2088 int rtl_pci_probe(struct pci_dev *pdev, 2089 const struct pci_device_id *id) 2090 { 2091 struct ieee80211_hw *hw = NULL; 2092 2093 struct rtl_priv *rtlpriv = NULL; 2094 struct rtl_pci_priv *pcipriv = NULL; 2095 struct rtl_pci *rtlpci; 2096 unsigned long pmem_start, pmem_len, pmem_flags; 2097 int err; 2098 2099 err = pci_enable_device(pdev); 2100 if (err) { 2101 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2102 pci_name(pdev)); 2103 return err; 2104 } 2105 2106 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2107 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2108 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2109 WARN_ONCE(true, 2110 "Unable to obtain 64bit DMA for consistent allocations\n"); 2111 err = -ENOMEM; 2112 goto fail1; 2113 } 2114 2115 platform_enable_dma64(pdev, true); 2116 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2117 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2118 WARN_ONCE(true, 2119 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2120 err = -ENOMEM; 2121 goto fail1; 2122 } 2123 2124 platform_enable_dma64(pdev, false); 2125 } 2126 2127 pci_set_master(pdev); 2128 2129 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2130 sizeof(struct rtl_priv), &rtl_ops); 2131 if (!hw) { 2132 WARN_ONCE(true, 2133 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2134 err = -ENOMEM; 2135 goto fail1; 2136 } 2137 2138 SET_IEEE80211_DEV(hw, &pdev->dev); 2139 pci_set_drvdata(pdev, hw); 2140 2141 rtlpriv = hw->priv; 2142 rtlpriv->hw = hw; 2143 pcipriv = (void *)rtlpriv->priv; 2144 pcipriv->dev.pdev = pdev; 2145 init_completion(&rtlpriv->firmware_loading_complete); 2146 /*proximity init here*/ 2147 rtlpriv->proximity.proxim_on = false; 2148 2149 pcipriv = (void *)rtlpriv->priv; 2150 pcipriv->dev.pdev = pdev; 2151 2152 /* init cfg & intf_ops */ 2153 rtlpriv->rtlhal.interface = INTF_PCI; 2154 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2155 rtlpriv->intf_ops = &rtl_pci_ops; 2156 rtl_efuse_ops_init(hw); 2157 2158 /* MEM map */ 2159 err = pci_request_regions(pdev, KBUILD_MODNAME); 2160 if (err) { 2161 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2162 goto fail1; 2163 } 2164 2165 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2166 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2167 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2168 2169 /*shared mem start */ 2170 rtlpriv->io.pci_mem_start = 2171 (unsigned long)pci_iomap(pdev, 2172 rtlpriv->cfg->bar_id, pmem_len); 2173 if (rtlpriv->io.pci_mem_start == 0) { 2174 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2175 err = -ENOMEM; 2176 goto fail2; 2177 } 2178 2179 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2180 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2181 pmem_start, pmem_len, pmem_flags, 2182 rtlpriv->io.pci_mem_start); 2183 2184 /* Disable Clk Request */ 2185 pci_write_config_byte(pdev, 0x81, 0); 2186 /* leave D3 mode */ 2187 pci_write_config_byte(pdev, 0x44, 0); 2188 pci_write_config_byte(pdev, 0x04, 0x06); 2189 pci_write_config_byte(pdev, 0x04, 0x07); 2190 2191 /* find adapter */ 2192 if (!_rtl_pci_find_adapter(pdev, hw)) { 2193 err = -ENODEV; 2194 goto fail2; 2195 } 2196 2197 /* Init IO handler */ 2198 _rtl_pci_io_handler_init(&pdev->dev, hw); 2199 2200 /*like read eeprom and so on */ 2201 rtlpriv->cfg->ops->read_eeprom_info(hw); 2202 2203 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2204 pr_err("Can't init_sw_vars\n"); 2205 err = -ENODEV; 2206 goto fail2; 2207 } 2208 rtl_init_sw_leds(hw); 2209 2210 /*aspm */ 2211 rtl_pci_init_aspm(hw); 2212 2213 /* Init mac80211 sw */ 2214 err = rtl_init_core(hw); 2215 if (err) { 2216 pr_err("Can't allocate sw for mac80211\n"); 2217 goto fail3; 2218 } 2219 2220 /* Init PCI sw */ 2221 err = rtl_pci_init(hw, pdev); 2222 if (err) { 2223 pr_err("Failed to init PCI\n"); 2224 goto fail4; 2225 } 2226 2227 err = ieee80211_register_hw(hw); 2228 if (err) { 2229 pr_err("Can't register mac80211 hw.\n"); 2230 err = -ENODEV; 2231 goto fail5; 2232 } 2233 rtlpriv->mac80211.mac80211_registered = 1; 2234 2235 /* add for debug */ 2236 rtl_debug_add_one(hw); 2237 2238 /*init rfkill */ 2239 rtl_init_rfkill(hw); /* Init PCI sw */ 2240 2241 rtlpci = rtl_pcidev(pcipriv); 2242 err = rtl_pci_intr_mode_decide(hw); 2243 if (err) { 2244 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2245 "%s: failed to register IRQ handler\n", 2246 wiphy_name(hw->wiphy)); 2247 goto fail6; 2248 } 2249 rtlpci->irq_alloc = 1; 2250 2251 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2252 return 0; 2253 2254 fail6: 2255 rtl_deinit_rfkill(hw); 2256 rtl_debug_remove_one(hw); 2257 ieee80211_unregister_hw(hw); 2258 fail5: 2259 rtl_pci_deinit(hw); 2260 fail4: 2261 rtl_deinit_core(hw); 2262 fail3: 2263 wait_for_completion(&rtlpriv->firmware_loading_complete); 2264 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2265 2266 fail2: 2267 if (rtlpriv->io.pci_mem_start != 0) 2268 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2269 2270 pci_release_regions(pdev); 2271 2272 fail1: 2273 if (hw) 2274 ieee80211_free_hw(hw); 2275 pci_disable_device(pdev); 2276 2277 return err; 2278 } 2279 EXPORT_SYMBOL(rtl_pci_probe); 2280 2281 void rtl_pci_disconnect(struct pci_dev *pdev) 2282 { 2283 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2284 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2285 struct rtl_priv *rtlpriv = rtl_priv(hw); 2286 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2287 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2288 2289 /* just in case driver is removed before firmware callback */ 2290 wait_for_completion(&rtlpriv->firmware_loading_complete); 2291 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2292 2293 /* remove form debug */ 2294 rtl_debug_remove_one(hw); 2295 2296 /*ieee80211_unregister_hw will call ops_stop */ 2297 if (rtlmac->mac80211_registered == 1) { 2298 ieee80211_unregister_hw(hw); 2299 rtlmac->mac80211_registered = 0; 2300 } else { 2301 rtl_deinit_deferred_work(hw, false); 2302 rtlpriv->intf_ops->adapter_stop(hw); 2303 } 2304 rtlpriv->cfg->ops->disable_interrupt(hw); 2305 2306 /*deinit rfkill */ 2307 rtl_deinit_rfkill(hw); 2308 2309 rtl_pci_deinit(hw); 2310 rtl_deinit_core(hw); 2311 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2312 2313 if (rtlpci->irq_alloc) { 2314 free_irq(rtlpci->pdev->irq, hw); 2315 rtlpci->irq_alloc = 0; 2316 } 2317 2318 if (rtlpci->using_msi) 2319 pci_disable_msi(rtlpci->pdev); 2320 2321 if (rtlpriv->io.pci_mem_start != 0) { 2322 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2323 pci_release_regions(pdev); 2324 } 2325 2326 pci_disable_device(pdev); 2327 2328 rtl_pci_disable_aspm(hw); 2329 2330 pci_set_drvdata(pdev, NULL); 2331 2332 ieee80211_free_hw(hw); 2333 } 2334 EXPORT_SYMBOL(rtl_pci_disconnect); 2335 2336 #ifdef CONFIG_PM_SLEEP 2337 /*************************************** 2338 * kernel pci power state define: 2339 * PCI_D0 ((pci_power_t __force) 0) 2340 * PCI_D1 ((pci_power_t __force) 1) 2341 * PCI_D2 ((pci_power_t __force) 2) 2342 * PCI_D3hot ((pci_power_t __force) 3) 2343 * PCI_D3cold ((pci_power_t __force) 4) 2344 * PCI_UNKNOWN ((pci_power_t __force) 5) 2345 2346 * This function is called when system 2347 * goes into suspend state mac80211 will 2348 * call rtl_mac_stop() from the mac80211 2349 * suspend function first, So there is 2350 * no need to call hw_disable here. 2351 ****************************************/ 2352 int rtl_pci_suspend(struct device *dev) 2353 { 2354 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2355 struct rtl_priv *rtlpriv = rtl_priv(hw); 2356 2357 rtlpriv->cfg->ops->hw_suspend(hw); 2358 rtl_deinit_rfkill(hw); 2359 2360 return 0; 2361 } 2362 EXPORT_SYMBOL(rtl_pci_suspend); 2363 2364 int rtl_pci_resume(struct device *dev) 2365 { 2366 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2367 struct rtl_priv *rtlpriv = rtl_priv(hw); 2368 2369 rtlpriv->cfg->ops->hw_resume(hw); 2370 rtl_init_rfkill(hw); 2371 return 0; 2372 } 2373 EXPORT_SYMBOL(rtl_pci_resume); 2374 #endif /* CONFIG_PM_SLEEP */ 2375 2376 const struct rtl_intf_ops rtl_pci_ops = { 2377 .adapter_start = rtl_pci_start, 2378 .adapter_stop = rtl_pci_stop, 2379 .adapter_tx = rtl_pci_tx, 2380 .flush = rtl_pci_flush, 2381 .reset_trx_ring = rtl_pci_reset_trx_ring, 2382 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2383 2384 .disable_aspm = rtl_pci_disable_aspm, 2385 .enable_aspm = rtl_pci_enable_aspm, 2386 }; 2387