1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "wifi.h" 5 #include "core.h" 6 #include "pci.h" 7 #include "base.h" 8 #include "ps.h" 9 #include "efuse.h" 10 #include <linux/interrupt.h> 11 #include <linux/export.h> 12 #include <linux/module.h> 13 14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 17 MODULE_LICENSE("GPL"); 18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 19 20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 21 INTEL_VENDOR_ID, 22 ATI_VENDOR_ID, 23 AMD_VENDOR_ID, 24 SIS_VENDOR_ID 25 }; 26 27 static const u8 ac_to_hwq[] = { 28 VO_QUEUE, 29 VI_QUEUE, 30 BE_QUEUE, 31 BK_QUEUE 32 }; 33 34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 35 { 36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 37 __le16 fc = rtl_get_fc(skb); 38 u8 queue_index = skb_get_queue_mapping(skb); 39 struct ieee80211_hdr *hdr; 40 41 if (unlikely(ieee80211_is_beacon(fc))) 42 return BEACON_QUEUE; 43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 44 return MGNT_QUEUE; 45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 46 if (ieee80211_is_nullfunc(fc)) 47 return HIGH_QUEUE; 48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 49 hdr = rtl_get_hdr(skb); 50 51 if (is_multicast_ether_addr(hdr->addr1) || 52 is_broadcast_ether_addr(hdr->addr1)) 53 return HIGH_QUEUE; 54 } 55 56 return ac_to_hwq[queue_index]; 57 } 58 59 /* Update PCI dependent default settings*/ 60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 61 { 62 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 67 u16 init_aspm; 68 69 ppsc->reg_rfps_level = 0; 70 ppsc->support_aspm = false; 71 72 /*Update PCI ASPM setting */ 73 switch (rtlpci->const_pci_aspm) { 74 case 0: 75 /*No ASPM */ 76 break; 77 78 case 1: 79 /*ASPM dynamically enabled/disable. */ 80 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 81 break; 82 83 case 2: 84 /*ASPM with Clock Req dynamically enabled/disable. */ 85 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 86 RT_RF_OFF_LEVL_CLK_REQ); 87 break; 88 89 case 3: 90 /* Always enable ASPM and Clock Req 91 * from initialization to halt. 92 */ 93 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 94 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 95 RT_RF_OFF_LEVL_CLK_REQ); 96 break; 97 98 case 4: 99 /* Always enable ASPM without Clock Req 100 * from initialization to halt. 101 */ 102 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 103 RT_RF_OFF_LEVL_CLK_REQ); 104 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 105 break; 106 } 107 108 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 109 110 /*Update Radio OFF setting */ 111 switch (rtlpci->const_hwsw_rfoff_d3) { 112 case 1: 113 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 114 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 115 break; 116 117 case 2: 118 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 119 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 121 break; 122 123 case 3: 124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 125 break; 126 } 127 128 /*Set HW definition to determine if it supports ASPM. */ 129 switch (rtlpci->const_support_pciaspm) { 130 case 0: 131 /*Not support ASPM. */ 132 ppsc->support_aspm = false; 133 break; 134 case 1: 135 /*Support ASPM. */ 136 ppsc->support_aspm = true; 137 ppsc->support_backdoor = true; 138 break; 139 case 2: 140 /*ASPM value set by chipset. */ 141 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 142 ppsc->support_aspm = true; 143 break; 144 default: 145 pr_err("switch case %#x not processed\n", 146 rtlpci->const_support_pciaspm); 147 break; 148 } 149 150 /* toshiba aspm issue, toshiba will set aspm selfly 151 * so we should not set aspm in driver 152 */ 153 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &init_aspm); 154 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 155 ((u8)init_aspm) == (PCI_EXP_LNKCTL_ASPM_L0S | 156 PCI_EXP_LNKCTL_ASPM_L1 | PCI_EXP_LNKCTL_CCC)) 157 ppsc->support_aspm = false; 158 } 159 160 static bool _rtl_pci_platform_switch_device_pci_aspm( 161 struct ieee80211_hw *hw, 162 u8 value) 163 { 164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 166 167 value &= PCI_EXP_LNKCTL_ASPMC; 168 169 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 170 value |= PCI_EXP_LNKCTL_CCC; 171 172 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 173 PCI_EXP_LNKCTL_ASPMC | value, 174 value); 175 176 return false; 177 } 178 179 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */ 180 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value) 181 { 182 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 183 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 184 185 value &= PCI_EXP_LNKCTL_CLKREQ_EN; 186 187 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 188 PCI_EXP_LNKCTL_CLKREQ_EN, 189 value); 190 191 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 192 udelay(100); 193 } 194 195 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 196 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 197 { 198 struct rtl_priv *rtlpriv = rtl_priv(hw); 199 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 200 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 202 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 203 /*Retrieve original configuration settings. */ 204 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 205 u16 aspmlevel = 0; 206 u16 tmp_u1b = 0; 207 208 if (!ppsc->support_aspm) 209 return; 210 211 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 212 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 213 "PCI(Bridge) UNKNOWN\n"); 214 215 return; 216 } 217 218 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 219 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 220 _rtl_pci_switch_clk_req(hw, 0x0); 221 } 222 223 /*for promising device will in L0 state after an I/O. */ 224 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &tmp_u1b); 225 226 /*Set corresponding value. */ 227 aspmlevel |= PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1; 228 linkctrl_reg &= ~aspmlevel; 229 230 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 231 } 232 233 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 234 *power saving We should follow the sequence to enable 235 *RTL8192SE first then enable Pci Bridge ASPM 236 *or the system will show bluescreen. 237 */ 238 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 239 { 240 struct rtl_priv *rtlpriv = rtl_priv(hw); 241 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 242 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 244 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 245 u16 aspmlevel; 246 u8 u_device_aspmsetting; 247 248 if (!ppsc->support_aspm) 249 return; 250 251 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 252 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 253 "PCI(Bridge) UNKNOWN\n"); 254 return; 255 } 256 257 /*Get ASPM level (with/without Clock Req) */ 258 aspmlevel = rtlpci->const_devicepci_aspm_setting; 259 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 260 261 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 262 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 263 264 u_device_aspmsetting |= aspmlevel; 265 266 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 267 268 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 269 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 270 RT_RF_OFF_LEVL_CLK_REQ) ? 271 PCI_EXP_LNKCTL_CLKREQ_EN : 0); 272 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 273 } 274 udelay(100); 275 } 276 277 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 278 { 279 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 280 281 bool status = false; 282 u8 offset_e0; 283 unsigned int offset_e4; 284 285 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 286 287 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 288 289 if (offset_e0 == 0xA0) { 290 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 291 if (offset_e4 & BIT(23)) 292 status = true; 293 } 294 295 return status; 296 } 297 298 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 299 struct ieee80211_hw *hw) 300 { 301 struct rtl_priv *rtlpriv = rtl_priv(hw); 302 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 303 304 u8 tmp; 305 u16 linkctrl_reg; 306 307 /*Link Control Register */ 308 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 309 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 310 311 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 312 pcipriv->ndis_adapter.linkctrl_reg); 313 314 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 315 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 316 317 tmp = 0x17; 318 pci_write_config_byte(pdev, 0x70f, tmp); 319 } 320 321 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 322 { 323 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 324 325 _rtl_pci_update_default_setting(hw); 326 327 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 328 /*Always enable ASPM & Clock Req. */ 329 rtl_pci_enable_aspm(hw); 330 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 331 } 332 } 333 334 static void _rtl_pci_io_handler_init(struct device *dev, 335 struct ieee80211_hw *hw) 336 { 337 struct rtl_priv *rtlpriv = rtl_priv(hw); 338 339 rtlpriv->io.dev = dev; 340 341 rtlpriv->io.write8 = pci_write8_async; 342 rtlpriv->io.write16 = pci_write16_async; 343 rtlpriv->io.write32 = pci_write32_async; 344 345 rtlpriv->io.read8 = pci_read8_sync; 346 rtlpriv->io.read16 = pci_read16_sync; 347 rtlpriv->io.read32 = pci_read32_sync; 348 } 349 350 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 351 struct sk_buff *skb, 352 struct rtl_tcb_desc *tcb_desc, u8 tid) 353 { 354 struct rtl_priv *rtlpriv = rtl_priv(hw); 355 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 356 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 357 struct sk_buff *next_skb; 358 u8 additionlen = FCS_LEN; 359 360 /* here open is 4, wep/tkip is 8, aes is 12*/ 361 if (info->control.hw_key) 362 additionlen += info->control.hw_key->icv_len; 363 364 /* The most skb num is 6 */ 365 tcb_desc->empkt_num = 0; 366 spin_lock_bh(&rtlpriv->locks.waitq_lock); 367 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 368 struct ieee80211_tx_info *next_info; 369 370 next_info = IEEE80211_SKB_CB(next_skb); 371 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 372 tcb_desc->empkt_len[tcb_desc->empkt_num] = 373 next_skb->len + additionlen; 374 tcb_desc->empkt_num++; 375 } else { 376 break; 377 } 378 379 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 380 next_skb)) 381 break; 382 383 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 384 break; 385 } 386 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 387 388 return true; 389 } 390 391 /* just for early mode now */ 392 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 393 { 394 struct rtl_priv *rtlpriv = rtl_priv(hw); 395 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 396 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 397 struct sk_buff *skb = NULL; 398 struct ieee80211_tx_info *info = NULL; 399 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 400 int tid; 401 402 if (!rtlpriv->rtlhal.earlymode_enable) 403 return; 404 405 /* we just use em for BE/BK/VI/VO */ 406 for (tid = 7; tid >= 0; tid--) { 407 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 408 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 409 410 while (!mac->act_scanning && 411 rtlpriv->psc.rfpwr_state == ERFON) { 412 struct rtl_tcb_desc tcb_desc; 413 414 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 415 416 spin_lock(&rtlpriv->locks.waitq_lock); 417 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 418 (ring->entries - skb_queue_len(&ring->queue) > 419 rtlhal->max_earlymode_num)) { 420 skb = skb_dequeue(&mac->skb_waitq[tid]); 421 } else { 422 spin_unlock(&rtlpriv->locks.waitq_lock); 423 break; 424 } 425 spin_unlock(&rtlpriv->locks.waitq_lock); 426 427 /* Some macaddr can't do early mode. like 428 * multicast/broadcast/no_qos data 429 */ 430 info = IEEE80211_SKB_CB(skb); 431 if (info->flags & IEEE80211_TX_CTL_AMPDU) 432 _rtl_update_earlymode_info(hw, skb, 433 &tcb_desc, tid); 434 435 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 436 } 437 } 438 } 439 440 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 441 { 442 struct rtl_priv *rtlpriv = rtl_priv(hw); 443 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 444 445 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 446 447 while (skb_queue_len(&ring->queue)) { 448 struct sk_buff *skb; 449 struct ieee80211_tx_info *info; 450 __le16 fc; 451 u8 tid; 452 u8 *entry; 453 454 if (rtlpriv->use_new_trx_flow) 455 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 456 else 457 entry = (u8 *)(&ring->desc[ring->idx]); 458 459 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 460 return; 461 ring->idx = (ring->idx + 1) % ring->entries; 462 463 skb = __skb_dequeue(&ring->queue); 464 dma_unmap_single(&rtlpci->pdev->dev, 465 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 466 true, HW_DESC_TXBUFF_ADDR), 467 skb->len, DMA_TO_DEVICE); 468 469 /* remove early mode header */ 470 if (rtlpriv->rtlhal.earlymode_enable) 471 skb_pull(skb, EM_HDR_LEN); 472 473 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 474 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 475 ring->idx, 476 skb_queue_len(&ring->queue), 477 *(u16 *)(skb->data + 22)); 478 479 if (prio == TXCMD_QUEUE) { 480 dev_kfree_skb(skb); 481 goto tx_status_ok; 482 } 483 484 /* for sw LPS, just after NULL skb send out, we can 485 * sure AP knows we are sleeping, we should not let 486 * rf sleep 487 */ 488 fc = rtl_get_fc(skb); 489 if (ieee80211_is_nullfunc(fc)) { 490 if (ieee80211_has_pm(fc)) { 491 rtlpriv->mac80211.offchan_delay = true; 492 rtlpriv->psc.state_inap = true; 493 } else { 494 rtlpriv->psc.state_inap = false; 495 } 496 } 497 if (ieee80211_is_action(fc)) { 498 struct ieee80211_mgmt *action_frame = 499 (struct ieee80211_mgmt *)skb->data; 500 if (action_frame->u.action.u.ht_smps.action == 501 WLAN_HT_ACTION_SMPS) { 502 dev_kfree_skb(skb); 503 goto tx_status_ok; 504 } 505 } 506 507 /* update tid tx pkt num */ 508 tid = rtl_get_tid(skb); 509 if (tid <= 7) 510 rtlpriv->link_info.tidtx_inperiod[tid]++; 511 512 info = IEEE80211_SKB_CB(skb); 513 514 if (likely(!ieee80211_is_nullfunc(fc))) { 515 ieee80211_tx_info_clear_status(info); 516 info->flags |= IEEE80211_TX_STAT_ACK; 517 /*info->status.rates[0].count = 1; */ 518 ieee80211_tx_status_irqsafe(hw, skb); 519 } else { 520 rtl_tx_ackqueue(hw, skb); 521 } 522 523 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 524 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, 525 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 526 prio, ring->idx, 527 skb_queue_len(&ring->queue)); 528 529 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 530 } 531 tx_status_ok: 532 skb = NULL; 533 } 534 535 if (((rtlpriv->link_info.num_rx_inperiod + 536 rtlpriv->link_info.num_tx_inperiod) > 8) || 537 rtlpriv->link_info.num_rx_inperiod > 2) 538 rtl_lps_leave(hw, false); 539 } 540 541 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 542 struct sk_buff *new_skb, u8 *entry, 543 int rxring_idx, int desc_idx) 544 { 545 struct rtl_priv *rtlpriv = rtl_priv(hw); 546 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 547 u32 bufferaddress; 548 u8 tmp_one = 1; 549 struct sk_buff *skb; 550 551 if (likely(new_skb)) { 552 skb = new_skb; 553 goto remap; 554 } 555 skb = dev_alloc_skb(rtlpci->rxbuffersize); 556 if (!skb) 557 return 0; 558 559 remap: 560 /* just set skb->cb to mapping addr for pci_unmap_single use */ 561 *((dma_addr_t *)skb->cb) = 562 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb), 563 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 564 bufferaddress = *((dma_addr_t *)skb->cb); 565 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress)) 566 return 0; 567 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 568 if (rtlpriv->use_new_trx_flow) { 569 /* skb->cb may be 64 bit address */ 570 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 571 HW_DESC_RX_PREPARE, 572 (u8 *)(dma_addr_t *)skb->cb); 573 } else { 574 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 575 HW_DESC_RXBUFF_ADDR, 576 (u8 *)&bufferaddress); 577 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 578 HW_DESC_RXPKT_LEN, 579 (u8 *)&rtlpci->rxbuffersize); 580 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 581 HW_DESC_RXOWN, 582 (u8 *)&tmp_one); 583 } 584 return 1; 585 } 586 587 /* inorder to receive 8K AMSDU we have set skb to 588 * 9100bytes in init rx ring, but if this packet is 589 * not a AMSDU, this large packet will be sent to 590 * TCP/IP directly, this cause big packet ping fail 591 * like: "ping -s 65507", so here we will realloc skb 592 * based on the true size of packet, Mac80211 593 * Probably will do it better, but does not yet. 594 * 595 * Some platform will fail when alloc skb sometimes. 596 * in this condition, we will send the old skb to 597 * mac80211 directly, this will not cause any other 598 * issues, but only this packet will be lost by TCP/IP 599 */ 600 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 601 struct sk_buff *skb, 602 struct ieee80211_rx_status rx_status) 603 { 604 if (unlikely(!rtl_action_proc(hw, skb, false))) { 605 dev_kfree_skb_any(skb); 606 } else { 607 struct sk_buff *uskb = NULL; 608 609 uskb = dev_alloc_skb(skb->len + 128); 610 if (likely(uskb)) { 611 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 612 sizeof(rx_status)); 613 skb_put_data(uskb, skb->data, skb->len); 614 dev_kfree_skb_any(skb); 615 ieee80211_rx_irqsafe(hw, uskb); 616 } else { 617 ieee80211_rx_irqsafe(hw, skb); 618 } 619 } 620 } 621 622 /*hsisr interrupt handler*/ 623 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 624 { 625 struct rtl_priv *rtlpriv = rtl_priv(hw); 626 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 627 628 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 629 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 630 rtlpci->sys_irq_mask); 631 } 632 633 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 634 { 635 struct rtl_priv *rtlpriv = rtl_priv(hw); 636 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 637 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 638 struct ieee80211_rx_status rx_status = { 0 }; 639 unsigned int count = rtlpci->rxringcount; 640 u8 own; 641 u8 tmp_one; 642 bool unicast = false; 643 u8 hw_queue = 0; 644 unsigned int rx_remained_cnt = 0; 645 struct rtl_stats stats = { 646 .signal = 0, 647 .rate = 0, 648 }; 649 650 /*RX NORMAL PKT */ 651 while (count--) { 652 struct ieee80211_hdr *hdr; 653 __le16 fc; 654 u16 len; 655 /*rx buffer descriptor */ 656 struct rtl_rx_buffer_desc *buffer_desc = NULL; 657 /*if use new trx flow, it means wifi info */ 658 struct rtl_rx_desc *pdesc = NULL; 659 /*rx pkt */ 660 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 661 rtlpci->rx_ring[rxring_idx].idx]; 662 struct sk_buff *new_skb; 663 664 if (rtlpriv->use_new_trx_flow) { 665 if (rx_remained_cnt == 0) 666 rx_remained_cnt = 667 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 668 hw_queue); 669 if (rx_remained_cnt == 0) 670 return; 671 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 672 rtlpci->rx_ring[rxring_idx].idx]; 673 pdesc = (struct rtl_rx_desc *)skb->data; 674 } else { /* rx descriptor */ 675 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 676 rtlpci->rx_ring[rxring_idx].idx]; 677 678 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 679 false, 680 HW_DESC_OWN); 681 if (own) /* wait data to be filled by hardware */ 682 return; 683 } 684 685 /* Reaching this point means: data is filled already 686 * AAAAAAttention !!! 687 * We can NOT access 'skb' before 'pci_unmap_single' 688 */ 689 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 690 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 691 692 /* get a new skb - if fail, old one will be reused */ 693 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 694 if (unlikely(!new_skb)) 695 goto no_new; 696 memset(&rx_status, 0, sizeof(rx_status)); 697 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 698 &rx_status, (u8 *)pdesc, skb); 699 700 if (rtlpriv->use_new_trx_flow) 701 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 702 (u8 *)buffer_desc, 703 hw_queue); 704 705 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 706 HW_DESC_RXPKT_LEN); 707 708 if (skb->end - skb->tail > len) { 709 skb_put(skb, len); 710 if (rtlpriv->use_new_trx_flow) 711 skb_reserve(skb, stats.rx_drvinfo_size + 712 stats.rx_bufshift + 24); 713 else 714 skb_reserve(skb, stats.rx_drvinfo_size + 715 stats.rx_bufshift); 716 } else { 717 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 718 "skb->end - skb->tail = %d, len is %d\n", 719 skb->end - skb->tail, len); 720 dev_kfree_skb_any(skb); 721 goto new_trx_end; 722 } 723 /* handle command packet here */ 724 if (stats.packet_report_type == C2H_PACKET) { 725 rtl_c2hcmd_enqueue(hw, skb); 726 goto new_trx_end; 727 } 728 729 /* NOTICE This can not be use for mac80211, 730 * this is done in mac80211 code, 731 * if done here sec DHCP will fail 732 * skb_trim(skb, skb->len - 4); 733 */ 734 735 hdr = rtl_get_hdr(skb); 736 fc = rtl_get_fc(skb); 737 738 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) { 739 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 740 sizeof(rx_status)); 741 742 if (is_broadcast_ether_addr(hdr->addr1)) { 743 ;/*TODO*/ 744 } else if (is_multicast_ether_addr(hdr->addr1)) { 745 ;/*TODO*/ 746 } else { 747 unicast = true; 748 rtlpriv->stats.rxbytesunicast += skb->len; 749 } 750 rtl_is_special_data(hw, skb, false, true); 751 752 if (ieee80211_is_data(fc)) { 753 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 754 if (unicast) 755 rtlpriv->link_info.num_rx_inperiod++; 756 } 757 758 rtl_collect_scan_list(hw, skb); 759 760 /* static bcn for roaming */ 761 rtl_beacon_statistic(hw, skb); 762 rtl_p2p_info(hw, (void *)skb->data, skb->len); 763 /* for sw lps */ 764 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 765 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 766 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 767 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 768 (ieee80211_is_beacon(fc) || 769 ieee80211_is_probe_resp(fc))) { 770 dev_kfree_skb_any(skb); 771 } else { 772 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 773 } 774 } else { 775 /* drop packets with errors or those too short */ 776 dev_kfree_skb_any(skb); 777 } 778 new_trx_end: 779 if (rtlpriv->use_new_trx_flow) { 780 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 781 rtlpci->rx_ring[hw_queue].next_rx_rp %= 782 RTL_PCI_MAX_RX_COUNT; 783 784 rx_remained_cnt--; 785 rtl_write_word(rtlpriv, 0x3B4, 786 rtlpci->rx_ring[hw_queue].next_rx_rp); 787 } 788 if (((rtlpriv->link_info.num_rx_inperiod + 789 rtlpriv->link_info.num_tx_inperiod) > 8) || 790 rtlpriv->link_info.num_rx_inperiod > 2) 791 rtl_lps_leave(hw, false); 792 skb = new_skb; 793 no_new: 794 if (rtlpriv->use_new_trx_flow) { 795 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 796 rxring_idx, 797 rtlpci->rx_ring[rxring_idx].idx); 798 } else { 799 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 800 rxring_idx, 801 rtlpci->rx_ring[rxring_idx].idx); 802 if (rtlpci->rx_ring[rxring_idx].idx == 803 rtlpci->rxringcount - 1) 804 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 805 false, 806 HW_DESC_RXERO, 807 (u8 *)&tmp_one); 808 } 809 rtlpci->rx_ring[rxring_idx].idx = 810 (rtlpci->rx_ring[rxring_idx].idx + 1) % 811 rtlpci->rxringcount; 812 } 813 } 814 815 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 816 { 817 struct ieee80211_hw *hw = dev_id; 818 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 819 struct rtl_priv *rtlpriv = rtl_priv(hw); 820 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 821 unsigned long flags; 822 struct rtl_int intvec = {0}; 823 824 irqreturn_t ret = IRQ_HANDLED; 825 826 if (rtlpci->irq_enabled == 0) 827 return ret; 828 829 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 830 rtlpriv->cfg->ops->disable_interrupt(hw); 831 832 /*read ISR: 4/8bytes */ 833 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 834 835 /*Shared IRQ or HW disappeared */ 836 if (!intvec.inta || intvec.inta == 0xffff) 837 goto done; 838 839 /*<1> beacon related */ 840 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 841 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 842 "beacon ok interrupt!\n"); 843 844 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 845 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 846 "beacon err interrupt!\n"); 847 848 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 849 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 850 851 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 852 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 853 "prepare beacon for interrupt!\n"); 854 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 855 } 856 857 /*<2> Tx related */ 858 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 859 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 860 861 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 862 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 863 "Manage ok interrupt!\n"); 864 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 865 } 866 867 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 868 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 869 "HIGH_QUEUE ok interrupt!\n"); 870 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 871 } 872 873 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 874 rtlpriv->link_info.num_tx_inperiod++; 875 876 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 877 "BK Tx OK interrupt!\n"); 878 _rtl_pci_tx_isr(hw, BK_QUEUE); 879 } 880 881 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 882 rtlpriv->link_info.num_tx_inperiod++; 883 884 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 885 "BE TX OK interrupt!\n"); 886 _rtl_pci_tx_isr(hw, BE_QUEUE); 887 } 888 889 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 890 rtlpriv->link_info.num_tx_inperiod++; 891 892 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 893 "VI TX OK interrupt!\n"); 894 _rtl_pci_tx_isr(hw, VI_QUEUE); 895 } 896 897 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 898 rtlpriv->link_info.num_tx_inperiod++; 899 900 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 901 "Vo TX OK interrupt!\n"); 902 _rtl_pci_tx_isr(hw, VO_QUEUE); 903 } 904 905 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 906 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 907 rtlpriv->link_info.num_tx_inperiod++; 908 909 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 910 "H2C TX OK interrupt!\n"); 911 _rtl_pci_tx_isr(hw, H2C_QUEUE); 912 } 913 } 914 915 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 916 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 917 rtlpriv->link_info.num_tx_inperiod++; 918 919 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 920 "CMD TX OK interrupt!\n"); 921 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 922 } 923 } 924 925 /*<3> Rx related */ 926 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 927 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 928 _rtl_pci_rx_interrupt(hw); 929 } 930 931 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 932 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 933 "rx descriptor unavailable!\n"); 934 _rtl_pci_rx_interrupt(hw); 935 } 936 937 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 938 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 939 _rtl_pci_rx_interrupt(hw); 940 } 941 942 /*<4> fw related*/ 943 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 944 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 945 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 946 "firmware interrupt!\n"); 947 queue_delayed_work(rtlpriv->works.rtl_wq, 948 &rtlpriv->works.fwevt_wq, 0); 949 } 950 } 951 952 /*<5> hsisr related*/ 953 /* Only 8188EE & 8723BE Supported. 954 * If Other ICs Come in, System will corrupt, 955 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 956 * are not initialized 957 */ 958 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 959 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 960 if (unlikely(intvec.inta & 961 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 962 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 963 "hsisr interrupt!\n"); 964 _rtl_pci_hs_interrupt(hw); 965 } 966 } 967 968 if (rtlpriv->rtlhal.earlymode_enable) 969 tasklet_schedule(&rtlpriv->works.irq_tasklet); 970 971 done: 972 rtlpriv->cfg->ops->enable_interrupt(hw); 973 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 974 return ret; 975 } 976 977 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t) 978 { 979 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet); 980 struct ieee80211_hw *hw = rtlpriv->hw; 981 _rtl_pci_tx_chk_waitq(hw); 982 } 983 984 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t) 985 { 986 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, 987 works.irq_prepare_bcn_tasklet); 988 struct ieee80211_hw *hw = rtlpriv->hw; 989 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 990 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 991 struct rtl8192_tx_ring *ring = NULL; 992 struct ieee80211_hdr *hdr = NULL; 993 struct ieee80211_tx_info *info = NULL; 994 struct sk_buff *pskb = NULL; 995 struct rtl_tx_desc *pdesc = NULL; 996 struct rtl_tcb_desc tcb_desc; 997 /*This is for new trx flow*/ 998 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 999 u8 temp_one = 1; 1000 u8 *entry; 1001 1002 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1003 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1004 pskb = __skb_dequeue(&ring->queue); 1005 if (rtlpriv->use_new_trx_flow) 1006 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1007 else 1008 entry = (u8 *)(&ring->desc[ring->idx]); 1009 if (pskb) { 1010 dma_unmap_single(&rtlpci->pdev->dev, 1011 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1012 true, HW_DESC_TXBUFF_ADDR), 1013 pskb->len, DMA_TO_DEVICE); 1014 kfree_skb(pskb); 1015 } 1016 1017 /*NB: the beacon data buffer must be 32-bit aligned. */ 1018 pskb = ieee80211_beacon_get(hw, mac->vif, 0); 1019 if (!pskb) 1020 return; 1021 hdr = rtl_get_hdr(pskb); 1022 info = IEEE80211_SKB_CB(pskb); 1023 pdesc = &ring->desc[0]; 1024 if (rtlpriv->use_new_trx_flow) 1025 pbuffer_desc = &ring->buffer_desc[0]; 1026 1027 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1028 (u8 *)pbuffer_desc, info, NULL, pskb, 1029 BEACON_QUEUE, &tcb_desc); 1030 1031 __skb_queue_tail(&ring->queue, pskb); 1032 1033 if (rtlpriv->use_new_trx_flow) { 1034 temp_one = 4; 1035 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1036 HW_DESC_OWN, (u8 *)&temp_one); 1037 } else { 1038 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1039 &temp_one); 1040 } 1041 } 1042 1043 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1044 { 1045 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1046 struct rtl_priv *rtlpriv = rtl_priv(hw); 1047 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1048 u8 i; 1049 u16 desc_num; 1050 1051 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1052 desc_num = TX_DESC_NUM_92E; 1053 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1054 desc_num = TX_DESC_NUM_8822B; 1055 else 1056 desc_num = RT_TXDESC_NUM; 1057 1058 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1059 rtlpci->txringcount[i] = desc_num; 1060 1061 /*we just alloc 2 desc for beacon queue, 1062 *because we just need first desc in hw beacon. 1063 */ 1064 rtlpci->txringcount[BEACON_QUEUE] = 2; 1065 1066 /*BE queue need more descriptor for performance 1067 *consideration or, No more tx desc will happen, 1068 *and may cause mac80211 mem leakage. 1069 */ 1070 if (!rtl_priv(hw)->use_new_trx_flow) 1071 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1072 1073 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1074 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1075 } 1076 1077 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1078 struct pci_dev *pdev) 1079 { 1080 struct rtl_priv *rtlpriv = rtl_priv(hw); 1081 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1082 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1083 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1084 1085 rtlpci->up_first_time = true; 1086 rtlpci->being_init_adapter = false; 1087 1088 rtlhal->hw = hw; 1089 rtlpci->pdev = pdev; 1090 1091 /*Tx/Rx related var */ 1092 _rtl_pci_init_trx_var(hw); 1093 1094 /*IBSS*/ 1095 mac->beacon_interval = 100; 1096 1097 /*AMPDU*/ 1098 mac->min_space_cfg = 0; 1099 mac->max_mss_density = 0; 1100 /*set sane AMPDU defaults */ 1101 mac->current_ampdu_density = 7; 1102 mac->current_ampdu_factor = 3; 1103 1104 /*Retry Limit*/ 1105 mac->retry_short = 7; 1106 mac->retry_long = 7; 1107 1108 /*QOS*/ 1109 rtlpci->acm_method = EACMWAY2_SW; 1110 1111 /*task */ 1112 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet); 1113 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet, 1114 _rtl_pci_prepare_bcn_tasklet); 1115 INIT_WORK(&rtlpriv->works.lps_change_work, 1116 rtl_lps_change_work_callback); 1117 } 1118 1119 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1120 unsigned int prio, unsigned int entries) 1121 { 1122 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1123 struct rtl_priv *rtlpriv = rtl_priv(hw); 1124 struct rtl_tx_buffer_desc *buffer_desc; 1125 struct rtl_tx_desc *desc; 1126 dma_addr_t buffer_desc_dma, desc_dma; 1127 u32 nextdescaddress; 1128 int i; 1129 1130 /* alloc tx buffer desc for new trx flow*/ 1131 if (rtlpriv->use_new_trx_flow) { 1132 buffer_desc = 1133 dma_alloc_coherent(&rtlpci->pdev->dev, 1134 sizeof(*buffer_desc) * entries, 1135 &buffer_desc_dma, GFP_KERNEL); 1136 1137 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1138 pr_err("Cannot allocate TX ring (prio = %d)\n", 1139 prio); 1140 return -ENOMEM; 1141 } 1142 1143 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1144 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1145 1146 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1147 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1148 } 1149 1150 /* alloc dma for this ring */ 1151 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries, 1152 &desc_dma, GFP_KERNEL); 1153 1154 if (!desc || (unsigned long)desc & 0xFF) { 1155 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1156 return -ENOMEM; 1157 } 1158 1159 rtlpci->tx_ring[prio].desc = desc; 1160 rtlpci->tx_ring[prio].dma = desc_dma; 1161 1162 rtlpci->tx_ring[prio].idx = 0; 1163 rtlpci->tx_ring[prio].entries = entries; 1164 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1165 1166 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1167 prio, desc); 1168 1169 /* init every desc in this ring */ 1170 if (!rtlpriv->use_new_trx_flow) { 1171 for (i = 0; i < entries; i++) { 1172 nextdescaddress = (u32)desc_dma + 1173 ((i + 1) % entries) * 1174 sizeof(*desc); 1175 1176 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1177 true, 1178 HW_DESC_TX_NEXTDESC_ADDR, 1179 (u8 *)&nextdescaddress); 1180 } 1181 } 1182 return 0; 1183 } 1184 1185 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1186 { 1187 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1188 struct rtl_priv *rtlpriv = rtl_priv(hw); 1189 int i; 1190 1191 if (rtlpriv->use_new_trx_flow) { 1192 struct rtl_rx_buffer_desc *entry = NULL; 1193 /* alloc dma for this ring */ 1194 rtlpci->rx_ring[rxring_idx].buffer_desc = 1195 dma_alloc_coherent(&rtlpci->pdev->dev, 1196 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1197 rtlpci->rxringcount, 1198 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1199 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1200 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1201 pr_err("Cannot allocate RX ring\n"); 1202 return -ENOMEM; 1203 } 1204 1205 /* init every desc in this ring */ 1206 rtlpci->rx_ring[rxring_idx].idx = 0; 1207 for (i = 0; i < rtlpci->rxringcount; i++) { 1208 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1209 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1210 rxring_idx, i)) 1211 return -ENOMEM; 1212 } 1213 } else { 1214 struct rtl_rx_desc *entry = NULL; 1215 u8 tmp_one = 1; 1216 /* alloc dma for this ring */ 1217 rtlpci->rx_ring[rxring_idx].desc = 1218 dma_alloc_coherent(&rtlpci->pdev->dev, 1219 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1220 rtlpci->rxringcount, 1221 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1222 if (!rtlpci->rx_ring[rxring_idx].desc || 1223 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1224 pr_err("Cannot allocate RX ring\n"); 1225 return -ENOMEM; 1226 } 1227 1228 /* init every desc in this ring */ 1229 rtlpci->rx_ring[rxring_idx].idx = 0; 1230 1231 for (i = 0; i < rtlpci->rxringcount; i++) { 1232 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1233 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1234 rxring_idx, i)) 1235 return -ENOMEM; 1236 } 1237 1238 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1239 HW_DESC_RXERO, &tmp_one); 1240 } 1241 return 0; 1242 } 1243 1244 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1245 unsigned int prio) 1246 { 1247 struct rtl_priv *rtlpriv = rtl_priv(hw); 1248 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1249 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1250 1251 /* free every desc in this ring */ 1252 while (skb_queue_len(&ring->queue)) { 1253 u8 *entry; 1254 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1255 1256 if (rtlpriv->use_new_trx_flow) 1257 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1258 else 1259 entry = (u8 *)(&ring->desc[ring->idx]); 1260 1261 dma_unmap_single(&rtlpci->pdev->dev, 1262 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1263 true, HW_DESC_TXBUFF_ADDR), 1264 skb->len, DMA_TO_DEVICE); 1265 kfree_skb(skb); 1266 ring->idx = (ring->idx + 1) % ring->entries; 1267 } 1268 1269 /* free dma of this ring */ 1270 dma_free_coherent(&rtlpci->pdev->dev, 1271 sizeof(*ring->desc) * ring->entries, ring->desc, 1272 ring->dma); 1273 ring->desc = NULL; 1274 if (rtlpriv->use_new_trx_flow) { 1275 dma_free_coherent(&rtlpci->pdev->dev, 1276 sizeof(*ring->buffer_desc) * ring->entries, 1277 ring->buffer_desc, ring->buffer_desc_dma); 1278 ring->buffer_desc = NULL; 1279 } 1280 } 1281 1282 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1283 { 1284 struct rtl_priv *rtlpriv = rtl_priv(hw); 1285 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1286 int i; 1287 1288 /* free every desc in this ring */ 1289 for (i = 0; i < rtlpci->rxringcount; i++) { 1290 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1291 1292 if (!skb) 1293 continue; 1294 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 1295 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 1296 kfree_skb(skb); 1297 } 1298 1299 /* free dma of this ring */ 1300 if (rtlpriv->use_new_trx_flow) { 1301 dma_free_coherent(&rtlpci->pdev->dev, 1302 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1303 rtlpci->rxringcount, 1304 rtlpci->rx_ring[rxring_idx].buffer_desc, 1305 rtlpci->rx_ring[rxring_idx].dma); 1306 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1307 } else { 1308 dma_free_coherent(&rtlpci->pdev->dev, 1309 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1310 rtlpci->rxringcount, 1311 rtlpci->rx_ring[rxring_idx].desc, 1312 rtlpci->rx_ring[rxring_idx].dma); 1313 rtlpci->rx_ring[rxring_idx].desc = NULL; 1314 } 1315 } 1316 1317 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1318 { 1319 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1320 int ret; 1321 int i, rxring_idx; 1322 1323 /* rxring_idx 0:RX_MPDU_QUEUE 1324 * rxring_idx 1:RX_CMD_QUEUE 1325 */ 1326 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1327 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1328 if (ret) 1329 return ret; 1330 } 1331 1332 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1333 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1334 if (ret) 1335 goto err_free_rings; 1336 } 1337 1338 return 0; 1339 1340 err_free_rings: 1341 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1342 _rtl_pci_free_rx_ring(hw, rxring_idx); 1343 1344 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1345 if (rtlpci->tx_ring[i].desc || 1346 rtlpci->tx_ring[i].buffer_desc) 1347 _rtl_pci_free_tx_ring(hw, i); 1348 1349 return 1; 1350 } 1351 1352 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1353 { 1354 u32 i, rxring_idx; 1355 1356 /*free rx rings */ 1357 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1358 _rtl_pci_free_rx_ring(hw, rxring_idx); 1359 1360 /*free tx rings */ 1361 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1362 _rtl_pci_free_tx_ring(hw, i); 1363 1364 return 0; 1365 } 1366 1367 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1368 { 1369 struct rtl_priv *rtlpriv = rtl_priv(hw); 1370 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1371 int i, rxring_idx; 1372 unsigned long flags; 1373 u8 tmp_one = 1; 1374 u32 bufferaddress; 1375 /* rxring_idx 0:RX_MPDU_QUEUE */ 1376 /* rxring_idx 1:RX_CMD_QUEUE */ 1377 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1378 /* force the rx_ring[RX_MPDU_QUEUE/ 1379 * RX_CMD_QUEUE].idx to the first one 1380 *new trx flow, do nothing 1381 */ 1382 if (!rtlpriv->use_new_trx_flow && 1383 rtlpci->rx_ring[rxring_idx].desc) { 1384 struct rtl_rx_desc *entry = NULL; 1385 1386 rtlpci->rx_ring[rxring_idx].idx = 0; 1387 for (i = 0; i < rtlpci->rxringcount; i++) { 1388 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1389 bufferaddress = 1390 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1391 false, HW_DESC_RXBUFF_ADDR); 1392 memset((u8 *)entry, 0, 1393 sizeof(*rtlpci->rx_ring 1394 [rxring_idx].desc));/*clear one entry*/ 1395 if (rtlpriv->use_new_trx_flow) { 1396 rtlpriv->cfg->ops->set_desc(hw, 1397 (u8 *)entry, false, 1398 HW_DESC_RX_PREPARE, 1399 (u8 *)&bufferaddress); 1400 } else { 1401 rtlpriv->cfg->ops->set_desc(hw, 1402 (u8 *)entry, false, 1403 HW_DESC_RXBUFF_ADDR, 1404 (u8 *)&bufferaddress); 1405 rtlpriv->cfg->ops->set_desc(hw, 1406 (u8 *)entry, false, 1407 HW_DESC_RXPKT_LEN, 1408 (u8 *)&rtlpci->rxbuffersize); 1409 rtlpriv->cfg->ops->set_desc(hw, 1410 (u8 *)entry, false, 1411 HW_DESC_RXOWN, 1412 (u8 *)&tmp_one); 1413 } 1414 } 1415 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1416 HW_DESC_RXERO, (u8 *)&tmp_one); 1417 } 1418 rtlpci->rx_ring[rxring_idx].idx = 0; 1419 } 1420 1421 /*after reset, release previous pending packet, 1422 *and force the tx idx to the first one 1423 */ 1424 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1425 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1426 if (rtlpci->tx_ring[i].desc || 1427 rtlpci->tx_ring[i].buffer_desc) { 1428 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1429 1430 while (skb_queue_len(&ring->queue)) { 1431 u8 *entry; 1432 struct sk_buff *skb = 1433 __skb_dequeue(&ring->queue); 1434 if (rtlpriv->use_new_trx_flow) 1435 entry = (u8 *)(&ring->buffer_desc 1436 [ring->idx]); 1437 else 1438 entry = (u8 *)(&ring->desc[ring->idx]); 1439 1440 dma_unmap_single(&rtlpci->pdev->dev, 1441 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1442 true, HW_DESC_TXBUFF_ADDR), 1443 skb->len, DMA_TO_DEVICE); 1444 dev_kfree_skb_irq(skb); 1445 ring->idx = (ring->idx + 1) % ring->entries; 1446 } 1447 1448 if (rtlpriv->use_new_trx_flow) { 1449 rtlpci->tx_ring[i].cur_tx_rp = 0; 1450 rtlpci->tx_ring[i].cur_tx_wp = 0; 1451 } 1452 1453 ring->idx = 0; 1454 ring->entries = rtlpci->txringcount[i]; 1455 } 1456 } 1457 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1458 1459 return 0; 1460 } 1461 1462 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1463 struct ieee80211_sta *sta, 1464 struct sk_buff *skb) 1465 { 1466 struct rtl_priv *rtlpriv = rtl_priv(hw); 1467 struct rtl_sta_info *sta_entry = NULL; 1468 u8 tid = rtl_get_tid(skb); 1469 __le16 fc = rtl_get_fc(skb); 1470 1471 if (!sta) 1472 return false; 1473 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1474 1475 if (!rtlpriv->rtlhal.earlymode_enable) 1476 return false; 1477 if (ieee80211_is_nullfunc(fc)) 1478 return false; 1479 if (ieee80211_is_qos_nullfunc(fc)) 1480 return false; 1481 if (ieee80211_is_pspoll(fc)) 1482 return false; 1483 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1484 return false; 1485 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1486 return false; 1487 if (tid > 7) 1488 return false; 1489 1490 /* maybe every tid should be checked */ 1491 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1492 return false; 1493 1494 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1495 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1496 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1497 1498 return true; 1499 } 1500 1501 static int rtl_pci_tx(struct ieee80211_hw *hw, 1502 struct ieee80211_sta *sta, 1503 struct sk_buff *skb, 1504 struct rtl_tcb_desc *ptcb_desc) 1505 { 1506 struct rtl_priv *rtlpriv = rtl_priv(hw); 1507 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1508 struct rtl8192_tx_ring *ring; 1509 struct rtl_tx_desc *pdesc; 1510 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1511 u16 idx; 1512 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1513 unsigned long flags; 1514 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1515 __le16 fc = rtl_get_fc(skb); 1516 u8 *pda_addr = hdr->addr1; 1517 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1518 u8 own; 1519 u8 temp_one = 1; 1520 1521 if (ieee80211_is_mgmt(fc)) 1522 rtl_tx_mgmt_proc(hw, skb); 1523 1524 if (rtlpriv->psc.sw_ps_enabled) { 1525 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1526 !ieee80211_has_pm(fc)) 1527 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1528 } 1529 1530 rtl_action_proc(hw, skb, true); 1531 1532 if (is_multicast_ether_addr(pda_addr)) 1533 rtlpriv->stats.txbytesmulticast += skb->len; 1534 else if (is_broadcast_ether_addr(pda_addr)) 1535 rtlpriv->stats.txbytesbroadcast += skb->len; 1536 else 1537 rtlpriv->stats.txbytesunicast += skb->len; 1538 1539 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1540 ring = &rtlpci->tx_ring[hw_queue]; 1541 if (hw_queue != BEACON_QUEUE) { 1542 if (rtlpriv->use_new_trx_flow) 1543 idx = ring->cur_tx_wp; 1544 else 1545 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1546 ring->entries; 1547 } else { 1548 idx = 0; 1549 } 1550 1551 pdesc = &ring->desc[idx]; 1552 if (rtlpriv->use_new_trx_flow) { 1553 ptx_bd_desc = &ring->buffer_desc[idx]; 1554 } else { 1555 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1556 true, HW_DESC_OWN); 1557 1558 if (own == 1 && hw_queue != BEACON_QUEUE) { 1559 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1560 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1561 hw_queue, ring->idx, idx, 1562 skb_queue_len(&ring->queue)); 1563 1564 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1565 flags); 1566 return skb->len; 1567 } 1568 } 1569 1570 if (rtlpriv->cfg->ops->get_available_desc && 1571 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1572 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1573 "get_available_desc fail\n"); 1574 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1575 return skb->len; 1576 } 1577 1578 if (ieee80211_is_data(fc)) 1579 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1580 1581 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1582 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1583 1584 __skb_queue_tail(&ring->queue, skb); 1585 1586 if (rtlpriv->use_new_trx_flow) { 1587 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1588 HW_DESC_OWN, &hw_queue); 1589 } else { 1590 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1591 HW_DESC_OWN, &temp_one); 1592 } 1593 1594 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1595 hw_queue != BEACON_QUEUE) { 1596 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1597 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1598 hw_queue, ring->idx, idx, 1599 skb_queue_len(&ring->queue)); 1600 1601 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1602 } 1603 1604 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1605 1606 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1607 1608 return 0; 1609 } 1610 1611 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1612 { 1613 struct rtl_priv *rtlpriv = rtl_priv(hw); 1614 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1615 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1616 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1617 u16 i = 0; 1618 int queue_id; 1619 struct rtl8192_tx_ring *ring; 1620 1621 if (mac->skip_scan) 1622 return; 1623 1624 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1625 u32 queue_len; 1626 1627 if (((queues >> queue_id) & 0x1) == 0) { 1628 queue_id--; 1629 continue; 1630 } 1631 ring = &pcipriv->dev.tx_ring[queue_id]; 1632 queue_len = skb_queue_len(&ring->queue); 1633 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1634 queue_id == TXCMD_QUEUE) { 1635 queue_id--; 1636 continue; 1637 } else { 1638 msleep(20); 1639 i++; 1640 } 1641 1642 /* we just wait 1s for all queues */ 1643 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1644 is_hal_stop(rtlhal) || i >= 200) 1645 return; 1646 } 1647 } 1648 1649 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1650 { 1651 struct rtl_priv *rtlpriv = rtl_priv(hw); 1652 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1653 1654 _rtl_pci_deinit_trx_ring(hw); 1655 1656 synchronize_irq(rtlpci->pdev->irq); 1657 tasklet_kill(&rtlpriv->works.irq_tasklet); 1658 cancel_work_sync(&rtlpriv->works.lps_change_work); 1659 } 1660 1661 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1662 { 1663 int err; 1664 1665 _rtl_pci_init_struct(hw, pdev); 1666 1667 err = _rtl_pci_init_trx_ring(hw); 1668 if (err) { 1669 pr_err("tx ring initialization failed\n"); 1670 return err; 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int rtl_pci_start(struct ieee80211_hw *hw) 1677 { 1678 struct rtl_priv *rtlpriv = rtl_priv(hw); 1679 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1680 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1681 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1682 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1683 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1684 1685 int err; 1686 1687 rtl_pci_reset_trx_ring(hw); 1688 1689 rtlpci->driver_is_goingto_unload = false; 1690 if (rtlpriv->cfg->ops->get_btc_status && 1691 rtlpriv->cfg->ops->get_btc_status()) { 1692 rtlpriv->btcoexist.btc_info.ap_num = 36; 1693 btc_ops->btc_init_variables(rtlpriv); 1694 btc_ops->btc_init_hal_vars(rtlpriv); 1695 } else if (btc_ops) { 1696 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1697 } 1698 1699 err = rtlpriv->cfg->ops->hw_init(hw); 1700 if (err) { 1701 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1702 "Failed to config hardware!\n"); 1703 kfree(rtlpriv->btcoexist.btc_context); 1704 kfree(rtlpriv->btcoexist.wifi_only_context); 1705 return err; 1706 } 1707 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1708 &rtlmac->retry_long); 1709 1710 rtlpriv->cfg->ops->enable_interrupt(hw); 1711 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1712 1713 rtl_init_rx_config(hw); 1714 1715 /*should be after adapter start and interrupt enable. */ 1716 set_hal_start(rtlhal); 1717 1718 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1719 1720 rtlpci->up_first_time = false; 1721 1722 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1723 return 0; 1724 } 1725 1726 static void rtl_pci_stop(struct ieee80211_hw *hw) 1727 { 1728 struct rtl_priv *rtlpriv = rtl_priv(hw); 1729 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1730 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1731 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1732 unsigned long flags; 1733 u8 rf_timeout = 0; 1734 1735 if (rtlpriv->cfg->ops->get_btc_status()) 1736 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1737 1738 if (rtlpriv->btcoexist.btc_ops) 1739 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1740 1741 /*should be before disable interrupt&adapter 1742 *and will do it immediately. 1743 */ 1744 set_hal_stop(rtlhal); 1745 1746 rtlpci->driver_is_goingto_unload = true; 1747 rtlpriv->cfg->ops->disable_interrupt(hw); 1748 cancel_work_sync(&rtlpriv->works.lps_change_work); 1749 1750 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1751 while (ppsc->rfchange_inprogress) { 1752 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1753 if (rf_timeout > 100) { 1754 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1755 break; 1756 } 1757 mdelay(1); 1758 rf_timeout++; 1759 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1760 } 1761 ppsc->rfchange_inprogress = true; 1762 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1763 1764 rtlpriv->cfg->ops->hw_disable(hw); 1765 /* some things are not needed if firmware not available */ 1766 if (!rtlpriv->max_fw_size) 1767 return; 1768 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1769 1770 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1771 ppsc->rfchange_inprogress = false; 1772 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1773 1774 rtl_pci_enable_aspm(hw); 1775 } 1776 1777 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1778 struct ieee80211_hw *hw) 1779 { 1780 struct rtl_priv *rtlpriv = rtl_priv(hw); 1781 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1782 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1783 struct pci_dev *bridge_pdev = pdev->bus->self; 1784 u16 venderid; 1785 u16 deviceid; 1786 u8 revisionid; 1787 u16 irqline; 1788 u8 tmp; 1789 1790 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1791 venderid = pdev->vendor; 1792 deviceid = pdev->device; 1793 pci_read_config_byte(pdev, 0x8, &revisionid); 1794 pci_read_config_word(pdev, 0x3C, &irqline); 1795 1796 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1797 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1798 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1799 * the correct driver is r8192e_pci, thus this routine should 1800 * return false. 1801 */ 1802 if (deviceid == RTL_PCI_8192SE_DID && 1803 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1804 return false; 1805 1806 if (deviceid == RTL_PCI_8192_DID || 1807 deviceid == RTL_PCI_0044_DID || 1808 deviceid == RTL_PCI_0047_DID || 1809 deviceid == RTL_PCI_8192SE_DID || 1810 deviceid == RTL_PCI_8174_DID || 1811 deviceid == RTL_PCI_8173_DID || 1812 deviceid == RTL_PCI_8172_DID || 1813 deviceid == RTL_PCI_8171_DID) { 1814 switch (revisionid) { 1815 case RTL_PCI_REVISION_ID_8192PCIE: 1816 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1817 "8192 PCI-E is found - vid/did=%x/%x\n", 1818 venderid, deviceid); 1819 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1820 return false; 1821 case RTL_PCI_REVISION_ID_8192SE: 1822 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1823 "8192SE is found - vid/did=%x/%x\n", 1824 venderid, deviceid); 1825 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1826 break; 1827 default: 1828 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1829 "Err: Unknown device - vid/did=%x/%x\n", 1830 venderid, deviceid); 1831 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1832 break; 1833 } 1834 } else if (deviceid == RTL_PCI_8723AE_DID) { 1835 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1836 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1837 "8723AE PCI-E is found - vid/did=%x/%x\n", 1838 venderid, deviceid); 1839 } else if (deviceid == RTL_PCI_8192CET_DID || 1840 deviceid == RTL_PCI_8192CE_DID || 1841 deviceid == RTL_PCI_8191CE_DID || 1842 deviceid == RTL_PCI_8188CE_DID) { 1843 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1844 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1845 "8192C PCI-E is found - vid/did=%x/%x\n", 1846 venderid, deviceid); 1847 } else if (deviceid == RTL_PCI_8192DE_DID || 1848 deviceid == RTL_PCI_8192DE_DID2) { 1849 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1850 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1851 "8192D PCI-E is found - vid/did=%x/%x\n", 1852 venderid, deviceid); 1853 } else if (deviceid == RTL_PCI_8188EE_DID) { 1854 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1855 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1856 "Find adapter, Hardware type is 8188EE\n"); 1857 } else if (deviceid == RTL_PCI_8723BE_DID) { 1858 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1859 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1860 "Find adapter, Hardware type is 8723BE\n"); 1861 } else if (deviceid == RTL_PCI_8192EE_DID) { 1862 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1863 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1864 "Find adapter, Hardware type is 8192EE\n"); 1865 } else if (deviceid == RTL_PCI_8821AE_DID) { 1866 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1867 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1868 "Find adapter, Hardware type is 8821AE\n"); 1869 } else if (deviceid == RTL_PCI_8812AE_DID) { 1870 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1871 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1872 "Find adapter, Hardware type is 8812AE\n"); 1873 } else if (deviceid == RTL_PCI_8822BE_DID) { 1874 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1875 rtlhal->bandset = BAND_ON_BOTH; 1876 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1877 "Find adapter, Hardware type is 8822BE\n"); 1878 } else { 1879 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1880 "Err: Unknown device - vid/did=%x/%x\n", 1881 venderid, deviceid); 1882 1883 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1884 } 1885 1886 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1887 if (revisionid == 0 || revisionid == 1) { 1888 if (revisionid == 0) { 1889 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1890 "Find 92DE MAC0\n"); 1891 rtlhal->interfaceindex = 0; 1892 } else if (revisionid == 1) { 1893 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1894 "Find 92DE MAC1\n"); 1895 rtlhal->interfaceindex = 1; 1896 } 1897 } else { 1898 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1899 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 1900 venderid, deviceid, revisionid); 1901 rtlhal->interfaceindex = 0; 1902 } 1903 } 1904 1905 switch (rtlhal->hw_type) { 1906 case HARDWARE_TYPE_RTL8192EE: 1907 case HARDWARE_TYPE_RTL8822BE: 1908 /* use new trx flow */ 1909 rtlpriv->use_new_trx_flow = true; 1910 break; 1911 1912 default: 1913 rtlpriv->use_new_trx_flow = false; 1914 break; 1915 } 1916 1917 /*find bus info */ 1918 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 1919 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 1920 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 1921 1922 /*find bridge info */ 1923 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1924 /* some ARM have no bridge_pdev and will crash here 1925 * so we should check if bridge_pdev is NULL 1926 */ 1927 if (bridge_pdev) { 1928 /*find bridge info if available */ 1929 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 1930 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 1931 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 1932 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1933 "Pci Bridge Vendor is found index: %d\n", 1934 tmp); 1935 break; 1936 } 1937 } 1938 } 1939 1940 if (pcipriv->ndis_adapter.pcibridge_vendor != 1941 PCI_BRIDGE_VENDOR_UNKNOWN) { 1942 pcipriv->ndis_adapter.pcibridge_busnum = 1943 bridge_pdev->bus->number; 1944 pcipriv->ndis_adapter.pcibridge_devnum = 1945 PCI_SLOT(bridge_pdev->devfn); 1946 pcipriv->ndis_adapter.pcibridge_funcnum = 1947 PCI_FUNC(bridge_pdev->devfn); 1948 1949 if (pcipriv->ndis_adapter.pcibridge_vendor == 1950 PCI_BRIDGE_VENDOR_AMD) { 1951 pcipriv->ndis_adapter.amd_l1_patch = 1952 rtl_pci_get_amd_l1_patch(hw); 1953 } 1954 } 1955 1956 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1957 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 1958 pcipriv->ndis_adapter.busnumber, 1959 pcipriv->ndis_adapter.devnumber, 1960 pcipriv->ndis_adapter.funcnumber, 1961 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 1962 1963 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1964 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n", 1965 pcipriv->ndis_adapter.pcibridge_busnum, 1966 pcipriv->ndis_adapter.pcibridge_devnum, 1967 pcipriv->ndis_adapter.pcibridge_funcnum, 1968 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 1969 pcipriv->ndis_adapter.amd_l1_patch); 1970 1971 rtl_pci_parse_configuration(pdev, hw); 1972 1973 return true; 1974 } 1975 1976 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 1977 { 1978 struct rtl_priv *rtlpriv = rtl_priv(hw); 1979 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1980 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 1981 int ret; 1982 1983 ret = pci_enable_msi(rtlpci->pdev); 1984 if (ret < 0) 1985 return ret; 1986 1987 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 1988 IRQF_SHARED, KBUILD_MODNAME, hw); 1989 if (ret < 0) { 1990 pci_disable_msi(rtlpci->pdev); 1991 return ret; 1992 } 1993 1994 rtlpci->using_msi = true; 1995 1996 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 1997 "MSI Interrupt Mode!\n"); 1998 return 0; 1999 } 2000 2001 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2002 { 2003 struct rtl_priv *rtlpriv = rtl_priv(hw); 2004 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2005 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2006 int ret; 2007 2008 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2009 IRQF_SHARED, KBUILD_MODNAME, hw); 2010 if (ret < 0) 2011 return ret; 2012 2013 rtlpci->using_msi = false; 2014 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2015 "Pin-based Interrupt Mode!\n"); 2016 return 0; 2017 } 2018 2019 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2020 { 2021 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2022 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2023 int ret; 2024 2025 if (rtlpci->msi_support) { 2026 ret = rtl_pci_intr_mode_msi(hw); 2027 if (ret < 0) 2028 ret = rtl_pci_intr_mode_legacy(hw); 2029 } else { 2030 ret = rtl_pci_intr_mode_legacy(hw); 2031 } 2032 return ret; 2033 } 2034 2035 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2036 { 2037 u8 value; 2038 2039 pci_read_config_byte(pdev, 0x719, &value); 2040 2041 /* 0x719 Bit5 is DMA64 bit fetch. */ 2042 if (dma64) 2043 value |= BIT(5); 2044 else 2045 value &= ~BIT(5); 2046 2047 pci_write_config_byte(pdev, 0x719, value); 2048 } 2049 2050 int rtl_pci_probe(struct pci_dev *pdev, 2051 const struct pci_device_id *id) 2052 { 2053 struct ieee80211_hw *hw = NULL; 2054 2055 struct rtl_priv *rtlpriv = NULL; 2056 struct rtl_pci_priv *pcipriv = NULL; 2057 struct rtl_pci *rtlpci; 2058 unsigned long pmem_start, pmem_len, pmem_flags; 2059 int err; 2060 2061 err = pci_enable_device(pdev); 2062 if (err) { 2063 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2064 pci_name(pdev)); 2065 return err; 2066 } 2067 2068 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2069 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2070 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2071 WARN_ONCE(true, 2072 "Unable to obtain 64bit DMA for consistent allocations\n"); 2073 err = -ENOMEM; 2074 goto fail1; 2075 } 2076 2077 platform_enable_dma64(pdev, true); 2078 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2079 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2080 WARN_ONCE(true, 2081 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2082 err = -ENOMEM; 2083 goto fail1; 2084 } 2085 2086 platform_enable_dma64(pdev, false); 2087 } 2088 2089 pci_set_master(pdev); 2090 2091 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2092 sizeof(struct rtl_priv), &rtl_ops); 2093 if (!hw) { 2094 WARN_ONCE(true, 2095 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2096 err = -ENOMEM; 2097 goto fail1; 2098 } 2099 2100 SET_IEEE80211_DEV(hw, &pdev->dev); 2101 pci_set_drvdata(pdev, hw); 2102 2103 rtlpriv = hw->priv; 2104 rtlpriv->hw = hw; 2105 pcipriv = (void *)rtlpriv->priv; 2106 pcipriv->dev.pdev = pdev; 2107 init_completion(&rtlpriv->firmware_loading_complete); 2108 /*proximity init here*/ 2109 rtlpriv->proximity.proxim_on = false; 2110 2111 pcipriv = (void *)rtlpriv->priv; 2112 pcipriv->dev.pdev = pdev; 2113 2114 /* init cfg & intf_ops */ 2115 rtlpriv->rtlhal.interface = INTF_PCI; 2116 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2117 rtlpriv->intf_ops = &rtl_pci_ops; 2118 rtl_efuse_ops_init(hw); 2119 2120 /* MEM map */ 2121 err = pci_request_regions(pdev, KBUILD_MODNAME); 2122 if (err) { 2123 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2124 goto fail1; 2125 } 2126 2127 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2128 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2129 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2130 2131 /*shared mem start */ 2132 rtlpriv->io.pci_mem_start = 2133 (unsigned long)pci_iomap(pdev, 2134 rtlpriv->cfg->bar_id, pmem_len); 2135 if (rtlpriv->io.pci_mem_start == 0) { 2136 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2137 err = -ENOMEM; 2138 goto fail2; 2139 } 2140 2141 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2142 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2143 pmem_start, pmem_len, pmem_flags, 2144 rtlpriv->io.pci_mem_start); 2145 2146 /* Disable Clk Request */ 2147 pci_write_config_byte(pdev, 0x81, 0); 2148 /* leave D3 mode */ 2149 pci_write_config_byte(pdev, 0x44, 0); 2150 pci_write_config_byte(pdev, 0x04, 0x06); 2151 pci_write_config_byte(pdev, 0x04, 0x07); 2152 2153 /* find adapter */ 2154 if (!_rtl_pci_find_adapter(pdev, hw)) { 2155 err = -ENODEV; 2156 goto fail2; 2157 } 2158 2159 /* Init IO handler */ 2160 _rtl_pci_io_handler_init(&pdev->dev, hw); 2161 2162 /*like read eeprom and so on */ 2163 rtlpriv->cfg->ops->read_eeprom_info(hw); 2164 2165 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2166 pr_err("Can't init_sw_vars\n"); 2167 err = -ENODEV; 2168 goto fail2; 2169 } 2170 rtl_init_sw_leds(hw); 2171 2172 /*aspm */ 2173 rtl_pci_init_aspm(hw); 2174 2175 /* Init mac80211 sw */ 2176 err = rtl_init_core(hw); 2177 if (err) { 2178 pr_err("Can't allocate sw for mac80211\n"); 2179 goto fail3; 2180 } 2181 2182 /* Init PCI sw */ 2183 err = rtl_pci_init(hw, pdev); 2184 if (err) { 2185 pr_err("Failed to init PCI\n"); 2186 goto fail4; 2187 } 2188 2189 err = ieee80211_register_hw(hw); 2190 if (err) { 2191 pr_err("Can't register mac80211 hw.\n"); 2192 err = -ENODEV; 2193 goto fail5; 2194 } 2195 rtlpriv->mac80211.mac80211_registered = 1; 2196 2197 /* add for debug */ 2198 rtl_debug_add_one(hw); 2199 2200 /*init rfkill */ 2201 rtl_init_rfkill(hw); /* Init PCI sw */ 2202 2203 rtlpci = rtl_pcidev(pcipriv); 2204 err = rtl_pci_intr_mode_decide(hw); 2205 if (err) { 2206 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2207 "%s: failed to register IRQ handler\n", 2208 wiphy_name(hw->wiphy)); 2209 goto fail3; 2210 } 2211 rtlpci->irq_alloc = 1; 2212 2213 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2214 return 0; 2215 2216 fail5: 2217 rtl_pci_deinit(hw); 2218 fail4: 2219 rtl_deinit_core(hw); 2220 fail3: 2221 wait_for_completion(&rtlpriv->firmware_loading_complete); 2222 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2223 2224 fail2: 2225 if (rtlpriv->io.pci_mem_start != 0) 2226 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2227 2228 pci_release_regions(pdev); 2229 2230 fail1: 2231 if (hw) 2232 ieee80211_free_hw(hw); 2233 pci_disable_device(pdev); 2234 2235 return err; 2236 } 2237 EXPORT_SYMBOL(rtl_pci_probe); 2238 2239 void rtl_pci_disconnect(struct pci_dev *pdev) 2240 { 2241 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2242 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2243 struct rtl_priv *rtlpriv = rtl_priv(hw); 2244 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2245 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2246 2247 /* just in case driver is removed before firmware callback */ 2248 wait_for_completion(&rtlpriv->firmware_loading_complete); 2249 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2250 2251 /* remove form debug */ 2252 rtl_debug_remove_one(hw); 2253 2254 /*ieee80211_unregister_hw will call ops_stop */ 2255 if (rtlmac->mac80211_registered == 1) { 2256 ieee80211_unregister_hw(hw); 2257 rtlmac->mac80211_registered = 0; 2258 } else { 2259 rtl_deinit_deferred_work(hw, false); 2260 rtlpriv->intf_ops->adapter_stop(hw); 2261 } 2262 rtlpriv->cfg->ops->disable_interrupt(hw); 2263 2264 /*deinit rfkill */ 2265 rtl_deinit_rfkill(hw); 2266 2267 rtl_pci_deinit(hw); 2268 rtl_deinit_core(hw); 2269 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2270 2271 if (rtlpci->irq_alloc) { 2272 free_irq(rtlpci->pdev->irq, hw); 2273 rtlpci->irq_alloc = 0; 2274 } 2275 2276 if (rtlpci->using_msi) 2277 pci_disable_msi(rtlpci->pdev); 2278 2279 if (rtlpriv->io.pci_mem_start != 0) { 2280 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2281 pci_release_regions(pdev); 2282 } 2283 2284 pci_disable_device(pdev); 2285 2286 rtl_pci_disable_aspm(hw); 2287 2288 pci_set_drvdata(pdev, NULL); 2289 2290 ieee80211_free_hw(hw); 2291 } 2292 EXPORT_SYMBOL(rtl_pci_disconnect); 2293 2294 #ifdef CONFIG_PM_SLEEP 2295 /*************************************** 2296 * kernel pci power state define: 2297 * PCI_D0 ((pci_power_t __force) 0) 2298 * PCI_D1 ((pci_power_t __force) 1) 2299 * PCI_D2 ((pci_power_t __force) 2) 2300 * PCI_D3hot ((pci_power_t __force) 3) 2301 * PCI_D3cold ((pci_power_t __force) 4) 2302 * PCI_UNKNOWN ((pci_power_t __force) 5) 2303 2304 * This function is called when system 2305 * goes into suspend state mac80211 will 2306 * call rtl_mac_stop() from the mac80211 2307 * suspend function first, So there is 2308 * no need to call hw_disable here. 2309 ****************************************/ 2310 int rtl_pci_suspend(struct device *dev) 2311 { 2312 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2313 struct rtl_priv *rtlpriv = rtl_priv(hw); 2314 2315 rtlpriv->cfg->ops->hw_suspend(hw); 2316 rtl_deinit_rfkill(hw); 2317 2318 return 0; 2319 } 2320 EXPORT_SYMBOL(rtl_pci_suspend); 2321 2322 int rtl_pci_resume(struct device *dev) 2323 { 2324 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2325 struct rtl_priv *rtlpriv = rtl_priv(hw); 2326 2327 rtlpriv->cfg->ops->hw_resume(hw); 2328 rtl_init_rfkill(hw); 2329 return 0; 2330 } 2331 EXPORT_SYMBOL(rtl_pci_resume); 2332 #endif /* CONFIG_PM_SLEEP */ 2333 2334 const struct rtl_intf_ops rtl_pci_ops = { 2335 .adapter_start = rtl_pci_start, 2336 .adapter_stop = rtl_pci_stop, 2337 .adapter_tx = rtl_pci_tx, 2338 .flush = rtl_pci_flush, 2339 .reset_trx_ring = rtl_pci_reset_trx_ring, 2340 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2341 2342 .disable_aspm = rtl_pci_disable_aspm, 2343 .enable_aspm = rtl_pci_enable_aspm, 2344 }; 2345