1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/firmware.h> 17 #include "regs.h" 18 #include "rtl8xxxu.h" 19 20 #define DRIVER_NAME "rtl8xxxu" 21 22 int rtl8xxxu_debug; 23 static bool rtl8xxxu_ht40_2g; 24 static bool rtl8xxxu_dma_aggregation; 25 static int rtl8xxxu_dma_agg_timeout = -1; 26 static int rtl8xxxu_dma_agg_pages = -1; 27 28 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>"); 29 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); 30 MODULE_LICENSE("GPL"); 31 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); 32 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); 33 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); 34 MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin"); 35 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); 36 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); 37 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); 38 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); 39 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); 40 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); 41 MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); 42 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin"); 43 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin"); 44 MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin"); 45 46 module_param_named(debug, rtl8xxxu_debug, int, 0600); 47 MODULE_PARM_DESC(debug, "Set debug mask"); 48 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); 49 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); 50 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); 51 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); 52 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); 53 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); 54 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); 55 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); 56 57 #define USB_VENDOR_ID_REALTEK 0x0bda 58 #define RTL8XXXU_RX_URBS 32 59 #define RTL8XXXU_RX_URB_PENDING_WATER 8 60 #define RTL8XXXU_TX_URBS 64 61 #define RTL8XXXU_TX_URB_LOW_WATER 25 62 #define RTL8XXXU_TX_URB_HIGH_WATER 32 63 64 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 65 struct rtl8xxxu_rx_urb *rx_urb); 66 67 static struct ieee80211_rate rtl8xxxu_rates[] = { 68 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, 69 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, 70 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, 71 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, 72 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, 73 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, 74 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, 75 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, 76 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, 77 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, 78 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, 79 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, 80 }; 81 82 static struct ieee80211_channel rtl8xxxu_channels_2g[] = { 83 { .band = NL80211_BAND_2GHZ, .center_freq = 2412, 84 .hw_value = 1, .max_power = 30 }, 85 { .band = NL80211_BAND_2GHZ, .center_freq = 2417, 86 .hw_value = 2, .max_power = 30 }, 87 { .band = NL80211_BAND_2GHZ, .center_freq = 2422, 88 .hw_value = 3, .max_power = 30 }, 89 { .band = NL80211_BAND_2GHZ, .center_freq = 2427, 90 .hw_value = 4, .max_power = 30 }, 91 { .band = NL80211_BAND_2GHZ, .center_freq = 2432, 92 .hw_value = 5, .max_power = 30 }, 93 { .band = NL80211_BAND_2GHZ, .center_freq = 2437, 94 .hw_value = 6, .max_power = 30 }, 95 { .band = NL80211_BAND_2GHZ, .center_freq = 2442, 96 .hw_value = 7, .max_power = 30 }, 97 { .band = NL80211_BAND_2GHZ, .center_freq = 2447, 98 .hw_value = 8, .max_power = 30 }, 99 { .band = NL80211_BAND_2GHZ, .center_freq = 2452, 100 .hw_value = 9, .max_power = 30 }, 101 { .band = NL80211_BAND_2GHZ, .center_freq = 2457, 102 .hw_value = 10, .max_power = 30 }, 103 { .band = NL80211_BAND_2GHZ, .center_freq = 2462, 104 .hw_value = 11, .max_power = 30 }, 105 { .band = NL80211_BAND_2GHZ, .center_freq = 2467, 106 .hw_value = 12, .max_power = 30 }, 107 { .band = NL80211_BAND_2GHZ, .center_freq = 2472, 108 .hw_value = 13, .max_power = 30 }, 109 { .band = NL80211_BAND_2GHZ, .center_freq = 2484, 110 .hw_value = 14, .max_power = 30 } 111 }; 112 113 static struct ieee80211_supported_band rtl8xxxu_supported_band = { 114 .channels = rtl8xxxu_channels_2g, 115 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), 116 .bitrates = rtl8xxxu_rates, 117 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), 118 }; 119 120 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { 121 {0x800, 0x80040000}, {0x804, 0x00000003}, 122 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 123 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 124 {0x818, 0x02200385}, {0x81c, 0x00000000}, 125 {0x820, 0x01000100}, {0x824, 0x00390004}, 126 {0x828, 0x00000000}, {0x82c, 0x00000000}, 127 {0x830, 0x00000000}, {0x834, 0x00000000}, 128 {0x838, 0x00000000}, {0x83c, 0x00000000}, 129 {0x840, 0x00010000}, {0x844, 0x00000000}, 130 {0x848, 0x00000000}, {0x84c, 0x00000000}, 131 {0x850, 0x00000000}, {0x854, 0x00000000}, 132 {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, 133 {0x860, 0x66f60110}, {0x864, 0x061f0130}, 134 {0x868, 0x00000000}, {0x86c, 0x32323200}, 135 {0x870, 0x07000760}, {0x874, 0x22004000}, 136 {0x878, 0x00000808}, {0x87c, 0x00000000}, 137 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 138 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 139 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 140 {0x898, 0x40302010}, {0x89c, 0x00706050}, 141 {0x900, 0x00000000}, {0x904, 0x00000023}, 142 {0x908, 0x00000000}, {0x90c, 0x81121111}, 143 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 144 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 145 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 146 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 147 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 148 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 149 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 150 {0xa78, 0x00000900}, 151 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 152 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 153 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 154 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 155 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 156 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 157 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 158 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 159 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 160 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 161 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 162 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 163 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 164 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 165 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, 166 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 167 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 168 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 169 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 170 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 171 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 172 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 173 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 174 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 175 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 176 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 177 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 178 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 179 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 180 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 181 {0xd00, 0x00080740}, {0xd04, 0x00020401}, 182 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 183 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 184 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 185 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 186 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 187 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 188 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 189 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 190 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 191 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 192 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 193 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 194 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 195 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 196 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 197 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 198 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 199 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 200 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 201 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 202 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 203 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 204 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 205 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, 206 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, 207 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, 208 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, 209 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, 210 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, 211 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, 212 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, 213 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 214 {0xf00, 0x00000300}, 215 {0xffff, 0xffffffff}, 216 }; 217 218 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { 219 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 220 {0x800, 0x80040002}, {0x804, 0x00000003}, 221 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 222 {0x810, 0x10000330}, {0x814, 0x020c3d10}, 223 {0x818, 0x02200385}, {0x81c, 0x00000000}, 224 {0x820, 0x01000100}, {0x824, 0x00390004}, 225 {0x828, 0x01000100}, {0x82c, 0x00390004}, 226 {0x830, 0x27272727}, {0x834, 0x27272727}, 227 {0x838, 0x27272727}, {0x83c, 0x27272727}, 228 {0x840, 0x00010000}, {0x844, 0x00010000}, 229 {0x848, 0x27272727}, {0x84c, 0x27272727}, 230 {0x850, 0x00000000}, {0x854, 0x00000000}, 231 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, 232 {0x860, 0x66e60230}, {0x864, 0x061f0130}, 233 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, 234 {0x870, 0x07000700}, {0x874, 0x22184000}, 235 {0x878, 0x08080808}, {0x87c, 0x00000000}, 236 {0x880, 0xc0083070}, {0x884, 0x000004d5}, 237 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 238 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 239 {0x898, 0x40302010}, {0x89c, 0x00706050}, 240 {0x900, 0x00000000}, {0x904, 0x00000023}, 241 {0x908, 0x00000000}, {0x90c, 0x81121313}, 242 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, 243 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, 244 {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, 245 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 246 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 247 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 248 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 249 {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, 250 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 251 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 252 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 253 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 254 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 255 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, 256 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 257 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 258 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 259 {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, 260 {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, 261 {0xc60, 0x00000000}, {0xc64, 0x5116848b}, 262 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 263 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, 264 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, 265 {0xc80, 0x40000100}, {0xc84, 0x20f60000}, 266 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, 267 {0xc90, 0x00121820}, {0xc94, 0x00000000}, 268 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 269 {0xca0, 0x00000000}, {0xca4, 0x00000080}, 270 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 271 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 272 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 273 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 274 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 275 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 276 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 277 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 278 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 279 {0xd00, 0x00080740}, {0xd04, 0x00020403}, 280 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 281 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 282 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, 283 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 284 {0xd38, 0x00000000}, {0xd3c, 0x00027293}, 285 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 286 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 287 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 288 {0xd58, 0x00000000}, {0xd5c, 0x30032064}, 289 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 290 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 291 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 292 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, 293 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, 294 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, 295 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, 296 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 297 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 298 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 299 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 300 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 301 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 302 {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, 303 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, 304 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, 305 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, 306 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, 307 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, 308 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, 309 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, 310 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, 311 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 312 {0xf00, 0x00000300}, 313 {0xffff, 0xffffffff}, 314 }; 315 316 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { 317 {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, 318 {0x040, 0x000c0004}, {0x800, 0x80040000}, 319 {0x804, 0x00000001}, {0x808, 0x0000fc00}, 320 {0x80c, 0x0000000a}, {0x810, 0x10005388}, 321 {0x814, 0x020c3d10}, {0x818, 0x02200385}, 322 {0x81c, 0x00000000}, {0x820, 0x01000100}, 323 {0x824, 0x00390204}, {0x828, 0x00000000}, 324 {0x82c, 0x00000000}, {0x830, 0x00000000}, 325 {0x834, 0x00000000}, {0x838, 0x00000000}, 326 {0x83c, 0x00000000}, {0x840, 0x00010000}, 327 {0x844, 0x00000000}, {0x848, 0x00000000}, 328 {0x84c, 0x00000000}, {0x850, 0x00000000}, 329 {0x854, 0x00000000}, {0x858, 0x569a569a}, 330 {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, 331 {0x864, 0x061f0130}, {0x868, 0x00000000}, 332 {0x86c, 0x20202000}, {0x870, 0x03000300}, 333 {0x874, 0x22004000}, {0x878, 0x00000808}, 334 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, 335 {0x884, 0x000004d5}, {0x888, 0x00000000}, 336 {0x88c, 0xccc000c0}, {0x890, 0x00000800}, 337 {0x894, 0xfffffffe}, {0x898, 0x40302010}, 338 {0x89c, 0x00706050}, {0x900, 0x00000000}, 339 {0x904, 0x00000023}, {0x908, 0x00000000}, 340 {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, 341 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, 342 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, 343 {0xa14, 0x11144028}, {0xa18, 0x00881117}, 344 {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, 345 {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, 346 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, 347 {0xa74, 0x00000007}, {0xc00, 0x48071d40}, 348 {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, 349 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 350 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 351 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 352 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 353 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, 354 {0xc34, 0x469652cf}, {0xc38, 0x49795994}, 355 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 356 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 357 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, 358 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, 359 {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, 360 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, 361 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, 362 {0xc74, 0x018610db}, {0xc78, 0x0000001f}, 363 {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, 364 {0xc84, 0x20f60000}, {0xc88, 0x24000090}, 365 {0xc8c, 0x20200000}, {0xc90, 0x00121820}, 366 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 367 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 368 {0xca4, 0x00000080}, {0xca8, 0x00000000}, 369 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 370 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 371 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 372 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 373 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 374 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 375 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 376 {0xce4, 0x00000000}, {0xce8, 0x37644302}, 377 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 378 {0xd04, 0x00020401}, {0xd08, 0x0000907f}, 379 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 380 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 381 {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, 382 {0xd34, 0x80608000}, {0xd38, 0x00000000}, 383 {0xd3c, 0x00027293}, {0xd40, 0x00000000}, 384 {0xd44, 0x00000000}, {0xd48, 0x00000000}, 385 {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, 386 {0xd54, 0x00000000}, {0xd58, 0x00000000}, 387 {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, 388 {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, 389 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, 390 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, 391 {0xe00, 0x24242424}, {0xe04, 0x24242424}, 392 {0xe08, 0x03902024}, {0xe10, 0x24242424}, 393 {0xe14, 0x24242424}, {0xe18, 0x24242424}, 394 {0xe1c, 0x24242424}, {0xe28, 0x00000000}, 395 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 396 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 397 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 398 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 399 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 400 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 401 {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, 402 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, 403 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, 404 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, 405 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, 406 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, 407 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, 408 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, 409 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, 410 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 411 {0xf00, 0x00000300}, 412 {0xffff, 0xffffffff}, 413 }; 414 415 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { 416 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 417 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 418 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 419 {0xc78, 0x7a060001}, {0xc78, 0x79070001}, 420 {0xc78, 0x78080001}, {0xc78, 0x77090001}, 421 {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, 422 {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, 423 {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, 424 {0xc78, 0x70100001}, {0xc78, 0x6f110001}, 425 {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, 426 {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, 427 {0xc78, 0x6a160001}, {0xc78, 0x69170001}, 428 {0xc78, 0x68180001}, {0xc78, 0x67190001}, 429 {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, 430 {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, 431 {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, 432 {0xc78, 0x60200001}, {0xc78, 0x49210001}, 433 {0xc78, 0x48220001}, {0xc78, 0x47230001}, 434 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 435 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 436 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 437 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 438 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 439 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 440 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 441 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 442 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 443 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 444 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 445 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 446 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 447 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 448 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 449 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 450 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 451 {0xc78, 0x7a460001}, {0xc78, 0x79470001}, 452 {0xc78, 0x78480001}, {0xc78, 0x77490001}, 453 {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, 454 {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, 455 {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, 456 {0xc78, 0x70500001}, {0xc78, 0x6f510001}, 457 {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, 458 {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, 459 {0xc78, 0x6a560001}, {0xc78, 0x69570001}, 460 {0xc78, 0x68580001}, {0xc78, 0x67590001}, 461 {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, 462 {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, 463 {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, 464 {0xc78, 0x60600001}, {0xc78, 0x49610001}, 465 {0xc78, 0x48620001}, {0xc78, 0x47630001}, 466 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 467 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 468 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 469 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 470 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 471 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 472 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 473 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 474 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 475 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 476 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 477 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 478 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 479 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 480 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 481 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 482 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 483 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 484 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 485 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 486 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 487 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 488 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 489 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 490 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 491 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 492 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 493 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 494 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 495 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 496 {0xffff, 0xffffffff} 497 }; 498 499 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { 500 {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, 501 {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, 502 {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, 503 {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, 504 {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, 505 {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, 506 {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, 507 {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, 508 {0xc78, 0x73100001}, {0xc78, 0x72110001}, 509 {0xc78, 0x71120001}, {0xc78, 0x70130001}, 510 {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, 511 {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, 512 {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, 513 {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, 514 {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, 515 {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, 516 {0xc78, 0x63200001}, {0xc78, 0x62210001}, 517 {0xc78, 0x61220001}, {0xc78, 0x60230001}, 518 {0xc78, 0x46240001}, {0xc78, 0x45250001}, 519 {0xc78, 0x44260001}, {0xc78, 0x43270001}, 520 {0xc78, 0x42280001}, {0xc78, 0x41290001}, 521 {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, 522 {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, 523 {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, 524 {0xc78, 0x21300001}, {0xc78, 0x20310001}, 525 {0xc78, 0x06320001}, {0xc78, 0x05330001}, 526 {0xc78, 0x04340001}, {0xc78, 0x03350001}, 527 {0xc78, 0x02360001}, {0xc78, 0x01370001}, 528 {0xc78, 0x00380001}, {0xc78, 0x00390001}, 529 {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, 530 {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, 531 {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, 532 {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, 533 {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, 534 {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, 535 {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, 536 {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, 537 {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, 538 {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, 539 {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, 540 {0xc78, 0x73500001}, {0xc78, 0x72510001}, 541 {0xc78, 0x71520001}, {0xc78, 0x70530001}, 542 {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, 543 {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, 544 {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, 545 {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, 546 {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, 547 {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, 548 {0xc78, 0x63600001}, {0xc78, 0x62610001}, 549 {0xc78, 0x61620001}, {0xc78, 0x60630001}, 550 {0xc78, 0x46640001}, {0xc78, 0x45650001}, 551 {0xc78, 0x44660001}, {0xc78, 0x43670001}, 552 {0xc78, 0x42680001}, {0xc78, 0x41690001}, 553 {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, 554 {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, 555 {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, 556 {0xc78, 0x21700001}, {0xc78, 0x20710001}, 557 {0xc78, 0x06720001}, {0xc78, 0x05730001}, 558 {0xc78, 0x04740001}, {0xc78, 0x03750001}, 559 {0xc78, 0x02760001}, {0xc78, 0x01770001}, 560 {0xc78, 0x00780001}, {0xc78, 0x00790001}, 561 {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, 562 {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, 563 {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, 564 {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, 565 {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, 566 {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, 567 {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, 568 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, 569 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, 570 {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, 571 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, 572 {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, 573 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, 574 {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, 575 {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, 576 {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, 577 {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, 578 {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, 579 {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, 580 {0xffff, 0xffffffff} 581 }; 582 583 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { 584 { /* RF_A */ 585 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, 586 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, 587 .lssiparm = REG_FPGA0_XA_LSSI_PARM, 588 .hspiread = REG_HSPI_XA_READBACK, 589 .lssiread = REG_FPGA0_XA_LSSI_READBACK, 590 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, 591 }, 592 { /* RF_B */ 593 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, 594 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, 595 .lssiparm = REG_FPGA0_XB_LSSI_PARM, 596 .hspiread = REG_HSPI_XB_READBACK, 597 .lssiread = REG_FPGA0_XB_LSSI_READBACK, 598 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, 599 }, 600 }; 601 602 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { 603 REG_OFDM0_XA_RX_IQ_IMBALANCE, 604 REG_OFDM0_XB_RX_IQ_IMBALANCE, 605 REG_OFDM0_ENERGY_CCA_THRES, 606 REG_OFDM0_AGC_RSSI_TABLE, 607 REG_OFDM0_XA_TX_IQ_IMBALANCE, 608 REG_OFDM0_XB_TX_IQ_IMBALANCE, 609 REG_OFDM0_XC_TX_AFE, 610 REG_OFDM0_XD_TX_AFE, 611 REG_OFDM0_RX_IQ_EXT_ANTA 612 }; 613 614 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) 615 { 616 struct usb_device *udev = priv->udev; 617 int len; 618 u8 data; 619 620 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 621 addr |= 0x8000; 622 623 mutex_lock(&priv->usb_buf_mutex); 624 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 625 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 626 addr, 0, &priv->usb_buf.val8, sizeof(u8), 627 RTW_USB_CONTROL_MSG_TIMEOUT); 628 data = priv->usb_buf.val8; 629 mutex_unlock(&priv->usb_buf_mutex); 630 631 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 632 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", 633 __func__, addr, data, len); 634 return data; 635 } 636 637 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) 638 { 639 struct usb_device *udev = priv->udev; 640 int len; 641 u16 data; 642 643 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 644 addr |= 0x8000; 645 646 mutex_lock(&priv->usb_buf_mutex); 647 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 648 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 649 addr, 0, &priv->usb_buf.val16, sizeof(u16), 650 RTW_USB_CONTROL_MSG_TIMEOUT); 651 data = le16_to_cpu(priv->usb_buf.val16); 652 mutex_unlock(&priv->usb_buf_mutex); 653 654 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 655 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", 656 __func__, addr, data, len); 657 return data; 658 } 659 660 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) 661 { 662 struct usb_device *udev = priv->udev; 663 int len; 664 u32 data; 665 666 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 667 addr |= 0x8000; 668 669 mutex_lock(&priv->usb_buf_mutex); 670 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 671 REALTEK_USB_CMD_REQ, REALTEK_USB_READ, 672 addr, 0, &priv->usb_buf.val32, sizeof(u32), 673 RTW_USB_CONTROL_MSG_TIMEOUT); 674 data = le32_to_cpu(priv->usb_buf.val32); 675 mutex_unlock(&priv->usb_buf_mutex); 676 677 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) 678 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", 679 __func__, addr, data, len); 680 return data; 681 } 682 683 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) 684 { 685 struct usb_device *udev = priv->udev; 686 int ret; 687 688 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 689 addr |= 0x8000; 690 691 mutex_lock(&priv->usb_buf_mutex); 692 priv->usb_buf.val8 = val; 693 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 694 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 695 addr, 0, &priv->usb_buf.val8, sizeof(u8), 696 RTW_USB_CONTROL_MSG_TIMEOUT); 697 698 mutex_unlock(&priv->usb_buf_mutex); 699 700 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 701 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", 702 __func__, addr, val); 703 return ret; 704 } 705 706 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) 707 { 708 struct usb_device *udev = priv->udev; 709 int ret; 710 711 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 712 addr |= 0x8000; 713 714 mutex_lock(&priv->usb_buf_mutex); 715 priv->usb_buf.val16 = cpu_to_le16(val); 716 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 717 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 718 addr, 0, &priv->usb_buf.val16, sizeof(u16), 719 RTW_USB_CONTROL_MSG_TIMEOUT); 720 mutex_unlock(&priv->usb_buf_mutex); 721 722 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 723 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", 724 __func__, addr, val); 725 return ret; 726 } 727 728 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) 729 { 730 struct usb_device *udev = priv->udev; 731 int ret; 732 733 if (priv->rtl_chip == RTL8710B && addr <= 0xff) 734 addr |= 0x8000; 735 736 mutex_lock(&priv->usb_buf_mutex); 737 priv->usb_buf.val32 = cpu_to_le32(val); 738 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 739 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 740 addr, 0, &priv->usb_buf.val32, sizeof(u32), 741 RTW_USB_CONTROL_MSG_TIMEOUT); 742 mutex_unlock(&priv->usb_buf_mutex); 743 744 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 745 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", 746 __func__, addr, val); 747 return ret; 748 } 749 750 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 751 { 752 u8 val8; 753 754 val8 = rtl8xxxu_read8(priv, addr); 755 val8 |= bits; 756 return rtl8xxxu_write8(priv, addr, val8); 757 } 758 759 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) 760 { 761 u8 val8; 762 763 val8 = rtl8xxxu_read8(priv, addr); 764 val8 &= ~bits; 765 return rtl8xxxu_write8(priv, addr, val8); 766 } 767 768 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 769 { 770 u16 val16; 771 772 val16 = rtl8xxxu_read16(priv, addr); 773 val16 |= bits; 774 return rtl8xxxu_write16(priv, addr, val16); 775 } 776 777 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) 778 { 779 u16 val16; 780 781 val16 = rtl8xxxu_read16(priv, addr); 782 val16 &= ~bits; 783 return rtl8xxxu_write16(priv, addr, val16); 784 } 785 786 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 787 { 788 u32 val32; 789 790 val32 = rtl8xxxu_read32(priv, addr); 791 val32 |= bits; 792 return rtl8xxxu_write32(priv, addr, val32); 793 } 794 795 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) 796 { 797 u32 val32; 798 799 val32 = rtl8xxxu_read32(priv, addr); 800 val32 &= ~bits; 801 return rtl8xxxu_write32(priv, addr, val32); 802 } 803 804 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 805 u32 mask, u32 val) 806 { 807 u32 orig, new, shift; 808 809 shift = __ffs(mask); 810 811 orig = rtl8xxxu_read32(priv, addr); 812 new = (orig & ~mask) | ((val << shift) & mask); 813 return rtl8xxxu_write32(priv, addr, new); 814 } 815 816 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 817 enum rtl8xxxu_rfpath path, u8 reg, 818 u32 mask, u32 val) 819 { 820 u32 orig, new, shift; 821 822 shift = __ffs(mask); 823 824 orig = rtl8xxxu_read_rfreg(priv, path, reg); 825 new = (orig & ~mask) | ((val << shift) & mask); 826 return rtl8xxxu_write_rfreg(priv, path, reg, new); 827 } 828 829 static int 830 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) 831 { 832 struct usb_device *udev = priv->udev; 833 int blocksize = priv->fops->writeN_block_size; 834 int ret, i, count, remainder; 835 836 count = len / blocksize; 837 remainder = len % blocksize; 838 839 for (i = 0; i < count; i++) { 840 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 841 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 842 addr, 0, buf, blocksize, 843 RTW_USB_CONTROL_MSG_TIMEOUT); 844 if (ret != blocksize) 845 goto write_error; 846 847 addr += blocksize; 848 buf += blocksize; 849 } 850 851 if (remainder) { 852 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 853 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, 854 addr, 0, buf, remainder, 855 RTW_USB_CONTROL_MSG_TIMEOUT); 856 if (ret != remainder) 857 goto write_error; 858 } 859 860 return len; 861 862 write_error: 863 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) 864 dev_info(&udev->dev, 865 "%s: Failed to write block at addr: %04x size: %04x\n", 866 __func__, addr, blocksize); 867 return -EAGAIN; 868 } 869 870 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 871 enum rtl8xxxu_rfpath path, u8 reg) 872 { 873 u32 hssia, val32, retval; 874 875 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 876 if (path != RF_A) 877 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); 878 else 879 val32 = hssia; 880 881 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; 882 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); 883 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; 884 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; 885 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 886 887 udelay(10); 888 889 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); 890 udelay(100); 891 892 hssia |= FPGA0_HSSI_PARM2_EDGE_READ; 893 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); 894 udelay(10); 895 896 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); 897 if (val32 & FPGA0_HSSI_PARM1_PI) 898 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); 899 else 900 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); 901 902 retval &= 0xfffff; 903 904 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) 905 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 906 __func__, reg, retval); 907 return retval; 908 } 909 910 /* 911 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can 912 * have write issues in high temperature conditions. We may have to 913 * retry writing them. 914 */ 915 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 916 enum rtl8xxxu_rfpath path, u8 reg, u32 data) 917 { 918 int ret, retval; 919 u32 dataaddr, val32; 920 921 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) 922 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", 923 __func__, reg, data); 924 925 data &= FPGA0_LSSI_PARM_DATA_MASK; 926 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; 927 928 if (priv->rtl_chip == RTL8192E) { 929 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 930 val32 &= ~0x20000; 931 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 932 } 933 934 /* Use XB for path B */ 935 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); 936 if (ret != sizeof(dataaddr)) 937 retval = -EIO; 938 else 939 retval = 0; 940 941 udelay(1); 942 943 if (priv->rtl_chip == RTL8192E) { 944 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 945 val32 |= 0x20000; 946 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 947 } 948 949 return retval; 950 } 951 952 static int 953 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 954 { 955 struct device *dev = &priv->udev->dev; 956 int mbox_nr, retry, retval = 0; 957 int mbox_reg, mbox_ext_reg; 958 u8 val8; 959 960 mutex_lock(&priv->h2c_mutex); 961 962 mbox_nr = priv->next_mbox; 963 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 964 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); 965 966 /* 967 * MBOX ready? 968 */ 969 retry = 100; 970 do { 971 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 972 if (!(val8 & BIT(mbox_nr))) 973 break; 974 } while (retry--); 975 976 if (!retry) { 977 dev_info(dev, "%s: Mailbox busy\n", __func__); 978 retval = -EBUSY; 979 goto error; 980 } 981 982 /* 983 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 984 */ 985 if (len > sizeof(u32)) { 986 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); 987 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 988 dev_info(dev, "H2C_EXT %04x\n", 989 le16_to_cpu(h2c->raw.ext)); 990 } 991 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 992 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 993 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 994 995 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 996 997 error: 998 mutex_unlock(&priv->h2c_mutex); 999 return retval; 1000 } 1001 1002 int 1003 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) 1004 { 1005 struct device *dev = &priv->udev->dev; 1006 int mbox_nr, retry, retval = 0; 1007 int mbox_reg, mbox_ext_reg; 1008 u8 val8; 1009 1010 mutex_lock(&priv->h2c_mutex); 1011 1012 mbox_nr = priv->next_mbox; 1013 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); 1014 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); 1015 1016 /* 1017 * MBOX ready? 1018 */ 1019 retry = 100; 1020 do { 1021 val8 = rtl8xxxu_read8(priv, REG_HMTFR); 1022 if (!(val8 & BIT(mbox_nr))) 1023 break; 1024 } while (retry--); 1025 1026 if (!retry) { 1027 dev_info(dev, "%s: Mailbox busy\n", __func__); 1028 retval = -EBUSY; 1029 goto error; 1030 } 1031 1032 /* 1033 * Need to swap as it's being swapped again by rtl8xxxu_write16/32() 1034 */ 1035 if (len > sizeof(u32)) { 1036 rtl8xxxu_write32(priv, mbox_ext_reg, 1037 le32_to_cpu(h2c->raw_wide.ext)); 1038 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1039 dev_info(dev, "H2C_EXT %08x\n", 1040 le32_to_cpu(h2c->raw_wide.ext)); 1041 } 1042 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); 1043 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) 1044 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); 1045 1046 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; 1047 1048 error: 1049 mutex_unlock(&priv->h2c_mutex); 1050 return retval; 1051 } 1052 1053 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) 1054 { 1055 u8 val8; 1056 u32 val32; 1057 1058 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1059 val8 |= BIT(0) | BIT(3); 1060 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); 1061 1062 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1063 val32 &= ~(BIT(4) | BIT(5)); 1064 val32 |= BIT(3); 1065 if (priv->rf_paths == 2) { 1066 val32 &= ~(BIT(20) | BIT(21)); 1067 val32 |= BIT(19); 1068 } 1069 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1070 1071 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1072 val32 &= ~OFDM_RF_PATH_TX_MASK; 1073 if (priv->tx_paths == 2) 1074 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1075 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) 1076 val32 |= OFDM_RF_PATH_TX_B; 1077 else 1078 val32 |= OFDM_RF_PATH_TX_A; 1079 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1080 1081 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1082 val32 &= ~FPGA_RF_MODE_JAPAN; 1083 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1084 1085 if (priv->rf_paths == 2) 1086 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); 1087 else 1088 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); 1089 1090 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); 1091 if (priv->rf_paths == 2) 1092 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); 1093 1094 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1095 } 1096 1097 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) 1098 { 1099 u8 sps0; 1100 u32 val32; 1101 1102 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); 1103 1104 /* RF RX code for preamble power saving */ 1105 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); 1106 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); 1107 if (priv->rf_paths == 2) 1108 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); 1109 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); 1110 1111 /* Disable TX for four paths */ 1112 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1113 val32 &= ~OFDM_RF_PATH_TX_MASK; 1114 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1115 1116 /* Enable power saving */ 1117 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1118 val32 |= FPGA_RF_MODE_JAPAN; 1119 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1120 1121 /* AFE control register to power down bits [30:22] */ 1122 if (priv->rf_paths == 2) 1123 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); 1124 else 1125 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); 1126 1127 /* Power down RF module */ 1128 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1129 if (priv->rf_paths == 2) 1130 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); 1131 1132 sps0 &= ~(BIT(0) | BIT(3)); 1133 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); 1134 } 1135 1136 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) 1137 { 1138 u8 val8; 1139 1140 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1141 val8 &= ~BIT(6); 1142 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1143 1144 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); 1145 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1146 val8 &= ~BIT(0); 1147 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1148 } 1149 1150 static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv) 1151 { 1152 u8 val8; 1153 1154 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); 1155 val8 |= EN_BCNQ_DL >> 16; 1156 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); 1157 1158 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80); 1159 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); 1160 val8 &= 0xF0; 1161 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); 1162 } 1163 1164 1165 /* 1166 * The rtl8723a has 3 channel groups for its efuse settings. It only 1167 * supports the 2.4GHz band, so channels 1 - 14: 1168 * group 0: channels 1 - 3 1169 * group 1: channels 4 - 9 1170 * group 2: channels 10 - 14 1171 * 1172 * Note: We index from 0 in the code 1173 */ 1174 static int rtl8xxxu_gen1_channel_to_group(int channel) 1175 { 1176 int group; 1177 1178 if (channel < 4) 1179 group = 0; 1180 else if (channel < 10) 1181 group = 1; 1182 else 1183 group = 2; 1184 1185 return group; 1186 } 1187 1188 /* 1189 * Valid for rtl8723bu and rtl8192eu 1190 */ 1191 int rtl8xxxu_gen2_channel_to_group(int channel) 1192 { 1193 int group; 1194 1195 if (channel < 3) 1196 group = 0; 1197 else if (channel < 6) 1198 group = 1; 1199 else if (channel < 9) 1200 group = 2; 1201 else if (channel < 12) 1202 group = 3; 1203 else 1204 group = 4; 1205 1206 return group; 1207 } 1208 1209 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) 1210 { 1211 struct rtl8xxxu_priv *priv = hw->priv; 1212 u32 val32, rsr; 1213 u8 val8, opmode; 1214 bool ht = true; 1215 int sec_ch_above, channel; 1216 int i; 1217 1218 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 1219 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 1220 channel = hw->conf.chandef.chan->hw_value; 1221 1222 switch (hw->conf.chandef.width) { 1223 case NL80211_CHAN_WIDTH_20_NOHT: 1224 ht = false; 1225 fallthrough; 1226 case NL80211_CHAN_WIDTH_20: 1227 opmode |= BW_OPMODE_20MHZ; 1228 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1229 1230 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1231 val32 &= ~FPGA_RF_MODE; 1232 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1233 1234 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1235 val32 &= ~FPGA_RF_MODE; 1236 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1237 1238 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1239 val32 |= FPGA0_ANALOG2_20MHZ; 1240 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1241 break; 1242 case NL80211_CHAN_WIDTH_40: 1243 if (hw->conf.chandef.center_freq1 > 1244 hw->conf.chandef.chan->center_freq) { 1245 sec_ch_above = 1; 1246 channel += 2; 1247 } else { 1248 sec_ch_above = 0; 1249 channel -= 2; 1250 } 1251 1252 opmode &= ~BW_OPMODE_20MHZ; 1253 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 1254 rsr &= ~RSR_RSC_BANDWIDTH_40M; 1255 if (sec_ch_above) 1256 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 1257 else 1258 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 1259 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 1260 1261 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1262 val32 |= FPGA_RF_MODE; 1263 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1264 1265 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1266 val32 |= FPGA_RF_MODE; 1267 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1268 1269 /* 1270 * Set Control channel to upper or lower. These settings 1271 * are required only for 40MHz 1272 */ 1273 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1274 val32 &= ~CCK0_SIDEBAND; 1275 if (!sec_ch_above) 1276 val32 |= CCK0_SIDEBAND; 1277 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1278 1279 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1280 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1281 if (sec_ch_above) 1282 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1283 else 1284 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1285 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1286 1287 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); 1288 val32 &= ~FPGA0_ANALOG2_20MHZ; 1289 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); 1290 1291 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1292 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1293 if (sec_ch_above) 1294 val32 |= FPGA0_PS_UPPER_CHANNEL; 1295 else 1296 val32 |= FPGA0_PS_LOWER_CHANNEL; 1297 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1298 break; 1299 1300 default: 1301 break; 1302 } 1303 1304 for (i = RF_A; i < priv->rf_paths; i++) { 1305 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1306 val32 &= ~MODE_AG_CHANNEL_MASK; 1307 val32 |= channel; 1308 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1309 } 1310 1311 if (ht) 1312 val8 = 0x0e; 1313 else 1314 val8 = 0x0a; 1315 1316 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1317 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1318 1319 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1320 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1321 1322 for (i = RF_A; i < priv->rf_paths; i++) { 1323 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1324 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 1325 val32 &= ~MODE_AG_CHANNEL_20MHZ; 1326 else 1327 val32 |= MODE_AG_CHANNEL_20MHZ; 1328 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1329 } 1330 } 1331 1332 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) 1333 { 1334 struct rtl8xxxu_priv *priv = hw->priv; 1335 u32 val32; 1336 u8 val8, subchannel; 1337 u16 rf_mode_bw; 1338 bool ht = true; 1339 int sec_ch_above, channel; 1340 int i; 1341 1342 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); 1343 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; 1344 channel = hw->conf.chandef.chan->hw_value; 1345 1346 /* Hack */ 1347 subchannel = 0; 1348 1349 switch (hw->conf.chandef.width) { 1350 case NL80211_CHAN_WIDTH_20_NOHT: 1351 ht = false; 1352 fallthrough; 1353 case NL80211_CHAN_WIDTH_20: 1354 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; 1355 subchannel = 0; 1356 1357 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1358 val32 &= ~FPGA_RF_MODE; 1359 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1360 1361 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1362 val32 &= ~FPGA_RF_MODE; 1363 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1364 1365 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 1366 val32 &= ~(BIT(30) | BIT(31)); 1367 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 1368 1369 break; 1370 case NL80211_CHAN_WIDTH_40: 1371 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; 1372 1373 if (hw->conf.chandef.center_freq1 > 1374 hw->conf.chandef.chan->center_freq) { 1375 sec_ch_above = 1; 1376 channel += 2; 1377 } else { 1378 sec_ch_above = 0; 1379 channel -= 2; 1380 } 1381 1382 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 1383 val32 |= FPGA_RF_MODE; 1384 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 1385 1386 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 1387 val32 |= FPGA_RF_MODE; 1388 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 1389 1390 /* 1391 * Set Control channel to upper or lower. These settings 1392 * are required only for 40MHz 1393 */ 1394 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 1395 val32 &= ~CCK0_SIDEBAND; 1396 if (!sec_ch_above) 1397 val32 |= CCK0_SIDEBAND; 1398 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 1399 1400 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 1401 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 1402 if (sec_ch_above) 1403 val32 |= OFDM_LSTF_PRIME_CH_LOW; 1404 else 1405 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 1406 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 1407 1408 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 1409 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 1410 if (sec_ch_above) 1411 val32 |= FPGA0_PS_UPPER_CHANNEL; 1412 else 1413 val32 |= FPGA0_PS_LOWER_CHANNEL; 1414 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 1415 break; 1416 case NL80211_CHAN_WIDTH_80: 1417 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; 1418 break; 1419 default: 1420 break; 1421 } 1422 1423 for (i = RF_A; i < priv->rf_paths; i++) { 1424 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1425 val32 &= ~MODE_AG_CHANNEL_MASK; 1426 val32 |= channel; 1427 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1428 } 1429 1430 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); 1431 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 1432 1433 if (ht) 1434 val8 = 0x0e; 1435 else 1436 val8 = 0x0a; 1437 1438 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); 1439 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); 1440 1441 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); 1442 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); 1443 1444 for (i = RF_A; i < priv->rf_paths; i++) { 1445 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 1446 val32 &= ~MODE_AG_BW_MASK; 1447 switch(hw->conf.chandef.width) { 1448 case NL80211_CHAN_WIDTH_80: 1449 val32 |= MODE_AG_BW_80MHZ_8723B; 1450 break; 1451 case NL80211_CHAN_WIDTH_40: 1452 val32 |= MODE_AG_BW_40MHZ_8723B; 1453 break; 1454 default: 1455 val32 |= MODE_AG_BW_20MHZ_8723B; 1456 break; 1457 } 1458 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 1459 } 1460 } 1461 1462 void 1463 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 1464 { 1465 struct rtl8xxxu_power_base *power_base = priv->power_base; 1466 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; 1467 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; 1468 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; 1469 u8 val8, base; 1470 int group, i; 1471 1472 group = rtl8xxxu_gen1_channel_to_group(channel); 1473 1474 cck[0] = priv->cck_tx_power_index_A[group]; 1475 cck[1] = priv->cck_tx_power_index_B[group]; 1476 1477 if (priv->hi_pa) { 1478 if (cck[0] > 0x20) 1479 cck[0] = 0x20; 1480 if (cck[1] > 0x20) 1481 cck[1] = 0x20; 1482 } 1483 1484 ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; 1485 ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; 1486 1487 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; 1488 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; 1489 1490 mcsbase[0] = ofdm[0]; 1491 mcsbase[1] = ofdm[1]; 1492 if (!ht40) { 1493 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; 1494 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; 1495 } 1496 1497 if (priv->tx_paths > 1) { 1498 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) 1499 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; 1500 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) 1501 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; 1502 } 1503 1504 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 1505 dev_info(&priv->udev->dev, 1506 "%s: Setting TX power CCK A: %02x, " 1507 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", 1508 __func__, cck[0], cck[1], ofdm[0], ofdm[1]); 1509 1510 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { 1511 if (cck[i] > RF6052_MAX_TX_PWR) 1512 cck[i] = RF6052_MAX_TX_PWR; 1513 if (ofdm[i] > RF6052_MAX_TX_PWR) 1514 ofdm[i] = RF6052_MAX_TX_PWR; 1515 } 1516 1517 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 1518 val32 &= 0xffff00ff; 1519 val32 |= (cck[0] << 8); 1520 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 1521 1522 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1523 val32 &= 0xff; 1524 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); 1525 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1526 1527 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 1528 val32 &= 0xffffff00; 1529 val32 |= cck[1]; 1530 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 1531 1532 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 1533 val32 &= 0xff; 1534 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); 1535 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 1536 1537 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | 1538 ofdmbase[0] << 16 | ofdmbase[0] << 24; 1539 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | 1540 ofdmbase[1] << 16 | ofdmbase[1] << 24; 1541 1542 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, 1543 ofdm_a + power_base->reg_0e00); 1544 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, 1545 ofdm_b + power_base->reg_0830); 1546 1547 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, 1548 ofdm_a + power_base->reg_0e04); 1549 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, 1550 ofdm_b + power_base->reg_0834); 1551 1552 mcs_a = mcsbase[0] | mcsbase[0] << 8 | 1553 mcsbase[0] << 16 | mcsbase[0] << 24; 1554 mcs_b = mcsbase[1] | mcsbase[1] << 8 | 1555 mcsbase[1] << 16 | mcsbase[1] << 24; 1556 1557 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, 1558 mcs_a + power_base->reg_0e10); 1559 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, 1560 mcs_b + power_base->reg_083c); 1561 1562 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, 1563 mcs_a + power_base->reg_0e14); 1564 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, 1565 mcs_b + power_base->reg_0848); 1566 1567 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, 1568 mcs_a + power_base->reg_0e18); 1569 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, 1570 mcs_b + power_base->reg_084c); 1571 1572 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, 1573 mcs_a + power_base->reg_0e1c); 1574 val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000); 1575 for (i = 0; i < 3; i++) { 1576 base = i != 2 ? 8 : 6; 1577 val8 = max_t(int, val8 - base, 0); 1578 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); 1579 } 1580 1581 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, 1582 mcs_b + power_base->reg_0868); 1583 val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000); 1584 for (i = 0; i < 3; i++) { 1585 base = i != 2 ? 8 : 6; 1586 val8 = max_t(int, val8 - base, 0); 1587 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); 1588 } 1589 } 1590 1591 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, 1592 enum nl80211_iftype linktype, int port_num) 1593 { 1594 u8 val8, type; 1595 1596 switch (linktype) { 1597 case NL80211_IFTYPE_UNSPECIFIED: 1598 type = MSR_LINKTYPE_NONE; 1599 break; 1600 case NL80211_IFTYPE_ADHOC: 1601 type = MSR_LINKTYPE_ADHOC; 1602 break; 1603 case NL80211_IFTYPE_STATION: 1604 type = MSR_LINKTYPE_STATION; 1605 break; 1606 case NL80211_IFTYPE_AP: 1607 type = MSR_LINKTYPE_AP; 1608 break; 1609 default: 1610 return; 1611 } 1612 1613 switch (port_num) { 1614 case 0: 1615 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x0c; 1616 val8 |= type; 1617 break; 1618 case 1: 1619 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x03; 1620 val8 |= type << 2; 1621 break; 1622 default: 1623 return; 1624 } 1625 1626 rtl8xxxu_write8(priv, REG_MSR, val8); 1627 } 1628 1629 static void 1630 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) 1631 { 1632 u16 val16; 1633 1634 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & 1635 RETRY_LIMIT_SHORT_MASK) | 1636 ((long_retry << RETRY_LIMIT_LONG_SHIFT) & 1637 RETRY_LIMIT_LONG_MASK); 1638 1639 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); 1640 } 1641 1642 static void 1643 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) 1644 { 1645 u16 val16; 1646 1647 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | 1648 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); 1649 1650 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); 1651 } 1652 1653 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) 1654 { 1655 struct device *dev = &priv->udev->dev; 1656 char cut = 'A' + priv->chip_cut; 1657 1658 dev_info(dev, 1659 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", 1660 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev, 1661 priv->tx_paths, priv->rx_paths, priv->ep_tx_count, 1662 priv->has_wifi, priv->has_bluetooth, priv->has_gps, 1663 priv->hi_pa); 1664 1665 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); 1666 } 1667 1668 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor) 1669 { 1670 if (vendor) { 1671 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1672 priv->vendor_umc = 1; 1673 } else { 1674 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1675 } 1676 } 1677 1678 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor) 1679 { 1680 switch (vendor) { 1681 case SYS_CFG_VENDOR_ID_TSMC: 1682 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); 1683 break; 1684 case SYS_CFG_VENDOR_ID_SMIC: 1685 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor)); 1686 priv->vendor_smic = 1; 1687 break; 1688 case SYS_CFG_VENDOR_ID_UMC: 1689 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); 1690 priv->vendor_umc = 1; 1691 break; 1692 default: 1693 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor)); 1694 } 1695 } 1696 1697 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv) 1698 { 1699 u16 val16; 1700 1701 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); 1702 1703 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { 1704 priv->ep_tx_high_queue = 1; 1705 priv->ep_tx_count++; 1706 } 1707 1708 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { 1709 priv->ep_tx_normal_queue = 1; 1710 priv->ep_tx_count++; 1711 } 1712 1713 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { 1714 priv->ep_tx_low_queue = 1; 1715 priv->ep_tx_count++; 1716 } 1717 } 1718 1719 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv) 1720 { 1721 struct device *dev = &priv->udev->dev; 1722 1723 switch (priv->nr_out_eps) { 1724 case 6: 1725 case 5: 1726 case 4: 1727 case 3: 1728 priv->ep_tx_low_queue = 1; 1729 priv->ep_tx_count++; 1730 fallthrough; 1731 case 2: 1732 priv->ep_tx_normal_queue = 1; 1733 priv->ep_tx_count++; 1734 fallthrough; 1735 case 1: 1736 priv->ep_tx_high_queue = 1; 1737 priv->ep_tx_count++; 1738 break; 1739 default: 1740 dev_info(dev, "Unsupported USB TX end-points\n"); 1741 return -ENOTSUPP; 1742 } 1743 1744 return 0; 1745 } 1746 1747 int 1748 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) 1749 { 1750 int i; 1751 u8 val8; 1752 u32 val32; 1753 1754 /* Write Address */ 1755 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); 1756 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); 1757 val8 &= 0xfc; 1758 val8 |= (offset >> 8) & 0x03; 1759 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); 1760 1761 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); 1762 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); 1763 1764 /* Poll for data read */ 1765 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1766 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { 1767 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1768 if (val32 & BIT(31)) 1769 break; 1770 } 1771 1772 if (i == RTL8XXXU_MAX_REG_POLL) 1773 return -EIO; 1774 1775 udelay(50); 1776 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 1777 1778 *data = val32 & 0xff; 1779 return 0; 1780 } 1781 1782 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) 1783 { 1784 struct device *dev = &priv->udev->dev; 1785 int i, ret = 0; 1786 u8 val8, word_mask, header, extheader; 1787 u16 val16, efuse_addr, offset; 1788 u32 val32; 1789 1790 val16 = rtl8xxxu_read16(priv, REG_9346CR); 1791 if (val16 & EEPROM_ENABLE) 1792 priv->has_eeprom = 1; 1793 if (val16 & EEPROM_BOOT) 1794 priv->boot_eeprom = 1; 1795 1796 if (priv->is_multi_func) { 1797 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); 1798 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; 1799 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); 1800 } 1801 1802 dev_dbg(dev, "Booting from %s\n", 1803 priv->boot_eeprom ? "EEPROM" : "EFUSE"); 1804 1805 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); 1806 1807 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ 1808 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 1809 if (!(val16 & SYS_ISO_PWC_EV12V)) { 1810 val16 |= SYS_ISO_PWC_EV12V; 1811 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 1812 } 1813 /* Reset: 0x0000[28], default valid */ 1814 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1815 if (!(val16 & SYS_FUNC_ELDR)) { 1816 val16 |= SYS_FUNC_ELDR; 1817 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1818 } 1819 1820 /* 1821 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid 1822 */ 1823 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 1824 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { 1825 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); 1826 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); 1827 } 1828 1829 /* Default value is 0xff */ 1830 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); 1831 1832 efuse_addr = 0; 1833 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { 1834 u16 map_addr; 1835 1836 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); 1837 if (ret || header == 0xff) 1838 goto exit; 1839 1840 if ((header & 0x1f) == 0x0f) { /* extended header */ 1841 offset = (header & 0xe0) >> 5; 1842 1843 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, 1844 &extheader); 1845 if (ret) 1846 goto exit; 1847 /* All words disabled */ 1848 if ((extheader & 0x0f) == 0x0f) 1849 continue; 1850 1851 offset |= ((extheader & 0xf0) >> 1); 1852 word_mask = extheader & 0x0f; 1853 } else { 1854 offset = (header >> 4) & 0x0f; 1855 word_mask = header & 0x0f; 1856 } 1857 1858 /* Get word enable value from PG header */ 1859 1860 /* We have 8 bits to indicate validity */ 1861 map_addr = offset * 8; 1862 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1863 /* Check word enable condition in the section */ 1864 if (word_mask & BIT(i)) { 1865 map_addr += 2; 1866 continue; 1867 } 1868 1869 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1870 if (ret) 1871 goto exit; 1872 if (map_addr >= EFUSE_MAP_LEN - 1) { 1873 dev_warn(dev, "%s: Illegal map_addr (%04x), " 1874 "efuse corrupt!\n", 1875 __func__, map_addr); 1876 ret = -EINVAL; 1877 goto exit; 1878 } 1879 priv->efuse_wifi.raw[map_addr++] = val8; 1880 1881 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); 1882 if (ret) 1883 goto exit; 1884 priv->efuse_wifi.raw[map_addr++] = val8; 1885 } 1886 } 1887 1888 exit: 1889 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); 1890 1891 return ret; 1892 } 1893 1894 static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv) 1895 { 1896 dev_info(&priv->udev->dev, 1897 "Dumping efuse for RTL%s (0x%02x bytes):\n", 1898 priv->chip_name, EFUSE_MAP_LEN); 1899 1900 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1901 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true); 1902 } 1903 1904 static ssize_t read_file_efuse(struct file *file, char __user *user_buf, 1905 size_t count, loff_t *ppos) 1906 { 1907 struct rtl8xxxu_priv *priv = file_inode(file)->i_private; 1908 1909 return simple_read_from_buffer(user_buf, count, ppos, 1910 priv->efuse_wifi.raw, EFUSE_MAP_LEN); 1911 } 1912 1913 static const struct debugfs_short_fops fops_efuse = { 1914 .read = read_file_efuse, 1915 }; 1916 1917 static void rtl8xxxu_debugfs_init(struct rtl8xxxu_priv *priv) 1918 { 1919 struct dentry *phydir; 1920 1921 phydir = debugfs_create_dir("rtl8xxxu", priv->hw->wiphy->debugfsdir); 1922 debugfs_create_file("efuse", 0400, phydir, priv, &fops_efuse); 1923 } 1924 1925 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1926 { 1927 u8 val8; 1928 u16 sys_func; 1929 1930 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1931 val8 &= ~BIT(0); 1932 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1933 1934 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1935 sys_func &= ~SYS_FUNC_CPU_ENABLE; 1936 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1937 1938 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1939 val8 |= BIT(0); 1940 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1941 1942 sys_func |= SYS_FUNC_CPU_ENABLE; 1943 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 1944 } 1945 1946 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) 1947 { 1948 struct device *dev = &priv->udev->dev; 1949 u16 reg_mcu_fw_dl; 1950 int ret = 0, i; 1951 u32 val32; 1952 1953 if (priv->rtl_chip == RTL8710B) 1954 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 1955 else 1956 reg_mcu_fw_dl = REG_MCU_FW_DL; 1957 1958 /* Poll checksum report */ 1959 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1960 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1961 if (val32 & MCU_FW_DL_CSUM_REPORT) 1962 break; 1963 } 1964 1965 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1966 dev_warn(dev, "Firmware checksum poll timed out\n"); 1967 ret = -EAGAIN; 1968 goto exit; 1969 } 1970 1971 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1972 val32 |= MCU_FW_DL_READY; 1973 val32 &= ~MCU_WINT_INIT_READY; 1974 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 1975 1976 /* 1977 * Reset the 8051 in order for the firmware to start running, 1978 * otherwise it won't come up on the 8192eu 1979 */ 1980 priv->fops->reset_8051(priv); 1981 1982 /* Wait for firmware to become ready */ 1983 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { 1984 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 1985 if (val32 & MCU_WINT_INIT_READY) 1986 break; 1987 1988 udelay(100); 1989 } 1990 1991 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { 1992 dev_warn(dev, "Firmware failed to start\n"); 1993 ret = -EAGAIN; 1994 goto exit; 1995 } 1996 1997 /* 1998 * Init H2C command 1999 */ 2000 if (priv->fops->init_reg_hmtfr) 2001 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); 2002 exit: 2003 return ret; 2004 } 2005 2006 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) 2007 { 2008 int pages, remainder, i, ret; 2009 u16 reg_fw_start_address; 2010 u16 reg_mcu_fw_dl; 2011 u8 val8; 2012 u16 val16; 2013 u32 val32; 2014 u8 *fwptr; 2015 2016 if (priv->rtl_chip == RTL8192F) 2017 reg_fw_start_address = REG_FW_START_ADDRESS_8192F; 2018 else 2019 reg_fw_start_address = REG_FW_START_ADDRESS; 2020 2021 if (priv->rtl_chip == RTL8710B) { 2022 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; 2023 } else { 2024 reg_mcu_fw_dl = REG_MCU_FW_DL; 2025 2026 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); 2027 val8 |= 4; 2028 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); 2029 2030 /* 8051 enable */ 2031 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2032 val16 |= SYS_FUNC_CPU_ENABLE; 2033 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2034 } 2035 2036 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2037 if (val8 & MCU_FW_RAM_SEL) { 2038 dev_info(&priv->udev->dev, 2039 "Firmware is already running, resetting the MCU.\n"); 2040 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00); 2041 priv->fops->reset_8051(priv); 2042 } 2043 2044 /* MCU firmware download enable */ 2045 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2046 val8 |= MCU_FW_DL_ENABLE; 2047 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2048 2049 /* 8051 reset */ 2050 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); 2051 val32 &= ~BIT(19); 2052 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); 2053 2054 if (priv->rtl_chip == RTL8710B) { 2055 /* We must set 0x8090[8]=1 before download FW. */ 2056 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1); 2057 val8 |= BIT(0); 2058 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8); 2059 } 2060 2061 /* Reset firmware download checksum */ 2062 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); 2063 val8 |= MCU_FW_DL_CSUM_REPORT; 2064 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); 2065 2066 pages = priv->fw_size / RTL_FW_PAGE_SIZE; 2067 remainder = priv->fw_size % RTL_FW_PAGE_SIZE; 2068 2069 fwptr = priv->fw_data->data; 2070 2071 for (i = 0; i < pages; i++) { 2072 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2073 val8 |= i; 2074 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2075 2076 ret = rtl8xxxu_writeN(priv, reg_fw_start_address, 2077 fwptr, RTL_FW_PAGE_SIZE); 2078 if (ret != RTL_FW_PAGE_SIZE) { 2079 ret = -EAGAIN; 2080 goto fw_abort; 2081 } 2082 2083 fwptr += RTL_FW_PAGE_SIZE; 2084 } 2085 2086 if (remainder) { 2087 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; 2088 val8 |= i; 2089 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); 2090 ret = rtl8xxxu_writeN(priv, reg_fw_start_address, 2091 fwptr, remainder); 2092 if (ret != remainder) { 2093 ret = -EAGAIN; 2094 goto fw_abort; 2095 } 2096 } 2097 2098 ret = 0; 2099 fw_abort: 2100 /* MCU firmware download disable */ 2101 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl); 2102 val16 &= ~MCU_FW_DL_ENABLE; 2103 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16); 2104 2105 return ret; 2106 } 2107 2108 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name) 2109 { 2110 struct device *dev = &priv->udev->dev; 2111 const struct firmware *fw; 2112 int ret = 0; 2113 u16 signature; 2114 2115 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); 2116 if (request_firmware(&fw, fw_name, &priv->udev->dev)) { 2117 dev_warn(dev, "request_firmware(%s) failed\n", fw_name); 2118 ret = -EAGAIN; 2119 goto exit; 2120 } 2121 if (!fw) { 2122 dev_warn(dev, "Firmware data not available\n"); 2123 ret = -EINVAL; 2124 goto exit; 2125 } 2126 2127 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); 2128 if (!priv->fw_data) { 2129 ret = -ENOMEM; 2130 goto exit; 2131 } 2132 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); 2133 2134 signature = le16_to_cpu(priv->fw_data->signature); 2135 switch (signature & 0xfff0) { 2136 case 0x92e0: 2137 case 0x92c0: 2138 case 0x88e0: 2139 case 0x88c0: 2140 case 0x5300: 2141 case 0x2300: 2142 case 0x88f0: 2143 case 0x10b0: 2144 case 0x92f0: 2145 break; 2146 default: 2147 ret = -EINVAL; 2148 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", 2149 __func__, signature); 2150 } 2151 2152 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", 2153 le16_to_cpu(priv->fw_data->major_version), 2154 priv->fw_data->minor_version, signature); 2155 2156 exit: 2157 release_firmware(fw); 2158 return ret; 2159 } 2160 2161 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) 2162 { 2163 u16 val16; 2164 int i = 100; 2165 2166 /* Inform 8051 to perform reset */ 2167 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); 2168 2169 for (i = 100; i > 0; i--) { 2170 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2171 2172 if (!(val16 & SYS_FUNC_CPU_ENABLE)) { 2173 dev_dbg(&priv->udev->dev, 2174 "%s: Firmware self reset success!\n", __func__); 2175 break; 2176 } 2177 udelay(50); 2178 } 2179 2180 if (!i) { 2181 /* Force firmware reset */ 2182 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2183 val16 &= ~SYS_FUNC_CPU_ENABLE; 2184 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2185 } 2186 } 2187 2188 static int 2189 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) 2190 { 2191 const struct rtl8xxxu_reg8val *array = priv->fops->mactable; 2192 int i, ret; 2193 u16 reg; 2194 u8 val; 2195 2196 for (i = 0; ; i++) { 2197 reg = array[i].reg; 2198 val = array[i].val; 2199 2200 if (reg == 0xffff && val == 0xff) 2201 break; 2202 2203 ret = rtl8xxxu_write8(priv, reg, val); 2204 if (ret != 1) { 2205 dev_warn(&priv->udev->dev, 2206 "Failed to initialize MAC " 2207 "(reg: %04x, val %02x)\n", reg, val); 2208 return -EAGAIN; 2209 } 2210 } 2211 2212 switch (priv->rtl_chip) { 2213 case RTL8188C: 2214 case RTL8188R: 2215 case RTL8191C: 2216 case RTL8192C: 2217 case RTL8723A: 2218 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); 2219 break; 2220 case RTL8188E: 2221 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707); 2222 break; 2223 default: 2224 break; 2225 } 2226 2227 return 0; 2228 } 2229 2230 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2231 const struct rtl8xxxu_reg32val *array) 2232 { 2233 int i, ret; 2234 u16 reg; 2235 u32 val; 2236 2237 for (i = 0; ; i++) { 2238 reg = array[i].reg; 2239 val = array[i].val; 2240 2241 if (reg == 0xffff && val == 0xffffffff) 2242 break; 2243 2244 ret = rtl8xxxu_write32(priv, reg, val); 2245 if (ret != sizeof(val)) { 2246 dev_warn(&priv->udev->dev, 2247 "Failed to initialize PHY\n"); 2248 return -EAGAIN; 2249 } 2250 udelay(1); 2251 } 2252 2253 return 0; 2254 } 2255 2256 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) 2257 { 2258 u8 val8, ldoa15, ldov12d, lpldo, ldohci12; 2259 u16 val16; 2260 u32 val32; 2261 2262 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 2263 udelay(2); 2264 val8 |= AFE_PLL_320_ENABLE; 2265 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 2266 udelay(2); 2267 2268 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); 2269 udelay(2); 2270 2271 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 2272 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 2273 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 2274 2275 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 2276 val32 &= ~AFE_XTAL_RF_GATE; 2277 if (priv->has_bluetooth) 2278 val32 &= ~AFE_XTAL_BT_GATE; 2279 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 2280 2281 /* 6. 0x1f[7:0] = 0x07 */ 2282 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 2283 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 2284 2285 if (priv->hi_pa) 2286 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); 2287 else if (priv->tx_paths == 2) 2288 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); 2289 else 2290 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); 2291 2292 if (priv->rtl_chip == RTL8188R && priv->hi_pa && 2293 priv->vendor_umc && priv->chip_cut == 1) 2294 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); 2295 2296 if (priv->hi_pa) 2297 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); 2298 else 2299 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); 2300 2301 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; 2302 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); 2303 ldohci12 = 0x57; 2304 lpldo = 1; 2305 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; 2306 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); 2307 } 2308 2309 /* 2310 * Most of this is black magic retrieved from the old rtl8723au driver 2311 */ 2312 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) 2313 { 2314 u32 val32; 2315 2316 priv->fops->init_phy_bb(priv); 2317 2318 if (priv->tx_paths == 1 && priv->rx_paths == 2) { 2319 /* 2320 * For 1T2R boards, patch the registers. 2321 * 2322 * It looks like 8191/2 1T2R boards use path B for TX 2323 */ 2324 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); 2325 val32 &= ~(BIT(0) | BIT(1)); 2326 val32 |= BIT(1); 2327 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); 2328 2329 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); 2330 val32 &= ~0x300033; 2331 val32 |= 0x200022; 2332 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); 2333 2334 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 2335 val32 &= ~CCK0_AFE_RX_MASK; 2336 val32 &= 0x00ffffff; 2337 val32 |= 0x40000000; 2338 val32 |= CCK0_AFE_RX_ANT_B; 2339 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 2340 2341 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 2342 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 2343 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 2344 OFDM_RF_PATH_TX_B); 2345 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 2346 2347 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); 2348 val32 &= ~(BIT(4) | BIT(5)); 2349 val32 |= BIT(4); 2350 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); 2351 2352 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); 2353 val32 &= ~(BIT(27) | BIT(26)); 2354 val32 |= BIT(27); 2355 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); 2356 2357 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); 2358 val32 &= ~(BIT(27) | BIT(26)); 2359 val32 |= BIT(27); 2360 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); 2361 2362 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); 2363 val32 &= ~(BIT(27) | BIT(26)); 2364 val32 |= BIT(27); 2365 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); 2366 2367 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); 2368 val32 &= ~(BIT(27) | BIT(26)); 2369 val32 |= BIT(27); 2370 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); 2371 2372 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); 2373 val32 &= ~(BIT(27) | BIT(26)); 2374 val32 |= BIT(27); 2375 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); 2376 } 2377 2378 if (priv->fops->set_crystal_cap) 2379 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap); 2380 2381 if (priv->rtl_chip == RTL8192E) 2382 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); 2383 2384 return 0; 2385 } 2386 2387 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, 2388 const struct rtl8xxxu_rfregval *array, 2389 enum rtl8xxxu_rfpath path) 2390 { 2391 int i, ret; 2392 u8 reg; 2393 u32 val; 2394 2395 for (i = 0; ; i++) { 2396 reg = array[i].reg; 2397 val = array[i].val; 2398 2399 if (reg == 0xff && val == 0xffffffff) 2400 break; 2401 2402 switch (reg) { 2403 case 0xfe: 2404 msleep(50); 2405 continue; 2406 case 0xfd: 2407 mdelay(5); 2408 continue; 2409 case 0xfc: 2410 mdelay(1); 2411 continue; 2412 case 0xfb: 2413 udelay(50); 2414 continue; 2415 case 0xfa: 2416 udelay(5); 2417 continue; 2418 case 0xf9: 2419 udelay(1); 2420 continue; 2421 } 2422 2423 ret = rtl8xxxu_write_rfreg(priv, path, reg, val); 2424 if (ret) { 2425 dev_warn(&priv->udev->dev, 2426 "Failed to initialize RF\n"); 2427 return -EAGAIN; 2428 } 2429 udelay(1); 2430 } 2431 2432 return 0; 2433 } 2434 2435 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2436 const struct rtl8xxxu_rfregval *table, 2437 enum rtl8xxxu_rfpath path) 2438 { 2439 u32 val32; 2440 u16 val16, rfsi_rfenv; 2441 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; 2442 2443 switch (path) { 2444 case RF_A: 2445 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; 2446 reg_int_oe = REG_FPGA0_XA_RF_INT_OE; 2447 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; 2448 break; 2449 case RF_B: 2450 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; 2451 reg_int_oe = REG_FPGA0_XB_RF_INT_OE; 2452 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; 2453 break; 2454 default: 2455 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", 2456 __func__, path + 'A'); 2457 return -EINVAL; 2458 } 2459 /* For path B, use XB */ 2460 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); 2461 rfsi_rfenv &= FPGA0_RF_RFENV; 2462 2463 /* 2464 * These two we might be able to optimize into one 2465 */ 2466 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2467 val32 |= BIT(20); /* 0x10 << 16 */ 2468 rtl8xxxu_write32(priv, reg_int_oe, val32); 2469 udelay(1); 2470 2471 val32 = rtl8xxxu_read32(priv, reg_int_oe); 2472 val32 |= BIT(4); 2473 rtl8xxxu_write32(priv, reg_int_oe, val32); 2474 udelay(1); 2475 2476 /* 2477 * These two we might be able to optimize into one 2478 */ 2479 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2480 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; 2481 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2482 udelay(1); 2483 2484 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); 2485 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; 2486 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); 2487 udelay(1); 2488 2489 rtl8xxxu_init_rf_regs(priv, table, path); 2490 2491 /* For path B, use XB */ 2492 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); 2493 val16 &= ~FPGA0_RF_RFENV; 2494 val16 |= rfsi_rfenv; 2495 rtl8xxxu_write16(priv, reg_sw_ctrl, val16); 2496 2497 return 0; 2498 } 2499 2500 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) 2501 { 2502 int ret = -EBUSY; 2503 int count = 0; 2504 u32 value; 2505 2506 value = LLT_OP_WRITE | address << 8 | data; 2507 2508 rtl8xxxu_write32(priv, REG_LLT_INIT, value); 2509 2510 do { 2511 value = rtl8xxxu_read32(priv, REG_LLT_INIT); 2512 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { 2513 ret = 0; 2514 break; 2515 } 2516 } while (count++ < 20); 2517 2518 return ret; 2519 } 2520 2521 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) 2522 { 2523 int ret; 2524 int i, last_entry; 2525 u8 last_tx_page; 2526 2527 last_tx_page = priv->fops->total_page_num; 2528 2529 if (priv->fops->last_llt_entry) 2530 last_entry = priv->fops->last_llt_entry; 2531 else 2532 last_entry = 255; 2533 2534 for (i = 0; i < last_tx_page; i++) { 2535 ret = rtl8xxxu_llt_write(priv, i, i + 1); 2536 if (ret) 2537 goto exit; 2538 } 2539 2540 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); 2541 if (ret) 2542 goto exit; 2543 2544 /* Mark remaining pages as a ring buffer */ 2545 for (i = last_tx_page + 1; i < last_entry; i++) { 2546 ret = rtl8xxxu_llt_write(priv, i, (i + 1)); 2547 if (ret) 2548 goto exit; 2549 } 2550 2551 /* Let last entry point to the start entry of ring buffer */ 2552 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1); 2553 if (ret) 2554 goto exit; 2555 2556 exit: 2557 return ret; 2558 } 2559 2560 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) 2561 { 2562 u32 val32; 2563 int ret = 0; 2564 int i; 2565 2566 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2567 val32 |= AUTO_LLT_INIT_LLT; 2568 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); 2569 2570 for (i = 500; i; i--) { 2571 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); 2572 if (!(val32 & AUTO_LLT_INIT_LLT)) 2573 break; 2574 usleep_range(2, 4); 2575 } 2576 2577 if (!i) { 2578 ret = -EBUSY; 2579 dev_warn(&priv->udev->dev, "LLT table init failed\n"); 2580 } 2581 2582 return ret; 2583 } 2584 2585 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) 2586 { 2587 u16 val16, hi, lo; 2588 u16 hiq, mgq, bkq, beq, viq, voq; 2589 int hip, mgp, bkp, bep, vip, vop; 2590 int ret = 0; 2591 u32 val32; 2592 2593 switch (priv->ep_tx_count) { 2594 case 1: 2595 if (priv->ep_tx_high_queue) { 2596 hi = TRXDMA_QUEUE_HIGH; 2597 } else if (priv->ep_tx_low_queue) { 2598 hi = TRXDMA_QUEUE_LOW; 2599 } else if (priv->ep_tx_normal_queue) { 2600 hi = TRXDMA_QUEUE_NORMAL; 2601 } else { 2602 hi = 0; 2603 ret = -EINVAL; 2604 } 2605 2606 hiq = hi; 2607 mgq = hi; 2608 bkq = hi; 2609 beq = hi; 2610 viq = hi; 2611 voq = hi; 2612 2613 hip = 0; 2614 mgp = 0; 2615 bkp = 0; 2616 bep = 0; 2617 vip = 0; 2618 vop = 0; 2619 break; 2620 case 2: 2621 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { 2622 hi = TRXDMA_QUEUE_HIGH; 2623 lo = TRXDMA_QUEUE_LOW; 2624 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { 2625 hi = TRXDMA_QUEUE_NORMAL; 2626 lo = TRXDMA_QUEUE_LOW; 2627 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { 2628 hi = TRXDMA_QUEUE_HIGH; 2629 lo = TRXDMA_QUEUE_NORMAL; 2630 } else { 2631 ret = -EINVAL; 2632 hi = 0; 2633 lo = 0; 2634 } 2635 2636 hiq = hi; 2637 mgq = hi; 2638 bkq = lo; 2639 beq = lo; 2640 viq = hi; 2641 voq = hi; 2642 2643 hip = 0; 2644 mgp = 0; 2645 bkp = 1; 2646 bep = 1; 2647 vip = 0; 2648 vop = 0; 2649 break; 2650 case 3: 2651 beq = TRXDMA_QUEUE_LOW; 2652 bkq = TRXDMA_QUEUE_LOW; 2653 viq = TRXDMA_QUEUE_NORMAL; 2654 voq = TRXDMA_QUEUE_HIGH; 2655 mgq = TRXDMA_QUEUE_HIGH; 2656 hiq = TRXDMA_QUEUE_HIGH; 2657 2658 hip = hiq ^ 3; 2659 mgp = mgq ^ 3; 2660 bkp = bkq ^ 3; 2661 bep = beq ^ 3; 2662 vip = viq ^ 3; 2663 vop = viq ^ 3; 2664 break; 2665 default: 2666 ret = -EINVAL; 2667 } 2668 2669 /* 2670 * None of the vendor drivers are configuring the beacon 2671 * queue here .... why? 2672 */ 2673 if (!ret) { 2674 /* Only RTL8192F seems to do it like this. */ 2675 if (priv->rtl_chip == RTL8192F) { 2676 val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL); 2677 val32 &= 0x7; 2678 val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) | 2679 (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) | 2680 (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) | 2681 (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) | 2682 (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) | 2683 (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F); 2684 rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32); 2685 } else { 2686 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); 2687 val16 &= 0x7; 2688 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | 2689 (viq << TRXDMA_CTRL_VIQ_SHIFT) | 2690 (beq << TRXDMA_CTRL_BEQ_SHIFT) | 2691 (bkq << TRXDMA_CTRL_BKQ_SHIFT) | 2692 (mgq << TRXDMA_CTRL_MGQ_SHIFT) | 2693 (hiq << TRXDMA_CTRL_HIQ_SHIFT); 2694 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); 2695 } 2696 2697 priv->pipe_out[TXDESC_QUEUE_VO] = 2698 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); 2699 priv->pipe_out[TXDESC_QUEUE_VI] = 2700 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); 2701 priv->pipe_out[TXDESC_QUEUE_BE] = 2702 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); 2703 priv->pipe_out[TXDESC_QUEUE_BK] = 2704 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); 2705 priv->pipe_out[TXDESC_QUEUE_BEACON] = 2706 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2707 priv->pipe_out[TXDESC_QUEUE_MGNT] = 2708 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); 2709 priv->pipe_out[TXDESC_QUEUE_HIGH] = 2710 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); 2711 priv->pipe_out[TXDESC_QUEUE_CMD] = 2712 usb_sndbulkpipe(priv->udev, priv->out_ep[0]); 2713 } 2714 2715 return ret; 2716 } 2717 2718 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2719 int result[][8], int candidate, bool tx_only) 2720 { 2721 u32 oldval, x, tx0_a, reg; 2722 int y, tx0_c; 2723 u32 val32; 2724 2725 if (!iqk_ok) 2726 return; 2727 2728 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2729 oldval = val32 >> 22; 2730 2731 x = result[candidate][0]; 2732 if ((x & 0x00000200) != 0) 2733 x = x | 0xfffffc00; 2734 tx0_a = (x * oldval) >> 8; 2735 2736 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2737 val32 &= ~0x3ff; 2738 val32 |= tx0_a; 2739 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2740 2741 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2742 val32 &= ~BIT(31); 2743 if ((x * oldval >> 7) & 0x1) 2744 val32 |= BIT(31); 2745 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2746 2747 y = result[candidate][1]; 2748 if ((y & 0x00000200) != 0) 2749 y = y | 0xfffffc00; 2750 tx0_c = (y * oldval) >> 8; 2751 2752 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); 2753 val32 &= ~0xf0000000; 2754 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); 2755 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); 2756 2757 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); 2758 val32 &= ~0x003f0000; 2759 val32 |= ((tx0_c & 0x3f) << 16); 2760 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); 2761 2762 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2763 val32 &= ~BIT(29); 2764 if ((y * oldval >> 7) & 0x1) 2765 val32 |= BIT(29); 2766 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2767 2768 if (tx_only) { 2769 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2770 return; 2771 } 2772 2773 reg = result[candidate][2]; 2774 2775 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2776 val32 &= ~0x3ff; 2777 val32 |= (reg & 0x3ff); 2778 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2779 2780 reg = result[candidate][3] & 0x3F; 2781 2782 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); 2783 val32 &= ~0xfc00; 2784 val32 |= ((reg << 10) & 0xfc00); 2785 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); 2786 2787 reg = (result[candidate][3] >> 6) & 0xF; 2788 2789 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); 2790 val32 &= ~0xf0000000; 2791 val32 |= (reg << 28); 2792 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); 2793 } 2794 2795 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2796 int result[][8], int candidate, bool tx_only) 2797 { 2798 u32 oldval, x, tx1_a, reg; 2799 int y, tx1_c; 2800 u32 val32; 2801 2802 if (!iqk_ok) 2803 return; 2804 2805 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2806 oldval = val32 >> 22; 2807 2808 x = result[candidate][4]; 2809 if ((x & 0x00000200) != 0) 2810 x = x | 0xfffffc00; 2811 tx1_a = (x * oldval) >> 8; 2812 2813 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2814 val32 &= ~0x3ff; 2815 val32 |= tx1_a; 2816 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2817 2818 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2819 val32 &= ~BIT(27); 2820 if ((x * oldval >> 7) & 0x1) 2821 val32 |= BIT(27); 2822 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2823 2824 y = result[candidate][5]; 2825 if ((y & 0x00000200) != 0) 2826 y = y | 0xfffffc00; 2827 tx1_c = (y * oldval) >> 8; 2828 2829 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); 2830 val32 &= ~0xf0000000; 2831 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); 2832 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); 2833 2834 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); 2835 val32 &= ~0x003f0000; 2836 val32 |= ((tx1_c & 0x3f) << 16); 2837 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); 2838 2839 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); 2840 val32 &= ~BIT(25); 2841 if ((y * oldval >> 7) & 0x1) 2842 val32 |= BIT(25); 2843 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); 2844 2845 if (tx_only) { 2846 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); 2847 return; 2848 } 2849 2850 reg = result[candidate][6]; 2851 2852 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2853 val32 &= ~0x3ff; 2854 val32 |= (reg & 0x3ff); 2855 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2856 2857 reg = result[candidate][7] & 0x3f; 2858 2859 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); 2860 val32 &= ~0xfc00; 2861 val32 |= ((reg << 10) & 0xfc00); 2862 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); 2863 2864 reg = (result[candidate][7] >> 6) & 0xf; 2865 2866 if (priv->rtl_chip == RTL8192F) { 2867 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg); 2868 } else { 2869 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE); 2870 val32 &= ~0x0000f000; 2871 val32 |= (reg << 12); 2872 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32); 2873 } 2874 } 2875 2876 #define MAX_TOLERANCE 5 2877 2878 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2879 int result[][8], int c1, int c2) 2880 { 2881 u32 i, j, diff, simubitmap, bound = 0; 2882 int candidate[2] = {-1, -1}; /* for path A and path B */ 2883 bool retval = true; 2884 2885 if (priv->tx_paths > 1) 2886 bound = 8; 2887 else 2888 bound = 4; 2889 2890 simubitmap = 0; 2891 2892 for (i = 0; i < bound; i++) { 2893 diff = (result[c1][i] > result[c2][i]) ? 2894 (result[c1][i] - result[c2][i]) : 2895 (result[c2][i] - result[c1][i]); 2896 if (diff > MAX_TOLERANCE) { 2897 if ((i == 2 || i == 6) && !simubitmap) { 2898 if (result[c1][i] + result[c1][i + 1] == 0) 2899 candidate[(i / 4)] = c2; 2900 else if (result[c2][i] + result[c2][i + 1] == 0) 2901 candidate[(i / 4)] = c1; 2902 else 2903 simubitmap = simubitmap | (1 << i); 2904 } else { 2905 simubitmap = simubitmap | (1 << i); 2906 } 2907 } 2908 } 2909 2910 if (simubitmap == 0) { 2911 for (i = 0; i < (bound / 4); i++) { 2912 if (candidate[i] >= 0) { 2913 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2914 result[3][j] = result[candidate[i]][j]; 2915 retval = false; 2916 } 2917 } 2918 return retval; 2919 } else if (!(simubitmap & 0x0f)) { 2920 /* path A OK */ 2921 for (i = 0; i < 4; i++) 2922 result[3][i] = result[c1][i]; 2923 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { 2924 /* path B OK */ 2925 for (i = 4; i < 8; i++) 2926 result[3][i] = result[c1][i]; 2927 } 2928 2929 return false; 2930 } 2931 2932 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2933 int result[][8], int c1, int c2) 2934 { 2935 u32 i, j, diff, simubitmap, bound = 0; 2936 int candidate[2] = {-1, -1}; /* for path A and path B */ 2937 int tmp1, tmp2; 2938 bool retval = true; 2939 2940 if (priv->tx_paths > 1) 2941 bound = 8; 2942 else 2943 bound = 4; 2944 2945 simubitmap = 0; 2946 2947 for (i = 0; i < bound; i++) { 2948 if (i & 1) { 2949 if ((result[c1][i] & 0x00000200)) 2950 tmp1 = result[c1][i] | 0xfffffc00; 2951 else 2952 tmp1 = result[c1][i]; 2953 2954 if ((result[c2][i]& 0x00000200)) 2955 tmp2 = result[c2][i] | 0xfffffc00; 2956 else 2957 tmp2 = result[c2][i]; 2958 } else { 2959 tmp1 = result[c1][i]; 2960 tmp2 = result[c2][i]; 2961 } 2962 2963 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2964 2965 if (diff > MAX_TOLERANCE) { 2966 if ((i == 2 || i == 6) && !simubitmap) { 2967 if (result[c1][i] + result[c1][i + 1] == 0) 2968 candidate[(i / 4)] = c2; 2969 else if (result[c2][i] + result[c2][i + 1] == 0) 2970 candidate[(i / 4)] = c1; 2971 else 2972 simubitmap = simubitmap | (1 << i); 2973 } else { 2974 simubitmap = simubitmap | (1 << i); 2975 } 2976 } 2977 } 2978 2979 if (simubitmap == 0) { 2980 for (i = 0; i < (bound / 4); i++) { 2981 if (candidate[i] >= 0) { 2982 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2983 result[3][j] = result[candidate[i]][j]; 2984 retval = false; 2985 } 2986 } 2987 return retval; 2988 } else { 2989 if (!(simubitmap & 0x03)) { 2990 /* path A TX OK */ 2991 for (i = 0; i < 2; i++) 2992 result[3][i] = result[c1][i]; 2993 } 2994 2995 if (!(simubitmap & 0x0c)) { 2996 /* path A RX OK */ 2997 for (i = 2; i < 4; i++) 2998 result[3][i] = result[c1][i]; 2999 } 3000 3001 if (!(simubitmap & 0x30) && priv->tx_paths > 1) { 3002 /* path B TX OK */ 3003 for (i = 4; i < 6; i++) 3004 result[3][i] = result[c1][i]; 3005 } 3006 3007 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { 3008 /* path B RX OK */ 3009 for (i = 6; i < 8; i++) 3010 result[3][i] = result[c1][i]; 3011 } 3012 } 3013 3014 return false; 3015 } 3016 3017 void 3018 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) 3019 { 3020 int i; 3021 3022 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 3023 backup[i] = rtl8xxxu_read8(priv, reg[i]); 3024 3025 backup[i] = rtl8xxxu_read32(priv, reg[i]); 3026 } 3027 3028 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 3029 const u32 *reg, u32 *backup) 3030 { 3031 int i; 3032 3033 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) 3034 rtl8xxxu_write8(priv, reg[i], backup[i]); 3035 3036 rtl8xxxu_write32(priv, reg[i], backup[i]); 3037 } 3038 3039 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3040 u32 *backup, int count) 3041 { 3042 int i; 3043 3044 for (i = 0; i < count; i++) 3045 backup[i] = rtl8xxxu_read32(priv, regs[i]); 3046 } 3047 3048 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 3049 u32 *backup, int count) 3050 { 3051 int i; 3052 3053 for (i = 0; i < count; i++) 3054 rtl8xxxu_write32(priv, regs[i], backup[i]); 3055 } 3056 3057 3058 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 3059 bool path_a_on) 3060 { 3061 u32 path_on; 3062 int i; 3063 3064 if (priv->tx_paths == 1) { 3065 path_on = priv->fops->adda_1t_path_on; 3066 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); 3067 } else { 3068 path_on = path_a_on ? priv->fops->adda_2t_path_on_a : 3069 priv->fops->adda_2t_path_on_b; 3070 3071 rtl8xxxu_write32(priv, regs[0], path_on); 3072 } 3073 3074 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) 3075 rtl8xxxu_write32(priv, regs[i], path_on); 3076 } 3077 3078 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 3079 const u32 *regs, u32 *backup) 3080 { 3081 int i = 0; 3082 3083 rtl8xxxu_write8(priv, regs[i], 0x3f); 3084 3085 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) 3086 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); 3087 3088 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); 3089 } 3090 3091 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) 3092 { 3093 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; 3094 int result = 0; 3095 3096 /* path-A IQK setting */ 3097 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); 3098 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); 3099 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); 3100 3101 val32 = (priv->rf_paths > 1) ? 0x28160202 : 3102 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ 3103 0x28160502; 3104 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); 3105 3106 /* path-B IQK setting */ 3107 if (priv->rf_paths > 1) { 3108 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); 3109 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); 3110 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); 3111 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); 3112 } 3113 3114 /* LO calibration setting */ 3115 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); 3116 3117 /* One shot, path A LOK & IQK */ 3118 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 3119 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 3120 3121 mdelay(1); 3122 3123 /* Check failed */ 3124 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3125 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 3126 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 3127 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 3128 3129 if (!(reg_eac & BIT(28)) && 3130 ((reg_e94 & 0x03ff0000) != 0x01420000) && 3131 ((reg_e9c & 0x03ff0000) != 0x00420000)) 3132 result |= 0x01; 3133 else /* If TX not OK, ignore RX */ 3134 goto out; 3135 3136 /* If TX is OK, check whether RX is OK */ 3137 if (!(reg_eac & BIT(27)) && 3138 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 3139 ((reg_eac & 0x03ff0000) != 0x00360000)) 3140 result |= 0x02; 3141 else 3142 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 3143 __func__); 3144 out: 3145 return result; 3146 } 3147 3148 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) 3149 { 3150 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3151 int result = 0; 3152 3153 /* One shot, path B LOK & IQK */ 3154 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); 3155 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); 3156 3157 mdelay(1); 3158 3159 /* Check failed */ 3160 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 3161 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3162 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3163 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3164 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3165 3166 if (!(reg_eac & BIT(31)) && 3167 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 3168 ((reg_ebc & 0x03ff0000) != 0x00420000)) 3169 result |= 0x01; 3170 else 3171 goto out; 3172 3173 if (!(reg_eac & BIT(30)) && 3174 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && 3175 (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) 3176 result |= 0x02; 3177 else 3178 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 3179 __func__); 3180 out: 3181 return result; 3182 } 3183 3184 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 3185 int result[][8], int t) 3186 { 3187 struct device *dev = &priv->udev->dev; 3188 u32 i, val32; 3189 int path_a_ok, path_b_ok; 3190 int retry = 2; 3191 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 3192 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 3193 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 3194 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 3195 REG_TX_OFDM_BBON, REG_TX_TO_RX, 3196 REG_TX_TO_TX, REG_RX_CCK, 3197 REG_RX_OFDM, REG_RX_WAIT_RIFS, 3198 REG_RX_TO_RX, REG_STANDBY, 3199 REG_SLEEP, REG_PMPD_ANAEN 3200 }; 3201 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 3202 REG_TXPAUSE, REG_BEACON_CTRL, 3203 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 3204 }; 3205 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 3206 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 3207 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 3208 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 3209 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 3210 }; 3211 3212 /* 3213 * Note: IQ calibration must be performed after loading 3214 * PHY_REG.txt , and radio_a, radio_b.txt 3215 */ 3216 3217 if (t == 0) { 3218 /* Save ADDA parameters, turn Path A ADDA on */ 3219 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 3220 RTL8XXXU_ADDA_REGS); 3221 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3222 rtl8xxxu_save_regs(priv, iqk_bb_regs, 3223 priv->bb_backup, RTL8XXXU_BB_REGS); 3224 } 3225 3226 rtl8xxxu_path_adda_on(priv, adda_regs, true); 3227 3228 if (t == 0) { 3229 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 3230 if (val32 & FPGA0_HSSI_PARM1_PI) 3231 priv->pi_enabled = 1; 3232 } 3233 3234 if (!priv->pi_enabled) { 3235 /* Switch BB to PI mode to do IQ Calibration. */ 3236 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 3237 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 3238 } 3239 3240 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3241 val32 &= ~FPGA_RF_MODE_CCK; 3242 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 3243 3244 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 3245 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 3246 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 3247 3248 if (!priv->no_pape) { 3249 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 3250 val32 |= (FPGA0_RF_PAPE | 3251 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 3252 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 3253 } 3254 3255 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 3256 val32 &= ~BIT(10); 3257 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 3258 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 3259 val32 &= ~BIT(10); 3260 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 3261 3262 if (priv->tx_paths > 1) { 3263 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3264 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); 3265 } 3266 3267 /* MAC settings */ 3268 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 3269 3270 /* Page B init */ 3271 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); 3272 3273 if (priv->tx_paths > 1) 3274 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); 3275 3276 /* IQ calibration setting */ 3277 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3278 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 3279 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 3280 3281 for (i = 0; i < retry; i++) { 3282 path_a_ok = rtl8xxxu_iqk_path_a(priv); 3283 if (path_a_ok == 0x03) { 3284 val32 = rtl8xxxu_read32(priv, 3285 REG_TX_POWER_BEFORE_IQK_A); 3286 result[t][0] = (val32 >> 16) & 0x3ff; 3287 val32 = rtl8xxxu_read32(priv, 3288 REG_TX_POWER_AFTER_IQK_A); 3289 result[t][1] = (val32 >> 16) & 0x3ff; 3290 val32 = rtl8xxxu_read32(priv, 3291 REG_RX_POWER_BEFORE_IQK_A_2); 3292 result[t][2] = (val32 >> 16) & 0x3ff; 3293 val32 = rtl8xxxu_read32(priv, 3294 REG_RX_POWER_AFTER_IQK_A_2); 3295 result[t][3] = (val32 >> 16) & 0x3ff; 3296 break; 3297 } else if (i == (retry - 1) && path_a_ok == 0x01) { 3298 /* TX IQK OK */ 3299 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", 3300 __func__); 3301 3302 val32 = rtl8xxxu_read32(priv, 3303 REG_TX_POWER_BEFORE_IQK_A); 3304 result[t][0] = (val32 >> 16) & 0x3ff; 3305 val32 = rtl8xxxu_read32(priv, 3306 REG_TX_POWER_AFTER_IQK_A); 3307 result[t][1] = (val32 >> 16) & 0x3ff; 3308 } 3309 } 3310 3311 if (!path_a_ok) 3312 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 3313 3314 if (priv->tx_paths > 1) { 3315 /* 3316 * Path A into standby 3317 */ 3318 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); 3319 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); 3320 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 3321 3322 /* Turn Path B ADDA on */ 3323 rtl8xxxu_path_adda_on(priv, adda_regs, false); 3324 3325 for (i = 0; i < retry; i++) { 3326 path_b_ok = rtl8xxxu_iqk_path_b(priv); 3327 if (path_b_ok == 0x03) { 3328 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3329 result[t][4] = (val32 >> 16) & 0x3ff; 3330 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3331 result[t][5] = (val32 >> 16) & 0x3ff; 3332 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 3333 result[t][6] = (val32 >> 16) & 0x3ff; 3334 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 3335 result[t][7] = (val32 >> 16) & 0x3ff; 3336 break; 3337 } else if (i == (retry - 1) && path_b_ok == 0x01) { 3338 /* TX IQK OK */ 3339 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 3340 result[t][4] = (val32 >> 16) & 0x3ff; 3341 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 3342 result[t][5] = (val32 >> 16) & 0x3ff; 3343 } 3344 } 3345 3346 if (!path_b_ok) 3347 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 3348 } 3349 3350 /* Back to BB mode, load original value */ 3351 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); 3352 3353 if (t) { 3354 if (!priv->pi_enabled) { 3355 /* 3356 * Switch back BB to SI mode after finishing 3357 * IQ Calibration 3358 */ 3359 val32 = 0x01000000; 3360 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 3361 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 3362 } 3363 3364 /* Reload ADDA power saving parameters */ 3365 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 3366 RTL8XXXU_ADDA_REGS); 3367 3368 /* Reload MAC parameters */ 3369 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 3370 3371 /* Reload BB parameters */ 3372 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 3373 priv->bb_backup, RTL8XXXU_BB_REGS); 3374 3375 /* Restore RX initial gain */ 3376 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 3377 3378 if (priv->tx_paths > 1) { 3379 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 3380 0x00032ed3); 3381 } 3382 3383 /* Load 0xe30 IQC default value */ 3384 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 3385 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 3386 } 3387 } 3388 3389 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) 3390 { 3391 struct h2c_cmd h2c; 3392 3393 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3394 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; 3395 h2c.bt_wlan_calibration.data = start; 3396 3397 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); 3398 } 3399 3400 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 3401 { 3402 struct device *dev = &priv->udev->dev; 3403 int result[4][8]; /* last is final result */ 3404 int i, candidate; 3405 bool path_a_ok, path_b_ok; 3406 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 3407 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 3408 s32 reg_tmp = 0; 3409 bool simu; 3410 3411 memset(result, 0, sizeof(result)); 3412 candidate = -1; 3413 3414 path_a_ok = false; 3415 path_b_ok = false; 3416 3417 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 3418 3419 for (i = 0; i < 3; i++) { 3420 rtl8xxxu_phy_iqcalibrate(priv, result, i); 3421 3422 if (i == 1) { 3423 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); 3424 if (simu) { 3425 candidate = 0; 3426 break; 3427 } 3428 } 3429 3430 if (i == 2) { 3431 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); 3432 if (simu) { 3433 candidate = 0; 3434 break; 3435 } 3436 3437 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); 3438 if (simu) { 3439 candidate = 1; 3440 } else { 3441 for (i = 0; i < 8; i++) 3442 reg_tmp += result[3][i]; 3443 3444 if (reg_tmp) 3445 candidate = 3; 3446 else 3447 candidate = -1; 3448 } 3449 } 3450 } 3451 3452 for (i = 0; i < 4; i++) { 3453 reg_e94 = result[i][0]; 3454 reg_e9c = result[i][1]; 3455 reg_ea4 = result[i][2]; 3456 reg_eac = result[i][3]; 3457 reg_eb4 = result[i][4]; 3458 reg_ebc = result[i][5]; 3459 reg_ec4 = result[i][6]; 3460 reg_ecc = result[i][7]; 3461 } 3462 3463 if (candidate >= 0) { 3464 reg_e94 = result[candidate][0]; 3465 priv->rege94 = reg_e94; 3466 reg_e9c = result[candidate][1]; 3467 priv->rege9c = reg_e9c; 3468 reg_ea4 = result[candidate][2]; 3469 reg_eac = result[candidate][3]; 3470 reg_eb4 = result[candidate][4]; 3471 priv->regeb4 = reg_eb4; 3472 reg_ebc = result[candidate][5]; 3473 priv->regebc = reg_ebc; 3474 reg_ec4 = result[candidate][6]; 3475 reg_ecc = result[candidate][7]; 3476 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 3477 dev_dbg(dev, 3478 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 3479 __func__, reg_e94, reg_e9c, 3480 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 3481 path_a_ok = true; 3482 path_b_ok = true; 3483 } else { 3484 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 3485 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 3486 } 3487 3488 if (reg_e94 && candidate >= 0) 3489 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 3490 candidate, (reg_ea4 == 0)); 3491 3492 if (priv->tx_paths > 1 && reg_eb4) 3493 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 3494 candidate, (reg_ec4 == 0)); 3495 3496 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 3497 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 3498 } 3499 3500 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 3501 { 3502 u32 val32; 3503 u32 rf_amode, rf_bmode = 0, lstf; 3504 3505 /* Check continuous TX and Packet TX */ 3506 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 3507 3508 if (lstf & OFDM_LSTF_MASK) { 3509 /* Disable all continuous TX */ 3510 val32 = lstf & ~OFDM_LSTF_MASK; 3511 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 3512 3513 /* Read original RF mode Path A */ 3514 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); 3515 3516 /* Set RF mode to standby Path A */ 3517 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 3518 (rf_amode & 0x8ffff) | 0x10000); 3519 3520 /* Path-B */ 3521 if (priv->tx_paths > 1) { 3522 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, 3523 RF6052_REG_AC); 3524 3525 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3526 (rf_bmode & 0x8ffff) | 0x10000); 3527 } 3528 } else { 3529 /* Deal with Packet TX case */ 3530 /* block all queues */ 3531 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3532 } 3533 3534 /* Start LC calibration */ 3535 if (priv->fops->has_s0s1) 3536 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); 3537 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 3538 val32 |= 0x08000; 3539 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 3540 3541 msleep(100); 3542 3543 if (priv->fops->has_s0s1) 3544 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); 3545 3546 /* Restore original parameters */ 3547 if (lstf & OFDM_LSTF_MASK) { 3548 /* Path-A */ 3549 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 3550 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); 3551 3552 /* Path-B */ 3553 if (priv->tx_paths > 1) 3554 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 3555 rf_bmode); 3556 } else /* Deal with Packet TX case */ 3557 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 3558 } 3559 3560 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv, int port_num) 3561 { 3562 int i; 3563 u16 reg; 3564 3565 switch (port_num) { 3566 case 0: 3567 reg = REG_MACID; 3568 break; 3569 case 1: 3570 reg = REG_MACID1; 3571 break; 3572 default: 3573 WARN_ONCE(1, "%s: invalid port_num\n", __func__); 3574 return -EINVAL; 3575 } 3576 3577 for (i = 0; i < ETH_ALEN; i++) 3578 rtl8xxxu_write8(priv, reg + i, priv->vifs[port_num]->addr[i]); 3579 3580 return 0; 3581 } 3582 3583 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid, int port_num) 3584 { 3585 int i; 3586 u16 reg; 3587 3588 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); 3589 3590 switch (port_num) { 3591 case 0: 3592 reg = REG_BSSID; 3593 break; 3594 case 1: 3595 reg = REG_BSSID1; 3596 break; 3597 default: 3598 WARN_ONCE(1, "%s: invalid port_num\n", __func__); 3599 return -EINVAL; 3600 } 3601 3602 for (i = 0; i < ETH_ALEN; i++) 3603 rtl8xxxu_write8(priv, reg + i, bssid[i]); 3604 3605 return 0; 3606 } 3607 3608 static void 3609 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) 3610 { 3611 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 3612 u8 max_agg = 0xf; 3613 int i; 3614 3615 ampdu_factor = 1 << (ampdu_factor + 2); 3616 if (ampdu_factor > max_agg) 3617 ampdu_factor = max_agg; 3618 3619 for (i = 0; i < 4; i++) { 3620 if ((vals[i] & 0xf0) > (ampdu_factor << 4)) 3621 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); 3622 3623 if ((vals[i] & 0x0f) > ampdu_factor) 3624 vals[i] = (vals[i] & 0xf0) | ampdu_factor; 3625 3626 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); 3627 } 3628 } 3629 3630 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) 3631 { 3632 u8 val8; 3633 3634 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); 3635 val8 &= 0xf8; 3636 val8 |= density; 3637 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); 3638 } 3639 3640 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) 3641 { 3642 u8 val8; 3643 int count, ret = 0; 3644 3645 /* Start of rtl8723AU_card_enable_flow */ 3646 /* Act to Cardemu sequence*/ 3647 /* Turn off RF */ 3648 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 3649 3650 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ 3651 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 3652 val8 &= ~LEDCFG2_DPDT_SELECT; 3653 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 3654 3655 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 3656 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3657 val8 |= BIT(1); 3658 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3659 3660 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3661 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3662 if ((val8 & BIT(1)) == 0) 3663 break; 3664 udelay(10); 3665 } 3666 3667 if (!count) { 3668 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 3669 __func__); 3670 ret = -EBUSY; 3671 goto exit; 3672 } 3673 3674 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 3675 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 3676 val8 |= SYS_ISO_ANALOG_IPS; 3677 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 3678 3679 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 3680 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 3681 val8 &= ~LDOA15_ENABLE; 3682 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 3683 3684 exit: 3685 return ret; 3686 } 3687 3688 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) 3689 { 3690 u8 val8; 3691 u8 val32; 3692 int count, ret = 0; 3693 3694 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3695 3696 /* 3697 * Poll - wait for RX packet to complete 3698 */ 3699 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 3700 val32 = rtl8xxxu_read32(priv, 0x5f8); 3701 if (!val32) 3702 break; 3703 udelay(10); 3704 } 3705 3706 if (!count) { 3707 dev_warn(&priv->udev->dev, 3708 "%s: RX poll timed out (0x05f8)\n", __func__); 3709 ret = -EBUSY; 3710 goto exit; 3711 } 3712 3713 /* Disable CCK and OFDM, clock gated */ 3714 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3715 val8 &= ~SYS_FUNC_BBRSTB; 3716 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3717 3718 udelay(2); 3719 3720 /* Reset baseband */ 3721 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 3722 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 3723 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 3724 3725 /* Reset MAC TRX */ 3726 val8 = rtl8xxxu_read8(priv, REG_CR); 3727 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; 3728 rtl8xxxu_write8(priv, REG_CR, val8); 3729 3730 /* Reset MAC TRX */ 3731 val8 = rtl8xxxu_read8(priv, REG_CR + 1); 3732 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ 3733 rtl8xxxu_write8(priv, REG_CR + 1, val8); 3734 3735 /* Respond TX OK to scheduler */ 3736 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 3737 val8 |= DUAL_TSF_TX_OK; 3738 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 3739 3740 exit: 3741 return ret; 3742 } 3743 3744 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) 3745 { 3746 u8 val8; 3747 3748 /* Clear suspend enable and power down enable*/ 3749 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3750 val8 &= ~(BIT(3) | BIT(7)); 3751 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3752 3753 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ 3754 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3755 val8 &= ~BIT(0); 3756 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3757 3758 /* 0x04[12:11] = 11 enable WL suspend*/ 3759 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3760 val8 &= ~(BIT(3) | BIT(4)); 3761 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3762 } 3763 3764 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) 3765 { 3766 u8 val8; 3767 3768 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ 3769 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 3770 3771 /* 0x04[12:11] = 01 enable WL suspend */ 3772 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3773 val8 &= ~BIT(4); 3774 val8 |= BIT(3); 3775 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3776 3777 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 3778 val8 |= BIT(7); 3779 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 3780 3781 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 3782 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 3783 val8 |= BIT(0); 3784 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 3785 3786 return 0; 3787 } 3788 3789 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) 3790 { 3791 struct device *dev = &priv->udev->dev; 3792 u32 val32; 3793 int retry, retval; 3794 3795 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 3796 3797 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3798 val32 |= RXPKT_NUM_RW_RELEASE_EN; 3799 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); 3800 3801 retry = 100; 3802 retval = -EBUSY; 3803 3804 do { 3805 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); 3806 if (val32 & RXPKT_NUM_RXDMA_IDLE) { 3807 retval = 0; 3808 break; 3809 } 3810 } while (retry--); 3811 3812 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); 3813 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); 3814 mdelay(2); 3815 3816 if (!retry) 3817 dev_warn(dev, "Failed to flush FIFO\n"); 3818 3819 return retval; 3820 } 3821 3822 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) 3823 { 3824 /* Fix USB interface interference issue */ 3825 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3826 rtl8xxxu_write8(priv, 0xfe41, 0x8d); 3827 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3828 /* 3829 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits 3830 * 8 and 5, for which I have found no documentation. 3831 */ 3832 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); 3833 3834 /* 3835 * Solve too many protocol error on USB bus. 3836 * Can't do this for 8188/8192 UMC A cut parts 3837 */ 3838 if (!(!priv->chip_cut && priv->vendor_umc)) { 3839 rtl8xxxu_write8(priv, 0xfe40, 0xe6); 3840 rtl8xxxu_write8(priv, 0xfe41, 0x94); 3841 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3842 3843 rtl8xxxu_write8(priv, 0xfe40, 0xe0); 3844 rtl8xxxu_write8(priv, 0xfe41, 0x19); 3845 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3846 3847 rtl8xxxu_write8(priv, 0xfe40, 0xe5); 3848 rtl8xxxu_write8(priv, 0xfe41, 0x91); 3849 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3850 3851 rtl8xxxu_write8(priv, 0xfe40, 0xe2); 3852 rtl8xxxu_write8(priv, 0xfe41, 0x81); 3853 rtl8xxxu_write8(priv, 0xfe42, 0x80); 3854 } 3855 } 3856 3857 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) 3858 { 3859 u32 val32; 3860 3861 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 3862 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 3863 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 3864 } 3865 3866 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) 3867 { 3868 u8 val8; 3869 u16 val16; 3870 u32 val32; 3871 3872 /* 3873 * Workaround for 8188RU LNA power leakage problem. 3874 */ 3875 if (priv->rtl_chip == RTL8188R) { 3876 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 3877 val32 |= BIT(1); 3878 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 3879 } 3880 3881 rtl8xxxu_flush_fifo(priv); 3882 3883 rtl8xxxu_active_to_lps(priv); 3884 3885 /* Turn off RF */ 3886 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 3887 3888 /* Reset Firmware if running in RAM */ 3889 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 3890 rtl8xxxu_firmware_self_reset(priv); 3891 3892 /* Reset MCU */ 3893 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 3894 val16 &= ~SYS_FUNC_CPU_ENABLE; 3895 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 3896 3897 /* Reset MCU ready status */ 3898 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 3899 3900 rtl8xxxu_active_to_emu(priv); 3901 rtl8xxxu_emu_to_disabled(priv); 3902 3903 /* Reset MCU IO Wrapper */ 3904 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3905 val8 &= ~BIT(0); 3906 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3907 3908 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 3909 val8 |= BIT(0); 3910 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 3911 3912 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ 3913 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); 3914 } 3915 3916 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 3917 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) 3918 { 3919 struct h2c_cmd h2c; 3920 3921 memset(&h2c, 0, sizeof(struct h2c_cmd)); 3922 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; 3923 h2c.b_type_dma.data1 = arg1; 3924 h2c.b_type_dma.data2 = arg2; 3925 h2c.b_type_dma.data3 = arg3; 3926 h2c.b_type_dma.data4 = arg4; 3927 h2c.b_type_dma.data5 = arg5; 3928 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); 3929 } 3930 3931 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) 3932 { 3933 u32 val32; 3934 3935 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 3936 val32 &= ~(BIT(22) | BIT(23)); 3937 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 3938 } 3939 3940 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) 3941 { 3942 struct rtl8xxxu_fileops *fops = priv->fops; 3943 u32 hq, lq, nq, eq, pubq; 3944 u32 val32; 3945 3946 hq = 0; 3947 lq = 0; 3948 nq = 0; 3949 eq = 0; 3950 pubq = 0; 3951 3952 if (priv->ep_tx_high_queue) 3953 hq = fops->page_num_hi; 3954 if (priv->ep_tx_low_queue) 3955 lq = fops->page_num_lo; 3956 if (priv->ep_tx_normal_queue) 3957 nq = fops->page_num_norm; 3958 3959 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); 3960 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); 3961 3962 pubq = fops->total_page_num - hq - lq - nq - 1; 3963 3964 val32 = RQPN_LOAD; 3965 val32 |= (hq << RQPN_HI_PQ_SHIFT); 3966 val32 |= (lq << RQPN_LO_PQ_SHIFT); 3967 val32 |= (pubq << RQPN_PUB_PQ_SHIFT); 3968 3969 rtl8xxxu_write32(priv, REG_RQPN, val32); 3970 } 3971 3972 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv) 3973 { 3974 u8 val8; 3975 3976 /* 3977 * For USB high speed set 512B packets 3978 */ 3979 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 3980 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE); 3981 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT); 3982 val8 |= RXDMA_PRO_DMA_MODE; 3983 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); 3984 3985 /* 3986 * Enable single packet AMPDU 3987 */ 3988 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); 3989 val8 |= HT_SINGLE_AMPDU_ENABLE; 3990 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); 3991 3992 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num); 3993 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 3994 priv->fops->ampdu_max_time); 3995 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); 3996 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); 3997 rtl8xxxu_write8(priv, REG_PIFS, 0x00); 3998 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B || 3999 priv->rtl_chip == RTL8192F) { 4000 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); 4001 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); 4002 } 4003 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca); 4004 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca); 4005 4006 /* to prevent mac is reseted by bus. */ 4007 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 4008 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST; 4009 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 4010 } 4011 4012 static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv) 4013 { 4014 u8 macid; 4015 4016 macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); 4017 if (macid < RTL8XXXU_MAX_MAC_ID_NUM) 4018 set_bit(macid, priv->mac_id_map); 4019 4020 return macid; 4021 } 4022 4023 static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid) 4024 { 4025 clear_bit(macid, priv->mac_id_map); 4026 } 4027 4028 static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv, 4029 struct ieee80211_sta *sta) 4030 { 4031 struct rtl8xxxu_sta_info *sta_info; 4032 4033 if (!sta) 4034 return 0; 4035 4036 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 4037 if (!sta_info) 4038 return 0; 4039 4040 return sta_info->macid; 4041 } 4042 4043 static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 4044 { 4045 struct rtl8xxxu_priv *priv = hw->priv; 4046 struct device *dev = &priv->udev->dev; 4047 struct rtl8xxxu_fileops *fops = priv->fops; 4048 bool macpower; 4049 int ret; 4050 u8 val8; 4051 u16 val16; 4052 u32 val32; 4053 4054 /* Check if MAC is already powered on */ 4055 val8 = rtl8xxxu_read8(priv, REG_CR); 4056 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); 4057 4058 /* 4059 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not 4060 * initialized. First MAC returns 0xea, second MAC returns 0x00 4061 */ 4062 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) 4063 macpower = false; 4064 else 4065 macpower = true; 4066 4067 if (fops->needs_full_init) 4068 macpower = false; 4069 4070 ret = fops->power_on(priv); 4071 if (ret < 0) { 4072 dev_warn(dev, "%s: Failed power on\n", __func__); 4073 goto exit; 4074 } 4075 4076 if (!macpower) 4077 rtl8xxxu_init_queue_reserved_page(priv); 4078 4079 ret = rtl8xxxu_init_queue_priority(priv); 4080 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); 4081 if (ret) 4082 goto exit; 4083 4084 /* 4085 * Set RX page boundary 4086 */ 4087 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); 4088 4089 for (int retry = 5; retry >= 0 ; retry--) { 4090 ret = rtl8xxxu_download_firmware(priv); 4091 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); 4092 if (ret != -EAGAIN) 4093 break; 4094 if (retry) 4095 dev_dbg(dev, "%s: retry firmware download\n", __func__); 4096 } 4097 if (ret) 4098 goto exit; 4099 ret = rtl8xxxu_start_firmware(priv); 4100 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); 4101 if (ret) 4102 goto exit; 4103 4104 if (fops->phy_init_antenna_selection) 4105 fops->phy_init_antenna_selection(priv); 4106 4107 ret = rtl8xxxu_init_mac(priv); 4108 4109 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); 4110 if (ret) 4111 goto exit; 4112 4113 ret = rtl8xxxu_init_phy_bb(priv); 4114 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); 4115 if (ret) 4116 goto exit; 4117 4118 ret = fops->init_phy_rf(priv); 4119 if (ret) 4120 goto exit; 4121 4122 /* Mac APLL Setting */ 4123 if (priv->rtl_chip == RTL8192F) 4124 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15)); 4125 4126 /* RFSW Control - clear bit 14 ?? */ 4127 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E && 4128 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B && 4129 priv->rtl_chip != RTL8192F) 4130 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); 4131 4132 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | 4133 FPGA0_RF_ANTSWB | 4134 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); 4135 if (!priv->no_pape) { 4136 val32 |= (FPGA0_RF_PAPE | 4137 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 4138 } 4139 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 4140 4141 /* 0x860[6:5]= 00 - why? - this sets antenna B */ 4142 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E && 4143 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) 4144 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); 4145 4146 if (!macpower) { 4147 /* 4148 * Set TX buffer boundary 4149 */ 4150 val8 = fops->total_page_num + 1; 4151 4152 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); 4153 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); 4154 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); 4155 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); 4156 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); 4157 } 4158 4159 /* 4160 * The vendor drivers set PBP for all devices, except 8192e. 4161 * There is no explanation for this in any of the sources. 4162 */ 4163 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | 4164 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); 4165 if (priv->rtl_chip != RTL8192E) 4166 rtl8xxxu_write8(priv, REG_PBP, val8); 4167 4168 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); 4169 if (!macpower) { 4170 ret = fops->llt_init(priv); 4171 if (ret) { 4172 dev_warn(dev, "%s: LLT table init failed\n", __func__); 4173 goto exit; 4174 } 4175 4176 /* 4177 * Chip specific quirks 4178 */ 4179 fops->usb_quirks(priv); 4180 4181 /* 4182 * Enable TX report and TX report timer for 8723bu/8188eu/... 4183 */ 4184 if (fops->has_tx_report) { 4185 /* 4186 * The RTL8188EU has two types of TX reports: 4187 * rpt_sel=1: 4188 * One report for one frame. We can use this for frames 4189 * with IEEE80211_TX_CTL_REQ_TX_STATUS. 4190 * rpt_sel=2: 4191 * One report for many frames transmitted over a period 4192 * of time. (This is what REG_TX_REPORT_TIME is for.) The 4193 * report includes the number of frames transmitted 4194 * successfully, and the number of unsuccessful 4195 * transmissions. We use this for software rate control. 4196 * 4197 * Bit 0 of REG_TX_REPORT_CTRL is required for both types. 4198 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for 4199 * type 2. 4200 */ 4201 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 4202 if (priv->rtl_chip == RTL8188E) 4203 val8 |= BIT(0); 4204 val8 |= TX_REPORT_CTRL_TIMER_ENABLE; 4205 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 4206 /* Set MAX RPT MACID */ 4207 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); 4208 /* TX report Timer. Unit: 32us */ 4209 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); 4210 4211 /* tmp ps ? */ 4212 val8 = rtl8xxxu_read8(priv, 0xa3); 4213 val8 &= 0xf8; 4214 rtl8xxxu_write8(priv, 0xa3, val8); 4215 } 4216 4217 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) 4218 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0); 4219 } 4220 4221 /* 4222 * Unit in 8 bytes. 4223 * Get Rx PHY status in order to report RSSI and others. 4224 */ 4225 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); 4226 4227 if (priv->rtl_chip == RTL8192E) { 4228 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); 4229 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); 4230 } else if (priv->rtl_chip == RTL8188F) { 4231 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4232 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); 4233 } else if (priv->rtl_chip == RTL8188E) { 4234 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); 4235 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2; 4236 rtl8xxxu_write32(priv, REG_HIMR0, val32); 4237 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW; 4238 rtl8xxxu_write32(priv, REG_HIMR1, val32); 4239 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4240 val8 |= USB_SPEC_INT_BULK_SELECT; 4241 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8); 4242 } else if (priv->rtl_chip == RTL8710B) { 4243 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0); 4244 } else if (priv->rtl_chip != RTL8192F) { 4245 /* 4246 * Enable all interrupts - not obvious USB needs to do this 4247 */ 4248 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); 4249 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); 4250 } 4251 4252 /* 4253 * Configure initial WMAC settings 4254 */ 4255 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | 4256 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | 4257 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; 4258 rtl8xxxu_write32(priv, REG_RCR, val32); 4259 priv->regrcr = val32; 4260 4261 if (fops->init_reg_rxfltmap) { 4262 /* Accept all data frames */ 4263 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 4264 4265 /* 4266 * Since ADF is removed from RCR, ps-poll will not be indicate to driver, 4267 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. 4268 */ 4269 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); 4270 4271 /* Accept all management frames */ 4272 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 4273 } else { 4274 /* 4275 * Accept all multicast 4276 */ 4277 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); 4278 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); 4279 } 4280 4281 /* 4282 * Init adaptive controls 4283 */ 4284 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4285 val32 &= ~RESPONSE_RATE_BITMAP_ALL; 4286 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; 4287 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4288 4289 /* CCK = 0x0a, OFDM = 0x10 */ 4290 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); 4291 rtl8xxxu_set_retry(priv, 0x30, 0x30); 4292 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); 4293 4294 /* 4295 * Init EDCA 4296 */ 4297 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); 4298 4299 /* Set CCK SIFS */ 4300 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); 4301 4302 /* Set OFDM SIFS */ 4303 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); 4304 4305 /* TXOP */ 4306 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); 4307 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); 4308 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); 4309 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); 4310 4311 /* Set data auto rate fallback retry count */ 4312 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); 4313 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); 4314 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); 4315 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); 4316 4317 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); 4318 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; 4319 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); 4320 4321 /* Set ACK timeout */ 4322 rtl8xxxu_write8(priv, REG_ACKTO, 0x40); 4323 4324 /* 4325 * Initialize beacon parameters 4326 */ 4327 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); 4328 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); 4329 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); 4330 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B && 4331 priv->rtl_chip != RTL8192F) 4332 /* Firmware will control REG_DRVERLYINT when power saving is enable, */ 4333 /* so don't set this register on STA mode. */ 4334 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); 4335 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); 4336 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); 4337 4338 /* 4339 * Initialize burst parameters 4340 */ 4341 if (priv->fops->init_burst) 4342 priv->fops->init_burst(priv); 4343 4344 if (fops->init_aggregation) 4345 fops->init_aggregation(priv); 4346 4347 if (fops->init_reg_pkt_life_time) { 4348 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4349 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 4350 } 4351 4352 /* 4353 * Enable CCK and OFDM block 4354 */ 4355 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4356 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); 4357 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4358 4359 /* 4360 * Invalidate all CAM entries - bit 30 is undocumented 4361 */ 4362 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); 4363 4364 /* 4365 * Start out with default power levels for channel 6, 20MHz 4366 */ 4367 fops->set_tx_power(priv, 1, false); 4368 4369 /* Let the 8051 take control of antenna setting */ 4370 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F && 4371 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192C) { 4372 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 4373 val8 |= LEDCFG2_DPDT_SELECT; 4374 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 4375 } 4376 4377 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); 4378 4379 /* Disable BAR - not sure if this has any effect on USB */ 4380 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); 4381 4382 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E && 4383 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) 4384 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); 4385 4386 if (fops->init_statistics) 4387 fops->init_statistics(priv); 4388 4389 if (priv->rtl_chip == RTL8192E) { 4390 /* 4391 * 0x4c6[3] 1: RTS BW = Data BW 4392 * 0: RTS BW depends on CCA / secondary CCA result. 4393 */ 4394 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); 4395 val8 &= ~BIT(3); 4396 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); 4397 /* 4398 * Reset USB mode switch setting 4399 */ 4400 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); 4401 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E || 4402 priv->rtl_chip == RTL8192F) { 4403 /* 4404 * Init GPIO settings for 8188f, 8188e, 8192f 4405 */ 4406 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 4407 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; 4408 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 4409 } 4410 4411 if (priv->rtl_chip == RTL8188F) 4412 /* CCK PD */ 4413 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); 4414 4415 fops->phy_lc_calibrate(priv); 4416 4417 fops->phy_iq_calibrate(priv); 4418 4419 /* 4420 * This should enable thermal meter 4421 */ 4422 if (fops->gen2_thermal_meter) { 4423 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) { 4424 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); 4425 val32 |= 0x30000; 4426 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); 4427 } else { 4428 rtl8xxxu_write_rfreg(priv, 4429 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); 4430 } 4431 } else { 4432 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); 4433 } 4434 4435 /* Set NAV_UPPER to 30000us */ 4436 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); 4437 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); 4438 4439 if (priv->rtl_chip == RTL8723A) { 4440 /* 4441 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, 4442 * but we need to find root cause. 4443 * This is 8723au only. 4444 */ 4445 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 4446 if ((val32 & 0xff000000) != 0x83000000) { 4447 val32 |= FPGA_RF_MODE_CCK; 4448 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 4449 } 4450 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) { 4451 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); 4452 } 4453 4454 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); 4455 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; 4456 /* ack for xmit mgmt frames. */ 4457 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); 4458 4459 if (priv->rtl_chip == RTL8192E) { 4460 /* 4461 * Fix LDPC rx hang issue. 4462 */ 4463 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); 4464 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); 4465 val32 &= 0xfff00fff; 4466 val32 |= 0x0007e000; 4467 rtl8xxxu_write32(priv, REG_AFE_MISC, val32); 4468 4469 /* 4470 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting 4471 * should be equal or CCK RSSI report may be incorrect 4472 */ 4473 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); 4474 priv->cck_agc_report_type = 4475 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR); 4476 4477 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2); 4478 if (priv->cck_agc_report_type != 4479 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) { 4480 if (priv->cck_agc_report_type) 4481 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4482 else 4483 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR; 4484 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32); 4485 } 4486 4487 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT); 4488 if (priv->cck_agc_report_type) 4489 val32 |= AGC_RPT_CCK; 4490 else 4491 val32 &= ~AGC_RPT_CCK; 4492 rtl8xxxu_write32(priv, REG_AGC_RPT, val32); 4493 } 4494 4495 if (priv->rtl_chip == RTL8710B) { 4496 /* 4497 * 0x76D[5:4] is Port0,Port1 Enable Bit. 4498 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver 4499 */ 4500 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B); 4501 val8 |= BIT(5) | BIT(4); 4502 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8); 4503 4504 /* Set 0x5c[8] and [2:0] = 1, LDO mode */ 4505 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B); 4506 val32 |= 0x107; 4507 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32); 4508 } 4509 4510 val32 = rtl8xxxu_read32(priv, 0xa9c); 4511 priv->cck_new_agc = u32_get_bits(val32, BIT(17)); 4512 4513 /* Initialise the center frequency offset tracking */ 4514 if (priv->fops->set_crystal_cap) { 4515 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 4516 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS; 4517 priv->cfo_tracking.adjust = true; 4518 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap; 4519 } 4520 4521 if (priv->rtl_chip == RTL8188E) 4522 rtl8188e_ra_info_init_all(&priv->ra_info); 4523 4524 set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map); 4525 set_bit(RTL8XXXU_BC_MC_MACID1, priv->mac_id_map); 4526 4527 exit: 4528 return ret; 4529 } 4530 4531 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, 4532 struct ieee80211_key_conf *key, const u8 *mac) 4533 { 4534 u32 cmd, val32, addr, ctrl; 4535 int j, i, tmp_debug; 4536 4537 tmp_debug = rtl8xxxu_debug; 4538 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) 4539 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; 4540 4541 /* 4542 * This is a bit of a hack - the lower bits of the cipher 4543 * suite selector happens to match the cipher index in the CAM 4544 */ 4545 addr = key->hw_key_idx << CAM_CMD_KEY_SHIFT; 4546 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; 4547 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 4548 ctrl |= BIT(6); 4549 4550 for (j = 5; j >= 0; j--) { 4551 switch (j) { 4552 case 0: 4553 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); 4554 break; 4555 case 1: 4556 val32 = mac[2] | (mac[3] << 8) | 4557 (mac[4] << 16) | (mac[5] << 24); 4558 break; 4559 default: 4560 i = (j - 2) << 2; 4561 val32 = key->key[i] | (key->key[i + 1] << 8) | 4562 key->key[i + 2] << 16 | key->key[i + 3] << 24; 4563 break; 4564 } 4565 4566 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); 4567 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); 4568 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); 4569 udelay(100); 4570 } 4571 4572 rtl8xxxu_debug = tmp_debug; 4573 } 4574 4575 static 4576 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, int radio_idx, u32 *tx_ant, 4577 u32 *rx_ant) 4578 { 4579 struct rtl8xxxu_priv *priv = hw->priv; 4580 4581 *tx_ant = BIT(priv->tx_paths) - 1; 4582 *rx_ant = BIT(priv->rx_paths) - 1; 4583 4584 return 0; 4585 } 4586 4587 static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 4588 bool set) 4589 { 4590 struct rtl8xxxu_priv *priv = hw->priv; 4591 4592 schedule_delayed_work(&priv->update_beacon_work, 0); 4593 4594 return 0; 4595 } 4596 4597 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, 4598 struct ieee80211_vif *vif, const u8 *mac) 4599 { 4600 struct rtl8xxxu_priv *priv = hw->priv; 4601 u8 val8; 4602 4603 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4604 val8 |= BEACON_DISABLE_TSF_UPDATE; 4605 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4606 } 4607 4608 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, 4609 struct ieee80211_vif *vif) 4610 { 4611 struct rtl8xxxu_priv *priv = hw->priv; 4612 u8 val8; 4613 4614 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 4615 val8 &= ~BEACON_DISABLE_TSF_UPDATE; 4616 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 4617 } 4618 4619 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 4620 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 4621 u8 macid) 4622 { 4623 struct h2c_cmd h2c; 4624 4625 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4626 4627 h2c.ramask.cmd = H2C_SET_RATE_MASK; 4628 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); 4629 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); 4630 4631 h2c.ramask.arg = 0x80; 4632 if (sgi) 4633 h2c.ramask.arg |= 0x20; 4634 4635 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", 4636 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); 4637 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); 4638 } 4639 4640 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 4641 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 4642 u8 macid) 4643 { 4644 struct h2c_cmd h2c; 4645 u8 bw; 4646 4647 if (txbw_40mhz) 4648 bw = RTL8XXXU_CHANNEL_WIDTH_40; 4649 else 4650 bw = RTL8XXXU_CHANNEL_WIDTH_20; 4651 4652 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4653 4654 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; 4655 h2c.b_macid_cfg.ramask0 = ramask & 0xff; 4656 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; 4657 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; 4658 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; 4659 h2c.b_macid_cfg.macid = macid; 4660 4661 h2c.b_macid_cfg.data1 = rateid; 4662 if (sgi) 4663 h2c.b_macid_cfg.data1 |= BIT(7); 4664 4665 h2c.b_macid_cfg.data2 = bw; 4666 4667 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", 4668 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); 4669 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); 4670 } 4671 4672 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 4673 u8 macid, u8 role, bool connect) 4674 { 4675 struct h2c_cmd h2c; 4676 4677 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4678 4679 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; 4680 4681 if (connect) 4682 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; 4683 else 4684 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; 4685 4686 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); 4687 } 4688 4689 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 4690 u8 macid, u8 role, bool connect) 4691 { 4692 /* 4693 * The firmware turns on the rate control when it knows it's 4694 * connected to a network. 4695 */ 4696 struct h2c_cmd h2c; 4697 4698 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4699 4700 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; 4701 if (connect) 4702 h2c.media_status_rpt.parm |= BIT(0); 4703 else 4704 h2c.media_status_rpt.parm &= ~BIT(0); 4705 4706 h2c.media_status_rpt.parm |= ((role << 4) & 0xf0); 4707 h2c.media_status_rpt.macid = macid; 4708 4709 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); 4710 } 4711 4712 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4713 { 4714 struct h2c_cmd h2c; 4715 const int h2c_size = 4; 4716 4717 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4718 4719 h2c.rssi_report.cmd = H2C_SET_RSSI; 4720 h2c.rssi_report.macid = macid; 4721 h2c.rssi_report.rssi = rssi; 4722 4723 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size); 4724 } 4725 4726 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 4727 { 4728 struct h2c_cmd h2c; 4729 int h2c_size = sizeof(h2c.rssi_report); 4730 4731 if (priv->rtl_chip == RTL8723B) 4732 h2c_size = 4; 4733 4734 memset(&h2c, 0, sizeof(struct h2c_cmd)); 4735 4736 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING; 4737 h2c.rssi_report.macid = macid; 4738 h2c.rssi_report.rssi = rssi; 4739 4740 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size); 4741 } 4742 4743 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) 4744 { 4745 u8 agg_ctrl, usb_spec, page_thresh, timeout; 4746 4747 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 4748 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 4749 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 4750 4751 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 4752 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 4753 4754 if (!rtl8xxxu_dma_aggregation) { 4755 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4756 return; 4757 } 4758 4759 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; 4760 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 4761 4762 /* 4763 * The number of packets we can take looks to be buffer size / 512 4764 * which matches the 512 byte rounding we have to do when de-muxing 4765 * the packets. 4766 * 4767 * Sample numbers from the vendor driver: 4768 * USB High-Speed mode values: 4769 * RxAggBlockCount = 8 : 512 byte unit 4770 * RxAggBlockTimeout = 6 4771 * RxAggPageCount = 48 : 128 byte unit 4772 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) 4773 */ 4774 4775 page_thresh = (priv->fops->rx_agg_buf_size / 512); 4776 if (rtl8xxxu_dma_agg_pages >= 0) { 4777 if (rtl8xxxu_dma_agg_pages <= page_thresh) 4778 timeout = page_thresh; 4779 else if (rtl8xxxu_dma_agg_pages <= 6) 4780 dev_err(&priv->udev->dev, 4781 "%s: dma_agg_pages=%i too small, minimum is 6\n", 4782 __func__, rtl8xxxu_dma_agg_pages); 4783 else 4784 dev_err(&priv->udev->dev, 4785 "%s: dma_agg_pages=%i larger than limit %i\n", 4786 __func__, rtl8xxxu_dma_agg_pages, page_thresh); 4787 } 4788 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); 4789 /* 4790 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on 4791 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we 4792 * don't set it, so better set both. 4793 */ 4794 timeout = 4; 4795 4796 if (rtl8xxxu_dma_agg_timeout >= 0) { 4797 if (rtl8xxxu_dma_agg_timeout <= 127) 4798 timeout = rtl8xxxu_dma_agg_timeout; 4799 else 4800 dev_err(&priv->udev->dev, 4801 "%s: Invalid dma_agg_timeout: %i\n", 4802 __func__, rtl8xxxu_dma_agg_timeout); 4803 } 4804 4805 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); 4806 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); 4807 priv->rx_buf_aggregation = 1; 4808 } 4809 4810 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { 4811 {.bitrate = 10, .hw_value = 0x00,}, 4812 {.bitrate = 20, .hw_value = 0x01,}, 4813 {.bitrate = 55, .hw_value = 0x02,}, 4814 {.bitrate = 110, .hw_value = 0x03,}, 4815 {.bitrate = 60, .hw_value = 0x04,}, 4816 {.bitrate = 90, .hw_value = 0x05,}, 4817 {.bitrate = 120, .hw_value = 0x06,}, 4818 {.bitrate = 180, .hw_value = 0x07,}, 4819 {.bitrate = 240, .hw_value = 0x08,}, 4820 {.bitrate = 360, .hw_value = 0x09,}, 4821 {.bitrate = 480, .hw_value = 0x0a,}, 4822 {.bitrate = 540, .hw_value = 0x0b,}, 4823 }; 4824 4825 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) 4826 { 4827 if (rate <= DESC_RATE_54M) 4828 return; 4829 4830 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { 4831 if (rate < DESC_RATE_MCS8) 4832 *nss = 1; 4833 else 4834 *nss = 2; 4835 *mcs = rate - DESC_RATE_MCS0; 4836 } 4837 } 4838 4839 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) 4840 { 4841 struct ieee80211_hw *hw = priv->hw; 4842 u32 val32; 4843 u8 rate_idx = 0; 4844 4845 rate_cfg &= RESPONSE_RATE_BITMAP_ALL; 4846 4847 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 4848 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) 4849 val32 &= RESPONSE_RATE_RRSR_INIT_5G; 4850 else 4851 val32 &= RESPONSE_RATE_RRSR_INIT_2G; 4852 val32 |= rate_cfg; 4853 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 4854 4855 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); 4856 4857 if (rate_cfg) 4858 rate_idx = __fls(rate_cfg); 4859 4860 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); 4861 } 4862 4863 static u16 4864 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) 4865 { 4866 u16 network_type = WIRELESS_MODE_UNKNOWN; 4867 4868 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { 4869 if (sta->deflink.vht_cap.vht_supported) 4870 network_type = WIRELESS_MODE_AC; 4871 else if (sta->deflink.ht_cap.ht_supported) 4872 network_type = WIRELESS_MODE_N_5G; 4873 4874 network_type |= WIRELESS_MODE_A; 4875 } else { 4876 if (sta->deflink.vht_cap.vht_supported) 4877 network_type = WIRELESS_MODE_AC; 4878 else if (sta->deflink.ht_cap.ht_supported) 4879 network_type = WIRELESS_MODE_N_24G; 4880 4881 if (sta->deflink.supp_rates[0] <= 0xf) 4882 network_type |= WIRELESS_MODE_B; 4883 else if (sta->deflink.supp_rates[0] & 0xf) 4884 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); 4885 else 4886 network_type |= WIRELESS_MODE_G; 4887 } 4888 4889 return network_type; 4890 } 4891 4892 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) 4893 { 4894 u32 reg_edca_param[IEEE80211_NUM_ACS] = { 4895 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, 4896 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, 4897 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, 4898 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, 4899 }; 4900 u32 val32; 4901 u16 wireless_mode = 0; 4902 u8 aifs, aifsn, sifs; 4903 int i; 4904 4905 for (i = 0; i < ARRAY_SIZE(priv->vifs); i++) { 4906 struct ieee80211_sta *sta; 4907 4908 if (!priv->vifs[i]) 4909 continue; 4910 4911 rcu_read_lock(); 4912 sta = ieee80211_find_sta(priv->vifs[i], priv->vifs[i]->bss_conf.bssid); 4913 if (sta) 4914 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); 4915 rcu_read_unlock(); 4916 4917 if (wireless_mode) 4918 break; 4919 } 4920 4921 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || 4922 (wireless_mode & WIRELESS_MODE_N_24G)) 4923 sifs = 16; 4924 else 4925 sifs = 10; 4926 4927 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 4928 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); 4929 4930 /* It was set in conf_tx. */ 4931 aifsn = val32 & 0xff; 4932 4933 /* aifsn not set yet or already fixed */ 4934 if (aifsn < 2 || aifsn > 15) 4935 continue; 4936 4937 aifs = aifsn * slot_time + sifs; 4938 4939 val32 &= ~0xff; 4940 val32 |= aifs; 4941 rtl8xxxu_write32(priv, reg_edca_param[i], val32); 4942 } 4943 } 4944 4945 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 4946 u8 rate, u8 sgi, u8 bw) 4947 { 4948 u8 mcs, nss; 4949 4950 rarpt->txrate.flags = 0; 4951 4952 if (rate <= DESC_RATE_54M) { 4953 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate; 4954 } else { 4955 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); 4956 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; 4957 4958 rarpt->txrate.mcs = mcs; 4959 rarpt->txrate.nss = nss; 4960 4961 if (sgi) 4962 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 4963 4964 rarpt->txrate.bw = bw; 4965 } 4966 4967 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); 4968 rarpt->desc_rate = rate; 4969 } 4970 4971 static void 4972 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4973 struct ieee80211_bss_conf *bss_conf, u64 changed) 4974 { 4975 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 4976 struct rtl8xxxu_priv *priv = hw->priv; 4977 struct device *dev = &priv->udev->dev; 4978 struct rtl8xxxu_sta_info *sta_info; 4979 struct ieee80211_sta *sta; 4980 struct rtl8xxxu_ra_report *rarpt; 4981 u8 val8, macid; 4982 u32 val32; 4983 4984 rarpt = &priv->ra_report; 4985 4986 if (changed & BSS_CHANGED_ASSOC) { 4987 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc); 4988 4989 rtl8xxxu_set_linktype(priv, vif->type, rtlvif->port_num); 4990 4991 if (vif->cfg.assoc) { 4992 u32 ramask; 4993 int sgi = 0; 4994 u8 highest_rate; 4995 u8 bw; 4996 4997 rcu_read_lock(); 4998 sta = ieee80211_find_sta(vif, bss_conf->bssid); 4999 if (!sta) { 5000 dev_info(dev, "%s: ASSOC no sta found\n", 5001 __func__); 5002 rcu_read_unlock(); 5003 goto error; 5004 } 5005 macid = rtl8xxxu_get_macid(priv, sta); 5006 5007 if (sta->deflink.ht_cap.ht_supported) 5008 dev_info(dev, "%s: HT supported\n", __func__); 5009 if (sta->deflink.vht_cap.vht_supported) 5010 dev_info(dev, "%s: VHT supported\n", __func__); 5011 5012 /* TODO: Set bits 28-31 for rate adaptive id */ 5013 ramask = (sta->deflink.supp_rates[0] & 0xfff) | 5014 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 | 5015 sta->deflink.ht_cap.mcs.rx_mask[1] << 20; 5016 if (sta->deflink.ht_cap.cap & 5017 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 5018 sgi = 1; 5019 5020 highest_rate = fls(ramask) - 1; 5021 if (rtl8xxxu_ht40_2g && 5022 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) 5023 bw = RATE_INFO_BW_40; 5024 else 5025 bw = RATE_INFO_BW_20; 5026 5027 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 5028 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; 5029 rcu_read_unlock(); 5030 5031 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw); 5032 5033 priv->fops->update_rate_mask(priv, ramask, 0, sgi, 5034 bw == RATE_INFO_BW_40, macid); 5035 5036 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); 5037 5038 if (rtlvif->port_num == 0) 5039 rtl8xxxu_stop_tx_beacon(priv); 5040 5041 /* joinbss sequence */ 5042 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, 5043 0xc000 | vif->cfg.aid); 5044 5045 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true); 5046 } else { 5047 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 5048 val8 |= BEACON_DISABLE_TSF_UPDATE; 5049 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 5050 5051 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false); 5052 } 5053 } 5054 5055 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 5056 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", 5057 bss_conf->use_short_preamble); 5058 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 5059 if (bss_conf->use_short_preamble) 5060 val32 |= RSR_ACK_SHORT_PREAMBLE; 5061 else 5062 val32 &= ~RSR_ACK_SHORT_PREAMBLE; 5063 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 5064 } 5065 5066 if (changed & BSS_CHANGED_ERP_SLOT) { 5067 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", 5068 bss_conf->use_short_slot); 5069 5070 if (bss_conf->use_short_slot) 5071 val8 = 9; 5072 else 5073 val8 = 20; 5074 rtl8xxxu_write8(priv, REG_SLOT, val8); 5075 5076 rtl8xxxu_set_aifs(priv, val8); 5077 } 5078 5079 if (changed & BSS_CHANGED_BSSID) { 5080 dev_dbg(dev, "Changed BSSID!\n"); 5081 rtl8xxxu_set_bssid(priv, bss_conf->bssid, rtlvif->port_num); 5082 } 5083 5084 if (changed & BSS_CHANGED_BASIC_RATES) { 5085 dev_dbg(dev, "Changed BASIC_RATES!\n"); 5086 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); 5087 } 5088 5089 if (changed & BSS_CHANGED_BEACON_ENABLED) { 5090 if (bss_conf->enable_beacon) { 5091 rtl8xxxu_start_tx_beacon(priv); 5092 schedule_delayed_work(&priv->update_beacon_work, 0); 5093 } else { 5094 rtl8xxxu_stop_tx_beacon(priv); 5095 } 5096 } 5097 5098 if (changed & BSS_CHANGED_BEACON) 5099 schedule_delayed_work(&priv->update_beacon_work, 0); 5100 5101 error: 5102 return; 5103 } 5104 5105 static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5106 struct ieee80211_bss_conf *link_conf) 5107 { 5108 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 5109 struct rtl8xxxu_priv *priv = hw->priv; 5110 struct device *dev = &priv->udev->dev; 5111 5112 dev_dbg(dev, "Start AP mode\n"); 5113 rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid, rtlvif->port_num); 5114 rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int); 5115 priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true); 5116 5117 return 0; 5118 } 5119 5120 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) 5121 { 5122 u32 rtlqueue; 5123 5124 switch (queue) { 5125 case IEEE80211_AC_VO: 5126 rtlqueue = TXDESC_QUEUE_VO; 5127 break; 5128 case IEEE80211_AC_VI: 5129 rtlqueue = TXDESC_QUEUE_VI; 5130 break; 5131 case IEEE80211_AC_BE: 5132 rtlqueue = TXDESC_QUEUE_BE; 5133 break; 5134 case IEEE80211_AC_BK: 5135 rtlqueue = TXDESC_QUEUE_BK; 5136 break; 5137 default: 5138 rtlqueue = TXDESC_QUEUE_BE; 5139 } 5140 5141 return rtlqueue; 5142 } 5143 5144 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb) 5145 { 5146 u32 queue; 5147 5148 if (unlikely(ieee80211_is_beacon(hdr->frame_control))) 5149 queue = TXDESC_QUEUE_BEACON; 5150 else if (ieee80211_is_mgmt(hdr->frame_control)) 5151 queue = TXDESC_QUEUE_MGNT; 5152 else 5153 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); 5154 5155 return queue; 5156 } 5157 5158 /* 5159 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor 5160 * format. The descriptor checksum is still only calculated over the 5161 * initial 32 bytes of the descriptor! 5162 */ 5163 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) 5164 { 5165 __le16 *ptr = (__le16 *)tx_desc; 5166 u16 csum = 0; 5167 int i; 5168 5169 /* 5170 * Clear csum field before calculation, as the csum field is 5171 * in the middle of the struct. 5172 */ 5173 tx_desc->csum = cpu_to_le16(0); 5174 5175 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) 5176 csum = csum ^ le16_to_cpu(ptr[i]); 5177 5178 tx_desc->csum |= cpu_to_le16(csum); 5179 } 5180 5181 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) 5182 { 5183 struct rtl8xxxu_tx_urb *tx_urb, *tmp; 5184 unsigned long flags; 5185 5186 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5187 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { 5188 list_del(&tx_urb->list); 5189 priv->tx_urb_free_count--; 5190 usb_free_urb(&tx_urb->urb); 5191 } 5192 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5193 } 5194 5195 static struct rtl8xxxu_tx_urb * 5196 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) 5197 { 5198 struct rtl8xxxu_tx_urb *tx_urb; 5199 unsigned long flags; 5200 5201 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5202 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, 5203 struct rtl8xxxu_tx_urb, list); 5204 if (tx_urb) { 5205 list_del(&tx_urb->list); 5206 priv->tx_urb_free_count--; 5207 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && 5208 !priv->tx_stopped) { 5209 priv->tx_stopped = true; 5210 ieee80211_stop_queues(priv->hw); 5211 } 5212 } 5213 5214 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5215 5216 return tx_urb; 5217 } 5218 5219 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, 5220 struct rtl8xxxu_tx_urb *tx_urb) 5221 { 5222 unsigned long flags; 5223 5224 INIT_LIST_HEAD(&tx_urb->list); 5225 5226 spin_lock_irqsave(&priv->tx_urb_lock, flags); 5227 5228 list_add(&tx_urb->list, &priv->tx_urb_free_list); 5229 priv->tx_urb_free_count++; 5230 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && 5231 priv->tx_stopped) { 5232 priv->tx_stopped = false; 5233 ieee80211_wake_queues(priv->hw); 5234 } 5235 5236 spin_unlock_irqrestore(&priv->tx_urb_lock, flags); 5237 } 5238 5239 static void rtl8xxxu_tx_complete(struct urb *urb) 5240 { 5241 struct sk_buff *skb = (struct sk_buff *)urb->context; 5242 struct ieee80211_tx_info *tx_info; 5243 struct ieee80211_hw *hw; 5244 struct rtl8xxxu_priv *priv; 5245 struct rtl8xxxu_tx_urb *tx_urb = 5246 container_of(urb, struct rtl8xxxu_tx_urb, urb); 5247 5248 tx_info = IEEE80211_SKB_CB(skb); 5249 hw = tx_info->rate_driver_data[0]; 5250 priv = hw->priv; 5251 5252 skb_pull(skb, priv->fops->tx_desc_size); 5253 5254 ieee80211_tx_info_clear_status(tx_info); 5255 tx_info->status.rates[0].idx = -1; 5256 tx_info->status.rates[0].count = 0; 5257 5258 if (!urb->status) 5259 tx_info->flags |= IEEE80211_TX_STAT_ACK; 5260 5261 ieee80211_tx_status_irqsafe(hw, skb); 5262 5263 rtl8xxxu_free_tx_urb(priv, tx_urb); 5264 } 5265 5266 static void rtl8xxxu_dump_action(struct device *dev, 5267 struct ieee80211_hdr *hdr) 5268 { 5269 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 5270 u16 cap, timeout; 5271 5272 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) 5273 return; 5274 5275 switch (mgmt->u.action.u.addba_resp.action_code) { 5276 case WLAN_ACTION_ADDBA_RESP: 5277 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); 5278 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); 5279 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " 5280 "timeout %i, tid %02x, buf_size %02x, policy %02x, " 5281 "status %02x\n", 5282 timeout, 5283 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5284 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5285 (cap >> 1) & 0x1, 5286 le16_to_cpu(mgmt->u.action.u.addba_resp.status)); 5287 break; 5288 case WLAN_ACTION_ADDBA_REQ: 5289 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 5290 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); 5291 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " 5292 "timeout %i, tid %02x, buf_size %02x, policy %02x\n", 5293 timeout, 5294 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, 5295 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, 5296 (cap >> 1) & 0x1); 5297 break; 5298 default: 5299 dev_info(dev, "action frame %02x\n", 5300 mgmt->u.action.u.addba_resp.action_code); 5301 break; 5302 } 5303 } 5304 5305 /* 5306 * Fill in v1 (gen1) specific TX descriptor bits. 5307 * This format is used on 8188cu/8192cu/8723au 5308 */ 5309 void 5310 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5311 struct ieee80211_tx_info *tx_info, 5312 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5313 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5314 u8 macid) 5315 { 5316 struct rtl8xxxu_priv *priv = hw->priv; 5317 struct device *dev = &priv->udev->dev; 5318 u8 *qc = ieee80211_get_qos_ctl(hdr); 5319 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5320 u32 rate = 0; 5321 u16 seq_number; 5322 5323 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5324 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5325 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5326 5327 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5328 5329 tx_desc->txdw5 = cpu_to_le32(rate); 5330 5331 if (ieee80211_is_data(hdr->frame_control)) 5332 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5333 5334 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5335 5336 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5337 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); 5338 else 5339 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); 5340 5341 if (ieee80211_is_mgmt(hdr->frame_control)) { 5342 tx_desc->txdw5 = cpu_to_le32(rate); 5343 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5344 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5345 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5346 } 5347 5348 if (ieee80211_is_data_qos(hdr->frame_control)) 5349 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5350 5351 if (short_preamble) 5352 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5353 5354 if (sgi) 5355 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5356 5357 /* 5358 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5359 */ 5360 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5361 if (ampdu_enable || tx_info->control.use_rts) { 5362 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5363 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5364 } else if (tx_info->control.use_cts_prot) { 5365 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5366 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5367 } 5368 } 5369 5370 /* 5371 * Fill in v2 (gen2) specific TX descriptor bits. 5372 * This format is used on 8192eu/8723bu 5373 */ 5374 void 5375 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5376 struct ieee80211_tx_info *tx_info, 5377 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 5378 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5379 u8 macid) 5380 { 5381 struct rtl8xxxu_priv *priv = hw->priv; 5382 struct device *dev = &priv->udev->dev; 5383 struct rtl8xxxu_txdesc40 *tx_desc40; 5384 u8 *qc = ieee80211_get_qos_ctl(hdr); 5385 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5386 u32 rate = 0; 5387 u16 seq_number; 5388 5389 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; 5390 5391 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5392 dev_info(dev, "%s: TX rate: %d, pkt size %u\n", 5393 __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); 5394 5395 tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT); 5396 5397 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5398 5399 tx_desc40->txdw4 = cpu_to_le32(rate); 5400 if (ieee80211_is_data(hdr->frame_control)) { 5401 tx_desc40->txdw4 |= cpu_to_le32(0x1f << 5402 TXDESC40_DATA_RATE_FB_SHIFT); 5403 } 5404 5405 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); 5406 5407 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5408 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5409 else 5410 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5411 5412 if (ieee80211_is_mgmt(hdr->frame_control)) { 5413 tx_desc40->txdw4 = cpu_to_le32(rate); 5414 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); 5415 tx_desc40->txdw4 |= 5416 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); 5417 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); 5418 } 5419 5420 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 5421 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE); 5422 5423 if (short_preamble) 5424 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); 5425 5426 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); 5427 5428 /* 5429 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5430 */ 5431 if (ampdu_enable || tx_info->control.use_rts) { 5432 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); 5433 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); 5434 } else if (tx_info->control.use_cts_prot) { 5435 /* 5436 * For some reason the vendor driver doesn't set 5437 * TXDESC40_HW_RTS_ENABLE for CTS to SELF 5438 */ 5439 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); 5440 } 5441 } 5442 5443 /* 5444 * Fill in v3 (gen1) specific TX descriptor bits. 5445 * This format is a hybrid between the v1 and v2 formats, only seen 5446 * on 8188eu devices so far. 5447 */ 5448 void 5449 rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 5450 struct ieee80211_tx_info *tx_info, 5451 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 5452 bool short_preamble, bool ampdu_enable, u32 rts_rate, 5453 u8 macid) 5454 { 5455 struct rtl8xxxu_priv *priv = hw->priv; 5456 struct device *dev = &priv->udev->dev; 5457 struct rtl8xxxu_ra_info *ra = &priv->ra_info; 5458 u8 *qc = ieee80211_get_qos_ctl(hdr); 5459 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5460 u32 rate = 0; 5461 u16 seq_number; 5462 5463 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 5464 5465 if (ieee80211_is_data(hdr->frame_control)) { 5466 rate = ra->decision_rate; 5467 tx_desc->txdw5 = cpu_to_le32(rate); 5468 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5469 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK); 5470 /* Data/RTS rate FB limit */ 5471 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); 5472 } 5473 5474 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) 5475 dev_info(dev, "%s: TX rate: %d, pkt size %d\n", 5476 __func__, rate, le16_to_cpu(tx_desc->pkt_size)); 5477 5478 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); 5479 5480 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) 5481 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); 5482 else 5483 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); 5484 5485 if (ieee80211_is_mgmt(hdr->frame_control)) { 5486 tx_desc->txdw5 = cpu_to_le32(rate); 5487 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); 5488 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); 5489 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); 5490 } 5491 5492 if (ieee80211_is_data_qos(hdr->frame_control)) { 5493 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); 5494 5495 if (conf_is_ht40(&hw->conf)) { 5496 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW); 5497 5498 if (conf_is_ht40_minus(&hw->conf)) 5499 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER); 5500 else 5501 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER); 5502 } 5503 } 5504 5505 if (short_preamble) 5506 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); 5507 5508 if (sgi && ra->rate_sgi) 5509 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); 5510 5511 /* 5512 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled 5513 */ 5514 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); 5515 if (ampdu_enable || tx_info->control.use_rts) { 5516 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); 5517 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5518 } else if (tx_info->control.use_cts_prot) { 5519 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); 5520 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); 5521 } 5522 5523 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A | 5524 TXDESC_ANTENNA_SELECT_B); 5525 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16); 5526 } 5527 5528 static void rtl8xxxu_tx(struct ieee80211_hw *hw, 5529 struct ieee80211_tx_control *control, 5530 struct sk_buff *skb) 5531 { 5532 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 5533 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 5534 struct rtl8xxxu_priv *priv = hw->priv; 5535 struct rtl8xxxu_txdesc32 *tx_desc; 5536 struct rtl8xxxu_tx_urb *tx_urb; 5537 struct ieee80211_sta *sta = NULL; 5538 struct ieee80211_vif *vif = tx_info->control.vif; 5539 struct rtl8xxxu_vif *rtlvif = vif ? (struct rtl8xxxu_vif *)vif->drv_priv : NULL; 5540 struct device *dev = &priv->udev->dev; 5541 u32 queue, rts_rate; 5542 u16 pktlen = skb->len; 5543 int tx_desc_size = priv->fops->tx_desc_size; 5544 u8 macid; 5545 int ret; 5546 bool ampdu_enable, sgi = false, short_preamble = false, bmc = false; 5547 5548 if (skb_headroom(skb) < tx_desc_size) { 5549 dev_warn(dev, 5550 "%s: Not enough headroom (%i) for tx descriptor\n", 5551 __func__, skb_headroom(skb)); 5552 goto error; 5553 } 5554 5555 if (unlikely(skb->len > (65535 - tx_desc_size))) { 5556 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", 5557 __func__, skb->len); 5558 goto error; 5559 } 5560 5561 tx_urb = rtl8xxxu_alloc_tx_urb(priv); 5562 if (!tx_urb) { 5563 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); 5564 goto error; 5565 } 5566 5567 if (ieee80211_is_action(hdr->frame_control)) 5568 rtl8xxxu_dump_action(dev, hdr); 5569 5570 tx_info->rate_driver_data[0] = hw; 5571 5572 if (control && control->sta) 5573 sta = control->sta; 5574 5575 queue = rtl8xxxu_queue_select(hdr, skb); 5576 5577 tx_desc = skb_push(skb, tx_desc_size); 5578 5579 memset(tx_desc, 0, tx_desc_size); 5580 tx_desc->pkt_size = cpu_to_le16(pktlen); 5581 tx_desc->pkt_offset = tx_desc_size; 5582 5583 /* These bits mean different things to the RTL8192F. */ 5584 if (priv->rtl_chip != RTL8192F) 5585 tx_desc->txdw0 = 5586 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; 5587 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 5588 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) { 5589 tx_desc->txdw0 |= TXDESC_BROADMULTICAST; 5590 bmc = true; 5591 } 5592 5593 5594 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); 5595 macid = rtl8xxxu_get_macid(priv, sta); 5596 5597 if (tx_info->control.hw_key) { 5598 switch (tx_info->control.hw_key->cipher) { 5599 case WLAN_CIPHER_SUITE_WEP40: 5600 case WLAN_CIPHER_SUITE_WEP104: 5601 case WLAN_CIPHER_SUITE_TKIP: 5602 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); 5603 break; 5604 case WLAN_CIPHER_SUITE_CCMP: 5605 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); 5606 break; 5607 default: 5608 break; 5609 } 5610 if (bmc && rtlvif && rtlvif->hw_key_idx != 0xff) { 5611 tx_desc->txdw1 |= cpu_to_le32(TXDESC_EN_DESC_ID); 5612 macid = rtlvif->hw_key_idx; 5613 } 5614 } 5615 5616 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ 5617 ampdu_enable = false; 5618 if (ieee80211_is_data_qos(hdr->frame_control) && sta) { 5619 if (sta->deflink.ht_cap.ht_supported) { 5620 u32 ampdu, val32; 5621 u8 *qc = ieee80211_get_qos_ctl(hdr); 5622 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 5623 5624 ampdu = (u32)sta->deflink.ht_cap.ampdu_density; 5625 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; 5626 tx_desc->txdw2 |= cpu_to_le32(val32); 5627 5628 ampdu_enable = true; 5629 5630 if (!test_bit(tid, priv->tx_aggr_started) && 5631 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) 5632 if (!ieee80211_start_tx_ba_session(sta, tid, 0)) 5633 set_bit(tid, priv->tx_aggr_started); 5634 } 5635 } 5636 5637 if (ieee80211_is_data_qos(hdr->frame_control) && 5638 sta && sta->deflink.ht_cap.cap & 5639 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 5640 sgi = true; 5641 5642 if (sta && vif && vif->bss_conf.use_short_preamble) 5643 short_preamble = true; 5644 5645 if (skb->len > hw->wiphy->rts_threshold) 5646 tx_info->control.use_rts = true; 5647 5648 if (sta && vif && vif->bss_conf.use_cts_prot) 5649 tx_info->control.use_cts_prot = true; 5650 5651 if (ampdu_enable || tx_info->control.use_rts || 5652 tx_info->control.use_cts_prot) 5653 rts_rate = DESC_RATE_24M; 5654 else 5655 rts_rate = 0; 5656 5657 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, 5658 ampdu_enable, rts_rate, macid); 5659 5660 rtl8xxxu_calc_tx_desc_csum(tx_desc); 5661 5662 /* avoid zero checksum make tx hang */ 5663 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) 5664 tx_desc->csum = ~tx_desc->csum; 5665 5666 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], 5667 skb->data, skb->len, rtl8xxxu_tx_complete, skb); 5668 5669 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); 5670 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); 5671 if (ret) { 5672 usb_unanchor_urb(&tx_urb->urb); 5673 rtl8xxxu_free_tx_urb(priv, tx_urb); 5674 goto error; 5675 } 5676 return; 5677 error: 5678 dev_kfree_skb(skb); 5679 } 5680 5681 static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw, 5682 struct ieee80211_vif *vif) 5683 { 5684 struct rtl8xxxu_priv *priv = hw->priv; 5685 struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0); 5686 struct device *dev = &priv->udev->dev; 5687 int retry; 5688 u8 val8; 5689 5690 /* BCN_VALID, write 1 to clear, cleared by SW */ 5691 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); 5692 val8 |= BIT_BCN_VALID >> 16; 5693 rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8); 5694 5695 /* SW_BCN_SEL - Port0 */ 5696 val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2); 5697 val8 &= ~(BIT_SW_BCN_SEL >> 16); 5698 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8); 5699 5700 if (skb) 5701 rtl8xxxu_tx(hw, NULL, skb); 5702 5703 retry = 100; 5704 do { 5705 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); 5706 if (val8 & (BIT_BCN_VALID >> 16)) 5707 break; 5708 usleep_range(10, 20); 5709 } while (--retry); 5710 5711 if (!retry) 5712 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__); 5713 } 5714 5715 static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work) 5716 { 5717 struct rtl8xxxu_priv *priv = 5718 container_of(work, struct rtl8xxxu_priv, update_beacon_work.work); 5719 struct ieee80211_hw *hw = priv->hw; 5720 struct ieee80211_vif *vif = priv->vifs[0]; 5721 5722 if (!vif) { 5723 WARN_ONCE(true, "no vif to update beacon\n"); 5724 return; 5725 } 5726 5727 if (vif->bss_conf.csa_active) { 5728 if (ieee80211_beacon_cntdwn_is_complete(vif, 0)) { 5729 ieee80211_csa_finish(vif, 0); 5730 return; 5731 } 5732 schedule_delayed_work(&priv->update_beacon_work, 5733 msecs_to_jiffies(vif->bss_conf.beacon_int)); 5734 } 5735 rtl8xxxu_send_beacon_frame(hw, vif); 5736 } 5737 5738 static inline bool rtl8xxxu_is_packet_match_bssid(struct rtl8xxxu_priv *priv, 5739 struct ieee80211_hdr *hdr, 5740 int port_num) 5741 { 5742 return priv->vifs[port_num] && 5743 priv->vifs[port_num]->type == NL80211_IFTYPE_STATION && 5744 priv->vifs[port_num]->cfg.assoc && 5745 ether_addr_equal(priv->vifs[port_num]->bss_conf.bssid, hdr->addr2); 5746 } 5747 5748 static inline bool rtl8xxxu_is_sta_sta(struct rtl8xxxu_priv *priv) 5749 { 5750 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc && 5751 priv->vifs[0]->type == NL80211_IFTYPE_STATION) && 5752 (priv->vifs[1] && priv->vifs[1]->cfg.assoc && 5753 priv->vifs[1]->type == NL80211_IFTYPE_STATION); 5754 } 5755 5756 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5757 struct ieee80211_rx_status *rx_status, 5758 struct rtl8723au_phy_stats *phy_stats, 5759 u32 rxmcs, struct ieee80211_hdr *hdr, 5760 bool crc_icv_err) 5761 { 5762 if (phy_stats->sgi_en) 5763 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 5764 5765 if (rxmcs < DESC_RATE_6M) { 5766 /* 5767 * Handle PHY stats for CCK rates 5768 */ 5769 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats); 5770 } else { 5771 bool parse_cfo = priv->fops->set_crystal_cap && 5772 !crc_icv_err && 5773 !ieee80211_is_ctl(hdr->frame_control) && 5774 !rtl8xxxu_is_sta_sta(priv) && 5775 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || 5776 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); 5777 5778 if (parse_cfo) { 5779 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0]; 5780 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1]; 5781 5782 priv->cfo_tracking.packet_count++; 5783 } 5784 5785 rx_status->signal = 5786 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; 5787 } 5788 } 5789 5790 static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv, 5791 struct ieee80211_rx_status *rx_status, 5792 struct jaguar2_phy_stats_type0 *phy_stats0, 5793 u32 rxmcs, struct ieee80211_hdr *hdr, 5794 bool crc_icv_err) 5795 { 5796 s8 rx_power = phy_stats0->pwdb - 110; 5797 5798 if (!priv->cck_new_agc) 5799 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0); 5800 5801 rx_status->signal = rx_power; 5802 } 5803 5804 static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv, 5805 struct ieee80211_rx_status *rx_status, 5806 struct jaguar2_phy_stats_type1 *phy_stats1, 5807 u32 rxmcs, struct ieee80211_hdr *hdr, 5808 bool crc_icv_err) 5809 { 5810 bool parse_cfo = priv->fops->set_crystal_cap && 5811 !crc_icv_err && 5812 !ieee80211_is_ctl(hdr->frame_control) && 5813 !rtl8xxxu_is_sta_sta(priv) && 5814 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || 5815 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); 5816 u8 pwdb_max = 0; 5817 int rx_path; 5818 5819 if (parse_cfo) { 5820 /* Only path-A and path-B have CFO tail and short CFO */ 5821 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A]; 5822 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B]; 5823 5824 priv->cfo_tracking.packet_count++; 5825 } 5826 5827 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5828 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]); 5829 5830 rx_status->signal = pwdb_max - 110; 5831 } 5832 5833 static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv, 5834 struct ieee80211_rx_status *rx_status, 5835 struct jaguar2_phy_stats_type2 *phy_stats2, 5836 u32 rxmcs, struct ieee80211_hdr *hdr, 5837 bool crc_icv_err) 5838 { 5839 u8 pwdb_max = 0; 5840 int rx_path; 5841 5842 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) 5843 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]); 5844 5845 rx_status->signal = pwdb_max - 110; 5846 } 5847 5848 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 5849 struct ieee80211_rx_status *rx_status, 5850 struct rtl8723au_phy_stats *phy_stats, 5851 u32 rxmcs, struct ieee80211_hdr *hdr, 5852 bool crc_icv_err) 5853 { 5854 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; 5855 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats; 5856 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats; 5857 5858 switch (phy_stats0->page_num) { 5859 case 0: 5860 /* CCK */ 5861 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0, 5862 rxmcs, hdr, crc_icv_err); 5863 break; 5864 case 1: 5865 /* OFDM */ 5866 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1, 5867 rxmcs, hdr, crc_icv_err); 5868 break; 5869 case 2: 5870 /* Also OFDM but different (how?) */ 5871 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2, 5872 rxmcs, hdr, crc_icv_err); 5873 break; 5874 default: 5875 return; 5876 } 5877 } 5878 5879 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) 5880 { 5881 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5882 unsigned long flags; 5883 5884 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5885 5886 list_for_each_entry_safe(rx_urb, tmp, 5887 &priv->rx_urb_pending_list, list) { 5888 list_del(&rx_urb->list); 5889 priv->rx_urb_pending_count--; 5890 usb_free_urb(&rx_urb->urb); 5891 } 5892 5893 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5894 } 5895 5896 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, 5897 struct rtl8xxxu_rx_urb *rx_urb) 5898 { 5899 struct sk_buff *skb; 5900 unsigned long flags; 5901 int pending = 0; 5902 5903 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5904 5905 if (!priv->shutdown) { 5906 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); 5907 priv->rx_urb_pending_count++; 5908 pending = priv->rx_urb_pending_count; 5909 } else { 5910 skb = (struct sk_buff *)rx_urb->urb.context; 5911 dev_kfree_skb_irq(skb); 5912 usb_free_urb(&rx_urb->urb); 5913 } 5914 5915 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5916 5917 if (pending > RTL8XXXU_RX_URB_PENDING_WATER) 5918 schedule_work(&priv->rx_urb_wq); 5919 } 5920 5921 static void rtl8xxxu_rx_urb_work(struct work_struct *work) 5922 { 5923 struct rtl8xxxu_priv *priv; 5924 struct rtl8xxxu_rx_urb *rx_urb, *tmp; 5925 struct list_head local; 5926 struct sk_buff *skb; 5927 unsigned long flags; 5928 int ret; 5929 5930 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); 5931 INIT_LIST_HEAD(&local); 5932 5933 spin_lock_irqsave(&priv->rx_urb_lock, flags); 5934 5935 list_splice_init(&priv->rx_urb_pending_list, &local); 5936 priv->rx_urb_pending_count = 0; 5937 5938 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 5939 5940 list_for_each_entry_safe(rx_urb, tmp, &local, list) { 5941 list_del_init(&rx_urb->list); 5942 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 5943 /* 5944 * If out of memory or temporary error, put it back on the 5945 * queue and try again. Otherwise the device is dead/gone 5946 * and we should drop it. 5947 */ 5948 switch (ret) { 5949 case 0: 5950 break; 5951 case -ENOMEM: 5952 case -EAGAIN: 5953 rtl8xxxu_queue_rx_urb(priv, rx_urb); 5954 break; 5955 default: 5956 dev_warn(&priv->udev->dev, 5957 "failed to requeue urb with error %i\n", ret); 5958 skb = (struct sk_buff *)rx_urb->urb.context; 5959 dev_kfree_skb(skb); 5960 usb_free_urb(&rx_urb->urb); 5961 } 5962 } 5963 } 5964 5965 /* 5966 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type 5967 * 0-7 to represent writing different combinations of register values 5968 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use 5969 * cases which Realtek doesn't provide detail for these settings. Keep 5970 * this aligned with vendor driver for easier maintenance. 5971 */ 5972 static 5973 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) 5974 { 5975 switch (type) { 5976 case 0: 5977 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5978 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 5979 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5980 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5981 break; 5982 case 1: 5983 case 3: 5984 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 5985 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5986 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5987 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5988 break; 5989 case 2: 5990 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5991 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); 5992 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5993 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 5994 break; 5995 case 4: 5996 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 5997 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); 5998 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 5999 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 6000 break; 6001 case 5: 6002 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); 6003 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); 6004 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 6005 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 6006 break; 6007 case 6: 6008 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 6009 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 6010 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 6011 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 6012 break; 6013 case 7: 6014 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); 6015 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); 6016 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 6017 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 6018 break; 6019 default: 6020 break; 6021 } 6022 } 6023 6024 static 6025 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) 6026 { 6027 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; 6028 6029 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) 6030 btcoex->c2h_bt_inquiry = true; 6031 else 6032 btcoex->c2h_bt_inquiry = false; 6033 6034 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { 6035 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; 6036 btcoex->has_sco = false; 6037 btcoex->has_hid = false; 6038 btcoex->has_pan = false; 6039 btcoex->has_a2dp = false; 6040 } else { 6041 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) 6042 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; 6043 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || 6044 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) 6045 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; 6046 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) 6047 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; 6048 else 6049 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; 6050 6051 if (bt_info & BT_INFO_8723B_1ANT_B_FTP) 6052 btcoex->has_pan = true; 6053 else 6054 btcoex->has_pan = false; 6055 6056 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) 6057 btcoex->has_a2dp = true; 6058 else 6059 btcoex->has_a2dp = false; 6060 6061 if (bt_info & BT_INFO_8723B_1ANT_B_HID) 6062 btcoex->has_hid = true; 6063 else 6064 btcoex->has_hid = false; 6065 6066 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) 6067 btcoex->has_sco = true; 6068 else 6069 btcoex->has_sco = false; 6070 } 6071 6072 if (!btcoex->has_a2dp && !btcoex->has_sco && 6073 !btcoex->has_pan && btcoex->has_hid) 6074 btcoex->hid_only = true; 6075 else 6076 btcoex->hid_only = false; 6077 6078 if (!btcoex->has_sco && !btcoex->has_pan && 6079 !btcoex->has_hid && btcoex->has_a2dp) 6080 btcoex->has_a2dp = true; 6081 else 6082 btcoex->has_a2dp = false; 6083 6084 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || 6085 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) 6086 btcoex->bt_busy = true; 6087 else 6088 btcoex->bt_busy = false; 6089 } 6090 6091 static inline bool rtl8xxxu_is_assoc(struct rtl8xxxu_priv *priv) 6092 { 6093 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc) || 6094 (priv->vifs[1] && priv->vifs[1]->cfg.assoc); 6095 } 6096 6097 static 6098 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) 6099 { 6100 struct rtl8xxxu_btcoex *btcoex; 6101 6102 btcoex = &priv->bt_coex; 6103 6104 if (!rtl8xxxu_is_assoc(priv)) { 6105 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6106 rtl8723bu_set_coex_with_type(priv, 0); 6107 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { 6108 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); 6109 rtl8723bu_set_coex_with_type(priv, 4); 6110 } else if (btcoex->has_pan) { 6111 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); 6112 rtl8723bu_set_coex_with_type(priv, 4); 6113 } else { 6114 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6115 rtl8723bu_set_coex_with_type(priv, 7); 6116 } 6117 } 6118 6119 static 6120 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) 6121 { 6122 struct rtl8xxxu_btcoex *btcoex; 6123 6124 btcoex = &priv->bt_coex; 6125 6126 if (rtl8xxxu_is_assoc(priv)) { 6127 u32 val32 = 0; 6128 u32 high_prio_tx = 0, high_prio_rx = 0; 6129 6130 val32 = rtl8xxxu_read32(priv, 0x770); 6131 high_prio_tx = val32 & 0x0000ffff; 6132 high_prio_rx = (val32 & 0xffff0000) >> 16; 6133 6134 if (btcoex->bt_busy) { 6135 if (btcoex->hid_only) { 6136 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, 6137 0x3, 0x11, 0x11); 6138 rtl8723bu_set_coex_with_type(priv, 5); 6139 } else if (btcoex->a2dp_only) { 6140 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 6141 0x3, 0x11, 0x11); 6142 rtl8723bu_set_coex_with_type(priv, 4); 6143 } else if ((btcoex->has_a2dp && btcoex->has_pan) || 6144 (btcoex->has_hid && btcoex->has_a2dp && 6145 btcoex->has_pan)) { 6146 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 6147 0x3, 0x10, 0x10); 6148 rtl8723bu_set_coex_with_type(priv, 4); 6149 } else if (btcoex->has_hid && btcoex->has_a2dp) { 6150 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, 6151 0x3, 0x10, 0x10); 6152 rtl8723bu_set_coex_with_type(priv, 3); 6153 } else { 6154 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 6155 0x3, 0x11, 0x11); 6156 rtl8723bu_set_coex_with_type(priv, 4); 6157 } 6158 } else { 6159 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6160 if (high_prio_tx + high_prio_rx <= 60) 6161 rtl8723bu_set_coex_with_type(priv, 2); 6162 else 6163 rtl8723bu_set_coex_with_type(priv, 7); 6164 } 6165 } else { 6166 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); 6167 rtl8723bu_set_coex_with_type(priv, 0); 6168 } 6169 } 6170 6171 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) 6172 { 6173 struct rtl8xxxu_priv *priv; 6174 struct rtl8723bu_c2h *c2h; 6175 struct sk_buff *skb = NULL; 6176 u8 bt_info = 0; 6177 struct rtl8xxxu_btcoex *btcoex; 6178 struct rtl8xxxu_ra_report *rarpt; 6179 u8 bw; 6180 6181 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 6182 btcoex = &priv->bt_coex; 6183 rarpt = &priv->ra_report; 6184 6185 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 6186 skb = skb_dequeue(&priv->c2hcmd_queue); 6187 6188 c2h = (struct rtl8723bu_c2h *)skb->data; 6189 6190 switch (c2h->id) { 6191 case C2H_8723B_BT_INFO: 6192 bt_info = c2h->bt_info.bt_info; 6193 6194 rtl8723bu_update_bt_link_info(priv, bt_info); 6195 if (btcoex->c2h_bt_inquiry) { 6196 rtl8723bu_handle_bt_inquiry(priv); 6197 break; 6198 } 6199 rtl8723bu_handle_bt_info(priv); 6200 break; 6201 case C2H_8723B_RA_REPORT: 6202 bw = rarpt->txrate.bw; 6203 6204 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) { 6205 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40) 6206 bw = RATE_INFO_BW_40; 6207 else 6208 bw = RATE_INFO_BW_20; 6209 } 6210 6211 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate, 6212 c2h->ra_report.sgi, bw); 6213 break; 6214 default: 6215 break; 6216 } 6217 6218 dev_kfree_skb(skb); 6219 } 6220 } 6221 6222 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, 6223 struct sk_buff *skb) 6224 { 6225 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; 6226 struct device *dev = &priv->udev->dev; 6227 int len; 6228 6229 len = skb->len - 2; 6230 6231 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", 6232 c2h->id, c2h->seq, len, c2h->bt_info.response_source); 6233 6234 switch(c2h->id) { 6235 case C2H_8723B_BT_INFO: 6236 if (c2h->bt_info.response_source > 6237 BT_INFO_SRC_8723B_BT_ACTIVE_SEND) 6238 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); 6239 else 6240 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); 6241 6242 if (c2h->bt_info.bt_has_reset) 6243 dev_dbg(dev, "BT has been reset\n"); 6244 if (c2h->bt_info.tx_rx_mask) 6245 dev_dbg(dev, "BT TRx mask\n"); 6246 6247 break; 6248 case C2H_8723B_BT_MP_INFO: 6249 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", 6250 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); 6251 break; 6252 case C2H_8723B_RA_REPORT: 6253 dev_dbg(dev, 6254 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", 6255 c2h->ra_report.rate, c2h->ra_report.sgi, 6256 c2h->ra_report.macid, c2h->ra_report.noisy_state); 6257 break; 6258 default: 6259 dev_info(dev, "Unhandled C2H event %02x seq %02x\n", 6260 c2h->id, c2h->seq); 6261 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, 6262 16, 1, c2h->raw.payload, len, false); 6263 break; 6264 } 6265 6266 skb_queue_tail(&priv->c2hcmd_queue, skb); 6267 6268 schedule_work(&priv->c2hcmd_work); 6269 } 6270 6271 static void rtl8188e_c2hcmd_callback(struct work_struct *work) 6272 { 6273 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); 6274 struct device *dev = &priv->udev->dev; 6275 struct sk_buff *skb = NULL; 6276 struct rtl8xxxu_rxdesc16 *rx_desc; 6277 6278 while (!skb_queue_empty(&priv->c2hcmd_queue)) { 6279 skb = skb_dequeue(&priv->c2hcmd_queue); 6280 6281 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); 6282 6283 switch (rx_desc->rpt_sel) { 6284 case 1: 6285 dev_dbg(dev, "C2H TX report type 1\n"); 6286 6287 break; 6288 case 2: 6289 dev_dbg(dev, "C2H TX report type 2\n"); 6290 6291 rtl8188e_handle_ra_tx_report2(priv, skb); 6292 6293 break; 6294 case 3: 6295 dev_dbg(dev, "C2H USB interrupt report\n"); 6296 6297 break; 6298 default: 6299 dev_warn(dev, "%s: rpt_sel should not be %d\n", 6300 __func__, rx_desc->rpt_sel); 6301 6302 break; 6303 } 6304 6305 dev_kfree_skb(skb); 6306 } 6307 } 6308 6309 #define rtl8xxxu_iterate_vifs_atomic(priv, iterator, data) \ 6310 ieee80211_iterate_active_interfaces_atomic((priv)->hw, \ 6311 IEEE80211_IFACE_ITER_NORMAL, iterator, data) 6312 6313 struct rtl8xxxu_rx_update_rssi_data { 6314 struct rtl8xxxu_priv *priv; 6315 struct ieee80211_hdr *hdr; 6316 struct ieee80211_rx_status *rx_status; 6317 u8 *bssid; 6318 }; 6319 6320 static void rtl8xxxu_rx_update_rssi_iter(void *data, u8 *mac, 6321 struct ieee80211_vif *vif) 6322 { 6323 struct rtl8xxxu_rx_update_rssi_data *iter_data = data; 6324 struct ieee80211_sta *sta; 6325 struct ieee80211_hdr *hdr = iter_data->hdr; 6326 struct rtl8xxxu_priv *priv = iter_data->priv; 6327 struct rtl8xxxu_sta_info *sta_info; 6328 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 6329 u8 *bssid = iter_data->bssid; 6330 6331 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 6332 return; 6333 6334 if (!(ether_addr_equal(vif->addr, hdr->addr1) || 6335 ieee80211_is_beacon(hdr->frame_control))) 6336 return; 6337 6338 sta = ieee80211_find_sta_by_ifaddr(priv->hw, hdr->addr2, 6339 vif->addr); 6340 if (!sta) 6341 return; 6342 6343 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 6344 ewma_rssi_add(&sta_info->avg_rssi, -rx_status->signal); 6345 } 6346 6347 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6348 { 6349 __le16 fc = hdr->frame_control; 6350 u8 *bssid; 6351 6352 if (ieee80211_has_tods(fc)) 6353 bssid = hdr->addr1; 6354 else if (ieee80211_has_fromds(fc)) 6355 bssid = hdr->addr2; 6356 else 6357 bssid = hdr->addr3; 6358 6359 return bssid; 6360 } 6361 6362 static void rtl8xxxu_rx_update_rssi(struct rtl8xxxu_priv *priv, 6363 struct ieee80211_rx_status *rx_status, 6364 struct ieee80211_hdr *hdr) 6365 { 6366 struct rtl8xxxu_rx_update_rssi_data data = {}; 6367 6368 if (ieee80211_is_ctl(hdr->frame_control)) 6369 return; 6370 6371 data.priv = priv; 6372 data.hdr = hdr; 6373 data.rx_status = rx_status; 6374 data.bssid = get_hdr_bssid(hdr); 6375 6376 rtl8xxxu_iterate_vifs_atomic(priv, rtl8xxxu_rx_update_rssi_iter, &data); 6377 } 6378 6379 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6380 { 6381 struct ieee80211_hw *hw = priv->hw; 6382 struct ieee80211_rx_status *rx_status; 6383 struct rtl8xxxu_rxdesc16 *rx_desc; 6384 struct rtl8723au_phy_stats *phy_stats; 6385 struct sk_buff *next_skb = NULL; 6386 __le32 *_rx_desc_le; 6387 u32 *_rx_desc; 6388 int drvinfo_sz, desc_shift; 6389 int i, pkt_cnt, pkt_len, urb_len, pkt_offset; 6390 6391 urb_len = skb->len; 6392 pkt_cnt = 0; 6393 6394 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) { 6395 kfree_skb(skb); 6396 return RX_TYPE_ERROR; 6397 } 6398 6399 do { 6400 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; 6401 _rx_desc_le = (__le32 *)skb->data; 6402 _rx_desc = (u32 *)skb->data; 6403 6404 for (i = 0; 6405 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) 6406 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6407 6408 /* 6409 * Only read pkt_cnt from the header if we're parsing the 6410 * first packet 6411 */ 6412 if (!pkt_cnt) 6413 pkt_cnt = rx_desc->pkt_cnt; 6414 pkt_len = rx_desc->pktlen; 6415 6416 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6417 desc_shift = rx_desc->shift; 6418 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 6419 sizeof(struct rtl8xxxu_rxdesc16), 128); 6420 6421 /* 6422 * Only clone the skb if there's enough data at the end to 6423 * at least cover the rx descriptor 6424 */ 6425 if (pkt_cnt > 1 && 6426 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) 6427 next_skb = skb_clone(skb, GFP_ATOMIC); 6428 6429 rx_status = IEEE80211_SKB_RXCB(skb); 6430 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6431 6432 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); 6433 6434 if (rx_desc->rpt_sel) { 6435 skb_queue_tail(&priv->c2hcmd_queue, skb); 6436 schedule_work(&priv->c2hcmd_work); 6437 } else { 6438 struct ieee80211_hdr *hdr; 6439 6440 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6441 6442 skb_pull(skb, drvinfo_sz + desc_shift); 6443 6444 skb_trim(skb, pkt_len); 6445 6446 hdr = (struct ieee80211_hdr *)skb->data; 6447 if (rx_desc->phy_stats) { 6448 priv->fops->parse_phystats( 6449 priv, rx_status, phy_stats, 6450 rx_desc->rxmcs, 6451 hdr, 6452 rx_desc->crc32 || rx_desc->icverr); 6453 if (!rx_desc->crc32 && !rx_desc->icverr) 6454 rtl8xxxu_rx_update_rssi(priv, 6455 rx_status, 6456 hdr); 6457 } 6458 6459 rx_status->mactime = rx_desc->tsfl; 6460 rx_status->flag |= RX_FLAG_MACTIME_START; 6461 6462 if (!rx_desc->swdec && 6463 rx_desc->security != RX_DESC_ENC_NONE) 6464 rx_status->flag |= RX_FLAG_DECRYPTED; 6465 if (rx_desc->crc32) 6466 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6467 if (rx_desc->bw) 6468 rx_status->bw = RATE_INFO_BW_40; 6469 6470 if (rx_desc->rxht) { 6471 rx_status->encoding = RX_ENC_HT; 6472 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6473 } else { 6474 rx_status->rate_idx = rx_desc->rxmcs; 6475 } 6476 6477 rx_status->freq = hw->conf.chandef.chan->center_freq; 6478 rx_status->band = hw->conf.chandef.chan->band; 6479 6480 ieee80211_rx_irqsafe(hw, skb); 6481 } 6482 6483 skb = next_skb; 6484 if (skb) 6485 skb_pull(next_skb, pkt_offset); 6486 6487 pkt_cnt--; 6488 urb_len -= pkt_offset; 6489 next_skb = NULL; 6490 } while (skb && pkt_cnt > 0 && 6491 urb_len >= sizeof(struct rtl8xxxu_rxdesc16)); 6492 6493 return RX_TYPE_DATA_PKT; 6494 } 6495 6496 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 6497 { 6498 struct ieee80211_hw *hw = priv->hw; 6499 struct ieee80211_rx_status *rx_status; 6500 struct rtl8xxxu_rxdesc24 *rx_desc; 6501 struct rtl8723au_phy_stats *phy_stats; 6502 struct sk_buff *next_skb = NULL; 6503 __le32 *_rx_desc_le; 6504 u32 *_rx_desc; 6505 int drvinfo_sz, desc_shift; 6506 int i, pkt_len, urb_len, pkt_offset; 6507 6508 urb_len = skb->len; 6509 6510 if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) { 6511 kfree_skb(skb); 6512 return RX_TYPE_ERROR; 6513 } 6514 6515 do { 6516 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data; 6517 _rx_desc_le = (__le32 *)skb->data; 6518 _rx_desc = (u32 *)skb->data; 6519 6520 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) 6521 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); 6522 6523 pkt_len = rx_desc->pktlen; 6524 6525 drvinfo_sz = rx_desc->drvinfo_sz * 8; 6526 desc_shift = rx_desc->shift; 6527 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + 6528 sizeof(struct rtl8xxxu_rxdesc24), 8); 6529 6530 /* 6531 * Only clone the skb if there's enough data at the end to 6532 * at least cover the rx descriptor 6533 */ 6534 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24))) 6535 next_skb = skb_clone(skb, GFP_ATOMIC); 6536 6537 rx_status = IEEE80211_SKB_RXCB(skb); 6538 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 6539 6540 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); 6541 6542 phy_stats = (struct rtl8723au_phy_stats *)skb->data; 6543 6544 skb_pull(skb, drvinfo_sz + desc_shift); 6545 6546 skb_trim(skb, pkt_len); 6547 6548 if (rx_desc->rpt_sel) { 6549 struct device *dev = &priv->udev->dev; 6550 dev_dbg(dev, "%s: C2H packet\n", __func__); 6551 rtl8723bu_handle_c2h(priv, skb); 6552 } else { 6553 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 6554 6555 if (rx_desc->phy_stats) { 6556 priv->fops->parse_phystats(priv, rx_status, phy_stats, 6557 rx_desc->rxmcs, hdr, 6558 rx_desc->crc32 || rx_desc->icverr); 6559 if (!rx_desc->crc32 && !rx_desc->icverr) 6560 rtl8xxxu_rx_update_rssi(priv, 6561 rx_status, 6562 hdr); 6563 } 6564 6565 rx_status->mactime = rx_desc->tsfl; 6566 rx_status->flag |= RX_FLAG_MACTIME_START; 6567 6568 if (!rx_desc->swdec && 6569 rx_desc->security != RX_DESC_ENC_NONE) 6570 rx_status->flag |= RX_FLAG_DECRYPTED; 6571 if (rx_desc->crc32) 6572 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 6573 if (rx_desc->bw) 6574 rx_status->bw = RATE_INFO_BW_40; 6575 6576 if (rx_desc->rxmcs >= DESC_RATE_MCS0) { 6577 rx_status->encoding = RX_ENC_HT; 6578 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; 6579 } else { 6580 rx_status->rate_idx = rx_desc->rxmcs; 6581 } 6582 6583 rx_status->freq = hw->conf.chandef.chan->center_freq; 6584 rx_status->band = hw->conf.chandef.chan->band; 6585 6586 ieee80211_rx_irqsafe(hw, skb); 6587 } 6588 6589 skb = next_skb; 6590 if (skb) 6591 skb_pull(next_skb, pkt_offset); 6592 6593 urb_len -= pkt_offset; 6594 next_skb = NULL; 6595 } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24)); 6596 6597 return RX_TYPE_DATA_PKT; 6598 } 6599 6600 static void rtl8xxxu_rx_complete(struct urb *urb) 6601 { 6602 struct rtl8xxxu_rx_urb *rx_urb = 6603 container_of(urb, struct rtl8xxxu_rx_urb, urb); 6604 struct ieee80211_hw *hw = rx_urb->hw; 6605 struct rtl8xxxu_priv *priv = hw->priv; 6606 struct sk_buff *skb = (struct sk_buff *)urb->context; 6607 struct device *dev = &priv->udev->dev; 6608 6609 skb_put(skb, urb->actual_length); 6610 6611 if (urb->status == 0) { 6612 priv->fops->parse_rx_desc(priv, skb); 6613 6614 skb = NULL; 6615 rx_urb->urb.context = NULL; 6616 rtl8xxxu_queue_rx_urb(priv, rx_urb); 6617 } else { 6618 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6619 goto cleanup; 6620 } 6621 return; 6622 6623 cleanup: 6624 usb_free_urb(urb); 6625 dev_kfree_skb(skb); 6626 } 6627 6628 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, 6629 struct rtl8xxxu_rx_urb *rx_urb) 6630 { 6631 struct rtl8xxxu_fileops *fops = priv->fops; 6632 struct sk_buff *skb; 6633 int skb_size; 6634 int ret, rx_desc_sz; 6635 6636 rx_desc_sz = fops->rx_desc_size; 6637 6638 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { 6639 skb_size = fops->rx_agg_buf_size; 6640 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); 6641 } else { 6642 skb_size = IEEE80211_MAX_FRAME_LEN + rx_desc_sz; 6643 } 6644 6645 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); 6646 if (!skb) 6647 return -ENOMEM; 6648 6649 memset(skb->data, 0, rx_desc_sz); 6650 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, 6651 skb_size, rtl8xxxu_rx_complete, skb); 6652 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); 6653 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); 6654 if (ret) 6655 usb_unanchor_urb(&rx_urb->urb); 6656 return ret; 6657 } 6658 6659 static void rtl8xxxu_int_complete(struct urb *urb) 6660 { 6661 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; 6662 struct device *dev = &priv->udev->dev; 6663 int ret; 6664 6665 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) 6666 dev_dbg(dev, "%s: status %i\n", __func__, urb->status); 6667 if (urb->status == 0) { 6668 usb_anchor_urb(urb, &priv->int_anchor); 6669 ret = usb_submit_urb(urb, GFP_ATOMIC); 6670 if (ret) 6671 usb_unanchor_urb(urb); 6672 } else { 6673 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); 6674 } 6675 } 6676 6677 6678 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) 6679 { 6680 struct rtl8xxxu_priv *priv = hw->priv; 6681 struct urb *urb; 6682 u32 val32; 6683 int ret; 6684 6685 urb = usb_alloc_urb(0, GFP_KERNEL); 6686 if (!urb) 6687 return -ENOMEM; 6688 6689 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, 6690 priv->int_buf, USB_INTR_CONTENT_LENGTH, 6691 rtl8xxxu_int_complete, priv, 1); 6692 usb_anchor_urb(urb, &priv->int_anchor); 6693 ret = usb_submit_urb(urb, GFP_KERNEL); 6694 if (ret) { 6695 usb_unanchor_urb(urb); 6696 goto error; 6697 } 6698 6699 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); 6700 val32 |= USB_HIMR_CPWM; 6701 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); 6702 6703 error: 6704 usb_free_urb(urb); 6705 return ret; 6706 } 6707 6708 static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv) 6709 { 6710 u8 macid[ETH_ALEN], bssid[ETH_ALEN], macid_1[ETH_ALEN], bssid_1[ETH_ALEN]; 6711 u8 msr, bcn_ctrl, bcn_ctrl_1, atimwnd[2], atimwnd_1[2]; 6712 struct rtl8xxxu_vif *rtlvif; 6713 u8 tsftr[8], tsftr_1[8]; 6714 int i; 6715 6716 msr = rtl8xxxu_read8(priv, REG_MSR); 6717 bcn_ctrl = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 6718 bcn_ctrl_1 = rtl8xxxu_read8(priv, REG_BEACON_CTRL_1); 6719 6720 for (i = 0; i < ARRAY_SIZE(atimwnd); i++) 6721 atimwnd[i] = rtl8xxxu_read8(priv, REG_ATIMWND + i); 6722 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) 6723 atimwnd_1[i] = rtl8xxxu_read8(priv, REG_ATIMWND_1 + i); 6724 6725 for (i = 0; i < ARRAY_SIZE(tsftr); i++) 6726 tsftr[i] = rtl8xxxu_read8(priv, REG_TSFTR + i); 6727 for (i = 0; i < ARRAY_SIZE(tsftr); i++) 6728 tsftr_1[i] = rtl8xxxu_read8(priv, REG_TSFTR1 + i); 6729 6730 for (i = 0; i < ARRAY_SIZE(macid); i++) 6731 macid[i] = rtl8xxxu_read8(priv, REG_MACID + i); 6732 6733 for (i = 0; i < ARRAY_SIZE(bssid); i++) 6734 bssid[i] = rtl8xxxu_read8(priv, REG_BSSID + i); 6735 6736 for (i = 0; i < ARRAY_SIZE(macid_1); i++) 6737 macid_1[i] = rtl8xxxu_read8(priv, REG_MACID1 + i); 6738 6739 for (i = 0; i < ARRAY_SIZE(bssid_1); i++) 6740 bssid_1[i] = rtl8xxxu_read8(priv, REG_BSSID1 + i); 6741 6742 /* disable bcn function, disable update TSF */ 6743 rtl8xxxu_write8(priv, REG_BEACON_CTRL, (bcn_ctrl & 6744 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); 6745 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, (bcn_ctrl_1 & 6746 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); 6747 6748 /* switch msr */ 6749 msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2); 6750 rtl8xxxu_write8(priv, REG_MSR, msr); 6751 6752 /* write port0 */ 6753 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1 & ~BEACON_FUNCTION_ENABLE); 6754 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) 6755 rtl8xxxu_write8(priv, REG_ATIMWND + i, atimwnd_1[i]); 6756 for (i = 0; i < ARRAY_SIZE(tsftr_1); i++) 6757 rtl8xxxu_write8(priv, REG_TSFTR + i, tsftr_1[i]); 6758 for (i = 0; i < ARRAY_SIZE(macid_1); i++) 6759 rtl8xxxu_write8(priv, REG_MACID + i, macid_1[i]); 6760 for (i = 0; i < ARRAY_SIZE(bssid_1); i++) 6761 rtl8xxxu_write8(priv, REG_BSSID + i, bssid_1[i]); 6762 6763 /* write port1 */ 6764 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl & ~BEACON_FUNCTION_ENABLE); 6765 for (i = 0; i < ARRAY_SIZE(atimwnd); i++) 6766 rtl8xxxu_write8(priv, REG_ATIMWND_1 + i, atimwnd[i]); 6767 for (i = 0; i < ARRAY_SIZE(tsftr); i++) 6768 rtl8xxxu_write8(priv, REG_TSFTR1 + i, tsftr[i]); 6769 for (i = 0; i < ARRAY_SIZE(macid); i++) 6770 rtl8xxxu_write8(priv, REG_MACID1 + i, macid[i]); 6771 for (i = 0; i < ARRAY_SIZE(bssid); i++) 6772 rtl8xxxu_write8(priv, REG_BSSID1 + i, bssid[i]); 6773 6774 /* write bcn ctl */ 6775 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1); 6776 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl); 6777 swap(priv->vifs[0], priv->vifs[1]); 6778 6779 /* priv->vifs[0] is NULL here, based on how this function is currently 6780 * called from rtl8xxxu_add_interface(). 6781 * When this function will be used in the future for a different 6782 * scenario, please check whether vifs[0] or vifs[1] can be NULL and if 6783 * necessary add code to set port_num = 1. 6784 */ 6785 rtlvif = (struct rtl8xxxu_vif *)priv->vifs[1]->drv_priv; 6786 rtlvif->port_num = 1; 6787 } 6788 6789 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, 6790 struct ieee80211_vif *vif) 6791 { 6792 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 6793 struct rtl8xxxu_priv *priv = hw->priv; 6794 int port_num; 6795 u8 val8; 6796 6797 if (!priv->vifs[0]) 6798 port_num = 0; 6799 else if (!priv->vifs[1]) 6800 port_num = 1; 6801 else 6802 return -EOPNOTSUPP; 6803 6804 switch (vif->type) { 6805 case NL80211_IFTYPE_STATION: 6806 if (port_num == 0) { 6807 rtl8xxxu_stop_tx_beacon(priv); 6808 6809 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); 6810 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | 6811 BEACON_DISABLE_TSF_UPDATE; 6812 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); 6813 } 6814 break; 6815 case NL80211_IFTYPE_AP: 6816 if (port_num == 1) { 6817 rtl8xxxu_switch_ports(priv); 6818 port_num = 0; 6819 } 6820 6821 rtl8xxxu_write8(priv, REG_BEACON_CTRL, 6822 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID); 6823 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */ 6824 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */ 6825 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0); 6826 6827 /* enable BCN0 function */ 6828 rtl8xxxu_write8(priv, REG_BEACON_CTRL, 6829 BEACON_DISABLE_TSF_UPDATE | 6830 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID | 6831 BEACON_CTRL_TX_BEACON_RPT); 6832 6833 /* select BCN on port 0 */ 6834 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK); 6835 val8 &= ~BIT_BCN_PORT_SEL; 6836 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8); 6837 break; 6838 default: 6839 return -EOPNOTSUPP; 6840 } 6841 6842 priv->vifs[port_num] = vif; 6843 rtlvif->port_num = port_num; 6844 rtlvif->hw_key_idx = 0xff; 6845 6846 rtl8xxxu_set_linktype(priv, vif->type, port_num); 6847 ether_addr_copy(priv->mac_addr, vif->addr); 6848 rtl8xxxu_set_mac(priv, port_num); 6849 6850 return 0; 6851 } 6852 6853 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, 6854 struct ieee80211_vif *vif) 6855 { 6856 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 6857 struct rtl8xxxu_priv *priv = hw->priv; 6858 6859 dev_dbg(&priv->udev->dev, "%s\n", __func__); 6860 6861 priv->vifs[rtlvif->port_num] = NULL; 6862 } 6863 6864 static int rtl8xxxu_config(struct ieee80211_hw *hw, int radio_idx, u32 changed) 6865 { 6866 struct rtl8xxxu_priv *priv = hw->priv; 6867 struct device *dev = &priv->udev->dev; 6868 int ret = 0, channel; 6869 bool ht40; 6870 6871 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) 6872 dev_info(dev, 6873 "%s: channel: %i (changed %08x chandef.width %02x)\n", 6874 __func__, hw->conf.chandef.chan->hw_value, 6875 changed, hw->conf.chandef.width); 6876 6877 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 6878 switch (hw->conf.chandef.width) { 6879 case NL80211_CHAN_WIDTH_20_NOHT: 6880 case NL80211_CHAN_WIDTH_20: 6881 ht40 = false; 6882 break; 6883 case NL80211_CHAN_WIDTH_40: 6884 ht40 = true; 6885 break; 6886 default: 6887 ret = -ENOTSUPP; 6888 goto exit; 6889 } 6890 6891 channel = hw->conf.chandef.chan->hw_value; 6892 6893 priv->fops->set_tx_power(priv, channel, ht40); 6894 6895 priv->fops->config_channel(hw); 6896 } 6897 6898 exit: 6899 return ret; 6900 } 6901 6902 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, 6903 struct ieee80211_vif *vif, 6904 unsigned int link_id, u16 queue, 6905 const struct ieee80211_tx_queue_params *param) 6906 { 6907 struct rtl8xxxu_priv *priv = hw->priv; 6908 struct device *dev = &priv->udev->dev; 6909 u32 val32; 6910 u8 aifs, acm_ctrl, acm_bit; 6911 6912 aifs = param->aifs; 6913 6914 val32 = aifs | 6915 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | 6916 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | 6917 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; 6918 6919 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); 6920 dev_dbg(dev, 6921 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", 6922 __func__, queue, val32, param->acm, acm_ctrl); 6923 6924 switch (queue) { 6925 case IEEE80211_AC_VO: 6926 acm_bit = ACM_HW_CTRL_VO; 6927 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); 6928 break; 6929 case IEEE80211_AC_VI: 6930 acm_bit = ACM_HW_CTRL_VI; 6931 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); 6932 break; 6933 case IEEE80211_AC_BE: 6934 acm_bit = ACM_HW_CTRL_BE; 6935 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); 6936 break; 6937 case IEEE80211_AC_BK: 6938 acm_bit = ACM_HW_CTRL_BK; 6939 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); 6940 break; 6941 default: 6942 acm_bit = 0; 6943 break; 6944 } 6945 6946 if (param->acm) 6947 acm_ctrl |= acm_bit; 6948 else 6949 acm_ctrl &= ~acm_bit; 6950 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); 6951 6952 return 0; 6953 } 6954 6955 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, 6956 unsigned int changed_flags, 6957 unsigned int *total_flags, u64 multicast) 6958 { 6959 struct rtl8xxxu_priv *priv = hw->priv; 6960 u32 rcr = priv->regrcr; 6961 6962 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", 6963 __func__, changed_flags, *total_flags); 6964 6965 /* 6966 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) 6967 */ 6968 6969 if (*total_flags & FIF_FCSFAIL) 6970 rcr |= RCR_ACCEPT_CRC32; 6971 else 6972 rcr &= ~RCR_ACCEPT_CRC32; 6973 6974 /* 6975 * FIF_PLCPFAIL not supported? 6976 */ 6977 6978 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 6979 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH); 6980 else 6981 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH; 6982 6983 if (priv->vifs[0] && priv->vifs[0]->type == NL80211_IFTYPE_AP) 6984 rcr &= ~(RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON); 6985 6986 if (*total_flags & FIF_CONTROL) 6987 rcr |= RCR_ACCEPT_CTRL_FRAME; 6988 else 6989 rcr &= ~RCR_ACCEPT_CTRL_FRAME; 6990 6991 if (*total_flags & FIF_OTHER_BSS) 6992 rcr |= RCR_ACCEPT_AP; 6993 else 6994 rcr &= ~RCR_ACCEPT_AP; 6995 6996 if (*total_flags & FIF_PSPOLL) 6997 rcr |= RCR_ACCEPT_PM; 6998 else 6999 rcr &= ~RCR_ACCEPT_PM; 7000 7001 /* 7002 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted 7003 */ 7004 7005 rtl8xxxu_write32(priv, REG_RCR, rcr); 7006 priv->regrcr = rcr; 7007 7008 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | 7009 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | 7010 FIF_PROBE_REQ); 7011 } 7012 7013 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, int radio_idx, 7014 u32 rts) 7015 { 7016 if (rts > 2347 && rts != (u32)-1) 7017 return -EINVAL; 7018 7019 return 0; 7020 } 7021 7022 static int rtl8xxxu_get_free_sec_cam(struct ieee80211_hw *hw) 7023 { 7024 struct rtl8xxxu_priv *priv = hw->priv; 7025 7026 return find_first_zero_bit(priv->cam_map, priv->fops->max_sec_cam_num); 7027 } 7028 7029 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 7030 struct ieee80211_vif *vif, 7031 struct ieee80211_sta *sta, 7032 struct ieee80211_key_conf *key) 7033 { 7034 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 7035 struct rtl8xxxu_priv *priv = hw->priv; 7036 struct device *dev = &priv->udev->dev; 7037 u8 mac_addr[ETH_ALEN]; 7038 u8 val8; 7039 u16 val16; 7040 u32 val32; 7041 int retval = -EOPNOTSUPP; 7042 7043 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", 7044 __func__, cmd, key->cipher, key->keyidx); 7045 7046 if (key->keyidx > 3) 7047 return -EOPNOTSUPP; 7048 7049 switch (key->cipher) { 7050 case WLAN_CIPHER_SUITE_WEP40: 7051 case WLAN_CIPHER_SUITE_WEP104: 7052 7053 break; 7054 case WLAN_CIPHER_SUITE_CCMP: 7055 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 7056 break; 7057 case WLAN_CIPHER_SUITE_TKIP: 7058 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 7059 break; 7060 default: 7061 return -EOPNOTSUPP; 7062 } 7063 7064 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 7065 dev_dbg(dev, "%s: pairwise key\n", __func__); 7066 ether_addr_copy(mac_addr, sta->addr); 7067 } else { 7068 dev_dbg(dev, "%s: group key\n", __func__); 7069 ether_addr_copy(mac_addr, vif->bss_conf.bssid); 7070 } 7071 7072 val16 = rtl8xxxu_read16(priv, REG_CR); 7073 val16 |= CR_SECURITY_ENABLE; 7074 rtl8xxxu_write16(priv, REG_CR, val16); 7075 7076 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | 7077 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; 7078 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; 7079 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); 7080 7081 switch (cmd) { 7082 case SET_KEY: 7083 7084 retval = rtl8xxxu_get_free_sec_cam(hw); 7085 if (retval < 0) 7086 return -EOPNOTSUPP; 7087 7088 key->hw_key_idx = retval; 7089 7090 if (vif->type == NL80211_IFTYPE_AP && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 7091 rtlvif->hw_key_idx = key->hw_key_idx; 7092 7093 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 7094 rtl8xxxu_cam_write(priv, key, mac_addr); 7095 set_bit(key->hw_key_idx, priv->cam_map); 7096 retval = 0; 7097 break; 7098 case DISABLE_KEY: 7099 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); 7100 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | 7101 key->hw_key_idx << CAM_CMD_KEY_SHIFT; 7102 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); 7103 rtlvif->hw_key_idx = 0xff; 7104 clear_bit(key->hw_key_idx, priv->cam_map); 7105 retval = 0; 7106 break; 7107 default: 7108 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); 7109 } 7110 7111 return retval; 7112 } 7113 7114 static int 7115 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 7116 struct ieee80211_ampdu_params *params) 7117 { 7118 struct rtl8xxxu_priv *priv = hw->priv; 7119 struct device *dev = &priv->udev->dev; 7120 u8 ampdu_factor, ampdu_density; 7121 struct ieee80211_sta *sta = params->sta; 7122 u16 tid = params->tid; 7123 enum ieee80211_ampdu_mlme_action action = params->action; 7124 7125 switch (action) { 7126 case IEEE80211_AMPDU_TX_START: 7127 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); 7128 ampdu_factor = sta->deflink.ht_cap.ampdu_factor; 7129 ampdu_density = sta->deflink.ht_cap.ampdu_density; 7130 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); 7131 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); 7132 dev_dbg(dev, 7133 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", 7134 ampdu_factor, ampdu_density); 7135 return IEEE80211_AMPDU_TX_START_IMMEDIATE; 7136 case IEEE80211_AMPDU_TX_STOP_CONT: 7137 case IEEE80211_AMPDU_TX_STOP_FLUSH: 7138 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 7139 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__); 7140 rtl8xxxu_set_ampdu_factor(priv, 0); 7141 rtl8xxxu_set_ampdu_min_space(priv, 0); 7142 clear_bit(tid, priv->tx_aggr_started); 7143 clear_bit(tid, priv->tid_tx_operational); 7144 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 7145 break; 7146 case IEEE80211_AMPDU_TX_OPERATIONAL: 7147 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__); 7148 set_bit(tid, priv->tid_tx_operational); 7149 break; 7150 case IEEE80211_AMPDU_RX_START: 7151 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); 7152 break; 7153 case IEEE80211_AMPDU_RX_STOP: 7154 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); 7155 break; 7156 default: 7157 break; 7158 } 7159 return 0; 7160 } 7161 7162 static void 7163 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 7164 struct ieee80211_sta *sta, struct station_info *sinfo) 7165 { 7166 struct rtl8xxxu_priv *priv = hw->priv; 7167 7168 sinfo->txrate = priv->ra_report.txrate; 7169 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); 7170 } 7171 7172 static u8 rtl8xxxu_signal_to_snr(int signal) 7173 { 7174 if (signal < RTL8XXXU_NOISE_FLOOR_MIN) 7175 signal = RTL8XXXU_NOISE_FLOOR_MIN; 7176 else if (signal > 0) 7177 signal = 0; 7178 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); 7179 } 7180 7181 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, 7182 int signal, struct ieee80211_sta *sta, 7183 bool force) 7184 { 7185 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7186 struct ieee80211_hw *hw = priv->hw; 7187 u16 wireless_mode; 7188 u8 rssi_level, ratr_idx; 7189 u8 txbw_40mhz; 7190 u8 snr, snr_thresh_high, snr_thresh_low; 7191 u8 go_up_gap = 5; 7192 u8 macid = rtl8xxxu_get_macid(priv, sta); 7193 7194 rssi_level = sta_info->rssi_level; 7195 snr = rtl8xxxu_signal_to_snr(signal); 7196 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; 7197 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; 7198 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; 7199 7200 switch (rssi_level) { 7201 case RTL8XXXU_RATR_STA_MID: 7202 snr_thresh_high += go_up_gap; 7203 break; 7204 case RTL8XXXU_RATR_STA_LOW: 7205 snr_thresh_high += go_up_gap; 7206 snr_thresh_low += go_up_gap; 7207 break; 7208 default: 7209 break; 7210 } 7211 7212 if (snr > snr_thresh_high) 7213 rssi_level = RTL8XXXU_RATR_STA_HIGH; 7214 else if (snr > snr_thresh_low) 7215 rssi_level = RTL8XXXU_RATR_STA_MID; 7216 else 7217 rssi_level = RTL8XXXU_RATR_STA_LOW; 7218 7219 if (rssi_level != sta_info->rssi_level || force) { 7220 int sgi = 0; 7221 u32 rate_bitmap = 0; 7222 7223 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) | 7224 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) | 7225 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20); 7226 if (sta->deflink.ht_cap.cap & 7227 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) 7228 sgi = 1; 7229 7230 wireless_mode = rtl8xxxu_wireless_mode(hw, sta); 7231 switch (wireless_mode) { 7232 case WIRELESS_MODE_B: 7233 ratr_idx = RATEID_IDX_B; 7234 if (rate_bitmap & 0x0000000c) 7235 rate_bitmap &= 0x0000000d; 7236 else 7237 rate_bitmap &= 0x0000000f; 7238 break; 7239 case WIRELESS_MODE_A: 7240 case WIRELESS_MODE_G: 7241 ratr_idx = RATEID_IDX_G; 7242 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 7243 rate_bitmap &= 0x00000f00; 7244 else 7245 rate_bitmap &= 0x00000ff0; 7246 break; 7247 case (WIRELESS_MODE_B | WIRELESS_MODE_G): 7248 ratr_idx = RATEID_IDX_BG; 7249 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) 7250 rate_bitmap &= 0x00000f00; 7251 else if (rssi_level == RTL8XXXU_RATR_STA_MID) 7252 rate_bitmap &= 0x00000ff0; 7253 else 7254 rate_bitmap &= 0x00000ff5; 7255 break; 7256 case WIRELESS_MODE_N_24G: 7257 case WIRELESS_MODE_N_5G: 7258 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 7259 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): 7260 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7261 ratr_idx = RATEID_IDX_GN_N2SS; 7262 else 7263 ratr_idx = RATEID_IDX_GN_N1SS; 7264 break; 7265 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): 7266 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): 7267 if (txbw_40mhz) { 7268 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7269 ratr_idx = RATEID_IDX_BGN_40M_2SS; 7270 else 7271 ratr_idx = RATEID_IDX_BGN_40M_1SS; 7272 } else { 7273 if (priv->tx_paths == 2 && priv->rx_paths == 2) 7274 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; 7275 else 7276 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; 7277 } 7278 7279 if (priv->tx_paths == 2 && priv->rx_paths == 2) { 7280 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 7281 rate_bitmap &= 0x0f8f0000; 7282 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 7283 rate_bitmap &= 0x0f8ff000; 7284 } else { 7285 if (txbw_40mhz) 7286 rate_bitmap &= 0x0f8ff015; 7287 else 7288 rate_bitmap &= 0x0f8ff005; 7289 } 7290 } else { 7291 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { 7292 rate_bitmap &= 0x000f0000; 7293 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { 7294 rate_bitmap &= 0x000ff000; 7295 } else { 7296 if (txbw_40mhz) 7297 rate_bitmap &= 0x000ff015; 7298 else 7299 rate_bitmap &= 0x000ff005; 7300 } 7301 } 7302 break; 7303 default: 7304 ratr_idx = RATEID_IDX_BGN_40M_2SS; 7305 rate_bitmap &= 0x0fffffff; 7306 break; 7307 } 7308 7309 sta_info->rssi_level = rssi_level; 7310 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid); 7311 } 7312 } 7313 7314 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status) 7315 { 7316 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 7317 u32 val32; 7318 7319 if (atc_status == cfo->atc_status) 7320 return; 7321 7322 cfo->atc_status = atc_status; 7323 7324 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 7325 if (atc_status) 7326 val32 |= CFO_TRACKING_ATC_STATUS; 7327 else 7328 val32 &= ~CFO_TRACKING_ATC_STATUS; 7329 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 7330 } 7331 7332 /* Central frequency offset correction */ 7333 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv) 7334 { 7335 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 7336 int cfo_khz_a, cfo_khz_b, cfo_average; 7337 int crystal_cap; 7338 7339 if (!rtl8xxxu_is_assoc(priv)) { 7340 /* Reset */ 7341 cfo->adjust = true; 7342 7343 if (cfo->crystal_cap > priv->default_crystal_cap) 7344 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1); 7345 else if (cfo->crystal_cap < priv->default_crystal_cap) 7346 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1); 7347 7348 rtl8xxxu_set_atc_status(priv, true); 7349 7350 return; 7351 } 7352 7353 if (cfo->packet_count == cfo->packet_count_pre) 7354 /* No new information. */ 7355 return; 7356 7357 cfo->packet_count_pre = cfo->packet_count; 7358 7359 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ 7360 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7; 7361 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7; 7362 7363 if (priv->tx_paths == 1) 7364 cfo_average = cfo_khz_a; 7365 else 7366 cfo_average = (cfo_khz_a + cfo_khz_b) / 2; 7367 7368 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average); 7369 7370 if (cfo->adjust) { 7371 if (abs(cfo_average) < CFO_TH_XTAL_LOW) 7372 cfo->adjust = false; 7373 } else { 7374 if (abs(cfo_average) > CFO_TH_XTAL_HIGH) 7375 cfo->adjust = true; 7376 } 7377 7378 /* 7379 * TODO: We should return here only if bluetooth is enabled. 7380 * See the vendor drivers for how to determine that. 7381 */ 7382 if (priv->has_bluetooth) 7383 return; 7384 7385 if (!cfo->adjust) 7386 return; 7387 7388 crystal_cap = cfo->crystal_cap; 7389 7390 if (cfo_average > CFO_TH_XTAL_LOW) 7391 crystal_cap++; 7392 else if (cfo_average < -CFO_TH_XTAL_LOW) 7393 crystal_cap--; 7394 7395 crystal_cap = clamp(crystal_cap, 0, 0x3f); 7396 7397 priv->fops->set_crystal_cap(priv, crystal_cap); 7398 7399 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC); 7400 } 7401 7402 static void rtl8xxxu_ra_iter(void *data, struct ieee80211_sta *sta) 7403 { 7404 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7405 struct rtl8xxxu_priv *priv = data; 7406 int signal = -ewma_rssi_read(&sta_info->avg_rssi); 7407 7408 priv->fops->report_rssi(priv, rtl8xxxu_get_macid(priv, sta), 7409 rtl8xxxu_signal_to_snr(signal)); 7410 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false); 7411 } 7412 7413 struct rtl8xxxu_stas_entry { 7414 struct list_head list; 7415 struct ieee80211_sta *sta; 7416 }; 7417 7418 struct rtl8xxxu_iter_stas_data { 7419 struct rtl8xxxu_priv *priv; 7420 struct list_head list; 7421 }; 7422 7423 static void rtl8xxxu_collect_sta_iter(void *data, struct ieee80211_sta *sta) 7424 { 7425 struct rtl8xxxu_iter_stas_data *iter_stas = data; 7426 struct rtl8xxxu_stas_entry *stas_entry; 7427 7428 stas_entry = kmalloc(sizeof(*stas_entry), GFP_ATOMIC); 7429 if (!stas_entry) 7430 return; 7431 7432 stas_entry->sta = sta; 7433 list_add_tail(&stas_entry->list, &iter_stas->list); 7434 } 7435 7436 static void rtl8xxxu_watchdog_callback(struct work_struct *work) 7437 { 7438 7439 struct rtl8xxxu_iter_stas_data iter_data; 7440 struct rtl8xxxu_stas_entry *sta_entry, *tmp; 7441 struct rtl8xxxu_priv *priv; 7442 7443 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); 7444 iter_data.priv = priv; 7445 INIT_LIST_HEAD(&iter_data.list); 7446 7447 mutex_lock(&priv->sta_mutex); 7448 ieee80211_iterate_stations_atomic(priv->hw, rtl8xxxu_collect_sta_iter, 7449 &iter_data); 7450 list_for_each_entry_safe(sta_entry, tmp, &iter_data.list, list) { 7451 list_del_init(&sta_entry->list); 7452 rtl8xxxu_ra_iter(priv, sta_entry->sta); 7453 kfree(sta_entry); 7454 } 7455 mutex_unlock(&priv->sta_mutex); 7456 7457 if (priv->fops->set_crystal_cap) 7458 rtl8xxxu_track_cfo(priv); 7459 7460 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 7461 } 7462 7463 static int rtl8xxxu_start(struct ieee80211_hw *hw) 7464 { 7465 struct rtl8xxxu_priv *priv = hw->priv; 7466 struct rtl8xxxu_rx_urb *rx_urb; 7467 struct rtl8xxxu_tx_urb *tx_urb; 7468 struct sk_buff *skb; 7469 unsigned long flags; 7470 int ret, i; 7471 7472 ret = 0; 7473 7474 init_usb_anchor(&priv->rx_anchor); 7475 init_usb_anchor(&priv->tx_anchor); 7476 init_usb_anchor(&priv->int_anchor); 7477 7478 priv->fops->enable_rf(priv); 7479 if (priv->usb_interrupts) { 7480 ret = rtl8xxxu_submit_int_urb(hw); 7481 if (ret) 7482 goto exit; 7483 } 7484 7485 for (i = 0; i < RTL8XXXU_TX_URBS; i++) { 7486 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); 7487 if (!tx_urb) { 7488 if (!i) 7489 ret = -ENOMEM; 7490 7491 goto error_out; 7492 } 7493 usb_init_urb(&tx_urb->urb); 7494 INIT_LIST_HEAD(&tx_urb->list); 7495 tx_urb->hw = hw; 7496 list_add(&tx_urb->list, &priv->tx_urb_free_list); 7497 priv->tx_urb_free_count++; 7498 } 7499 7500 priv->tx_stopped = false; 7501 7502 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7503 priv->shutdown = false; 7504 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7505 7506 for (i = 0; i < RTL8XXXU_RX_URBS; i++) { 7507 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); 7508 if (!rx_urb) { 7509 if (!i) 7510 ret = -ENOMEM; 7511 7512 goto error_out; 7513 } 7514 usb_init_urb(&rx_urb->urb); 7515 INIT_LIST_HEAD(&rx_urb->list); 7516 rx_urb->hw = hw; 7517 7518 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); 7519 if (ret) { 7520 if (ret != -ENOMEM) { 7521 skb = (struct sk_buff *)rx_urb->urb.context; 7522 dev_kfree_skb(skb); 7523 } 7524 rtl8xxxu_queue_rx_urb(priv, rx_urb); 7525 } 7526 } 7527 7528 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); 7529 exit: 7530 /* 7531 * Accept all data and mgmt frames 7532 */ 7533 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); 7534 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); 7535 7536 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 7537 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e); 7538 7539 return ret; 7540 7541 error_out: 7542 rtl8xxxu_free_tx_resources(priv); 7543 /* 7544 * Disable all data and mgmt frames 7545 */ 7546 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7547 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7548 7549 return ret; 7550 } 7551 7552 static void rtl8xxxu_stop(struct ieee80211_hw *hw, bool suspend) 7553 { 7554 struct rtl8xxxu_priv *priv = hw->priv; 7555 unsigned long flags; 7556 7557 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7558 7559 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); 7560 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); 7561 7562 spin_lock_irqsave(&priv->rx_urb_lock, flags); 7563 priv->shutdown = true; 7564 spin_unlock_irqrestore(&priv->rx_urb_lock, flags); 7565 7566 usb_kill_anchored_urbs(&priv->rx_anchor); 7567 usb_kill_anchored_urbs(&priv->tx_anchor); 7568 if (priv->usb_interrupts) 7569 usb_kill_anchored_urbs(&priv->int_anchor); 7570 7571 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 7572 7573 priv->fops->disable_rf(priv); 7574 7575 /* 7576 * Disable interrupts 7577 */ 7578 if (priv->usb_interrupts) 7579 rtl8xxxu_write32(priv, REG_USB_HIMR, 0); 7580 7581 cancel_work_sync(&priv->c2hcmd_work); 7582 cancel_delayed_work_sync(&priv->ra_watchdog); 7583 cancel_delayed_work_sync(&priv->update_beacon_work); 7584 7585 rtl8xxxu_free_rx_resources(priv); 7586 rtl8xxxu_free_tx_resources(priv); 7587 } 7588 7589 static int rtl8xxxu_sta_add(struct ieee80211_hw *hw, 7590 struct ieee80211_vif *vif, 7591 struct ieee80211_sta *sta) 7592 { 7593 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7594 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; 7595 struct rtl8xxxu_priv *priv = hw->priv; 7596 7597 mutex_lock(&priv->sta_mutex); 7598 ewma_rssi_init(&sta_info->avg_rssi); 7599 if (vif->type == NL80211_IFTYPE_AP) { 7600 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; 7601 sta_info->macid = rtl8xxxu_acquire_macid(priv); 7602 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM) { 7603 mutex_unlock(&priv->sta_mutex); 7604 return -ENOSPC; 7605 } 7606 7607 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true); 7608 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true); 7609 } else { 7610 switch (rtlvif->port_num) { 7611 case 0: 7612 sta_info->macid = RTL8XXXU_BC_MC_MACID; 7613 break; 7614 case 1: 7615 sta_info->macid = RTL8XXXU_BC_MC_MACID1; 7616 break; 7617 default: 7618 break; 7619 } 7620 } 7621 mutex_unlock(&priv->sta_mutex); 7622 7623 return 0; 7624 } 7625 7626 static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw, 7627 struct ieee80211_vif *vif, 7628 struct ieee80211_sta *sta) 7629 { 7630 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; 7631 struct rtl8xxxu_priv *priv = hw->priv; 7632 7633 mutex_lock(&priv->sta_mutex); 7634 if (vif->type == NL80211_IFTYPE_AP) 7635 rtl8xxxu_release_macid(priv, sta_info->macid); 7636 mutex_unlock(&priv->sta_mutex); 7637 7638 return 0; 7639 } 7640 7641 static const struct ieee80211_ops rtl8xxxu_ops = { 7642 .add_chanctx = ieee80211_emulate_add_chanctx, 7643 .remove_chanctx = ieee80211_emulate_remove_chanctx, 7644 .change_chanctx = ieee80211_emulate_change_chanctx, 7645 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx, 7646 .tx = rtl8xxxu_tx, 7647 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 7648 .add_interface = rtl8xxxu_add_interface, 7649 .remove_interface = rtl8xxxu_remove_interface, 7650 .config = rtl8xxxu_config, 7651 .conf_tx = rtl8xxxu_conf_tx, 7652 .bss_info_changed = rtl8xxxu_bss_info_changed, 7653 .start_ap = rtl8xxxu_start_ap, 7654 .configure_filter = rtl8xxxu_configure_filter, 7655 .set_rts_threshold = rtl8xxxu_set_rts_threshold, 7656 .start = rtl8xxxu_start, 7657 .stop = rtl8xxxu_stop, 7658 .sw_scan_start = rtl8xxxu_sw_scan_start, 7659 .sw_scan_complete = rtl8xxxu_sw_scan_complete, 7660 .set_key = rtl8xxxu_set_key, 7661 .ampdu_action = rtl8xxxu_ampdu_action, 7662 .sta_statistics = rtl8xxxu_sta_statistics, 7663 .get_antenna = rtl8xxxu_get_antenna, 7664 .set_tim = rtl8xxxu_set_tim, 7665 .sta_add = rtl8xxxu_sta_add, 7666 .sta_remove = rtl8xxxu_sta_remove, 7667 }; 7668 7669 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, 7670 struct usb_interface *interface) 7671 { 7672 struct usb_interface_descriptor *interface_desc; 7673 struct usb_host_interface *host_interface; 7674 struct usb_endpoint_descriptor *endpoint; 7675 struct device *dev = &priv->udev->dev; 7676 int i, j = 0, endpoints; 7677 u8 dir, xtype, num; 7678 int ret = 0; 7679 7680 host_interface = interface->cur_altsetting; 7681 interface_desc = &host_interface->desc; 7682 endpoints = interface_desc->bNumEndpoints; 7683 7684 for (i = 0; i < endpoints; i++) { 7685 endpoint = &host_interface->endpoint[i].desc; 7686 7687 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 7688 num = usb_endpoint_num(endpoint); 7689 xtype = usb_endpoint_type(endpoint); 7690 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7691 dev_dbg(dev, 7692 "%s: endpoint: dir %02x, # %02x, type %02x\n", 7693 __func__, dir, num, xtype); 7694 if (usb_endpoint_dir_in(endpoint) && 7695 usb_endpoint_xfer_bulk(endpoint)) { 7696 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7697 dev_dbg(dev, "%s: in endpoint num %i\n", 7698 __func__, num); 7699 7700 if (priv->pipe_in) { 7701 dev_warn(dev, 7702 "%s: Too many IN pipes\n", __func__); 7703 ret = -EINVAL; 7704 goto exit; 7705 } 7706 7707 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); 7708 } 7709 7710 if (usb_endpoint_dir_in(endpoint) && 7711 usb_endpoint_xfer_int(endpoint)) { 7712 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7713 dev_dbg(dev, "%s: interrupt endpoint num %i\n", 7714 __func__, num); 7715 7716 if (priv->pipe_interrupt) { 7717 dev_warn(dev, "%s: Too many INTERRUPT pipes\n", 7718 __func__); 7719 ret = -EINVAL; 7720 goto exit; 7721 } 7722 7723 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); 7724 } 7725 7726 if (usb_endpoint_dir_out(endpoint) && 7727 usb_endpoint_xfer_bulk(endpoint)) { 7728 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) 7729 dev_dbg(dev, "%s: out endpoint num %i\n", 7730 __func__, num); 7731 if (j >= RTL8XXXU_OUT_ENDPOINTS) { 7732 dev_warn(dev, 7733 "%s: Too many OUT pipes\n", __func__); 7734 ret = -EINVAL; 7735 goto exit; 7736 } 7737 priv->out_ep[j++] = num; 7738 } 7739 } 7740 exit: 7741 priv->nr_out_eps = j; 7742 return ret; 7743 } 7744 7745 static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv) 7746 { 7747 struct led_classdev *led = &priv->led_cdev; 7748 7749 if (!priv->fops->led_classdev_brightness_set) 7750 return; 7751 7752 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set; 7753 7754 snprintf(priv->led_name, sizeof(priv->led_name), 7755 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev)); 7756 led->name = priv->led_name; 7757 led->max_brightness = RTL8XXXU_HW_LED_CONTROL; 7758 7759 if (led_classdev_register(&priv->udev->dev, led)) 7760 return; 7761 7762 priv->led_registered = true; 7763 7764 led->brightness = led->max_brightness; 7765 priv->fops->led_classdev_brightness_set(led, led->brightness); 7766 } 7767 7768 static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv) 7769 { 7770 struct led_classdev *led = &priv->led_cdev; 7771 7772 if (!priv->led_registered) 7773 return; 7774 7775 priv->fops->led_classdev_brightness_set(led, LED_OFF); 7776 led_classdev_unregister(led); 7777 } 7778 7779 static const struct ieee80211_iface_limit rtl8xxxu_limits[] = { 7780 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION), }, 7781 { .max = 1, .types = BIT(NL80211_IFTYPE_AP), }, 7782 }; 7783 7784 static const struct ieee80211_iface_combination rtl8xxxu_combinations[] = { 7785 { 7786 .limits = rtl8xxxu_limits, 7787 .n_limits = ARRAY_SIZE(rtl8xxxu_limits), 7788 .max_interfaces = 2, 7789 .num_different_channels = 1, 7790 }, 7791 }; 7792 7793 static int rtl8xxxu_probe(struct usb_interface *interface, 7794 const struct usb_device_id *id) 7795 { 7796 struct rtl8xxxu_priv *priv; 7797 struct ieee80211_hw *hw; 7798 struct usb_device *udev; 7799 struct ieee80211_supported_band *sband; 7800 int ret; 7801 int untested = 1; 7802 7803 udev = usb_get_dev(interface_to_usbdev(interface)); 7804 7805 switch (id->idVendor) { 7806 case USB_VENDOR_ID_REALTEK: 7807 switch(id->idProduct) { 7808 case 0x1724: 7809 case 0x8176: 7810 case 0x8178: 7811 case 0x817f: 7812 case 0x818b: 7813 case 0xf179: 7814 case 0x8179: 7815 case 0xb711: 7816 case 0xf192: 7817 case 0x2005: 7818 untested = 0; 7819 break; 7820 } 7821 break; 7822 case 0x7392: 7823 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811) 7824 untested = 0; 7825 break; 7826 case 0x050d: 7827 if (id->idProduct == 0x1004) 7828 untested = 0; 7829 break; 7830 case 0x20f4: 7831 if (id->idProduct == 0x648b) 7832 untested = 0; 7833 break; 7834 case 0x2001: 7835 if (id->idProduct == 0x3308) 7836 untested = 0; 7837 break; 7838 case 0x2357: 7839 if (id->idProduct == 0x0109 || id->idProduct == 0x010c || 7840 id->idProduct == 0x0135) 7841 untested = 0; 7842 break; 7843 case 0x0b05: 7844 if (id->idProduct == 0x18f1) 7845 untested = 0; 7846 break; 7847 default: 7848 break; 7849 } 7850 7851 if (untested) { 7852 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; 7853 dev_info(&udev->dev, 7854 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", 7855 id->idVendor, id->idProduct); 7856 dev_info(&udev->dev, 7857 "Please report results to Jes.Sorensen@gmail.com\n"); 7858 } 7859 7860 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); 7861 if (!hw) { 7862 ret = -ENOMEM; 7863 goto err_put_dev; 7864 } 7865 7866 priv = hw->priv; 7867 priv->hw = hw; 7868 priv->udev = udev; 7869 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; 7870 mutex_init(&priv->usb_buf_mutex); 7871 mutex_init(&priv->syson_indirect_access_mutex); 7872 mutex_init(&priv->h2c_mutex); 7873 mutex_init(&priv->sta_mutex); 7874 INIT_LIST_HEAD(&priv->tx_urb_free_list); 7875 spin_lock_init(&priv->tx_urb_lock); 7876 INIT_LIST_HEAD(&priv->rx_urb_pending_list); 7877 spin_lock_init(&priv->rx_urb_lock); 7878 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); 7879 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); 7880 INIT_DELAYED_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback); 7881 skb_queue_head_init(&priv->c2hcmd_queue); 7882 7883 usb_set_intfdata(interface, hw); 7884 7885 ret = rtl8xxxu_parse_usb(priv, interface); 7886 if (ret) 7887 goto err_set_intfdata; 7888 7889 ret = priv->fops->identify_chip(priv); 7890 if (ret) { 7891 dev_err(&udev->dev, "Fatal - failed to identify chip\n"); 7892 goto err_set_intfdata; 7893 } 7894 7895 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; 7896 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; 7897 7898 if (priv->rtl_chip == RTL8188E) 7899 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback); 7900 else 7901 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); 7902 7903 ret = priv->fops->read_efuse(priv); 7904 if (ret) { 7905 dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); 7906 goto err_set_intfdata; 7907 } 7908 7909 ret = priv->fops->parse_efuse(priv); 7910 if (ret) { 7911 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); 7912 goto err_set_intfdata; 7913 } 7914 7915 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) 7916 rtl8xxxu_dump_efuse(priv); 7917 7918 rtl8xxxu_print_chipinfo(priv); 7919 7920 ret = priv->fops->load_firmware(priv); 7921 if (ret) { 7922 dev_err(&udev->dev, "Fatal - failed to load firmware\n"); 7923 goto err_set_intfdata; 7924 } 7925 7926 ret = rtl8xxxu_init_device(hw); 7927 if (ret) 7928 goto err_set_intfdata; 7929 7930 hw->vif_data_size = sizeof(struct rtl8xxxu_vif); 7931 7932 hw->wiphy->max_scan_ssids = 1; 7933 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 7934 if (priv->fops->max_macid_num) 7935 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1; 7936 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 7937 if (priv->fops->supports_ap) 7938 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP); 7939 hw->queues = 4; 7940 7941 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 7942 7943 if (priv->fops->supports_concurrent) { 7944 hw->wiphy->iface_combinations = rtl8xxxu_combinations; 7945 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtl8xxxu_combinations); 7946 } 7947 7948 sband = &rtl8xxxu_supported_band; 7949 sband->ht_cap.ht_supported = true; 7950 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 7951 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 7952 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; 7953 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); 7954 sband->ht_cap.mcs.rx_mask[0] = 0xff; 7955 sband->ht_cap.mcs.rx_mask[4] = 0x01; 7956 if (priv->rf_paths > 1) { 7957 sband->ht_cap.mcs.rx_mask[1] = 0xff; 7958 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 7959 } 7960 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 7961 /* 7962 * Some APs will negotiate HT20_40 in a noisy environment leading 7963 * to miserable performance. Rather than defaulting to this, only 7964 * enable it if explicitly requested at module load time. 7965 */ 7966 if (rtl8xxxu_ht40_2g) { 7967 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); 7968 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 7969 } 7970 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 7971 7972 hw->wiphy->rts_threshold = 2347; 7973 7974 SET_IEEE80211_DEV(priv->hw, &interface->dev); 7975 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); 7976 7977 hw->extra_tx_headroom = priv->fops->tx_desc_size; 7978 ieee80211_hw_set(hw, SIGNAL_DBM); 7979 7980 /* 7981 * The firmware handles rate control, except for RTL8188EU, 7982 * where we handle the rate control in the driver. 7983 */ 7984 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 7985 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 7986 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 7987 ieee80211_hw_set(hw, MFP_CAPABLE); 7988 7989 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 7990 7991 ret = ieee80211_register_hw(priv->hw); 7992 if (ret) { 7993 dev_err(&udev->dev, "%s: Failed to register: %i\n", 7994 __func__, ret); 7995 goto err_set_intfdata; 7996 } 7997 7998 rtl8xxxu_init_led(priv); 7999 rtl8xxxu_debugfs_init(priv); 8000 8001 return 0; 8002 8003 err_set_intfdata: 8004 usb_set_intfdata(interface, NULL); 8005 8006 kfree(priv->fw_data); 8007 mutex_destroy(&priv->usb_buf_mutex); 8008 mutex_destroy(&priv->syson_indirect_access_mutex); 8009 mutex_destroy(&priv->h2c_mutex); 8010 8011 ieee80211_free_hw(hw); 8012 err_put_dev: 8013 usb_put_dev(udev); 8014 8015 return ret; 8016 } 8017 8018 static void rtl8xxxu_disconnect(struct usb_interface *interface) 8019 { 8020 struct rtl8xxxu_priv *priv; 8021 struct ieee80211_hw *hw; 8022 8023 hw = usb_get_intfdata(interface); 8024 priv = hw->priv; 8025 8026 rtl8xxxu_deinit_led(priv); 8027 8028 ieee80211_unregister_hw(hw); 8029 8030 priv->fops->power_off(priv); 8031 8032 usb_set_intfdata(interface, NULL); 8033 8034 dev_info(&priv->udev->dev, "disconnecting\n"); 8035 8036 kfree(priv->fw_data); 8037 mutex_destroy(&priv->usb_buf_mutex); 8038 mutex_destroy(&priv->syson_indirect_access_mutex); 8039 mutex_destroy(&priv->h2c_mutex); 8040 8041 if (priv->udev->state != USB_STATE_NOTATTACHED) { 8042 dev_info(&priv->udev->dev, 8043 "Device still attached, trying to reset\n"); 8044 usb_reset_device(priv->udev); 8045 } 8046 usb_put_dev(priv->udev); 8047 ieee80211_free_hw(hw); 8048 } 8049 8050 static const struct usb_device_id dev_table[] = { 8051 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), 8052 .driver_info = (unsigned long)&rtl8723au_fops}, 8053 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), 8054 .driver_info = (unsigned long)&rtl8723au_fops}, 8055 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), 8056 .driver_info = (unsigned long)&rtl8723au_fops}, 8057 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), 8058 .driver_info = (unsigned long)&rtl8192eu_fops}, 8059 /* TP-Link TL-WN822N v4 */ 8060 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), 8061 .driver_info = (unsigned long)&rtl8192eu_fops}, 8062 /* D-Link DWA-131 rev E1, tested by David Patiño */ 8063 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), 8064 .driver_info = (unsigned long)&rtl8192eu_fops}, 8065 /* Tested by Myckel Habets */ 8066 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), 8067 .driver_info = (unsigned long)&rtl8192eu_fops}, 8068 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), 8069 .driver_info = (unsigned long)&rtl8723bu_fops}, 8070 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), 8071 .driver_info = (unsigned long)&rtl8723bu_fops}, 8072 /* RTL8188FU */ 8073 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), 8074 .driver_info = (unsigned long)&rtl8188fu_fops}, 8075 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff), 8076 .driver_info = (unsigned long)&rtl8188eu_fops}, 8077 /* Tested by Hans de Goede - rtl8188etv */ 8078 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff), 8079 .driver_info = (unsigned long)&rtl8188eu_fops}, 8080 /* Sitecom rtl8188eus */ 8081 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff), 8082 .driver_info = (unsigned long)&rtl8188eu_fops}, 8083 /* D-Link USB-GO-N150 */ 8084 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff), 8085 .driver_info = (unsigned long)&rtl8188eu_fops}, 8086 /* D-Link DWA-125 REV D1 */ 8087 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff), 8088 .driver_info = (unsigned long)&rtl8188eu_fops}, 8089 /* D-Link DWA-123 REV D1 */ 8090 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff), 8091 .driver_info = (unsigned long)&rtl8188eu_fops}, 8092 /* D-Link DWA-121 rev B1 */ 8093 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff), 8094 .driver_info = (unsigned long)&rtl8188eu_fops}, 8095 /* Abocom - Abocom */ 8096 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff), 8097 .driver_info = (unsigned long)&rtl8188eu_fops}, 8098 /* Elecom WDC-150SU2M */ 8099 {USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff), 8100 .driver_info = (unsigned long)&rtl8188eu_fops}, 8101 /* TP-Link TL-WN722N v2 */ 8102 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff), 8103 .driver_info = (unsigned long)&rtl8188eu_fops}, 8104 /* TP-Link TL-WN727N v5.21 */ 8105 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff), 8106 .driver_info = (unsigned long)&rtl8188eu_fops}, 8107 /* MERCUSYS MW150US v2 */ 8108 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff), 8109 .driver_info = (unsigned long)&rtl8188eu_fops}, 8110 /* ASUS USB-N10 Nano B1 */ 8111 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff), 8112 .driver_info = (unsigned long)&rtl8188eu_fops}, 8113 /* Edimax EW-7811Un V2 */ 8114 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff), 8115 .driver_info = (unsigned long)&rtl8188eu_fops}, 8116 /* Rosewill USB-N150 Nano */ 8117 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff), 8118 .driver_info = (unsigned long)&rtl8188eu_fops}, 8119 /* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */ 8120 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff), 8121 .driver_info = (unsigned long)&rtl8710bu_fops}, 8122 /* TOTOLINK N150UA V5 / N150UA-B */ 8123 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff), 8124 .driver_info = (unsigned long)&rtl8710bu_fops}, 8125 /* Comfast CF-826F */ 8126 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff), 8127 .driver_info = (unsigned long)&rtl8192fu_fops}, 8128 /* Asus USB-N13 rev C1 */ 8129 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff), 8130 .driver_info = (unsigned long)&rtl8192fu_fops}, 8131 /* EDIMAX EW-7722UTn V3 */ 8132 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff), 8133 .driver_info = (unsigned long)&rtl8192fu_fops}, 8134 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff), 8135 .driver_info = (unsigned long)&rtl8192fu_fops}, 8136 /* TP-Link TL-WN823N V2 */ 8137 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0135, 0xff, 0xff, 0xff), 8138 .driver_info = (unsigned long)&rtl8192fu_fops}, 8139 #ifdef CONFIG_RTL8XXXU_UNTESTED 8140 /* Still supported by rtlwifi */ 8141 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), 8142 .driver_info = (unsigned long)&rtl8192cu_fops}, 8143 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), 8144 .driver_info = (unsigned long)&rtl8192cu_fops}, 8145 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), 8146 .driver_info = (unsigned long)&rtl8192cu_fops}, 8147 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x819a, 0xff, 0xff, 0xff), 8148 .driver_info = (unsigned long)&rtl8192cu_fops}, 8149 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8754, 0xff, 0xff, 0xff), 8150 .driver_info = (unsigned long)&rtl8192cu_fops}, 8151 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817c, 0xff, 0xff, 0xff), 8152 .driver_info = (unsigned long)&rtl8192cu_fops}, 8153 /* Tested by Larry Finger */ 8154 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), 8155 .driver_info = (unsigned long)&rtl8192cu_fops}, 8156 /* Tested by Andrea Merello */ 8157 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), 8158 .driver_info = (unsigned long)&rtl8192cu_fops}, 8159 /* Tested by Jocelyn Mayer */ 8160 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), 8161 .driver_info = (unsigned long)&rtl8192cu_fops}, 8162 /* Tested by Stefano Bravi */ 8163 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), 8164 .driver_info = (unsigned long)&rtl8192cu_fops}, 8165 /* Currently untested 8188 series devices */ 8166 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), 8167 .driver_info = (unsigned long)&rtl8192cu_fops}, 8168 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), 8169 .driver_info = (unsigned long)&rtl8192cu_fops}, 8170 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), 8171 .driver_info = (unsigned long)&rtl8192cu_fops}, 8172 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), 8173 .driver_info = (unsigned long)&rtl8192cu_fops}, 8174 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), 8175 .driver_info = (unsigned long)&rtl8192cu_fops}, 8176 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), 8177 .driver_info = (unsigned long)&rtl8192cu_fops}, 8178 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), 8179 .driver_info = (unsigned long)&rtl8192cu_fops}, 8180 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), 8181 .driver_info = (unsigned long)&rtl8192cu_fops}, 8182 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8186, 0xff, 0xff, 0xff), 8183 .driver_info = (unsigned long)&rtl8192cu_fops}, 8184 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), 8185 .driver_info = (unsigned long)&rtl8192cu_fops}, 8186 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), 8187 .driver_info = (unsigned long)&rtl8192cu_fops}, 8188 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), 8189 .driver_info = (unsigned long)&rtl8192cu_fops}, 8190 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), 8191 .driver_info = (unsigned long)&rtl8192cu_fops}, 8192 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), 8193 .driver_info = (unsigned long)&rtl8192cu_fops}, 8194 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x11f2, 0xff, 0xff, 0xff), 8195 .driver_info = (unsigned long)&rtl8192cu_fops}, 8196 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 8197 .driver_info = (unsigned long)&rtl8192cu_fops}, 8198 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 8199 .driver_info = (unsigned long)&rtl8192cu_fops}, 8200 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), 8201 .driver_info = (unsigned long)&rtl8192cu_fops}, 8202 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9043, 0xff, 0xff, 0xff), 8203 .driver_info = (unsigned long)&rtl8192cu_fops}, 8204 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), 8205 .driver_info = (unsigned long)&rtl8192cu_fops}, 8206 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), 8207 .driver_info = (unsigned long)&rtl8192cu_fops}, 8208 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), 8209 .driver_info = (unsigned long)&rtl8192cu_fops}, 8210 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), 8211 .driver_info = (unsigned long)&rtl8192cu_fops}, 8212 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), 8213 .driver_info = (unsigned long)&rtl8192cu_fops}, 8214 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), 8215 .driver_info = (unsigned long)&rtl8192cu_fops}, 8216 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), 8217 .driver_info = (unsigned long)&rtl8192cu_fops}, 8218 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), 8219 .driver_info = (unsigned long)&rtl8192cu_fops}, 8220 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3358, 0xff, 0xff, 0xff), 8221 .driver_info = (unsigned long)&rtl8192cu_fops}, 8222 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3359, 0xff, 0xff, 0xff), 8223 .driver_info = (unsigned long)&rtl8192cu_fops}, 8224 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), 8225 .driver_info = (unsigned long)&rtl8192cu_fops}, 8226 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), 8227 .driver_info = (unsigned long)&rtl8192cu_fops}, 8228 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), 8229 .driver_info = (unsigned long)&rtl8192cu_fops}, 8230 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), 8231 .driver_info = (unsigned long)&rtl8192cu_fops}, 8232 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), 8233 .driver_info = (unsigned long)&rtl8192cu_fops}, 8234 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), 8235 .driver_info = (unsigned long)&rtl8192cu_fops}, 8236 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), 8237 .driver_info = (unsigned long)&rtl8192cu_fops}, 8238 {USB_DEVICE_AND_INTERFACE_INFO(0x9846, 0x9041, 0xff, 0xff, 0xff), 8239 .driver_info = (unsigned long)&rtl8192cu_fops}, 8240 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), 8241 .driver_info = (unsigned long)&rtl8192cu_fops}, 8242 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), 8243 .driver_info = (unsigned long)&rtl8192cu_fops}, 8244 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), 8245 .driver_info = (unsigned long)&rtl8192cu_fops}, 8246 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), 8247 .driver_info = (unsigned long)&rtl8192cu_fops}, 8248 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), 8249 .driver_info = (unsigned long)&rtl8192cu_fops}, 8250 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), 8251 .driver_info = (unsigned long)&rtl8192cu_fops}, 8252 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), 8253 .driver_info = (unsigned long)&rtl8192cu_fops}, 8254 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), 8255 .driver_info = (unsigned long)&rtl8192cu_fops}, 8256 /* Currently untested 8192 series devices */ 8257 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), 8258 .driver_info = (unsigned long)&rtl8192cu_fops}, 8259 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), 8260 .driver_info = (unsigned long)&rtl8192cu_fops}, 8261 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), 8262 .driver_info = (unsigned long)&rtl8192cu_fops}, 8263 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), 8264 .driver_info = (unsigned long)&rtl8192cu_fops}, 8265 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 8266 .driver_info = (unsigned long)&rtl8192cu_fops}, 8267 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), 8268 .driver_info = (unsigned long)&rtl8192cu_fops}, 8269 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), 8270 .driver_info = (unsigned long)&rtl8192cu_fops}, 8271 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), 8272 .driver_info = (unsigned long)&rtl8192cu_fops}, 8273 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), 8274 .driver_info = (unsigned long)&rtl8192cu_fops}, 8275 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0077, 0xff, 0xff, 0xff), 8276 .driver_info = (unsigned long)&rtl8192cu_fops}, 8277 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), 8278 .driver_info = (unsigned long)&rtl8192cu_fops}, 8279 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), 8280 .driver_info = (unsigned long)&rtl8192cu_fops}, 8281 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), 8282 .driver_info = (unsigned long)&rtl8192cu_fops}, 8283 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), 8284 .driver_info = (unsigned long)&rtl8192cu_fops}, 8285 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), 8286 .driver_info = (unsigned long)&rtl8192cu_fops}, 8287 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), 8288 .driver_info = (unsigned long)&rtl8192cu_fops}, 8289 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), 8290 .driver_info = (unsigned long)&rtl8192cu_fops}, 8291 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), 8292 .driver_info = (unsigned long)&rtl8192cu_fops}, 8293 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), 8294 .driver_info = (unsigned long)&rtl8192cu_fops}, 8295 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), 8296 .driver_info = (unsigned long)&rtl8192cu_fops}, 8297 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), 8298 .driver_info = (unsigned long)&rtl8192cu_fops}, 8299 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330d, 0xff, 0xff, 0xff), 8300 .driver_info = (unsigned long)&rtl8192cu_fops}, 8301 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), 8302 .driver_info = (unsigned long)&rtl8192cu_fops}, 8303 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), 8304 .driver_info = (unsigned long)&rtl8192cu_fops}, 8305 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), 8306 .driver_info = (unsigned long)&rtl8192cu_fops}, 8307 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), 8308 .driver_info = (unsigned long)&rtl8192cu_fops}, 8309 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), 8310 .driver_info = (unsigned long)&rtl8192cu_fops}, 8311 /* found in rtl8192eu vendor driver */ 8312 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), 8313 .driver_info = (unsigned long)&rtl8192eu_fops}, 8314 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), 8315 .driver_info = (unsigned long)&rtl8192eu_fops}, 8316 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), 8317 .driver_info = (unsigned long)&rtl8192eu_fops}, 8318 /* D-Link DWA-131 rev C1 */ 8319 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff), 8320 .driver_info = (unsigned long)&rtl8192eu_fops}, 8321 /* TP-Link TL-WN8200ND V2 */ 8322 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff), 8323 .driver_info = (unsigned long)&rtl8192eu_fops}, 8324 /* Mercusys MW300UM */ 8325 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff), 8326 .driver_info = (unsigned long)&rtl8192eu_fops}, 8327 /* Mercusys MW300UH */ 8328 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff), 8329 .driver_info = (unsigned long)&rtl8192eu_fops}, 8330 #endif 8331 { } 8332 }; 8333 8334 static struct usb_driver rtl8xxxu_driver = { 8335 .name = DRIVER_NAME, 8336 .probe = rtl8xxxu_probe, 8337 .disconnect = rtl8xxxu_disconnect, 8338 .id_table = dev_table, 8339 .no_dynamic_id = 1, 8340 .disable_hub_initiated_lpm = 1, 8341 }; 8342 8343 MODULE_DEVICE_TABLE(usb, dev_table); 8344 8345 module_usb_driver(rtl8xxxu_driver); 8346