1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver - 8188c/8188r/8192c specific subdriver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include "regs.h" 17 #include "rtl8xxxu.h" 18 19 #ifdef CONFIG_RTL8XXXU_UNTESTED 20 static struct rtl8xxxu_power_base rtl8192c_power_base = { 21 .reg_0e00 = 0x07090c0c, 22 .reg_0e04 = 0x01020405, 23 .reg_0e08 = 0x00000000, 24 .reg_086c = 0x00000000, 25 26 .reg_0e10 = 0x0b0c0c0e, 27 .reg_0e14 = 0x01030506, 28 .reg_0e18 = 0x0b0c0d0e, 29 .reg_0e1c = 0x01030509, 30 31 .reg_0830 = 0x07090c0c, 32 .reg_0834 = 0x01020405, 33 .reg_0838 = 0x00000000, 34 .reg_086c_2 = 0x00000000, 35 36 .reg_083c = 0x0b0c0d0e, 37 .reg_0848 = 0x01030509, 38 .reg_084c = 0x0b0c0d0e, 39 .reg_0868 = 0x01030509, 40 }; 41 42 static struct rtl8xxxu_power_base rtl8188r_power_base = { 43 .reg_0e00 = 0x06080808, 44 .reg_0e04 = 0x00040406, 45 .reg_0e08 = 0x00000000, 46 .reg_086c = 0x00000000, 47 48 .reg_0e10 = 0x04060608, 49 .reg_0e14 = 0x00020204, 50 .reg_0e18 = 0x04060608, 51 .reg_0e1c = 0x00020204, 52 53 .reg_0830 = 0x06080808, 54 .reg_0834 = 0x00040406, 55 .reg_0838 = 0x00000000, 56 .reg_086c_2 = 0x00000000, 57 58 .reg_083c = 0x04060608, 59 .reg_0848 = 0x00020204, 60 .reg_084c = 0x04060608, 61 .reg_0868 = 0x00020204, 62 }; 63 64 static const struct rtl8xxxu_reg8val rtl8192cu_mac_init_table[] = { 65 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 66 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 67 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 68 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 69 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 70 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 71 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 72 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 73 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 74 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 75 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 76 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 77 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 78 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 79 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 80 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 81 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 82 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 83 {0x652, 0x20}, {0x652, 0x20}, {0x63c, 0x08}, {0x63d, 0x08}, 84 {0x63e, 0x0c}, {0x63f, 0x0c}, {0x66e, 0x05}, {0x700, 0x21}, 85 {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, 86 {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, 87 {0xffff, 0xff}, 88 }; 89 90 static const struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { 91 {0x00, 0x00030159}, {0x01, 0x00031284}, 92 {0x02, 0x00098000}, {0x03, 0x00018c63}, 93 {0x04, 0x000210e7}, {0x09, 0x0002044f}, 94 {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, 95 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, 96 {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 97 {0x19, 0x00000000}, {0x1a, 0x00010255}, 98 {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 99 {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, 100 {0x1f, 0x00080001}, {0x20, 0x0000b614}, 101 {0x21, 0x0006c000}, {0x22, 0x00000000}, 102 {0x23, 0x00001558}, {0x24, 0x00000060}, 103 {0x25, 0x00000483}, {0x26, 0x0004f000}, 104 {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, 105 {0x29, 0x00004783}, {0x2a, 0x00000001}, 106 {0x2b, 0x00021334}, {0x2a, 0x00000000}, 107 {0x2b, 0x00000054}, {0x2a, 0x00000001}, 108 {0x2b, 0x00000808}, {0x2b, 0x00053333}, 109 {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 110 {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 111 {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 112 {0x2b, 0x00000808}, {0x2b, 0x00063333}, 113 {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 114 {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 115 {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 116 {0x2b, 0x00000808}, {0x2b, 0x00073333}, 117 {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 118 {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 119 {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 120 {0x2b, 0x00000709}, {0x2b, 0x00063333}, 121 {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 122 {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 123 {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 124 {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 125 {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 126 {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 127 {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 128 {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 129 {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 130 {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 131 {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 132 {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 133 {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 134 {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 135 {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 136 {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 137 {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 138 {0x10, 0x0002000f}, {0x11, 0x000203f9}, 139 {0x10, 0x0003000f}, {0x11, 0x000ff500}, 140 {0x10, 0x00000000}, {0x11, 0x00000000}, 141 {0x10, 0x0008000f}, {0x11, 0x0003f100}, 142 {0x10, 0x0009000f}, {0x11, 0x00023100}, 143 {0x12, 0x00032000}, {0x12, 0x00071000}, 144 {0x12, 0x000b0000}, {0x12, 0x000fc000}, 145 {0x13, 0x000287b3}, {0x13, 0x000244b7}, 146 {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 147 {0x13, 0x00018493}, {0x13, 0x0001429b}, 148 {0x13, 0x00010299}, {0x13, 0x0000c29c}, 149 {0x13, 0x000081a0}, {0x13, 0x000040ac}, 150 {0x13, 0x00000020}, {0x14, 0x0001944c}, 151 {0x14, 0x00059444}, {0x14, 0x0009944c}, 152 {0x14, 0x000d9444}, {0x15, 0x0000f424}, 153 {0x15, 0x0004f424}, {0x15, 0x0008f424}, 154 {0x15, 0x000cf424}, {0x16, 0x000e0330}, 155 {0x16, 0x000a0330}, {0x16, 0x00060330}, 156 {0x16, 0x00020330}, {0x00, 0x00010159}, 157 {0x18, 0x0000f401}, {0xfe, 0x00000000}, 158 {0xfe, 0x00000000}, {0x1f, 0x00080003}, 159 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 160 {0x1e, 0x00044457}, {0x1f, 0x00080000}, 161 {0x00, 0x00030159}, 162 {0xff, 0xffffffff} 163 }; 164 165 static const struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { 166 {0x00, 0x00030159}, {0x01, 0x00031284}, 167 {0x02, 0x00098000}, {0x03, 0x00018c63}, 168 {0x04, 0x000210e7}, {0x09, 0x0002044f}, 169 {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, 170 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, 171 {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 172 {0x12, 0x00032000}, {0x12, 0x00071000}, 173 {0x12, 0x000b0000}, {0x12, 0x000fc000}, 174 {0x13, 0x000287af}, {0x13, 0x000244b7}, 175 {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 176 {0x13, 0x00018493}, {0x13, 0x00014297}, 177 {0x13, 0x00010295}, {0x13, 0x0000c298}, 178 {0x13, 0x0000819c}, {0x13, 0x000040a8}, 179 {0x13, 0x0000001c}, {0x14, 0x0001944c}, 180 {0x14, 0x00059444}, {0x14, 0x0009944c}, 181 {0x14, 0x000d9444}, {0x15, 0x0000f424}, 182 {0x15, 0x0004f424}, {0x15, 0x0008f424}, 183 {0x15, 0x000cf424}, {0x16, 0x000e0330}, 184 {0x16, 0x000a0330}, {0x16, 0x00060330}, 185 {0x16, 0x00020330}, 186 {0xff, 0xffffffff} 187 }; 188 189 static const struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { 190 {0x00, 0x00030159}, {0x01, 0x00031284}, 191 {0x02, 0x00098000}, {0x03, 0x00018c63}, 192 {0x04, 0x000210e7}, {0x09, 0x0002044f}, 193 {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, 194 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, 195 {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 196 {0x19, 0x00000000}, {0x1a, 0x00010255}, 197 {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 198 {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, 199 {0x1f, 0x00080001}, {0x20, 0x0000b614}, 200 {0x21, 0x0006c000}, {0x22, 0x00000000}, 201 {0x23, 0x00001558}, {0x24, 0x00000060}, 202 {0x25, 0x00000483}, {0x26, 0x0004f000}, 203 {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, 204 {0x29, 0x00004783}, {0x2a, 0x00000001}, 205 {0x2b, 0x00021334}, {0x2a, 0x00000000}, 206 {0x2b, 0x00000054}, {0x2a, 0x00000001}, 207 {0x2b, 0x00000808}, {0x2b, 0x00053333}, 208 {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 209 {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 210 {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 211 {0x2b, 0x00000808}, {0x2b, 0x00063333}, 212 {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 213 {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 214 {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 215 {0x2b, 0x00000808}, {0x2b, 0x00073333}, 216 {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 217 {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 218 {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 219 {0x2b, 0x00000709}, {0x2b, 0x00063333}, 220 {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 221 {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 222 {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 223 {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 224 {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 225 {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 226 {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 227 {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 228 {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 229 {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 230 {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 231 {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 232 {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 233 {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 234 {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 235 {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 236 {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 237 {0x10, 0x0002000f}, {0x11, 0x000203f9}, 238 {0x10, 0x0003000f}, {0x11, 0x000ff500}, 239 {0x10, 0x00000000}, {0x11, 0x00000000}, 240 {0x10, 0x0008000f}, {0x11, 0x0003f100}, 241 {0x10, 0x0009000f}, {0x11, 0x00023100}, 242 {0x12, 0x00032000}, {0x12, 0x00071000}, 243 {0x12, 0x000b0000}, {0x12, 0x000fc000}, 244 {0x13, 0x000287b3}, {0x13, 0x000244b7}, 245 {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 246 {0x13, 0x00018493}, {0x13, 0x0001429b}, 247 {0x13, 0x00010299}, {0x13, 0x0000c29c}, 248 {0x13, 0x000081a0}, {0x13, 0x000040ac}, 249 {0x13, 0x00000020}, {0x14, 0x0001944c}, 250 {0x14, 0x00059444}, {0x14, 0x0009944c}, 251 {0x14, 0x000d9444}, {0x15, 0x0000f405}, 252 {0x15, 0x0004f405}, {0x15, 0x0008f405}, 253 {0x15, 0x000cf405}, {0x16, 0x000e0330}, 254 {0x16, 0x000a0330}, {0x16, 0x00060330}, 255 {0x16, 0x00020330}, {0x00, 0x00010159}, 256 {0x18, 0x0000f401}, {0xfe, 0x00000000}, 257 {0xfe, 0x00000000}, {0x1f, 0x00080003}, 258 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 259 {0x1e, 0x00044457}, {0x1f, 0x00080000}, 260 {0x00, 0x00030159}, 261 {0xff, 0xffffffff} 262 }; 263 264 static const struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { 265 {0x00, 0x00030159}, {0x01, 0x00031284}, 266 {0x02, 0x00098000}, {0x03, 0x00018c63}, 267 {0x04, 0x000210e7}, {0x09, 0x0002044f}, 268 {0x0a, 0x0001adb0}, {0x0b, 0x00054867}, 269 {0x0c, 0x0008992e}, {0x0d, 0x0000e529}, 270 {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 271 {0x19, 0x00000000}, {0x1a, 0x00000255}, 272 {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 273 {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, 274 {0x1f, 0x00080001}, {0x20, 0x0000b614}, 275 {0x21, 0x0006c000}, {0x22, 0x0000083c}, 276 {0x23, 0x00001558}, {0x24, 0x00000060}, 277 {0x25, 0x00000483}, {0x26, 0x0004f000}, 278 {0x27, 0x000ec7d9}, {0x28, 0x000977c0}, 279 {0x29, 0x00004783}, {0x2a, 0x00000001}, 280 {0x2b, 0x00021334}, {0x2a, 0x00000000}, 281 {0x2b, 0x00000054}, {0x2a, 0x00000001}, 282 {0x2b, 0x00000808}, {0x2b, 0x00053333}, 283 {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 284 {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 285 {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 286 {0x2b, 0x00000808}, {0x2b, 0x00063333}, 287 {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 288 {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 289 {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 290 {0x2b, 0x00000808}, {0x2b, 0x00073333}, 291 {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 292 {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 293 {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 294 {0x2b, 0x00000709}, {0x2b, 0x00063333}, 295 {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 296 {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 297 {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 298 {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 299 {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 300 {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 301 {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 302 {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 303 {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 304 {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 305 {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 306 {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 307 {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 308 {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 309 {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 310 {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 311 {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 312 {0x10, 0x0002000f}, {0x11, 0x000203f9}, 313 {0x10, 0x0003000f}, {0x11, 0x000ff500}, 314 {0x10, 0x00000000}, {0x11, 0x00000000}, 315 {0x10, 0x0008000f}, {0x11, 0x0003f100}, 316 {0x10, 0x0009000f}, {0x11, 0x00023100}, 317 {0x12, 0x000d8000}, {0x12, 0x00090000}, 318 {0x12, 0x00051000}, {0x12, 0x00012000}, 319 {0x13, 0x00028fb4}, {0x13, 0x00024fa8}, 320 {0x13, 0x000207a4}, {0x13, 0x0001c3b0}, 321 {0x13, 0x000183a4}, {0x13, 0x00014398}, 322 {0x13, 0x000101a4}, {0x13, 0x0000c198}, 323 {0x13, 0x000080a4}, {0x13, 0x00004098}, 324 {0x13, 0x00000000}, {0x14, 0x0001944c}, 325 {0x14, 0x00059444}, {0x14, 0x0009944c}, 326 {0x14, 0x000d9444}, {0x15, 0x0000f405}, 327 {0x15, 0x0004f405}, {0x15, 0x0008f405}, 328 {0x15, 0x000cf405}, {0x16, 0x000e0330}, 329 {0x16, 0x000a0330}, {0x16, 0x00060330}, 330 {0x16, 0x00020330}, {0x00, 0x00010159}, 331 {0x18, 0x0000f401}, {0xfe, 0x00000000}, 332 {0xfe, 0x00000000}, {0x1f, 0x00080003}, 333 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 334 {0x1e, 0x00044457}, {0x1f, 0x00080000}, 335 {0x00, 0x00030159}, 336 {0xff, 0xffffffff} 337 }; 338 339 static int rtl8192cu_identify_chip(struct rtl8xxxu_priv *priv) 340 { 341 struct device *dev = &priv->udev->dev; 342 u32 val32, bonding, sys_cfg, vendor; 343 int ret = 0; 344 345 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 346 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 347 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 348 dev_info(dev, "Unsupported test chip\n"); 349 ret = -ENOTSUPP; 350 goto out; 351 } 352 353 if (sys_cfg & SYS_CFG_TYPE_ID) { 354 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); 355 bonding &= HPON_FSM_BONDING_MASK; 356 if (bonding == HPON_FSM_BONDING_1T2R) { 357 strscpy(priv->chip_name, "8191CU", sizeof(priv->chip_name)); 358 priv->tx_paths = 1; 359 priv->usb_interrupts = 1; 360 priv->rtl_chip = RTL8191C; 361 } else { 362 strscpy(priv->chip_name, "8192CU", sizeof(priv->chip_name)); 363 priv->tx_paths = 2; 364 priv->usb_interrupts = 0; 365 priv->rtl_chip = RTL8192C; 366 } 367 priv->rf_paths = 2; 368 priv->rx_paths = 2; 369 } else { 370 strscpy(priv->chip_name, "8188CU", sizeof(priv->chip_name)); 371 priv->rf_paths = 1; 372 priv->rx_paths = 1; 373 priv->tx_paths = 1; 374 priv->rtl_chip = RTL8188C; 375 priv->usb_interrupts = 0; 376 } 377 priv->has_wifi = 1; 378 379 vendor = sys_cfg & SYS_CFG_VENDOR_ID; 380 rtl8xxxu_identify_vendor_1bit(priv, vendor); 381 382 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 383 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); 384 385 rtl8xxxu_config_endpoints_sie(priv); 386 387 /* 388 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 389 */ 390 if (!priv->ep_tx_count) 391 ret = rtl8xxxu_config_endpoints_no_sie(priv); 392 393 out: 394 return ret; 395 } 396 397 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv) 398 { 399 const char *fw_name; 400 int ret; 401 402 if (!priv->vendor_umc) 403 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; 404 else if (priv->chip_cut || priv->rtl_chip == RTL8192C) 405 fw_name = "rtlwifi/rtl8192cufw_B.bin"; 406 else 407 fw_name = "rtlwifi/rtl8192cufw_A.bin"; 408 409 ret = rtl8xxxu_load_firmware(priv, fw_name); 410 411 return ret; 412 } 413 414 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv) 415 { 416 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192; 417 418 if (efuse->rtl_id != cpu_to_le16(0x8129)) 419 return -EINVAL; 420 421 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 422 423 memcpy(priv->cck_tx_power_index_A, 424 efuse->cck_tx_power_index_A, 425 sizeof(efuse->cck_tx_power_index_A)); 426 memcpy(priv->cck_tx_power_index_B, 427 efuse->cck_tx_power_index_B, 428 sizeof(efuse->cck_tx_power_index_B)); 429 430 memcpy(priv->ht40_1s_tx_power_index_A, 431 efuse->ht40_1s_tx_power_index_A, 432 sizeof(efuse->ht40_1s_tx_power_index_A)); 433 memcpy(priv->ht40_1s_tx_power_index_B, 434 efuse->ht40_1s_tx_power_index_B, 435 sizeof(efuse->ht40_1s_tx_power_index_B)); 436 memcpy(priv->ht40_2s_tx_power_index_diff, 437 efuse->ht40_2s_tx_power_index_diff, 438 sizeof(efuse->ht40_2s_tx_power_index_diff)); 439 440 memcpy(priv->ht20_tx_power_index_diff, 441 efuse->ht20_tx_power_index_diff, 442 sizeof(efuse->ht20_tx_power_index_diff)); 443 memcpy(priv->ofdm_tx_power_index_diff, 444 efuse->ofdm_tx_power_index_diff, 445 sizeof(efuse->ofdm_tx_power_index_diff)); 446 447 memcpy(priv->ht40_max_power_offset, 448 efuse->ht40_max_power_offset, 449 sizeof(efuse->ht40_max_power_offset)); 450 memcpy(priv->ht20_max_power_offset, 451 efuse->ht20_max_power_offset, 452 sizeof(efuse->ht20_max_power_offset)); 453 454 priv->power_base = &rtl8192c_power_base; 455 456 if (efuse->rf_regulatory & 0x20) { 457 strscpy(priv->chip_name, "8188RU", sizeof(priv->chip_name)); 458 priv->rtl_chip = RTL8188R; 459 priv->hi_pa = 1; 460 priv->no_pape = 1; 461 priv->power_base = &rtl8188r_power_base; 462 } 463 464 return 0; 465 } 466 467 static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv) 468 { 469 const struct rtl8xxxu_rfregval *rftable; 470 int ret; 471 472 if (priv->rtl_chip == RTL8188R) { 473 rftable = rtl8188ru_radioa_1t_highpa_table; 474 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); 475 } else if (priv->rf_paths == 1) { 476 rftable = rtl8192cu_radioa_1t_init_table; 477 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); 478 } else { 479 rftable = rtl8192cu_radioa_2t_init_table; 480 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); 481 if (ret) 482 goto exit; 483 rftable = rtl8192cu_radiob_2t_init_table; 484 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); 485 } 486 487 exit: 488 return ret; 489 } 490 491 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) 492 { 493 u8 val8; 494 u16 val16; 495 u32 val32; 496 int i; 497 498 for (i = 100; i; i--) { 499 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO); 500 if (val8 & APS_FSMCO_PFM_ALDN) 501 break; 502 } 503 504 if (!i) { 505 pr_info("%s: Poll failed\n", __func__); 506 return -ENODEV; 507 } 508 509 /* 510 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register 511 */ 512 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); 513 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b); 514 udelay(100); 515 516 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL); 517 if (!(val8 & LDOV12D_ENABLE)) { 518 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8); 519 val8 |= LDOV12D_ENABLE; 520 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8); 521 522 udelay(100); 523 524 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 525 val8 &= ~SYS_ISO_MD2PP; 526 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 527 } 528 529 /* 530 * Auto enable WLAN 531 */ 532 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 533 val16 |= APS_FSMCO_MAC_ENABLE; 534 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 535 536 for (i = 1000; i; i--) { 537 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 538 if (!(val16 & APS_FSMCO_MAC_ENABLE)) 539 break; 540 } 541 if (!i) { 542 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__); 543 return -EBUSY; 544 } 545 546 /* 547 * Enable radio, GPIO, LED 548 */ 549 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN | 550 APS_FSMCO_PFM_ALDN; 551 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 552 553 /* 554 * Release RF digital isolation 555 */ 556 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); 557 val16 &= ~SYS_ISO_DIOR; 558 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); 559 560 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); 561 val8 &= ~APSD_CTRL_OFF; 562 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8); 563 for (i = 200; i; i--) { 564 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); 565 if (!(val8 & APSD_CTRL_OFF_STATUS)) 566 break; 567 } 568 569 if (!i) { 570 pr_info("%s: APSD_CTRL poll failed\n", __func__); 571 return -EBUSY; 572 } 573 574 /* 575 * Enable MAC DMA/WMAC/SCHEDULE/SEC block 576 */ 577 val16 = rtl8xxxu_read16(priv, REG_CR); 578 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 579 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE | 580 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE; 581 rtl8xxxu_write16(priv, REG_CR, val16); 582 583 rtl8xxxu_write8(priv, 0xfe10, 0x19); 584 585 /* 586 * Workaround for 8188RU LNA power leakage problem. 587 */ 588 if (priv->rtl_chip == RTL8188R) { 589 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); 590 val32 &= ~BIT(1); 591 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); 592 } 593 return 0; 594 } 595 596 static int rtl8192cu_led_brightness_set(struct led_classdev *led_cdev, 597 enum led_brightness brightness) 598 { 599 struct rtl8xxxu_priv *priv = container_of(led_cdev, 600 struct rtl8xxxu_priv, 601 led_cdev); 602 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG0); 603 604 if (brightness == LED_OFF) 605 ledcfg = LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; 606 else if (brightness == LED_ON) 607 ledcfg = LEDCFG2_SW_LED_CONTROL; 608 else if (brightness == RTL8XXXU_HW_LED_CONTROL) 609 ledcfg = LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; 610 611 rtl8xxxu_write8(priv, REG_LEDCFG0, ledcfg); 612 613 return 0; 614 } 615 616 struct rtl8xxxu_fileops rtl8192cu_fops = { 617 .identify_chip = rtl8192cu_identify_chip, 618 .parse_efuse = rtl8192cu_parse_efuse, 619 .load_firmware = rtl8192cu_load_firmware, 620 .power_on = rtl8192cu_power_on, 621 .power_off = rtl8xxxu_power_off, 622 .read_efuse = rtl8xxxu_read_efuse, 623 .reset_8051 = rtl8xxxu_reset_8051, 624 .llt_init = rtl8xxxu_init_llt_table, 625 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, 626 .init_phy_rf = rtl8192cu_init_phy_rf, 627 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, 628 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, 629 .config_channel = rtl8xxxu_gen1_config_channel, 630 .parse_rx_desc = rtl8xxxu_parse_rxdesc16, 631 .parse_phystats = rtl8723au_rx_parse_phystats, 632 .init_aggregation = rtl8xxxu_gen1_init_aggregation, 633 .enable_rf = rtl8xxxu_gen1_enable_rf, 634 .disable_rf = rtl8xxxu_gen1_disable_rf, 635 .usb_quirks = rtl8xxxu_gen1_usb_quirks, 636 .set_tx_power = rtl8xxxu_gen1_set_tx_power, 637 .update_rate_mask = rtl8xxxu_update_rate_mask, 638 .report_connect = rtl8xxxu_gen1_report_connect, 639 .report_rssi = rtl8xxxu_gen1_report_rssi, 640 .fill_txdesc = rtl8xxxu_fill_txdesc_v1, 641 .cck_rssi = rtl8723a_cck_rssi, 642 .led_classdev_brightness_set = rtl8192cu_led_brightness_set, 643 .writeN_block_size = 128, 644 .rx_agg_buf_size = 16000, 645 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), 646 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), 647 .max_sec_cam_num = 32, 648 .adda_1t_init = 0x0b1b25a0, 649 .adda_1t_path_on = 0x0bdb25a0, 650 .adda_2t_path_on_a = 0x04db25a4, 651 .adda_2t_path_on_b = 0x0b1b25a4, 652 .trxff_boundary = 0x27ff, 653 .pbp_rx = PBP_PAGE_SIZE_128, 654 .pbp_tx = PBP_PAGE_SIZE_128, 655 .mactable = rtl8192cu_mac_init_table, 656 .total_page_num = TX_TOTAL_PAGE_NUM, 657 .page_num_hi = TX_PAGE_NUM_HI_PQ, 658 .page_num_lo = TX_PAGE_NUM_LO_PQ, 659 .page_num_norm = TX_PAGE_NUM_NORM_PQ, 660 }; 661 #endif 662