1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver - 8188f specific subdriver 4 * 5 * Copyright (c) 2022 Bitterblue Smith <rtl8821cerfe2@gmail.com> 6 * 7 * Portions copied from existing rtl8xxxu code: 8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 9 * 10 * Portions, notably calibration code: 11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 12 */ 13 14 #include "regs.h" 15 #include "rtl8xxxu.h" 16 17 static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { 18 {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, 19 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, 20 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, 21 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, 22 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, 23 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, 24 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, 25 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, 26 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, 27 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44}, 28 {0x461, 0x44}, {0x4BC, 0xC0}, {0x4C8, 0xFF}, {0x4C9, 0x08}, 29 {0x4CC, 0xFF}, {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, 30 {0x501, 0xA2}, {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, 31 {0x505, 0xA3}, {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, 32 {0x509, 0xA4}, {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, 33 {0x50D, 0xA4}, {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, 34 {0x514, 0x0A}, {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, 35 {0x551, 0x10}, {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, 36 {0x605, 0x30}, {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, 37 {0x621, 0xFF}, {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, 38 {0x625, 0xFF}, {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, 39 {0x63C, 0x0A}, {0x63D, 0x0A}, {0x63E, 0x0E}, {0x63F, 0x0E}, 40 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, 41 {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, 42 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, 43 {0x70B, 0x87}, 44 {0xffff, 0xff}, 45 }; 46 47 static const struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = { 48 {0x800, 0x80045700}, {0x804, 0x00000001}, 49 {0x808, 0x0000FC00}, {0x80C, 0x0000000A}, 50 {0x810, 0x10001331}, {0x814, 0x020C3D10}, 51 {0x818, 0x00200385}, {0x81C, 0x00000000}, 52 {0x820, 0x01000100}, {0x824, 0x00390204}, 53 {0x828, 0x00000000}, {0x82C, 0x00000000}, 54 {0x830, 0x00000000}, {0x834, 0x00000000}, 55 {0x838, 0x00000000}, {0x83C, 0x00000000}, 56 {0x840, 0x00010000}, {0x844, 0x00000000}, 57 {0x848, 0x00000000}, {0x84C, 0x00000000}, 58 {0x850, 0x00030000}, {0x854, 0x00000000}, 59 {0x858, 0x569A569A}, {0x85C, 0x569A569A}, 60 {0x860, 0x00000130}, {0x864, 0x00000000}, 61 {0x868, 0x00000000}, {0x86C, 0x27272700}, 62 {0x870, 0x00000000}, {0x874, 0x25004000}, 63 {0x878, 0x00000808}, {0x87C, 0x004F0201}, 64 {0x880, 0xB0000B1E}, {0x884, 0x00000007}, 65 {0x888, 0x00000000}, {0x88C, 0xCCC000C0}, 66 {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, 67 {0x898, 0x40302010}, {0x89C, 0x00706050}, 68 {0x900, 0x00000000}, {0x904, 0x00000023}, 69 {0x908, 0x00000000}, {0x90C, 0x81121111}, 70 {0x910, 0x00000002}, {0x914, 0x00000201}, 71 {0x948, 0x99000000}, {0x94C, 0x00000010}, 72 {0x950, 0x20003000}, {0x954, 0x4A880000}, 73 {0x958, 0x4BC5D87A}, {0x95C, 0x04EB9B79}, 74 {0x96C, 0x00000003}, {0xA00, 0x00D047C8}, 75 {0xA04, 0x80FF800C}, {0xA08, 0x8C898300}, 76 {0xA0C, 0x2E7F120F}, {0xA10, 0x9500BB78}, 77 {0xA14, 0x1114D028}, {0xA18, 0x00881117}, 78 {0xA1C, 0x89140F00}, {0xA20, 0xD1D80000}, 79 {0xA24, 0x5A7DA0BD}, {0xA28, 0x0000223B}, 80 {0xA2C, 0x00D30000}, {0xA70, 0x101FBF00}, 81 {0xA74, 0x00000007}, {0xA78, 0x00000900}, 82 {0xA7C, 0x225B0606}, {0xA80, 0x218075B1}, 83 {0xA84, 0x00120000}, {0xA88, 0x040C0000}, 84 {0xA8C, 0x12345678}, {0xA90, 0xABCDEF00}, 85 {0xA94, 0x001B1B89}, {0xA98, 0x05100000}, 86 {0xA9C, 0x3F000000}, {0xAA0, 0x00000000}, 87 {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, 88 {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, 89 {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, 90 {0xC14, 0x40000100}, {0xC18, 0x08800000}, 91 {0xC1C, 0x40000100}, {0xC20, 0x00000000}, 92 {0xC24, 0x00000000}, {0xC28, 0x00000000}, 93 {0xC2C, 0x00000000}, {0xC30, 0x69E9CC4A}, 94 {0xC34, 0x31000040}, {0xC38, 0x21688080}, 95 {0xC3C, 0x00001714}, {0xC40, 0x1F78403F}, 96 {0xC44, 0x00010036}, {0xC48, 0xEC020107}, 97 {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, 98 {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, 99 {0xC5C, 0x00250492}, {0xC60, 0x00000000}, 100 {0xC64, 0x7112848B}, {0xC68, 0x47C07BFF}, 101 {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, 102 {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, 103 {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, 104 {0xC84, 0x11F60000}, 105 {0xC88, 0x40000100}, {0xC8C, 0x20200000}, 106 {0xC90, 0x00091521}, {0xC94, 0x00000000}, 107 {0xC98, 0x00121820}, {0xC9C, 0x00007F7F}, 108 {0xCA0, 0x00000000}, {0xCA4, 0x000300A0}, 109 {0xCA8, 0x00000000}, {0xCAC, 0x00000000}, 110 {0xCB0, 0x00000000}, {0xCB4, 0x00000000}, 111 {0xCB8, 0x00000000}, {0xCBC, 0x28000000}, 112 {0xCC0, 0x00000000}, {0xCC4, 0x00000000}, 113 {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, 114 {0xCD0, 0x00000000}, {0xCD4, 0x00000000}, 115 {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, 116 {0xCE0, 0x00222222}, {0xCE4, 0x10000000}, 117 {0xCE8, 0x37644302}, {0xCEC, 0x2F97D40C}, 118 {0xD00, 0x04030740}, {0xD04, 0x40020401}, 119 {0xD08, 0x0000907F}, {0xD0C, 0x20010201}, 120 {0xD10, 0xA0633333}, {0xD14, 0x3333BC53}, 121 {0xD18, 0x7A8F5B6F}, {0xD2C, 0xCB979975}, 122 {0xD30, 0x00000000}, {0xD34, 0x80608000}, 123 {0xD38, 0x98000000}, {0xD3C, 0x40127353}, 124 {0xD40, 0x00000000}, {0xD44, 0x00000000}, 125 {0xD48, 0x00000000}, {0xD4C, 0x00000000}, 126 {0xD50, 0x6437140A}, {0xD54, 0x00000000}, 127 {0xD58, 0x00000282}, {0xD5C, 0x30032064}, 128 {0xD60, 0x4653DE68}, {0xD64, 0x04518A3C}, 129 {0xD68, 0x00002101}, {0xD6C, 0x2A201C16}, 130 {0xD70, 0x1812362E}, {0xD74, 0x322C2220}, 131 {0xD78, 0x000E3C24}, {0xE00, 0x2D2D2D2D}, 132 {0xE04, 0x2D2D2D2D}, {0xE08, 0x0390272D}, 133 {0xE10, 0x2D2D2D2D}, {0xE14, 0x2D2D2D2D}, 134 {0xE18, 0x2D2D2D2D}, {0xE1C, 0x2D2D2D2D}, 135 {0xE28, 0x00000000}, {0xE30, 0x1000DC1F}, 136 {0xE34, 0x10008C1F}, {0xE38, 0x02140102}, 137 {0xE3C, 0x681604C2}, {0xE40, 0x01007C00}, 138 {0xE44, 0x01004800}, {0xE48, 0xFB000000}, 139 {0xE4C, 0x000028D1}, {0xE50, 0x1000DC1F}, 140 {0xE54, 0x10008C1F}, {0xE58, 0x02140102}, 141 {0xE5C, 0x28160D05}, {0xE60, 0x00000008}, 142 {0xE60, 0x021400A0}, {0xE64, 0x281600A0}, 143 {0xE6C, 0x01C00010}, {0xE70, 0x01C00010}, 144 {0xE74, 0x02000010}, {0xE78, 0x02000010}, 145 {0xE7C, 0x02000010}, {0xE80, 0x02000010}, 146 {0xE84, 0x01C00010}, {0xE88, 0x02000010}, 147 {0xE8C, 0x01C00010}, {0xED0, 0x01C00010}, 148 {0xED4, 0x01C00010}, {0xED8, 0x01C00010}, 149 {0xEDC, 0x00000010}, {0xEE0, 0x00000010}, 150 {0xEEC, 0x03C00010}, {0xF14, 0x00000003}, 151 {0xF4C, 0x00000000}, {0xF00, 0x00000300}, 152 {0xffff, 0xffffffff}, 153 }; 154 155 static const struct rtl8xxxu_reg32val rtl8188f_agc_table[] = { 156 {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, 157 {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, 158 {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, 159 {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, 160 {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, 161 {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, 162 {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, 163 {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, 164 {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, 165 {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, 166 {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, 167 {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, 168 {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, 169 {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, 170 {0xC78, 0xE01C0001}, {0xC78, 0xC21D0001}, 171 {0xC78, 0xC11E0001}, {0xC78, 0xC01F0001}, 172 {0xC78, 0xA5200001}, {0xC78, 0xA4210001}, 173 {0xC78, 0xA3220001}, {0xC78, 0xA2230001}, 174 {0xC78, 0xA1240001}, {0xC78, 0xA0250001}, 175 {0xC78, 0x65260001}, {0xC78, 0x64270001}, 176 {0xC78, 0x63280001}, {0xC78, 0x62290001}, 177 {0xC78, 0x612A0001}, {0xC78, 0x442B0001}, 178 {0xC78, 0x432C0001}, {0xC78, 0x422D0001}, 179 {0xC78, 0x412E0001}, {0xC78, 0x402F0001}, 180 {0xC78, 0x21300001}, {0xC78, 0x20310001}, 181 {0xC78, 0x05320001}, {0xC78, 0x04330001}, 182 {0xC78, 0x03340001}, {0xC78, 0x02350001}, 183 {0xC78, 0x01360001}, {0xC78, 0x00370001}, 184 {0xC78, 0x00380001}, {0xC78, 0x00390001}, 185 {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, 186 {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, 187 {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, 188 {0xC50, 0x69553422}, {0xC50, 0x69553420}, 189 {0xffff, 0xffffffff} 190 }; 191 192 static const struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = { 193 {0x00, 0x00030000}, {0x08, 0x00008400}, 194 {0x18, 0x00000407}, {0x19, 0x00000012}, 195 {0x1B, 0x00001C6C}, 196 {0x1E, 0x00080009}, {0x1F, 0x00000880}, 197 {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 198 {0x42, 0x000060C0}, {0x57, 0x000D0000}, 199 {0x58, 0x000C0160}, {0x67, 0x00001552}, 200 {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 201 {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 202 {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 203 {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 204 {0xB8, 0x00010200}, {0xB9, 0x00080001}, 205 {0xBA, 0x00040001}, {0xBB, 0x00000400}, 206 {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 207 {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 208 {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 209 {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 210 {0xC9, 0x00000000}, {0xCA, 0x00080000}, 211 {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 212 {0x51, 0x000E8333}, {0x52, 0x000FAC2C}, 213 {0x53, 0x00000103}, {0x56, 0x000517F0}, 214 {0x35, 0x00000099}, {0x35, 0x00000199}, 215 {0x35, 0x00000299}, {0x36, 0x00000064}, 216 {0x36, 0x00008064}, {0x36, 0x00010064}, 217 {0x36, 0x00018064}, {0x18, 0x00000C07}, 218 {0x5A, 0x00048000}, {0x19, 0x000739D0}, 219 {0x34, 0x0000ADD6}, {0x34, 0x00009DD3}, 220 {0x34, 0x00008CF4}, {0x34, 0x00007CF1}, 221 {0x34, 0x00006CEE}, {0x34, 0x00005CEB}, 222 {0x34, 0x00004CCE}, {0x34, 0x00003CCB}, 223 {0x34, 0x00002CC8}, {0x34, 0x00001C4B}, 224 {0x34, 0x00000C48}, 225 {0x00, 0x00030159}, {0x84, 0x00048000}, 226 {0x86, 0x0000002A}, {0x87, 0x00000025}, 227 {0x8E, 0x00065540}, {0x8F, 0x00088000}, 228 {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 229 {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 230 {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 231 {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 232 {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 233 {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 234 {0x3B, 0x00040700}, {0x3B, 0x00030600}, 235 {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 236 {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 237 {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 238 {0x3B, 0x00010400}, {0xEF, 0x00000000}, 239 {0xEF, 0x00080000}, {0x30, 0x00010000}, 240 {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 241 {0xEF, 0x00000000}, {0x00, 0x00010159}, 242 {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 243 {0xFE, 0x00000000}, {0x1F, 0x00080003}, 244 {0xFE, 0x00000000}, {0xFE, 0x00000000}, 245 {0x1E, 0x00000001}, {0x1F, 0x00080000}, 246 {0x00, 0x00033D95}, 247 {0xff, 0xffffffff} 248 }; 249 250 static const struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = { 251 {0x00, 0x00030000}, {0x08, 0x00008400}, 252 {0x18, 0x00000407}, {0x19, 0x00000012}, 253 {0x1B, 0x00001C6C}, 254 {0x1E, 0x00080009}, {0x1F, 0x00000880}, 255 {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 256 {0x42, 0x000060C0}, {0x57, 0x000D0000}, 257 {0x58, 0x000C0160}, {0x67, 0x00001552}, 258 {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 259 {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 260 {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 261 {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 262 {0xB8, 0x00010200}, {0xB9, 0x00080001}, 263 {0xBA, 0x00040001}, {0xBB, 0x00000400}, 264 {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 265 {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 266 {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 267 {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 268 {0xC9, 0x00000000}, {0xCA, 0x00080000}, 269 {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 270 {0x51, 0x000E8231}, {0x52, 0x000FAC2C}, 271 {0x53, 0x00000141}, {0x56, 0x000517F0}, 272 {0x35, 0x00000090}, {0x35, 0x00000190}, 273 {0x35, 0x00000290}, {0x36, 0x00001064}, 274 {0x36, 0x00009064}, {0x36, 0x00011064}, 275 {0x36, 0x00019064}, {0x18, 0x00000C07}, 276 {0x5A, 0x00048000}, {0x19, 0x000739D0}, 277 {0x34, 0x0000ADD2}, {0x34, 0x00009DD0}, 278 {0x34, 0x00008CF3}, {0x34, 0x00007CF0}, 279 {0x34, 0x00006CED}, {0x34, 0x00005CD2}, 280 {0x34, 0x00004CCF}, {0x34, 0x00003CCC}, 281 {0x34, 0x00002CC9}, {0x34, 0x00001C4C}, 282 {0x34, 0x00000C49}, 283 {0x00, 0x00030159}, {0x84, 0x00048000}, 284 {0x86, 0x0000002A}, {0x87, 0x00000025}, 285 {0x8E, 0x00065540}, {0x8F, 0x00088000}, 286 {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 287 {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 288 {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 289 {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 290 {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 291 {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 292 {0x3B, 0x00040700}, {0x3B, 0x00030600}, 293 {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 294 {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 295 {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 296 {0x3B, 0x00010400}, {0xEF, 0x00000000}, 297 {0xEF, 0x00080000}, {0x30, 0x00010000}, 298 {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 299 {0xEF, 0x00000000}, {0x00, 0x00010159}, 300 {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 301 {0xFE, 0x00000000}, {0x1F, 0x00080003}, 302 {0xFE, 0x00000000}, {0xFE, 0x00000000}, 303 {0x1E, 0x00000001}, {0x1F, 0x00080000}, 304 {0x00, 0x00033D95}, 305 {0xff, 0xffffffff} 306 }; 307 308 static int rtl8188fu_identify_chip(struct rtl8xxxu_priv *priv) 309 { 310 struct device *dev = &priv->udev->dev; 311 u32 sys_cfg, vendor; 312 int ret = 0; 313 314 strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name)); 315 priv->rtl_chip = RTL8188F; 316 priv->rf_paths = 1; 317 priv->rx_paths = 1; 318 priv->tx_paths = 1; 319 priv->has_wifi = 1; 320 321 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 322 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 323 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 324 dev_info(dev, "Unsupported test chip\n"); 325 ret = -ENOTSUPP; 326 goto out; 327 } 328 329 vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; 330 rtl8xxxu_identify_vendor_2bits(priv, vendor); 331 332 ret = rtl8xxxu_config_endpoints_no_sie(priv); 333 334 out: 335 return ret; 336 } 337 338 void rtl8188f_channel_to_group(int channel, int *group, int *cck_group) 339 { 340 if (channel < 3) 341 *group = 0; 342 else if (channel < 6) 343 *group = 1; 344 else if (channel < 9) 345 *group = 2; 346 else if (channel < 12) 347 *group = 3; 348 else 349 *group = 4; 350 351 if (channel == 14) 352 *cck_group = 5; 353 else 354 *cck_group = *group; 355 } 356 357 void 358 rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 359 { 360 u32 val32, ofdm, mcs; 361 u8 cck, ofdmbase, mcsbase; 362 int group, cck_group; 363 364 rtl8188f_channel_to_group(channel, &group, &cck_group); 365 366 cck = priv->cck_tx_power_index_A[cck_group]; 367 368 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 369 val32 &= 0xffff00ff; 370 val32 |= (cck << 8); 371 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 372 373 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 374 val32 &= 0xff; 375 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 376 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 377 378 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; 379 ofdmbase += priv->ofdm_tx_power_diff[0].a; 380 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 381 382 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); 383 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); 384 385 mcsbase = priv->ht40_1s_tx_power_index_A[group]; 386 if (ht40) 387 /* This diff is always 0 - not used in 8188FU. */ 388 mcsbase += priv->ht40_tx_power_diff[0].a; 389 else 390 mcsbase += priv->ht20_tx_power_diff[0].a; 391 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 392 393 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); 394 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); 395 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); 396 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); 397 } 398 399 /* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ 400 static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) 401 { 402 static const u32 frequencies[14 + 1] = { 403 [5] = 0xFCCD, 404 [6] = 0xFC4D, 405 [7] = 0xFFCD, 406 [8] = 0xFF4D, 407 [11] = 0xFDCD, 408 [13] = 0xFCCD, 409 [14] = 0xFF9A 410 }; 411 412 static const u32 reg_d40[14 + 1] = { 413 [5] = 0x06000000, 414 [6] = 0x00000600, 415 [13] = 0x06000000 416 }; 417 418 static const u32 reg_d44[14 + 1] = { 419 [11] = 0x04000000 420 }; 421 422 static const u32 reg_d4c[14 + 1] = { 423 [7] = 0x06000000, 424 [8] = 0x00000380, 425 [14] = 0x00180000 426 }; 427 428 const u8 threshold = 0x16; 429 bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1 = 0, sw_ctrl_s1 = 0; 430 u32 val32, initial_gain, reg948; 431 432 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 433 val32 |= GENMASK(28, 24); 434 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 435 436 /* enable notch filter */ 437 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 438 val32 |= BIT(9); 439 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 440 441 if (channel <= 14 && frequencies[channel] > 0) { 442 reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 443 hw_ctrl = reg948 & BIT(6); 444 sw_ctrl = !hw_ctrl; 445 446 if (hw_ctrl) { 447 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 448 val32 &= GENMASK(5, 3); 449 hw_ctrl_s1 = val32 == BIT(3); 450 } else if (sw_ctrl) { 451 sw_ctrl_s1 = !(reg948 & BIT(9)); 452 } 453 454 if (hw_ctrl_s1 || sw_ctrl_s1) { 455 initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 456 457 /* Disable CCK block */ 458 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 459 val32 &= ~FPGA_RF_MODE_CCK; 460 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 461 462 val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; 463 val32 |= 0x30; 464 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 465 466 /* disable 3-wire */ 467 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 468 469 /* Setup PSD */ 470 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 471 472 /* Start PSD */ 473 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); 474 475 msleep(30); 476 477 do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; 478 479 /* turn off PSD */ 480 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 481 482 /* enable 3-wire */ 483 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); 484 485 /* Enable CCK block */ 486 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 487 val32 |= FPGA_RF_MODE_CCK; 488 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 489 490 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); 491 492 if (do_notch) { 493 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); 494 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); 495 rtl8xxxu_write32(priv, 0xd48, 0x0); 496 rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); 497 498 /* enable CSI mask */ 499 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 500 val32 |= BIT(28); 501 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 502 503 return; 504 } 505 } 506 } 507 508 /* disable CSI mask function */ 509 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 510 val32 &= ~BIT(28); 511 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 512 } 513 514 static void rtl8188fu_config_channel(struct ieee80211_hw *hw) 515 { 516 struct rtl8xxxu_priv *priv = hw->priv; 517 u32 val32; 518 u8 channel, subchannel; 519 bool sec_ch_above; 520 521 channel = (u8)hw->conf.chandef.chan->hw_value; 522 523 /* Set channel */ 524 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 525 val32 &= ~MODE_AG_CHANNEL_MASK; 526 val32 |= channel; 527 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 528 529 /* Spur calibration */ 530 rtl8188f_spur_calibration(priv, channel); 531 532 /* Set bandwidth mode */ 533 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 534 val32 &= ~FPGA_RF_MODE; 535 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 536 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 537 538 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 539 val32 &= ~FPGA_RF_MODE; 540 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 541 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 542 543 /* RXADC CLK */ 544 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 545 val32 |= GENMASK(10, 8); 546 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 547 548 /* TXDAC CLK */ 549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 550 val32 |= BIT(14) | BIT(12); 551 val32 &= ~BIT(13); 552 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 553 554 /* small BW */ 555 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 556 val32 &= ~GENMASK(31, 30); 557 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 558 559 /* adc buffer clk */ 560 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 561 val32 &= ~BIT(29); 562 val32 |= BIT(28); 563 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 564 565 /* adc buffer clk */ 566 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); 567 val32 &= ~BIT(29); 568 val32 |= BIT(28); 569 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); 570 571 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 572 val32 &= ~BIT(19); 573 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 574 575 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 576 val32 &= ~GENMASK(23, 20); 577 val32 |= BIT(21); 578 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 579 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 580 val32 |= BIT(20); 581 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 582 val32 |= BIT(22); 583 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 584 585 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) { 586 if (hw->conf.chandef.center_freq1 > 587 hw->conf.chandef.chan->center_freq) { 588 sec_ch_above = 1; 589 channel += 2; 590 } else { 591 sec_ch_above = 0; 592 channel -= 2; 593 } 594 595 /* Set Control channel to upper or lower. */ 596 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 597 val32 &= ~CCK0_SIDEBAND; 598 if (!sec_ch_above) 599 val32 |= CCK0_SIDEBAND; 600 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 601 602 val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); 603 val32 &= ~GENMASK(3, 0); 604 if (sec_ch_above) 605 subchannel = 2; 606 else 607 subchannel = 1; 608 val32 |= subchannel; 609 rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); 610 611 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 612 val32 &= ~RSR_RSC_BANDWIDTH_40M; 613 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 614 } 615 616 /* RF TRX_BW */ 617 val32 = channel; 618 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 619 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 620 val32 |= MODE_AG_BW_20MHZ_8723B; 621 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 622 val32 |= MODE_AG_BW_40MHZ_8723B; 623 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 624 625 /* FILTER BW&RC Corner (ACPR) */ 626 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 627 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 628 val32 = 0x00065; 629 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 630 val32 = 0x00025; 631 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); 632 633 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 634 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 635 val32 = 0x0; 636 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 637 val32 = 0x01000; 638 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); 639 640 /* RC Corner */ 641 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00140); 642 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); 643 } 644 645 static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) 646 { 647 u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = 6; 648 u32 agg_rx, val32; 649 650 /* TX aggregation */ 651 val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); 652 val32 &= ~(0xf << 4); 653 val32 |= usb_tx_agg_desc_num << 4; 654 rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); 655 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); 656 657 /* RX aggregation */ 658 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 659 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 660 661 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); 662 agg_rx &= ~RXDMA_USB_AGG_ENABLE; 663 agg_rx &= ~0xFF0F; /* reset agg size and timeout */ 664 665 rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 666 rxdma_mode &= ~BIT(1); 667 668 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 669 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); 670 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); 671 } 672 673 static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) 674 { 675 u32 val32; 676 677 /* Time duration for NHM unit: 4us, 0xc350=200ms */ 678 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); 679 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); 680 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); 681 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); 682 683 /* TH8 */ 684 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 685 val32 |= 0xff; 686 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 687 688 /* Enable CCK */ 689 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); 690 val32 &= ~(BIT(8) | BIT(9) | BIT(10)); 691 val32 |= BIT(8); 692 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); 693 694 /* Max power amongst all RX antennas */ 695 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); 696 val32 |= BIT(7); 697 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); 698 } 699 700 static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) 701 { 702 struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; 703 704 if (efuse->rtl_id != cpu_to_le16(0x8129)) 705 return -EINVAL; 706 707 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 708 709 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 710 sizeof(efuse->tx_power_index_A.cck_base)); 711 712 memcpy(priv->ht40_1s_tx_power_index_A, 713 efuse->tx_power_index_A.ht40_base, 714 sizeof(efuse->tx_power_index_A.ht40_base)); 715 716 priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; 717 priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 718 719 priv->default_crystal_cap = efuse->xtal_k & 0x3f; 720 721 return 0; 722 } 723 724 static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) 725 { 726 const char *fw_name; 727 int ret; 728 729 fw_name = "rtlwifi/rtl8188fufw.bin"; 730 731 ret = rtl8xxxu_load_firmware(priv, fw_name); 732 733 return ret; 734 } 735 736 static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) 737 { 738 u8 val8; 739 u16 val16; 740 741 /* Enable BB and RF */ 742 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 743 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 744 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 745 746 /* 747 * Per vendor driver, run power sequence before init of RF 748 */ 749 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 750 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 751 752 usleep_range(10, 20); 753 754 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); 755 756 val8 = SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_USBA | SYS_FUNC_USBD; 757 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 758 759 rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); 760 rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); 761 } 762 763 static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) 764 { 765 int ret; 766 767 if (priv->chip_cut == 1) 768 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); 769 else 770 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); 771 772 return ret; 773 } 774 775 void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 776 { 777 u32 val32; 778 u32 rf_amode, lstf; 779 int i; 780 781 /* Check continuous TX and Packet TX */ 782 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 783 784 if (lstf & OFDM_LSTF_MASK) { 785 /* Disable all continuous TX */ 786 val32 = lstf & ~OFDM_LSTF_MASK; 787 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 788 } else { 789 /* Deal with Packet TX case */ 790 /* block all queues */ 791 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 792 } 793 794 /* Read original RF mode Path A */ 795 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 796 797 /* Start LC calibration */ 798 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); 799 800 for (i = 0; i < 100; i++) { 801 if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) 802 break; 803 msleep(10); 804 } 805 806 if (i == 100) 807 dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); 808 809 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); 810 811 /* Restore original parameters */ 812 if (lstf & OFDM_LSTF_MASK) 813 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 814 else /* Deal with Packet TX case */ 815 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 816 } 817 818 static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) 819 { 820 u32 reg_eac, reg_e94, reg_e9c, val32; 821 int result = 0; 822 823 /* 824 * Leave IQK mode 825 */ 826 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 827 val32 &= 0x000000ff; 828 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 829 830 /* 831 * Enable path A PA in TX IQK mode 832 */ 833 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 834 val32 |= 0x80000; 835 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 836 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); 837 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 838 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); 839 840 /* PA,PAD gain adjust */ 841 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); 842 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); 843 844 /* enter IQK mode */ 845 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 846 val32 &= 0x000000ff; 847 val32 |= 0x80800000; 848 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 849 850 /* path-A IQK setting */ 851 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 852 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 853 854 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); 855 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 856 857 /* LO calibration setting */ 858 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 859 860 /* One shot, path A LOK & IQK */ 861 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 862 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 863 864 mdelay(25); 865 866 /* 867 * Leave IQK mode 868 */ 869 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 870 val32 &= 0x000000ff; 871 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 872 873 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); 874 875 /* save LOK result */ 876 *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); 877 878 /* Check failed */ 879 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 880 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 881 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 882 883 if (!(reg_eac & BIT(28)) && 884 ((reg_e94 & 0x03ff0000) != 0x01420000) && 885 ((reg_e9c & 0x03ff0000) != 0x00420000)) 886 result |= 0x01; 887 888 return result; 889 } 890 891 static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) 892 { 893 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; 894 int result = 0; 895 896 /* 897 * Leave IQK mode 898 */ 899 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 900 val32 &= 0x000000ff; 901 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 902 903 /* 904 * Enable path A PA in TX IQK mode 905 */ 906 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 907 val32 |= 0x80000; 908 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 909 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 910 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 911 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); 912 913 /* PA,PAD gain adjust */ 914 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); 915 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); 916 917 /* 918 * Enter IQK mode 919 */ 920 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 921 val32 &= 0x000000ff; 922 val32 |= 0x80800000; 923 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 924 925 /* 926 * Tx IQK setting 927 */ 928 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 929 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 930 931 /* path-A IQK setting */ 932 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); 933 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); 934 935 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); 936 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 937 938 /* LO calibration setting */ 939 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 940 941 /* One shot, path A LOK & IQK */ 942 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 943 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 944 945 mdelay(25); 946 947 /* 948 * Leave IQK mode 949 */ 950 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 951 val32 &= 0x000000ff; 952 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 953 954 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); 955 956 /* Check failed */ 957 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 958 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 959 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 960 961 if (!(reg_eac & BIT(28)) && 962 ((reg_e94 & 0x03ff0000) != 0x01420000) && 963 ((reg_e9c & 0x03ff0000) != 0x00420000)) 964 result |= 0x01; 965 else /* If TX not OK, ignore RX */ 966 goto out; 967 968 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | 969 ((reg_e9c & 0x3ff0000) >> 16); 970 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 971 972 /* 973 * Modify RX IQK mode table 974 */ 975 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 976 val32 &= 0x000000ff; 977 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 978 979 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 980 val32 |= 0x80000; 981 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 982 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 983 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 984 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); 985 986 /* 987 * PA, PAD setting 988 */ 989 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); 990 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x51000); 991 992 /* 993 * Enter IQK mode 994 */ 995 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 996 val32 &= 0x000000ff; 997 val32 |= 0x80800000; 998 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 999 1000 /* 1001 * RX IQK setting 1002 */ 1003 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1004 1005 /* path-A IQK setting */ 1006 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); 1007 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); 1008 1009 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); 1010 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); 1011 1012 /* LO calibration setting */ 1013 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 1014 1015 /* One shot, path A LOK & IQK */ 1016 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 1017 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 1018 1019 mdelay(25); 1020 1021 /* 1022 * Leave IQK mode 1023 */ 1024 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1025 val32 &= 0x000000ff; 1026 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1027 1028 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); 1029 1030 /* reload LOK value */ 1031 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); 1032 1033 /* Check failed */ 1034 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1035 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 1036 1037 if (!(reg_eac & BIT(27)) && 1038 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 1039 ((reg_eac & 0x03ff0000) != 0x00360000)) 1040 result |= 0x02; 1041 1042 out: 1043 return result; 1044 } 1045 1046 static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 1047 int result[][8], int t) 1048 { 1049 struct device *dev = &priv->udev->dev; 1050 u32 i, val32, rx_initial_gain, lok_result; 1051 u32 path_sel_bb, path_sel_rf; 1052 int path_a_ok; 1053 int retry = 2; 1054 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 1055 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 1056 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 1057 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 1058 REG_TX_OFDM_BBON, REG_TX_TO_RX, 1059 REG_TX_TO_TX, REG_RX_CCK, 1060 REG_RX_OFDM, REG_RX_WAIT_RIFS, 1061 REG_RX_TO_RX, REG_STANDBY, 1062 REG_SLEEP, REG_PMPD_ANAEN 1063 }; 1064 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 1065 REG_TXPAUSE, REG_BEACON_CTRL, 1066 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 1067 }; 1068 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 1069 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 1070 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 1071 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 1072 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 1073 }; 1074 1075 /* 1076 * Note: IQ calibration must be performed after loading 1077 * PHY_REG.txt , and radio_a, radio_b.txt 1078 */ 1079 1080 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1081 1082 if (t == 0) { 1083 /* Save ADDA parameters, turn Path A ADDA on */ 1084 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 1085 RTL8XXXU_ADDA_REGS); 1086 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1087 rtl8xxxu_save_regs(priv, iqk_bb_regs, 1088 priv->bb_backup, RTL8XXXU_BB_REGS); 1089 } 1090 1091 rtl8xxxu_path_adda_on(priv, adda_regs, true); 1092 1093 if (t == 0) { 1094 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 1095 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); 1096 } 1097 1098 /* save RF path */ 1099 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1100 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1101 1102 /* BB setting */ 1103 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 1104 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 1105 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); 1106 1107 /* MAC settings */ 1108 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); 1109 val32 |= 0x00ff0000; 1110 rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); 1111 1112 /* IQ calibration setting */ 1113 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1114 val32 &= 0xff; 1115 val32 |= 0x80800000; 1116 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1117 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 1118 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1119 1120 for (i = 0; i < retry; i++) { 1121 path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); 1122 if (path_a_ok == 0x01) { 1123 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1124 val32 &= 0xff; 1125 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1126 1127 val32 = rtl8xxxu_read32(priv, 1128 REG_TX_POWER_BEFORE_IQK_A); 1129 result[t][0] = (val32 >> 16) & 0x3ff; 1130 1131 val32 = rtl8xxxu_read32(priv, 1132 REG_TX_POWER_AFTER_IQK_A); 1133 result[t][1] = (val32 >> 16) & 0x3ff; 1134 break; 1135 } 1136 } 1137 1138 for (i = 0; i < retry; i++) { 1139 path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); 1140 if (path_a_ok == 0x03) { 1141 val32 = rtl8xxxu_read32(priv, 1142 REG_RX_POWER_BEFORE_IQK_A_2); 1143 result[t][2] = (val32 >> 16) & 0x3ff; 1144 1145 val32 = rtl8xxxu_read32(priv, 1146 REG_RX_POWER_AFTER_IQK_A_2); 1147 result[t][3] = (val32 >> 16) & 0x3ff; 1148 break; 1149 } 1150 } 1151 1152 if (!path_a_ok) 1153 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 1154 1155 /* Back to BB mode, load original value */ 1156 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1157 val32 &= 0xff; 1158 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1159 1160 if (t == 0) 1161 return; 1162 1163 if (!priv->pi_enabled) { 1164 /* 1165 * Switch back BB to SI mode after finishing 1166 * IQ Calibration 1167 */ 1168 val32 = 0x01000000; 1169 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 1170 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 1171 } 1172 1173 /* Reload ADDA power saving parameters */ 1174 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1175 RTL8XXXU_ADDA_REGS); 1176 1177 /* Reload MAC parameters */ 1178 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1179 1180 /* Reload BB parameters */ 1181 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 1182 priv->bb_backup, RTL8XXXU_BB_REGS); 1183 1184 /* Reload RF path */ 1185 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1186 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1187 1188 /* Restore RX initial gain */ 1189 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1190 val32 &= 0xffffff00; 1191 val32 |= 0x50; 1192 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1193 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1194 val32 &= 0xffffff00; 1195 val32 |= rx_initial_gain & 0xff; 1196 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1197 1198 /* Load 0xe30 IQC default value */ 1199 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 1200 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 1201 } 1202 1203 static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1204 { 1205 struct device *dev = &priv->udev->dev; 1206 int result[4][8]; /* last is final result */ 1207 int i, candidate; 1208 bool path_a_ok; 1209 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1210 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1211 s32 reg_tmp = 0; 1212 bool simu; 1213 u32 path_sel_bb, path_sel_rf; 1214 1215 /* Save RF path */ 1216 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1217 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1218 1219 memset(result, 0, sizeof(result)); 1220 candidate = -1; 1221 1222 path_a_ok = false; 1223 1224 for (i = 0; i < 3; i++) { 1225 rtl8188fu_phy_iqcalibrate(priv, result, i); 1226 1227 if (i == 1) { 1228 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); 1229 if (simu) { 1230 candidate = 0; 1231 break; 1232 } 1233 } 1234 1235 if (i == 2) { 1236 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); 1237 if (simu) { 1238 candidate = 0; 1239 break; 1240 } 1241 1242 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); 1243 if (simu) { 1244 candidate = 1; 1245 } else { 1246 for (i = 0; i < 8; i++) 1247 reg_tmp += result[3][i]; 1248 1249 if (reg_tmp) 1250 candidate = 3; 1251 else 1252 candidate = -1; 1253 } 1254 } 1255 } 1256 1257 for (i = 0; i < 4; i++) { 1258 reg_e94 = result[i][0]; 1259 reg_e9c = result[i][1]; 1260 reg_ea4 = result[i][2]; 1261 reg_eac = result[i][3]; 1262 reg_eb4 = result[i][4]; 1263 reg_ebc = result[i][5]; 1264 reg_ec4 = result[i][6]; 1265 reg_ecc = result[i][7]; 1266 } 1267 1268 if (candidate >= 0) { 1269 reg_e94 = result[candidate][0]; 1270 priv->rege94 = reg_e94; 1271 reg_e9c = result[candidate][1]; 1272 priv->rege9c = reg_e9c; 1273 reg_ea4 = result[candidate][2]; 1274 reg_eac = result[candidate][3]; 1275 reg_eb4 = result[candidate][4]; 1276 priv->regeb4 = reg_eb4; 1277 reg_ebc = result[candidate][5]; 1278 priv->regebc = reg_ebc; 1279 reg_ec4 = result[candidate][6]; 1280 reg_ecc = result[candidate][7]; 1281 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1282 dev_dbg(dev, 1283 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 1284 __func__, reg_e94, reg_e9c, 1285 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1286 path_a_ok = true; 1287 } else { 1288 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 1289 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 1290 } 1291 1292 if (reg_e94 && candidate >= 0) 1293 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1294 candidate, (reg_ea4 == 0)); 1295 1296 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1297 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1298 1299 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1300 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1301 } 1302 1303 static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) 1304 { 1305 u16 val8; 1306 1307 /* 0x04[12:11] = 2b'01enable WL suspend */ 1308 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1309 val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1310 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1311 1312 /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1313 val8 = rtl8xxxu_read8(priv, 0xc4); 1314 val8 &= ~BIT(4); 1315 rtl8xxxu_write8(priv, 0xc4, val8); 1316 } 1317 1318 static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) 1319 { 1320 u8 val8; 1321 u32 val32; 1322 int count, ret = 0; 1323 1324 /* Disable SW LPS */ 1325 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1326 val8 &= ~(APS_FSMCO_SW_LPS >> 8); 1327 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1328 1329 /* wait till 0x04[17] = 1 power ready */ 1330 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1331 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1332 if (val32 & BIT(17)) 1333 break; 1334 1335 udelay(10); 1336 } 1337 1338 if (!count) { 1339 ret = -EBUSY; 1340 goto exit; 1341 } 1342 1343 /* Disable HWPDN */ 1344 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1345 val8 &= ~(APS_FSMCO_HW_POWERDOWN >> 8); 1346 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1347 1348 /* Disable WL suspend */ 1349 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1350 val8 &= ~(APS_FSMCO_HW_SUSPEND >> 8); 1351 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1352 1353 /* set, then poll until 0 */ 1354 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1355 val8 |= APS_FSMCO_MAC_ENABLE >> 8; 1356 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1357 1358 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1359 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1360 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1361 ret = 0; 1362 break; 1363 } 1364 udelay(10); 1365 } 1366 1367 if (!count) { 1368 ret = -EBUSY; 1369 goto exit; 1370 } 1371 1372 /* 0x27<=35 to reduce RF noise */ 1373 val8 = rtl8xxxu_write8(priv, 0x27, 0x35); 1374 exit: 1375 return ret; 1376 } 1377 1378 static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) 1379 { 1380 u8 val8; 1381 u32 val32; 1382 int count, ret = 0; 1383 1384 /* Turn off RF */ 1385 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 1386 1387 /* 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ 1388 val8 = rtl8xxxu_read8(priv, 0x4e); 1389 val8 &= ~BIT(7); 1390 rtl8xxxu_write8(priv, 0x4e, val8); 1391 1392 /* 0x27 <= 34, xtal_qsel = 0 to xtal bring up */ 1393 rtl8xxxu_write8(priv, 0x27, 0x34); 1394 1395 /* 0x04[9] = 1 turn off MAC by HW state machine */ 1396 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1397 val8 |= APS_FSMCO_MAC_OFF >> 8; 1398 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1399 1400 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1401 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1402 if ((val32 & APS_FSMCO_MAC_OFF) == 0) { 1403 ret = 0; 1404 break; 1405 } 1406 udelay(10); 1407 } 1408 1409 if (!count) { 1410 ret = -EBUSY; 1411 goto exit; 1412 } 1413 1414 exit: 1415 return ret; 1416 } 1417 1418 static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) 1419 { 1420 u8 val8; 1421 1422 /* 0x04[12:11] = 2b'01 enable WL suspend */ 1423 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1424 val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1425 val8 |= APS_FSMCO_HW_SUSPEND >> 8; 1426 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1427 1428 /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1429 val8 = rtl8xxxu_read8(priv, 0xc4); 1430 val8 |= BIT(4); 1431 rtl8xxxu_write8(priv, 0xc4, val8); 1432 1433 return 0; 1434 } 1435 1436 static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) 1437 { 1438 struct device *dev = &priv->udev->dev; 1439 u8 val8; 1440 u16 val16; 1441 u32 val32; 1442 int retry, retval; 1443 1444 /* set RPWM IMR */ 1445 val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); 1446 val8 |= IMR0_CPWM >> 8; 1447 rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); 1448 1449 /* Tx Pause */ 1450 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 1451 1452 retry = 100; 1453 retval = -EBUSY; 1454 1455 /* 1456 * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. 1457 */ 1458 do { 1459 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); 1460 if (!val32) { 1461 retval = 0; 1462 break; 1463 } 1464 } while (retry--); 1465 1466 if (!retry) { 1467 dev_warn(dev, "Failed to flush TX queue\n"); 1468 retval = -EBUSY; 1469 goto out; 1470 } 1471 1472 /* Disable CCK and OFDM, clock gated */ 1473 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1474 val8 &= ~SYS_FUNC_BBRSTB; 1475 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1476 1477 udelay(2); 1478 1479 /* Whole BB is reset */ 1480 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1481 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 1482 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1483 1484 /* Reset MAC TRX */ 1485 val16 = rtl8xxxu_read16(priv, REG_CR); 1486 val16 |= 0x3f; 1487 val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); 1488 rtl8xxxu_write16(priv, REG_CR, val16); 1489 1490 /* Respond TxOK to scheduler */ 1491 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 1492 val8 |= DUAL_TSF_TX_OK; 1493 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 1494 1495 out: 1496 return retval; 1497 } 1498 1499 static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) 1500 { 1501 u16 val16; 1502 int ret; 1503 1504 rtl8188f_disabled_to_emu(priv); 1505 1506 ret = rtl8188f_emu_to_active(priv); 1507 if (ret) 1508 goto exit; 1509 1510 rtl8xxxu_write8(priv, REG_CR, 0); 1511 1512 val16 = rtl8xxxu_read16(priv, REG_CR); 1513 1514 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1515 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1516 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1517 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1518 rtl8xxxu_write16(priv, REG_CR, val16); 1519 1520 exit: 1521 return ret; 1522 } 1523 1524 static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) 1525 { 1526 u8 val8; 1527 u16 val16; 1528 1529 rtl8xxxu_flush_fifo(priv); 1530 1531 val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); 1532 val16 &= ~BIT(12); 1533 rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); 1534 1535 rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); 1536 rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); 1537 1538 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ 1539 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1540 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1541 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1542 1543 /* Turn off RF */ 1544 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 1545 1546 /* Reset Firmware if running in RAM */ 1547 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1548 rtl8xxxu_firmware_self_reset(priv); 1549 1550 rtl8188fu_active_to_lps(priv); 1551 1552 /* Reset MCU */ 1553 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1554 val16 &= ~SYS_FUNC_CPU_ENABLE; 1555 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1556 1557 /* Reset MCU ready status */ 1558 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1559 1560 rtl8188fu_active_to_emu(priv); 1561 rtl8188fu_emu_to_disabled(priv); 1562 } 1563 1564 #define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee 1565 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f 1566 1567 static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) 1568 { 1569 u32 val32; 1570 u8 pg_pwrtrim = 0xff, val8; 1571 s8 bb_gain; 1572 1573 /* Somehow this is not found in the efuse we read earlier. */ 1574 rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); 1575 1576 if (pg_pwrtrim != 0xff) { 1577 bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK; 1578 1579 if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK) 1580 bb_gain = 0; 1581 else if (bb_gain & 1) 1582 bb_gain = bb_gain >> 1; 1583 else 1584 bb_gain = -(bb_gain >> 1); 1585 1586 val8 = abs(bb_gain); 1587 if (bb_gain > 0) 1588 val8 |= BIT(5); 1589 1590 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); 1591 val32 &= ~0xfc000; 1592 val32 |= val8 << 14; 1593 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); 1594 } 1595 1596 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); 1597 1598 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1599 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 1600 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; 1601 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1602 1603 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1604 } 1605 1606 static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) 1607 { 1608 u32 val32; 1609 1610 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1611 val32 &= ~OFDM_RF_PATH_TX_MASK; 1612 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1613 1614 /* Power down RF module */ 1615 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1616 } 1617 1618 static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) 1619 { 1620 u16 val16; 1621 u32 val32; 1622 1623 val16 = rtl8xxxu_read16(priv, REG_CR); 1624 val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); 1625 rtl8xxxu_write16(priv, REG_CR, val16); 1626 1627 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 1628 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 1629 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 1630 } 1631 1632 #define XTAL1 GENMASK(22, 17) 1633 #define XTAL0 GENMASK(16, 11) 1634 1635 void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) 1636 { 1637 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 1638 u32 val32; 1639 1640 if (crystal_cap == cfo->crystal_cap) 1641 return; 1642 1643 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 1644 1645 dev_dbg(&priv->udev->dev, 1646 "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", 1647 __func__, 1648 cfo->crystal_cap, 1649 FIELD_GET(XTAL1, val32), 1650 FIELD_GET(XTAL0, val32), 1651 crystal_cap); 1652 1653 val32 &= ~(XTAL1 | XTAL0); 1654 val32 |= FIELD_PREP(XTAL1, crystal_cap) | 1655 FIELD_PREP(XTAL0, crystal_cap); 1656 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 1657 1658 cfo->crystal_cap = crystal_cap; 1659 } 1660 1661 static s8 rtl8188f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) 1662 { 1663 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 1664 s8 rx_pwr_all = 0x00; 1665 u8 vga_idx, lna_idx; 1666 1667 lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); 1668 vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); 1669 1670 switch (lna_idx) { 1671 case 7: 1672 if (vga_idx <= 27) 1673 rx_pwr_all = -100 + 2 * (27 - vga_idx); 1674 else 1675 rx_pwr_all = -100; 1676 break; 1677 case 5: 1678 rx_pwr_all = -74 + 2 * (21 - vga_idx); 1679 break; 1680 case 3: 1681 rx_pwr_all = -60 + 2 * (20 - vga_idx); 1682 break; 1683 case 1: 1684 rx_pwr_all = -44 + 2 * (19 - vga_idx); 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 return rx_pwr_all; 1691 } 1692 1693 struct rtl8xxxu_fileops rtl8188fu_fops = { 1694 .identify_chip = rtl8188fu_identify_chip, 1695 .parse_efuse = rtl8188fu_parse_efuse, 1696 .load_firmware = rtl8188fu_load_firmware, 1697 .power_on = rtl8188fu_power_on, 1698 .power_off = rtl8188fu_power_off, 1699 .read_efuse = rtl8xxxu_read_efuse, 1700 .reset_8051 = rtl8xxxu_reset_8051, 1701 .llt_init = rtl8xxxu_auto_llt_table, 1702 .init_phy_bb = rtl8188fu_init_phy_bb, 1703 .init_phy_rf = rtl8188fu_init_phy_rf, 1704 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, 1705 .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, 1706 .phy_iq_calibrate = rtl8188fu_phy_iq_calibrate, 1707 .config_channel = rtl8188fu_config_channel, 1708 .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 1709 .parse_phystats = rtl8723au_rx_parse_phystats, 1710 .init_aggregation = rtl8188fu_init_aggregation, 1711 .init_statistics = rtl8188fu_init_statistics, 1712 .init_burst = rtl8xxxu_init_burst, 1713 .enable_rf = rtl8188f_enable_rf, 1714 .disable_rf = rtl8188f_disable_rf, 1715 .usb_quirks = rtl8188f_usb_quirks, 1716 .set_tx_power = rtl8188f_set_tx_power, 1717 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 1718 .report_connect = rtl8xxxu_gen2_report_connect, 1719 .report_rssi = rtl8xxxu_gen2_report_rssi, 1720 .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 1721 .set_crystal_cap = rtl8188f_set_crystal_cap, 1722 .cck_rssi = rtl8188f_cck_rssi, 1723 .writeN_block_size = 128, 1724 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 1725 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 1726 .has_s0s1 = 1, 1727 .has_tx_report = 1, 1728 .gen2_thermal_meter = 1, 1729 .needs_full_init = 1, 1730 .init_reg_rxfltmap = 1, 1731 .init_reg_pkt_life_time = 1, 1732 .init_reg_hmtfr = 1, 1733 .ampdu_max_time = 0x70, 1734 .ustime_tsf_edca = 0x28, 1735 .max_aggr_num = 0x0c14, 1736 .supports_ap = 1, 1737 .max_macid_num = 16, 1738 .max_sec_cam_num = 16, 1739 .supports_concurrent = 1, 1740 .adda_1t_init = 0x03c00014, 1741 .adda_1t_path_on = 0x03c00014, 1742 .trxff_boundary = 0x3f7f, 1743 .pbp_rx = PBP_PAGE_SIZE_256, 1744 .pbp_tx = PBP_PAGE_SIZE_256, 1745 .mactable = rtl8188f_mac_init_table, 1746 .total_page_num = TX_TOTAL_PAGE_NUM_8188F, 1747 .page_num_hi = TX_PAGE_NUM_HI_PQ_8188F, 1748 .page_num_lo = TX_PAGE_NUM_LO_PQ_8188F, 1749 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F, 1750 }; 1751