1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 7 8 Based on the original rt2800pci.c and rt2800usb.c. 9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 15 <http://rt2x00.serialmonkey.com> 16 17 */ 18 19 /* 20 Module: rt2800lib 21 Abstract: rt2800 generic device routines. 22 */ 23 24 #include <linux/crc-ccitt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "rt2x00.h" 30 #include "rt2800lib.h" 31 #include "rt2800.h" 32 33 static bool modparam_watchdog; 34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO); 35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected"); 36 37 /* 38 * Register access. 39 * All access to the CSR registers will go through the methods 40 * rt2800_register_read and rt2800_register_write. 41 * BBP and RF register require indirect register access, 42 * and use the CSR registers BBPCSR and RFCSR to achieve this. 43 * These indirect registers work with busy bits, 44 * and we will try maximal REGISTER_BUSY_COUNT times to access 45 * the register while taking a REGISTER_BUSY_DELAY us delay 46 * between each attampt. When the busy bit is still set at that time, 47 * the access attempt is considered to have failed, 48 * and we will print an error. 49 * The _lock versions must be used if you already hold the csr_mutex 50 */ 51 #define WAIT_FOR_BBP(__dev, __reg) \ 52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 53 #define WAIT_FOR_RFCSR(__dev, __reg) \ 54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 56 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 57 (__reg)) 58 #define WAIT_FOR_RF(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 60 #define WAIT_FOR_MCU(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 62 H2M_MAILBOX_CSR_OWNER, (__reg)) 63 64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 65 { 66 /* check for rt2872 on SoC */ 67 if (!rt2x00_is_soc(rt2x00dev) || 68 !rt2x00_rt(rt2x00dev, RT2872)) 69 return false; 70 71 /* we know for sure that these rf chipsets are used on rt305x boards */ 72 if (rt2x00_rf(rt2x00dev, RF3020) || 73 rt2x00_rf(rt2x00dev, RF3021) || 74 rt2x00_rf(rt2x00dev, RF3022)) 75 return true; 76 77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 78 return false; 79 } 80 81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 82 const unsigned int word, const u8 value) 83 { 84 u32 reg; 85 86 mutex_lock(&rt2x00dev->csr_mutex); 87 88 /* 89 * Wait until the BBP becomes available, afterwards we 90 * can safely write the new data into the register. 91 */ 92 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 93 reg = 0; 94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 99 100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 101 } 102 103 mutex_unlock(&rt2x00dev->csr_mutex); 104 } 105 106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 107 { 108 u32 reg; 109 u8 value; 110 111 mutex_lock(&rt2x00dev->csr_mutex); 112 113 /* 114 * Wait until the BBP becomes available, afterwards we 115 * can safely write the read request into the register. 116 * After the data has been written, we wait until hardware 117 * returns the correct value, if at any time the register 118 * doesn't become available in time, reg will be 0xffffffff 119 * which means we return 0xff to the caller. 120 */ 121 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 122 reg = 0; 123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 127 128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 129 130 WAIT_FOR_BBP(rt2x00dev, ®); 131 } 132 133 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 134 135 mutex_unlock(&rt2x00dev->csr_mutex); 136 137 return value; 138 } 139 140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 141 const unsigned int word, const u8 value) 142 { 143 u32 reg; 144 145 mutex_lock(&rt2x00dev->csr_mutex); 146 147 /* 148 * Wait until the RFCSR becomes available, afterwards we 149 * can safely write the new data into the register. 150 */ 151 switch (rt2x00dev->chip.rt) { 152 case RT6352: 153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 157 word); 158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 160 161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 162 } 163 break; 164 165 default: 166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 167 reg = 0; 168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 172 173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 174 } 175 break; 176 } 177 178 mutex_unlock(&rt2x00dev->csr_mutex); 179 } 180 181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 182 const unsigned int reg, const u8 value) 183 { 184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 185 } 186 187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 188 const unsigned int reg, const u8 value) 189 { 190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 192 } 193 194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 199 } 200 201 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 202 const u8 reg, const u8 value) 203 { 204 rt2800_bbp_write(rt2x00dev, 158, reg); 205 rt2800_bbp_write(rt2x00dev, 159, value); 206 } 207 208 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 209 { 210 rt2800_bbp_write(rt2x00dev, 158, reg); 211 return rt2800_bbp_read(rt2x00dev, 159); 212 } 213 214 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 215 const u8 reg, const u8 value) 216 { 217 rt2800_bbp_write(rt2x00dev, 195, reg); 218 rt2800_bbp_write(rt2x00dev, 196, value); 219 } 220 221 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 222 const unsigned int word) 223 { 224 u32 reg; 225 u8 value; 226 227 mutex_lock(&rt2x00dev->csr_mutex); 228 229 /* 230 * Wait until the RFCSR becomes available, afterwards we 231 * can safely write the read request into the register. 232 * After the data has been written, we wait until hardware 233 * returns the correct value, if at any time the register 234 * doesn't become available in time, reg will be 0xffffffff 235 * which means we return 0xff to the caller. 236 */ 237 switch (rt2x00dev->chip.rt) { 238 case RT6352: 239 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 240 reg = 0; 241 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 242 word); 243 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 244 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 245 246 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 247 248 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 249 } 250 251 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 252 break; 253 254 default: 255 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 256 reg = 0; 257 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 258 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 259 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 260 261 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 262 263 WAIT_FOR_RFCSR(rt2x00dev, ®); 264 } 265 266 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 267 break; 268 } 269 270 mutex_unlock(&rt2x00dev->csr_mutex); 271 272 return value; 273 } 274 275 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 276 const unsigned int reg) 277 { 278 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 279 } 280 281 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 282 const unsigned int word, const u32 value) 283 { 284 u32 reg; 285 286 mutex_lock(&rt2x00dev->csr_mutex); 287 288 /* 289 * Wait until the RF becomes available, afterwards we 290 * can safely write the new data into the register. 291 */ 292 if (WAIT_FOR_RF(rt2x00dev, ®)) { 293 reg = 0; 294 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 295 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 296 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 297 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 298 299 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 300 rt2x00_rf_write(rt2x00dev, word, value); 301 } 302 303 mutex_unlock(&rt2x00dev->csr_mutex); 304 } 305 306 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 307 [EEPROM_CHIP_ID] = 0x0000, 308 [EEPROM_VERSION] = 0x0001, 309 [EEPROM_MAC_ADDR_0] = 0x0002, 310 [EEPROM_MAC_ADDR_1] = 0x0003, 311 [EEPROM_MAC_ADDR_2] = 0x0004, 312 [EEPROM_NIC_CONF0] = 0x001a, 313 [EEPROM_NIC_CONF1] = 0x001b, 314 [EEPROM_FREQ] = 0x001d, 315 [EEPROM_LED_AG_CONF] = 0x001e, 316 [EEPROM_LED_ACT_CONF] = 0x001f, 317 [EEPROM_LED_POLARITY] = 0x0020, 318 [EEPROM_NIC_CONF2] = 0x0021, 319 [EEPROM_LNA] = 0x0022, 320 [EEPROM_RSSI_BG] = 0x0023, 321 [EEPROM_RSSI_BG2] = 0x0024, 322 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 323 [EEPROM_RSSI_A] = 0x0025, 324 [EEPROM_RSSI_A2] = 0x0026, 325 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 326 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 327 [EEPROM_TXPOWER_DELTA] = 0x0028, 328 [EEPROM_TXPOWER_BG1] = 0x0029, 329 [EEPROM_TXPOWER_BG2] = 0x0030, 330 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 331 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 332 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 333 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 334 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 335 [EEPROM_TXPOWER_A1] = 0x003c, 336 [EEPROM_TXPOWER_A2] = 0x0053, 337 [EEPROM_TXPOWER_INIT] = 0x0068, 338 [EEPROM_TSSI_BOUND_A1] = 0x006a, 339 [EEPROM_TSSI_BOUND_A2] = 0x006b, 340 [EEPROM_TSSI_BOUND_A3] = 0x006c, 341 [EEPROM_TSSI_BOUND_A4] = 0x006d, 342 [EEPROM_TSSI_BOUND_A5] = 0x006e, 343 [EEPROM_TXPOWER_BYRATE] = 0x006f, 344 [EEPROM_BBP_START] = 0x0078, 345 }; 346 347 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 348 [EEPROM_CHIP_ID] = 0x0000, 349 [EEPROM_VERSION] = 0x0001, 350 [EEPROM_MAC_ADDR_0] = 0x0002, 351 [EEPROM_MAC_ADDR_1] = 0x0003, 352 [EEPROM_MAC_ADDR_2] = 0x0004, 353 [EEPROM_NIC_CONF0] = 0x001a, 354 [EEPROM_NIC_CONF1] = 0x001b, 355 [EEPROM_NIC_CONF2] = 0x001c, 356 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 357 [EEPROM_FREQ] = 0x0022, 358 [EEPROM_LED_AG_CONF] = 0x0023, 359 [EEPROM_LED_ACT_CONF] = 0x0024, 360 [EEPROM_LED_POLARITY] = 0x0025, 361 [EEPROM_LNA] = 0x0026, 362 [EEPROM_EXT_LNA2] = 0x0027, 363 [EEPROM_RSSI_BG] = 0x0028, 364 [EEPROM_RSSI_BG2] = 0x0029, 365 [EEPROM_RSSI_A] = 0x002a, 366 [EEPROM_RSSI_A2] = 0x002b, 367 [EEPROM_TXPOWER_BG1] = 0x0030, 368 [EEPROM_TXPOWER_BG2] = 0x0037, 369 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 370 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 371 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 372 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 373 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 374 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 375 [EEPROM_TXPOWER_A1] = 0x004b, 376 [EEPROM_TXPOWER_A2] = 0x0065, 377 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 378 [EEPROM_TSSI_BOUND_A1] = 0x009a, 379 [EEPROM_TSSI_BOUND_A2] = 0x009b, 380 [EEPROM_TSSI_BOUND_A3] = 0x009c, 381 [EEPROM_TSSI_BOUND_A4] = 0x009d, 382 [EEPROM_TSSI_BOUND_A5] = 0x009e, 383 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 384 }; 385 386 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 387 const enum rt2800_eeprom_word word) 388 { 389 const unsigned int *map; 390 unsigned int index; 391 392 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 393 "%s: invalid EEPROM word %d\n", 394 wiphy_name(rt2x00dev->hw->wiphy), word)) 395 return 0; 396 397 if (rt2x00_rt(rt2x00dev, RT3593) || 398 rt2x00_rt(rt2x00dev, RT3883)) 399 map = rt2800_eeprom_map_ext; 400 else 401 map = rt2800_eeprom_map; 402 403 index = map[word]; 404 405 /* Index 0 is valid only for EEPROM_CHIP_ID. 406 * Otherwise it means that the offset of the 407 * given word is not initialized in the map, 408 * or that the field is not usable on the 409 * actual chipset. 410 */ 411 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 412 "%s: invalid access of EEPROM word %d\n", 413 wiphy_name(rt2x00dev->hw->wiphy), word); 414 415 return index; 416 } 417 418 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 419 const enum rt2800_eeprom_word word) 420 { 421 unsigned int index; 422 423 index = rt2800_eeprom_word_index(rt2x00dev, word); 424 return rt2x00_eeprom_addr(rt2x00dev, index); 425 } 426 427 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 428 const enum rt2800_eeprom_word word) 429 { 430 unsigned int index; 431 432 index = rt2800_eeprom_word_index(rt2x00dev, word); 433 return rt2x00_eeprom_read(rt2x00dev, index); 434 } 435 436 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 437 const enum rt2800_eeprom_word word, u16 data) 438 { 439 unsigned int index; 440 441 index = rt2800_eeprom_word_index(rt2x00dev, word); 442 rt2x00_eeprom_write(rt2x00dev, index, data); 443 } 444 445 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 446 const enum rt2800_eeprom_word array, 447 unsigned int offset) 448 { 449 unsigned int index; 450 451 index = rt2800_eeprom_word_index(rt2x00dev, array); 452 return rt2x00_eeprom_read(rt2x00dev, index + offset); 453 } 454 455 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 456 { 457 u32 reg; 458 int i, count; 459 460 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 461 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 462 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 463 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 464 rt2x00_set_field32(®, WLAN_EN, 1); 465 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 466 467 udelay(REGISTER_BUSY_DELAY); 468 469 count = 0; 470 do { 471 /* 472 * Check PLL_LD & XTAL_RDY. 473 */ 474 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 475 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 476 if (rt2x00_get_field32(reg, PLL_LD) && 477 rt2x00_get_field32(reg, XTAL_RDY)) 478 break; 479 udelay(REGISTER_BUSY_DELAY); 480 } 481 482 if (i >= REGISTER_BUSY_COUNT) { 483 484 if (count >= 10) 485 return -EIO; 486 487 rt2800_register_write(rt2x00dev, 0x58, 0x018); 488 udelay(REGISTER_BUSY_DELAY); 489 rt2800_register_write(rt2x00dev, 0x58, 0x418); 490 udelay(REGISTER_BUSY_DELAY); 491 rt2800_register_write(rt2x00dev, 0x58, 0x618); 492 udelay(REGISTER_BUSY_DELAY); 493 count++; 494 } else { 495 count = 0; 496 } 497 498 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 499 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 500 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 501 rt2x00_set_field32(®, WLAN_RESET, 1); 502 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 503 udelay(10); 504 rt2x00_set_field32(®, WLAN_RESET, 0); 505 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 506 udelay(10); 507 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 508 } while (count != 0); 509 510 return 0; 511 } 512 513 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 514 const u8 command, const u8 token, 515 const u8 arg0, const u8 arg1) 516 { 517 u32 reg; 518 519 /* 520 * SOC devices don't support MCU requests. 521 */ 522 if (rt2x00_is_soc(rt2x00dev)) 523 return; 524 525 mutex_lock(&rt2x00dev->csr_mutex); 526 527 /* 528 * Wait until the MCU becomes available, afterwards we 529 * can safely write the new data into the register. 530 */ 531 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 532 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 533 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 534 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 535 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 536 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 537 538 reg = 0; 539 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 540 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 541 } 542 543 mutex_unlock(&rt2x00dev->csr_mutex); 544 } 545 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 546 547 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 548 { 549 unsigned int i = 0; 550 u32 reg; 551 552 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 553 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 554 if (reg && reg != ~0) 555 return 0; 556 msleep(1); 557 } 558 559 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 560 return -EBUSY; 561 } 562 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 563 564 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 565 { 566 unsigned int i; 567 u32 reg; 568 569 /* 570 * Some devices are really slow to respond here. Wait a whole second 571 * before timing out. 572 */ 573 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 574 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 575 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 576 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 577 return 0; 578 579 msleep(10); 580 } 581 582 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 583 return -EACCES; 584 } 585 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 586 587 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 588 { 589 u32 reg; 590 591 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 592 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 593 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 594 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 595 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 596 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 597 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 598 } 599 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 600 601 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 602 unsigned short *txwi_size, 603 unsigned short *rxwi_size) 604 { 605 switch (rt2x00dev->chip.rt) { 606 case RT3593: 607 case RT3883: 608 *txwi_size = TXWI_DESC_SIZE_4WORDS; 609 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 610 break; 611 612 case RT5592: 613 case RT6352: 614 *txwi_size = TXWI_DESC_SIZE_5WORDS; 615 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 616 break; 617 618 default: 619 *txwi_size = TXWI_DESC_SIZE_4WORDS; 620 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 621 break; 622 } 623 } 624 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 625 626 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 627 { 628 u16 fw_crc; 629 u16 crc; 630 631 /* 632 * The last 2 bytes in the firmware array are the crc checksum itself, 633 * this means that we should never pass those 2 bytes to the crc 634 * algorithm. 635 */ 636 fw_crc = (data[len - 2] << 8 | data[len - 1]); 637 638 /* 639 * Use the crc ccitt algorithm. 640 * This will return the same value as the legacy driver which 641 * used bit ordering reversion on the both the firmware bytes 642 * before input input as well as on the final output. 643 * Obviously using crc ccitt directly is much more efficient. 644 */ 645 crc = crc_ccitt(~0, data, len - 2); 646 647 /* 648 * There is a small difference between the crc-itu-t + bitrev and 649 * the crc-ccitt crc calculation. In the latter method the 2 bytes 650 * will be swapped, use swab16 to convert the crc to the correct 651 * value. 652 */ 653 crc = swab16(crc); 654 655 return fw_crc == crc; 656 } 657 658 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 659 const u8 *data, const size_t len) 660 { 661 size_t offset = 0; 662 size_t fw_len; 663 bool multiple; 664 665 /* 666 * PCI(e) & SOC devices require firmware with a length 667 * of 8kb. USB devices require firmware files with a length 668 * of 4kb. Certain USB chipsets however require different firmware, 669 * which Ralink only provides attached to the original firmware 670 * file. Thus for USB devices, firmware files have a length 671 * which is a multiple of 4kb. The firmware for rt3290 chip also 672 * have a length which is a multiple of 4kb. 673 */ 674 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 675 fw_len = 4096; 676 else 677 fw_len = 8192; 678 679 multiple = true; 680 /* 681 * Validate the firmware length 682 */ 683 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 684 return FW_BAD_LENGTH; 685 686 /* 687 * Check if the chipset requires one of the upper parts 688 * of the firmware. 689 */ 690 if (rt2x00_is_usb(rt2x00dev) && 691 !rt2x00_rt(rt2x00dev, RT2860) && 692 !rt2x00_rt(rt2x00dev, RT2872) && 693 !rt2x00_rt(rt2x00dev, RT3070) && 694 ((len / fw_len) == 1)) 695 return FW_BAD_VERSION; 696 697 /* 698 * 8kb firmware files must be checked as if it were 699 * 2 separate firmware files. 700 */ 701 while (offset < len) { 702 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 703 return FW_BAD_CRC; 704 705 offset += fw_len; 706 } 707 708 return FW_OK; 709 } 710 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 711 712 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 713 const u8 *data, const size_t len) 714 { 715 unsigned int i; 716 u32 reg; 717 int retval; 718 719 if (rt2x00_rt(rt2x00dev, RT3290)) { 720 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 721 if (retval) 722 return -EBUSY; 723 } 724 725 /* 726 * If driver doesn't wake up firmware here, 727 * rt2800_load_firmware will hang forever when interface is up again. 728 */ 729 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 730 731 /* 732 * Wait for stable hardware. 733 */ 734 if (rt2800_wait_csr_ready(rt2x00dev)) 735 return -EBUSY; 736 737 if (rt2x00_is_pci(rt2x00dev)) { 738 if (rt2x00_rt(rt2x00dev, RT3290) || 739 rt2x00_rt(rt2x00dev, RT3572) || 740 rt2x00_rt(rt2x00dev, RT5390) || 741 rt2x00_rt(rt2x00dev, RT5392)) { 742 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 743 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 744 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 745 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 746 } 747 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 748 } 749 750 rt2800_disable_wpdma(rt2x00dev); 751 752 /* 753 * Write firmware to the device. 754 */ 755 rt2800_drv_write_firmware(rt2x00dev, data, len); 756 757 /* 758 * Wait for device to stabilize. 759 */ 760 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 761 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 762 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 763 break; 764 msleep(1); 765 } 766 767 if (i == REGISTER_BUSY_COUNT) { 768 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 769 return -EBUSY; 770 } 771 772 /* 773 * Disable DMA, will be reenabled later when enabling 774 * the radio. 775 */ 776 rt2800_disable_wpdma(rt2x00dev); 777 778 /* 779 * Initialize firmware. 780 */ 781 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 782 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 783 if (rt2x00_is_usb(rt2x00dev)) { 784 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 785 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 786 } 787 msleep(1); 788 789 return 0; 790 } 791 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 792 793 void rt2800_write_tx_data(struct queue_entry *entry, 794 struct txentry_desc *txdesc) 795 { 796 __le32 *txwi = rt2800_drv_get_txwi(entry); 797 u32 word; 798 int i; 799 800 /* 801 * Initialize TX Info descriptor 802 */ 803 word = rt2x00_desc_read(txwi, 0); 804 rt2x00_set_field32(&word, TXWI_W0_FRAG, 805 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 807 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 808 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 809 rt2x00_set_field32(&word, TXWI_W0_TS, 810 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 811 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 812 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 814 txdesc->u.ht.mpdu_density); 815 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 816 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 817 rt2x00_set_field32(&word, TXWI_W0_BW, 818 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 819 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 820 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 821 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 822 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 823 rt2x00_desc_write(txwi, 0, word); 824 825 word = rt2x00_desc_read(txwi, 1); 826 rt2x00_set_field32(&word, TXWI_W1_ACK, 827 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 828 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 829 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 830 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 831 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 832 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 833 txdesc->key_idx : txdesc->u.ht.wcid); 834 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 835 txdesc->length); 836 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 837 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 838 rt2x00_desc_write(txwi, 1, word); 839 840 /* 841 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 842 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 843 * When TXD_W3_WIV is set to 1 it will use the IV data 844 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 845 * crypto entry in the registers should be used to encrypt the frame. 846 * 847 * Nulify all remaining words as well, we don't know how to program them. 848 */ 849 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 850 _rt2x00_desc_write(txwi, i, 0); 851 } 852 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 853 854 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 855 { 856 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 857 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 858 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 859 u16 eeprom; 860 u8 offset0; 861 u8 offset1; 862 u8 offset2; 863 864 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 865 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 866 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 867 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 868 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 869 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 870 } else { 871 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 872 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 873 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 874 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 875 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 876 } 877 878 /* 879 * Convert the value from the descriptor into the RSSI value 880 * If the value in the descriptor is 0, it is considered invalid 881 * and the default (extremely low) rssi value is assumed 882 */ 883 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 884 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 885 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 886 887 /* 888 * mac80211 only accepts a single RSSI value. Calculating the 889 * average doesn't deliver a fair answer either since -60:-60 would 890 * be considered equally good as -50:-70 while the second is the one 891 * which gives less energy... 892 */ 893 rssi0 = max(rssi0, rssi1); 894 return (int)max(rssi0, rssi2); 895 } 896 897 void rt2800_process_rxwi(struct queue_entry *entry, 898 struct rxdone_entry_desc *rxdesc) 899 { 900 __le32 *rxwi = (__le32 *) entry->skb->data; 901 u32 word; 902 903 word = rt2x00_desc_read(rxwi, 0); 904 905 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 906 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 907 908 word = rt2x00_desc_read(rxwi, 1); 909 910 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 911 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 912 913 if (rt2x00_get_field32(word, RXWI_W1_BW)) 914 rxdesc->bw = RATE_INFO_BW_40; 915 916 /* 917 * Detect RX rate, always use MCS as signal type. 918 */ 919 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 920 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 921 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 922 923 /* 924 * Mask of 0x8 bit to remove the short preamble flag. 925 */ 926 if (rxdesc->rate_mode == RATE_MODE_CCK) 927 rxdesc->signal &= ~0x8; 928 929 word = rt2x00_desc_read(rxwi, 2); 930 931 /* 932 * Convert descriptor AGC value to RSSI value. 933 */ 934 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 935 /* 936 * Remove RXWI descriptor from start of the buffer. 937 */ 938 skb_pull(entry->skb, entry->queue->winfo_size); 939 } 940 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 941 942 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 943 u32 status, enum nl80211_band band) 944 { 945 u8 flags = 0; 946 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 947 948 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 949 case RATE_MODE_HT_GREENFIELD: 950 flags |= IEEE80211_TX_RC_GREEN_FIELD; 951 fallthrough; 952 case RATE_MODE_HT_MIX: 953 flags |= IEEE80211_TX_RC_MCS; 954 break; 955 case RATE_MODE_OFDM: 956 if (band == NL80211_BAND_2GHZ) 957 idx += 4; 958 break; 959 case RATE_MODE_CCK: 960 if (idx >= 8) 961 idx -= 8; 962 break; 963 } 964 965 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 966 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 967 968 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 969 flags |= IEEE80211_TX_RC_SHORT_GI; 970 971 skbdesc->tx_rate_idx = idx; 972 skbdesc->tx_rate_flags = flags; 973 } 974 975 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 976 { 977 __le32 *txwi; 978 u32 word; 979 int wcid, ack, pid; 980 int tx_wcid, tx_ack, tx_pid, is_agg; 981 982 /* 983 * This frames has returned with an IO error, 984 * so the status report is not intended for this 985 * frame. 986 */ 987 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 988 return false; 989 990 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 991 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 992 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 993 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 994 995 /* 996 * Validate if this TX status report is intended for 997 * this entry by comparing the WCID/ACK/PID fields. 998 */ 999 txwi = rt2800_drv_get_txwi(entry); 1000 1001 word = rt2x00_desc_read(txwi, 1); 1002 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 1003 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 1004 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 1005 1006 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 1007 rt2x00_dbg(entry->queue->rt2x00dev, 1008 "TX status report missed for queue %d entry %d\n", 1009 entry->queue->qid, entry->entry_idx); 1010 return false; 1011 } 1012 1013 return true; 1014 } 1015 1016 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 1017 bool match) 1018 { 1019 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1020 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1021 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1022 struct txdone_entry_desc txdesc; 1023 u32 word; 1024 u16 mcs, real_mcs; 1025 int aggr, ampdu, wcid, ack_req; 1026 1027 /* 1028 * Obtain the status about this packet. 1029 */ 1030 txdesc.flags = 0; 1031 word = rt2x00_desc_read(txwi, 0); 1032 1033 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1034 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1035 1036 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1037 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1038 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1039 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1040 1041 /* 1042 * If a frame was meant to be sent as a single non-aggregated MPDU 1043 * but ended up in an aggregate the used tx rate doesn't correlate 1044 * with the one specified in the TXWI as the whole aggregate is sent 1045 * with the same rate. 1046 * 1047 * For example: two frames are sent to rt2x00, the first one sets 1048 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1049 * and requests MCS15. If the hw aggregates both frames into one 1050 * AMDPU the tx status for both frames will contain MCS7 although 1051 * the frame was sent successfully. 1052 * 1053 * Hence, replace the requested rate with the real tx rate to not 1054 * confuse the rate control algortihm by providing clearly wrong 1055 * data. 1056 * 1057 * FIXME: if we do not find matching entry, we tell that frame was 1058 * posted without any retries. We need to find a way to fix that 1059 * and provide retry count. 1060 */ 1061 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1062 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1063 mcs = real_mcs; 1064 } 1065 1066 if (aggr == 1 || ampdu == 1) 1067 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1068 1069 if (!ack_req) 1070 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1071 1072 /* 1073 * Ralink has a retry mechanism using a global fallback 1074 * table. We setup this fallback table to try the immediate 1075 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1076 * always contains the MCS used for the last transmission, be 1077 * it successful or not. 1078 */ 1079 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1080 /* 1081 * Transmission succeeded. The number of retries is 1082 * mcs - real_mcs 1083 */ 1084 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1085 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1086 } else { 1087 /* 1088 * Transmission failed. The number of retries is 1089 * always 7 in this case (for a total number of 8 1090 * frames sent). 1091 */ 1092 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1093 txdesc.retry = rt2x00dev->long_retry; 1094 } 1095 1096 /* 1097 * the frame was retried at least once 1098 * -> hw used fallback rates 1099 */ 1100 if (txdesc.retry) 1101 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1102 1103 if (!match) { 1104 /* RCU assures non-null sta will not be freed by mac80211. */ 1105 rcu_read_lock(); 1106 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1107 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1108 else 1109 skbdesc->sta = NULL; 1110 rt2x00lib_txdone_nomatch(entry, &txdesc); 1111 rcu_read_unlock(); 1112 } else { 1113 rt2x00lib_txdone(entry, &txdesc); 1114 } 1115 } 1116 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1117 1118 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1119 { 1120 struct data_queue *queue; 1121 struct queue_entry *entry; 1122 u32 reg; 1123 u8 qid; 1124 bool match; 1125 1126 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1127 /* 1128 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1129 * guaranteed to be one of the TX QIDs . 1130 */ 1131 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1132 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1133 1134 if (unlikely(rt2x00queue_empty(queue))) { 1135 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1136 qid); 1137 break; 1138 } 1139 1140 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1141 1142 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1143 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1144 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1145 entry->entry_idx, qid); 1146 break; 1147 } 1148 1149 match = rt2800_txdone_entry_check(entry, reg); 1150 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1151 } 1152 } 1153 EXPORT_SYMBOL_GPL(rt2800_txdone); 1154 1155 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1156 struct queue_entry *entry) 1157 { 1158 bool ret; 1159 unsigned long tout; 1160 1161 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1162 return false; 1163 1164 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1165 tout = msecs_to_jiffies(50); 1166 else 1167 tout = msecs_to_jiffies(2000); 1168 1169 ret = time_after(jiffies, entry->last_action + tout); 1170 if (unlikely(ret)) 1171 rt2x00_dbg(entry->queue->rt2x00dev, 1172 "TX status timeout for entry %d in queue %d\n", 1173 entry->entry_idx, entry->queue->qid); 1174 return ret; 1175 } 1176 1177 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1178 { 1179 struct data_queue *queue; 1180 struct queue_entry *entry; 1181 1182 tx_queue_for_each(rt2x00dev, queue) { 1183 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1184 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1185 return true; 1186 } 1187 1188 return false; 1189 } 1190 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1191 1192 /* 1193 * test if there is an entry in any TX queue for which DMA is done 1194 * but the TX status has not been returned yet 1195 */ 1196 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1197 { 1198 struct data_queue *queue; 1199 1200 tx_queue_for_each(rt2x00dev, queue) { 1201 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1202 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1203 return true; 1204 } 1205 return false; 1206 } 1207 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1208 1209 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1210 { 1211 struct data_queue *queue; 1212 struct queue_entry *entry; 1213 1214 /* 1215 * Process any trailing TX status reports for IO failures, 1216 * we loop until we find the first non-IO error entry. This 1217 * can either be a frame which is free, is being uploaded, 1218 * or has completed the upload but didn't have an entry 1219 * in the TX_STAT_FIFO register yet. 1220 */ 1221 tx_queue_for_each(rt2x00dev, queue) { 1222 while (!rt2x00queue_empty(queue)) { 1223 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1224 1225 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1226 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1227 break; 1228 1229 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1230 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1231 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1232 else 1233 break; 1234 } 1235 } 1236 } 1237 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1238 1239 static int rt2800_check_hung(struct data_queue *queue) 1240 { 1241 unsigned int cur_idx = rt2800_drv_get_dma_done(queue); 1242 1243 if (queue->wd_idx != cur_idx) 1244 queue->wd_count = 0; 1245 else 1246 queue->wd_count++; 1247 1248 return queue->wd_count > 16; 1249 } 1250 1251 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev) 1252 { 1253 struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan; 1254 struct rt2x00_chan_survey *chan_survey = 1255 &rt2x00dev->chan_survey[chan->hw_value]; 1256 1257 chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA); 1258 chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA); 1259 chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 1260 } 1261 1262 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev) 1263 { 1264 struct data_queue *queue; 1265 bool hung_tx = false; 1266 bool hung_rx = false; 1267 1268 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) 1269 return; 1270 1271 rt2800_update_survey(rt2x00dev); 1272 1273 queue_for_each(rt2x00dev, queue) { 1274 switch (queue->qid) { 1275 case QID_AC_VO: 1276 case QID_AC_VI: 1277 case QID_AC_BE: 1278 case QID_AC_BK: 1279 case QID_MGMT: 1280 if (rt2x00queue_empty(queue)) 1281 continue; 1282 hung_tx = rt2800_check_hung(queue); 1283 break; 1284 case QID_RX: 1285 /* For station mode we should reactive at least 1286 * beacons. TODO: need to find good way detect 1287 * RX hung for AP mode. 1288 */ 1289 if (rt2x00dev->intf_sta_count == 0) 1290 continue; 1291 hung_rx = rt2800_check_hung(queue); 1292 break; 1293 default: 1294 break; 1295 } 1296 } 1297 1298 if (hung_tx) 1299 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n"); 1300 1301 if (hung_rx) 1302 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n"); 1303 1304 if (hung_tx || hung_rx) 1305 ieee80211_restart_hw(rt2x00dev->hw); 1306 } 1307 EXPORT_SYMBOL_GPL(rt2800_watchdog); 1308 1309 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1310 unsigned int index) 1311 { 1312 return HW_BEACON_BASE(index); 1313 } 1314 1315 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1316 unsigned int index) 1317 { 1318 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1319 } 1320 1321 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1322 { 1323 struct data_queue *queue = rt2x00dev->bcn; 1324 struct queue_entry *entry; 1325 int i, bcn_num = 0; 1326 u64 off, reg = 0; 1327 u32 bssid_dw1; 1328 1329 /* 1330 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1331 */ 1332 for (i = 0; i < queue->limit; i++) { 1333 entry = &queue->entries[i]; 1334 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1335 continue; 1336 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1337 reg |= off << (8 * bcn_num); 1338 bcn_num++; 1339 } 1340 1341 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1342 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1343 1344 /* 1345 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1346 */ 1347 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1348 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1349 bcn_num > 0 ? bcn_num - 1 : 0); 1350 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1351 } 1352 1353 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1354 { 1355 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1356 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1357 unsigned int beacon_base; 1358 unsigned int padding_len; 1359 u32 orig_reg, reg; 1360 const int txwi_desc_size = entry->queue->winfo_size; 1361 1362 /* 1363 * Disable beaconing while we are reloading the beacon data, 1364 * otherwise we might be sending out invalid data. 1365 */ 1366 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1367 orig_reg = reg; 1368 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1369 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1370 1371 /* 1372 * Add space for the TXWI in front of the skb. 1373 */ 1374 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1375 1376 /* 1377 * Register descriptor details in skb frame descriptor. 1378 */ 1379 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1380 skbdesc->desc = entry->skb->data; 1381 skbdesc->desc_len = txwi_desc_size; 1382 1383 /* 1384 * Add the TXWI for the beacon to the skb. 1385 */ 1386 rt2800_write_tx_data(entry, txdesc); 1387 1388 /* 1389 * Dump beacon to userspace through debugfs. 1390 */ 1391 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1392 1393 /* 1394 * Write entire beacon with TXWI and padding to register. 1395 */ 1396 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1397 if (padding_len && skb_pad(entry->skb, padding_len)) { 1398 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1399 /* skb freed by skb_pad() on failure */ 1400 entry->skb = NULL; 1401 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1402 return; 1403 } 1404 1405 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1406 1407 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1408 entry->skb->len + padding_len); 1409 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1410 1411 /* 1412 * Change global beacons settings. 1413 */ 1414 rt2800_update_beacons_setup(rt2x00dev); 1415 1416 /* 1417 * Restore beaconing state. 1418 */ 1419 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1420 1421 /* 1422 * Clean up beacon skb. 1423 */ 1424 dev_kfree_skb_any(entry->skb); 1425 entry->skb = NULL; 1426 } 1427 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1428 1429 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1430 unsigned int index) 1431 { 1432 int i; 1433 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1434 unsigned int beacon_base; 1435 1436 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1437 1438 /* 1439 * For the Beacon base registers we only need to clear 1440 * the whole TXWI which (when set to 0) will invalidate 1441 * the entire beacon. 1442 */ 1443 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1444 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1445 } 1446 1447 void rt2800_clear_beacon(struct queue_entry *entry) 1448 { 1449 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1450 u32 orig_reg, reg; 1451 1452 /* 1453 * Disable beaconing while we are reloading the beacon data, 1454 * otherwise we might be sending out invalid data. 1455 */ 1456 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1457 reg = orig_reg; 1458 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1459 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1460 1461 /* 1462 * Clear beacon. 1463 */ 1464 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1465 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1466 1467 /* 1468 * Change global beacons settings. 1469 */ 1470 rt2800_update_beacons_setup(rt2x00dev); 1471 /* 1472 * Restore beaconing state. 1473 */ 1474 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1475 } 1476 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1477 1478 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1479 const struct rt2x00debug rt2800_rt2x00debug = { 1480 .owner = THIS_MODULE, 1481 .csr = { 1482 .read = rt2800_register_read, 1483 .write = rt2800_register_write, 1484 .flags = RT2X00DEBUGFS_OFFSET, 1485 .word_base = CSR_REG_BASE, 1486 .word_size = sizeof(u32), 1487 .word_count = CSR_REG_SIZE / sizeof(u32), 1488 }, 1489 .eeprom = { 1490 /* NOTE: The local EEPROM access functions can't 1491 * be used here, use the generic versions instead. 1492 */ 1493 .read = rt2x00_eeprom_read, 1494 .write = rt2x00_eeprom_write, 1495 .word_base = EEPROM_BASE, 1496 .word_size = sizeof(u16), 1497 .word_count = EEPROM_SIZE / sizeof(u16), 1498 }, 1499 .bbp = { 1500 .read = rt2800_bbp_read, 1501 .write = rt2800_bbp_write, 1502 .word_base = BBP_BASE, 1503 .word_size = sizeof(u8), 1504 .word_count = BBP_SIZE / sizeof(u8), 1505 }, 1506 .rf = { 1507 .read = rt2x00_rf_read, 1508 .write = rt2800_rf_write, 1509 .word_base = RF_BASE, 1510 .word_size = sizeof(u32), 1511 .word_count = RF_SIZE / sizeof(u32), 1512 }, 1513 .rfcsr = { 1514 .read = rt2800_rfcsr_read, 1515 .write = rt2800_rfcsr_write, 1516 .word_base = RFCSR_BASE, 1517 .word_size = sizeof(u8), 1518 .word_count = RFCSR_SIZE / sizeof(u8), 1519 }, 1520 }; 1521 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1522 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1523 1524 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1525 { 1526 u32 reg; 1527 1528 if (rt2x00_rt(rt2x00dev, RT3290)) { 1529 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1530 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1531 } else { 1532 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1533 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1534 } 1535 } 1536 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1537 1538 #ifdef CONFIG_RT2X00_LIB_LEDS 1539 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1540 enum led_brightness brightness) 1541 { 1542 struct rt2x00_led *led = 1543 container_of(led_cdev, struct rt2x00_led, led_dev); 1544 unsigned int enabled = brightness != LED_OFF; 1545 unsigned int bg_mode = 1546 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1547 unsigned int polarity = 1548 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1549 EEPROM_FREQ_LED_POLARITY); 1550 unsigned int ledmode = 1551 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1552 EEPROM_FREQ_LED_MODE); 1553 u32 reg; 1554 1555 /* Check for SoC (SOC devices don't support MCU requests) */ 1556 if (rt2x00_is_soc(led->rt2x00dev)) { 1557 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1558 1559 /* Set LED Polarity */ 1560 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1561 1562 /* Set LED Mode */ 1563 if (led->type == LED_TYPE_RADIO) { 1564 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1565 enabled ? 3 : 0); 1566 } else if (led->type == LED_TYPE_ASSOC) { 1567 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1568 enabled ? 3 : 0); 1569 } else if (led->type == LED_TYPE_QUALITY) { 1570 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1571 enabled ? 3 : 0); 1572 } 1573 1574 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1575 1576 } else { 1577 if (led->type == LED_TYPE_RADIO) { 1578 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1579 enabled ? 0x20 : 0); 1580 } else if (led->type == LED_TYPE_ASSOC) { 1581 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1582 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1583 } else if (led->type == LED_TYPE_QUALITY) { 1584 /* 1585 * The brightness is divided into 6 levels (0 - 5), 1586 * The specs tell us the following levels: 1587 * 0, 1 ,3, 7, 15, 31 1588 * to determine the level in a simple way we can simply 1589 * work with bitshifting: 1590 * (1 << level) - 1 1591 */ 1592 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1593 (1 << brightness / (LED_FULL / 6)) - 1, 1594 polarity); 1595 } 1596 } 1597 } 1598 1599 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1600 struct rt2x00_led *led, enum led_type type) 1601 { 1602 led->rt2x00dev = rt2x00dev; 1603 led->type = type; 1604 led->led_dev.brightness_set = rt2800_brightness_set; 1605 led->flags = LED_INITIALIZED; 1606 } 1607 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1608 1609 /* 1610 * Configuration handlers. 1611 */ 1612 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1613 const u8 *address, 1614 int wcid) 1615 { 1616 struct mac_wcid_entry wcid_entry; 1617 u32 offset; 1618 1619 offset = MAC_WCID_ENTRY(wcid); 1620 1621 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1622 if (address) 1623 memcpy(wcid_entry.mac, address, ETH_ALEN); 1624 1625 rt2800_register_multiwrite(rt2x00dev, offset, 1626 &wcid_entry, sizeof(wcid_entry)); 1627 } 1628 1629 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1630 { 1631 u32 offset; 1632 offset = MAC_WCID_ATTR_ENTRY(wcid); 1633 rt2800_register_write(rt2x00dev, offset, 0); 1634 } 1635 1636 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1637 int wcid, u32 bssidx) 1638 { 1639 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1640 u32 reg; 1641 1642 /* 1643 * The BSS Idx numbers is split in a main value of 3 bits, 1644 * and a extended field for adding one additional bit to the value. 1645 */ 1646 reg = rt2800_register_read(rt2x00dev, offset); 1647 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1649 (bssidx & 0x8) >> 3); 1650 rt2800_register_write(rt2x00dev, offset, reg); 1651 } 1652 1653 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1654 struct rt2x00lib_crypto *crypto, 1655 struct ieee80211_key_conf *key) 1656 { 1657 struct mac_iveiv_entry iveiv_entry; 1658 u32 offset; 1659 u32 reg; 1660 1661 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1662 1663 if (crypto->cmd == SET_KEY) { 1664 reg = rt2800_register_read(rt2x00dev, offset); 1665 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1666 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1667 /* 1668 * Both the cipher as the BSS Idx numbers are split in a main 1669 * value of 3 bits, and a extended field for adding one additional 1670 * bit to the value. 1671 */ 1672 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1673 (crypto->cipher & 0x7)); 1674 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1675 (crypto->cipher & 0x8) >> 3); 1676 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1677 rt2800_register_write(rt2x00dev, offset, reg); 1678 } else { 1679 /* Delete the cipher without touching the bssidx */ 1680 reg = rt2800_register_read(rt2x00dev, offset); 1681 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1682 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1683 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1684 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1685 rt2800_register_write(rt2x00dev, offset, reg); 1686 } 1687 1688 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 1689 return; 1690 1691 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1692 1693 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1694 if ((crypto->cipher == CIPHER_TKIP) || 1695 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1696 (crypto->cipher == CIPHER_AES)) 1697 iveiv_entry.iv[3] |= 0x20; 1698 iveiv_entry.iv[3] |= key->keyidx << 6; 1699 rt2800_register_multiwrite(rt2x00dev, offset, 1700 &iveiv_entry, sizeof(iveiv_entry)); 1701 } 1702 1703 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1704 struct rt2x00lib_crypto *crypto, 1705 struct ieee80211_key_conf *key) 1706 { 1707 struct hw_key_entry key_entry; 1708 struct rt2x00_field32 field; 1709 u32 offset; 1710 u32 reg; 1711 1712 if (crypto->cmd == SET_KEY) { 1713 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1714 1715 memcpy(key_entry.key, crypto->key, 1716 sizeof(key_entry.key)); 1717 memcpy(key_entry.tx_mic, crypto->tx_mic, 1718 sizeof(key_entry.tx_mic)); 1719 memcpy(key_entry.rx_mic, crypto->rx_mic, 1720 sizeof(key_entry.rx_mic)); 1721 1722 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1723 rt2800_register_multiwrite(rt2x00dev, offset, 1724 &key_entry, sizeof(key_entry)); 1725 } 1726 1727 /* 1728 * The cipher types are stored over multiple registers 1729 * starting with SHARED_KEY_MODE_BASE each word will have 1730 * 32 bits and contains the cipher types for 2 bssidx each. 1731 * Using the correct defines correctly will cause overhead, 1732 * so just calculate the correct offset. 1733 */ 1734 field.bit_offset = 4 * (key->hw_key_idx % 8); 1735 field.bit_mask = 0x7 << field.bit_offset; 1736 1737 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1738 1739 reg = rt2800_register_read(rt2x00dev, offset); 1740 rt2x00_set_field32(®, field, 1741 (crypto->cmd == SET_KEY) * crypto->cipher); 1742 rt2800_register_write(rt2x00dev, offset, reg); 1743 1744 /* 1745 * Update WCID information 1746 */ 1747 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1748 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1749 crypto->bssidx); 1750 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1751 1752 return 0; 1753 } 1754 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1755 1756 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1757 struct rt2x00lib_crypto *crypto, 1758 struct ieee80211_key_conf *key) 1759 { 1760 struct hw_key_entry key_entry; 1761 u32 offset; 1762 1763 if (crypto->cmd == SET_KEY) { 1764 /* 1765 * Allow key configuration only for STAs that are 1766 * known by the hw. 1767 */ 1768 if (crypto->wcid > WCID_END) 1769 return -ENOSPC; 1770 key->hw_key_idx = crypto->wcid; 1771 1772 memcpy(key_entry.key, crypto->key, 1773 sizeof(key_entry.key)); 1774 memcpy(key_entry.tx_mic, crypto->tx_mic, 1775 sizeof(key_entry.tx_mic)); 1776 memcpy(key_entry.rx_mic, crypto->rx_mic, 1777 sizeof(key_entry.rx_mic)); 1778 1779 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1780 rt2800_register_multiwrite(rt2x00dev, offset, 1781 &key_entry, sizeof(key_entry)); 1782 } 1783 1784 /* 1785 * Update WCID information 1786 */ 1787 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1788 1789 return 0; 1790 } 1791 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1792 1793 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1794 { 1795 u8 i, max_psdu; 1796 u32 reg; 1797 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1798 1799 for (i = 0; i < 3; i++) 1800 if (drv_data->ampdu_factor_cnt[i] > 0) 1801 break; 1802 1803 max_psdu = min(drv_data->max_psdu, i); 1804 1805 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1806 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1807 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1808 } 1809 1810 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1811 struct ieee80211_sta *sta) 1812 { 1813 struct rt2x00_dev *rt2x00dev = hw->priv; 1814 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1815 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1816 int wcid; 1817 1818 /* 1819 * Limit global maximum TX AMPDU length to smallest value of all 1820 * connected stations. In AP mode this can be suboptimal, but we 1821 * do not have a choice if some connected STA is not capable to 1822 * receive the same amount of data like the others. 1823 */ 1824 if (sta->deflink.ht_cap.ht_supported) { 1825 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++; 1826 rt2800_set_max_psdu_len(rt2x00dev); 1827 } 1828 1829 /* 1830 * Search for the first free WCID entry and return the corresponding 1831 * index. 1832 */ 1833 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1834 1835 /* 1836 * Store selected wcid even if it is invalid so that we can 1837 * later decide if the STA is uploaded into the hw. 1838 */ 1839 sta_priv->wcid = wcid; 1840 1841 /* 1842 * No space left in the device, however, we can still communicate 1843 * with the STA -> No error. 1844 */ 1845 if (wcid > WCID_END) 1846 return 0; 1847 1848 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1849 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1850 1851 /* 1852 * Clean up WCID attributes and write STA address to the device. 1853 */ 1854 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1855 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1856 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1857 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1858 return 0; 1859 } 1860 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1861 1862 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1863 struct ieee80211_sta *sta) 1864 { 1865 struct rt2x00_dev *rt2x00dev = hw->priv; 1866 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1867 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1868 int wcid = sta_priv->wcid; 1869 1870 if (sta->deflink.ht_cap.ht_supported) { 1871 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--; 1872 rt2800_set_max_psdu_len(rt2x00dev); 1873 } 1874 1875 if (wcid > WCID_END) 1876 return 0; 1877 /* 1878 * Remove WCID entry, no need to clean the attributes as they will 1879 * get renewed when the WCID is reused. 1880 */ 1881 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1882 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1883 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1884 1885 return 0; 1886 } 1887 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1888 1889 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev) 1890 { 1891 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1892 struct data_queue *queue = rt2x00dev->bcn; 1893 struct queue_entry *entry; 1894 int i, wcid; 1895 1896 for (wcid = WCID_START; wcid < WCID_END; wcid++) { 1897 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1898 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1899 } 1900 1901 for (i = 0; i < queue->limit; i++) { 1902 entry = &queue->entries[i]; 1903 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags); 1904 } 1905 } 1906 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw); 1907 1908 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1909 const unsigned int filter_flags) 1910 { 1911 u32 reg; 1912 1913 /* 1914 * Start configuration steps. 1915 * Note that the version error will always be dropped 1916 * and broadcast frames will always be accepted since 1917 * there is no filter for it at this time. 1918 */ 1919 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1920 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1921 !(filter_flags & FIF_FCSFAIL)); 1922 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1923 !(filter_flags & FIF_PLCPFAIL)); 1924 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1925 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1926 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1927 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1928 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1929 !(filter_flags & FIF_ALLMULTI)); 1930 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1931 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1932 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1933 !(filter_flags & FIF_CONTROL)); 1934 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1935 !(filter_flags & FIF_CONTROL)); 1936 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1937 !(filter_flags & FIF_CONTROL)); 1938 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1939 !(filter_flags & FIF_CONTROL)); 1940 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1941 !(filter_flags & FIF_CONTROL)); 1942 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1943 !(filter_flags & FIF_PSPOLL)); 1944 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1945 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1946 !(filter_flags & FIF_CONTROL)); 1947 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1948 !(filter_flags & FIF_CONTROL)); 1949 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1950 } 1951 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1952 1953 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1954 struct rt2x00intf_conf *conf, const unsigned int flags) 1955 { 1956 u32 reg; 1957 bool update_bssid = false; 1958 1959 if (flags & CONFIG_UPDATE_TYPE) { 1960 /* 1961 * Enable synchronisation. 1962 */ 1963 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1964 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1965 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1966 1967 if (conf->sync == TSF_SYNC_AP_NONE) { 1968 /* 1969 * Tune beacon queue transmit parameters for AP mode 1970 */ 1971 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1972 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1973 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1974 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1975 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1976 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1977 } else { 1978 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1979 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1980 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1981 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1982 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1983 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1984 } 1985 } 1986 1987 if (flags & CONFIG_UPDATE_MAC) { 1988 if (flags & CONFIG_UPDATE_TYPE && 1989 conf->sync == TSF_SYNC_AP_NONE) { 1990 /* 1991 * The BSSID register has to be set to our own mac 1992 * address in AP mode. 1993 */ 1994 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1995 update_bssid = true; 1996 } 1997 1998 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1999 reg = le32_to_cpu(conf->mac[1]); 2000 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 2001 conf->mac[1] = cpu_to_le32(reg); 2002 } 2003 2004 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 2005 conf->mac, sizeof(conf->mac)); 2006 } 2007 2008 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 2009 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 2010 reg = le32_to_cpu(conf->bssid[1]); 2011 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 2012 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 2013 conf->bssid[1] = cpu_to_le32(reg); 2014 } 2015 2016 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 2017 conf->bssid, sizeof(conf->bssid)); 2018 } 2019 } 2020 EXPORT_SYMBOL_GPL(rt2800_config_intf); 2021 2022 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 2023 struct rt2x00lib_erp *erp) 2024 { 2025 bool any_sta_nongf = !!(erp->ht_opmode & 2026 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 2027 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 2028 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 2029 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 2030 u32 reg; 2031 2032 /* default protection rate for HT20: OFDM 24M */ 2033 mm20_rate = gf20_rate = 0x4004; 2034 2035 /* default protection rate for HT40: duplicate OFDM 24M */ 2036 mm40_rate = gf40_rate = 0x4084; 2037 2038 switch (protection) { 2039 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 2040 /* 2041 * All STAs in this BSS are HT20/40 but there might be 2042 * STAs not supporting greenfield mode. 2043 * => Disable protection for HT transmissions. 2044 */ 2045 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 2046 2047 break; 2048 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2049 /* 2050 * All STAs in this BSS are HT20 or HT20/40 but there 2051 * might be STAs not supporting greenfield mode. 2052 * => Protect all HT40 transmissions. 2053 */ 2054 mm20_mode = gf20_mode = 0; 2055 mm40_mode = gf40_mode = 1; 2056 2057 break; 2058 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 2059 /* 2060 * Nonmember protection: 2061 * According to 802.11n we _should_ protect all 2062 * HT transmissions (but we don't have to). 2063 * 2064 * But if cts_protection is enabled we _shall_ protect 2065 * all HT transmissions using a CCK rate. 2066 * 2067 * And if any station is non GF we _shall_ protect 2068 * GF transmissions. 2069 * 2070 * We decide to protect everything 2071 * -> fall through to mixed mode. 2072 */ 2073 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2074 /* 2075 * Legacy STAs are present 2076 * => Protect all HT transmissions. 2077 */ 2078 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 2079 2080 /* 2081 * If erp protection is needed we have to protect HT 2082 * transmissions with CCK 11M long preamble. 2083 */ 2084 if (erp->cts_protection) { 2085 /* don't duplicate RTS/CTS in CCK mode */ 2086 mm20_rate = mm40_rate = 0x0003; 2087 gf20_rate = gf40_rate = 0x0003; 2088 } 2089 break; 2090 } 2091 2092 /* check for STAs not supporting greenfield mode */ 2093 if (any_sta_nongf) 2094 gf20_mode = gf40_mode = 1; 2095 2096 /* Update HT protection config */ 2097 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 2098 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 2099 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 2100 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 2101 2102 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 2103 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 2104 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 2105 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 2106 2107 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 2108 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 2109 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 2110 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2111 2112 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 2113 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 2114 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2115 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2116 } 2117 2118 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2119 u32 changed) 2120 { 2121 u32 reg; 2122 2123 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2124 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2125 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2126 !!erp->short_preamble); 2127 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2128 } 2129 2130 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2131 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2132 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2133 erp->cts_protection ? 2 : 0); 2134 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2135 } 2136 2137 if (changed & BSS_CHANGED_BASIC_RATES) { 2138 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2139 0xff0 | erp->basic_rates); 2140 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2141 } 2142 2143 if (changed & BSS_CHANGED_ERP_SLOT) { 2144 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2145 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2146 erp->slot_time); 2147 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2148 2149 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2150 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2151 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2152 } 2153 2154 if (changed & BSS_CHANGED_BEACON_INT) { 2155 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2156 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2157 erp->beacon_int * 16); 2158 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2159 } 2160 2161 if (changed & BSS_CHANGED_HT) 2162 rt2800_config_ht_opmode(rt2x00dev, erp); 2163 } 2164 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2165 2166 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev, 2167 const struct rt2x00_field32 mask) 2168 { 2169 unsigned int i; 2170 u32 reg; 2171 2172 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2173 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 2174 if (!rt2x00_get_field32(reg, mask)) 2175 return 0; 2176 2177 udelay(REGISTER_BUSY_DELAY); 2178 } 2179 2180 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 2181 return -EACCES; 2182 } 2183 2184 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 2185 { 2186 unsigned int i; 2187 u8 value; 2188 2189 /* 2190 * BBP was enabled after firmware was loaded, 2191 * but we need to reactivate it now. 2192 */ 2193 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 2194 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 2195 msleep(1); 2196 2197 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2198 value = rt2800_bbp_read(rt2x00dev, 0); 2199 if ((value != 0xff) && (value != 0x00)) 2200 return 0; 2201 udelay(REGISTER_BUSY_DELAY); 2202 } 2203 2204 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 2205 return -EACCES; 2206 } 2207 2208 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2209 { 2210 u32 reg; 2211 u16 eeprom; 2212 u8 led_ctrl, led_g_mode, led_r_mode; 2213 2214 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2215 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2216 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2217 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2218 } else { 2219 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2220 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2221 } 2222 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2223 2224 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2225 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2226 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2227 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2228 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2229 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2230 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2231 if (led_ctrl == 0 || led_ctrl > 0x40) { 2232 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2233 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2234 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2235 } else { 2236 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2237 (led_g_mode << 2) | led_r_mode, 1); 2238 } 2239 } 2240 } 2241 2242 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2243 enum antenna ant) 2244 { 2245 u32 reg; 2246 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2247 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2248 2249 if (rt2x00_is_pci(rt2x00dev)) { 2250 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2251 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2252 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2253 } else if (rt2x00_is_usb(rt2x00dev)) 2254 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2255 eesk_pin, 0); 2256 2257 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2258 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2259 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2260 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2261 } 2262 2263 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2264 { 2265 u8 r1; 2266 u8 r3; 2267 u16 eeprom; 2268 2269 r1 = rt2800_bbp_read(rt2x00dev, 1); 2270 r3 = rt2800_bbp_read(rt2x00dev, 3); 2271 2272 if (rt2x00_rt(rt2x00dev, RT3572) && 2273 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2274 rt2800_config_3572bt_ant(rt2x00dev); 2275 2276 /* 2277 * Configure the TX antenna. 2278 */ 2279 switch (ant->tx_chain_num) { 2280 case 1: 2281 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2282 break; 2283 case 2: 2284 if (rt2x00_rt(rt2x00dev, RT3572) && 2285 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2286 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2287 else 2288 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2289 break; 2290 case 3: 2291 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2292 break; 2293 } 2294 2295 /* 2296 * Configure the RX antenna. 2297 */ 2298 switch (ant->rx_chain_num) { 2299 case 1: 2300 if (rt2x00_rt(rt2x00dev, RT3070) || 2301 rt2x00_rt(rt2x00dev, RT3090) || 2302 rt2x00_rt(rt2x00dev, RT3352) || 2303 rt2x00_rt(rt2x00dev, RT3390)) { 2304 eeprom = rt2800_eeprom_read(rt2x00dev, 2305 EEPROM_NIC_CONF1); 2306 if (rt2x00_get_field16(eeprom, 2307 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2308 rt2800_set_ant_diversity(rt2x00dev, 2309 rt2x00dev->default_ant.rx); 2310 } 2311 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2312 break; 2313 case 2: 2314 if (rt2x00_rt(rt2x00dev, RT3572) && 2315 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2316 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2317 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2318 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2319 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2320 } else { 2321 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2322 } 2323 break; 2324 case 3: 2325 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2326 break; 2327 } 2328 2329 rt2800_bbp_write(rt2x00dev, 3, r3); 2330 rt2800_bbp_write(rt2x00dev, 1, r1); 2331 2332 if (rt2x00_rt(rt2x00dev, RT3593) || 2333 rt2x00_rt(rt2x00dev, RT3883)) { 2334 if (ant->rx_chain_num == 1) 2335 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2336 else 2337 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2338 } 2339 } 2340 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2341 2342 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2343 struct rt2x00lib_conf *libconf) 2344 { 2345 u16 eeprom; 2346 short lna_gain; 2347 2348 if (libconf->rf.channel <= 14) { 2349 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2350 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2351 } else if (libconf->rf.channel <= 64) { 2352 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2353 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2354 } else if (libconf->rf.channel <= 128) { 2355 if (rt2x00_rt(rt2x00dev, RT3593) || 2356 rt2x00_rt(rt2x00dev, RT3883)) { 2357 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2358 lna_gain = rt2x00_get_field16(eeprom, 2359 EEPROM_EXT_LNA2_A1); 2360 } else { 2361 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2362 lna_gain = rt2x00_get_field16(eeprom, 2363 EEPROM_RSSI_BG2_LNA_A1); 2364 } 2365 } else { 2366 if (rt2x00_rt(rt2x00dev, RT3593) || 2367 rt2x00_rt(rt2x00dev, RT3883)) { 2368 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2369 lna_gain = rt2x00_get_field16(eeprom, 2370 EEPROM_EXT_LNA2_A2); 2371 } else { 2372 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2373 lna_gain = rt2x00_get_field16(eeprom, 2374 EEPROM_RSSI_A2_LNA_A2); 2375 } 2376 } 2377 2378 rt2x00dev->lna_gain = lna_gain; 2379 } 2380 2381 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2382 { 2383 return clk_get_rate(rt2x00dev->clk) == 20000000; 2384 } 2385 2386 #define FREQ_OFFSET_BOUND 0x5f 2387 2388 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2389 { 2390 u8 freq_offset, prev_freq_offset; 2391 u8 rfcsr, prev_rfcsr; 2392 2393 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2394 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2395 2396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2397 prev_rfcsr = rfcsr; 2398 2399 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2400 if (rfcsr == prev_rfcsr) 2401 return; 2402 2403 if (rt2x00_is_usb(rt2x00dev)) { 2404 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2405 freq_offset, prev_rfcsr); 2406 return; 2407 } 2408 2409 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2410 while (prev_freq_offset != freq_offset) { 2411 if (prev_freq_offset < freq_offset) 2412 prev_freq_offset++; 2413 else 2414 prev_freq_offset--; 2415 2416 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2417 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2418 2419 usleep_range(1000, 1500); 2420 } 2421 } 2422 2423 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2424 struct ieee80211_conf *conf, 2425 struct rf_channel *rf, 2426 struct channel_info *info) 2427 { 2428 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2429 2430 if (rt2x00dev->default_ant.tx_chain_num == 1) 2431 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2432 2433 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2434 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2435 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2436 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2437 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2438 2439 if (rf->channel > 14) { 2440 /* 2441 * When TX power is below 0, we should increase it by 7 to 2442 * make it a positive value (Minimum value is -7). 2443 * However this means that values between 0 and 7 have 2444 * double meaning, and we should set a 7DBm boost flag. 2445 */ 2446 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2447 (info->default_power1 >= 0)); 2448 2449 if (info->default_power1 < 0) 2450 info->default_power1 += 7; 2451 2452 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2453 2454 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2455 (info->default_power2 >= 0)); 2456 2457 if (info->default_power2 < 0) 2458 info->default_power2 += 7; 2459 2460 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2461 } else { 2462 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2463 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2464 } 2465 2466 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2467 2468 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2469 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2470 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2471 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2472 2473 udelay(200); 2474 2475 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2476 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2477 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2478 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2479 2480 udelay(200); 2481 2482 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2483 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2484 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2485 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2486 } 2487 2488 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2489 struct ieee80211_conf *conf, 2490 struct rf_channel *rf, 2491 struct channel_info *info) 2492 { 2493 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2494 u8 rfcsr, calib_tx, calib_rx; 2495 2496 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2497 2498 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2499 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2500 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2501 2502 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2503 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2504 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2505 2506 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2507 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2508 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2509 2510 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2511 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2512 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2513 2514 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2515 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2516 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2517 rt2x00dev->default_ant.rx_chain_num <= 1); 2518 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2519 rt2x00dev->default_ant.rx_chain_num <= 2); 2520 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2521 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2522 rt2x00dev->default_ant.tx_chain_num <= 1); 2523 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2524 rt2x00dev->default_ant.tx_chain_num <= 2); 2525 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2526 2527 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2528 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2529 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2530 2531 if (rt2x00_rt(rt2x00dev, RT3390)) { 2532 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2533 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2534 } else { 2535 if (conf_is_ht40(conf)) { 2536 calib_tx = drv_data->calibration_bw40; 2537 calib_rx = drv_data->calibration_bw40; 2538 } else { 2539 calib_tx = drv_data->calibration_bw20; 2540 calib_rx = drv_data->calibration_bw20; 2541 } 2542 } 2543 2544 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2545 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2546 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2547 2548 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2549 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2550 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2551 2552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2553 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2554 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2555 2556 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2557 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2558 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2559 2560 usleep_range(1000, 1500); 2561 2562 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2563 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2564 } 2565 2566 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2567 struct ieee80211_conf *conf, 2568 struct rf_channel *rf, 2569 struct channel_info *info) 2570 { 2571 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2572 u8 rfcsr; 2573 u32 reg; 2574 2575 if (rf->channel <= 14) { 2576 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2577 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2578 } else { 2579 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2580 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2581 } 2582 2583 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2584 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2585 2586 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2587 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2588 if (rf->channel <= 14) 2589 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2590 else 2591 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2592 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2593 2594 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2595 if (rf->channel <= 14) 2596 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2597 else 2598 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2599 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2600 2601 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2602 if (rf->channel <= 14) { 2603 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2604 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2605 info->default_power1); 2606 } else { 2607 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2608 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2609 (info->default_power1 & 0x3) | 2610 ((info->default_power1 & 0xC) << 1)); 2611 } 2612 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2613 2614 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2615 if (rf->channel <= 14) { 2616 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2617 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2618 info->default_power2); 2619 } else { 2620 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2621 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2622 (info->default_power2 & 0x3) | 2623 ((info->default_power2 & 0xC) << 1)); 2624 } 2625 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2626 2627 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2628 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2629 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2630 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2631 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2632 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2633 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2634 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2635 if (rf->channel <= 14) { 2636 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2637 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2638 } 2639 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2640 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2641 } else { 2642 switch (rt2x00dev->default_ant.tx_chain_num) { 2643 case 1: 2644 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2645 fallthrough; 2646 case 2: 2647 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2648 break; 2649 } 2650 2651 switch (rt2x00dev->default_ant.rx_chain_num) { 2652 case 1: 2653 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2654 fallthrough; 2655 case 2: 2656 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2657 break; 2658 } 2659 } 2660 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2661 2662 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2663 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2664 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2665 2666 if (conf_is_ht40(conf)) { 2667 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2668 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2669 } else { 2670 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2671 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2672 } 2673 2674 if (rf->channel <= 14) { 2675 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2676 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2677 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2678 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2679 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2680 rfcsr = 0x4c; 2681 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2682 drv_data->txmixer_gain_24g); 2683 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2684 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2685 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2686 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2687 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2688 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2689 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2690 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2691 } else { 2692 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2693 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2694 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2695 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2696 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2697 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2698 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2699 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2700 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2701 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2702 rfcsr = 0x7a; 2703 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2704 drv_data->txmixer_gain_5g); 2705 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2706 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2707 if (rf->channel <= 64) { 2708 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2709 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2710 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2711 } else if (rf->channel <= 128) { 2712 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2713 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2714 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2715 } else { 2716 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2717 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2718 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2719 } 2720 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2721 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2722 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2723 } 2724 2725 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2726 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2727 if (rf->channel <= 14) 2728 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2729 else 2730 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2731 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2732 2733 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2734 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2735 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2736 } 2737 2738 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2739 struct ieee80211_conf *conf, 2740 struct rf_channel *rf, 2741 struct channel_info *info) 2742 { 2743 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2744 u8 txrx_agc_fc; 2745 u8 txrx_h20m; 2746 u8 rfcsr; 2747 u8 bbp; 2748 const bool txbf_enabled = false; /* TODO */ 2749 2750 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2751 bbp = rt2800_bbp_read(rt2x00dev, 109); 2752 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2753 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2754 rt2800_bbp_write(rt2x00dev, 109, bbp); 2755 2756 bbp = rt2800_bbp_read(rt2x00dev, 110); 2757 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2758 rt2800_bbp_write(rt2x00dev, 110, bbp); 2759 2760 if (rf->channel <= 14) { 2761 /* Restore BBP 25 & 26 for 2.4 GHz */ 2762 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2763 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2764 } else { 2765 /* Hard code BBP 25 & 26 for 5GHz */ 2766 2767 /* Enable IQ Phase correction */ 2768 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2769 /* Setup IQ Phase correction value */ 2770 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2771 } 2772 2773 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2774 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2775 2776 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2777 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2778 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2779 2780 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2781 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2782 if (rf->channel <= 14) 2783 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2784 else 2785 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2786 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2787 2788 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2789 if (rf->channel <= 14) { 2790 rfcsr = 0; 2791 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2792 info->default_power1 & 0x1f); 2793 } else { 2794 if (rt2x00_is_usb(rt2x00dev)) 2795 rfcsr = 0x40; 2796 2797 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2798 ((info->default_power1 & 0x18) << 1) | 2799 (info->default_power1 & 7)); 2800 } 2801 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2802 2803 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2804 if (rf->channel <= 14) { 2805 rfcsr = 0; 2806 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2807 info->default_power2 & 0x1f); 2808 } else { 2809 if (rt2x00_is_usb(rt2x00dev)) 2810 rfcsr = 0x40; 2811 2812 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2813 ((info->default_power2 & 0x18) << 1) | 2814 (info->default_power2 & 7)); 2815 } 2816 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2817 2818 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2819 if (rf->channel <= 14) { 2820 rfcsr = 0; 2821 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2822 info->default_power3 & 0x1f); 2823 } else { 2824 if (rt2x00_is_usb(rt2x00dev)) 2825 rfcsr = 0x40; 2826 2827 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2828 ((info->default_power3 & 0x18) << 1) | 2829 (info->default_power3 & 7)); 2830 } 2831 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2832 2833 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2834 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2835 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2836 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2837 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2838 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2839 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2840 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2841 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2842 2843 switch (rt2x00dev->default_ant.tx_chain_num) { 2844 case 3: 2845 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2846 fallthrough; 2847 case 2: 2848 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2849 fallthrough; 2850 case 1: 2851 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2852 break; 2853 } 2854 2855 switch (rt2x00dev->default_ant.rx_chain_num) { 2856 case 3: 2857 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2858 fallthrough; 2859 case 2: 2860 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2861 fallthrough; 2862 case 1: 2863 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2864 break; 2865 } 2866 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2867 2868 rt2800_freq_cal_mode1(rt2x00dev); 2869 2870 if (conf_is_ht40(conf)) { 2871 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2872 RFCSR24_TX_AGC_FC); 2873 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2874 RFCSR24_TX_H20M); 2875 } else { 2876 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2877 RFCSR24_TX_AGC_FC); 2878 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2879 RFCSR24_TX_H20M); 2880 } 2881 2882 /* NOTE: the reference driver does not writes the new value 2883 * back to RFCSR 32 2884 */ 2885 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2886 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2887 2888 if (rf->channel <= 14) 2889 rfcsr = 0xa0; 2890 else 2891 rfcsr = 0x80; 2892 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2893 2894 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2895 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2896 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2897 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2898 2899 /* Band selection */ 2900 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2901 if (rf->channel <= 14) 2902 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2903 else 2904 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2905 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2906 2907 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2908 if (rf->channel <= 14) 2909 rfcsr = 0x3c; 2910 else 2911 rfcsr = 0x20; 2912 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2913 2914 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2915 if (rf->channel <= 14) 2916 rfcsr = 0x1a; 2917 else 2918 rfcsr = 0x12; 2919 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2920 2921 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2922 if (rf->channel >= 1 && rf->channel <= 14) 2923 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2924 else if (rf->channel >= 36 && rf->channel <= 64) 2925 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2926 else if (rf->channel >= 100 && rf->channel <= 128) 2927 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2928 else 2929 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2930 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2931 2932 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2933 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2934 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2935 2936 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2937 2938 if (rf->channel <= 14) { 2939 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2940 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2941 } else { 2942 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2943 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2944 } 2945 2946 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2947 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2948 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2949 2950 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2951 if (rf->channel <= 14) { 2952 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2953 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2954 } else { 2955 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2956 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2957 } 2958 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2959 2960 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2961 if (rf->channel <= 14) 2962 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2963 else 2964 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2965 2966 if (txbf_enabled) 2967 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2968 2969 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2970 2971 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2972 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2973 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2974 2975 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2976 if (rf->channel <= 14) 2977 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2978 else 2979 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2980 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2981 2982 if (rf->channel <= 14) { 2983 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2984 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2985 } else { 2986 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2987 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2988 } 2989 2990 /* Initiate VCO calibration */ 2991 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2992 if (rf->channel <= 14) { 2993 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2994 } else { 2995 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2996 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2997 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2998 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2999 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 3000 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3001 } 3002 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3003 3004 if (rf->channel >= 1 && rf->channel <= 14) { 3005 rfcsr = 0x23; 3006 if (txbf_enabled) 3007 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3008 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3009 3010 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 3011 } else if (rf->channel >= 36 && rf->channel <= 64) { 3012 rfcsr = 0x36; 3013 if (txbf_enabled) 3014 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3015 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 3016 3017 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 3018 } else if (rf->channel >= 100 && rf->channel <= 128) { 3019 rfcsr = 0x32; 3020 if (txbf_enabled) 3021 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3022 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3023 3024 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 3025 } else { 3026 rfcsr = 0x30; 3027 if (txbf_enabled) 3028 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3029 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3030 3031 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 3032 } 3033 } 3034 3035 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev, 3036 struct ieee80211_conf *conf, 3037 struct rf_channel *rf, 3038 struct channel_info *info) 3039 { 3040 u8 rfcsr; 3041 u8 bbp; 3042 u8 pwr1, pwr2, pwr3; 3043 3044 const bool txbf_enabled = false; /* TODO */ 3045 3046 /* TODO: add band selection */ 3047 3048 if (rf->channel <= 14) 3049 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3050 else if (rf->channel < 132) 3051 rt2800_rfcsr_write(rt2x00dev, 6, 0x80); 3052 else 3053 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3054 3055 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3056 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3057 3058 if (rf->channel <= 14) 3059 rt2800_rfcsr_write(rt2x00dev, 11, 0x46); 3060 else 3061 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 3062 3063 if (rf->channel <= 14) 3064 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 3065 else 3066 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3067 3068 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 3069 3070 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3071 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 3072 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 3073 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3074 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3075 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3076 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3077 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3078 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3079 3080 switch (rt2x00dev->default_ant.tx_chain_num) { 3081 case 3: 3082 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 3083 fallthrough; 3084 case 2: 3085 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3086 fallthrough; 3087 case 1: 3088 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3089 break; 3090 } 3091 3092 switch (rt2x00dev->default_ant.rx_chain_num) { 3093 case 3: 3094 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 3095 fallthrough; 3096 case 2: 3097 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3098 fallthrough; 3099 case 1: 3100 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3101 break; 3102 } 3103 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3104 3105 rt2800_freq_cal_mode1(rt2x00dev); 3106 3107 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3108 if (!conf_is_ht40(conf)) 3109 rfcsr &= ~(0x06); 3110 else 3111 rfcsr |= 0x06; 3112 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3113 3114 if (rf->channel <= 14) 3115 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0); 3116 else 3117 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3118 3119 if (conf_is_ht40(conf)) 3120 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3121 else 3122 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 3123 3124 if (rf->channel <= 14) 3125 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 3126 else 3127 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 3128 3129 /* loopback RF_BS */ 3130 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 3131 if (rf->channel <= 14) 3132 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 3133 else 3134 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 3135 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 3136 3137 if (rf->channel <= 14) 3138 rfcsr = 0x23; 3139 else if (rf->channel < 100) 3140 rfcsr = 0x36; 3141 else if (rf->channel < 132) 3142 rfcsr = 0x32; 3143 else 3144 rfcsr = 0x30; 3145 3146 if (txbf_enabled) 3147 rfcsr |= 0x40; 3148 3149 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3150 3151 if (rf->channel <= 14) 3152 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 3153 else 3154 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 3155 3156 if (rf->channel <= 14) 3157 rfcsr = 0xbb; 3158 else if (rf->channel < 100) 3159 rfcsr = 0xeb; 3160 else if (rf->channel < 132) 3161 rfcsr = 0xb3; 3162 else 3163 rfcsr = 0x9b; 3164 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr); 3165 3166 if (rf->channel <= 14) 3167 rfcsr = 0x8e; 3168 else 3169 rfcsr = 0x8a; 3170 3171 if (txbf_enabled) 3172 rfcsr |= 0x20; 3173 3174 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3175 3176 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 3177 3178 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 3179 if (rf->channel <= 14) 3180 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 3181 else 3182 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 3183 3184 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52); 3185 if (rf->channel <= 14) 3186 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 3187 else 3188 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 3189 3190 if (rf->channel <= 14) { 3191 pwr1 = info->default_power1 & 0x1f; 3192 pwr2 = info->default_power2 & 0x1f; 3193 pwr3 = info->default_power3 & 0x1f; 3194 } else { 3195 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) | 3196 (info->default_power1 & 0x7); 3197 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) | 3198 (info->default_power2 & 0x7); 3199 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) | 3200 (info->default_power3 & 0x7); 3201 } 3202 3203 rt2800_rfcsr_write(rt2x00dev, 53, pwr1); 3204 rt2800_rfcsr_write(rt2x00dev, 54, pwr2); 3205 rt2800_rfcsr_write(rt2x00dev, 55, pwr3); 3206 3207 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n", 3208 rf->channel, pwr1, pwr2, pwr3); 3209 3210 bbp = (info->default_power1 >> 5) | 3211 ((info->default_power2 & 0xe0) >> 1); 3212 rt2800_bbp_write(rt2x00dev, 109, bbp); 3213 3214 bbp = rt2800_bbp_read(rt2x00dev, 110); 3215 bbp &= 0x0f; 3216 bbp |= (info->default_power3 & 0xe0) >> 1; 3217 rt2800_bbp_write(rt2x00dev, 110, bbp); 3218 3219 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 3220 if (rf->channel <= 14) 3221 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 3222 else 3223 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 3224 3225 /* Enable RF tuning */ 3226 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3227 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3228 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3229 3230 udelay(2000); 3231 3232 bbp = rt2800_bbp_read(rt2x00dev, 49); 3233 /* clear update flag */ 3234 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe); 3235 rt2800_bbp_write(rt2x00dev, 49, bbp); 3236 3237 /* TODO: add calibration for TxBF */ 3238 } 3239 3240 #define POWER_BOUND 0x27 3241 #define POWER_BOUND_5G 0x2b 3242 3243 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 3244 struct ieee80211_conf *conf, 3245 struct rf_channel *rf, 3246 struct channel_info *info) 3247 { 3248 u8 rfcsr; 3249 3250 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3251 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3252 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3253 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3254 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3255 3256 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3257 if (info->default_power1 > POWER_BOUND) 3258 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3259 else 3260 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3261 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3262 3263 rt2800_freq_cal_mode1(rt2x00dev); 3264 3265 if (rf->channel <= 14) { 3266 if (rf->channel == 6) 3267 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 3268 else 3269 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3270 3271 if (rf->channel >= 1 && rf->channel <= 6) 3272 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 3273 else if (rf->channel >= 7 && rf->channel <= 11) 3274 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 3275 else if (rf->channel >= 12 && rf->channel <= 14) 3276 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 3277 } 3278 } 3279 3280 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 3281 struct ieee80211_conf *conf, 3282 struct rf_channel *rf, 3283 struct channel_info *info) 3284 { 3285 u8 rfcsr; 3286 3287 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3288 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3289 3290 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 3291 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 3292 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 3293 3294 if (info->default_power1 > POWER_BOUND) 3295 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 3296 else 3297 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 3298 3299 if (info->default_power2 > POWER_BOUND) 3300 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 3301 else 3302 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 3303 3304 rt2800_freq_cal_mode1(rt2x00dev); 3305 3306 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3307 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3308 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3309 3310 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 3311 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3312 else 3313 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3314 3315 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 3316 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3317 else 3318 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3319 3320 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3321 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3322 3323 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3324 3325 rt2800_rfcsr_write(rt2x00dev, 31, 80); 3326 } 3327 3328 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 3329 struct ieee80211_conf *conf, 3330 struct rf_channel *rf, 3331 struct channel_info *info) 3332 { 3333 u8 rfcsr; 3334 int idx = rf->channel-1; 3335 3336 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3337 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3338 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3339 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3340 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3341 3342 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3343 if (info->default_power1 > POWER_BOUND) 3344 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3345 else 3346 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3347 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3348 3349 if (rt2x00_rt(rt2x00dev, RT5392)) { 3350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3351 if (info->default_power2 > POWER_BOUND) 3352 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 3353 else 3354 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 3355 info->default_power2); 3356 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3357 } 3358 3359 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3360 if (rt2x00_rt(rt2x00dev, RT5392)) { 3361 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3362 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3363 } 3364 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3365 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3366 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3367 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3368 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3369 3370 rt2800_freq_cal_mode1(rt2x00dev); 3371 3372 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3373 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3374 /* r55/r59 value array of channel 1~14 */ 3375 static const char r55_bt_rev[] = {0x83, 0x83, 3376 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3377 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3378 static const char r59_bt_rev[] = {0x0e, 0x0e, 3379 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3380 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3381 3382 rt2800_rfcsr_write(rt2x00dev, 55, 3383 r55_bt_rev[idx]); 3384 rt2800_rfcsr_write(rt2x00dev, 59, 3385 r59_bt_rev[idx]); 3386 } else { 3387 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 3388 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3389 0x88, 0x88, 0x86, 0x85, 0x84}; 3390 3391 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3392 } 3393 } else { 3394 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3395 static const char r55_nonbt_rev[] = {0x23, 0x23, 3396 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3397 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3398 static const char r59_nonbt_rev[] = {0x07, 0x07, 3399 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3400 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3401 3402 rt2800_rfcsr_write(rt2x00dev, 55, 3403 r55_nonbt_rev[idx]); 3404 rt2800_rfcsr_write(rt2x00dev, 59, 3405 r59_nonbt_rev[idx]); 3406 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3407 rt2x00_rt(rt2x00dev, RT5392) || 3408 rt2x00_rt(rt2x00dev, RT6352)) { 3409 static const char r59_non_bt[] = {0x8f, 0x8f, 3410 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3411 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3412 3413 rt2800_rfcsr_write(rt2x00dev, 59, 3414 r59_non_bt[idx]); 3415 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3416 static const char r59_non_bt[] = {0x0b, 0x0b, 3417 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3418 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3419 3420 rt2800_rfcsr_write(rt2x00dev, 59, 3421 r59_non_bt[idx]); 3422 } 3423 } 3424 } 3425 3426 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3427 struct ieee80211_conf *conf, 3428 struct rf_channel *rf, 3429 struct channel_info *info) 3430 { 3431 u8 rfcsr, ep_reg; 3432 u32 reg; 3433 int power_bound; 3434 3435 /* TODO */ 3436 const bool is_11b = false; 3437 const bool is_type_ep = false; 3438 3439 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3440 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3441 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3442 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3443 3444 /* Order of values on rf_channel entry: N, K, mod, R */ 3445 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3446 3447 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3448 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3449 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3450 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3451 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3452 3453 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3454 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3455 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3456 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3457 3458 if (rf->channel <= 14) { 3459 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3460 /* FIXME: RF11 owerwrite ? */ 3461 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3462 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3463 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3464 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3465 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3466 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3467 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3468 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3469 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3470 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3471 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3472 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3473 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3474 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3475 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3476 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3477 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3478 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3479 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3480 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3481 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3482 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3483 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3484 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3485 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3486 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3487 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3488 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3489 3490 /* TODO RF27 <- tssi */ 3491 3492 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3493 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3494 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3495 3496 if (is_11b) { 3497 /* CCK */ 3498 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3499 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3500 if (is_type_ep) 3501 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3502 else 3503 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3504 } else { 3505 /* OFDM */ 3506 if (is_type_ep) 3507 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3508 else 3509 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3510 } 3511 3512 power_bound = POWER_BOUND; 3513 ep_reg = 0x2; 3514 } else { 3515 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3516 /* FIMXE: RF11 overwrite */ 3517 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3518 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3519 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3520 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3521 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3522 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3523 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3524 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3525 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3526 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3527 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3528 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3529 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3530 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3531 3532 /* TODO RF27 <- tssi */ 3533 3534 if (rf->channel >= 36 && rf->channel <= 64) { 3535 3536 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3537 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3538 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3539 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3540 if (rf->channel <= 50) 3541 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3542 else if (rf->channel >= 52) 3543 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3544 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3545 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3546 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3547 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3548 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3549 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3550 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3551 if (rf->channel <= 50) { 3552 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3553 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3554 } else if (rf->channel >= 52) { 3555 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3556 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3557 } 3558 3559 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3560 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3561 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3562 3563 } else if (rf->channel >= 100 && rf->channel <= 165) { 3564 3565 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3566 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3567 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3568 if (rf->channel <= 153) { 3569 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3570 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3571 } else if (rf->channel >= 155) { 3572 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3573 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3574 } 3575 if (rf->channel <= 138) { 3576 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3577 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3578 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3579 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3580 } else if (rf->channel >= 140) { 3581 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3582 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3583 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3584 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3585 } 3586 if (rf->channel <= 124) 3587 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3588 else if (rf->channel >= 126) 3589 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3590 if (rf->channel <= 138) 3591 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3592 else if (rf->channel >= 140) 3593 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3594 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3595 if (rf->channel <= 138) 3596 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3597 else if (rf->channel >= 140) 3598 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3599 if (rf->channel <= 128) 3600 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3601 else if (rf->channel >= 130) 3602 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3603 if (rf->channel <= 116) 3604 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3605 else if (rf->channel >= 118) 3606 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3607 if (rf->channel <= 138) 3608 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3609 else if (rf->channel >= 140) 3610 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3611 if (rf->channel <= 116) 3612 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3613 else if (rf->channel >= 118) 3614 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3615 } 3616 3617 power_bound = POWER_BOUND_5G; 3618 ep_reg = 0x3; 3619 } 3620 3621 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3622 if (info->default_power1 > power_bound) 3623 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3624 else 3625 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3626 if (is_type_ep) 3627 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3628 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3629 3630 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3631 if (info->default_power2 > power_bound) 3632 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3633 else 3634 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3635 if (is_type_ep) 3636 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3637 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3638 3639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3640 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3641 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3642 3643 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3644 rt2x00dev->default_ant.tx_chain_num >= 1); 3645 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3646 rt2x00dev->default_ant.tx_chain_num == 2); 3647 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3648 3649 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3650 rt2x00dev->default_ant.rx_chain_num >= 1); 3651 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3652 rt2x00dev->default_ant.rx_chain_num == 2); 3653 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3654 3655 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3656 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3657 3658 if (conf_is_ht40(conf)) 3659 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3660 else 3661 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3662 3663 if (!is_11b) { 3664 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3665 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3666 } 3667 3668 /* TODO proper frequency adjustment */ 3669 rt2800_freq_cal_mode1(rt2x00dev); 3670 3671 /* TODO merge with others */ 3672 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3673 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3674 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3675 3676 /* BBP settings */ 3677 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3678 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3679 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3680 3681 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3682 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3683 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3684 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3685 3686 /* GLRT band configuration */ 3687 rt2800_bbp_write(rt2x00dev, 195, 128); 3688 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3689 rt2800_bbp_write(rt2x00dev, 195, 129); 3690 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3691 rt2800_bbp_write(rt2x00dev, 195, 130); 3692 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3693 rt2800_bbp_write(rt2x00dev, 195, 131); 3694 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3695 rt2800_bbp_write(rt2x00dev, 195, 133); 3696 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3697 rt2800_bbp_write(rt2x00dev, 195, 124); 3698 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3699 } 3700 3701 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3702 struct ieee80211_conf *conf, 3703 struct rf_channel *rf, 3704 struct channel_info *info) 3705 { 3706 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3707 u8 rx_agc_fc, tx_agc_fc; 3708 u8 rfcsr; 3709 3710 /* Frequeny plan setting */ 3711 /* Rdiv setting (set 0x03 if Xtal==20) 3712 * R13[1:0] 3713 */ 3714 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3715 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3716 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3717 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3718 3719 /* N setting 3720 * R20[7:0] in rf->rf1 3721 * R21[0] always 0 3722 */ 3723 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3724 rfcsr = (rf->rf1 & 0x00ff); 3725 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3726 3727 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3728 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3729 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3730 3731 /* K setting (always 0) 3732 * R16[3:0] (RF PLL freq selection) 3733 */ 3734 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3735 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3736 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3737 3738 /* D setting (always 0) 3739 * R22[2:0] (D=15, R22[2:0]=<111>) 3740 */ 3741 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3742 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3743 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3744 3745 /* Ksd setting 3746 * Ksd: R17<7:0> in rf->rf2 3747 * R18<7:0> in rf->rf3 3748 * R19<1:0> in rf->rf4 3749 */ 3750 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3751 rfcsr = rf->rf2; 3752 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3753 3754 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3755 rfcsr = rf->rf3; 3756 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3757 3758 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3759 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3760 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3761 3762 /* Default: XO=20MHz , SDM mode */ 3763 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3764 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3765 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3766 3767 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3768 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3769 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3770 3771 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3772 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3773 rt2x00dev->default_ant.tx_chain_num != 1); 3774 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3775 3776 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3777 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3778 rt2x00dev->default_ant.tx_chain_num != 1); 3779 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3780 rt2x00dev->default_ant.rx_chain_num != 1); 3781 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3782 3783 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3784 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3785 rt2x00dev->default_ant.tx_chain_num != 1); 3786 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3787 3788 /* RF for DC Cal BW */ 3789 if (conf_is_ht40(conf)) { 3790 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3791 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3792 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3793 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3794 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3795 } else { 3796 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3797 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3798 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3799 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3800 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3801 } 3802 3803 if (conf_is_ht40(conf)) { 3804 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3805 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3806 } else { 3807 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3808 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3809 } 3810 3811 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3812 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3813 conf_is_ht40(conf) && (rf->channel == 11)); 3814 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3815 3816 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3817 if (conf_is_ht40(conf)) { 3818 rx_agc_fc = drv_data->rx_calibration_bw40; 3819 tx_agc_fc = drv_data->tx_calibration_bw40; 3820 } else { 3821 rx_agc_fc = drv_data->rx_calibration_bw20; 3822 tx_agc_fc = drv_data->tx_calibration_bw20; 3823 } 3824 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3825 rfcsr &= (~0x3F); 3826 rfcsr |= rx_agc_fc; 3827 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3828 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3829 rfcsr &= (~0x3F); 3830 rfcsr |= rx_agc_fc; 3831 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3832 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3833 rfcsr &= (~0x3F); 3834 rfcsr |= rx_agc_fc; 3835 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3836 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3837 rfcsr &= (~0x3F); 3838 rfcsr |= rx_agc_fc; 3839 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3840 3841 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3842 rfcsr &= (~0x3F); 3843 rfcsr |= tx_agc_fc; 3844 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3845 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3846 rfcsr &= (~0x3F); 3847 rfcsr |= tx_agc_fc; 3848 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3849 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3850 rfcsr &= (~0x3F); 3851 rfcsr |= tx_agc_fc; 3852 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3853 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3854 rfcsr &= (~0x3F); 3855 rfcsr |= tx_agc_fc; 3856 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3857 } 3858 3859 if (conf_is_ht40(conf)) { 3860 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10); 3861 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f); 3862 } else { 3863 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a); 3864 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40); 3865 } 3866 } 3867 3868 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3869 struct ieee80211_channel *chan, 3870 int power_level) { 3871 u16 eeprom, target_power, max_power; 3872 u32 mac_sys_ctrl; 3873 u32 reg; 3874 u8 bbp; 3875 3876 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3877 power_level *= 2; 3878 if (power_level > 0x2f) 3879 power_level = 0x2f; 3880 3881 max_power = chan->max_power * 2; 3882 if (max_power > 0x2f) 3883 max_power = 0x2f; 3884 3885 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3886 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3887 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3888 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3889 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3890 3891 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3892 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3893 /* init base power by eeprom target power */ 3894 target_power = rt2800_eeprom_read(rt2x00dev, 3895 EEPROM_TXPOWER_INIT); 3896 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3897 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3898 } 3899 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3900 3901 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3902 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3903 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3904 3905 /* Save MAC SYS CTRL registers */ 3906 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3907 /* Disable Tx/Rx */ 3908 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3909 /* Check MAC Tx/Rx idle */ 3910 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 3911 rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n"); 3912 3913 if (chan->center_freq > 2457) { 3914 bbp = rt2800_bbp_read(rt2x00dev, 30); 3915 bbp = 0x40; 3916 rt2800_bbp_write(rt2x00dev, 30, bbp); 3917 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3918 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3919 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3920 else 3921 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3922 } else { 3923 bbp = rt2800_bbp_read(rt2x00dev, 30); 3924 bbp = 0x1f; 3925 rt2800_bbp_write(rt2x00dev, 30, bbp); 3926 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3927 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3928 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3929 else 3930 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3931 } 3932 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3933 3934 rt2800_vco_calibration(rt2x00dev); 3935 } 3936 3937 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3938 const unsigned int word, 3939 const u8 value) 3940 { 3941 u8 chain, reg; 3942 3943 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3944 reg = rt2800_bbp_read(rt2x00dev, 27); 3945 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3946 rt2800_bbp_write(rt2x00dev, 27, reg); 3947 3948 rt2800_bbp_write(rt2x00dev, word, value); 3949 } 3950 } 3951 3952 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3953 { 3954 u8 cal; 3955 3956 /* TX0 IQ Gain */ 3957 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3958 if (channel <= 14) 3959 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3960 else if (channel >= 36 && channel <= 64) 3961 cal = rt2x00_eeprom_byte(rt2x00dev, 3962 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3963 else if (channel >= 100 && channel <= 138) 3964 cal = rt2x00_eeprom_byte(rt2x00dev, 3965 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3966 else if (channel >= 140 && channel <= 165) 3967 cal = rt2x00_eeprom_byte(rt2x00dev, 3968 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3969 else 3970 cal = 0; 3971 rt2800_bbp_write(rt2x00dev, 159, cal); 3972 3973 /* TX0 IQ Phase */ 3974 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3975 if (channel <= 14) 3976 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3977 else if (channel >= 36 && channel <= 64) 3978 cal = rt2x00_eeprom_byte(rt2x00dev, 3979 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3980 else if (channel >= 100 && channel <= 138) 3981 cal = rt2x00_eeprom_byte(rt2x00dev, 3982 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3983 else if (channel >= 140 && channel <= 165) 3984 cal = rt2x00_eeprom_byte(rt2x00dev, 3985 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3986 else 3987 cal = 0; 3988 rt2800_bbp_write(rt2x00dev, 159, cal); 3989 3990 /* TX1 IQ Gain */ 3991 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3992 if (channel <= 14) 3993 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3994 else if (channel >= 36 && channel <= 64) 3995 cal = rt2x00_eeprom_byte(rt2x00dev, 3996 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3997 else if (channel >= 100 && channel <= 138) 3998 cal = rt2x00_eeprom_byte(rt2x00dev, 3999 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 4000 else if (channel >= 140 && channel <= 165) 4001 cal = rt2x00_eeprom_byte(rt2x00dev, 4002 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 4003 else 4004 cal = 0; 4005 rt2800_bbp_write(rt2x00dev, 159, cal); 4006 4007 /* TX1 IQ Phase */ 4008 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 4009 if (channel <= 14) 4010 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 4011 else if (channel >= 36 && channel <= 64) 4012 cal = rt2x00_eeprom_byte(rt2x00dev, 4013 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 4014 else if (channel >= 100 && channel <= 138) 4015 cal = rt2x00_eeprom_byte(rt2x00dev, 4016 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 4017 else if (channel >= 140 && channel <= 165) 4018 cal = rt2x00_eeprom_byte(rt2x00dev, 4019 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 4020 else 4021 cal = 0; 4022 rt2800_bbp_write(rt2x00dev, 159, cal); 4023 4024 /* FIXME: possible RX0, RX1 callibration ? */ 4025 4026 /* RF IQ compensation control */ 4027 rt2800_bbp_write(rt2x00dev, 158, 0x04); 4028 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 4029 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4030 4031 /* RF IQ imbalance compensation control */ 4032 rt2800_bbp_write(rt2x00dev, 158, 0x03); 4033 cal = rt2x00_eeprom_byte(rt2x00dev, 4034 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 4035 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4036 } 4037 4038 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 4039 unsigned int channel, 4040 char txpower) 4041 { 4042 if (rt2x00_rt(rt2x00dev, RT3593) || 4043 rt2x00_rt(rt2x00dev, RT3883)) 4044 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 4045 4046 if (channel <= 14) 4047 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 4048 4049 if (rt2x00_rt(rt2x00dev, RT3593) || 4050 rt2x00_rt(rt2x00dev, RT3883)) 4051 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 4052 MAX_A_TXPOWER_3593); 4053 else 4054 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 4055 } 4056 4057 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev, 4058 struct rf_channel *rf) 4059 { 4060 u8 bbp; 4061 4062 bbp = (rf->channel > 14) ? 0x48 : 0x38; 4063 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 4064 4065 rt2800_bbp_write(rt2x00dev, 69, 0x12); 4066 4067 if (rf->channel <= 14) { 4068 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4069 } else { 4070 /* Disable CCK packet detection */ 4071 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4072 } 4073 4074 rt2800_bbp_write(rt2x00dev, 73, 0x10); 4075 4076 if (rf->channel > 14) { 4077 rt2800_bbp_write(rt2x00dev, 62, 0x1d); 4078 rt2800_bbp_write(rt2x00dev, 63, 0x1d); 4079 rt2800_bbp_write(rt2x00dev, 64, 0x1d); 4080 } else { 4081 rt2800_bbp_write(rt2x00dev, 62, 0x2d); 4082 rt2800_bbp_write(rt2x00dev, 63, 0x2d); 4083 rt2800_bbp_write(rt2x00dev, 64, 0x2d); 4084 } 4085 } 4086 4087 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 4088 struct ieee80211_conf *conf, 4089 struct rf_channel *rf, 4090 struct channel_info *info) 4091 { 4092 u32 reg; 4093 u32 tx_pin; 4094 u8 bbp, rfcsr; 4095 4096 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4097 info->default_power1); 4098 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4099 info->default_power2); 4100 if (rt2x00dev->default_ant.tx_chain_num > 2) 4101 info->default_power3 = 4102 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4103 info->default_power3); 4104 4105 switch (rt2x00dev->chip.rt) { 4106 case RT3883: 4107 rt3883_bbp_adjust(rt2x00dev, rf); 4108 break; 4109 } 4110 4111 switch (rt2x00dev->chip.rf) { 4112 case RF2020: 4113 case RF3020: 4114 case RF3021: 4115 case RF3022: 4116 case RF3320: 4117 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 4118 break; 4119 case RF3052: 4120 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 4121 break; 4122 case RF3053: 4123 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 4124 break; 4125 case RF3290: 4126 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 4127 break; 4128 case RF3322: 4129 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 4130 break; 4131 case RF3853: 4132 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info); 4133 break; 4134 case RF3070: 4135 case RF5350: 4136 case RF5360: 4137 case RF5362: 4138 case RF5370: 4139 case RF5372: 4140 case RF5390: 4141 case RF5392: 4142 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 4143 break; 4144 case RF5592: 4145 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 4146 break; 4147 case RF7620: 4148 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 4149 break; 4150 default: 4151 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 4152 } 4153 4154 if (rt2x00_rf(rt2x00dev, RF3070) || 4155 rt2x00_rf(rt2x00dev, RF3290) || 4156 rt2x00_rf(rt2x00dev, RF3322) || 4157 rt2x00_rf(rt2x00dev, RF5350) || 4158 rt2x00_rf(rt2x00dev, RF5360) || 4159 rt2x00_rf(rt2x00dev, RF5362) || 4160 rt2x00_rf(rt2x00dev, RF5370) || 4161 rt2x00_rf(rt2x00dev, RF5372) || 4162 rt2x00_rf(rt2x00dev, RF5390) || 4163 rt2x00_rf(rt2x00dev, RF5392)) { 4164 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 4165 if (rt2x00_rf(rt2x00dev, RF3322)) { 4166 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 4167 conf_is_ht40(conf)); 4168 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 4169 conf_is_ht40(conf)); 4170 } else { 4171 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 4172 conf_is_ht40(conf)); 4173 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 4174 conf_is_ht40(conf)); 4175 } 4176 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 4177 4178 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4179 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4180 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4181 } 4182 4183 /* 4184 * Change BBP settings 4185 */ 4186 4187 if (rt2x00_rt(rt2x00dev, RT3352)) { 4188 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4189 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4190 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4191 4192 rt2800_bbp_write(rt2x00dev, 27, 0x0); 4193 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4194 rt2800_bbp_write(rt2x00dev, 27, 0x20); 4195 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4196 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4197 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 4198 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4199 if (rf->channel > 14) { 4200 /* Disable CCK Packet detection on 5GHz */ 4201 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4202 } else { 4203 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4204 } 4205 4206 if (conf_is_ht40(conf)) 4207 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4208 else 4209 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4210 4211 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4212 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4213 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4214 rt2800_bbp_write(rt2x00dev, 77, 0x98); 4215 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 4216 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4217 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4218 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4219 4220 if (rt2x00dev->default_ant.rx_chain_num > 1) 4221 rt2800_bbp_write(rt2x00dev, 86, 0x46); 4222 else 4223 rt2800_bbp_write(rt2x00dev, 86, 0); 4224 } else { 4225 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4226 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4227 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4228 rt2800_bbp_write(rt2x00dev, 86, 0); 4229 } 4230 4231 if (rf->channel <= 14) { 4232 if (!rt2x00_rt(rt2x00dev, RT5390) && 4233 !rt2x00_rt(rt2x00dev, RT5392) && 4234 !rt2x00_rt(rt2x00dev, RT6352)) { 4235 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4236 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4237 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4238 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4239 } else { 4240 if (rt2x00_rt(rt2x00dev, RT3593)) 4241 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4242 else 4243 rt2800_bbp_write(rt2x00dev, 82, 0x84); 4244 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4245 } 4246 if (rt2x00_rt(rt2x00dev, RT3593) || 4247 rt2x00_rt(rt2x00dev, RT3883)) 4248 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 4249 } 4250 4251 } else { 4252 if (rt2x00_rt(rt2x00dev, RT3572)) 4253 rt2800_bbp_write(rt2x00dev, 82, 0x94); 4254 else if (rt2x00_rt(rt2x00dev, RT3593) || 4255 rt2x00_rt(rt2x00dev, RT3883)) 4256 rt2800_bbp_write(rt2x00dev, 82, 0x82); 4257 else if (!rt2x00_rt(rt2x00dev, RT6352)) 4258 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 4259 4260 if (rt2x00_rt(rt2x00dev, RT3593) || 4261 rt2x00_rt(rt2x00dev, RT3883)) 4262 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 4263 4264 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 4265 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4266 else 4267 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4268 } 4269 4270 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 4271 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 4272 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 4273 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 4274 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 4275 4276 if (rt2x00_rt(rt2x00dev, RT3572)) 4277 rt2800_rfcsr_write(rt2x00dev, 8, 0); 4278 4279 if (rt2x00_rt(rt2x00dev, RT6352)) { 4280 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4281 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 4282 } else { 4283 tx_pin = 0; 4284 } 4285 4286 switch (rt2x00dev->default_ant.tx_chain_num) { 4287 case 3: 4288 /* Turn on tertiary PAs */ 4289 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 4290 rf->channel > 14); 4291 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 4292 rf->channel <= 14); 4293 fallthrough; 4294 case 2: 4295 /* Turn on secondary PAs */ 4296 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 4297 rf->channel > 14); 4298 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 4299 rf->channel <= 14); 4300 fallthrough; 4301 case 1: 4302 /* Turn on primary PAs */ 4303 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 4304 rf->channel > 14); 4305 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 4306 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4307 else 4308 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 4309 rf->channel <= 14); 4310 break; 4311 } 4312 4313 switch (rt2x00dev->default_ant.rx_chain_num) { 4314 case 3: 4315 /* Turn on tertiary LNAs */ 4316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 4317 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 4318 fallthrough; 4319 case 2: 4320 /* Turn on secondary LNAs */ 4321 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 4322 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 4323 fallthrough; 4324 case 1: 4325 /* Turn on primary LNAs */ 4326 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 4327 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 4328 break; 4329 } 4330 4331 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 4332 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 4333 4334 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4335 4336 if (rt2x00_rt(rt2x00dev, RT3572)) { 4337 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 4338 4339 /* AGC init */ 4340 if (rf->channel <= 14) 4341 reg = 0x1c + (2 * rt2x00dev->lna_gain); 4342 else 4343 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4344 4345 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4346 } 4347 4348 if (rt2x00_rt(rt2x00dev, RT3593)) { 4349 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 4350 4351 /* Band selection */ 4352 if (rt2x00_is_usb(rt2x00dev) || 4353 rt2x00_is_pcie(rt2x00dev)) { 4354 /* GPIO #8 controls all paths */ 4355 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 4356 if (rf->channel <= 14) 4357 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 4358 else 4359 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 4360 } 4361 4362 /* LNA PE control. */ 4363 if (rt2x00_is_usb(rt2x00dev)) { 4364 /* GPIO #4 controls PE0 and PE1, 4365 * GPIO #7 controls PE2 4366 */ 4367 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4368 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 4369 4370 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4371 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 4372 } else if (rt2x00_is_pcie(rt2x00dev)) { 4373 /* GPIO #4 controls PE0, PE1 and PE2 */ 4374 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4375 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4376 } 4377 4378 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 4379 4380 /* AGC init */ 4381 if (rf->channel <= 14) 4382 reg = 0x1c + 2 * rt2x00dev->lna_gain; 4383 else 4384 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4385 4386 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4387 4388 usleep_range(1000, 1500); 4389 } 4390 4391 if (rt2x00_rt(rt2x00dev, RT3883)) { 4392 if (!conf_is_ht40(conf)) 4393 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4394 else 4395 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4396 4397 /* AGC init */ 4398 if (rf->channel <= 14) 4399 reg = 0x2e + rt2x00dev->lna_gain; 4400 else 4401 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); 4402 4403 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4404 4405 usleep_range(1000, 1500); 4406 } 4407 4408 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 4409 reg = 0x10; 4410 if (!conf_is_ht40(conf)) { 4411 if (rt2x00_rt(rt2x00dev, RT6352) && 4412 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4413 reg |= 0x5; 4414 } else { 4415 reg |= 0xa; 4416 } 4417 } 4418 rt2800_bbp_write(rt2x00dev, 195, 141); 4419 rt2800_bbp_write(rt2x00dev, 196, reg); 4420 4421 /* AGC init. 4422 * Despite the vendor driver using different values here for 4423 * RT6352 chip, we use 0x1c for now. This may have to be changed 4424 * once TSSI got implemented. 4425 */ 4426 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; 4427 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4428 4429 if (rt2x00_rt(rt2x00dev, RT5592)) 4430 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4431 } 4432 4433 if (rt2x00_rt(rt2x00dev, RT6352)) { 4434 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, 4435 &rt2x00dev->cap_flags)) { 4436 reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); 4437 reg |= 0x00000101; 4438 rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); 4439 4440 reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); 4441 reg |= 0x00000101; 4442 rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); 4443 4444 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73); 4445 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73); 4446 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73); 4447 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 4448 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8); 4449 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4); 4450 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05); 4451 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 4452 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8); 4453 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4); 4454 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05); 4455 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27); 4456 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8); 4457 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4); 4458 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05); 4459 rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00); 4460 4461 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 4462 0x36303636); 4463 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 4464 0x6C6C6B6C); 4465 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 4466 0x6C6C6B6C); 4467 } 4468 } 4469 4470 bbp = rt2800_bbp_read(rt2x00dev, 4); 4471 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4472 rt2800_bbp_write(rt2x00dev, 4, bbp); 4473 4474 bbp = rt2800_bbp_read(rt2x00dev, 3); 4475 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4476 rt2800_bbp_write(rt2x00dev, 3, bbp); 4477 4478 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4479 if (conf_is_ht40(conf)) { 4480 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4481 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4482 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4483 } else { 4484 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4485 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4486 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4487 } 4488 } 4489 4490 usleep_range(1000, 1500); 4491 4492 /* 4493 * Clear channel statistic counters 4494 */ 4495 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4496 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4497 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4498 4499 /* 4500 * Clear update flag 4501 */ 4502 if (rt2x00_rt(rt2x00dev, RT3352) || 4503 rt2x00_rt(rt2x00dev, RT5350)) { 4504 bbp = rt2800_bbp_read(rt2x00dev, 49); 4505 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4506 rt2800_bbp_write(rt2x00dev, 49, bbp); 4507 } 4508 } 4509 4510 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4511 { 4512 u8 tssi_bounds[9]; 4513 u8 current_tssi; 4514 u16 eeprom; 4515 u8 step; 4516 int i; 4517 4518 /* 4519 * First check if temperature compensation is supported. 4520 */ 4521 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4522 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4523 return 0; 4524 4525 /* 4526 * Read TSSI boundaries for temperature compensation from 4527 * the EEPROM. 4528 * 4529 * Array idx 0 1 2 3 4 5 6 7 8 4530 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4531 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4532 */ 4533 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4534 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4535 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4536 EEPROM_TSSI_BOUND_BG1_MINUS4); 4537 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4538 EEPROM_TSSI_BOUND_BG1_MINUS3); 4539 4540 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4541 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4542 EEPROM_TSSI_BOUND_BG2_MINUS2); 4543 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4544 EEPROM_TSSI_BOUND_BG2_MINUS1); 4545 4546 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4547 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4548 EEPROM_TSSI_BOUND_BG3_REF); 4549 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4550 EEPROM_TSSI_BOUND_BG3_PLUS1); 4551 4552 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4553 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4554 EEPROM_TSSI_BOUND_BG4_PLUS2); 4555 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4556 EEPROM_TSSI_BOUND_BG4_PLUS3); 4557 4558 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4559 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4560 EEPROM_TSSI_BOUND_BG5_PLUS4); 4561 4562 step = rt2x00_get_field16(eeprom, 4563 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4564 } else { 4565 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4566 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4567 EEPROM_TSSI_BOUND_A1_MINUS4); 4568 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4569 EEPROM_TSSI_BOUND_A1_MINUS3); 4570 4571 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4572 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4573 EEPROM_TSSI_BOUND_A2_MINUS2); 4574 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4575 EEPROM_TSSI_BOUND_A2_MINUS1); 4576 4577 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4578 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4579 EEPROM_TSSI_BOUND_A3_REF); 4580 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4581 EEPROM_TSSI_BOUND_A3_PLUS1); 4582 4583 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4584 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4585 EEPROM_TSSI_BOUND_A4_PLUS2); 4586 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4587 EEPROM_TSSI_BOUND_A4_PLUS3); 4588 4589 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4590 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4591 EEPROM_TSSI_BOUND_A5_PLUS4); 4592 4593 step = rt2x00_get_field16(eeprom, 4594 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4595 } 4596 4597 /* 4598 * Check if temperature compensation is supported. 4599 */ 4600 if (tssi_bounds[4] == 0xff || step == 0xff) 4601 return 0; 4602 4603 /* 4604 * Read current TSSI (BBP 49). 4605 */ 4606 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4607 4608 /* 4609 * Compare TSSI value (BBP49) with the compensation boundaries 4610 * from the EEPROM and increase or decrease tx power. 4611 */ 4612 for (i = 0; i <= 3; i++) { 4613 if (current_tssi > tssi_bounds[i]) 4614 break; 4615 } 4616 4617 if (i == 4) { 4618 for (i = 8; i >= 5; i--) { 4619 if (current_tssi < tssi_bounds[i]) 4620 break; 4621 } 4622 } 4623 4624 return (i - 4) * step; 4625 } 4626 4627 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4628 enum nl80211_band band) 4629 { 4630 u16 eeprom; 4631 u8 comp_en; 4632 u8 comp_type; 4633 int comp_value = 0; 4634 4635 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4636 4637 /* 4638 * HT40 compensation not required. 4639 */ 4640 if (eeprom == 0xffff || 4641 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4642 return 0; 4643 4644 if (band == NL80211_BAND_2GHZ) { 4645 comp_en = rt2x00_get_field16(eeprom, 4646 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4647 if (comp_en) { 4648 comp_type = rt2x00_get_field16(eeprom, 4649 EEPROM_TXPOWER_DELTA_TYPE_2G); 4650 comp_value = rt2x00_get_field16(eeprom, 4651 EEPROM_TXPOWER_DELTA_VALUE_2G); 4652 if (!comp_type) 4653 comp_value = -comp_value; 4654 } 4655 } else { 4656 comp_en = rt2x00_get_field16(eeprom, 4657 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4658 if (comp_en) { 4659 comp_type = rt2x00_get_field16(eeprom, 4660 EEPROM_TXPOWER_DELTA_TYPE_5G); 4661 comp_value = rt2x00_get_field16(eeprom, 4662 EEPROM_TXPOWER_DELTA_VALUE_5G); 4663 if (!comp_type) 4664 comp_value = -comp_value; 4665 } 4666 } 4667 4668 return comp_value; 4669 } 4670 4671 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4672 int power_level, int max_power) 4673 { 4674 int delta; 4675 4676 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4677 return 0; 4678 4679 /* 4680 * XXX: We don't know the maximum transmit power of our hardware since 4681 * the EEPROM doesn't expose it. We only know that we are calibrated 4682 * to 100% tx power. 4683 * 4684 * Hence, we assume the regulatory limit that cfg80211 calulated for 4685 * the current channel is our maximum and if we are requested to lower 4686 * the value we just reduce our tx power accordingly. 4687 */ 4688 delta = power_level - max_power; 4689 return min(delta, 0); 4690 } 4691 4692 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4693 enum nl80211_band band, int power_level, 4694 u8 txpower, int delta) 4695 { 4696 u16 eeprom; 4697 u8 criterion; 4698 u8 eirp_txpower; 4699 u8 eirp_txpower_criterion; 4700 u8 reg_limit; 4701 4702 if (rt2x00_rt(rt2x00dev, RT3593)) 4703 return min_t(u8, txpower, 0xc); 4704 4705 if (rt2x00_rt(rt2x00dev, RT3883)) 4706 return min_t(u8, txpower, 0xf); 4707 4708 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4709 /* 4710 * Check if eirp txpower exceed txpower_limit. 4711 * We use OFDM 6M as criterion and its eirp txpower 4712 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4713 * .11b data rate need add additional 4dbm 4714 * when calculating eirp txpower. 4715 */ 4716 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4717 EEPROM_TXPOWER_BYRATE, 4718 1); 4719 criterion = rt2x00_get_field16(eeprom, 4720 EEPROM_TXPOWER_BYRATE_RATE0); 4721 4722 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4723 4724 if (band == NL80211_BAND_2GHZ) 4725 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4726 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4727 else 4728 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4729 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4730 4731 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4732 (is_rate_b ? 4 : 0) + delta; 4733 4734 reg_limit = (eirp_txpower > power_level) ? 4735 (eirp_txpower - power_level) : 0; 4736 } else 4737 reg_limit = 0; 4738 4739 txpower = max(0, txpower + delta - reg_limit); 4740 return min_t(u8, txpower, 0xc); 4741 } 4742 4743 4744 enum { 4745 TX_PWR_CFG_0_IDX, 4746 TX_PWR_CFG_1_IDX, 4747 TX_PWR_CFG_2_IDX, 4748 TX_PWR_CFG_3_IDX, 4749 TX_PWR_CFG_4_IDX, 4750 TX_PWR_CFG_5_IDX, 4751 TX_PWR_CFG_6_IDX, 4752 TX_PWR_CFG_7_IDX, 4753 TX_PWR_CFG_8_IDX, 4754 TX_PWR_CFG_9_IDX, 4755 TX_PWR_CFG_0_EXT_IDX, 4756 TX_PWR_CFG_1_EXT_IDX, 4757 TX_PWR_CFG_2_EXT_IDX, 4758 TX_PWR_CFG_3_EXT_IDX, 4759 TX_PWR_CFG_4_EXT_IDX, 4760 TX_PWR_CFG_IDX_COUNT, 4761 }; 4762 4763 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4764 struct ieee80211_channel *chan, 4765 int power_level) 4766 { 4767 u8 txpower; 4768 u16 eeprom; 4769 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4770 unsigned int offset; 4771 enum nl80211_band band = chan->band; 4772 int delta; 4773 int i; 4774 4775 memset(regs, '\0', sizeof(regs)); 4776 4777 /* TODO: adapt TX power reduction from the rt28xx code */ 4778 4779 /* calculate temperature compensation delta */ 4780 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4781 4782 if (band == NL80211_BAND_5GHZ) 4783 offset = 16; 4784 else 4785 offset = 0; 4786 4787 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4788 offset += 8; 4789 4790 /* read the next four txpower values */ 4791 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4792 offset); 4793 4794 /* CCK 1MBS,2MBS */ 4795 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4796 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4797 txpower, delta); 4798 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4799 TX_PWR_CFG_0_CCK1_CH0, txpower); 4800 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4801 TX_PWR_CFG_0_CCK1_CH1, txpower); 4802 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4803 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4804 4805 /* CCK 5.5MBS,11MBS */ 4806 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4807 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4808 txpower, delta); 4809 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4810 TX_PWR_CFG_0_CCK5_CH0, txpower); 4811 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4812 TX_PWR_CFG_0_CCK5_CH1, txpower); 4813 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4814 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4815 4816 /* OFDM 6MBS,9MBS */ 4817 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4818 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4819 txpower, delta); 4820 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4821 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4822 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4823 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4824 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4825 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4826 4827 /* OFDM 12MBS,18MBS */ 4828 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4829 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4830 txpower, delta); 4831 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4832 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4833 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4834 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4835 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4836 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4837 4838 /* read the next four txpower values */ 4839 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4840 offset + 1); 4841 4842 /* OFDM 24MBS,36MBS */ 4843 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4844 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4845 txpower, delta); 4846 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4847 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4848 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4849 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4850 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4851 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4852 4853 /* OFDM 48MBS */ 4854 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4855 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4856 txpower, delta); 4857 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4858 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4859 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4860 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4861 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4862 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4863 4864 /* OFDM 54MBS */ 4865 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4866 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4867 txpower, delta); 4868 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4869 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4870 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4871 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4872 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4873 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4874 4875 /* read the next four txpower values */ 4876 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4877 offset + 2); 4878 4879 /* MCS 0,1 */ 4880 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4881 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4882 txpower, delta); 4883 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4884 TX_PWR_CFG_1_MCS0_CH0, txpower); 4885 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4886 TX_PWR_CFG_1_MCS0_CH1, txpower); 4887 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4888 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4889 4890 /* MCS 2,3 */ 4891 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4892 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4893 txpower, delta); 4894 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4895 TX_PWR_CFG_1_MCS2_CH0, txpower); 4896 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4897 TX_PWR_CFG_1_MCS2_CH1, txpower); 4898 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4899 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4900 4901 /* MCS 4,5 */ 4902 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4903 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4904 txpower, delta); 4905 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4906 TX_PWR_CFG_2_MCS4_CH0, txpower); 4907 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4908 TX_PWR_CFG_2_MCS4_CH1, txpower); 4909 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4910 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4911 4912 /* MCS 6 */ 4913 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4914 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4915 txpower, delta); 4916 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4917 TX_PWR_CFG_2_MCS6_CH0, txpower); 4918 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4919 TX_PWR_CFG_2_MCS6_CH1, txpower); 4920 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4921 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4922 4923 /* read the next four txpower values */ 4924 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4925 offset + 3); 4926 4927 /* MCS 7 */ 4928 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4929 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4930 txpower, delta); 4931 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4932 TX_PWR_CFG_7_MCS7_CH0, txpower); 4933 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4934 TX_PWR_CFG_7_MCS7_CH1, txpower); 4935 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4936 TX_PWR_CFG_7_MCS7_CH2, txpower); 4937 4938 /* MCS 8,9 */ 4939 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4940 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4941 txpower, delta); 4942 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4943 TX_PWR_CFG_2_MCS8_CH0, txpower); 4944 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4945 TX_PWR_CFG_2_MCS8_CH1, txpower); 4946 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4947 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4948 4949 /* MCS 10,11 */ 4950 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4951 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4952 txpower, delta); 4953 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4954 TX_PWR_CFG_2_MCS10_CH0, txpower); 4955 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4956 TX_PWR_CFG_2_MCS10_CH1, txpower); 4957 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4958 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4959 4960 /* MCS 12,13 */ 4961 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4962 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4963 txpower, delta); 4964 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4965 TX_PWR_CFG_3_MCS12_CH0, txpower); 4966 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4967 TX_PWR_CFG_3_MCS12_CH1, txpower); 4968 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4969 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4970 4971 /* read the next four txpower values */ 4972 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4973 offset + 4); 4974 4975 /* MCS 14 */ 4976 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4977 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4978 txpower, delta); 4979 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4980 TX_PWR_CFG_3_MCS14_CH0, txpower); 4981 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4982 TX_PWR_CFG_3_MCS14_CH1, txpower); 4983 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4984 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4985 4986 /* MCS 15 */ 4987 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4988 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4989 txpower, delta); 4990 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4991 TX_PWR_CFG_8_MCS15_CH0, txpower); 4992 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4993 TX_PWR_CFG_8_MCS15_CH1, txpower); 4994 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4995 TX_PWR_CFG_8_MCS15_CH2, txpower); 4996 4997 /* MCS 16,17 */ 4998 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4999 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5000 txpower, delta); 5001 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5002 TX_PWR_CFG_5_MCS16_CH0, txpower); 5003 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5004 TX_PWR_CFG_5_MCS16_CH1, txpower); 5005 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5006 TX_PWR_CFG_5_MCS16_CH2, txpower); 5007 5008 /* MCS 18,19 */ 5009 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5010 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5011 txpower, delta); 5012 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5013 TX_PWR_CFG_5_MCS18_CH0, txpower); 5014 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5015 TX_PWR_CFG_5_MCS18_CH1, txpower); 5016 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5017 TX_PWR_CFG_5_MCS18_CH2, txpower); 5018 5019 /* read the next four txpower values */ 5020 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5021 offset + 5); 5022 5023 /* MCS 20,21 */ 5024 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5025 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5026 txpower, delta); 5027 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5028 TX_PWR_CFG_6_MCS20_CH0, txpower); 5029 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5030 TX_PWR_CFG_6_MCS20_CH1, txpower); 5031 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5032 TX_PWR_CFG_6_MCS20_CH2, txpower); 5033 5034 /* MCS 22 */ 5035 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5036 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5037 txpower, delta); 5038 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5039 TX_PWR_CFG_6_MCS22_CH0, txpower); 5040 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5041 TX_PWR_CFG_6_MCS22_CH1, txpower); 5042 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5043 TX_PWR_CFG_6_MCS22_CH2, txpower); 5044 5045 /* MCS 23 */ 5046 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5047 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5048 txpower, delta); 5049 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5050 TX_PWR_CFG_8_MCS23_CH0, txpower); 5051 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5052 TX_PWR_CFG_8_MCS23_CH1, txpower); 5053 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5054 TX_PWR_CFG_8_MCS23_CH2, txpower); 5055 5056 /* read the next four txpower values */ 5057 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5058 offset + 6); 5059 5060 /* STBC, MCS 0,1 */ 5061 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5062 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5063 txpower, delta); 5064 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5065 TX_PWR_CFG_3_STBC0_CH0, txpower); 5066 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5067 TX_PWR_CFG_3_STBC0_CH1, txpower); 5068 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5069 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 5070 5071 /* STBC, MCS 2,3 */ 5072 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5073 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5074 txpower, delta); 5075 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5076 TX_PWR_CFG_3_STBC2_CH0, txpower); 5077 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5078 TX_PWR_CFG_3_STBC2_CH1, txpower); 5079 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5080 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 5081 5082 /* STBC, MCS 4,5 */ 5083 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5084 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5085 txpower, delta); 5086 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 5087 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 5088 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 5089 txpower); 5090 5091 /* STBC, MCS 6 */ 5092 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5093 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5094 txpower, delta); 5095 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 5096 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 5097 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 5098 txpower); 5099 5100 /* read the next four txpower values */ 5101 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5102 offset + 7); 5103 5104 /* STBC, MCS 7 */ 5105 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5106 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5107 txpower, delta); 5108 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5109 TX_PWR_CFG_9_STBC7_CH0, txpower); 5110 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5111 TX_PWR_CFG_9_STBC7_CH1, txpower); 5112 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5113 TX_PWR_CFG_9_STBC7_CH2, txpower); 5114 5115 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 5116 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 5117 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 5118 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 5119 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 5120 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 5121 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 5122 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 5123 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 5124 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 5125 5126 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 5127 regs[TX_PWR_CFG_0_EXT_IDX]); 5128 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 5129 regs[TX_PWR_CFG_1_EXT_IDX]); 5130 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 5131 regs[TX_PWR_CFG_2_EXT_IDX]); 5132 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 5133 regs[TX_PWR_CFG_3_EXT_IDX]); 5134 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 5135 regs[TX_PWR_CFG_4_EXT_IDX]); 5136 5137 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 5138 rt2x00_dbg(rt2x00dev, 5139 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 5140 (band == NL80211_BAND_5GHZ) ? '5' : '2', 5141 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 5142 '4' : '2', 5143 (i > TX_PWR_CFG_9_IDX) ? 5144 (i - TX_PWR_CFG_9_IDX - 1) : i, 5145 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 5146 (unsigned long) regs[i]); 5147 } 5148 5149 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 5150 struct ieee80211_channel *chan, 5151 int power_level) 5152 { 5153 u32 reg, pwreg; 5154 u16 eeprom; 5155 u32 data, gdata; 5156 u8 t, i; 5157 enum nl80211_band band = chan->band; 5158 int delta; 5159 5160 /* Warn user if bw_comp is set in EEPROM */ 5161 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5162 5163 if (delta) 5164 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 5165 delta); 5166 5167 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 5168 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 5169 * driver does as well, though it looks kinda wrong. 5170 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 5171 * the hardware has a problem handling 0x20, and as the code initially 5172 * used a fixed offset between HT20 and HT40 rates they had to work- 5173 * around that issue and most likely just forgot about it later on. 5174 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 5175 * however, the corresponding EEPROM value is not respected by the 5176 * vendor driver, so maybe this is rather being taken care of the 5177 * TXALC and the driver doesn't need to handle it...? 5178 * Though this is all very awkward, just do as they did, as that's what 5179 * board vendors expected when they populated the EEPROM... 5180 */ 5181 for (i = 0; i < 5; i++) { 5182 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5183 EEPROM_TXPOWER_BYRATE, 5184 i * 2); 5185 5186 data = eeprom; 5187 5188 t = eeprom & 0x3f; 5189 if (t == 32) 5190 t++; 5191 5192 gdata = t; 5193 5194 t = (eeprom & 0x3f00) >> 8; 5195 if (t == 32) 5196 t++; 5197 5198 gdata |= (t << 8); 5199 5200 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5201 EEPROM_TXPOWER_BYRATE, 5202 (i * 2) + 1); 5203 5204 t = eeprom & 0x3f; 5205 if (t == 32) 5206 t++; 5207 5208 gdata |= (t << 16); 5209 5210 t = (eeprom & 0x3f00) >> 8; 5211 if (t == 32) 5212 t++; 5213 5214 gdata |= (t << 24); 5215 data |= (eeprom << 16); 5216 5217 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 5218 /* HT20 */ 5219 if (data != 0xffffffff) 5220 rt2800_register_write(rt2x00dev, 5221 TX_PWR_CFG_0 + (i * 4), 5222 data); 5223 } else { 5224 /* HT40 */ 5225 if (gdata != 0xffffffff) 5226 rt2800_register_write(rt2x00dev, 5227 TX_PWR_CFG_0 + (i * 4), 5228 gdata); 5229 } 5230 } 5231 5232 /* Aparently Ralink ran out of space in the BYRATE calibration section 5233 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 5234 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 5235 * power-offsets more space would be needed. Ralink decided to keep the 5236 * EEPROM layout untouched and rather have some shared values covering 5237 * multiple bitrates. 5238 * Populate the registers not covered by the EEPROM in the same way the 5239 * vendor driver does. 5240 */ 5241 5242 /* For OFDM 54MBS use value from OFDM 48MBS */ 5243 pwreg = 0; 5244 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 5245 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 5246 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 5247 5248 /* For MCS 7 use value from MCS 6 */ 5249 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 5250 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 5251 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 5252 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 5253 5254 /* For MCS 15 use value from MCS 14 */ 5255 pwreg = 0; 5256 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 5257 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 5258 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 5259 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 5260 5261 /* For STBC MCS 7 use value from STBC MCS 6 */ 5262 pwreg = 0; 5263 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 5264 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 5265 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 5266 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 5267 5268 rt2800_config_alc(rt2x00dev, chan, power_level); 5269 5270 /* TODO: temperature compensation code! */ 5271 } 5272 5273 /* 5274 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 5275 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 5276 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 5277 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 5278 * Reference per rate transmit power values are located in the EEPROM at 5279 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 5280 * current conditions (i.e. band, bandwidth, temperature, user settings). 5281 */ 5282 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 5283 struct ieee80211_channel *chan, 5284 int power_level) 5285 { 5286 u8 txpower, r1; 5287 u16 eeprom; 5288 u32 reg, offset; 5289 int i, is_rate_b, delta, power_ctrl; 5290 enum nl80211_band band = chan->band; 5291 5292 /* 5293 * Calculate HT40 compensation. For 40MHz we need to add or subtract 5294 * value read from EEPROM (different for 2GHz and for 5GHz). 5295 */ 5296 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5297 5298 /* 5299 * Calculate temperature compensation. Depends on measurement of current 5300 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 5301 * to temperature or maybe other factors) is smaller or bigger than 5302 * expected. We adjust it, based on TSSI reference and boundaries values 5303 * provided in EEPROM. 5304 */ 5305 switch (rt2x00dev->chip.rt) { 5306 case RT2860: 5307 case RT2872: 5308 case RT2883: 5309 case RT3070: 5310 case RT3071: 5311 case RT3090: 5312 case RT3572: 5313 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 5314 break; 5315 default: 5316 /* TODO: temperature compensation code for other chips. */ 5317 break; 5318 } 5319 5320 /* 5321 * Decrease power according to user settings, on devices with unknown 5322 * maximum tx power. For other devices we take user power_level into 5323 * consideration on rt2800_compensate_txpower(). 5324 */ 5325 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 5326 chan->max_power); 5327 5328 /* 5329 * BBP_R1 controls TX power for all rates, it allow to set the following 5330 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 5331 * 5332 * TODO: we do not use +6 dBm option to do not increase power beyond 5333 * regulatory limit, however this could be utilized for devices with 5334 * CAPABILITY_POWER_LIMIT. 5335 */ 5336 if (delta <= -12) { 5337 power_ctrl = 2; 5338 delta += 12; 5339 } else if (delta <= -6) { 5340 power_ctrl = 1; 5341 delta += 6; 5342 } else { 5343 power_ctrl = 0; 5344 } 5345 r1 = rt2800_bbp_read(rt2x00dev, 1); 5346 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 5347 rt2800_bbp_write(rt2x00dev, 1, r1); 5348 5349 offset = TX_PWR_CFG_0; 5350 5351 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 5352 /* just to be safe */ 5353 if (offset > TX_PWR_CFG_4) 5354 break; 5355 5356 reg = rt2800_register_read(rt2x00dev, offset); 5357 5358 /* read the next four txpower values */ 5359 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5360 EEPROM_TXPOWER_BYRATE, 5361 i); 5362 5363 is_rate_b = i ? 0 : 1; 5364 /* 5365 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 5366 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 5367 * TX_PWR_CFG_4: unknown 5368 */ 5369 txpower = rt2x00_get_field16(eeprom, 5370 EEPROM_TXPOWER_BYRATE_RATE0); 5371 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5372 power_level, txpower, delta); 5373 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 5374 5375 /* 5376 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 5377 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 5378 * TX_PWR_CFG_4: unknown 5379 */ 5380 txpower = rt2x00_get_field16(eeprom, 5381 EEPROM_TXPOWER_BYRATE_RATE1); 5382 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5383 power_level, txpower, delta); 5384 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 5385 5386 /* 5387 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 5388 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 5389 * TX_PWR_CFG_4: unknown 5390 */ 5391 txpower = rt2x00_get_field16(eeprom, 5392 EEPROM_TXPOWER_BYRATE_RATE2); 5393 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5394 power_level, txpower, delta); 5395 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 5396 5397 /* 5398 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 5399 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 5400 * TX_PWR_CFG_4: unknown 5401 */ 5402 txpower = rt2x00_get_field16(eeprom, 5403 EEPROM_TXPOWER_BYRATE_RATE3); 5404 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5405 power_level, txpower, delta); 5406 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 5407 5408 /* read the next four txpower values */ 5409 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5410 EEPROM_TXPOWER_BYRATE, 5411 i + 1); 5412 5413 is_rate_b = 0; 5414 /* 5415 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 5416 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 5417 * TX_PWR_CFG_4: unknown 5418 */ 5419 txpower = rt2x00_get_field16(eeprom, 5420 EEPROM_TXPOWER_BYRATE_RATE0); 5421 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5422 power_level, txpower, delta); 5423 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 5424 5425 /* 5426 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 5427 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 5428 * TX_PWR_CFG_4: unknown 5429 */ 5430 txpower = rt2x00_get_field16(eeprom, 5431 EEPROM_TXPOWER_BYRATE_RATE1); 5432 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5433 power_level, txpower, delta); 5434 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 5435 5436 /* 5437 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 5438 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 5439 * TX_PWR_CFG_4: unknown 5440 */ 5441 txpower = rt2x00_get_field16(eeprom, 5442 EEPROM_TXPOWER_BYRATE_RATE2); 5443 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5444 power_level, txpower, delta); 5445 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 5446 5447 /* 5448 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 5449 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 5450 * TX_PWR_CFG_4: unknown 5451 */ 5452 txpower = rt2x00_get_field16(eeprom, 5453 EEPROM_TXPOWER_BYRATE_RATE3); 5454 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5455 power_level, txpower, delta); 5456 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 5457 5458 rt2800_register_write(rt2x00dev, offset, reg); 5459 5460 /* next TX_PWR_CFG register */ 5461 offset += 4; 5462 } 5463 } 5464 5465 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5466 struct ieee80211_channel *chan, 5467 int power_level) 5468 { 5469 if (rt2x00_rt(rt2x00dev, RT3593) || 5470 rt2x00_rt(rt2x00dev, RT3883)) 5471 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5472 else if (rt2x00_rt(rt2x00dev, RT6352)) 5473 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5474 else 5475 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5476 } 5477 5478 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5479 { 5480 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5481 rt2x00dev->tx_power); 5482 } 5483 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5484 5485 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5486 { 5487 u32 tx_pin; 5488 u8 rfcsr; 5489 unsigned long min_sleep = 0; 5490 5491 /* 5492 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5493 * designed to be controlled in oscillation frequency by a voltage 5494 * input. Maybe the temperature will affect the frequency of 5495 * oscillation to be shifted. The VCO calibration will be called 5496 * periodically to adjust the frequency to be precision. 5497 */ 5498 5499 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5500 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5501 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5502 5503 switch (rt2x00dev->chip.rf) { 5504 case RF2020: 5505 case RF3020: 5506 case RF3021: 5507 case RF3022: 5508 case RF3320: 5509 case RF3052: 5510 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5511 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5512 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5513 break; 5514 case RF3053: 5515 case RF3070: 5516 case RF3290: 5517 case RF3853: 5518 case RF5350: 5519 case RF5360: 5520 case RF5362: 5521 case RF5370: 5522 case RF5372: 5523 case RF5390: 5524 case RF5392: 5525 case RF5592: 5526 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5527 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5528 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5529 min_sleep = 1000; 5530 break; 5531 case RF7620: 5532 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5533 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5534 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5535 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5536 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5537 min_sleep = 2000; 5538 break; 5539 default: 5540 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5541 rt2x00dev->chip.rf); 5542 return; 5543 } 5544 5545 if (min_sleep > 0) 5546 usleep_range(min_sleep, min_sleep * 2); 5547 5548 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5549 if (rt2x00dev->rf_channel <= 14) { 5550 switch (rt2x00dev->default_ant.tx_chain_num) { 5551 case 3: 5552 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5553 fallthrough; 5554 case 2: 5555 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5556 fallthrough; 5557 case 1: 5558 default: 5559 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5560 break; 5561 } 5562 } else { 5563 switch (rt2x00dev->default_ant.tx_chain_num) { 5564 case 3: 5565 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5566 fallthrough; 5567 case 2: 5568 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5569 fallthrough; 5570 case 1: 5571 default: 5572 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5573 break; 5574 } 5575 } 5576 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5577 5578 if (rt2x00_rt(rt2x00dev, RT6352)) { 5579 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5580 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5581 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5582 rt2800_bbp_write(rt2x00dev, 195, 128); 5583 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5584 rt2800_bbp_write(rt2x00dev, 195, 170); 5585 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5586 rt2800_bbp_write(rt2x00dev, 195, 171); 5587 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5588 } else { 5589 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5590 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5591 rt2800_bbp_write(rt2x00dev, 195, 128); 5592 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5593 rt2800_bbp_write(rt2x00dev, 195, 170); 5594 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5595 rt2800_bbp_write(rt2x00dev, 195, 171); 5596 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5597 } 5598 5599 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5600 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5601 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5602 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5603 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5604 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5605 } 5606 5607 /* On 11A, We should delay and wait RF/BBP to be stable 5608 * and the appropriate time should be 1000 micro seconds 5609 * 2005/06/05 - On 11G, we also need this delay time. 5610 * Otherwise it's difficult to pass the WHQL. 5611 */ 5612 usleep_range(1000, 1500); 5613 } 5614 } 5615 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5616 5617 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5618 struct rt2x00lib_conf *libconf) 5619 { 5620 u32 reg; 5621 5622 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5623 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5624 libconf->conf->short_frame_max_tx_count); 5625 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5626 libconf->conf->long_frame_max_tx_count); 5627 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5628 } 5629 5630 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5631 struct rt2x00lib_conf *libconf) 5632 { 5633 enum dev_state state = 5634 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5635 STATE_SLEEP : STATE_AWAKE; 5636 u32 reg; 5637 5638 if (state == STATE_SLEEP) { 5639 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5640 5641 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5642 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5643 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5644 libconf->conf->listen_interval - 1); 5645 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5646 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5647 5648 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5649 } else { 5650 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5651 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5652 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5653 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5654 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5655 5656 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5657 } 5658 } 5659 5660 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5661 struct rt2x00lib_conf *libconf, 5662 const unsigned int flags) 5663 { 5664 /* Always recalculate LNA gain before changing configuration */ 5665 rt2800_config_lna_gain(rt2x00dev, libconf); 5666 5667 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5668 /* 5669 * To provide correct survey data for survey-based ACS algorithm 5670 * we have to save survey data for current channel before switching. 5671 */ 5672 rt2800_update_survey(rt2x00dev); 5673 5674 rt2800_config_channel(rt2x00dev, libconf->conf, 5675 &libconf->rf, &libconf->channel); 5676 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5677 libconf->conf->power_level); 5678 } 5679 if (flags & IEEE80211_CONF_CHANGE_POWER) 5680 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5681 libconf->conf->power_level); 5682 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5683 rt2800_config_retry_limit(rt2x00dev, libconf); 5684 if (flags & IEEE80211_CONF_CHANGE_PS) 5685 rt2800_config_ps(rt2x00dev, libconf); 5686 } 5687 EXPORT_SYMBOL_GPL(rt2800_config); 5688 5689 /* 5690 * Link tuning 5691 */ 5692 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5693 { 5694 u32 reg; 5695 5696 /* 5697 * Update FCS error count from register. 5698 */ 5699 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5700 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5701 } 5702 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5703 5704 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5705 { 5706 u8 vgc; 5707 5708 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5709 if (rt2x00_rt(rt2x00dev, RT3070) || 5710 rt2x00_rt(rt2x00dev, RT3071) || 5711 rt2x00_rt(rt2x00dev, RT3090) || 5712 rt2x00_rt(rt2x00dev, RT3290) || 5713 rt2x00_rt(rt2x00dev, RT3390) || 5714 rt2x00_rt(rt2x00dev, RT3572) || 5715 rt2x00_rt(rt2x00dev, RT3593) || 5716 rt2x00_rt(rt2x00dev, RT5390) || 5717 rt2x00_rt(rt2x00dev, RT5392) || 5718 rt2x00_rt(rt2x00dev, RT5592) || 5719 rt2x00_rt(rt2x00dev, RT6352)) 5720 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5721 else 5722 vgc = 0x2e + rt2x00dev->lna_gain; 5723 } else { /* 5GHZ band */ 5724 if (rt2x00_rt(rt2x00dev, RT3593) || 5725 rt2x00_rt(rt2x00dev, RT3883)) 5726 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5727 else if (rt2x00_rt(rt2x00dev, RT5592)) 5728 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5729 else { 5730 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5731 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5732 else 5733 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5734 } 5735 } 5736 5737 return vgc; 5738 } 5739 5740 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5741 struct link_qual *qual, u8 vgc_level) 5742 { 5743 if (qual->vgc_level != vgc_level) { 5744 if (rt2x00_rt(rt2x00dev, RT3572) || 5745 rt2x00_rt(rt2x00dev, RT3593) || 5746 rt2x00_rt(rt2x00dev, RT3883)) { 5747 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5748 vgc_level); 5749 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5750 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5751 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5752 } else { 5753 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5754 } 5755 5756 qual->vgc_level = vgc_level; 5757 qual->vgc_level_reg = vgc_level; 5758 } 5759 } 5760 5761 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5762 { 5763 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5764 } 5765 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5766 5767 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5768 const u32 count) 5769 { 5770 u8 vgc; 5771 5772 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5773 return; 5774 5775 /* When RSSI is better than a certain threshold, increase VGC 5776 * with a chip specific value in order to improve the balance 5777 * between sensibility and noise isolation. 5778 */ 5779 5780 vgc = rt2800_get_default_vgc(rt2x00dev); 5781 5782 switch (rt2x00dev->chip.rt) { 5783 case RT3572: 5784 case RT3593: 5785 if (qual->rssi > -65) { 5786 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5787 vgc += 0x20; 5788 else 5789 vgc += 0x10; 5790 } 5791 break; 5792 5793 case RT3883: 5794 if (qual->rssi > -65) 5795 vgc += 0x10; 5796 break; 5797 5798 case RT5592: 5799 if (qual->rssi > -65) 5800 vgc += 0x20; 5801 break; 5802 5803 default: 5804 if (qual->rssi > -80) 5805 vgc += 0x10; 5806 break; 5807 } 5808 5809 rt2800_set_vgc(rt2x00dev, qual, vgc); 5810 } 5811 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5812 5813 /* 5814 * Initialization functions. 5815 */ 5816 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5817 { 5818 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5819 u32 reg; 5820 u16 eeprom; 5821 unsigned int i; 5822 int ret; 5823 5824 rt2800_disable_wpdma(rt2x00dev); 5825 5826 ret = rt2800_drv_init_registers(rt2x00dev); 5827 if (ret) 5828 return ret; 5829 5830 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5831 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5832 5833 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5834 5835 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5836 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5837 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5838 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5839 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5840 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5841 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5842 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5843 5844 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5845 5846 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5847 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5848 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5849 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5850 5851 if (rt2x00_rt(rt2x00dev, RT3290)) { 5852 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5853 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5854 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5855 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5856 } 5857 5858 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5859 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5860 rt2x00_set_field32(®, LDO0_EN, 1); 5861 rt2x00_set_field32(®, LDO_BGSEL, 3); 5862 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5863 } 5864 5865 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5866 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5867 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5868 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5869 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5870 5871 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5872 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5873 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5874 5875 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5876 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5877 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5878 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5879 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5880 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5881 5882 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5883 rt2x00_set_field32(®, PLL_CONTROL, 1); 5884 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5885 } 5886 5887 if (rt2x00_rt(rt2x00dev, RT3071) || 5888 rt2x00_rt(rt2x00dev, RT3090) || 5889 rt2x00_rt(rt2x00dev, RT3290) || 5890 rt2x00_rt(rt2x00dev, RT3390)) { 5891 5892 if (rt2x00_rt(rt2x00dev, RT3290)) 5893 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5894 0x00000404); 5895 else 5896 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5897 0x00000400); 5898 5899 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5900 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5901 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5902 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5903 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5904 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5905 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5906 0x0000002c); 5907 else 5908 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5909 0x0000000f); 5910 } else { 5911 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5912 } 5913 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5914 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5915 5916 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5917 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5918 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5919 } else { 5920 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5921 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5922 } 5923 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5924 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5925 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5926 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5927 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5928 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5929 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5930 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5931 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5932 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5933 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5934 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5935 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5936 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5937 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5938 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5939 if (rt2x00_get_field16(eeprom, 5940 EEPROM_NIC_CONF1_DAC_TEST)) 5941 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5942 0x0000001f); 5943 else 5944 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5945 0x0000000f); 5946 } else { 5947 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5948 0x00000000); 5949 } 5950 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5951 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5952 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5953 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); 5954 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); 5955 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); 5956 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5957 rt2x00_rt(rt2x00dev, RT5392)) { 5958 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5959 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5960 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5961 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5962 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5963 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5964 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5965 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5966 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5967 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5968 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5969 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001); 5970 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5971 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 5972 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5973 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5974 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5975 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5976 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5977 0x3630363A); 5978 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5979 0x3630363A); 5980 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5981 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5982 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5983 } else { 5984 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5985 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5986 } 5987 5988 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5989 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5990 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5991 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5992 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5993 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5994 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5995 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5996 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5997 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5998 5999 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 6000 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 6001 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 6002 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 6003 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 6004 6005 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 6006 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 6007 if (rt2x00_is_usb(rt2x00dev)) { 6008 drv_data->max_psdu = 3; 6009 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 6010 rt2x00_rt(rt2x00dev, RT2883) || 6011 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 6012 drv_data->max_psdu = 2; 6013 } else { 6014 drv_data->max_psdu = 1; 6015 } 6016 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 6017 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 6018 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 6019 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 6020 6021 reg = rt2800_register_read(rt2x00dev, LED_CFG); 6022 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 6023 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 6024 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 6025 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 6026 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 6027 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 6028 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 6029 rt2800_register_write(rt2x00dev, LED_CFG, reg); 6030 6031 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 6032 6033 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 6034 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 6035 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 6036 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 6037 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 6038 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 6039 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 6040 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 6041 6042 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 6043 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 6044 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 6045 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 6046 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 6047 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 6048 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 6049 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 6050 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 6051 6052 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 6053 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 6054 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 6055 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 6056 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6057 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6058 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6059 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6060 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6061 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6062 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 6063 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 6064 6065 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 6066 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 6067 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 6068 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 6069 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6070 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6071 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6072 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6073 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6074 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6075 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 6076 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 6077 6078 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 6079 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 6080 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 6081 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6082 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6083 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6084 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6085 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6086 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6087 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6088 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 6089 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 6090 6091 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 6092 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 6093 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 6094 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6095 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6096 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6097 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6098 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6099 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6100 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6101 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 6102 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 6103 6104 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 6105 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 6106 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 6107 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6108 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6109 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6110 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6111 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6112 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6113 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6114 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 6115 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 6116 6117 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 6118 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 6119 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 6120 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6121 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6122 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6123 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6124 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6125 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6126 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6127 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 6128 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 6129 6130 if (rt2x00_is_usb(rt2x00dev)) { 6131 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 6132 6133 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 6134 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 6135 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 6136 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 6137 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 6138 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 6139 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 6140 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 6141 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 6142 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 6143 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6144 } 6145 6146 /* 6147 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 6148 * although it is reserved. 6149 */ 6150 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 6151 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 6152 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 6153 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 6154 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 6155 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 6156 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 6157 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 6158 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 6159 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 6160 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 6161 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 6162 6163 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 6164 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 6165 6166 if (rt2x00_rt(rt2x00dev, RT3883)) { 6167 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); 6168 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); 6169 } 6170 6171 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 6172 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 6173 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 6174 IEEE80211_MAX_RTS_THRESHOLD); 6175 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 6176 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 6177 6178 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 6179 6180 /* 6181 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 6182 * time should be set to 16. However, the original Ralink driver uses 6183 * 16 for both and indeed using a value of 10 for CCK SIFS results in 6184 * connection problems with 11g + CTS protection. Hence, use the same 6185 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 6186 */ 6187 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 6188 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 6189 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 6190 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 6191 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 6192 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 6193 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 6194 6195 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 6196 6197 /* 6198 * ASIC will keep garbage value after boot, clear encryption keys. 6199 */ 6200 for (i = 0; i < 4; i++) 6201 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0); 6202 6203 for (i = 0; i < 256; i++) { 6204 rt2800_config_wcid(rt2x00dev, NULL, i); 6205 rt2800_delete_wcid_attr(rt2x00dev, i); 6206 } 6207 6208 /* 6209 * Clear encryption initialization vectors on start, but keep them 6210 * for watchdog reset. Otherwise we will have wrong IVs and not be 6211 * able to keep connections after reset. 6212 */ 6213 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 6214 for (i = 0; i < 256; i++) 6215 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 6216 6217 /* 6218 * Clear all beacons 6219 */ 6220 for (i = 0; i < 8; i++) 6221 rt2800_clear_beacon_register(rt2x00dev, i); 6222 6223 if (rt2x00_is_usb(rt2x00dev)) { 6224 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6225 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 6226 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6227 } else if (rt2x00_is_pcie(rt2x00dev)) { 6228 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6229 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 6230 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6231 } 6232 6233 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 6234 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 6235 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 6236 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 6237 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 6238 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 6239 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 6240 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 6241 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 6242 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 6243 6244 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 6245 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 6246 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 6247 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 6248 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 6249 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 6250 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 6251 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 6252 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 6253 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 6254 6255 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 6256 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 6257 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 6258 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 6259 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 6260 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 6261 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 6262 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 6263 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 6264 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 6265 6266 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 6267 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 6268 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 6269 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 6270 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 6271 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 6272 6273 /* 6274 * Do not force the BA window size, we use the TXWI to set it 6275 */ 6276 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 6277 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 6278 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 6279 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 6280 6281 /* 6282 * We must clear the error counters. 6283 * These registers are cleared on read, 6284 * so we may pass a useless variable to store the value. 6285 */ 6286 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 6287 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 6288 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 6289 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 6290 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 6291 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 6292 6293 /* 6294 * Setup leadtime for pre tbtt interrupt to 6ms 6295 */ 6296 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 6297 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 6298 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 6299 6300 /* 6301 * Set up channel statistics timer 6302 */ 6303 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 6304 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 6305 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 6306 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 6307 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 6308 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 6309 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 6310 6311 return 0; 6312 } 6313 6314 6315 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 6316 { 6317 u8 value; 6318 6319 value = rt2800_bbp_read(rt2x00dev, 4); 6320 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 6321 rt2800_bbp_write(rt2x00dev, 4, value); 6322 } 6323 6324 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 6325 { 6326 rt2800_bbp_write(rt2x00dev, 142, 1); 6327 rt2800_bbp_write(rt2x00dev, 143, 57); 6328 } 6329 6330 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 6331 { 6332 static const u8 glrt_table[] = { 6333 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 6334 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 6335 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 6336 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 6337 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 6338 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 6339 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 6340 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 6341 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 6342 }; 6343 int i; 6344 6345 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 6346 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 6347 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 6348 } 6349 }; 6350 6351 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 6352 { 6353 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6354 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6355 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 6356 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6357 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6358 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6359 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6360 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6361 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 6362 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6363 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6364 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6365 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6366 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6367 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6368 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6369 } 6370 6371 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 6372 { 6373 u16 eeprom; 6374 u8 value; 6375 6376 value = rt2800_bbp_read(rt2x00dev, 138); 6377 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6378 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6379 value |= 0x20; 6380 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6381 value &= ~0x02; 6382 rt2800_bbp_write(rt2x00dev, 138, value); 6383 } 6384 6385 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 6386 { 6387 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6388 6389 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6390 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6391 6392 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6393 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6394 6395 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6396 6397 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6398 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6399 6400 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6401 6402 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6403 6404 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6405 6406 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6407 6408 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6409 6410 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6411 6412 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6413 6414 rt2800_bbp_write(rt2x00dev, 105, 0x01); 6415 6416 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6417 } 6418 6419 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 6420 { 6421 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6422 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6423 6424 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 6425 rt2800_bbp_write(rt2x00dev, 69, 0x16); 6426 rt2800_bbp_write(rt2x00dev, 73, 0x12); 6427 } else { 6428 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6429 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6430 } 6431 6432 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6433 6434 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6435 6436 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6437 6438 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6439 6440 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 6441 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6442 else 6443 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6444 6445 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6446 6447 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6448 6449 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6450 6451 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6452 6453 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6454 6455 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6456 } 6457 6458 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6459 { 6460 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6461 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6462 6463 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6464 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6465 6466 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6467 6468 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6469 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6470 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6471 6472 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6473 6474 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6475 6476 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6477 6478 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6479 6480 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6481 6482 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6483 6484 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6485 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6486 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6487 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6488 else 6489 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6490 6491 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6492 6493 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6494 6495 if (rt2x00_rt(rt2x00dev, RT3071) || 6496 rt2x00_rt(rt2x00dev, RT3090)) 6497 rt2800_disable_unused_dac_adc(rt2x00dev); 6498 } 6499 6500 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6501 { 6502 u8 value; 6503 6504 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6505 6506 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6507 6508 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6509 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6510 6511 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6512 6513 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6514 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6515 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6516 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6517 6518 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6519 6520 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6521 6522 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6523 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6524 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6525 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6526 6527 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6528 6529 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6530 6531 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6532 6533 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6534 6535 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6536 6537 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6538 6539 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6540 6541 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6542 6543 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6544 6545 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6546 6547 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6548 6549 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6550 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6551 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6552 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6553 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6554 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6555 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6556 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6557 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6558 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6559 6560 value = rt2800_bbp_read(rt2x00dev, 47); 6561 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6562 rt2800_bbp_write(rt2x00dev, 47, value); 6563 6564 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6565 value = rt2800_bbp_read(rt2x00dev, 3); 6566 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6567 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6568 rt2800_bbp_write(rt2x00dev, 3, value); 6569 } 6570 6571 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6572 { 6573 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6574 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6575 6576 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6577 6578 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6579 6580 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6581 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6582 6583 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6584 6585 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6586 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6587 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6588 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6589 6590 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6591 6592 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6593 6594 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6595 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6596 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6597 6598 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6599 6600 if (rt2x00_rt(rt2x00dev, RT5350)) { 6601 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6602 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6603 } else { 6604 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6605 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6606 } 6607 6608 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6609 6610 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6611 6612 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6613 6614 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6615 6616 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6617 6618 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6619 6620 if (rt2x00_rt(rt2x00dev, RT5350)) { 6621 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6622 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6623 } else { 6624 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6625 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6626 } 6627 6628 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6629 6630 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6631 6632 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6633 /* Set ITxBF timeout to 0x9c40=1000msec */ 6634 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6635 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6636 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6637 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6638 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6639 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6640 /* Reprogram the inband interface to put right values in RXWI */ 6641 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6642 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6643 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6644 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6645 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6646 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6647 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6648 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6649 6650 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6651 6652 if (rt2x00_rt(rt2x00dev, RT5350)) { 6653 /* Antenna Software OFDM */ 6654 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6655 /* Antenna Software CCK */ 6656 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6657 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6658 /* Clear previously selected antenna */ 6659 rt2800_bbp_write(rt2x00dev, 154, 0); 6660 } 6661 } 6662 6663 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6664 { 6665 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6666 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6667 6668 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6669 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6670 6671 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6672 6673 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6674 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6675 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6676 6677 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6678 6679 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6680 6681 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6682 6683 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6684 6685 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6686 6687 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6688 6689 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6690 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6691 else 6692 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6693 6694 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6695 6696 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6697 6698 rt2800_disable_unused_dac_adc(rt2x00dev); 6699 } 6700 6701 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6702 { 6703 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6704 6705 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6706 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6707 6708 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6709 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6710 6711 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6712 6713 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6714 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6715 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6716 6717 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6718 6719 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6720 6721 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6722 6723 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6724 6725 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6726 6727 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6728 6729 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6730 6731 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6732 6733 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6734 6735 rt2800_disable_unused_dac_adc(rt2x00dev); 6736 } 6737 6738 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6739 { 6740 rt2800_init_bbp_early(rt2x00dev); 6741 6742 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6743 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6744 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6745 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6746 6747 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6748 6749 /* Enable DC filter */ 6750 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6751 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6752 } 6753 6754 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev) 6755 { 6756 rt2800_init_bbp_early(rt2x00dev); 6757 6758 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6759 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6760 6761 rt2800_bbp_write(rt2x00dev, 86, 0x46); 6762 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6763 6764 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6765 6766 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6767 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6768 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6769 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6770 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6771 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6772 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6773 6774 /* Set ITxBF timeout to 0x9C40=1000msec */ 6775 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6776 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6777 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6778 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6779 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6780 6781 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6782 6783 /* Reprogram the inband interface to put right values in RXWI */ 6784 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6785 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6786 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6787 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6788 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6789 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6790 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6791 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6792 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6793 } 6794 6795 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6796 { 6797 int ant, div_mode; 6798 u16 eeprom; 6799 u8 value; 6800 6801 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6802 6803 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6804 6805 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6806 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6807 6808 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6809 6810 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6811 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6812 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6813 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6814 6815 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6816 6817 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6818 6819 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6820 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6821 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6822 6823 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6824 6825 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6826 6827 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6828 6829 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6830 6831 if (rt2x00_rt(rt2x00dev, RT5392)) 6832 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6833 6834 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6835 6836 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6837 6838 if (rt2x00_rt(rt2x00dev, RT5392)) { 6839 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6840 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6841 } 6842 6843 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6844 6845 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6846 6847 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6848 6849 if (rt2x00_rt(rt2x00dev, RT5390)) 6850 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6851 else if (rt2x00_rt(rt2x00dev, RT5392)) 6852 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6853 else 6854 WARN_ON(1); 6855 6856 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6857 6858 if (rt2x00_rt(rt2x00dev, RT5392)) { 6859 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6860 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6861 } 6862 6863 rt2800_disable_unused_dac_adc(rt2x00dev); 6864 6865 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6866 div_mode = rt2x00_get_field16(eeprom, 6867 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6868 ant = (div_mode == 3) ? 1 : 0; 6869 6870 /* check if this is a Bluetooth combo card */ 6871 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6872 u32 reg; 6873 6874 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6875 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6876 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6877 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6878 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6879 if (ant == 0) 6880 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6881 else if (ant == 1) 6882 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6883 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6884 } 6885 6886 /* These chips have hardware RX antenna diversity */ 6887 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6888 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6889 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6890 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6891 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6892 } 6893 6894 value = rt2800_bbp_read(rt2x00dev, 152); 6895 if (ant == 0) 6896 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6897 else 6898 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6899 rt2800_bbp_write(rt2x00dev, 152, value); 6900 6901 rt2800_init_freq_calibration(rt2x00dev); 6902 } 6903 6904 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6905 { 6906 int ant, div_mode; 6907 u16 eeprom; 6908 u8 value; 6909 6910 rt2800_init_bbp_early(rt2x00dev); 6911 6912 value = rt2800_bbp_read(rt2x00dev, 105); 6913 rt2x00_set_field8(&value, BBP105_MLD, 6914 rt2x00dev->default_ant.rx_chain_num == 2); 6915 rt2800_bbp_write(rt2x00dev, 105, value); 6916 6917 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6918 6919 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6920 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6921 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6922 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6923 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6924 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6925 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6926 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6927 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6928 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6929 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6930 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6931 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6932 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6933 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6934 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6935 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6936 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6937 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6938 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6939 /* FIXME BBP105 owerwrite */ 6940 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6941 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6942 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6943 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6944 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6945 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6946 6947 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6948 rt2800_init_bbp_5592_glrt(rt2x00dev); 6949 6950 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6951 6952 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6953 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6954 ant = (div_mode == 3) ? 1 : 0; 6955 value = rt2800_bbp_read(rt2x00dev, 152); 6956 if (ant == 0) { 6957 /* Main antenna */ 6958 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6959 } else { 6960 /* Auxiliary antenna */ 6961 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6962 } 6963 rt2800_bbp_write(rt2x00dev, 152, value); 6964 6965 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6966 value = rt2800_bbp_read(rt2x00dev, 254); 6967 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6968 rt2800_bbp_write(rt2x00dev, 254, value); 6969 } 6970 6971 rt2800_init_freq_calibration(rt2x00dev); 6972 6973 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6974 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6975 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6976 } 6977 6978 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6979 { 6980 u8 bbp; 6981 6982 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6983 bbp = rt2800_bbp_read(rt2x00dev, 105); 6984 rt2x00_set_field8(&bbp, BBP105_MLD, 6985 rt2x00dev->default_ant.rx_chain_num == 2); 6986 rt2800_bbp_write(rt2x00dev, 105, bbp); 6987 6988 /* Avoid data loss and CRC errors */ 6989 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6990 6991 /* Fix I/Q swap issue */ 6992 bbp = rt2800_bbp_read(rt2x00dev, 1); 6993 bbp |= 0x04; 6994 rt2800_bbp_write(rt2x00dev, 1, bbp); 6995 6996 /* BBP for G band */ 6997 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6998 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6999 rt2800_bbp_write(rt2x00dev, 6, 0x08); 7000 rt2800_bbp_write(rt2x00dev, 14, 0x09); 7001 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 7002 rt2800_bbp_write(rt2x00dev, 16, 0x01); 7003 rt2800_bbp_write(rt2x00dev, 20, 0x06); 7004 rt2800_bbp_write(rt2x00dev, 21, 0x00); 7005 rt2800_bbp_write(rt2x00dev, 22, 0x00); 7006 rt2800_bbp_write(rt2x00dev, 27, 0x00); 7007 rt2800_bbp_write(rt2x00dev, 28, 0x00); 7008 rt2800_bbp_write(rt2x00dev, 30, 0x00); 7009 rt2800_bbp_write(rt2x00dev, 31, 0x48); 7010 rt2800_bbp_write(rt2x00dev, 47, 0x40); 7011 rt2800_bbp_write(rt2x00dev, 62, 0x00); 7012 rt2800_bbp_write(rt2x00dev, 63, 0x00); 7013 rt2800_bbp_write(rt2x00dev, 64, 0x00); 7014 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 7015 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 7016 rt2800_bbp_write(rt2x00dev, 67, 0x20); 7017 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 7018 rt2800_bbp_write(rt2x00dev, 69, 0x10); 7019 rt2800_bbp_write(rt2x00dev, 70, 0x05); 7020 rt2800_bbp_write(rt2x00dev, 73, 0x18); 7021 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 7022 rt2800_bbp_write(rt2x00dev, 75, 0x60); 7023 rt2800_bbp_write(rt2x00dev, 76, 0x44); 7024 rt2800_bbp_write(rt2x00dev, 77, 0x59); 7025 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 7026 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 7027 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 7028 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 7029 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 7030 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 7031 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 7032 rt2800_bbp_write(rt2x00dev, 86, 0x38); 7033 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7034 rt2800_bbp_write(rt2x00dev, 91, 0x04); 7035 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7036 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 7037 rt2800_bbp_write(rt2x00dev, 96, 0x00); 7038 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 7039 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7040 /* FIXME BBP105 owerwrite */ 7041 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 7042 rt2800_bbp_write(rt2x00dev, 106, 0x12); 7043 rt2800_bbp_write(rt2x00dev, 109, 0x00); 7044 rt2800_bbp_write(rt2x00dev, 134, 0x10); 7045 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 7046 rt2800_bbp_write(rt2x00dev, 137, 0x04); 7047 rt2800_bbp_write(rt2x00dev, 142, 0x30); 7048 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 7049 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 7050 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 7051 rt2800_bbp_write(rt2x00dev, 162, 0x77); 7052 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 7053 rt2800_bbp_write(rt2x00dev, 164, 0x00); 7054 rt2800_bbp_write(rt2x00dev, 165, 0x00); 7055 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7056 rt2800_bbp_write(rt2x00dev, 187, 0x00); 7057 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7058 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7059 rt2800_bbp_write(rt2x00dev, 187, 0x01); 7060 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7061 rt2800_bbp_write(rt2x00dev, 189, 0x00); 7062 7063 rt2800_bbp_write(rt2x00dev, 91, 0x06); 7064 rt2800_bbp_write(rt2x00dev, 92, 0x04); 7065 rt2800_bbp_write(rt2x00dev, 93, 0x54); 7066 rt2800_bbp_write(rt2x00dev, 99, 0x50); 7067 rt2800_bbp_write(rt2x00dev, 148, 0x84); 7068 rt2800_bbp_write(rt2x00dev, 167, 0x80); 7069 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 7070 rt2800_bbp_write(rt2x00dev, 106, 0x13); 7071 7072 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 7073 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 7074 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 7075 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 7076 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 7077 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 7078 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 7079 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 7080 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 7081 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 7082 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 7083 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 7084 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 7085 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 7086 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 7087 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 7088 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 7089 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 7090 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 7091 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 7092 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 7093 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 7094 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 7095 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 7096 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 7097 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 7098 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 7099 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 7100 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 7101 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 7102 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 7103 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 7104 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 7105 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 7106 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 7107 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 7108 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 7109 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 7110 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 7111 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 7112 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 7113 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 7114 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 7115 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 7116 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 7117 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 7118 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 7119 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 7120 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 7121 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 7122 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 7123 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 7124 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 7125 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 7126 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 7127 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 7128 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 7129 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 7130 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 7131 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 7132 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 7133 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 7134 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 7135 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 7136 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 7137 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 7138 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 7139 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 7140 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 7141 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 7142 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 7143 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 7144 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 7145 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 7146 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 7147 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 7148 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 7149 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 7150 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 7151 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 7152 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 7153 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 7154 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 7155 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 7156 7157 /* BBP for G band DCOC function */ 7158 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 7159 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 7160 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 7161 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 7162 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 7163 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 7164 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 7165 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 7166 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 7167 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 7168 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 7169 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 7170 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 7171 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 7172 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 7173 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 7174 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 7175 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 7176 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 7177 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7178 7179 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7180 } 7181 7182 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 7183 { 7184 unsigned int i; 7185 u16 eeprom; 7186 u8 reg_id; 7187 u8 value; 7188 7189 if (rt2800_is_305x_soc(rt2x00dev)) 7190 rt2800_init_bbp_305x_soc(rt2x00dev); 7191 7192 switch (rt2x00dev->chip.rt) { 7193 case RT2860: 7194 case RT2872: 7195 case RT2883: 7196 rt2800_init_bbp_28xx(rt2x00dev); 7197 break; 7198 case RT3070: 7199 case RT3071: 7200 case RT3090: 7201 rt2800_init_bbp_30xx(rt2x00dev); 7202 break; 7203 case RT3290: 7204 rt2800_init_bbp_3290(rt2x00dev); 7205 break; 7206 case RT3352: 7207 case RT5350: 7208 rt2800_init_bbp_3352(rt2x00dev); 7209 break; 7210 case RT3390: 7211 rt2800_init_bbp_3390(rt2x00dev); 7212 break; 7213 case RT3572: 7214 rt2800_init_bbp_3572(rt2x00dev); 7215 break; 7216 case RT3593: 7217 rt2800_init_bbp_3593(rt2x00dev); 7218 return; 7219 case RT3883: 7220 rt2800_init_bbp_3883(rt2x00dev); 7221 return; 7222 case RT5390: 7223 case RT5392: 7224 rt2800_init_bbp_53xx(rt2x00dev); 7225 break; 7226 case RT5592: 7227 rt2800_init_bbp_5592(rt2x00dev); 7228 return; 7229 case RT6352: 7230 rt2800_init_bbp_6352(rt2x00dev); 7231 break; 7232 } 7233 7234 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 7235 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 7236 EEPROM_BBP_START, i); 7237 7238 if (eeprom != 0xffff && eeprom != 0x0000) { 7239 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 7240 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 7241 rt2800_bbp_write(rt2x00dev, reg_id, value); 7242 } 7243 } 7244 } 7245 7246 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 7247 { 7248 u32 reg; 7249 7250 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 7251 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 7252 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 7253 } 7254 7255 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 7256 u8 filter_target) 7257 { 7258 unsigned int i; 7259 u8 bbp; 7260 u8 rfcsr; 7261 u8 passband; 7262 u8 stopband; 7263 u8 overtuned = 0; 7264 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 7265 7266 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7267 7268 bbp = rt2800_bbp_read(rt2x00dev, 4); 7269 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 7270 rt2800_bbp_write(rt2x00dev, 4, bbp); 7271 7272 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 7273 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 7274 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 7275 7276 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7277 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 7278 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7279 7280 /* 7281 * Set power & frequency of passband test tone 7282 */ 7283 rt2800_bbp_write(rt2x00dev, 24, 0); 7284 7285 for (i = 0; i < 100; i++) { 7286 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7287 msleep(1); 7288 7289 passband = rt2800_bbp_read(rt2x00dev, 55); 7290 if (passband) 7291 break; 7292 } 7293 7294 /* 7295 * Set power & frequency of stopband test tone 7296 */ 7297 rt2800_bbp_write(rt2x00dev, 24, 0x06); 7298 7299 for (i = 0; i < 100; i++) { 7300 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7301 msleep(1); 7302 7303 stopband = rt2800_bbp_read(rt2x00dev, 55); 7304 7305 if ((passband - stopband) <= filter_target) { 7306 rfcsr24++; 7307 overtuned += ((passband - stopband) == filter_target); 7308 } else 7309 break; 7310 7311 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7312 } 7313 7314 rfcsr24 -= !!overtuned; 7315 7316 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7317 return rfcsr24; 7318 } 7319 7320 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 7321 const unsigned int rf_reg) 7322 { 7323 u8 rfcsr; 7324 7325 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 7326 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 7327 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7328 msleep(1); 7329 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 7330 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7331 } 7332 7333 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 7334 { 7335 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7336 u8 filter_tgt_bw20; 7337 u8 filter_tgt_bw40; 7338 u8 rfcsr, bbp; 7339 7340 /* 7341 * TODO: sync filter_tgt values with vendor driver 7342 */ 7343 if (rt2x00_rt(rt2x00dev, RT3070)) { 7344 filter_tgt_bw20 = 0x16; 7345 filter_tgt_bw40 = 0x19; 7346 } else { 7347 filter_tgt_bw20 = 0x13; 7348 filter_tgt_bw40 = 0x15; 7349 } 7350 7351 drv_data->calibration_bw20 = 7352 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 7353 drv_data->calibration_bw40 = 7354 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 7355 7356 /* 7357 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 7358 */ 7359 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7360 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7361 7362 /* 7363 * Set back to initial state 7364 */ 7365 rt2800_bbp_write(rt2x00dev, 24, 0); 7366 7367 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7368 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 7369 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7370 7371 /* 7372 * Set BBP back to BW20 7373 */ 7374 bbp = rt2800_bbp_read(rt2x00dev, 4); 7375 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 7376 rt2800_bbp_write(rt2x00dev, 4, bbp); 7377 } 7378 7379 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 7380 { 7381 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7382 u8 min_gain, rfcsr, bbp; 7383 u16 eeprom; 7384 7385 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 7386 7387 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 7388 if (rt2x00_rt(rt2x00dev, RT3070) || 7389 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7390 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 7391 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 7392 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 7393 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 7394 } 7395 7396 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 7397 if (drv_data->txmixer_gain_24g >= min_gain) { 7398 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 7399 drv_data->txmixer_gain_24g); 7400 } 7401 7402 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 7403 7404 if (rt2x00_rt(rt2x00dev, RT3090)) { 7405 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7406 bbp = rt2800_bbp_read(rt2x00dev, 138); 7407 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7408 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7409 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 7410 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7411 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 7412 rt2800_bbp_write(rt2x00dev, 138, bbp); 7413 } 7414 7415 if (rt2x00_rt(rt2x00dev, RT3070)) { 7416 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 7417 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 7418 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 7419 else 7420 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 7421 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 7422 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 7423 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 7424 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 7425 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7426 rt2x00_rt(rt2x00dev, RT3090) || 7427 rt2x00_rt(rt2x00dev, RT3390)) { 7428 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7429 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7430 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 7431 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 7432 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 7433 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 7434 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7435 7436 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 7437 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 7438 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 7439 7440 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 7441 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 7442 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 7443 7444 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 7445 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 7446 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 7447 } 7448 } 7449 7450 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 7451 { 7452 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7453 u8 rfcsr; 7454 u8 tx_gain; 7455 7456 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 7457 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 7458 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7459 7460 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 7461 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 7462 RFCSR17_TXMIXER_GAIN); 7463 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 7464 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 7465 7466 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 7467 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 7468 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 7469 7470 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 7471 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 7472 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 7473 7474 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7475 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7476 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7477 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7478 7479 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7480 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7481 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7482 7483 /* TODO: enable stream mode */ 7484 } 7485 7486 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7487 { 7488 u8 reg; 7489 u16 eeprom; 7490 7491 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7492 reg = rt2800_bbp_read(rt2x00dev, 138); 7493 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7494 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7495 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7496 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7497 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7498 rt2800_bbp_write(rt2x00dev, 138, reg); 7499 7500 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7501 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7502 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7503 7504 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7505 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7506 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7507 7508 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7509 7510 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7511 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7512 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7513 } 7514 7515 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7516 { 7517 rt2800_rf_init_calibration(rt2x00dev, 30); 7518 7519 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7520 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7521 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7522 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7523 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7524 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7525 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7526 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7527 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7528 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7529 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7530 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7531 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7532 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7533 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7534 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7535 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7536 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7537 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7538 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7539 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7540 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7541 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7542 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7543 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7544 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7545 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7546 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7547 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7548 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7549 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7550 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7551 } 7552 7553 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7554 { 7555 u8 rfcsr; 7556 u16 eeprom; 7557 u32 reg; 7558 7559 /* XXX vendor driver do this only for 3070 */ 7560 rt2800_rf_init_calibration(rt2x00dev, 30); 7561 7562 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7563 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7564 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7565 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7566 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7567 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7568 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7569 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7570 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7571 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7572 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7573 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7574 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7575 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7576 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7577 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7578 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7579 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7580 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7581 7582 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7583 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7584 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7585 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7586 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7587 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7588 rt2x00_rt(rt2x00dev, RT3090)) { 7589 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7590 7591 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7592 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7593 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7594 7595 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7596 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7597 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7598 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7599 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7600 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7601 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7602 else 7603 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7604 } 7605 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7606 7607 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7608 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7609 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7610 } 7611 7612 rt2800_rx_filter_calibration(rt2x00dev); 7613 7614 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7615 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7616 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7617 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7618 7619 rt2800_led_open_drain_enable(rt2x00dev); 7620 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7621 } 7622 7623 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7624 { 7625 u8 rfcsr; 7626 7627 rt2800_rf_init_calibration(rt2x00dev, 2); 7628 7629 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7630 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7631 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7632 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7633 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7634 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7635 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7636 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7637 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7638 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7639 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7640 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7641 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7642 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7643 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7644 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7645 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7646 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7647 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7648 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7649 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7650 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7651 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7652 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7653 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7654 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7655 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7656 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7657 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7658 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7659 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7660 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7661 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7662 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7663 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7664 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7665 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7666 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7667 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7668 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7669 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7670 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7671 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7672 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7673 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7674 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7675 7676 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7677 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7678 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7679 7680 rt2800_led_open_drain_enable(rt2x00dev); 7681 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7682 } 7683 7684 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7685 { 7686 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7687 &rt2x00dev->cap_flags); 7688 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7689 &rt2x00dev->cap_flags); 7690 u8 rfcsr; 7691 7692 rt2800_rf_init_calibration(rt2x00dev, 30); 7693 7694 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7695 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7696 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7697 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7698 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7699 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7700 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7701 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7702 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7703 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7704 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7705 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7706 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7707 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7708 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7709 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7710 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7711 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7712 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7713 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7714 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7715 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7716 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7717 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7718 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7719 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7720 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7721 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7722 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7723 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7724 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7725 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7726 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7727 rfcsr = 0x01; 7728 if (tx0_ext_pa) 7729 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7730 if (tx1_ext_pa) 7731 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7732 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7733 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7734 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7735 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7736 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7737 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7738 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7739 rfcsr = 0x52; 7740 if (!tx0_ext_pa) { 7741 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7742 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7743 } 7744 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7745 rfcsr = 0x52; 7746 if (!tx1_ext_pa) { 7747 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7748 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7749 } 7750 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7751 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7752 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7753 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7754 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7755 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7756 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7757 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7758 rfcsr = 0x2d; 7759 if (tx0_ext_pa) 7760 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7761 if (tx1_ext_pa) 7762 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7763 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7764 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7765 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7766 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7767 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7768 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7769 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7770 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7771 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7772 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7773 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7774 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7775 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7776 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7777 7778 rt2800_rx_filter_calibration(rt2x00dev); 7779 rt2800_led_open_drain_enable(rt2x00dev); 7780 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7781 } 7782 7783 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7784 { 7785 u32 reg; 7786 7787 rt2800_rf_init_calibration(rt2x00dev, 30); 7788 7789 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7790 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7791 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7792 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7793 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7794 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7795 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7796 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7797 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7798 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7799 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7800 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7801 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7802 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7803 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7804 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7805 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7806 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7807 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7808 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7809 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7810 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7811 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7812 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7813 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7814 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7815 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7816 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7817 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7818 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7819 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7820 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7821 7822 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7823 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7824 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7825 7826 rt2800_rx_filter_calibration(rt2x00dev); 7827 7828 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7829 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7830 7831 rt2800_led_open_drain_enable(rt2x00dev); 7832 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7833 } 7834 7835 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7836 { 7837 u8 rfcsr; 7838 u32 reg; 7839 7840 rt2800_rf_init_calibration(rt2x00dev, 30); 7841 7842 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7843 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7844 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7845 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7846 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7847 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7848 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7849 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7850 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7851 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7852 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7853 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7854 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7855 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7856 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7857 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7858 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7859 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7860 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7861 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7862 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7863 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7864 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7865 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7866 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7867 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7868 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7869 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7870 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7871 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7872 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7873 7874 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7875 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7876 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7877 7878 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7879 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7880 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7881 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7882 msleep(1); 7883 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7884 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7885 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7886 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7887 7888 rt2800_rx_filter_calibration(rt2x00dev); 7889 rt2800_led_open_drain_enable(rt2x00dev); 7890 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7891 } 7892 7893 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7894 { 7895 u8 bbp; 7896 bool txbf_enabled = false; /* FIXME */ 7897 7898 bbp = rt2800_bbp_read(rt2x00dev, 105); 7899 if (rt2x00dev->default_ant.rx_chain_num == 1) 7900 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7901 else 7902 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7903 rt2800_bbp_write(rt2x00dev, 105, bbp); 7904 7905 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7906 7907 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7908 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7909 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7910 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7911 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7912 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7913 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7914 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7915 7916 if (txbf_enabled) 7917 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7918 else 7919 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7920 7921 /* SNR mapping */ 7922 rt2800_bbp_write(rt2x00dev, 142, 6); 7923 rt2800_bbp_write(rt2x00dev, 143, 160); 7924 rt2800_bbp_write(rt2x00dev, 142, 7); 7925 rt2800_bbp_write(rt2x00dev, 143, 161); 7926 rt2800_bbp_write(rt2x00dev, 142, 8); 7927 rt2800_bbp_write(rt2x00dev, 143, 162); 7928 7929 /* ADC/DAC control */ 7930 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7931 7932 /* RX AGC energy lower bound in log2 */ 7933 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7934 7935 /* FIXME: BBP 105 owerwrite? */ 7936 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7937 7938 } 7939 7940 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7941 { 7942 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7943 u32 reg; 7944 u8 rfcsr; 7945 7946 /* Disable GPIO #4 and #7 function for LAN PE control */ 7947 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7948 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7949 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7950 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7951 7952 /* Initialize default register values */ 7953 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7954 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7955 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7956 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7957 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7958 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7959 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7960 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7961 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7962 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7963 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7964 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7965 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7966 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7967 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7968 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7969 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7970 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7971 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7972 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7973 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7974 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7975 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7976 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7977 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7978 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7979 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7980 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7981 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7982 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7983 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7984 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7985 7986 /* Initiate calibration */ 7987 /* TODO: use rt2800_rf_init_calibration ? */ 7988 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7989 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7990 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7991 7992 rt2800_freq_cal_mode1(rt2x00dev); 7993 7994 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7995 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7996 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7997 7998 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7999 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 8000 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 8001 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8002 usleep_range(1000, 1500); 8003 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 8004 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 8005 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8006 8007 /* Set initial values for RX filter calibration */ 8008 drv_data->calibration_bw20 = 0x1f; 8009 drv_data->calibration_bw40 = 0x2f; 8010 8011 /* Save BBP 25 & 26 values for later use in channel switching */ 8012 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 8013 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 8014 8015 rt2800_led_open_drain_enable(rt2x00dev); 8016 rt2800_normal_mode_setup_3593(rt2x00dev); 8017 8018 rt3593_post_bbp_init(rt2x00dev); 8019 8020 /* TODO: enable stream mode support */ 8021 } 8022 8023 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 8024 { 8025 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 8026 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 8027 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8028 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8029 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 8030 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8031 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8032 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8033 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 8034 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 8035 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8036 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8037 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8038 if (rt2800_clk_is_20mhz(rt2x00dev)) 8039 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 8040 else 8041 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8042 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8043 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8044 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 8045 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8046 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8047 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8048 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8049 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8050 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8051 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8052 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8053 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8054 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8055 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8056 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 8057 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8058 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8059 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8060 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8061 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8062 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8063 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8064 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8065 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8066 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8067 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8068 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8069 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8070 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8071 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 8072 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 8073 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8074 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8075 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8076 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 8077 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 8078 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 8079 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8080 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8081 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8082 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8083 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 8084 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8085 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8086 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 8087 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8088 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8089 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8090 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8091 } 8092 8093 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev) 8094 { 8095 u8 rfcsr; 8096 8097 /* TODO: get the actual ECO value from the SoC */ 8098 const unsigned int eco = 5; 8099 8100 rt2800_rf_init_calibration(rt2x00dev, 2); 8101 8102 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0); 8103 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8104 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8105 rt2800_rfcsr_write(rt2x00dev, 3, 0x20); 8106 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 8107 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8108 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8109 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8110 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b); 8111 rt2800_rfcsr_write(rt2x00dev, 9, 0x08); 8112 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8113 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 8114 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 8115 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8116 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8117 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8118 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8119 8120 /* RFCSR 17 will be initialized later based on the 8121 * frequency offset stored in the EEPROM 8122 */ 8123 8124 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8125 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8126 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8127 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8128 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8129 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0); 8130 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8131 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8132 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8133 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8134 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8135 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 8136 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8137 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8138 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8139 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8140 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 8141 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8142 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8143 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8144 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8145 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8146 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8147 rt2800_rfcsr_write(rt2x00dev, 41, 0x00); 8148 rt2800_rfcsr_write(rt2x00dev, 42, 0x00); 8149 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8150 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 8151 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8152 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8153 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8154 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 8155 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8156 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8157 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 8158 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 8159 rt2800_rfcsr_write(rt2x00dev, 53, 0x76); 8160 rt2800_rfcsr_write(rt2x00dev, 54, 0x76); 8161 rt2800_rfcsr_write(rt2x00dev, 55, 0x76); 8162 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8163 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 8164 rt2800_rfcsr_write(rt2x00dev, 58, 0x00); 8165 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 8166 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 8167 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 8168 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8169 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8170 8171 /* TODO: rx filter calibration? */ 8172 8173 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 8174 8175 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 8176 8177 rt2800_bbp_write(rt2x00dev, 105, 0x05); 8178 8179 rt2800_bbp_write(rt2x00dev, 179, 0x02); 8180 rt2800_bbp_write(rt2x00dev, 180, 0x00); 8181 rt2800_bbp_write(rt2x00dev, 182, 0x40); 8182 rt2800_bbp_write(rt2x00dev, 180, 0x01); 8183 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 8184 8185 rt2800_bbp_write(rt2x00dev, 179, 0x00); 8186 8187 rt2800_bbp_write(rt2x00dev, 142, 0x04); 8188 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 8189 rt2800_bbp_write(rt2x00dev, 142, 0x06); 8190 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 8191 rt2800_bbp_write(rt2x00dev, 142, 0x07); 8192 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 8193 rt2800_bbp_write(rt2x00dev, 142, 0x08); 8194 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 8195 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 8196 8197 if (eco == 5) { 8198 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 8199 rt2800_rfcsr_write(rt2x00dev, 33, 0x32); 8200 } 8201 8202 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8203 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0); 8204 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8205 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8206 msleep(1); 8207 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 8208 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8209 8210 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 8211 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 8212 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 8213 8214 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 8215 rfcsr |= 0xc0; 8216 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 8217 8218 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 8219 rfcsr |= 0x20; 8220 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 8221 8222 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46); 8223 rfcsr |= 0x20; 8224 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr); 8225 8226 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 8227 rfcsr &= ~0xee; 8228 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 8229 } 8230 8231 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 8232 { 8233 rt2800_rf_init_calibration(rt2x00dev, 2); 8234 8235 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 8236 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8237 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8238 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8239 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8240 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8241 else 8242 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 8243 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8244 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8245 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8246 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8247 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8248 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8249 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8250 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8251 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8252 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8253 8254 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8255 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8256 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8257 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8258 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8259 if (rt2x00_is_usb(rt2x00dev) && 8260 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8261 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8262 else 8263 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 8264 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8265 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8266 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8267 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8268 8269 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8270 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8271 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8272 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8273 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8274 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8275 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8276 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8277 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8278 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8279 8280 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8281 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8282 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 8283 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 8284 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8285 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8286 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8287 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8288 else 8289 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 8290 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8291 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8292 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8293 8294 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8295 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8296 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8297 else 8298 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 8299 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 8300 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 8301 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8302 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 8303 else 8304 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 8305 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 8306 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 8307 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 8308 8309 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8310 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 8311 if (rt2x00_is_usb(rt2x00dev)) 8312 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8313 else 8314 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 8315 } else { 8316 if (rt2x00_is_usb(rt2x00dev)) 8317 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 8318 else 8319 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 8320 } 8321 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8322 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8323 8324 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8325 8326 rt2800_led_open_drain_enable(rt2x00dev); 8327 } 8328 8329 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 8330 { 8331 rt2800_rf_init_calibration(rt2x00dev, 2); 8332 8333 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 8334 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8335 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8336 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8337 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8338 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8339 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8340 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8341 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8342 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8343 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8344 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8345 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8346 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 8347 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8348 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 8349 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8350 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 8351 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 8352 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8353 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8354 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8355 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8356 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8357 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8358 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8359 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 8360 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8361 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8362 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8363 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8364 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8365 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 8366 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8367 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 8368 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8369 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8370 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8371 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8372 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8373 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8374 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 8375 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8376 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8377 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 8378 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 8379 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 8380 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 8381 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8382 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8383 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 8384 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8385 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8386 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 8387 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8388 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 8389 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 8390 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8391 8392 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8393 8394 rt2800_led_open_drain_enable(rt2x00dev); 8395 } 8396 8397 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 8398 { 8399 rt2800_rf_init_calibration(rt2x00dev, 30); 8400 8401 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 8402 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8403 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8404 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 8405 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8406 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8407 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8408 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8409 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8410 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 8411 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 8412 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 8413 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8414 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8415 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8416 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8417 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8418 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8419 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 8420 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 8421 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8422 8423 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8424 msleep(1); 8425 8426 rt2800_freq_cal_mode1(rt2x00dev); 8427 8428 /* Enable DC filter */ 8429 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 8430 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 8431 8432 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8433 8434 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 8435 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8436 8437 rt2800_led_open_drain_enable(rt2x00dev); 8438 } 8439 8440 static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev) 8441 { 8442 u8 rfb5r1_org, rfb7r1_org, rfvalue; 8443 u32 mac0518, mac051c, mac0528, mac052c; 8444 u8 i; 8445 8446 mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8447 mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8448 mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 8449 mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 8450 8451 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8452 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8453 8454 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC); 8455 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306); 8456 rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330); 8457 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff); 8458 rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8459 rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8460 8461 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4); 8462 for (i = 0; i < 100; ++i) { 8463 usleep_range(50, 100); 8464 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8465 if ((rfvalue & 0x04) != 0x4) 8466 break; 8467 } 8468 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org); 8469 8470 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4); 8471 for (i = 0; i < 100; ++i) { 8472 usleep_range(50, 100); 8473 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8474 if ((rfvalue & 0x04) != 0x4) 8475 break; 8476 } 8477 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org); 8478 8479 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8480 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8481 rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518); 8482 rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c); 8483 rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528); 8484 rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c); 8485 } 8486 8487 static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2) 8488 { 8489 int calcode = ((d2 - d1) * 1000) / 43; 8490 8491 if ((calcode % 10) >= 5) 8492 calcode += 10; 8493 calcode = (calcode / 10); 8494 8495 return calcode; 8496 } 8497 8498 static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) 8499 { 8500 u32 savemacsysctrl; 8501 u8 saverfb0r1, saverfb0r34, saverfb0r35; 8502 u8 saverfb5r4, saverfb5r17, saverfb5r18; 8503 u8 saverfb5r19, saverfb5r20; 8504 u8 savebbpr22, savebbpr47, savebbpr49; 8505 u8 bytevalue = 0; 8506 int rcalcode; 8507 u8 r_cal_code = 0; 8508 char d1 = 0, d2 = 0; 8509 u8 rfvalue; 8510 u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG; 8511 u32 maccfg; 8512 8513 saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8514 saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34); 8515 saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 8516 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8517 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8518 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8519 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8520 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8521 8522 savebbpr22 = rt2800_bbp_read(rt2x00dev, 22); 8523 savebbpr47 = rt2800_bbp_read(rt2x00dev, 47); 8524 savebbpr49 = rt2800_bbp_read(rt2x00dev, 49); 8525 8526 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8527 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8528 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8529 MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG); 8530 8531 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8532 maccfg &= (~0x04); 8533 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8534 8535 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8536 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n"); 8537 8538 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8539 maccfg &= (~0x04); 8540 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8541 8542 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 8543 rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n"); 8544 8545 rfvalue = (MAC_RF_BYPASS0 | 0x3004); 8546 rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue); 8547 rfvalue = (MAC_RF_CONTROL0 | (~0x3002)); 8548 rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue); 8549 8550 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27); 8551 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 8552 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83); 8553 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00); 8554 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 8555 8556 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00); 8557 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13); 8558 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 8559 8560 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1); 8561 8562 rt2800_bbp_write(rt2x00dev, 47, 0x04); 8563 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8564 usleep_range(100, 200); 8565 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8566 if (bytevalue > 128) 8567 d1 = bytevalue - 256; 8568 else 8569 d1 = (char)bytevalue; 8570 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8571 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01); 8572 8573 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8574 usleep_range(100, 200); 8575 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8576 if (bytevalue > 128) 8577 d2 = bytevalue - 256; 8578 else 8579 d2 = (char)bytevalue; 8580 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8581 8582 rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2); 8583 if (rcalcode < 0) 8584 r_cal_code = 256 + rcalcode; 8585 else 8586 r_cal_code = (u8)rcalcode; 8587 8588 rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code); 8589 8590 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8591 8592 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8593 bytevalue |= 0x1; 8594 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8595 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8596 bytevalue &= (~0x1); 8597 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8598 8599 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1); 8600 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34); 8601 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35); 8602 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8603 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8604 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8605 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8606 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8607 8608 rt2800_bbp_write(rt2x00dev, 22, savebbpr22); 8609 rt2800_bbp_write(rt2x00dev, 47, savebbpr47); 8610 rt2800_bbp_write(rt2x00dev, 49, savebbpr49); 8611 8612 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8613 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8614 8615 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 8616 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG); 8617 } 8618 8619 static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev) 8620 { 8621 u8 bbpreg = 0; 8622 u32 macvalue = 0; 8623 u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue; 8624 int i; 8625 8626 saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8627 rfvalue = saverfb0r2; 8628 rfvalue |= 0x03; 8629 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue); 8630 8631 rt2800_bbp_write(rt2x00dev, 158, 141); 8632 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8633 bbpreg |= 0x10; 8634 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8635 8636 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8637 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8); 8638 8639 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8640 rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n"); 8641 8642 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8643 saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8644 saverfb5r4 = saverfb5r4 & (~0x40); 8645 saverfb7r4 = saverfb7r4 & (~0x40); 8646 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64); 8647 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8648 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4); 8649 8650 rt2800_bbp_write(rt2x00dev, 158, 141); 8651 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8652 bbpreg = bbpreg & (~0x40); 8653 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8654 bbpreg |= 0x48; 8655 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8656 8657 for (i = 0; i < 10000; i++) { 8658 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8659 if ((bbpreg & 0x40) == 0) 8660 break; 8661 usleep_range(50, 100); 8662 } 8663 8664 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8665 bbpreg = bbpreg & (~0x40); 8666 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8667 8668 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 8669 8670 rt2800_bbp_write(rt2x00dev, 158, 141); 8671 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8672 bbpreg &= (~0x10); 8673 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8674 8675 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2); 8676 } 8677 8678 static u32 rt2800_do_sqrt_accumulation(u32 si) 8679 { 8680 u32 root, root_pre, bit; 8681 char i; 8682 8683 bit = 1 << 15; 8684 root = 0; 8685 for (i = 15; i >= 0; i = i - 1) { 8686 root_pre = root + bit; 8687 if ((root_pre * root_pre) <= si) 8688 root = root_pre; 8689 bit = bit >> 1; 8690 } 8691 8692 return root; 8693 } 8694 8695 static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev) 8696 { 8697 u8 rfb0r1, rfb0r2, rfb0r42; 8698 u8 rfb4r0, rfb4r19; 8699 u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20; 8700 u8 rfb6r0, rfb6r19; 8701 u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20; 8702 8703 u8 bbp1, bbp4; 8704 u8 bbpr241, bbpr242; 8705 u32 i; 8706 u8 ch_idx; 8707 u8 bbpval; 8708 u8 rfval, vga_idx = 0; 8709 int mi = 0, mq = 0, si = 0, sq = 0, riq = 0; 8710 int sigma_i, sigma_q, r_iq, g_rx; 8711 int g_imb; 8712 int ph_rx; 8713 u32 savemacsysctrl = 0; 8714 u32 orig_RF_CONTROL0 = 0; 8715 u32 orig_RF_BYPASS0 = 0; 8716 u32 orig_RF_CONTROL1 = 0; 8717 u32 orig_RF_BYPASS1 = 0; 8718 u32 orig_RF_CONTROL3 = 0; 8719 u32 orig_RF_BYPASS3 = 0; 8720 u32 bbpval1 = 0; 8721 static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f}; 8722 8723 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8724 orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8725 orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8726 orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1); 8727 orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1); 8728 orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 8729 orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 8730 8731 bbp1 = rt2800_bbp_read(rt2x00dev, 1); 8732 bbp4 = rt2800_bbp_read(rt2x00dev, 4); 8733 8734 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0); 8735 8736 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 8737 rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n"); 8738 8739 bbpval = bbp4 & (~0x18); 8740 bbpval = bbp4 | 0x00; 8741 rt2800_bbp_write(rt2x00dev, 4, bbpval); 8742 8743 bbpval = rt2800_bbp_read(rt2x00dev, 21); 8744 bbpval = bbpval | 1; 8745 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8746 bbpval = bbpval & 0xfe; 8747 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8748 8749 rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202); 8750 rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303); 8751 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 8752 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101); 8753 else 8754 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000); 8755 8756 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1); 8757 8758 rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8759 rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8760 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 8761 rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 8762 rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19); 8763 rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8764 rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8765 rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8766 rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8767 rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8768 rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8769 8770 rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 8771 rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19); 8772 rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 8773 rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8774 rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 8775 rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 8776 rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 8777 rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 8778 8779 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87); 8780 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27); 8781 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38); 8782 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38); 8783 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80); 8784 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1); 8785 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60); 8786 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8787 8788 rt2800_bbp_write(rt2x00dev, 23, 0x0); 8789 rt2800_bbp_write(rt2x00dev, 24, 0x0); 8790 8791 rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0); 8792 8793 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 8794 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 8795 8796 rt2800_bbp_write(rt2x00dev, 241, 0x10); 8797 rt2800_bbp_write(rt2x00dev, 242, 0x84); 8798 rt2800_bbp_write(rt2x00dev, 244, 0x31); 8799 8800 bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3); 8801 bbpval = bbpval & (~0x7); 8802 rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval); 8803 8804 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 8805 udelay(1); 8806 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 8807 usleep_range(1, 200); 8808 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376); 8809 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8810 udelay(1); 8811 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 8812 rt2800_bbp_write(rt2x00dev, 23, 0x06); 8813 rt2800_bbp_write(rt2x00dev, 24, 0x06); 8814 } else { 8815 rt2800_bbp_write(rt2x00dev, 23, 0x02); 8816 rt2800_bbp_write(rt2x00dev, 24, 0x02); 8817 } 8818 8819 for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) { 8820 if (ch_idx == 0) { 8821 rfval = rfb0r1 & (~0x3); 8822 rfval = rfb0r1 | 0x1; 8823 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8824 rfval = rfb0r2 & (~0x33); 8825 rfval = rfb0r2 | 0x11; 8826 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8827 rfval = rfb0r42 & (~0x50); 8828 rfval = rfb0r42 | 0x10; 8829 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8830 8831 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8832 udelay(1); 8833 8834 bbpval = bbp1 & (~0x18); 8835 bbpval = bbpval | 0x00; 8836 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8837 8838 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00); 8839 } else { 8840 rfval = rfb0r1 & (~0x3); 8841 rfval = rfb0r1 | 0x2; 8842 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8843 rfval = rfb0r2 & (~0x33); 8844 rfval = rfb0r2 | 0x22; 8845 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8846 rfval = rfb0r42 & (~0x50); 8847 rfval = rfb0r42 | 0x40; 8848 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8849 8850 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006); 8851 udelay(1); 8852 8853 bbpval = bbp1 & (~0x18); 8854 bbpval = bbpval | 0x08; 8855 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8856 8857 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01); 8858 } 8859 usleep_range(500, 1500); 8860 8861 vga_idx = 0; 8862 while (vga_idx < 11) { 8863 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]); 8864 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]); 8865 8866 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93); 8867 8868 for (i = 0; i < 10000; i++) { 8869 bbpval = rt2800_bbp_read(rt2x00dev, 159); 8870 if ((bbpval & 0xff) == 0x93) 8871 usleep_range(50, 100); 8872 else 8873 break; 8874 } 8875 8876 if ((bbpval & 0xff) == 0x93) { 8877 rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish"); 8878 goto restore_value; 8879 } 8880 for (i = 0; i < 5; i++) { 8881 u32 bbptemp = 0; 8882 u8 value = 0; 8883 int result = 0; 8884 8885 rt2800_bbp_write(rt2x00dev, 158, 0x1e); 8886 rt2800_bbp_write(rt2x00dev, 159, i); 8887 rt2800_bbp_write(rt2x00dev, 158, 0x22); 8888 value = rt2800_bbp_read(rt2x00dev, 159); 8889 bbptemp = bbptemp + (value << 24); 8890 rt2800_bbp_write(rt2x00dev, 158, 0x21); 8891 value = rt2800_bbp_read(rt2x00dev, 159); 8892 bbptemp = bbptemp + (value << 16); 8893 rt2800_bbp_write(rt2x00dev, 158, 0x20); 8894 value = rt2800_bbp_read(rt2x00dev, 159); 8895 bbptemp = bbptemp + (value << 8); 8896 rt2800_bbp_write(rt2x00dev, 158, 0x1f); 8897 value = rt2800_bbp_read(rt2x00dev, 159); 8898 bbptemp = bbptemp + value; 8899 8900 if (i < 2 && (bbptemp & 0x800000)) 8901 result = (bbptemp & 0xffffff) - 0x1000000; 8902 else if (i == 4) 8903 result = bbptemp; 8904 else 8905 result = bbptemp; 8906 8907 if (i == 0) 8908 mi = result / 4096; 8909 else if (i == 1) 8910 mq = result / 4096; 8911 else if (i == 2) 8912 si = bbptemp / 4096; 8913 else if (i == 3) 8914 sq = bbptemp / 4096; 8915 else 8916 riq = result / 4096; 8917 } 8918 8919 bbpval1 = si - mi * mi; 8920 rt2x00_dbg(rt2x00dev, 8921 "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d", 8922 si, sq, riq, bbpval1, vga_idx); 8923 8924 if (bbpval1 >= (100 * 100)) 8925 break; 8926 8927 if (bbpval1 <= 100) 8928 vga_idx = vga_idx + 9; 8929 else if (bbpval1 <= 158) 8930 vga_idx = vga_idx + 8; 8931 else if (bbpval1 <= 251) 8932 vga_idx = vga_idx + 7; 8933 else if (bbpval1 <= 398) 8934 vga_idx = vga_idx + 6; 8935 else if (bbpval1 <= 630) 8936 vga_idx = vga_idx + 5; 8937 else if (bbpval1 <= 1000) 8938 vga_idx = vga_idx + 4; 8939 else if (bbpval1 <= 1584) 8940 vga_idx = vga_idx + 3; 8941 else if (bbpval1 <= 2511) 8942 vga_idx = vga_idx + 2; 8943 else 8944 vga_idx = vga_idx + 1; 8945 } 8946 8947 sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi)); 8948 sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq)); 8949 r_iq = 10 * (riq - (mi * mq)); 8950 8951 rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq); 8952 8953 if (sigma_i <= 1400 && sigma_i >= 1000 && 8954 (sigma_i - sigma_q) <= 112 && 8955 (sigma_i - sigma_q) >= -112 && 8956 mi <= 32 && mi >= -32 && 8957 mq <= 32 && mq >= -32) { 8958 r_iq = 10 * (riq - (mi * mq)); 8959 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 8960 sigma_i, sigma_q, r_iq); 8961 8962 g_rx = (1000 * sigma_q) / sigma_i; 8963 g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx); 8964 ph_rx = (r_iq * 2292) / (sigma_i * sigma_q); 8965 8966 if (ph_rx > 20 || ph_rx < -20) { 8967 ph_rx = 0; 8968 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 8969 } 8970 8971 if (g_imb > 12 || g_imb < -12) { 8972 g_imb = 0; 8973 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 8974 } 8975 } else { 8976 g_imb = 0; 8977 ph_rx = 0; 8978 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 8979 sigma_i, sigma_q, r_iq); 8980 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 8981 } 8982 8983 if (ch_idx == 0) { 8984 rt2800_bbp_write(rt2x00dev, 158, 0x37); 8985 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 8986 rt2800_bbp_write(rt2x00dev, 158, 0x35); 8987 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 8988 } else { 8989 rt2800_bbp_write(rt2x00dev, 158, 0x55); 8990 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 8991 rt2800_bbp_write(rt2x00dev, 158, 0x53); 8992 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 8993 } 8994 } 8995 8996 restore_value: 8997 rt2800_bbp_write(rt2x00dev, 158, 0x3); 8998 bbpval = rt2800_bbp_read(rt2x00dev, 159); 8999 rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07)); 9000 9001 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9002 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9003 rt2800_bbp_write(rt2x00dev, 1, bbp1); 9004 rt2800_bbp_write(rt2x00dev, 4, bbp4); 9005 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9006 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9007 9008 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9009 bbpval = rt2800_bbp_read(rt2x00dev, 21); 9010 bbpval |= 0x1; 9011 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9012 usleep_range(10, 200); 9013 bbpval &= 0xfe; 9014 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9015 9016 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1); 9017 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2); 9018 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9019 9020 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0); 9021 rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19); 9022 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3); 9023 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4); 9024 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17); 9025 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18); 9026 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19); 9027 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20); 9028 9029 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0); 9030 rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19); 9031 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3); 9032 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4); 9033 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17); 9034 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18); 9035 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19); 9036 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20); 9037 9038 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 9039 udelay(1); 9040 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9041 udelay(1); 9042 rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0); 9043 udelay(1); 9044 rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0); 9045 rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1); 9046 rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1); 9047 rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3); 9048 rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3); 9049 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9050 } 9051 9052 static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, 9053 struct rf_reg_pair rf_reg_record[][13], u8 chain) 9054 { 9055 u8 rfvalue = 0; 9056 9057 if (chain == CHAIN_0) { 9058 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9059 rf_reg_record[CHAIN_0][0].bank = 0; 9060 rf_reg_record[CHAIN_0][0].reg = 1; 9061 rf_reg_record[CHAIN_0][0].value = rfvalue; 9062 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9063 rf_reg_record[CHAIN_0][1].bank = 0; 9064 rf_reg_record[CHAIN_0][1].reg = 2; 9065 rf_reg_record[CHAIN_0][1].value = rfvalue; 9066 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9067 rf_reg_record[CHAIN_0][2].bank = 0; 9068 rf_reg_record[CHAIN_0][2].reg = 35; 9069 rf_reg_record[CHAIN_0][2].value = rfvalue; 9070 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9071 rf_reg_record[CHAIN_0][3].bank = 0; 9072 rf_reg_record[CHAIN_0][3].reg = 42; 9073 rf_reg_record[CHAIN_0][3].value = rfvalue; 9074 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 9075 rf_reg_record[CHAIN_0][4].bank = 4; 9076 rf_reg_record[CHAIN_0][4].reg = 0; 9077 rf_reg_record[CHAIN_0][4].value = rfvalue; 9078 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2); 9079 rf_reg_record[CHAIN_0][5].bank = 4; 9080 rf_reg_record[CHAIN_0][5].reg = 2; 9081 rf_reg_record[CHAIN_0][5].value = rfvalue; 9082 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34); 9083 rf_reg_record[CHAIN_0][6].bank = 4; 9084 rf_reg_record[CHAIN_0][6].reg = 34; 9085 rf_reg_record[CHAIN_0][6].value = rfvalue; 9086 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 9087 rf_reg_record[CHAIN_0][7].bank = 5; 9088 rf_reg_record[CHAIN_0][7].reg = 3; 9089 rf_reg_record[CHAIN_0][7].value = rfvalue; 9090 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 9091 rf_reg_record[CHAIN_0][8].bank = 5; 9092 rf_reg_record[CHAIN_0][8].reg = 4; 9093 rf_reg_record[CHAIN_0][8].value = rfvalue; 9094 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 9095 rf_reg_record[CHAIN_0][9].bank = 5; 9096 rf_reg_record[CHAIN_0][9].reg = 17; 9097 rf_reg_record[CHAIN_0][9].value = rfvalue; 9098 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 9099 rf_reg_record[CHAIN_0][10].bank = 5; 9100 rf_reg_record[CHAIN_0][10].reg = 18; 9101 rf_reg_record[CHAIN_0][10].value = rfvalue; 9102 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 9103 rf_reg_record[CHAIN_0][11].bank = 5; 9104 rf_reg_record[CHAIN_0][11].reg = 19; 9105 rf_reg_record[CHAIN_0][11].value = rfvalue; 9106 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 9107 rf_reg_record[CHAIN_0][12].bank = 5; 9108 rf_reg_record[CHAIN_0][12].reg = 20; 9109 rf_reg_record[CHAIN_0][12].value = rfvalue; 9110 } else if (chain == CHAIN_1) { 9111 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9112 rf_reg_record[CHAIN_1][0].bank = 0; 9113 rf_reg_record[CHAIN_1][0].reg = 1; 9114 rf_reg_record[CHAIN_1][0].value = rfvalue; 9115 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9116 rf_reg_record[CHAIN_1][1].bank = 0; 9117 rf_reg_record[CHAIN_1][1].reg = 2; 9118 rf_reg_record[CHAIN_1][1].value = rfvalue; 9119 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9120 rf_reg_record[CHAIN_1][2].bank = 0; 9121 rf_reg_record[CHAIN_1][2].reg = 35; 9122 rf_reg_record[CHAIN_1][2].value = rfvalue; 9123 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9124 rf_reg_record[CHAIN_1][3].bank = 0; 9125 rf_reg_record[CHAIN_1][3].reg = 42; 9126 rf_reg_record[CHAIN_1][3].value = rfvalue; 9127 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 9128 rf_reg_record[CHAIN_1][4].bank = 6; 9129 rf_reg_record[CHAIN_1][4].reg = 0; 9130 rf_reg_record[CHAIN_1][4].value = rfvalue; 9131 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2); 9132 rf_reg_record[CHAIN_1][5].bank = 6; 9133 rf_reg_record[CHAIN_1][5].reg = 2; 9134 rf_reg_record[CHAIN_1][5].value = rfvalue; 9135 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34); 9136 rf_reg_record[CHAIN_1][6].bank = 6; 9137 rf_reg_record[CHAIN_1][6].reg = 34; 9138 rf_reg_record[CHAIN_1][6].value = rfvalue; 9139 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 9140 rf_reg_record[CHAIN_1][7].bank = 7; 9141 rf_reg_record[CHAIN_1][7].reg = 3; 9142 rf_reg_record[CHAIN_1][7].value = rfvalue; 9143 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 9144 rf_reg_record[CHAIN_1][8].bank = 7; 9145 rf_reg_record[CHAIN_1][8].reg = 4; 9146 rf_reg_record[CHAIN_1][8].value = rfvalue; 9147 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 9148 rf_reg_record[CHAIN_1][9].bank = 7; 9149 rf_reg_record[CHAIN_1][9].reg = 17; 9150 rf_reg_record[CHAIN_1][9].value = rfvalue; 9151 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 9152 rf_reg_record[CHAIN_1][10].bank = 7; 9153 rf_reg_record[CHAIN_1][10].reg = 18; 9154 rf_reg_record[CHAIN_1][10].value = rfvalue; 9155 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 9156 rf_reg_record[CHAIN_1][11].bank = 7; 9157 rf_reg_record[CHAIN_1][11].reg = 19; 9158 rf_reg_record[CHAIN_1][11].value = rfvalue; 9159 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 9160 rf_reg_record[CHAIN_1][12].bank = 7; 9161 rf_reg_record[CHAIN_1][12].reg = 20; 9162 rf_reg_record[CHAIN_1][12].value = rfvalue; 9163 } else { 9164 rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain); 9165 } 9166 } 9167 9168 static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, 9169 struct rf_reg_pair rf_record[][13]) 9170 { 9171 u8 chain_index = 0, record_index = 0; 9172 u8 bank = 0, rf_register = 0, value = 0; 9173 9174 for (chain_index = 0; chain_index < 2; chain_index++) { 9175 for (record_index = 0; record_index < 13; record_index++) { 9176 bank = rf_record[chain_index][record_index].bank; 9177 rf_register = rf_record[chain_index][record_index].reg; 9178 value = rf_record[chain_index][record_index].value; 9179 rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value); 9180 rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", 9181 bank, rf_register, value); 9182 } 9183 } 9184 } 9185 9186 static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev) 9187 { 9188 rt2800_bbp_write(rt2x00dev, 158, 0xAA); 9189 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9190 9191 rt2800_bbp_write(rt2x00dev, 158, 0xAB); 9192 rt2800_bbp_write(rt2x00dev, 159, 0x0A); 9193 9194 rt2800_bbp_write(rt2x00dev, 158, 0xAC); 9195 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9196 9197 rt2800_bbp_write(rt2x00dev, 158, 0xAD); 9198 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9199 9200 rt2800_bbp_write(rt2x00dev, 244, 0x40); 9201 } 9202 9203 static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg) 9204 { 9205 u32 macvalue = 0; 9206 int fftout_i = 0, fftout_q = 0; 9207 u32 ptmp = 0, pint = 0; 9208 u8 bbp = 0; 9209 u8 tidxi; 9210 9211 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9212 rt2800_bbp_write(rt2x00dev, 159, 0x9b); 9213 9214 bbp = 0x9b; 9215 9216 while (bbp == 0x9b) { 9217 usleep_range(10, 50); 9218 bbp = rt2800_bbp_read(rt2x00dev, 159); 9219 bbp = bbp & 0xff; 9220 } 9221 9222 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9223 rt2800_bbp_write(rt2x00dev, 159, tidx); 9224 rt2800_bbp_write(rt2x00dev, 159, tidx); 9225 rt2800_bbp_write(rt2x00dev, 159, tidx); 9226 9227 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9228 9229 fftout_i = (macvalue >> 16); 9230 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9231 fftout_q = (macvalue & 0xffff); 9232 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9233 ptmp = (fftout_i * fftout_i); 9234 ptmp = ptmp + (fftout_q * fftout_q); 9235 pint = ptmp; 9236 rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint); 9237 if (read_neg) { 9238 pint = pint >> 1; 9239 tidxi = 0x40 - tidx; 9240 tidxi = tidxi & 0x3f; 9241 9242 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9243 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9244 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9245 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9246 9247 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9248 9249 fftout_i = (macvalue >> 16); 9250 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9251 fftout_q = (macvalue & 0xffff); 9252 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9253 ptmp = (fftout_i * fftout_i); 9254 ptmp = ptmp + (fftout_q * fftout_q); 9255 ptmp = ptmp >> 1; 9256 pint = pint + ptmp; 9257 } 9258 9259 return pint; 9260 } 9261 9262 static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) 9263 { 9264 u32 macvalue = 0; 9265 int fftout_i = 0, fftout_q = 0; 9266 u32 ptmp = 0, pint = 0; 9267 9268 rt2800_bbp_write(rt2x00dev, 158, 0xBA); 9269 rt2800_bbp_write(rt2x00dev, 159, tidx); 9270 rt2800_bbp_write(rt2x00dev, 159, tidx); 9271 rt2800_bbp_write(rt2x00dev, 159, tidx); 9272 9273 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9274 9275 fftout_i = (macvalue >> 16); 9276 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9277 fftout_q = (macvalue & 0xffff); 9278 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9279 ptmp = (fftout_i * fftout_i); 9280 ptmp = ptmp + (fftout_q * fftout_q); 9281 pint = ptmp; 9282 9283 return pint; 9284 } 9285 9286 static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc) 9287 { 9288 u8 bbp = 0; 9289 9290 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9291 bbp = alc | 0x80; 9292 rt2800_bbp_write(rt2x00dev, 159, bbp); 9293 9294 if (ch_idx == 0) 9295 bbp = (iorq == 0) ? 0xb1 : 0xb2; 9296 else 9297 bbp = (iorq == 0) ? 0xb8 : 0xb9; 9298 9299 rt2800_bbp_write(rt2x00dev, 158, bbp); 9300 bbp = dc; 9301 rt2800_bbp_write(rt2x00dev, 159, bbp); 9302 } 9303 9304 static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, 9305 u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2]) 9306 { 9307 u32 p0 = 0, p1 = 0, pf = 0; 9308 char idx0 = 0, idx1 = 0; 9309 u8 idxf[] = {0x00, 0x00}; 9310 u8 ibit = 0x20; 9311 u8 iorq; 9312 char bidx; 9313 9314 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9315 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9316 9317 for (bidx = 5; bidx >= 0; bidx--) { 9318 for (iorq = 0; iorq <= 1; iorq++) { 9319 if (idxf[iorq] == 0x20) { 9320 idx0 = 0x20; 9321 p0 = pf; 9322 } else { 9323 idx0 = idxf[iorq] - ibit; 9324 idx0 = idx0 & 0x3F; 9325 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0); 9326 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9327 } 9328 9329 idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit); 9330 idx1 = idx1 & 0x3F; 9331 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1); 9332 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9333 9334 rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", 9335 alc_idx, iorq, idxf[iorq]); 9336 rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n", 9337 p0, p1, pf, idx0, idx1, ibit); 9338 9339 if (bidx != 5 && pf <= p0 && pf < p1) { 9340 idxf[iorq] = idxf[iorq]; 9341 } else if (p0 < p1) { 9342 pf = p0; 9343 idxf[iorq] = idx0 & 0x3F; 9344 } else { 9345 pf = p1; 9346 idxf[iorq] = idx1 & 0x3F; 9347 } 9348 rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", 9349 iorq, iorq, idxf[iorq], pf); 9350 9351 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]); 9352 } 9353 ibit = ibit >> 1; 9354 } 9355 dc_result[ch_idx][alc_idx][0] = idxf[0]; 9356 dc_result[ch_idx][alc_idx][1] = idxf[1]; 9357 } 9358 9359 static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes) 9360 { 9361 u32 p0 = 0, p1 = 0, pf = 0; 9362 char perr = 0, gerr = 0, iq_err = 0; 9363 char pef = 0, gef = 0; 9364 char psta, pend; 9365 char gsta, gend; 9366 9367 u8 ibit = 0x20; 9368 u8 first_search = 0x00, touch_neg_max = 0x00; 9369 char idx0 = 0, idx1 = 0; 9370 u8 gop; 9371 u8 bbp = 0; 9372 char bidx; 9373 9374 for (bidx = 5; bidx >= 1; bidx--) { 9375 for (gop = 0; gop < 2; gop++) { 9376 if (gop == 1 || bidx < 4) { 9377 if (gop == 0) 9378 iq_err = gerr; 9379 else 9380 iq_err = perr; 9381 9382 first_search = (gop == 0) ? (bidx == 3) : (bidx == 5); 9383 touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : 9384 ((iq_err & 0x3F) == 0x20); 9385 9386 if (touch_neg_max) { 9387 p0 = pf; 9388 idx0 = iq_err; 9389 } else { 9390 idx0 = iq_err - ibit; 9391 bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) : 9392 ((gop == 0) ? 0x46 : 0x47); 9393 9394 rt2800_bbp_write(rt2x00dev, 158, bbp); 9395 rt2800_bbp_write(rt2x00dev, 159, idx0); 9396 9397 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9398 } 9399 9400 idx1 = iq_err + (first_search ? 0 : ibit); 9401 idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F); 9402 9403 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9404 (gop == 0) ? 0x46 : 0x47; 9405 9406 rt2800_bbp_write(rt2x00dev, 158, bbp); 9407 rt2800_bbp_write(rt2x00dev, 159, idx1); 9408 9409 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9410 9411 rt2x00_dbg(rt2x00dev, 9412 "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n", 9413 p0, p1, pf, idx0, idx1, iq_err, gop, ibit); 9414 9415 if (!(!first_search && pf <= p0 && pf < p1)) { 9416 if (p0 < p1) { 9417 pf = p0; 9418 iq_err = idx0; 9419 } else { 9420 pf = p1; 9421 iq_err = idx1; 9422 } 9423 } 9424 9425 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9426 (gop == 0) ? 0x46 : 0x47; 9427 9428 rt2800_bbp_write(rt2x00dev, 158, bbp); 9429 rt2800_bbp_write(rt2x00dev, 159, iq_err); 9430 9431 if (gop == 0) 9432 gerr = iq_err; 9433 else 9434 perr = iq_err; 9435 9436 rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", 9437 pf, gerr & 0x0F, perr & 0x3F); 9438 } 9439 } 9440 9441 if (bidx > 0) 9442 ibit = (ibit >> 1); 9443 } 9444 gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F); 9445 perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F); 9446 9447 gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr; 9448 gsta = gerr - 1; 9449 gend = gerr + 2; 9450 9451 perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr; 9452 psta = perr - 1; 9453 pend = perr + 2; 9454 9455 for (gef = gsta; gef <= gend; gef = gef + 1) 9456 for (pef = psta; pef <= pend; pef = pef + 1) { 9457 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9458 rt2800_bbp_write(rt2x00dev, 158, bbp); 9459 rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F); 9460 9461 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9462 rt2800_bbp_write(rt2x00dev, 158, bbp); 9463 rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F); 9464 9465 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9466 if (gef == gsta && pef == psta) { 9467 pf = p1; 9468 gerr = gef; 9469 perr = pef; 9470 } else if (pf > p1) { 9471 pf = p1; 9472 gerr = gef; 9473 perr = pef; 9474 } 9475 rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", 9476 p1, pf, gef & 0x0F, pef & 0x3F); 9477 } 9478 9479 ges[ch_idx] = gerr & 0x0F; 9480 pes[ch_idx] = perr & 0x3F; 9481 } 9482 9483 static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev) 9484 { 9485 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21); 9486 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10); 9487 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9488 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b); 9489 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81); 9490 rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81); 9491 rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee); 9492 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d); 9493 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d); 9494 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 9495 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7); 9496 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2); 9497 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 9498 } 9499 9500 static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev) 9501 { 9502 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22); 9503 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20); 9504 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9505 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b); 9506 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81); 9507 rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81); 9508 rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee); 9509 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d); 9510 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d); 9511 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80); 9512 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7); 9513 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2); 9514 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20); 9515 } 9516 9517 static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev) 9518 { 9519 struct rf_reg_pair rf_store[CHAIN_NUM][13]; 9520 u32 macorg1 = 0; 9521 u32 macorg2 = 0; 9522 u32 macorg3 = 0; 9523 u32 macorg4 = 0; 9524 u32 macorg5 = 0; 9525 u32 orig528 = 0; 9526 u32 orig52c = 0; 9527 9528 u32 savemacsysctrl = 0; 9529 u32 macvalue = 0; 9530 u32 mac13b8 = 0; 9531 u32 p0 = 0, p1 = 0; 9532 u32 p0_idx10 = 0, p1_idx10 = 0; 9533 9534 u8 rfvalue; 9535 u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2]; 9536 u8 ger[CHAIN_NUM], per[CHAIN_NUM]; 9537 9538 u8 vga_gain[] = {14, 14}; 9539 u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0; 9540 u8 bbpr30, rfb0r39, rfb0r42; 9541 u8 bbpr1; 9542 u8 bbpr4; 9543 u8 bbpr241, bbpr242; 9544 u8 count_step; 9545 9546 static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c}; 9547 static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 9548 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F}; 9549 static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08}; 9550 9551 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9552 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9553 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9554 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9555 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9556 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9557 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9558 orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 9559 orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 9560 9561 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9562 macvalue &= (~0x04); 9563 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9564 9565 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9566 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9567 9568 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9569 macvalue &= (~0x08); 9570 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9571 9572 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9573 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9574 9575 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9576 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9577 9578 bbpr30 = rt2800_bbp_read(rt2x00dev, 30); 9579 rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39); 9580 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9581 9582 rt2800_bbp_write(rt2x00dev, 30, 0x1F); 9583 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80); 9584 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B); 9585 9586 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9587 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9588 9589 rt2800_setbbptonegenerator(rt2x00dev); 9590 9591 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9592 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9593 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9594 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00); 9595 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9596 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9597 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9598 rt2800_register_write(rt2x00dev, 0x13b8, 0x10); 9599 udelay(1); 9600 9601 if (ch_idx == 0) 9602 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9603 else 9604 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9605 9606 udelay(1); 9607 9608 if (ch_idx == 0) 9609 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9610 else 9611 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9612 9613 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9614 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9615 9616 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9617 if (ch_idx == 0) 9618 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9619 else 9620 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9621 9622 vga_gain[ch_idx] = 18; 9623 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9624 rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]); 9625 rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]); 9626 9627 macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9628 macvalue &= (~0x0000F1F1); 9629 macvalue |= (rf_gain[rf_alc_idx] << 4); 9630 macvalue |= (rf_gain[rf_alc_idx] << 12); 9631 rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue); 9632 macvalue = (0x0000F1F1); 9633 rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue); 9634 9635 if (rf_alc_idx == 0) { 9636 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21); 9637 for (; vga_gain[ch_idx] > 0; 9638 vga_gain[ch_idx] = vga_gain[ch_idx] - 2) { 9639 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9640 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9641 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9642 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9643 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9644 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9645 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21); 9646 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9647 rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1); 9648 if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000))) 9649 break; 9650 } 9651 9652 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9653 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9654 9655 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9656 rfvga_gain_table[vga_gain[ch_idx]]); 9657 9658 if (vga_gain[ch_idx] < 0) 9659 vga_gain[ch_idx] = 0; 9660 } 9661 9662 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9663 9664 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9665 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9666 9667 rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result); 9668 } 9669 } 9670 9671 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9672 for (idx = 0; idx < 4; idx++) { 9673 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9674 bbp = (idx << 2) + rf_alc_idx; 9675 rt2800_bbp_write(rt2x00dev, 159, bbp); 9676 rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp); 9677 9678 rt2800_bbp_write(rt2x00dev, 158, 0xb1); 9679 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00]; 9680 bbp = bbp & 0x3F; 9681 rt2800_bbp_write(rt2x00dev, 159, bbp); 9682 rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp); 9683 9684 rt2800_bbp_write(rt2x00dev, 158, 0xb2); 9685 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01]; 9686 bbp = bbp & 0x3F; 9687 rt2800_bbp_write(rt2x00dev, 159, bbp); 9688 rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp); 9689 9690 rt2800_bbp_write(rt2x00dev, 158, 0xb8); 9691 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00]; 9692 bbp = bbp & 0x3F; 9693 rt2800_bbp_write(rt2x00dev, 159, bbp); 9694 rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp); 9695 9696 rt2800_bbp_write(rt2x00dev, 158, 0xb9); 9697 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01]; 9698 bbp = bbp & 0x3F; 9699 rt2800_bbp_write(rt2x00dev, 159, bbp); 9700 rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp); 9701 } 9702 } 9703 9704 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9705 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9706 9707 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9708 9709 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9710 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9711 9712 bbp = 0x00; 9713 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9714 9715 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9716 udelay(1); 9717 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9718 9719 rt2800_rf_configrecover(rt2x00dev, rf_store); 9720 9721 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9722 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9723 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9724 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9725 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9726 udelay(1); 9727 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9728 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9729 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9730 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9731 rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528); 9732 rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c); 9733 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9734 9735 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9736 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9737 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9738 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9739 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9740 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9741 9742 bbpr1 = rt2800_bbp_read(rt2x00dev, 1); 9743 bbpr4 = rt2800_bbp_read(rt2x00dev, 4); 9744 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 9745 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 9746 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9747 9748 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9749 macvalue &= (~0x04); 9750 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9751 9752 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9753 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9754 9755 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9756 macvalue &= (~0x08); 9757 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9758 9759 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9760 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9761 9762 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9763 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101); 9764 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9765 } 9766 9767 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9768 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9769 9770 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9771 rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18)); 9772 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9773 udelay(1); 9774 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9775 9776 rt2800_bbp_write(rt2x00dev, 241, 0x14); 9777 rt2800_bbp_write(rt2x00dev, 242, 0x80); 9778 rt2800_bbp_write(rt2x00dev, 244, 0x31); 9779 } else { 9780 rt2800_setbbptonegenerator(rt2x00dev); 9781 } 9782 9783 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9784 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9785 udelay(1); 9786 9787 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9788 9789 if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9790 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000); 9791 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9792 } 9793 9794 rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010); 9795 9796 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9797 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9798 9799 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B); 9800 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B); 9801 9802 rt2800_bbp_write(rt2x00dev, 158, 0x03); 9803 rt2800_bbp_write(rt2x00dev, 159, 0x60); 9804 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9805 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9806 9807 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9808 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9809 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9810 9811 if (ch_idx == 0) { 9812 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9813 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9814 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9815 bbp = bbpr1 & (~0x18); 9816 bbp = bbp | 0x00; 9817 rt2800_bbp_write(rt2x00dev, 1, bbp); 9818 } 9819 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9820 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9821 } else { 9822 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9823 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9824 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) { 9825 bbp = bbpr1 & (~0x18); 9826 bbp = bbp | 0x08; 9827 rt2800_bbp_write(rt2x00dev, 1, bbp); 9828 } 9829 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9830 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9831 } 9832 9833 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9834 rt2800_bbp_write(rt2x00dev, 159, 0x04); 9835 9836 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9837 rt2800_bbp_write(rt2x00dev, 158, bbp); 9838 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9839 9840 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9841 rt2800_bbp_write(rt2x00dev, 23, 0x06); 9842 rt2800_bbp_write(rt2x00dev, 24, 0x06); 9843 count_step = 1; 9844 } else { 9845 rt2800_bbp_write(rt2x00dev, 23, 0x1F); 9846 rt2800_bbp_write(rt2x00dev, 24, 0x1F); 9847 count_step = 2; 9848 } 9849 9850 for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) { 9851 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9852 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9853 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9854 9855 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9856 rt2800_bbp_write(rt2x00dev, 158, bbp); 9857 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9858 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9859 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9860 p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9861 9862 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9863 rt2800_bbp_write(rt2x00dev, 158, bbp); 9864 rt2800_bbp_write(rt2x00dev, 159, 0x21); 9865 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9866 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) 9867 p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9868 9869 rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1); 9870 9871 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9872 rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10); 9873 if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) { 9874 if (vga_gain[ch_idx] != 0) 9875 vga_gain[ch_idx] = vga_gain[ch_idx] - 1; 9876 break; 9877 } 9878 } 9879 9880 if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500)) 9881 break; 9882 } 9883 9884 if (vga_gain[ch_idx] > 18) 9885 vga_gain[ch_idx] = 18; 9886 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9887 rfvga_gain_table[vga_gain[ch_idx]]); 9888 9889 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9890 rt2800_bbp_write(rt2x00dev, 158, bbp); 9891 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9892 9893 rt2800_iq_search(rt2x00dev, ch_idx, ger, per); 9894 } 9895 9896 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9897 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9898 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9899 9900 rt2800_bbp_write(rt2x00dev, 158, 0x28); 9901 bbp = ger[CHAIN_0] & 0x0F; 9902 rt2800_bbp_write(rt2x00dev, 159, bbp); 9903 9904 rt2800_bbp_write(rt2x00dev, 158, 0x29); 9905 bbp = per[CHAIN_0] & 0x3F; 9906 rt2800_bbp_write(rt2x00dev, 159, bbp); 9907 9908 rt2800_bbp_write(rt2x00dev, 158, 0x46); 9909 bbp = ger[CHAIN_1] & 0x0F; 9910 rt2800_bbp_write(rt2x00dev, 159, bbp); 9911 9912 rt2800_bbp_write(rt2x00dev, 158, 0x47); 9913 bbp = per[CHAIN_1] & 0x3F; 9914 rt2800_bbp_write(rt2x00dev, 159, bbp); 9915 9916 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9917 rt2800_bbp_write(rt2x00dev, 1, bbpr1); 9918 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9919 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9920 } 9921 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9922 9923 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9924 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9925 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9926 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9927 9928 rt2800_bbp_write(rt2x00dev, 30, bbpr30); 9929 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39); 9930 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9931 9932 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9933 rt2800_bbp_write(rt2x00dev, 4, bbpr4); 9934 9935 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9936 udelay(1); 9937 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9938 9939 rt2800_rf_configrecover(rt2x00dev, rf_store); 9940 9941 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9942 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9943 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9944 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9945 udelay(1); 9946 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9947 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9948 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9949 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9950 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9951 } 9952 9953 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 9954 bool set_bw, bool is_ht40) 9955 { 9956 u8 bbp_val; 9957 9958 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 9959 bbp_val |= 0x1; 9960 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 9961 usleep_range(100, 200); 9962 9963 if (set_bw) { 9964 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 9965 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 9966 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 9967 usleep_range(100, 200); 9968 } 9969 9970 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 9971 bbp_val &= (~0x1); 9972 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 9973 usleep_range(100, 200); 9974 } 9975 9976 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 9977 { 9978 u8 rf_val; 9979 9980 if (btxcal) 9981 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9982 else 9983 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 9984 9985 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 9986 9987 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 9988 rf_val |= 0x80; 9989 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 9990 9991 if (btxcal) { 9992 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 9993 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 9994 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 9995 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 9996 rf_val &= (~0x3F); 9997 rf_val |= 0x3F; 9998 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 9999 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10000 rf_val &= (~0x3F); 10001 rf_val |= 0x3F; 10002 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10003 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 10004 } else { 10005 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 10006 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 10007 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 10008 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10009 rf_val &= (~0x3F); 10010 rf_val |= 0x34; 10011 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 10012 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10013 rf_val &= (~0x3F); 10014 rf_val |= 0x34; 10015 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10016 } 10017 10018 return 0; 10019 } 10020 10021 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 10022 { 10023 unsigned int cnt; 10024 u8 bbp_val; 10025 char cal_val; 10026 10027 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 10028 10029 cnt = 0; 10030 do { 10031 usleep_range(500, 2000); 10032 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 10033 if (bbp_val == 0x02 || cnt == 20) 10034 break; 10035 10036 cnt++; 10037 } while (cnt < 20); 10038 10039 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 10040 cal_val = bbp_val & 0x7F; 10041 if (cal_val >= 0x40) 10042 cal_val -= 128; 10043 10044 return cal_val; 10045 } 10046 10047 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 10048 bool btxcal) 10049 { 10050 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10051 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 10052 u8 filter_target; 10053 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 10054 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 10055 int loop = 0, is_ht40, cnt; 10056 u8 bbp_val, rf_val; 10057 char cal_r32_init, cal_r32_val, cal_diff; 10058 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 10059 u8 saverfb5r06, saverfb5r07; 10060 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 10061 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 10062 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 10063 u8 saverfb5r58, saverfb5r59; 10064 u8 savebbp159r0, savebbp159r2, savebbpr23; 10065 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 10066 10067 /* Save MAC registers */ 10068 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 10069 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 10070 10071 /* save BBP registers */ 10072 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 10073 10074 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 10075 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10076 10077 /* Save RF registers */ 10078 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10079 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10080 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10081 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10082 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 10083 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10084 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10085 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10086 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 10087 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 10088 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 10089 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 10090 10091 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 10092 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 10093 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 10094 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 10095 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 10096 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 10097 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 10098 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 10099 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 10100 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 10101 10102 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10103 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10104 10105 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10106 rf_val |= 0x3; 10107 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10108 10109 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10110 rf_val |= 0x1; 10111 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 10112 10113 cnt = 0; 10114 do { 10115 usleep_range(500, 2000); 10116 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10117 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 10118 break; 10119 cnt++; 10120 } while (cnt < 40); 10121 10122 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10123 rf_val &= (~0x3); 10124 rf_val |= 0x1; 10125 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10126 10127 /* I-3 */ 10128 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 10129 bbp_val &= (~0x1F); 10130 bbp_val |= 0x10; 10131 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 10132 10133 do { 10134 /* I-4,5,6,7,8,9 */ 10135 if (loop == 0) { 10136 is_ht40 = false; 10137 10138 if (btxcal) 10139 filter_target = tx_filter_target_20m; 10140 else 10141 filter_target = rx_filter_target_20m; 10142 } else { 10143 is_ht40 = true; 10144 10145 if (btxcal) 10146 filter_target = tx_filter_target_40m; 10147 else 10148 filter_target = rx_filter_target_40m; 10149 } 10150 10151 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10152 rf_val &= (~0x04); 10153 if (loop == 1) 10154 rf_val |= 0x4; 10155 10156 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 10157 10158 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 10159 10160 rt2800_rf_lp_config(rt2x00dev, btxcal); 10161 if (btxcal) { 10162 tx_agc_fc = 0; 10163 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10164 rf_val &= (~0x7F); 10165 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10166 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10167 rf_val &= (~0x7F); 10168 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10169 } else { 10170 rx_agc_fc = 0; 10171 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10172 rf_val &= (~0x7F); 10173 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10174 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10175 rf_val &= (~0x7F); 10176 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10177 } 10178 10179 usleep_range(1000, 2000); 10180 10181 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10182 bbp_val &= (~0x6); 10183 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10184 10185 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10186 10187 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10188 10189 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10190 bbp_val |= 0x6; 10191 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10192 do_cal: 10193 if (btxcal) { 10194 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10195 rf_val &= (~0x7F); 10196 rf_val |= tx_agc_fc; 10197 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10198 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10199 rf_val &= (~0x7F); 10200 rf_val |= tx_agc_fc; 10201 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10202 } else { 10203 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10204 rf_val &= (~0x7F); 10205 rf_val |= rx_agc_fc; 10206 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10207 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10208 rf_val &= (~0x7F); 10209 rf_val |= rx_agc_fc; 10210 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10211 } 10212 10213 usleep_range(500, 1000); 10214 10215 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10216 10217 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10218 10219 cal_diff = cal_r32_init - cal_r32_val; 10220 10221 if (btxcal) 10222 cmm_agc_fc = tx_agc_fc; 10223 else 10224 cmm_agc_fc = rx_agc_fc; 10225 10226 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 10227 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 10228 if (btxcal) 10229 tx_agc_fc = 0; 10230 else 10231 rx_agc_fc = 0; 10232 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 10233 if (btxcal) 10234 tx_agc_fc++; 10235 else 10236 rx_agc_fc++; 10237 goto do_cal; 10238 } 10239 10240 if (btxcal) { 10241 if (loop == 0) 10242 drv_data->tx_calibration_bw20 = tx_agc_fc; 10243 else 10244 drv_data->tx_calibration_bw40 = tx_agc_fc; 10245 } else { 10246 if (loop == 0) 10247 drv_data->rx_calibration_bw20 = rx_agc_fc; 10248 else 10249 drv_data->rx_calibration_bw40 = rx_agc_fc; 10250 } 10251 10252 loop++; 10253 } while (loop <= 1); 10254 10255 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 10256 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 10257 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 10258 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 10259 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 10260 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 10261 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 10262 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 10263 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 10264 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 10265 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 10266 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 10267 10268 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 10269 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 10270 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 10271 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 10272 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 10273 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 10274 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 10275 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 10276 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 10277 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 10278 10279 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 10280 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 10281 10282 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 10283 10284 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 10285 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 10286 10287 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 10288 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 10289 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 10290 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 10291 10292 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 10293 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 10294 } 10295 10296 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 10297 { 10298 /* Initialize RF central register to default value */ 10299 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 10300 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 10301 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 10302 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 10303 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 10304 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 10305 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 10306 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 10307 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 10308 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 10309 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 10310 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 10311 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 10312 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10313 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 10314 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 10315 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 10316 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 10317 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 10318 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 10319 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 10320 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 10321 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 10322 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 10323 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 10324 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 10325 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 10326 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10327 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 10328 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 10329 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 10330 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 10331 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 10332 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 10333 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 10334 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 10335 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 10336 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 10337 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 10338 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 10339 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 10340 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 10341 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 10342 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 10343 10344 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 10345 if (rt2800_clk_is_20mhz(rt2x00dev)) 10346 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 10347 else 10348 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10349 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 10350 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 10351 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 10352 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 10353 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 10354 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 10355 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 10356 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 10357 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 10358 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 10359 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 10360 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 10361 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10362 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 10363 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 10364 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 10365 10366 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 10367 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 10368 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 10369 10370 /* Initialize RF channel register to default value */ 10371 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 10372 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 10373 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 10374 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 10375 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 10376 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 10377 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 10378 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 10379 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 10380 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 10381 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 10382 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10383 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 10384 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 10385 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10386 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 10387 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 10388 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 10389 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 10390 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10391 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 10392 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 10393 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 10394 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 10395 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 10396 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 10397 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 10398 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 10399 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 10400 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 10401 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 10402 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 10403 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 10404 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 10405 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 10406 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 10407 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 10408 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 10409 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 10410 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 10411 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 10412 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 10413 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 10414 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 10415 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 10416 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10417 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 10418 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 10419 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 10420 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 10421 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 10422 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 10423 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 10424 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 10425 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 10426 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 10427 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 10428 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 10429 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 10430 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 10431 10432 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 10433 10434 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 10435 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 10436 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 10437 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 10438 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 10439 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 10440 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 10441 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 10442 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 10443 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 10444 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 10445 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 10446 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 10447 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 10448 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10449 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 10450 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10451 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 10452 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 10453 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 10454 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 10455 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 10456 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 10457 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10458 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 10459 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 10460 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 10461 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10462 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 10463 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 10464 10465 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 10466 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10467 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10468 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 10469 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 10470 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 10471 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 10472 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10473 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 10474 10475 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 10476 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 10477 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 10478 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 10479 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10480 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10481 10482 /* Initialize RF channel register for DRQFN */ 10483 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10484 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 10485 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 10486 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 10487 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 10488 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 10489 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 10490 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 10491 10492 /* Initialize RF DC calibration register to default value */ 10493 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 10494 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 10495 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 10496 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 10497 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 10498 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10499 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 10500 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 10501 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 10502 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 10503 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 10504 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 10505 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 10506 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 10507 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 10508 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 10509 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 10510 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 10511 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 10512 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 10513 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 10514 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 10515 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 10516 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 10517 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 10518 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 10519 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 10520 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 10521 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 10522 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 10523 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 10524 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 10525 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 10526 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 10527 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 10528 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 10529 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 10530 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 10531 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 10532 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 10533 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 10534 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 10535 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 10536 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 10537 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 10538 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 10539 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 10540 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 10541 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 10542 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 10543 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 10544 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 10545 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 10546 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 10547 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 10548 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 10549 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 10550 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 10551 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 10552 10553 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 10554 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 10555 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 10556 10557 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10558 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 10559 10560 rt2800_r_calibration(rt2x00dev); 10561 rt2800_rf_self_txdc_cal(rt2x00dev); 10562 rt2800_rxdcoc_calibration(rt2x00dev); 10563 rt2800_bw_filter_calibration(rt2x00dev, true); 10564 rt2800_bw_filter_calibration(rt2x00dev, false); 10565 rt2800_loft_iq_calibration(rt2x00dev); 10566 rt2800_rxiq_calibration(rt2x00dev); 10567 } 10568 10569 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 10570 { 10571 if (rt2800_is_305x_soc(rt2x00dev)) { 10572 rt2800_init_rfcsr_305x_soc(rt2x00dev); 10573 return; 10574 } 10575 10576 switch (rt2x00dev->chip.rt) { 10577 case RT3070: 10578 case RT3071: 10579 case RT3090: 10580 rt2800_init_rfcsr_30xx(rt2x00dev); 10581 break; 10582 case RT3290: 10583 rt2800_init_rfcsr_3290(rt2x00dev); 10584 break; 10585 case RT3352: 10586 rt2800_init_rfcsr_3352(rt2x00dev); 10587 break; 10588 case RT3390: 10589 rt2800_init_rfcsr_3390(rt2x00dev); 10590 break; 10591 case RT3883: 10592 rt2800_init_rfcsr_3883(rt2x00dev); 10593 break; 10594 case RT3572: 10595 rt2800_init_rfcsr_3572(rt2x00dev); 10596 break; 10597 case RT3593: 10598 rt2800_init_rfcsr_3593(rt2x00dev); 10599 break; 10600 case RT5350: 10601 rt2800_init_rfcsr_5350(rt2x00dev); 10602 break; 10603 case RT5390: 10604 rt2800_init_rfcsr_5390(rt2x00dev); 10605 break; 10606 case RT5392: 10607 rt2800_init_rfcsr_5392(rt2x00dev); 10608 break; 10609 case RT5592: 10610 rt2800_init_rfcsr_5592(rt2x00dev); 10611 break; 10612 case RT6352: 10613 rt2800_init_rfcsr_6352(rt2x00dev); 10614 break; 10615 } 10616 } 10617 10618 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 10619 { 10620 u32 reg; 10621 u16 word; 10622 10623 /* 10624 * Initialize MAC registers. 10625 */ 10626 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 10627 rt2800_init_registers(rt2x00dev))) 10628 return -EIO; 10629 10630 /* 10631 * Wait BBP/RF to wake up. 10632 */ 10633 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 10634 return -EIO; 10635 10636 /* 10637 * Send signal during boot time to initialize firmware. 10638 */ 10639 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 10640 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 10641 if (rt2x00_is_usb(rt2x00dev)) 10642 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 10643 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 10644 msleep(1); 10645 10646 /* 10647 * Make sure BBP is up and running. 10648 */ 10649 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 10650 return -EIO; 10651 10652 /* 10653 * Initialize BBP/RF registers. 10654 */ 10655 rt2800_init_bbp(rt2x00dev); 10656 rt2800_init_rfcsr(rt2x00dev); 10657 10658 if (rt2x00_is_usb(rt2x00dev) && 10659 (rt2x00_rt(rt2x00dev, RT3070) || 10660 rt2x00_rt(rt2x00dev, RT3071) || 10661 rt2x00_rt(rt2x00dev, RT3572))) { 10662 udelay(200); 10663 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 10664 udelay(10); 10665 } 10666 10667 /* 10668 * Enable RX. 10669 */ 10670 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10671 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10672 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10673 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10674 10675 udelay(50); 10676 10677 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 10678 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 10679 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 10680 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 10681 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 10682 10683 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10684 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10685 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 10686 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10687 10688 /* 10689 * Initialize LED control 10690 */ 10691 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 10692 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 10693 word & 0xff, (word >> 8) & 0xff); 10694 10695 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 10696 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 10697 word & 0xff, (word >> 8) & 0xff); 10698 10699 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 10700 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 10701 word & 0xff, (word >> 8) & 0xff); 10702 10703 return 0; 10704 } 10705 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 10706 10707 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 10708 { 10709 u32 reg; 10710 10711 rt2800_disable_wpdma(rt2x00dev); 10712 10713 /* Wait for DMA, ignore error */ 10714 rt2800_wait_wpdma_ready(rt2x00dev); 10715 10716 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10717 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 10718 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10719 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10720 } 10721 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 10722 10723 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 10724 { 10725 u32 reg; 10726 u16 efuse_ctrl_reg; 10727 10728 if (rt2x00_rt(rt2x00dev, RT3290)) 10729 efuse_ctrl_reg = EFUSE_CTRL_3290; 10730 else 10731 efuse_ctrl_reg = EFUSE_CTRL; 10732 10733 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 10734 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 10735 } 10736 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 10737 10738 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 10739 { 10740 u32 reg; 10741 u16 efuse_ctrl_reg; 10742 u16 efuse_data0_reg; 10743 u16 efuse_data1_reg; 10744 u16 efuse_data2_reg; 10745 u16 efuse_data3_reg; 10746 10747 if (rt2x00_rt(rt2x00dev, RT3290)) { 10748 efuse_ctrl_reg = EFUSE_CTRL_3290; 10749 efuse_data0_reg = EFUSE_DATA0_3290; 10750 efuse_data1_reg = EFUSE_DATA1_3290; 10751 efuse_data2_reg = EFUSE_DATA2_3290; 10752 efuse_data3_reg = EFUSE_DATA3_3290; 10753 } else { 10754 efuse_ctrl_reg = EFUSE_CTRL; 10755 efuse_data0_reg = EFUSE_DATA0; 10756 efuse_data1_reg = EFUSE_DATA1; 10757 efuse_data2_reg = EFUSE_DATA2; 10758 efuse_data3_reg = EFUSE_DATA3; 10759 } 10760 mutex_lock(&rt2x00dev->csr_mutex); 10761 10762 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 10763 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 10764 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 10765 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 10766 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 10767 10768 /* Wait until the EEPROM has been loaded */ 10769 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 10770 /* Apparently the data is read from end to start */ 10771 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 10772 /* The returned value is in CPU order, but eeprom is le */ 10773 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 10774 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 10775 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 10776 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 10777 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 10778 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 10779 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 10780 10781 mutex_unlock(&rt2x00dev->csr_mutex); 10782 } 10783 10784 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 10785 { 10786 unsigned int i; 10787 10788 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 10789 rt2800_efuse_read(rt2x00dev, i); 10790 10791 return 0; 10792 } 10793 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 10794 10795 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 10796 { 10797 u16 word; 10798 10799 if (rt2x00_rt(rt2x00dev, RT3593) || 10800 rt2x00_rt(rt2x00dev, RT3883)) 10801 return 0; 10802 10803 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 10804 if ((word & 0x00ff) != 0x00ff) 10805 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 10806 10807 return 0; 10808 } 10809 10810 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 10811 { 10812 u16 word; 10813 10814 if (rt2x00_rt(rt2x00dev, RT3593) || 10815 rt2x00_rt(rt2x00dev, RT3883)) 10816 return 0; 10817 10818 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 10819 if ((word & 0x00ff) != 0x00ff) 10820 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 10821 10822 return 0; 10823 } 10824 10825 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 10826 { 10827 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10828 u16 word; 10829 u8 *mac; 10830 u8 default_lna_gain; 10831 int retval; 10832 10833 /* 10834 * Read the EEPROM. 10835 */ 10836 retval = rt2800_read_eeprom(rt2x00dev); 10837 if (retval) 10838 return retval; 10839 10840 /* 10841 * Start validation of the data that has been read. 10842 */ 10843 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 10844 rt2x00lib_set_mac_address(rt2x00dev, mac); 10845 10846 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 10847 if (word == 0xffff) { 10848 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10849 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 10850 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 10851 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10852 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 10853 } else if (rt2x00_rt(rt2x00dev, RT2860) || 10854 rt2x00_rt(rt2x00dev, RT2872)) { 10855 /* 10856 * There is a max of 2 RX streams for RT28x0 series 10857 */ 10858 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 10859 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10860 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10861 } 10862 10863 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 10864 if (word == 0xffff) { 10865 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 10866 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 10867 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 10868 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 10869 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 10870 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 10871 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 10872 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 10873 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 10874 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 10875 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 10876 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 10877 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 10878 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 10879 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 10880 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 10881 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 10882 } 10883 10884 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 10885 if ((word & 0x00ff) == 0x00ff) { 10886 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 10887 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 10888 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 10889 } 10890 if ((word & 0xff00) == 0xff00) { 10891 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 10892 LED_MODE_TXRX_ACTIVITY); 10893 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 10894 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 10895 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 10896 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 10897 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 10898 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 10899 } 10900 10901 /* 10902 * During the LNA validation we are going to use 10903 * lna0 as correct value. Note that EEPROM_LNA 10904 * is never validated. 10905 */ 10906 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 10907 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 10908 10909 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 10910 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 10911 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 10912 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 10913 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 10914 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 10915 10916 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 10917 10918 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 10919 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 10920 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 10921 if (!rt2x00_rt(rt2x00dev, RT3593) && 10922 !rt2x00_rt(rt2x00dev, RT3883)) { 10923 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 10924 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 10925 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 10926 default_lna_gain); 10927 } 10928 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 10929 10930 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 10931 10932 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 10933 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 10934 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 10935 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 10936 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 10937 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 10938 10939 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 10940 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 10941 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 10942 if (!rt2x00_rt(rt2x00dev, RT3593) && 10943 !rt2x00_rt(rt2x00dev, RT3883)) { 10944 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 10945 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 10946 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 10947 default_lna_gain); 10948 } 10949 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 10950 10951 if (rt2x00_rt(rt2x00dev, RT3593) || 10952 rt2x00_rt(rt2x00dev, RT3883)) { 10953 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 10954 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 10955 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 10956 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 10957 default_lna_gain); 10958 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 10959 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 10960 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 10961 default_lna_gain); 10962 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 10963 } 10964 10965 return 0; 10966 } 10967 10968 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 10969 { 10970 u16 value; 10971 u16 eeprom; 10972 u16 rf; 10973 10974 /* 10975 * Read EEPROM word for configuration. 10976 */ 10977 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 10978 10979 /* 10980 * Identify RF chipset by EEPROM value 10981 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 10982 * RT53xx: defined in "EEPROM_CHIP_ID" field 10983 */ 10984 if (rt2x00_rt(rt2x00dev, RT3290) || 10985 rt2x00_rt(rt2x00dev, RT5390) || 10986 rt2x00_rt(rt2x00dev, RT5392) || 10987 rt2x00_rt(rt2x00dev, RT6352)) 10988 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 10989 else if (rt2x00_rt(rt2x00dev, RT3352)) 10990 rf = RF3322; 10991 else if (rt2x00_rt(rt2x00dev, RT3883)) 10992 rf = RF3853; 10993 else if (rt2x00_rt(rt2x00dev, RT5350)) 10994 rf = RF5350; 10995 else if (rt2x00_rt(rt2x00dev, RT5592)) 10996 rf = RF5592; 10997 else 10998 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 10999 11000 switch (rf) { 11001 case RF2820: 11002 case RF2850: 11003 case RF2720: 11004 case RF2750: 11005 case RF3020: 11006 case RF2020: 11007 case RF3021: 11008 case RF3022: 11009 case RF3052: 11010 case RF3053: 11011 case RF3070: 11012 case RF3290: 11013 case RF3320: 11014 case RF3322: 11015 case RF3853: 11016 case RF5350: 11017 case RF5360: 11018 case RF5362: 11019 case RF5370: 11020 case RF5372: 11021 case RF5390: 11022 case RF5392: 11023 case RF5592: 11024 case RF7620: 11025 break; 11026 default: 11027 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 11028 rf); 11029 return -ENODEV; 11030 } 11031 11032 rt2x00_set_rf(rt2x00dev, rf); 11033 11034 /* 11035 * Identify default antenna configuration. 11036 */ 11037 rt2x00dev->default_ant.tx_chain_num = 11038 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 11039 rt2x00dev->default_ant.rx_chain_num = 11040 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 11041 11042 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11043 11044 if (rt2x00_rt(rt2x00dev, RT3070) || 11045 rt2x00_rt(rt2x00dev, RT3090) || 11046 rt2x00_rt(rt2x00dev, RT3352) || 11047 rt2x00_rt(rt2x00dev, RT3390)) { 11048 value = rt2x00_get_field16(eeprom, 11049 EEPROM_NIC_CONF1_ANT_DIVERSITY); 11050 switch (value) { 11051 case 0: 11052 case 1: 11053 case 2: 11054 rt2x00dev->default_ant.tx = ANTENNA_A; 11055 rt2x00dev->default_ant.rx = ANTENNA_A; 11056 break; 11057 case 3: 11058 rt2x00dev->default_ant.tx = ANTENNA_A; 11059 rt2x00dev->default_ant.rx = ANTENNA_B; 11060 break; 11061 } 11062 } else { 11063 rt2x00dev->default_ant.tx = ANTENNA_A; 11064 rt2x00dev->default_ant.rx = ANTENNA_A; 11065 } 11066 11067 /* These chips have hardware RX antenna diversity */ 11068 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 11069 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 11070 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 11071 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 11072 } 11073 11074 /* 11075 * Determine external LNA informations. 11076 */ 11077 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 11078 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 11079 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 11080 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 11081 11082 /* 11083 * Detect if this device has an hardware controlled radio. 11084 */ 11085 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 11086 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 11087 11088 /* 11089 * Detect if this device has Bluetooth co-existence. 11090 */ 11091 if (!rt2x00_rt(rt2x00dev, RT3352) && 11092 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 11093 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 11094 11095 /* 11096 * Read frequency offset and RF programming sequence. 11097 */ 11098 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 11099 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 11100 11101 /* 11102 * Store led settings, for correct led behaviour. 11103 */ 11104 #ifdef CONFIG_RT2X00_LIB_LEDS 11105 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 11106 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 11107 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 11108 11109 rt2x00dev->led_mcu_reg = eeprom; 11110 #endif /* CONFIG_RT2X00_LIB_LEDS */ 11111 11112 /* 11113 * Check if support EIRP tx power limit feature. 11114 */ 11115 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 11116 11117 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 11118 EIRP_MAX_TX_POWER_LIMIT) 11119 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 11120 11121 /* 11122 * Detect if device uses internal or external PA 11123 */ 11124 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11125 11126 if (rt2x00_rt(rt2x00dev, RT3352) || 11127 rt2x00_rt(rt2x00dev, RT6352)) { 11128 if (rt2x00_get_field16(eeprom, 11129 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 11130 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 11131 &rt2x00dev->cap_flags); 11132 if (rt2x00_get_field16(eeprom, 11133 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 11134 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 11135 &rt2x00dev->cap_flags); 11136 } 11137 11138 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2); 11139 11140 if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) { 11141 if (!rt2x00_get_field16(eeprom, 11142 EEPROM_NIC_CONF2_EXTERNAL_PA)) { 11143 __clear_bit(CAPABILITY_EXTERNAL_PA_TX0, 11144 &rt2x00dev->cap_flags); 11145 __clear_bit(CAPABILITY_EXTERNAL_PA_TX1, 11146 &rt2x00dev->cap_flags); 11147 } 11148 } 11149 11150 return 0; 11151 } 11152 11153 /* 11154 * RF value list for rt28xx 11155 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 11156 */ 11157 static const struct rf_channel rf_vals[] = { 11158 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 11159 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 11160 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 11161 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 11162 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 11163 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 11164 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 11165 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 11166 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 11167 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 11168 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 11169 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 11170 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 11171 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 11172 11173 /* 802.11 UNI / HyperLan 2 */ 11174 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 11175 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 11176 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 11177 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 11178 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 11179 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 11180 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 11181 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 11182 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 11183 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 11184 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 11185 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 11186 11187 /* 802.11 HyperLan 2 */ 11188 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 11189 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 11190 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 11191 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 11192 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 11193 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 11194 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 11195 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 11196 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 11197 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 11198 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 11199 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 11200 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 11201 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 11202 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 11203 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 11204 11205 /* 802.11 UNII */ 11206 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 11207 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 11208 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 11209 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 11210 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 11211 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 11212 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 11213 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 11214 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 11215 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 11216 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 11217 11218 /* 802.11 Japan */ 11219 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 11220 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 11221 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 11222 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 11223 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 11224 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 11225 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 11226 }; 11227 11228 /* 11229 * RF value list for rt3xxx 11230 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 11231 */ 11232 static const struct rf_channel rf_vals_3x[] = { 11233 {1, 241, 2, 2 }, 11234 {2, 241, 2, 7 }, 11235 {3, 242, 2, 2 }, 11236 {4, 242, 2, 7 }, 11237 {5, 243, 2, 2 }, 11238 {6, 243, 2, 7 }, 11239 {7, 244, 2, 2 }, 11240 {8, 244, 2, 7 }, 11241 {9, 245, 2, 2 }, 11242 {10, 245, 2, 7 }, 11243 {11, 246, 2, 2 }, 11244 {12, 246, 2, 7 }, 11245 {13, 247, 2, 2 }, 11246 {14, 248, 2, 4 }, 11247 11248 /* 802.11 UNI / HyperLan 2 */ 11249 {36, 0x56, 0, 4}, 11250 {38, 0x56, 0, 6}, 11251 {40, 0x56, 0, 8}, 11252 {44, 0x57, 0, 0}, 11253 {46, 0x57, 0, 2}, 11254 {48, 0x57, 0, 4}, 11255 {52, 0x57, 0, 8}, 11256 {54, 0x57, 0, 10}, 11257 {56, 0x58, 0, 0}, 11258 {60, 0x58, 0, 4}, 11259 {62, 0x58, 0, 6}, 11260 {64, 0x58, 0, 8}, 11261 11262 /* 802.11 HyperLan 2 */ 11263 {100, 0x5b, 0, 8}, 11264 {102, 0x5b, 0, 10}, 11265 {104, 0x5c, 0, 0}, 11266 {108, 0x5c, 0, 4}, 11267 {110, 0x5c, 0, 6}, 11268 {112, 0x5c, 0, 8}, 11269 {116, 0x5d, 0, 0}, 11270 {118, 0x5d, 0, 2}, 11271 {120, 0x5d, 0, 4}, 11272 {124, 0x5d, 0, 8}, 11273 {126, 0x5d, 0, 10}, 11274 {128, 0x5e, 0, 0}, 11275 {132, 0x5e, 0, 4}, 11276 {134, 0x5e, 0, 6}, 11277 {136, 0x5e, 0, 8}, 11278 {140, 0x5f, 0, 0}, 11279 11280 /* 802.11 UNII */ 11281 {149, 0x5f, 0, 9}, 11282 {151, 0x5f, 0, 11}, 11283 {153, 0x60, 0, 1}, 11284 {157, 0x60, 0, 5}, 11285 {159, 0x60, 0, 7}, 11286 {161, 0x60, 0, 9}, 11287 {165, 0x61, 0, 1}, 11288 {167, 0x61, 0, 3}, 11289 {169, 0x61, 0, 5}, 11290 {171, 0x61, 0, 7}, 11291 {173, 0x61, 0, 9}, 11292 }; 11293 11294 /* 11295 * RF value list for rt3xxx with Xtal20MHz 11296 * Supports: 2.4 GHz (all) (RF3322) 11297 */ 11298 static const struct rf_channel rf_vals_3x_xtal20[] = { 11299 {1, 0xE2, 2, 0x14}, 11300 {2, 0xE3, 2, 0x14}, 11301 {3, 0xE4, 2, 0x14}, 11302 {4, 0xE5, 2, 0x14}, 11303 {5, 0xE6, 2, 0x14}, 11304 {6, 0xE7, 2, 0x14}, 11305 {7, 0xE8, 2, 0x14}, 11306 {8, 0xE9, 2, 0x14}, 11307 {9, 0xEA, 2, 0x14}, 11308 {10, 0xEB, 2, 0x14}, 11309 {11, 0xEC, 2, 0x14}, 11310 {12, 0xED, 2, 0x14}, 11311 {13, 0xEE, 2, 0x14}, 11312 {14, 0xF0, 2, 0x18}, 11313 }; 11314 11315 static const struct rf_channel rf_vals_3853[] = { 11316 {1, 241, 6, 2}, 11317 {2, 241, 6, 7}, 11318 {3, 242, 6, 2}, 11319 {4, 242, 6, 7}, 11320 {5, 243, 6, 2}, 11321 {6, 243, 6, 7}, 11322 {7, 244, 6, 2}, 11323 {8, 244, 6, 7}, 11324 {9, 245, 6, 2}, 11325 {10, 245, 6, 7}, 11326 {11, 246, 6, 2}, 11327 {12, 246, 6, 7}, 11328 {13, 247, 6, 2}, 11329 {14, 248, 6, 4}, 11330 11331 {36, 0x56, 8, 4}, 11332 {38, 0x56, 8, 6}, 11333 {40, 0x56, 8, 8}, 11334 {44, 0x57, 8, 0}, 11335 {46, 0x57, 8, 2}, 11336 {48, 0x57, 8, 4}, 11337 {52, 0x57, 8, 8}, 11338 {54, 0x57, 8, 10}, 11339 {56, 0x58, 8, 0}, 11340 {60, 0x58, 8, 4}, 11341 {62, 0x58, 8, 6}, 11342 {64, 0x58, 8, 8}, 11343 11344 {100, 0x5b, 8, 8}, 11345 {102, 0x5b, 8, 10}, 11346 {104, 0x5c, 8, 0}, 11347 {108, 0x5c, 8, 4}, 11348 {110, 0x5c, 8, 6}, 11349 {112, 0x5c, 8, 8}, 11350 {114, 0x5c, 8, 10}, 11351 {116, 0x5d, 8, 0}, 11352 {118, 0x5d, 8, 2}, 11353 {120, 0x5d, 8, 4}, 11354 {124, 0x5d, 8, 8}, 11355 {126, 0x5d, 8, 10}, 11356 {128, 0x5e, 8, 0}, 11357 {132, 0x5e, 8, 4}, 11358 {134, 0x5e, 8, 6}, 11359 {136, 0x5e, 8, 8}, 11360 {140, 0x5f, 8, 0}, 11361 11362 {149, 0x5f, 8, 9}, 11363 {151, 0x5f, 8, 11}, 11364 {153, 0x60, 8, 1}, 11365 {157, 0x60, 8, 5}, 11366 {159, 0x60, 8, 7}, 11367 {161, 0x60, 8, 9}, 11368 {165, 0x61, 8, 1}, 11369 {167, 0x61, 8, 3}, 11370 {169, 0x61, 8, 5}, 11371 {171, 0x61, 8, 7}, 11372 {173, 0x61, 8, 9}, 11373 }; 11374 11375 static const struct rf_channel rf_vals_5592_xtal20[] = { 11376 /* Channel, N, K, mod, R */ 11377 {1, 482, 4, 10, 3}, 11378 {2, 483, 4, 10, 3}, 11379 {3, 484, 4, 10, 3}, 11380 {4, 485, 4, 10, 3}, 11381 {5, 486, 4, 10, 3}, 11382 {6, 487, 4, 10, 3}, 11383 {7, 488, 4, 10, 3}, 11384 {8, 489, 4, 10, 3}, 11385 {9, 490, 4, 10, 3}, 11386 {10, 491, 4, 10, 3}, 11387 {11, 492, 4, 10, 3}, 11388 {12, 493, 4, 10, 3}, 11389 {13, 494, 4, 10, 3}, 11390 {14, 496, 8, 10, 3}, 11391 {36, 172, 8, 12, 1}, 11392 {38, 173, 0, 12, 1}, 11393 {40, 173, 4, 12, 1}, 11394 {42, 173, 8, 12, 1}, 11395 {44, 174, 0, 12, 1}, 11396 {46, 174, 4, 12, 1}, 11397 {48, 174, 8, 12, 1}, 11398 {50, 175, 0, 12, 1}, 11399 {52, 175, 4, 12, 1}, 11400 {54, 175, 8, 12, 1}, 11401 {56, 176, 0, 12, 1}, 11402 {58, 176, 4, 12, 1}, 11403 {60, 176, 8, 12, 1}, 11404 {62, 177, 0, 12, 1}, 11405 {64, 177, 4, 12, 1}, 11406 {100, 183, 4, 12, 1}, 11407 {102, 183, 8, 12, 1}, 11408 {104, 184, 0, 12, 1}, 11409 {106, 184, 4, 12, 1}, 11410 {108, 184, 8, 12, 1}, 11411 {110, 185, 0, 12, 1}, 11412 {112, 185, 4, 12, 1}, 11413 {114, 185, 8, 12, 1}, 11414 {116, 186, 0, 12, 1}, 11415 {118, 186, 4, 12, 1}, 11416 {120, 186, 8, 12, 1}, 11417 {122, 187, 0, 12, 1}, 11418 {124, 187, 4, 12, 1}, 11419 {126, 187, 8, 12, 1}, 11420 {128, 188, 0, 12, 1}, 11421 {130, 188, 4, 12, 1}, 11422 {132, 188, 8, 12, 1}, 11423 {134, 189, 0, 12, 1}, 11424 {136, 189, 4, 12, 1}, 11425 {138, 189, 8, 12, 1}, 11426 {140, 190, 0, 12, 1}, 11427 {149, 191, 6, 12, 1}, 11428 {151, 191, 10, 12, 1}, 11429 {153, 192, 2, 12, 1}, 11430 {155, 192, 6, 12, 1}, 11431 {157, 192, 10, 12, 1}, 11432 {159, 193, 2, 12, 1}, 11433 {161, 193, 6, 12, 1}, 11434 {165, 194, 2, 12, 1}, 11435 {184, 164, 0, 12, 1}, 11436 {188, 164, 4, 12, 1}, 11437 {192, 165, 8, 12, 1}, 11438 {196, 166, 0, 12, 1}, 11439 }; 11440 11441 static const struct rf_channel rf_vals_5592_xtal40[] = { 11442 /* Channel, N, K, mod, R */ 11443 {1, 241, 2, 10, 3}, 11444 {2, 241, 7, 10, 3}, 11445 {3, 242, 2, 10, 3}, 11446 {4, 242, 7, 10, 3}, 11447 {5, 243, 2, 10, 3}, 11448 {6, 243, 7, 10, 3}, 11449 {7, 244, 2, 10, 3}, 11450 {8, 244, 7, 10, 3}, 11451 {9, 245, 2, 10, 3}, 11452 {10, 245, 7, 10, 3}, 11453 {11, 246, 2, 10, 3}, 11454 {12, 246, 7, 10, 3}, 11455 {13, 247, 2, 10, 3}, 11456 {14, 248, 4, 10, 3}, 11457 {36, 86, 4, 12, 1}, 11458 {38, 86, 6, 12, 1}, 11459 {40, 86, 8, 12, 1}, 11460 {42, 86, 10, 12, 1}, 11461 {44, 87, 0, 12, 1}, 11462 {46, 87, 2, 12, 1}, 11463 {48, 87, 4, 12, 1}, 11464 {50, 87, 6, 12, 1}, 11465 {52, 87, 8, 12, 1}, 11466 {54, 87, 10, 12, 1}, 11467 {56, 88, 0, 12, 1}, 11468 {58, 88, 2, 12, 1}, 11469 {60, 88, 4, 12, 1}, 11470 {62, 88, 6, 12, 1}, 11471 {64, 88, 8, 12, 1}, 11472 {100, 91, 8, 12, 1}, 11473 {102, 91, 10, 12, 1}, 11474 {104, 92, 0, 12, 1}, 11475 {106, 92, 2, 12, 1}, 11476 {108, 92, 4, 12, 1}, 11477 {110, 92, 6, 12, 1}, 11478 {112, 92, 8, 12, 1}, 11479 {114, 92, 10, 12, 1}, 11480 {116, 93, 0, 12, 1}, 11481 {118, 93, 2, 12, 1}, 11482 {120, 93, 4, 12, 1}, 11483 {122, 93, 6, 12, 1}, 11484 {124, 93, 8, 12, 1}, 11485 {126, 93, 10, 12, 1}, 11486 {128, 94, 0, 12, 1}, 11487 {130, 94, 2, 12, 1}, 11488 {132, 94, 4, 12, 1}, 11489 {134, 94, 6, 12, 1}, 11490 {136, 94, 8, 12, 1}, 11491 {138, 94, 10, 12, 1}, 11492 {140, 95, 0, 12, 1}, 11493 {149, 95, 9, 12, 1}, 11494 {151, 95, 11, 12, 1}, 11495 {153, 96, 1, 12, 1}, 11496 {155, 96, 3, 12, 1}, 11497 {157, 96, 5, 12, 1}, 11498 {159, 96, 7, 12, 1}, 11499 {161, 96, 9, 12, 1}, 11500 {165, 97, 1, 12, 1}, 11501 {184, 82, 0, 12, 1}, 11502 {188, 82, 4, 12, 1}, 11503 {192, 82, 8, 12, 1}, 11504 {196, 83, 0, 12, 1}, 11505 }; 11506 11507 static const struct rf_channel rf_vals_7620[] = { 11508 {1, 0x50, 0x99, 0x99, 1}, 11509 {2, 0x50, 0x44, 0x44, 2}, 11510 {3, 0x50, 0xEE, 0xEE, 2}, 11511 {4, 0x50, 0x99, 0x99, 3}, 11512 {5, 0x51, 0x44, 0x44, 0}, 11513 {6, 0x51, 0xEE, 0xEE, 0}, 11514 {7, 0x51, 0x99, 0x99, 1}, 11515 {8, 0x51, 0x44, 0x44, 2}, 11516 {9, 0x51, 0xEE, 0xEE, 2}, 11517 {10, 0x51, 0x99, 0x99, 3}, 11518 {11, 0x52, 0x44, 0x44, 0}, 11519 {12, 0x52, 0xEE, 0xEE, 0}, 11520 {13, 0x52, 0x99, 0x99, 1}, 11521 {14, 0x52, 0x33, 0x33, 3}, 11522 }; 11523 11524 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 11525 { 11526 struct hw_mode_spec *spec = &rt2x00dev->spec; 11527 struct channel_info *info; 11528 char *default_power1; 11529 char *default_power2; 11530 char *default_power3; 11531 unsigned int i, tx_chains, rx_chains; 11532 u32 reg; 11533 11534 /* 11535 * Disable powersaving as default. 11536 */ 11537 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 11538 11539 /* 11540 * Change default retry settings to values corresponding more closely 11541 * to rate[0].count setting of minstrel rate control algorithm. 11542 */ 11543 rt2x00dev->hw->wiphy->retry_short = 2; 11544 rt2x00dev->hw->wiphy->retry_long = 2; 11545 11546 /* 11547 * Initialize all hw fields. 11548 */ 11549 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 11550 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 11551 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 11552 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 11553 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 11554 11555 /* 11556 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 11557 * unless we are capable of sending the buffered frames out after the 11558 * DTIM transmission using rt2x00lib_beacondone. This will send out 11559 * multicast and broadcast traffic immediately instead of buffering it 11560 * infinitly and thus dropping it after some time. 11561 */ 11562 if (!rt2x00_is_usb(rt2x00dev)) 11563 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 11564 11565 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 11566 11567 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 11568 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 11569 rt2800_eeprom_addr(rt2x00dev, 11570 EEPROM_MAC_ADDR_0)); 11571 11572 /* 11573 * As rt2800 has a global fallback table we cannot specify 11574 * more then one tx rate per frame but since the hw will 11575 * try several rates (based on the fallback table) we should 11576 * initialize max_report_rates to the maximum number of rates 11577 * we are going to try. Otherwise mac80211 will truncate our 11578 * reported tx rates and the rc algortihm will end up with 11579 * incorrect data. 11580 */ 11581 rt2x00dev->hw->max_rates = 1; 11582 rt2x00dev->hw->max_report_rates = 7; 11583 rt2x00dev->hw->max_rate_tries = 1; 11584 11585 /* 11586 * Initialize hw_mode information. 11587 */ 11588 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 11589 11590 switch (rt2x00dev->chip.rf) { 11591 case RF2720: 11592 case RF2820: 11593 spec->num_channels = 14; 11594 spec->channels = rf_vals; 11595 break; 11596 11597 case RF2750: 11598 case RF2850: 11599 spec->num_channels = ARRAY_SIZE(rf_vals); 11600 spec->channels = rf_vals; 11601 break; 11602 11603 case RF2020: 11604 case RF3020: 11605 case RF3021: 11606 case RF3022: 11607 case RF3070: 11608 case RF3290: 11609 case RF3320: 11610 case RF3322: 11611 case RF5350: 11612 case RF5360: 11613 case RF5362: 11614 case RF5370: 11615 case RF5372: 11616 case RF5390: 11617 case RF5392: 11618 spec->num_channels = 14; 11619 if (rt2800_clk_is_20mhz(rt2x00dev)) 11620 spec->channels = rf_vals_3x_xtal20; 11621 else 11622 spec->channels = rf_vals_3x; 11623 break; 11624 11625 case RF7620: 11626 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 11627 spec->channels = rf_vals_7620; 11628 break; 11629 11630 case RF3052: 11631 case RF3053: 11632 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 11633 spec->channels = rf_vals_3x; 11634 break; 11635 11636 case RF3853: 11637 spec->num_channels = ARRAY_SIZE(rf_vals_3853); 11638 spec->channels = rf_vals_3853; 11639 break; 11640 11641 case RF5592: 11642 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 11643 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 11644 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 11645 spec->channels = rf_vals_5592_xtal40; 11646 } else { 11647 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 11648 spec->channels = rf_vals_5592_xtal20; 11649 } 11650 break; 11651 } 11652 11653 if (WARN_ON_ONCE(!spec->channels)) 11654 return -ENODEV; 11655 11656 spec->supported_bands = SUPPORT_BAND_2GHZ; 11657 if (spec->num_channels > 14) 11658 spec->supported_bands |= SUPPORT_BAND_5GHZ; 11659 11660 /* 11661 * Initialize HT information. 11662 */ 11663 if (!rt2x00_rf(rt2x00dev, RF2020)) 11664 spec->ht.ht_supported = true; 11665 else 11666 spec->ht.ht_supported = false; 11667 11668 spec->ht.cap = 11669 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 11670 IEEE80211_HT_CAP_GRN_FLD | 11671 IEEE80211_HT_CAP_SGI_20 | 11672 IEEE80211_HT_CAP_SGI_40; 11673 11674 tx_chains = rt2x00dev->default_ant.tx_chain_num; 11675 rx_chains = rt2x00dev->default_ant.rx_chain_num; 11676 11677 if (tx_chains >= 2) 11678 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 11679 11680 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 11681 11682 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 11683 spec->ht.ampdu_density = 4; 11684 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 11685 if (tx_chains != rx_chains) { 11686 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 11687 spec->ht.mcs.tx_params |= 11688 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 11689 } 11690 11691 switch (rx_chains) { 11692 case 3: 11693 spec->ht.mcs.rx_mask[2] = 0xff; 11694 fallthrough; 11695 case 2: 11696 spec->ht.mcs.rx_mask[1] = 0xff; 11697 fallthrough; 11698 case 1: 11699 spec->ht.mcs.rx_mask[0] = 0xff; 11700 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 11701 break; 11702 } 11703 11704 /* 11705 * Create channel information and survey arrays 11706 */ 11707 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 11708 if (!info) 11709 return -ENOMEM; 11710 11711 rt2x00dev->chan_survey = 11712 kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey), 11713 GFP_KERNEL); 11714 if (!rt2x00dev->chan_survey) { 11715 kfree(info); 11716 return -ENOMEM; 11717 } 11718 11719 spec->channels_info = info; 11720 11721 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 11722 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 11723 11724 if (rt2x00dev->default_ant.tx_chain_num > 2) 11725 default_power3 = rt2800_eeprom_addr(rt2x00dev, 11726 EEPROM_EXT_TXPOWER_BG3); 11727 else 11728 default_power3 = NULL; 11729 11730 for (i = 0; i < 14; i++) { 11731 info[i].default_power1 = default_power1[i]; 11732 info[i].default_power2 = default_power2[i]; 11733 if (default_power3) 11734 info[i].default_power3 = default_power3[i]; 11735 } 11736 11737 if (spec->num_channels > 14) { 11738 default_power1 = rt2800_eeprom_addr(rt2x00dev, 11739 EEPROM_TXPOWER_A1); 11740 default_power2 = rt2800_eeprom_addr(rt2x00dev, 11741 EEPROM_TXPOWER_A2); 11742 11743 if (rt2x00dev->default_ant.tx_chain_num > 2) 11744 default_power3 = 11745 rt2800_eeprom_addr(rt2x00dev, 11746 EEPROM_EXT_TXPOWER_A3); 11747 else 11748 default_power3 = NULL; 11749 11750 for (i = 14; i < spec->num_channels; i++) { 11751 info[i].default_power1 = default_power1[i - 14]; 11752 info[i].default_power2 = default_power2[i - 14]; 11753 if (default_power3) 11754 info[i].default_power3 = default_power3[i - 14]; 11755 } 11756 } 11757 11758 switch (rt2x00dev->chip.rf) { 11759 case RF2020: 11760 case RF3020: 11761 case RF3021: 11762 case RF3022: 11763 case RF3320: 11764 case RF3052: 11765 case RF3053: 11766 case RF3070: 11767 case RF3290: 11768 case RF3853: 11769 case RF5350: 11770 case RF5360: 11771 case RF5362: 11772 case RF5370: 11773 case RF5372: 11774 case RF5390: 11775 case RF5392: 11776 case RF5592: 11777 case RF7620: 11778 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 11779 break; 11780 } 11781 11782 return 0; 11783 } 11784 11785 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 11786 { 11787 u32 reg; 11788 u32 rt; 11789 u32 rev; 11790 11791 if (rt2x00_rt(rt2x00dev, RT3290)) 11792 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 11793 else 11794 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 11795 11796 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 11797 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 11798 11799 switch (rt) { 11800 case RT2860: 11801 case RT2872: 11802 case RT2883: 11803 case RT3070: 11804 case RT3071: 11805 case RT3090: 11806 case RT3290: 11807 case RT3352: 11808 case RT3390: 11809 case RT3572: 11810 case RT3593: 11811 case RT3883: 11812 case RT5350: 11813 case RT5390: 11814 case RT5392: 11815 case RT5592: 11816 break; 11817 default: 11818 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 11819 rt, rev); 11820 return -ENODEV; 11821 } 11822 11823 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 11824 rt = RT6352; 11825 11826 rt2x00_set_rt(rt2x00dev, rt, rev); 11827 11828 return 0; 11829 } 11830 11831 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 11832 { 11833 int retval; 11834 u32 reg; 11835 11836 retval = rt2800_probe_rt(rt2x00dev); 11837 if (retval) 11838 return retval; 11839 11840 /* 11841 * Allocate eeprom data. 11842 */ 11843 retval = rt2800_validate_eeprom(rt2x00dev); 11844 if (retval) 11845 return retval; 11846 11847 retval = rt2800_init_eeprom(rt2x00dev); 11848 if (retval) 11849 return retval; 11850 11851 /* 11852 * Enable rfkill polling by setting GPIO direction of the 11853 * rfkill switch GPIO pin correctly. 11854 */ 11855 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 11856 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 11857 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 11858 11859 /* 11860 * Initialize hw specifications. 11861 */ 11862 retval = rt2800_probe_hw_mode(rt2x00dev); 11863 if (retval) 11864 return retval; 11865 11866 /* 11867 * Set device capabilities. 11868 */ 11869 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 11870 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 11871 if (!rt2x00_is_usb(rt2x00dev)) 11872 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 11873 11874 /* 11875 * Set device requirements. 11876 */ 11877 if (!rt2x00_is_soc(rt2x00dev)) 11878 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 11879 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 11880 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 11881 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 11882 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 11883 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 11884 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 11885 if (rt2x00_is_usb(rt2x00dev)) 11886 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 11887 else { 11888 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 11889 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 11890 } 11891 11892 if (modparam_watchdog) { 11893 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags); 11894 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100); 11895 } else { 11896 rt2x00dev->link.watchdog_disabled = true; 11897 } 11898 11899 /* 11900 * Set the rssi offset. 11901 */ 11902 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 11903 11904 return 0; 11905 } 11906 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 11907 11908 /* 11909 * IEEE80211 stack callback functions. 11910 */ 11911 void rt2800_get_key_seq(struct ieee80211_hw *hw, 11912 struct ieee80211_key_conf *key, 11913 struct ieee80211_key_seq *seq) 11914 { 11915 struct rt2x00_dev *rt2x00dev = hw->priv; 11916 struct mac_iveiv_entry iveiv_entry; 11917 u32 offset; 11918 11919 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 11920 return; 11921 11922 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 11923 rt2800_register_multiread(rt2x00dev, offset, 11924 &iveiv_entry, sizeof(iveiv_entry)); 11925 11926 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 11927 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 11928 } 11929 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 11930 11931 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 11932 { 11933 struct rt2x00_dev *rt2x00dev = hw->priv; 11934 u32 reg; 11935 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 11936 11937 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 11938 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 11939 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 11940 11941 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 11942 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 11943 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 11944 11945 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 11946 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 11947 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 11948 11949 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 11950 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 11951 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 11952 11953 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 11954 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 11955 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 11956 11957 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 11958 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 11959 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 11960 11961 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 11962 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 11963 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 11964 11965 return 0; 11966 } 11967 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 11968 11969 int rt2800_conf_tx(struct ieee80211_hw *hw, 11970 struct ieee80211_vif *vif, 11971 unsigned int link_id, u16 queue_idx, 11972 const struct ieee80211_tx_queue_params *params) 11973 { 11974 struct rt2x00_dev *rt2x00dev = hw->priv; 11975 struct data_queue *queue; 11976 struct rt2x00_field32 field; 11977 int retval; 11978 u32 reg; 11979 u32 offset; 11980 11981 /* 11982 * First pass the configuration through rt2x00lib, that will 11983 * update the queue settings and validate the input. After that 11984 * we are free to update the registers based on the value 11985 * in the queue parameter. 11986 */ 11987 retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params); 11988 if (retval) 11989 return retval; 11990 11991 /* 11992 * We only need to perform additional register initialization 11993 * for WMM queues/ 11994 */ 11995 if (queue_idx >= 4) 11996 return 0; 11997 11998 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 11999 12000 /* Update WMM TXOP register */ 12001 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 12002 field.bit_offset = (queue_idx & 1) * 16; 12003 field.bit_mask = 0xffff << field.bit_offset; 12004 12005 reg = rt2800_register_read(rt2x00dev, offset); 12006 rt2x00_set_field32(®, field, queue->txop); 12007 rt2800_register_write(rt2x00dev, offset, reg); 12008 12009 /* Update WMM registers */ 12010 field.bit_offset = queue_idx * 4; 12011 field.bit_mask = 0xf << field.bit_offset; 12012 12013 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 12014 rt2x00_set_field32(®, field, queue->aifs); 12015 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 12016 12017 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 12018 rt2x00_set_field32(®, field, queue->cw_min); 12019 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 12020 12021 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 12022 rt2x00_set_field32(®, field, queue->cw_max); 12023 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 12024 12025 /* Update EDCA registers */ 12026 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 12027 12028 reg = rt2800_register_read(rt2x00dev, offset); 12029 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 12030 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 12031 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 12032 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 12033 rt2800_register_write(rt2x00dev, offset, reg); 12034 12035 return 0; 12036 } 12037 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 12038 12039 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 12040 { 12041 struct rt2x00_dev *rt2x00dev = hw->priv; 12042 u64 tsf; 12043 u32 reg; 12044 12045 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 12046 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 12047 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 12048 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 12049 12050 return tsf; 12051 } 12052 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 12053 12054 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 12055 struct ieee80211_ampdu_params *params) 12056 { 12057 struct ieee80211_sta *sta = params->sta; 12058 enum ieee80211_ampdu_mlme_action action = params->action; 12059 u16 tid = params->tid; 12060 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 12061 int ret = 0; 12062 12063 /* 12064 * Don't allow aggregation for stations the hardware isn't aware 12065 * of because tx status reports for frames to an unknown station 12066 * always contain wcid=WCID_END+1 and thus we can't distinguish 12067 * between multiple stations which leads to unwanted situations 12068 * when the hw reorders frames due to aggregation. 12069 */ 12070 if (sta_priv->wcid > WCID_END) 12071 return -ENOSPC; 12072 12073 switch (action) { 12074 case IEEE80211_AMPDU_RX_START: 12075 case IEEE80211_AMPDU_RX_STOP: 12076 /* 12077 * The hw itself takes care of setting up BlockAck mechanisms. 12078 * So, we only have to allow mac80211 to nagotiate a BlockAck 12079 * agreement. Once that is done, the hw will BlockAck incoming 12080 * AMPDUs without further setup. 12081 */ 12082 break; 12083 case IEEE80211_AMPDU_TX_START: 12084 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 12085 break; 12086 case IEEE80211_AMPDU_TX_STOP_CONT: 12087 case IEEE80211_AMPDU_TX_STOP_FLUSH: 12088 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 12089 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 12090 break; 12091 case IEEE80211_AMPDU_TX_OPERATIONAL: 12092 break; 12093 default: 12094 rt2x00_warn((struct rt2x00_dev *)hw->priv, 12095 "Unknown AMPDU action\n"); 12096 } 12097 12098 return ret; 12099 } 12100 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 12101 12102 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 12103 struct survey_info *survey) 12104 { 12105 struct rt2x00_dev *rt2x00dev = hw->priv; 12106 struct rt2x00_chan_survey *chan_survey = 12107 &rt2x00dev->chan_survey[idx]; 12108 enum nl80211_band band = NL80211_BAND_2GHZ; 12109 12110 if (idx >= rt2x00dev->bands[band].n_channels) { 12111 idx -= rt2x00dev->bands[band].n_channels; 12112 band = NL80211_BAND_5GHZ; 12113 } 12114 12115 if (idx >= rt2x00dev->bands[band].n_channels) 12116 return -ENOENT; 12117 12118 if (idx == 0) 12119 rt2800_update_survey(rt2x00dev); 12120 12121 survey->channel = &rt2x00dev->bands[band].channels[idx]; 12122 12123 survey->filled = SURVEY_INFO_TIME | 12124 SURVEY_INFO_TIME_BUSY | 12125 SURVEY_INFO_TIME_EXT_BUSY; 12126 12127 survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000); 12128 survey->time_busy = div_u64(chan_survey->time_busy, 1000); 12129 survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000); 12130 12131 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 12132 survey->filled |= SURVEY_INFO_IN_USE; 12133 12134 return 0; 12135 12136 } 12137 EXPORT_SYMBOL_GPL(rt2800_get_survey); 12138 12139 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 12140 MODULE_VERSION(DRV_VERSION); 12141 MODULE_DESCRIPTION("Ralink RT2800 library"); 12142 MODULE_LICENSE("GPL"); 12143