1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 7 8 Based on the original rt2800pci.c and rt2800usb.c. 9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 15 <http://rt2x00.serialmonkey.com> 16 17 */ 18 19 /* 20 Module: rt2800lib 21 Abstract: rt2800 generic device routines. 22 */ 23 24 #include <linux/crc-ccitt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "rt2x00.h" 30 #include "rt2800lib.h" 31 #include "rt2800.h" 32 33 static bool modparam_watchdog; 34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO); 35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected"); 36 37 /* 38 * Register access. 39 * All access to the CSR registers will go through the methods 40 * rt2800_register_read and rt2800_register_write. 41 * BBP and RF register require indirect register access, 42 * and use the CSR registers BBPCSR and RFCSR to achieve this. 43 * These indirect registers work with busy bits, 44 * and we will try maximal REGISTER_BUSY_COUNT times to access 45 * the register while taking a REGISTER_BUSY_DELAY us delay 46 * between each attampt. When the busy bit is still set at that time, 47 * the access attempt is considered to have failed, 48 * and we will print an error. 49 * The _lock versions must be used if you already hold the csr_mutex 50 */ 51 #define WAIT_FOR_BBP(__dev, __reg) \ 52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 53 #define WAIT_FOR_RFCSR(__dev, __reg) \ 54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 56 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 57 (__reg)) 58 #define WAIT_FOR_RF(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 60 #define WAIT_FOR_MCU(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 62 H2M_MAILBOX_CSR_OWNER, (__reg)) 63 64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 65 { 66 /* check for rt2872 on SoC */ 67 if (!rt2x00_is_soc(rt2x00dev) || 68 !rt2x00_rt(rt2x00dev, RT2872)) 69 return false; 70 71 /* we know for sure that these rf chipsets are used on rt305x boards */ 72 if (rt2x00_rf(rt2x00dev, RF3020) || 73 rt2x00_rf(rt2x00dev, RF3021) || 74 rt2x00_rf(rt2x00dev, RF3022)) 75 return true; 76 77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 78 return false; 79 } 80 81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 82 const unsigned int word, const u8 value) 83 { 84 u32 reg; 85 86 mutex_lock(&rt2x00dev->csr_mutex); 87 88 /* 89 * Wait until the BBP becomes available, afterwards we 90 * can safely write the new data into the register. 91 */ 92 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 93 reg = 0; 94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 99 100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 101 } 102 103 mutex_unlock(&rt2x00dev->csr_mutex); 104 } 105 106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 107 { 108 u32 reg; 109 u8 value; 110 111 mutex_lock(&rt2x00dev->csr_mutex); 112 113 /* 114 * Wait until the BBP becomes available, afterwards we 115 * can safely write the read request into the register. 116 * After the data has been written, we wait until hardware 117 * returns the correct value, if at any time the register 118 * doesn't become available in time, reg will be 0xffffffff 119 * which means we return 0xff to the caller. 120 */ 121 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 122 reg = 0; 123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 127 128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 129 130 WAIT_FOR_BBP(rt2x00dev, ®); 131 } 132 133 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 134 135 mutex_unlock(&rt2x00dev->csr_mutex); 136 137 return value; 138 } 139 140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 141 const unsigned int word, const u8 value) 142 { 143 u32 reg; 144 145 mutex_lock(&rt2x00dev->csr_mutex); 146 147 /* 148 * Wait until the RFCSR becomes available, afterwards we 149 * can safely write the new data into the register. 150 */ 151 switch (rt2x00dev->chip.rt) { 152 case RT6352: 153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 157 word); 158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 160 161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 162 } 163 break; 164 165 default: 166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 167 reg = 0; 168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 172 173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 174 } 175 break; 176 } 177 178 mutex_unlock(&rt2x00dev->csr_mutex); 179 } 180 181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 182 const unsigned int reg, const u8 value) 183 { 184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 185 } 186 187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 188 const unsigned int reg, const u8 value) 189 { 190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 192 } 193 194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 199 } 200 201 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 202 const u8 reg, const u8 value) 203 { 204 rt2800_bbp_write(rt2x00dev, 158, reg); 205 rt2800_bbp_write(rt2x00dev, 159, value); 206 } 207 208 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 209 { 210 rt2800_bbp_write(rt2x00dev, 158, reg); 211 return rt2800_bbp_read(rt2x00dev, 159); 212 } 213 214 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 215 const u8 reg, const u8 value) 216 { 217 rt2800_bbp_write(rt2x00dev, 195, reg); 218 rt2800_bbp_write(rt2x00dev, 196, value); 219 } 220 221 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 222 const unsigned int word) 223 { 224 u32 reg; 225 u8 value; 226 227 mutex_lock(&rt2x00dev->csr_mutex); 228 229 /* 230 * Wait until the RFCSR becomes available, afterwards we 231 * can safely write the read request into the register. 232 * After the data has been written, we wait until hardware 233 * returns the correct value, if at any time the register 234 * doesn't become available in time, reg will be 0xffffffff 235 * which means we return 0xff to the caller. 236 */ 237 switch (rt2x00dev->chip.rt) { 238 case RT6352: 239 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 240 reg = 0; 241 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 242 word); 243 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 244 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 245 246 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 247 248 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 249 } 250 251 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 252 break; 253 254 default: 255 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 256 reg = 0; 257 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 258 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 259 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 260 261 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 262 263 WAIT_FOR_RFCSR(rt2x00dev, ®); 264 } 265 266 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 267 break; 268 } 269 270 mutex_unlock(&rt2x00dev->csr_mutex); 271 272 return value; 273 } 274 275 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 276 const unsigned int reg) 277 { 278 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 279 } 280 281 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 282 const unsigned int word, const u32 value) 283 { 284 u32 reg; 285 286 mutex_lock(&rt2x00dev->csr_mutex); 287 288 /* 289 * Wait until the RF becomes available, afterwards we 290 * can safely write the new data into the register. 291 */ 292 if (WAIT_FOR_RF(rt2x00dev, ®)) { 293 reg = 0; 294 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 295 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 296 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 297 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 298 299 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 300 rt2x00_rf_write(rt2x00dev, word, value); 301 } 302 303 mutex_unlock(&rt2x00dev->csr_mutex); 304 } 305 306 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 307 [EEPROM_CHIP_ID] = 0x0000, 308 [EEPROM_VERSION] = 0x0001, 309 [EEPROM_MAC_ADDR_0] = 0x0002, 310 [EEPROM_MAC_ADDR_1] = 0x0003, 311 [EEPROM_MAC_ADDR_2] = 0x0004, 312 [EEPROM_NIC_CONF0] = 0x001a, 313 [EEPROM_NIC_CONF1] = 0x001b, 314 [EEPROM_FREQ] = 0x001d, 315 [EEPROM_LED_AG_CONF] = 0x001e, 316 [EEPROM_LED_ACT_CONF] = 0x001f, 317 [EEPROM_LED_POLARITY] = 0x0020, 318 [EEPROM_NIC_CONF2] = 0x0021, 319 [EEPROM_LNA] = 0x0022, 320 [EEPROM_RSSI_BG] = 0x0023, 321 [EEPROM_RSSI_BG2] = 0x0024, 322 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 323 [EEPROM_RSSI_A] = 0x0025, 324 [EEPROM_RSSI_A2] = 0x0026, 325 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 326 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 327 [EEPROM_TXPOWER_DELTA] = 0x0028, 328 [EEPROM_TXPOWER_BG1] = 0x0029, 329 [EEPROM_TXPOWER_BG2] = 0x0030, 330 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 331 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 332 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 333 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 334 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 335 [EEPROM_TXPOWER_A1] = 0x003c, 336 [EEPROM_TXPOWER_A2] = 0x0053, 337 [EEPROM_TXPOWER_INIT] = 0x0068, 338 [EEPROM_TSSI_BOUND_A1] = 0x006a, 339 [EEPROM_TSSI_BOUND_A2] = 0x006b, 340 [EEPROM_TSSI_BOUND_A3] = 0x006c, 341 [EEPROM_TSSI_BOUND_A4] = 0x006d, 342 [EEPROM_TSSI_BOUND_A5] = 0x006e, 343 [EEPROM_TXPOWER_BYRATE] = 0x006f, 344 [EEPROM_BBP_START] = 0x0078, 345 }; 346 347 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 348 [EEPROM_CHIP_ID] = 0x0000, 349 [EEPROM_VERSION] = 0x0001, 350 [EEPROM_MAC_ADDR_0] = 0x0002, 351 [EEPROM_MAC_ADDR_1] = 0x0003, 352 [EEPROM_MAC_ADDR_2] = 0x0004, 353 [EEPROM_NIC_CONF0] = 0x001a, 354 [EEPROM_NIC_CONF1] = 0x001b, 355 [EEPROM_NIC_CONF2] = 0x001c, 356 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 357 [EEPROM_FREQ] = 0x0022, 358 [EEPROM_LED_AG_CONF] = 0x0023, 359 [EEPROM_LED_ACT_CONF] = 0x0024, 360 [EEPROM_LED_POLARITY] = 0x0025, 361 [EEPROM_LNA] = 0x0026, 362 [EEPROM_EXT_LNA2] = 0x0027, 363 [EEPROM_RSSI_BG] = 0x0028, 364 [EEPROM_RSSI_BG2] = 0x0029, 365 [EEPROM_RSSI_A] = 0x002a, 366 [EEPROM_RSSI_A2] = 0x002b, 367 [EEPROM_TXPOWER_BG1] = 0x0030, 368 [EEPROM_TXPOWER_BG2] = 0x0037, 369 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 370 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 371 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 372 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 373 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 374 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 375 [EEPROM_TXPOWER_A1] = 0x004b, 376 [EEPROM_TXPOWER_A2] = 0x0065, 377 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 378 [EEPROM_TSSI_BOUND_A1] = 0x009a, 379 [EEPROM_TSSI_BOUND_A2] = 0x009b, 380 [EEPROM_TSSI_BOUND_A3] = 0x009c, 381 [EEPROM_TSSI_BOUND_A4] = 0x009d, 382 [EEPROM_TSSI_BOUND_A5] = 0x009e, 383 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 384 }; 385 386 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 387 const enum rt2800_eeprom_word word) 388 { 389 const unsigned int *map; 390 unsigned int index; 391 392 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 393 "%s: invalid EEPROM word %d\n", 394 wiphy_name(rt2x00dev->hw->wiphy), word)) 395 return 0; 396 397 if (rt2x00_rt(rt2x00dev, RT3593) || 398 rt2x00_rt(rt2x00dev, RT3883)) 399 map = rt2800_eeprom_map_ext; 400 else 401 map = rt2800_eeprom_map; 402 403 index = map[word]; 404 405 /* Index 0 is valid only for EEPROM_CHIP_ID. 406 * Otherwise it means that the offset of the 407 * given word is not initialized in the map, 408 * or that the field is not usable on the 409 * actual chipset. 410 */ 411 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 412 "%s: invalid access of EEPROM word %d\n", 413 wiphy_name(rt2x00dev->hw->wiphy), word); 414 415 return index; 416 } 417 418 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 419 const enum rt2800_eeprom_word word) 420 { 421 unsigned int index; 422 423 index = rt2800_eeprom_word_index(rt2x00dev, word); 424 return rt2x00_eeprom_addr(rt2x00dev, index); 425 } 426 427 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 428 const enum rt2800_eeprom_word word) 429 { 430 unsigned int index; 431 432 index = rt2800_eeprom_word_index(rt2x00dev, word); 433 return rt2x00_eeprom_read(rt2x00dev, index); 434 } 435 436 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 437 const enum rt2800_eeprom_word word, u16 data) 438 { 439 unsigned int index; 440 441 index = rt2800_eeprom_word_index(rt2x00dev, word); 442 rt2x00_eeprom_write(rt2x00dev, index, data); 443 } 444 445 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 446 const enum rt2800_eeprom_word array, 447 unsigned int offset) 448 { 449 unsigned int index; 450 451 index = rt2800_eeprom_word_index(rt2x00dev, array); 452 return rt2x00_eeprom_read(rt2x00dev, index + offset); 453 } 454 455 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 456 { 457 u32 reg; 458 int i, count; 459 460 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 461 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 462 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 463 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 464 rt2x00_set_field32(®, WLAN_EN, 1); 465 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 466 467 udelay(REGISTER_BUSY_DELAY); 468 469 count = 0; 470 do { 471 /* 472 * Check PLL_LD & XTAL_RDY. 473 */ 474 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 475 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 476 if (rt2x00_get_field32(reg, PLL_LD) && 477 rt2x00_get_field32(reg, XTAL_RDY)) 478 break; 479 udelay(REGISTER_BUSY_DELAY); 480 } 481 482 if (i >= REGISTER_BUSY_COUNT) { 483 484 if (count >= 10) 485 return -EIO; 486 487 rt2800_register_write(rt2x00dev, 0x58, 0x018); 488 udelay(REGISTER_BUSY_DELAY); 489 rt2800_register_write(rt2x00dev, 0x58, 0x418); 490 udelay(REGISTER_BUSY_DELAY); 491 rt2800_register_write(rt2x00dev, 0x58, 0x618); 492 udelay(REGISTER_BUSY_DELAY); 493 count++; 494 } else { 495 count = 0; 496 } 497 498 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 499 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 500 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 501 rt2x00_set_field32(®, WLAN_RESET, 1); 502 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 503 udelay(10); 504 rt2x00_set_field32(®, WLAN_RESET, 0); 505 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 506 udelay(10); 507 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 508 } while (count != 0); 509 510 return 0; 511 } 512 513 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 514 const u8 command, const u8 token, 515 const u8 arg0, const u8 arg1) 516 { 517 u32 reg; 518 519 /* 520 * SOC devices don't support MCU requests. 521 */ 522 if (rt2x00_is_soc(rt2x00dev)) 523 return; 524 525 mutex_lock(&rt2x00dev->csr_mutex); 526 527 /* 528 * Wait until the MCU becomes available, afterwards we 529 * can safely write the new data into the register. 530 */ 531 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 532 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 533 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 534 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 535 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 536 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 537 538 reg = 0; 539 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 540 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 541 } 542 543 mutex_unlock(&rt2x00dev->csr_mutex); 544 } 545 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 546 547 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 548 { 549 unsigned int i = 0; 550 u32 reg; 551 552 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 553 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 554 if (reg && reg != ~0) 555 return 0; 556 msleep(1); 557 } 558 559 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 560 return -EBUSY; 561 } 562 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 563 564 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 565 { 566 unsigned int i; 567 u32 reg; 568 569 /* 570 * Some devices are really slow to respond here. Wait a whole second 571 * before timing out. 572 */ 573 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 574 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 575 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 576 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 577 return 0; 578 579 msleep(10); 580 } 581 582 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 583 return -EACCES; 584 } 585 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 586 587 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 588 { 589 u32 reg; 590 591 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 592 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 593 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 594 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 595 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 596 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 597 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 598 } 599 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 600 601 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 602 unsigned short *txwi_size, 603 unsigned short *rxwi_size) 604 { 605 switch (rt2x00dev->chip.rt) { 606 case RT3593: 607 case RT3883: 608 *txwi_size = TXWI_DESC_SIZE_4WORDS; 609 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 610 break; 611 612 case RT5592: 613 case RT6352: 614 *txwi_size = TXWI_DESC_SIZE_5WORDS; 615 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 616 break; 617 618 default: 619 *txwi_size = TXWI_DESC_SIZE_4WORDS; 620 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 621 break; 622 } 623 } 624 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 625 626 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 627 { 628 u16 fw_crc; 629 u16 crc; 630 631 /* 632 * The last 2 bytes in the firmware array are the crc checksum itself, 633 * this means that we should never pass those 2 bytes to the crc 634 * algorithm. 635 */ 636 fw_crc = (data[len - 2] << 8 | data[len - 1]); 637 638 /* 639 * Use the crc ccitt algorithm. 640 * This will return the same value as the legacy driver which 641 * used bit ordering reversion on the both the firmware bytes 642 * before input input as well as on the final output. 643 * Obviously using crc ccitt directly is much more efficient. 644 */ 645 crc = crc_ccitt(~0, data, len - 2); 646 647 /* 648 * There is a small difference between the crc-itu-t + bitrev and 649 * the crc-ccitt crc calculation. In the latter method the 2 bytes 650 * will be swapped, use swab16 to convert the crc to the correct 651 * value. 652 */ 653 crc = swab16(crc); 654 655 return fw_crc == crc; 656 } 657 658 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 659 const u8 *data, const size_t len) 660 { 661 size_t offset = 0; 662 size_t fw_len; 663 bool multiple; 664 665 /* 666 * PCI(e) & SOC devices require firmware with a length 667 * of 8kb. USB devices require firmware files with a length 668 * of 4kb. Certain USB chipsets however require different firmware, 669 * which Ralink only provides attached to the original firmware 670 * file. Thus for USB devices, firmware files have a length 671 * which is a multiple of 4kb. The firmware for rt3290 chip also 672 * have a length which is a multiple of 4kb. 673 */ 674 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 675 fw_len = 4096; 676 else 677 fw_len = 8192; 678 679 multiple = true; 680 /* 681 * Validate the firmware length 682 */ 683 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 684 return FW_BAD_LENGTH; 685 686 /* 687 * Check if the chipset requires one of the upper parts 688 * of the firmware. 689 */ 690 if (rt2x00_is_usb(rt2x00dev) && 691 !rt2x00_rt(rt2x00dev, RT2860) && 692 !rt2x00_rt(rt2x00dev, RT2872) && 693 !rt2x00_rt(rt2x00dev, RT3070) && 694 ((len / fw_len) == 1)) 695 return FW_BAD_VERSION; 696 697 /* 698 * 8kb firmware files must be checked as if it were 699 * 2 separate firmware files. 700 */ 701 while (offset < len) { 702 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 703 return FW_BAD_CRC; 704 705 offset += fw_len; 706 } 707 708 return FW_OK; 709 } 710 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 711 712 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 713 const u8 *data, const size_t len) 714 { 715 unsigned int i; 716 u32 reg; 717 int retval; 718 719 if (rt2x00_rt(rt2x00dev, RT3290)) { 720 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 721 if (retval) 722 return -EBUSY; 723 } 724 725 /* 726 * If driver doesn't wake up firmware here, 727 * rt2800_load_firmware will hang forever when interface is up again. 728 */ 729 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 730 731 /* 732 * Wait for stable hardware. 733 */ 734 if (rt2800_wait_csr_ready(rt2x00dev)) 735 return -EBUSY; 736 737 if (rt2x00_is_pci(rt2x00dev)) { 738 if (rt2x00_rt(rt2x00dev, RT3290) || 739 rt2x00_rt(rt2x00dev, RT3572) || 740 rt2x00_rt(rt2x00dev, RT5390) || 741 rt2x00_rt(rt2x00dev, RT5392)) { 742 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 743 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 744 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 745 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 746 } 747 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 748 } 749 750 rt2800_disable_wpdma(rt2x00dev); 751 752 /* 753 * Write firmware to the device. 754 */ 755 rt2800_drv_write_firmware(rt2x00dev, data, len); 756 757 /* 758 * Wait for device to stabilize. 759 */ 760 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 761 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 762 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 763 break; 764 msleep(1); 765 } 766 767 if (i == REGISTER_BUSY_COUNT) { 768 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 769 return -EBUSY; 770 } 771 772 /* 773 * Disable DMA, will be reenabled later when enabling 774 * the radio. 775 */ 776 rt2800_disable_wpdma(rt2x00dev); 777 778 /* 779 * Initialize firmware. 780 */ 781 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 782 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 783 if (rt2x00_is_usb(rt2x00dev)) { 784 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 785 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 786 } 787 msleep(1); 788 789 return 0; 790 } 791 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 792 793 void rt2800_write_tx_data(struct queue_entry *entry, 794 struct txentry_desc *txdesc) 795 { 796 __le32 *txwi = rt2800_drv_get_txwi(entry); 797 u32 word; 798 int i; 799 800 /* 801 * Initialize TX Info descriptor 802 */ 803 word = rt2x00_desc_read(txwi, 0); 804 rt2x00_set_field32(&word, TXWI_W0_FRAG, 805 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 807 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 808 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 809 rt2x00_set_field32(&word, TXWI_W0_TS, 810 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 811 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 812 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 814 txdesc->u.ht.mpdu_density); 815 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 816 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 817 rt2x00_set_field32(&word, TXWI_W0_BW, 818 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 819 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 820 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 821 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 822 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 823 rt2x00_desc_write(txwi, 0, word); 824 825 word = rt2x00_desc_read(txwi, 1); 826 rt2x00_set_field32(&word, TXWI_W1_ACK, 827 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 828 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 829 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 830 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 831 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 832 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 833 txdesc->key_idx : txdesc->u.ht.wcid); 834 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 835 txdesc->length); 836 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 837 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 838 rt2x00_desc_write(txwi, 1, word); 839 840 /* 841 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 842 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 843 * When TXD_W3_WIV is set to 1 it will use the IV data 844 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 845 * crypto entry in the registers should be used to encrypt the frame. 846 * 847 * Nulify all remaining words as well, we don't know how to program them. 848 */ 849 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 850 _rt2x00_desc_write(txwi, i, 0); 851 } 852 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 853 854 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 855 { 856 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 857 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 858 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 859 s8 base_val = rt2x00_rt(rt2x00dev, RT6352) ? -2 : -12; 860 u16 eeprom; 861 u8 offset0; 862 u8 offset1; 863 u8 offset2; 864 865 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 866 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 867 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 868 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 869 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 870 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 871 } else { 872 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 873 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 874 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 875 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 876 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 877 } 878 879 /* 880 * Convert the value from the descriptor into the RSSI value 881 * If the value in the descriptor is 0, it is considered invalid 882 * and the default (extremely low) rssi value is assumed 883 */ 884 rssi0 = (rssi0) ? (base_val - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 885 rssi1 = (rssi1) ? (base_val - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 886 rssi2 = (rssi2) ? (base_val - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 887 888 /* 889 * mac80211 only accepts a single RSSI value. Calculating the 890 * average doesn't deliver a fair answer either since -60:-60 would 891 * be considered equally good as -50:-70 while the second is the one 892 * which gives less energy... 893 */ 894 rssi0 = max(rssi0, rssi1); 895 return (int)max(rssi0, rssi2); 896 } 897 898 void rt2800_process_rxwi(struct queue_entry *entry, 899 struct rxdone_entry_desc *rxdesc) 900 { 901 __le32 *rxwi = (__le32 *) entry->skb->data; 902 u32 word; 903 904 word = rt2x00_desc_read(rxwi, 0); 905 906 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 907 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 908 909 word = rt2x00_desc_read(rxwi, 1); 910 911 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 912 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 913 914 if (rt2x00_get_field32(word, RXWI_W1_BW)) 915 rxdesc->bw = RATE_INFO_BW_40; 916 917 /* 918 * Detect RX rate, always use MCS as signal type. 919 */ 920 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 921 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 922 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 923 924 /* 925 * Mask of 0x8 bit to remove the short preamble flag. 926 */ 927 if (rxdesc->rate_mode == RATE_MODE_CCK) 928 rxdesc->signal &= ~0x8; 929 930 word = rt2x00_desc_read(rxwi, 2); 931 932 /* 933 * Convert descriptor AGC value to RSSI value. 934 */ 935 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 936 /* 937 * Remove RXWI descriptor from start of the buffer. 938 */ 939 skb_pull(entry->skb, entry->queue->winfo_size); 940 } 941 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 942 943 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 944 u32 status, enum nl80211_band band) 945 { 946 u8 flags = 0; 947 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 948 949 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 950 case RATE_MODE_HT_GREENFIELD: 951 flags |= IEEE80211_TX_RC_GREEN_FIELD; 952 fallthrough; 953 case RATE_MODE_HT_MIX: 954 flags |= IEEE80211_TX_RC_MCS; 955 break; 956 case RATE_MODE_OFDM: 957 if (band == NL80211_BAND_2GHZ) 958 idx += 4; 959 break; 960 case RATE_MODE_CCK: 961 if (idx >= 8) 962 idx -= 8; 963 break; 964 } 965 966 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 967 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 968 969 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 970 flags |= IEEE80211_TX_RC_SHORT_GI; 971 972 skbdesc->tx_rate_idx = idx; 973 skbdesc->tx_rate_flags = flags; 974 } 975 976 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 977 { 978 __le32 *txwi; 979 u32 word; 980 int wcid, ack, pid; 981 int tx_wcid, tx_ack, tx_pid, is_agg; 982 983 /* 984 * This frames has returned with an IO error, 985 * so the status report is not intended for this 986 * frame. 987 */ 988 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 989 return false; 990 991 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 992 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 993 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 994 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 995 996 /* 997 * Validate if this TX status report is intended for 998 * this entry by comparing the WCID/ACK/PID fields. 999 */ 1000 txwi = rt2800_drv_get_txwi(entry); 1001 1002 word = rt2x00_desc_read(txwi, 1); 1003 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 1004 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 1005 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 1006 1007 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 1008 rt2x00_dbg(entry->queue->rt2x00dev, 1009 "TX status report missed for queue %d entry %d\n", 1010 entry->queue->qid, entry->entry_idx); 1011 return false; 1012 } 1013 1014 return true; 1015 } 1016 1017 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 1018 bool match) 1019 { 1020 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1021 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1022 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1023 struct txdone_entry_desc txdesc; 1024 u32 word; 1025 u16 mcs, real_mcs; 1026 int aggr, ampdu, wcid, ack_req; 1027 1028 /* 1029 * Obtain the status about this packet. 1030 */ 1031 txdesc.flags = 0; 1032 word = rt2x00_desc_read(txwi, 0); 1033 1034 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1035 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1036 1037 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1038 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1039 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1040 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1041 1042 /* 1043 * If a frame was meant to be sent as a single non-aggregated MPDU 1044 * but ended up in an aggregate the used tx rate doesn't correlate 1045 * with the one specified in the TXWI as the whole aggregate is sent 1046 * with the same rate. 1047 * 1048 * For example: two frames are sent to rt2x00, the first one sets 1049 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1050 * and requests MCS15. If the hw aggregates both frames into one 1051 * AMDPU the tx status for both frames will contain MCS7 although 1052 * the frame was sent successfully. 1053 * 1054 * Hence, replace the requested rate with the real tx rate to not 1055 * confuse the rate control algortihm by providing clearly wrong 1056 * data. 1057 * 1058 * FIXME: if we do not find matching entry, we tell that frame was 1059 * posted without any retries. We need to find a way to fix that 1060 * and provide retry count. 1061 */ 1062 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1063 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1064 mcs = real_mcs; 1065 } 1066 1067 if (aggr == 1 || ampdu == 1) 1068 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1069 1070 if (!ack_req) 1071 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1072 1073 /* 1074 * Ralink has a retry mechanism using a global fallback 1075 * table. We setup this fallback table to try the immediate 1076 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1077 * always contains the MCS used for the last transmission, be 1078 * it successful or not. 1079 */ 1080 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1081 /* 1082 * Transmission succeeded. The number of retries is 1083 * mcs - real_mcs 1084 */ 1085 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1086 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1087 } else { 1088 /* 1089 * Transmission failed. The number of retries is 1090 * always 7 in this case (for a total number of 8 1091 * frames sent). 1092 */ 1093 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1094 txdesc.retry = rt2x00dev->long_retry; 1095 } 1096 1097 /* 1098 * the frame was retried at least once 1099 * -> hw used fallback rates 1100 */ 1101 if (txdesc.retry) 1102 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1103 1104 if (!match) { 1105 /* RCU assures non-null sta will not be freed by mac80211. */ 1106 rcu_read_lock(); 1107 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1108 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1109 else 1110 skbdesc->sta = NULL; 1111 rt2x00lib_txdone_nomatch(entry, &txdesc); 1112 rcu_read_unlock(); 1113 } else { 1114 rt2x00lib_txdone(entry, &txdesc); 1115 } 1116 } 1117 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1118 1119 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1120 { 1121 struct data_queue *queue; 1122 struct queue_entry *entry; 1123 u32 reg; 1124 u8 qid; 1125 bool match; 1126 1127 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1128 /* 1129 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1130 * guaranteed to be one of the TX QIDs . 1131 */ 1132 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1133 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1134 1135 if (unlikely(rt2x00queue_empty(queue))) { 1136 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1137 qid); 1138 break; 1139 } 1140 1141 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1142 1143 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1144 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1145 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1146 entry->entry_idx, qid); 1147 break; 1148 } 1149 1150 match = rt2800_txdone_entry_check(entry, reg); 1151 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1152 } 1153 } 1154 EXPORT_SYMBOL_GPL(rt2800_txdone); 1155 1156 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1157 struct queue_entry *entry) 1158 { 1159 bool ret; 1160 unsigned long tout; 1161 1162 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1163 return false; 1164 1165 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1166 tout = msecs_to_jiffies(50); 1167 else 1168 tout = msecs_to_jiffies(2000); 1169 1170 ret = time_after(jiffies, entry->last_action + tout); 1171 if (unlikely(ret)) 1172 rt2x00_dbg(entry->queue->rt2x00dev, 1173 "TX status timeout for entry %d in queue %d\n", 1174 entry->entry_idx, entry->queue->qid); 1175 return ret; 1176 } 1177 1178 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1179 { 1180 struct data_queue *queue; 1181 struct queue_entry *entry; 1182 1183 tx_queue_for_each(rt2x00dev, queue) { 1184 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1185 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1186 return true; 1187 } 1188 1189 return false; 1190 } 1191 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1192 1193 /* 1194 * test if there is an entry in any TX queue for which DMA is done 1195 * but the TX status has not been returned yet 1196 */ 1197 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1198 { 1199 struct data_queue *queue; 1200 1201 tx_queue_for_each(rt2x00dev, queue) { 1202 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1203 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1204 return true; 1205 } 1206 return false; 1207 } 1208 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1209 1210 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1211 { 1212 struct data_queue *queue; 1213 struct queue_entry *entry; 1214 1215 /* 1216 * Process any trailing TX status reports for IO failures, 1217 * we loop until we find the first non-IO error entry. This 1218 * can either be a frame which is free, is being uploaded, 1219 * or has completed the upload but didn't have an entry 1220 * in the TX_STAT_FIFO register yet. 1221 */ 1222 tx_queue_for_each(rt2x00dev, queue) { 1223 while (!rt2x00queue_empty(queue)) { 1224 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1225 1226 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1227 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1228 break; 1229 1230 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1231 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1232 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1233 else 1234 break; 1235 } 1236 } 1237 } 1238 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1239 1240 static bool rt2800_check_hung(struct data_queue *queue) 1241 { 1242 unsigned int cur_idx = rt2800_drv_get_dma_done(queue); 1243 1244 if (queue->wd_idx != cur_idx) { 1245 queue->wd_idx = cur_idx; 1246 queue->wd_count = 0; 1247 } else 1248 queue->wd_count++; 1249 1250 return queue->wd_count > 16; 1251 } 1252 1253 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev) 1254 { 1255 struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan; 1256 struct rt2x00_chan_survey *chan_survey = 1257 &rt2x00dev->chan_survey[chan->hw_value]; 1258 1259 chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA); 1260 chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA); 1261 chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 1262 } 1263 1264 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev) 1265 { 1266 struct data_queue *queue; 1267 bool hung_tx = false; 1268 bool hung_rx = false; 1269 1270 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) 1271 return; 1272 1273 rt2800_update_survey(rt2x00dev); 1274 1275 queue_for_each(rt2x00dev, queue) { 1276 switch (queue->qid) { 1277 case QID_AC_VO: 1278 case QID_AC_VI: 1279 case QID_AC_BE: 1280 case QID_AC_BK: 1281 case QID_MGMT: 1282 if (rt2x00queue_empty(queue)) 1283 continue; 1284 hung_tx = hung_tx || rt2800_check_hung(queue); 1285 break; 1286 case QID_RX: 1287 /* For station mode we should reactive at least 1288 * beacons. TODO: need to find good way detect 1289 * RX hung for AP mode. 1290 */ 1291 if (rt2x00dev->intf_sta_count == 0) 1292 continue; 1293 hung_rx = hung_rx || rt2800_check_hung(queue); 1294 break; 1295 default: 1296 break; 1297 } 1298 } 1299 1300 if (hung_tx) 1301 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n"); 1302 1303 if (hung_rx) 1304 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n"); 1305 1306 if (hung_tx || hung_rx) { 1307 queue_for_each(rt2x00dev, queue) 1308 queue->wd_count = 0; 1309 1310 ieee80211_restart_hw(rt2x00dev->hw); 1311 } 1312 } 1313 EXPORT_SYMBOL_GPL(rt2800_watchdog); 1314 1315 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1316 unsigned int index) 1317 { 1318 return HW_BEACON_BASE(index); 1319 } 1320 1321 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1322 unsigned int index) 1323 { 1324 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1325 } 1326 1327 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1328 { 1329 struct data_queue *queue = rt2x00dev->bcn; 1330 struct queue_entry *entry; 1331 int i, bcn_num = 0; 1332 u64 off, reg = 0; 1333 u32 bssid_dw1; 1334 1335 /* 1336 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1337 */ 1338 for (i = 0; i < queue->limit; i++) { 1339 entry = &queue->entries[i]; 1340 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1341 continue; 1342 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1343 reg |= off << (8 * bcn_num); 1344 bcn_num++; 1345 } 1346 1347 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1348 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1349 1350 /* 1351 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1352 */ 1353 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1354 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1355 bcn_num > 0 ? bcn_num - 1 : 0); 1356 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1357 } 1358 1359 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1360 { 1361 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1362 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1363 unsigned int beacon_base; 1364 unsigned int padding_len; 1365 u32 orig_reg, reg; 1366 const int txwi_desc_size = entry->queue->winfo_size; 1367 1368 /* 1369 * Disable beaconing while we are reloading the beacon data, 1370 * otherwise we might be sending out invalid data. 1371 */ 1372 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1373 orig_reg = reg; 1374 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1375 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1376 1377 /* 1378 * Add space for the TXWI in front of the skb. 1379 */ 1380 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1381 1382 /* 1383 * Register descriptor details in skb frame descriptor. 1384 */ 1385 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1386 skbdesc->desc = entry->skb->data; 1387 skbdesc->desc_len = txwi_desc_size; 1388 1389 /* 1390 * Add the TXWI for the beacon to the skb. 1391 */ 1392 rt2800_write_tx_data(entry, txdesc); 1393 1394 /* 1395 * Dump beacon to userspace through debugfs. 1396 */ 1397 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1398 1399 /* 1400 * Write entire beacon with TXWI and padding to register. 1401 */ 1402 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1403 if (padding_len && skb_pad(entry->skb, padding_len)) { 1404 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1405 /* skb freed by skb_pad() on failure */ 1406 entry->skb = NULL; 1407 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1408 return; 1409 } 1410 1411 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1412 1413 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1414 entry->skb->len + padding_len); 1415 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1416 1417 /* 1418 * Change global beacons settings. 1419 */ 1420 rt2800_update_beacons_setup(rt2x00dev); 1421 1422 /* 1423 * Restore beaconing state. 1424 */ 1425 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1426 1427 /* 1428 * Clean up beacon skb. 1429 */ 1430 dev_kfree_skb_any(entry->skb); 1431 entry->skb = NULL; 1432 } 1433 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1434 1435 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1436 unsigned int index) 1437 { 1438 int i; 1439 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1440 unsigned int beacon_base; 1441 1442 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1443 1444 /* 1445 * For the Beacon base registers we only need to clear 1446 * the whole TXWI which (when set to 0) will invalidate 1447 * the entire beacon. 1448 */ 1449 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1450 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1451 } 1452 1453 void rt2800_clear_beacon(struct queue_entry *entry) 1454 { 1455 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1456 u32 orig_reg, reg; 1457 1458 /* 1459 * Disable beaconing while we are reloading the beacon data, 1460 * otherwise we might be sending out invalid data. 1461 */ 1462 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1463 reg = orig_reg; 1464 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1465 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1466 1467 /* 1468 * Clear beacon. 1469 */ 1470 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1471 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1472 1473 /* 1474 * Change global beacons settings. 1475 */ 1476 rt2800_update_beacons_setup(rt2x00dev); 1477 /* 1478 * Restore beaconing state. 1479 */ 1480 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1481 } 1482 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1483 1484 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1485 const struct rt2x00debug rt2800_rt2x00debug = { 1486 .owner = THIS_MODULE, 1487 .csr = { 1488 .read = rt2800_register_read, 1489 .write = rt2800_register_write, 1490 .flags = RT2X00DEBUGFS_OFFSET, 1491 .word_base = CSR_REG_BASE, 1492 .word_size = sizeof(u32), 1493 .word_count = CSR_REG_SIZE / sizeof(u32), 1494 }, 1495 .eeprom = { 1496 /* NOTE: The local EEPROM access functions can't 1497 * be used here, use the generic versions instead. 1498 */ 1499 .read = rt2x00_eeprom_read, 1500 .write = rt2x00_eeprom_write, 1501 .word_base = EEPROM_BASE, 1502 .word_size = sizeof(u16), 1503 .word_count = EEPROM_SIZE / sizeof(u16), 1504 }, 1505 .bbp = { 1506 .read = rt2800_bbp_read, 1507 .write = rt2800_bbp_write, 1508 .word_base = BBP_BASE, 1509 .word_size = sizeof(u8), 1510 .word_count = BBP_SIZE / sizeof(u8), 1511 }, 1512 .rf = { 1513 .read = rt2x00_rf_read, 1514 .write = rt2800_rf_write, 1515 .word_base = RF_BASE, 1516 .word_size = sizeof(u32), 1517 .word_count = RF_SIZE / sizeof(u32), 1518 }, 1519 .rfcsr = { 1520 .read = rt2800_rfcsr_read, 1521 .write = rt2800_rfcsr_write, 1522 .word_base = RFCSR_BASE, 1523 .word_size = sizeof(u8), 1524 .word_count = RFCSR_SIZE / sizeof(u8), 1525 }, 1526 }; 1527 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1528 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1529 1530 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1531 { 1532 u32 reg; 1533 1534 if (rt2x00_rt(rt2x00dev, RT3290)) { 1535 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1536 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1537 } else { 1538 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1539 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1540 } 1541 } 1542 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1543 1544 #ifdef CONFIG_RT2X00_LIB_LEDS 1545 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1546 enum led_brightness brightness) 1547 { 1548 struct rt2x00_led *led = 1549 container_of(led_cdev, struct rt2x00_led, led_dev); 1550 unsigned int enabled = brightness != LED_OFF; 1551 unsigned int bg_mode = 1552 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1553 unsigned int polarity = 1554 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1555 EEPROM_FREQ_LED_POLARITY); 1556 unsigned int ledmode = 1557 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1558 EEPROM_FREQ_LED_MODE); 1559 u32 reg; 1560 1561 /* Check for SoC (SOC devices don't support MCU requests) */ 1562 if (rt2x00_is_soc(led->rt2x00dev)) { 1563 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1564 1565 /* Set LED Polarity */ 1566 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1567 1568 /* Set LED Mode */ 1569 if (led->type == LED_TYPE_RADIO) { 1570 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1571 enabled ? 3 : 0); 1572 } else if (led->type == LED_TYPE_ASSOC) { 1573 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1574 enabled ? 3 : 0); 1575 } else if (led->type == LED_TYPE_QUALITY) { 1576 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1577 enabled ? 3 : 0); 1578 } 1579 1580 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1581 1582 } else { 1583 if (led->type == LED_TYPE_RADIO) { 1584 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1585 enabled ? 0x20 : 0); 1586 } else if (led->type == LED_TYPE_ASSOC) { 1587 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1588 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1589 } else if (led->type == LED_TYPE_QUALITY) { 1590 /* 1591 * The brightness is divided into 6 levels (0 - 5), 1592 * The specs tell us the following levels: 1593 * 0, 1 ,3, 7, 15, 31 1594 * to determine the level in a simple way we can simply 1595 * work with bitshifting: 1596 * (1 << level) - 1 1597 */ 1598 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1599 (1 << brightness / (LED_FULL / 6)) - 1, 1600 polarity); 1601 } 1602 } 1603 } 1604 1605 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1606 struct rt2x00_led *led, enum led_type type) 1607 { 1608 led->rt2x00dev = rt2x00dev; 1609 led->type = type; 1610 led->led_dev.brightness_set = rt2800_brightness_set; 1611 led->flags = LED_INITIALIZED; 1612 } 1613 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1614 1615 /* 1616 * Configuration handlers. 1617 */ 1618 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1619 const u8 *address, 1620 int wcid) 1621 { 1622 struct mac_wcid_entry wcid_entry; 1623 u32 offset; 1624 1625 offset = MAC_WCID_ENTRY(wcid); 1626 1627 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1628 if (address) 1629 memcpy(wcid_entry.mac, address, ETH_ALEN); 1630 1631 rt2800_register_multiwrite(rt2x00dev, offset, 1632 &wcid_entry, sizeof(wcid_entry)); 1633 } 1634 1635 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1636 { 1637 u32 offset; 1638 offset = MAC_WCID_ATTR_ENTRY(wcid); 1639 rt2800_register_write(rt2x00dev, offset, 0); 1640 } 1641 1642 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1643 int wcid, u32 bssidx) 1644 { 1645 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1646 u32 reg; 1647 1648 /* 1649 * The BSS Idx numbers is split in a main value of 3 bits, 1650 * and a extended field for adding one additional bit to the value. 1651 */ 1652 reg = rt2800_register_read(rt2x00dev, offset); 1653 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1654 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1655 (bssidx & 0x8) >> 3); 1656 rt2800_register_write(rt2x00dev, offset, reg); 1657 } 1658 1659 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1660 struct rt2x00lib_crypto *crypto, 1661 struct ieee80211_key_conf *key) 1662 { 1663 struct mac_iveiv_entry iveiv_entry; 1664 u32 offset; 1665 u32 reg; 1666 1667 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1668 1669 if (crypto->cmd == SET_KEY) { 1670 reg = rt2800_register_read(rt2x00dev, offset); 1671 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1672 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1673 /* 1674 * Both the cipher as the BSS Idx numbers are split in a main 1675 * value of 3 bits, and a extended field for adding one additional 1676 * bit to the value. 1677 */ 1678 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1679 (crypto->cipher & 0x7)); 1680 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1681 (crypto->cipher & 0x8) >> 3); 1682 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1683 rt2800_register_write(rt2x00dev, offset, reg); 1684 } else { 1685 /* Delete the cipher without touching the bssidx */ 1686 reg = rt2800_register_read(rt2x00dev, offset); 1687 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1688 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1689 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1690 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1691 rt2800_register_write(rt2x00dev, offset, reg); 1692 } 1693 1694 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 1695 return; 1696 1697 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1698 1699 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1700 if ((crypto->cipher == CIPHER_TKIP) || 1701 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1702 (crypto->cipher == CIPHER_AES)) 1703 iveiv_entry.iv[3] |= 0x20; 1704 iveiv_entry.iv[3] |= key->keyidx << 6; 1705 rt2800_register_multiwrite(rt2x00dev, offset, 1706 &iveiv_entry, sizeof(iveiv_entry)); 1707 } 1708 1709 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1710 struct rt2x00lib_crypto *crypto, 1711 struct ieee80211_key_conf *key) 1712 { 1713 struct hw_key_entry key_entry; 1714 struct rt2x00_field32 field; 1715 u32 offset; 1716 u32 reg; 1717 1718 if (crypto->cmd == SET_KEY) { 1719 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1720 1721 memcpy(key_entry.key, crypto->key, 1722 sizeof(key_entry.key)); 1723 memcpy(key_entry.tx_mic, crypto->tx_mic, 1724 sizeof(key_entry.tx_mic)); 1725 memcpy(key_entry.rx_mic, crypto->rx_mic, 1726 sizeof(key_entry.rx_mic)); 1727 1728 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1729 rt2800_register_multiwrite(rt2x00dev, offset, 1730 &key_entry, sizeof(key_entry)); 1731 } 1732 1733 /* 1734 * The cipher types are stored over multiple registers 1735 * starting with SHARED_KEY_MODE_BASE each word will have 1736 * 32 bits and contains the cipher types for 2 bssidx each. 1737 * Using the correct defines correctly will cause overhead, 1738 * so just calculate the correct offset. 1739 */ 1740 field.bit_offset = 4 * (key->hw_key_idx % 8); 1741 field.bit_mask = 0x7 << field.bit_offset; 1742 1743 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1744 1745 reg = rt2800_register_read(rt2x00dev, offset); 1746 rt2x00_set_field32(®, field, 1747 (crypto->cmd == SET_KEY) * crypto->cipher); 1748 rt2800_register_write(rt2x00dev, offset, reg); 1749 1750 /* 1751 * Update WCID information 1752 */ 1753 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1754 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1755 crypto->bssidx); 1756 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1757 1758 return 0; 1759 } 1760 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1761 1762 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1763 struct rt2x00lib_crypto *crypto, 1764 struct ieee80211_key_conf *key) 1765 { 1766 struct hw_key_entry key_entry; 1767 u32 offset; 1768 1769 if (crypto->cmd == SET_KEY) { 1770 /* 1771 * Allow key configuration only for STAs that are 1772 * known by the hw. 1773 */ 1774 if (crypto->wcid > WCID_END) 1775 return -ENOSPC; 1776 key->hw_key_idx = crypto->wcid; 1777 1778 memcpy(key_entry.key, crypto->key, 1779 sizeof(key_entry.key)); 1780 memcpy(key_entry.tx_mic, crypto->tx_mic, 1781 sizeof(key_entry.tx_mic)); 1782 memcpy(key_entry.rx_mic, crypto->rx_mic, 1783 sizeof(key_entry.rx_mic)); 1784 1785 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1786 rt2800_register_multiwrite(rt2x00dev, offset, 1787 &key_entry, sizeof(key_entry)); 1788 } 1789 1790 /* 1791 * Update WCID information 1792 */ 1793 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1794 1795 return 0; 1796 } 1797 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1798 1799 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1800 { 1801 u8 i, max_psdu; 1802 u32 reg; 1803 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1804 1805 for (i = 0; i < 3; i++) 1806 if (drv_data->ampdu_factor_cnt[i] > 0) 1807 break; 1808 1809 max_psdu = min(drv_data->max_psdu, i); 1810 1811 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1812 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1813 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1814 } 1815 1816 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1817 struct ieee80211_sta *sta) 1818 { 1819 struct rt2x00_dev *rt2x00dev = hw->priv; 1820 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1821 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1822 int wcid; 1823 1824 /* 1825 * Limit global maximum TX AMPDU length to smallest value of all 1826 * connected stations. In AP mode this can be suboptimal, but we 1827 * do not have a choice if some connected STA is not capable to 1828 * receive the same amount of data like the others. 1829 */ 1830 if (sta->deflink.ht_cap.ht_supported) { 1831 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++; 1832 rt2800_set_max_psdu_len(rt2x00dev); 1833 } 1834 1835 /* 1836 * Search for the first free WCID entry and return the corresponding 1837 * index. 1838 */ 1839 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1840 1841 /* 1842 * Store selected wcid even if it is invalid so that we can 1843 * later decide if the STA is uploaded into the hw. 1844 */ 1845 sta_priv->wcid = wcid; 1846 1847 /* 1848 * No space left in the device, however, we can still communicate 1849 * with the STA -> No error. 1850 */ 1851 if (wcid > WCID_END) 1852 return 0; 1853 1854 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1855 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1856 1857 /* 1858 * Clean up WCID attributes and write STA address to the device. 1859 */ 1860 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1861 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1862 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1863 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1864 return 0; 1865 } 1866 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1867 1868 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1869 struct ieee80211_sta *sta) 1870 { 1871 struct rt2x00_dev *rt2x00dev = hw->priv; 1872 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1873 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1874 int wcid = sta_priv->wcid; 1875 1876 if (sta->deflink.ht_cap.ht_supported) { 1877 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--; 1878 rt2800_set_max_psdu_len(rt2x00dev); 1879 } 1880 1881 if (wcid > WCID_END) 1882 return 0; 1883 /* 1884 * Remove WCID entry, no need to clean the attributes as they will 1885 * get renewed when the WCID is reused. 1886 */ 1887 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1888 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1889 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1890 1891 return 0; 1892 } 1893 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1894 1895 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev) 1896 { 1897 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1898 struct data_queue *queue = rt2x00dev->bcn; 1899 struct queue_entry *entry; 1900 int i, wcid; 1901 1902 for (wcid = WCID_START; wcid < WCID_END; wcid++) { 1903 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1904 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1905 } 1906 1907 for (i = 0; i < queue->limit; i++) { 1908 entry = &queue->entries[i]; 1909 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags); 1910 } 1911 } 1912 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw); 1913 1914 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1915 const unsigned int filter_flags) 1916 { 1917 u32 reg; 1918 1919 /* 1920 * Start configuration steps. 1921 * Note that the version error will always be dropped 1922 * and broadcast frames will always be accepted since 1923 * there is no filter for it at this time. 1924 */ 1925 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1926 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1927 !(filter_flags & FIF_FCSFAIL)); 1928 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1929 !(filter_flags & FIF_PLCPFAIL)); 1930 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1931 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1932 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1933 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1934 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1935 !(filter_flags & FIF_ALLMULTI)); 1936 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1937 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1938 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1939 !(filter_flags & FIF_CONTROL)); 1940 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1941 !(filter_flags & FIF_CONTROL)); 1942 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1943 !(filter_flags & FIF_CONTROL)); 1944 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1945 !(filter_flags & FIF_CONTROL)); 1946 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1947 !(filter_flags & FIF_CONTROL)); 1948 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1949 !(filter_flags & FIF_PSPOLL)); 1950 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1951 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1952 !(filter_flags & FIF_CONTROL)); 1953 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1954 !(filter_flags & FIF_CONTROL)); 1955 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1956 } 1957 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1958 1959 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1960 struct rt2x00intf_conf *conf, const unsigned int flags) 1961 { 1962 u32 reg; 1963 bool update_bssid = false; 1964 1965 if (flags & CONFIG_UPDATE_TYPE) { 1966 /* 1967 * Enable synchronisation. 1968 */ 1969 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1970 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1971 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1972 1973 if (conf->sync == TSF_SYNC_AP_NONE) { 1974 /* 1975 * Tune beacon queue transmit parameters for AP mode 1976 */ 1977 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1978 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1979 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1980 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1981 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1982 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1983 } else { 1984 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1985 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1986 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1987 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1988 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1989 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1990 } 1991 } 1992 1993 if (flags & CONFIG_UPDATE_MAC) { 1994 if (flags & CONFIG_UPDATE_TYPE && 1995 conf->sync == TSF_SYNC_AP_NONE) { 1996 /* 1997 * The BSSID register has to be set to our own mac 1998 * address in AP mode. 1999 */ 2000 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 2001 update_bssid = true; 2002 } 2003 2004 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 2005 reg = le32_to_cpu(conf->mac[1]); 2006 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 2007 conf->mac[1] = cpu_to_le32(reg); 2008 } 2009 2010 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 2011 conf->mac, sizeof(conf->mac)); 2012 } 2013 2014 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 2015 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 2016 reg = le32_to_cpu(conf->bssid[1]); 2017 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 2018 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 2019 conf->bssid[1] = cpu_to_le32(reg); 2020 } 2021 2022 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 2023 conf->bssid, sizeof(conf->bssid)); 2024 } 2025 } 2026 EXPORT_SYMBOL_GPL(rt2800_config_intf); 2027 2028 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 2029 struct rt2x00lib_erp *erp) 2030 { 2031 bool any_sta_nongf = !!(erp->ht_opmode & 2032 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 2033 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 2034 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 2035 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 2036 u32 reg; 2037 2038 /* default protection rate for HT20: OFDM 24M */ 2039 mm20_rate = gf20_rate = 0x4004; 2040 2041 /* default protection rate for HT40: duplicate OFDM 24M */ 2042 mm40_rate = gf40_rate = 0x4084; 2043 2044 switch (protection) { 2045 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 2046 /* 2047 * All STAs in this BSS are HT20/40 but there might be 2048 * STAs not supporting greenfield mode. 2049 * => Disable protection for HT transmissions. 2050 */ 2051 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 2052 2053 break; 2054 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2055 /* 2056 * All STAs in this BSS are HT20 or HT20/40 but there 2057 * might be STAs not supporting greenfield mode. 2058 * => Protect all HT40 transmissions. 2059 */ 2060 mm20_mode = gf20_mode = 0; 2061 mm40_mode = gf40_mode = 1; 2062 2063 break; 2064 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 2065 /* 2066 * Nonmember protection: 2067 * According to 802.11n we _should_ protect all 2068 * HT transmissions (but we don't have to). 2069 * 2070 * But if cts_protection is enabled we _shall_ protect 2071 * all HT transmissions using a CCK rate. 2072 * 2073 * And if any station is non GF we _shall_ protect 2074 * GF transmissions. 2075 * 2076 * We decide to protect everything 2077 * -> fall through to mixed mode. 2078 */ 2079 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2080 /* 2081 * Legacy STAs are present 2082 * => Protect all HT transmissions. 2083 */ 2084 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 2085 2086 /* 2087 * If erp protection is needed we have to protect HT 2088 * transmissions with CCK 11M long preamble. 2089 */ 2090 if (erp->cts_protection) { 2091 /* don't duplicate RTS/CTS in CCK mode */ 2092 mm20_rate = mm40_rate = 0x0003; 2093 gf20_rate = gf40_rate = 0x0003; 2094 } 2095 break; 2096 } 2097 2098 /* check for STAs not supporting greenfield mode */ 2099 if (any_sta_nongf) 2100 gf20_mode = gf40_mode = 1; 2101 2102 /* Update HT protection config */ 2103 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 2104 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 2105 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 2106 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 2107 2108 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 2109 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 2110 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 2111 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 2112 2113 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 2114 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 2115 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 2116 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2117 2118 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 2119 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 2120 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2121 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2122 } 2123 2124 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2125 u32 changed) 2126 { 2127 u32 reg; 2128 2129 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2130 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2131 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2132 !!erp->short_preamble); 2133 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2134 } 2135 2136 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2137 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2138 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2139 erp->cts_protection ? 2 : 0); 2140 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2141 } 2142 2143 if (changed & BSS_CHANGED_BASIC_RATES) { 2144 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2145 0xff0 | erp->basic_rates); 2146 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2147 } 2148 2149 if (changed & BSS_CHANGED_ERP_SLOT) { 2150 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2151 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2152 erp->slot_time); 2153 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2154 2155 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2156 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2157 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2158 } 2159 2160 if (changed & BSS_CHANGED_BEACON_INT) { 2161 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2162 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2163 erp->beacon_int * 16); 2164 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2165 } 2166 2167 if (changed & BSS_CHANGED_HT) 2168 rt2800_config_ht_opmode(rt2x00dev, erp); 2169 } 2170 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2171 2172 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev, 2173 const struct rt2x00_field32 mask) 2174 { 2175 unsigned int i; 2176 u32 reg; 2177 2178 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2179 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 2180 if (!rt2x00_get_field32(reg, mask)) 2181 return 0; 2182 2183 udelay(REGISTER_BUSY_DELAY); 2184 } 2185 2186 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 2187 return -EACCES; 2188 } 2189 2190 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 2191 { 2192 unsigned int i; 2193 u8 value; 2194 2195 /* 2196 * BBP was enabled after firmware was loaded, 2197 * but we need to reactivate it now. 2198 */ 2199 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 2200 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 2201 msleep(1); 2202 2203 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2204 value = rt2800_bbp_read(rt2x00dev, 0); 2205 if ((value != 0xff) && (value != 0x00)) 2206 return 0; 2207 udelay(REGISTER_BUSY_DELAY); 2208 } 2209 2210 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 2211 return -EACCES; 2212 } 2213 2214 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2215 { 2216 u32 reg; 2217 u16 eeprom; 2218 u8 led_ctrl, led_g_mode, led_r_mode; 2219 2220 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2221 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2222 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2223 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2224 } else { 2225 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2226 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2227 } 2228 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2229 2230 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2231 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2232 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2233 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2234 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2235 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2236 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2237 if (led_ctrl == 0 || led_ctrl > 0x40) { 2238 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2239 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2240 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2241 } else { 2242 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2243 (led_g_mode << 2) | led_r_mode, 1); 2244 } 2245 } 2246 } 2247 2248 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2249 enum antenna ant) 2250 { 2251 u32 reg; 2252 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2253 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2254 2255 if (rt2x00_is_pci(rt2x00dev)) { 2256 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2257 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2258 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2259 } else if (rt2x00_is_usb(rt2x00dev)) 2260 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2261 eesk_pin, 0); 2262 2263 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2264 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2265 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2266 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2267 } 2268 2269 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2270 { 2271 u8 r1; 2272 u8 r3; 2273 u16 eeprom; 2274 2275 r1 = rt2800_bbp_read(rt2x00dev, 1); 2276 r3 = rt2800_bbp_read(rt2x00dev, 3); 2277 2278 if (rt2x00_rt(rt2x00dev, RT3572) && 2279 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2280 rt2800_config_3572bt_ant(rt2x00dev); 2281 2282 /* 2283 * Configure the TX antenna. 2284 */ 2285 switch (ant->tx_chain_num) { 2286 case 1: 2287 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2288 break; 2289 case 2: 2290 if (rt2x00_rt(rt2x00dev, RT3572) && 2291 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2292 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2293 else 2294 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2295 break; 2296 case 3: 2297 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2298 break; 2299 } 2300 2301 /* 2302 * Configure the RX antenna. 2303 */ 2304 switch (ant->rx_chain_num) { 2305 case 1: 2306 if (rt2x00_rt(rt2x00dev, RT3070) || 2307 rt2x00_rt(rt2x00dev, RT3090) || 2308 rt2x00_rt(rt2x00dev, RT3352) || 2309 rt2x00_rt(rt2x00dev, RT3390)) { 2310 eeprom = rt2800_eeprom_read(rt2x00dev, 2311 EEPROM_NIC_CONF1); 2312 if (rt2x00_get_field16(eeprom, 2313 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2314 rt2800_set_ant_diversity(rt2x00dev, 2315 rt2x00dev->default_ant.rx); 2316 } 2317 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2318 break; 2319 case 2: 2320 if (rt2x00_rt(rt2x00dev, RT3572) && 2321 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2322 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2323 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2324 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2325 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2326 } else { 2327 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2328 } 2329 break; 2330 case 3: 2331 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2332 break; 2333 } 2334 2335 rt2800_bbp_write(rt2x00dev, 3, r3); 2336 rt2800_bbp_write(rt2x00dev, 1, r1); 2337 2338 if (rt2x00_rt(rt2x00dev, RT3593) || 2339 rt2x00_rt(rt2x00dev, RT3883)) { 2340 if (ant->rx_chain_num == 1) 2341 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2342 else 2343 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2344 } 2345 } 2346 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2347 2348 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2349 struct rt2x00lib_conf *libconf) 2350 { 2351 u16 eeprom; 2352 short lna_gain; 2353 2354 if (libconf->rf.channel <= 14) { 2355 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2356 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2357 } else if (libconf->rf.channel <= 64) { 2358 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2359 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2360 } else if (libconf->rf.channel <= 128) { 2361 if (rt2x00_rt(rt2x00dev, RT3593) || 2362 rt2x00_rt(rt2x00dev, RT3883)) { 2363 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2364 lna_gain = rt2x00_get_field16(eeprom, 2365 EEPROM_EXT_LNA2_A1); 2366 } else { 2367 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2368 lna_gain = rt2x00_get_field16(eeprom, 2369 EEPROM_RSSI_BG2_LNA_A1); 2370 } 2371 } else { 2372 if (rt2x00_rt(rt2x00dev, RT3593) || 2373 rt2x00_rt(rt2x00dev, RT3883)) { 2374 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2375 lna_gain = rt2x00_get_field16(eeprom, 2376 EEPROM_EXT_LNA2_A2); 2377 } else { 2378 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2379 lna_gain = rt2x00_get_field16(eeprom, 2380 EEPROM_RSSI_A2_LNA_A2); 2381 } 2382 } 2383 2384 rt2x00dev->lna_gain = lna_gain; 2385 } 2386 2387 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2388 { 2389 return clk_get_rate(rt2x00dev->clk) == 20000000; 2390 } 2391 2392 #define FREQ_OFFSET_BOUND 0x5f 2393 2394 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2395 { 2396 u8 freq_offset, prev_freq_offset; 2397 u8 rfcsr, prev_rfcsr; 2398 2399 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2400 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2401 2402 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2403 prev_rfcsr = rfcsr; 2404 2405 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2406 if (rfcsr == prev_rfcsr) 2407 return; 2408 2409 if (rt2x00_is_usb(rt2x00dev)) { 2410 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2411 freq_offset, prev_rfcsr); 2412 return; 2413 } 2414 2415 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2416 while (prev_freq_offset != freq_offset) { 2417 if (prev_freq_offset < freq_offset) 2418 prev_freq_offset++; 2419 else 2420 prev_freq_offset--; 2421 2422 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2423 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2424 2425 usleep_range(1000, 1500); 2426 } 2427 } 2428 2429 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2430 struct ieee80211_conf *conf, 2431 struct rf_channel *rf, 2432 struct channel_info *info) 2433 { 2434 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2435 2436 if (rt2x00dev->default_ant.tx_chain_num == 1) 2437 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2438 2439 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2440 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2441 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2442 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2443 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2444 2445 if (rf->channel > 14) { 2446 /* 2447 * When TX power is below 0, we should increase it by 7 to 2448 * make it a positive value (Minimum value is -7). 2449 * However this means that values between 0 and 7 have 2450 * double meaning, and we should set a 7DBm boost flag. 2451 */ 2452 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2453 (info->default_power1 >= 0)); 2454 2455 if (info->default_power1 < 0) 2456 info->default_power1 += 7; 2457 2458 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2459 2460 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2461 (info->default_power2 >= 0)); 2462 2463 if (info->default_power2 < 0) 2464 info->default_power2 += 7; 2465 2466 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2467 } else { 2468 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2469 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2470 } 2471 2472 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2473 2474 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2475 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2476 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2477 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2478 2479 udelay(200); 2480 2481 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2482 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2483 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2484 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2485 2486 udelay(200); 2487 2488 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2489 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2490 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2491 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2492 } 2493 2494 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2495 struct ieee80211_conf *conf, 2496 struct rf_channel *rf, 2497 struct channel_info *info) 2498 { 2499 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2500 u8 rfcsr, calib_tx, calib_rx; 2501 2502 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2503 2504 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2505 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2506 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2507 2508 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2509 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2510 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2511 2512 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2513 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2514 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2515 2516 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2517 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2518 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2519 2520 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2521 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2522 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2523 rt2x00dev->default_ant.rx_chain_num <= 1); 2524 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2525 rt2x00dev->default_ant.rx_chain_num <= 2); 2526 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2527 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2528 rt2x00dev->default_ant.tx_chain_num <= 1); 2529 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2530 rt2x00dev->default_ant.tx_chain_num <= 2); 2531 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2532 2533 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2534 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2535 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2536 2537 if (rt2x00_rt(rt2x00dev, RT3390)) { 2538 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2539 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2540 } else { 2541 if (conf_is_ht40(conf)) { 2542 calib_tx = drv_data->calibration_bw40; 2543 calib_rx = drv_data->calibration_bw40; 2544 } else { 2545 calib_tx = drv_data->calibration_bw20; 2546 calib_rx = drv_data->calibration_bw20; 2547 } 2548 } 2549 2550 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2551 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2552 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2553 2554 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2555 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2556 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2557 2558 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2559 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2560 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2561 2562 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2563 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2564 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2565 2566 usleep_range(1000, 1500); 2567 2568 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2569 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2570 } 2571 2572 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2573 struct ieee80211_conf *conf, 2574 struct rf_channel *rf, 2575 struct channel_info *info) 2576 { 2577 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2578 u8 rfcsr; 2579 u32 reg; 2580 2581 if (rf->channel <= 14) { 2582 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2583 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2584 } else { 2585 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2586 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2587 } 2588 2589 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2590 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2591 2592 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2593 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2594 if (rf->channel <= 14) 2595 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2596 else 2597 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2598 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2599 2600 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2601 if (rf->channel <= 14) 2602 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2603 else 2604 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2605 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2606 2607 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2608 if (rf->channel <= 14) { 2609 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2610 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2611 info->default_power1); 2612 } else { 2613 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2614 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2615 (info->default_power1 & 0x3) | 2616 ((info->default_power1 & 0xC) << 1)); 2617 } 2618 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2619 2620 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2621 if (rf->channel <= 14) { 2622 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2623 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2624 info->default_power2); 2625 } else { 2626 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2627 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2628 (info->default_power2 & 0x3) | 2629 ((info->default_power2 & 0xC) << 1)); 2630 } 2631 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2632 2633 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2634 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2635 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2636 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2637 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2638 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2639 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2640 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2641 if (rf->channel <= 14) { 2642 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2643 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2644 } 2645 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2646 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2647 } else { 2648 switch (rt2x00dev->default_ant.tx_chain_num) { 2649 case 1: 2650 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2651 fallthrough; 2652 case 2: 2653 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2654 break; 2655 } 2656 2657 switch (rt2x00dev->default_ant.rx_chain_num) { 2658 case 1: 2659 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2660 fallthrough; 2661 case 2: 2662 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2663 break; 2664 } 2665 } 2666 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2667 2668 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2669 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2670 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2671 2672 if (conf_is_ht40(conf)) { 2673 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2674 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2675 } else { 2676 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2677 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2678 } 2679 2680 if (rf->channel <= 14) { 2681 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2682 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2683 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2684 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2685 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2686 rfcsr = 0x4c; 2687 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2688 drv_data->txmixer_gain_24g); 2689 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2690 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2691 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2692 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2693 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2694 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2695 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2696 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2697 } else { 2698 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2699 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2700 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2701 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2702 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2703 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2704 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2705 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2706 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2707 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2708 rfcsr = 0x7a; 2709 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2710 drv_data->txmixer_gain_5g); 2711 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2712 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2713 if (rf->channel <= 64) { 2714 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2715 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2716 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2717 } else if (rf->channel <= 128) { 2718 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2719 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2720 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2721 } else { 2722 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2723 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2724 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2725 } 2726 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2727 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2728 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2729 } 2730 2731 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2732 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2733 if (rf->channel <= 14) 2734 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2735 else 2736 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2737 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2738 2739 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2740 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2741 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2742 } 2743 2744 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2745 struct ieee80211_conf *conf, 2746 struct rf_channel *rf, 2747 struct channel_info *info) 2748 { 2749 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2750 u8 txrx_agc_fc; 2751 u8 txrx_h20m; 2752 u8 rfcsr; 2753 u8 bbp; 2754 const bool txbf_enabled = false; /* TODO */ 2755 2756 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2757 bbp = rt2800_bbp_read(rt2x00dev, 109); 2758 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2759 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2760 rt2800_bbp_write(rt2x00dev, 109, bbp); 2761 2762 bbp = rt2800_bbp_read(rt2x00dev, 110); 2763 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2764 rt2800_bbp_write(rt2x00dev, 110, bbp); 2765 2766 if (rf->channel <= 14) { 2767 /* Restore BBP 25 & 26 for 2.4 GHz */ 2768 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2769 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2770 } else { 2771 /* Hard code BBP 25 & 26 for 5GHz */ 2772 2773 /* Enable IQ Phase correction */ 2774 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2775 /* Setup IQ Phase correction value */ 2776 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2777 } 2778 2779 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2780 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2781 2782 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2783 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2784 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2785 2786 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2787 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2788 if (rf->channel <= 14) 2789 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2790 else 2791 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2792 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2793 2794 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2795 if (rf->channel <= 14) { 2796 rfcsr = 0; 2797 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2798 info->default_power1 & 0x1f); 2799 } else { 2800 if (rt2x00_is_usb(rt2x00dev)) 2801 rfcsr = 0x40; 2802 2803 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2804 ((info->default_power1 & 0x18) << 1) | 2805 (info->default_power1 & 7)); 2806 } 2807 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2808 2809 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2810 if (rf->channel <= 14) { 2811 rfcsr = 0; 2812 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2813 info->default_power2 & 0x1f); 2814 } else { 2815 if (rt2x00_is_usb(rt2x00dev)) 2816 rfcsr = 0x40; 2817 2818 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2819 ((info->default_power2 & 0x18) << 1) | 2820 (info->default_power2 & 7)); 2821 } 2822 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2823 2824 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2825 if (rf->channel <= 14) { 2826 rfcsr = 0; 2827 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2828 info->default_power3 & 0x1f); 2829 } else { 2830 if (rt2x00_is_usb(rt2x00dev)) 2831 rfcsr = 0x40; 2832 2833 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2834 ((info->default_power3 & 0x18) << 1) | 2835 (info->default_power3 & 7)); 2836 } 2837 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2838 2839 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2840 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2841 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2842 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2843 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2844 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2845 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2846 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2847 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2848 2849 switch (rt2x00dev->default_ant.tx_chain_num) { 2850 case 3: 2851 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2852 fallthrough; 2853 case 2: 2854 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2855 fallthrough; 2856 case 1: 2857 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2858 break; 2859 } 2860 2861 switch (rt2x00dev->default_ant.rx_chain_num) { 2862 case 3: 2863 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2864 fallthrough; 2865 case 2: 2866 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2867 fallthrough; 2868 case 1: 2869 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2870 break; 2871 } 2872 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2873 2874 rt2800_freq_cal_mode1(rt2x00dev); 2875 2876 if (conf_is_ht40(conf)) { 2877 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2878 RFCSR24_TX_AGC_FC); 2879 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2880 RFCSR24_TX_H20M); 2881 } else { 2882 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2883 RFCSR24_TX_AGC_FC); 2884 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2885 RFCSR24_TX_H20M); 2886 } 2887 2888 /* NOTE: the reference driver does not writes the new value 2889 * back to RFCSR 32 2890 */ 2891 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2892 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2893 2894 if (rf->channel <= 14) 2895 rfcsr = 0xa0; 2896 else 2897 rfcsr = 0x80; 2898 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2899 2900 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2901 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2902 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2903 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2904 2905 /* Band selection */ 2906 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2907 if (rf->channel <= 14) 2908 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2909 else 2910 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2911 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2912 2913 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2914 if (rf->channel <= 14) 2915 rfcsr = 0x3c; 2916 else 2917 rfcsr = 0x20; 2918 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2919 2920 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2921 if (rf->channel <= 14) 2922 rfcsr = 0x1a; 2923 else 2924 rfcsr = 0x12; 2925 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2926 2927 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2928 if (rf->channel >= 1 && rf->channel <= 14) 2929 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2930 else if (rf->channel >= 36 && rf->channel <= 64) 2931 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2932 else if (rf->channel >= 100 && rf->channel <= 128) 2933 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2934 else 2935 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2936 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2937 2938 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2939 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2940 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2941 2942 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2943 2944 if (rf->channel <= 14) { 2945 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2946 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2947 } else { 2948 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2949 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2950 } 2951 2952 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2953 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2954 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2955 2956 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2957 if (rf->channel <= 14) { 2958 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2959 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2960 } else { 2961 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2962 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2963 } 2964 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2965 2966 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2967 if (rf->channel <= 14) 2968 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2969 else 2970 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2971 2972 if (txbf_enabled) 2973 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2974 2975 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2976 2977 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2978 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2979 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2980 2981 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2982 if (rf->channel <= 14) 2983 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2984 else 2985 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2986 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2987 2988 if (rf->channel <= 14) { 2989 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2990 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2991 } else { 2992 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2993 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2994 } 2995 2996 /* Initiate VCO calibration */ 2997 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2998 if (rf->channel <= 14) { 2999 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3000 } else { 3001 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 3002 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 3003 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 3004 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 3005 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 3006 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3007 } 3008 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3009 3010 if (rf->channel >= 1 && rf->channel <= 14) { 3011 rfcsr = 0x23; 3012 if (txbf_enabled) 3013 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3014 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3015 3016 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 3017 } else if (rf->channel >= 36 && rf->channel <= 64) { 3018 rfcsr = 0x36; 3019 if (txbf_enabled) 3020 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3021 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 3022 3023 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 3024 } else if (rf->channel >= 100 && rf->channel <= 128) { 3025 rfcsr = 0x32; 3026 if (txbf_enabled) 3027 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3028 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3029 3030 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 3031 } else { 3032 rfcsr = 0x30; 3033 if (txbf_enabled) 3034 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3035 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3036 3037 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 3038 } 3039 } 3040 3041 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev, 3042 struct ieee80211_conf *conf, 3043 struct rf_channel *rf, 3044 struct channel_info *info) 3045 { 3046 u8 rfcsr; 3047 u8 bbp; 3048 u8 pwr1, pwr2, pwr3; 3049 3050 const bool txbf_enabled = false; /* TODO */ 3051 3052 /* TODO: add band selection */ 3053 3054 if (rf->channel <= 14) 3055 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3056 else if (rf->channel < 132) 3057 rt2800_rfcsr_write(rt2x00dev, 6, 0x80); 3058 else 3059 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3060 3061 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3062 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3063 3064 if (rf->channel <= 14) 3065 rt2800_rfcsr_write(rt2x00dev, 11, 0x46); 3066 else 3067 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 3068 3069 if (rf->channel <= 14) 3070 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 3071 else 3072 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3073 3074 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 3075 3076 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3077 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 3078 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 3079 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3080 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3081 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3082 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3083 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3084 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3085 3086 switch (rt2x00dev->default_ant.tx_chain_num) { 3087 case 3: 3088 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 3089 fallthrough; 3090 case 2: 3091 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3092 fallthrough; 3093 case 1: 3094 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3095 break; 3096 } 3097 3098 switch (rt2x00dev->default_ant.rx_chain_num) { 3099 case 3: 3100 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 3101 fallthrough; 3102 case 2: 3103 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3104 fallthrough; 3105 case 1: 3106 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3107 break; 3108 } 3109 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3110 3111 rt2800_freq_cal_mode1(rt2x00dev); 3112 3113 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3114 if (!conf_is_ht40(conf)) 3115 rfcsr &= ~(0x06); 3116 else 3117 rfcsr |= 0x06; 3118 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3119 3120 if (rf->channel <= 14) 3121 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0); 3122 else 3123 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3124 3125 if (conf_is_ht40(conf)) 3126 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3127 else 3128 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 3129 3130 if (rf->channel <= 14) 3131 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 3132 else 3133 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 3134 3135 /* loopback RF_BS */ 3136 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 3137 if (rf->channel <= 14) 3138 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 3139 else 3140 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 3141 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 3142 3143 if (rf->channel <= 14) 3144 rfcsr = 0x23; 3145 else if (rf->channel < 100) 3146 rfcsr = 0x36; 3147 else if (rf->channel < 132) 3148 rfcsr = 0x32; 3149 else 3150 rfcsr = 0x30; 3151 3152 if (txbf_enabled) 3153 rfcsr |= 0x40; 3154 3155 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3156 3157 if (rf->channel <= 14) 3158 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 3159 else 3160 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 3161 3162 if (rf->channel <= 14) 3163 rfcsr = 0xbb; 3164 else if (rf->channel < 100) 3165 rfcsr = 0xeb; 3166 else if (rf->channel < 132) 3167 rfcsr = 0xb3; 3168 else 3169 rfcsr = 0x9b; 3170 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr); 3171 3172 if (rf->channel <= 14) 3173 rfcsr = 0x8e; 3174 else 3175 rfcsr = 0x8a; 3176 3177 if (txbf_enabled) 3178 rfcsr |= 0x20; 3179 3180 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3181 3182 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 3183 3184 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 3185 if (rf->channel <= 14) 3186 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 3187 else 3188 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 3189 3190 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52); 3191 if (rf->channel <= 14) 3192 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 3193 else 3194 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 3195 3196 if (rf->channel <= 14) { 3197 pwr1 = info->default_power1 & 0x1f; 3198 pwr2 = info->default_power2 & 0x1f; 3199 pwr3 = info->default_power3 & 0x1f; 3200 } else { 3201 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) | 3202 (info->default_power1 & 0x7); 3203 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) | 3204 (info->default_power2 & 0x7); 3205 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) | 3206 (info->default_power3 & 0x7); 3207 } 3208 3209 rt2800_rfcsr_write(rt2x00dev, 53, pwr1); 3210 rt2800_rfcsr_write(rt2x00dev, 54, pwr2); 3211 rt2800_rfcsr_write(rt2x00dev, 55, pwr3); 3212 3213 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n", 3214 rf->channel, pwr1, pwr2, pwr3); 3215 3216 bbp = (info->default_power1 >> 5) | 3217 ((info->default_power2 & 0xe0) >> 1); 3218 rt2800_bbp_write(rt2x00dev, 109, bbp); 3219 3220 bbp = rt2800_bbp_read(rt2x00dev, 110); 3221 bbp &= 0x0f; 3222 bbp |= (info->default_power3 & 0xe0) >> 1; 3223 rt2800_bbp_write(rt2x00dev, 110, bbp); 3224 3225 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 3226 if (rf->channel <= 14) 3227 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 3228 else 3229 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 3230 3231 /* Enable RF tuning */ 3232 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3233 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3234 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3235 3236 udelay(2000); 3237 3238 bbp = rt2800_bbp_read(rt2x00dev, 49); 3239 /* clear update flag */ 3240 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe); 3241 rt2800_bbp_write(rt2x00dev, 49, bbp); 3242 3243 /* TODO: add calibration for TxBF */ 3244 } 3245 3246 #define POWER_BOUND 0x27 3247 #define POWER_BOUND_5G 0x2b 3248 3249 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 3250 struct ieee80211_conf *conf, 3251 struct rf_channel *rf, 3252 struct channel_info *info) 3253 { 3254 u8 rfcsr; 3255 3256 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3257 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3258 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3259 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3260 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3261 3262 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3263 if (info->default_power1 > POWER_BOUND) 3264 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3265 else 3266 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3267 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3268 3269 rt2800_freq_cal_mode1(rt2x00dev); 3270 3271 if (rf->channel <= 14) { 3272 if (rf->channel == 6) 3273 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 3274 else 3275 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3276 3277 if (rf->channel >= 1 && rf->channel <= 6) 3278 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 3279 else if (rf->channel >= 7 && rf->channel <= 11) 3280 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 3281 else if (rf->channel >= 12 && rf->channel <= 14) 3282 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 3283 } 3284 } 3285 3286 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 3287 struct ieee80211_conf *conf, 3288 struct rf_channel *rf, 3289 struct channel_info *info) 3290 { 3291 u8 rfcsr; 3292 3293 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3294 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3295 3296 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 3297 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 3298 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 3299 3300 if (info->default_power1 > POWER_BOUND) 3301 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 3302 else 3303 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 3304 3305 if (info->default_power2 > POWER_BOUND) 3306 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 3307 else 3308 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 3309 3310 rt2800_freq_cal_mode1(rt2x00dev); 3311 3312 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3313 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3314 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3315 3316 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 3317 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3318 else 3319 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3320 3321 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 3322 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3323 else 3324 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3325 3326 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3327 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3328 3329 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3330 3331 rt2800_rfcsr_write(rt2x00dev, 31, 80); 3332 } 3333 3334 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 3335 struct ieee80211_conf *conf, 3336 struct rf_channel *rf, 3337 struct channel_info *info) 3338 { 3339 u8 rfcsr; 3340 int idx = rf->channel-1; 3341 3342 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3343 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3344 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3345 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3346 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3347 3348 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3349 if (info->default_power1 > POWER_BOUND) 3350 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3351 else 3352 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3353 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3354 3355 if (rt2x00_rt(rt2x00dev, RT5392)) { 3356 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3357 if (info->default_power2 > POWER_BOUND) 3358 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 3359 else 3360 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 3361 info->default_power2); 3362 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3363 } 3364 3365 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3366 if (rt2x00_rt(rt2x00dev, RT5392)) { 3367 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3368 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3369 } 3370 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3371 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3372 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3373 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3374 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3375 3376 rt2800_freq_cal_mode1(rt2x00dev); 3377 3378 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3379 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3380 /* r55/r59 value array of channel 1~14 */ 3381 static const u8 r55_bt_rev[] = {0x83, 0x83, 3382 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3383 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3384 static const u8 r59_bt_rev[] = {0x0e, 0x0e, 3385 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3386 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3387 3388 rt2800_rfcsr_write(rt2x00dev, 55, 3389 r55_bt_rev[idx]); 3390 rt2800_rfcsr_write(rt2x00dev, 59, 3391 r59_bt_rev[idx]); 3392 } else { 3393 static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b, 3394 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3395 0x88, 0x88, 0x86, 0x85, 0x84}; 3396 3397 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3398 } 3399 } else { 3400 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3401 static const u8 r55_nonbt_rev[] = {0x23, 0x23, 3402 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3403 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3404 static const u8 r59_nonbt_rev[] = {0x07, 0x07, 3405 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3406 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3407 3408 rt2800_rfcsr_write(rt2x00dev, 55, 3409 r55_nonbt_rev[idx]); 3410 rt2800_rfcsr_write(rt2x00dev, 59, 3411 r59_nonbt_rev[idx]); 3412 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3413 rt2x00_rt(rt2x00dev, RT5392) || 3414 rt2x00_rt(rt2x00dev, RT6352)) { 3415 static const u8 r59_non_bt[] = {0x8f, 0x8f, 3416 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3417 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3418 3419 rt2800_rfcsr_write(rt2x00dev, 59, 3420 r59_non_bt[idx]); 3421 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3422 static const u8 r59_non_bt[] = {0x0b, 0x0b, 3423 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3424 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3425 3426 rt2800_rfcsr_write(rt2x00dev, 59, 3427 r59_non_bt[idx]); 3428 } 3429 } 3430 } 3431 3432 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3433 struct ieee80211_conf *conf, 3434 struct rf_channel *rf, 3435 struct channel_info *info) 3436 { 3437 u8 rfcsr, ep_reg; 3438 u32 reg; 3439 int power_bound; 3440 3441 /* TODO */ 3442 const bool is_11b = false; 3443 const bool is_type_ep = false; 3444 3445 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3446 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3447 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3448 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3449 3450 /* Order of values on rf_channel entry: N, K, mod, R */ 3451 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3452 3453 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3454 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3455 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3456 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3457 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3458 3459 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3460 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3461 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3462 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3463 3464 if (rf->channel <= 14) { 3465 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3466 /* FIXME: RF11 owerwrite ? */ 3467 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3468 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3469 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3470 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3471 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3472 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3473 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3474 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3475 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3476 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3477 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3478 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3479 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3480 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3481 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3482 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3483 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3484 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3485 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3486 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3487 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3488 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3489 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3490 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3491 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3492 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3493 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3494 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3495 3496 /* TODO RF27 <- tssi */ 3497 3498 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3499 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3500 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3501 3502 if (is_11b) { 3503 /* CCK */ 3504 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3505 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3506 if (is_type_ep) 3507 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3508 else 3509 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3510 } else { 3511 /* OFDM */ 3512 if (is_type_ep) 3513 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3514 else 3515 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3516 } 3517 3518 power_bound = POWER_BOUND; 3519 ep_reg = 0x2; 3520 } else { 3521 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3522 /* FIMXE: RF11 overwrite */ 3523 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3524 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3525 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3526 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3527 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3528 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3529 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3530 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3531 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3532 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3533 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3534 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3535 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3536 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3537 3538 /* TODO RF27 <- tssi */ 3539 3540 if (rf->channel >= 36 && rf->channel <= 64) { 3541 3542 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3543 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3544 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3545 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3546 if (rf->channel <= 50) 3547 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3548 else if (rf->channel >= 52) 3549 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3550 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3551 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3552 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3553 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3554 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3555 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3556 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3557 if (rf->channel <= 50) { 3558 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3559 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3560 } else if (rf->channel >= 52) { 3561 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3562 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3563 } 3564 3565 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3566 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3567 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3568 3569 } else if (rf->channel >= 100 && rf->channel <= 165) { 3570 3571 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3572 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3573 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3574 if (rf->channel <= 153) { 3575 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3576 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3577 } else if (rf->channel >= 155) { 3578 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3579 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3580 } 3581 if (rf->channel <= 138) { 3582 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3583 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3584 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3585 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3586 } else if (rf->channel >= 140) { 3587 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3588 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3589 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3590 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3591 } 3592 if (rf->channel <= 124) 3593 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3594 else if (rf->channel >= 126) 3595 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3596 if (rf->channel <= 138) 3597 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3598 else if (rf->channel >= 140) 3599 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3600 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3601 if (rf->channel <= 138) 3602 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3603 else if (rf->channel >= 140) 3604 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3605 if (rf->channel <= 128) 3606 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3607 else if (rf->channel >= 130) 3608 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3609 if (rf->channel <= 116) 3610 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3611 else if (rf->channel >= 118) 3612 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3613 if (rf->channel <= 138) 3614 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3615 else if (rf->channel >= 140) 3616 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3617 if (rf->channel <= 116) 3618 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3619 else if (rf->channel >= 118) 3620 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3621 } 3622 3623 power_bound = POWER_BOUND_5G; 3624 ep_reg = 0x3; 3625 } 3626 3627 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3628 if (info->default_power1 > power_bound) 3629 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3630 else 3631 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3632 if (is_type_ep) 3633 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3634 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3635 3636 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3637 if (info->default_power2 > power_bound) 3638 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3639 else 3640 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3641 if (is_type_ep) 3642 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3643 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3644 3645 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3646 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3647 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3648 3649 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3650 rt2x00dev->default_ant.tx_chain_num >= 1); 3651 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3652 rt2x00dev->default_ant.tx_chain_num == 2); 3653 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3654 3655 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3656 rt2x00dev->default_ant.rx_chain_num >= 1); 3657 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3658 rt2x00dev->default_ant.rx_chain_num == 2); 3659 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3660 3661 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3662 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3663 3664 if (conf_is_ht40(conf)) 3665 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3666 else 3667 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3668 3669 if (!is_11b) { 3670 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3671 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3672 } 3673 3674 /* TODO proper frequency adjustment */ 3675 rt2800_freq_cal_mode1(rt2x00dev); 3676 3677 /* TODO merge with others */ 3678 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3679 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3680 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3681 3682 /* BBP settings */ 3683 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3684 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3685 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3686 3687 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3688 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3689 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3690 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3691 3692 /* GLRT band configuration */ 3693 rt2800_bbp_write(rt2x00dev, 195, 128); 3694 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3695 rt2800_bbp_write(rt2x00dev, 195, 129); 3696 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3697 rt2800_bbp_write(rt2x00dev, 195, 130); 3698 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3699 rt2800_bbp_write(rt2x00dev, 195, 131); 3700 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3701 rt2800_bbp_write(rt2x00dev, 195, 133); 3702 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3703 rt2800_bbp_write(rt2x00dev, 195, 124); 3704 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3705 } 3706 3707 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3708 struct ieee80211_conf *conf, 3709 struct rf_channel *rf, 3710 struct channel_info *info) 3711 { 3712 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3713 u8 rx_agc_fc, tx_agc_fc; 3714 u8 rfcsr; 3715 3716 /* Frequeny plan setting */ 3717 /* Rdiv setting (set 0x03 if Xtal==20) 3718 * R13[1:0] 3719 */ 3720 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3721 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3722 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3723 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3724 3725 /* N setting 3726 * R20[7:0] in rf->rf1 3727 * R21[0] always 0 3728 */ 3729 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3730 rfcsr = (rf->rf1 & 0x00ff); 3731 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3732 3733 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3734 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3735 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3736 3737 /* K setting (always 0) 3738 * R16[3:0] (RF PLL freq selection) 3739 */ 3740 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3741 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3742 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3743 3744 /* D setting (always 0) 3745 * R22[2:0] (D=15, R22[2:0]=<111>) 3746 */ 3747 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3748 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3749 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3750 3751 /* Ksd setting 3752 * Ksd: R17<7:0> in rf->rf2 3753 * R18<7:0> in rf->rf3 3754 * R19<1:0> in rf->rf4 3755 */ 3756 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3757 rfcsr = rf->rf2; 3758 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3759 3760 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3761 rfcsr = rf->rf3; 3762 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3763 3764 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3765 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3766 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3767 3768 /* Default: XO=20MHz , SDM mode */ 3769 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3770 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3771 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3772 3773 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3774 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3775 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3776 3777 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3778 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3779 rt2x00dev->default_ant.tx_chain_num != 1); 3780 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3781 3782 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3783 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3784 rt2x00dev->default_ant.tx_chain_num != 1); 3785 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3786 rt2x00dev->default_ant.rx_chain_num != 1); 3787 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3788 3789 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3790 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3791 rt2x00dev->default_ant.tx_chain_num != 1); 3792 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3793 3794 /* RF for DC Cal BW */ 3795 if (conf_is_ht40(conf)) { 3796 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3797 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3798 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3799 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3800 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3801 } else { 3802 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3803 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3804 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3805 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3806 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3807 } 3808 3809 if (conf_is_ht40(conf)) { 3810 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3811 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3812 } else { 3813 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3814 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3815 } 3816 3817 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3818 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3819 conf_is_ht40(conf) && (rf->channel == 11)); 3820 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3821 3822 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3823 if (conf_is_ht40(conf)) { 3824 rx_agc_fc = drv_data->rx_calibration_bw40; 3825 tx_agc_fc = drv_data->tx_calibration_bw40; 3826 } else { 3827 rx_agc_fc = drv_data->rx_calibration_bw20; 3828 tx_agc_fc = drv_data->tx_calibration_bw20; 3829 } 3830 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3831 rfcsr &= (~0x3F); 3832 rfcsr |= rx_agc_fc; 3833 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3834 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3835 rfcsr &= (~0x3F); 3836 rfcsr |= rx_agc_fc; 3837 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3838 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3839 rfcsr &= (~0x3F); 3840 rfcsr |= rx_agc_fc; 3841 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3842 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3843 rfcsr &= (~0x3F); 3844 rfcsr |= rx_agc_fc; 3845 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3846 3847 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3848 rfcsr &= (~0x3F); 3849 rfcsr |= tx_agc_fc; 3850 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3851 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3852 rfcsr &= (~0x3F); 3853 rfcsr |= tx_agc_fc; 3854 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3855 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3856 rfcsr &= (~0x3F); 3857 rfcsr |= tx_agc_fc; 3858 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3859 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3860 rfcsr &= (~0x3F); 3861 rfcsr |= tx_agc_fc; 3862 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3863 } 3864 } 3865 3866 static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev, 3867 struct ieee80211_channel *chan, 3868 int power_level) 3869 { 3870 int cur_channel = rt2x00dev->rf_channel; 3871 u16 eeprom, chan_power, rate_power, target_power; 3872 u16 tx_power[2]; 3873 s8 *power_group[2]; 3874 u32 mac_sys_ctrl; 3875 u32 cnt, reg; 3876 u8 bbp; 3877 3878 if (WARN_ON(cur_channel < 1 || cur_channel > 14)) 3879 return; 3880 3881 /* get per chain power, 2 chains in total, unit is 0.5dBm */ 3882 power_level = (power_level - 3) * 2; 3883 3884 /* We can't get the accurate TX power. Based on some tests, the real 3885 * TX power is approximately equal to channel_power + (max)rate_power. 3886 * Usually max rate_power is the gain of the OFDM 6M rate. The antenna 3887 * gain and externel PA gain are not included as we are unable to 3888 * obtain these values. 3889 */ 3890 rate_power = rt2800_eeprom_read_from_array(rt2x00dev, 3891 EEPROM_TXPOWER_BYRATE, 1); 3892 rate_power &= 0x3f; 3893 power_level -= rate_power; 3894 if (power_level < 1) 3895 power_level = 1; 3896 3897 power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 3898 power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 3899 for (cnt = 0; cnt < 2; cnt++) { 3900 chan_power = power_group[cnt][cur_channel - 1]; 3901 if (chan_power >= 0x20 || chan_power == 0) 3902 chan_power = 0x10; 3903 tx_power[cnt] = power_level < chan_power ? power_level : chan_power; 3904 } 3905 3906 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3907 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]); 3908 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]); 3909 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, 0x2f); 3910 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, 0x2f); 3911 3912 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3913 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3914 /* init base power by eeprom target power */ 3915 target_power = rt2800_eeprom_read(rt2x00dev, 3916 EEPROM_TXPOWER_INIT); 3917 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3918 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3919 } 3920 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3921 3922 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3923 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3924 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3925 3926 /* Save MAC SYS CTRL registers */ 3927 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3928 /* Disable Tx/Rx */ 3929 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3930 /* Check MAC Tx/Rx idle */ 3931 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 3932 rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n"); 3933 3934 if (chan->center_freq > 2457) { 3935 bbp = rt2800_bbp_read(rt2x00dev, 30); 3936 bbp = 0x40; 3937 rt2800_bbp_write(rt2x00dev, 30, bbp); 3938 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3939 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3940 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3941 else 3942 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3943 } else { 3944 bbp = rt2800_bbp_read(rt2x00dev, 30); 3945 bbp = 0x1f; 3946 rt2800_bbp_write(rt2x00dev, 30, bbp); 3947 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3948 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3949 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3950 else 3951 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3952 } 3953 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3954 3955 rt2800_vco_calibration(rt2x00dev); 3956 } 3957 3958 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3959 const unsigned int word, 3960 const u8 value) 3961 { 3962 u8 chain, reg; 3963 3964 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3965 reg = rt2800_bbp_read(rt2x00dev, 27); 3966 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3967 rt2800_bbp_write(rt2x00dev, 27, reg); 3968 3969 rt2800_bbp_write(rt2x00dev, word, value); 3970 } 3971 } 3972 3973 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3974 { 3975 u8 cal; 3976 3977 /* TX0 IQ Gain */ 3978 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3979 if (channel <= 14) 3980 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3981 else if (channel >= 36 && channel <= 64) 3982 cal = rt2x00_eeprom_byte(rt2x00dev, 3983 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3984 else if (channel >= 100 && channel <= 138) 3985 cal = rt2x00_eeprom_byte(rt2x00dev, 3986 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3987 else if (channel >= 140 && channel <= 165) 3988 cal = rt2x00_eeprom_byte(rt2x00dev, 3989 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3990 else 3991 cal = 0; 3992 rt2800_bbp_write(rt2x00dev, 159, cal); 3993 3994 /* TX0 IQ Phase */ 3995 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3996 if (channel <= 14) 3997 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3998 else if (channel >= 36 && channel <= 64) 3999 cal = rt2x00_eeprom_byte(rt2x00dev, 4000 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 4001 else if (channel >= 100 && channel <= 138) 4002 cal = rt2x00_eeprom_byte(rt2x00dev, 4003 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 4004 else if (channel >= 140 && channel <= 165) 4005 cal = rt2x00_eeprom_byte(rt2x00dev, 4006 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 4007 else 4008 cal = 0; 4009 rt2800_bbp_write(rt2x00dev, 159, cal); 4010 4011 /* TX1 IQ Gain */ 4012 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 4013 if (channel <= 14) 4014 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 4015 else if (channel >= 36 && channel <= 64) 4016 cal = rt2x00_eeprom_byte(rt2x00dev, 4017 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 4018 else if (channel >= 100 && channel <= 138) 4019 cal = rt2x00_eeprom_byte(rt2x00dev, 4020 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 4021 else if (channel >= 140 && channel <= 165) 4022 cal = rt2x00_eeprom_byte(rt2x00dev, 4023 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 4024 else 4025 cal = 0; 4026 rt2800_bbp_write(rt2x00dev, 159, cal); 4027 4028 /* TX1 IQ Phase */ 4029 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 4030 if (channel <= 14) 4031 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 4032 else if (channel >= 36 && channel <= 64) 4033 cal = rt2x00_eeprom_byte(rt2x00dev, 4034 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 4035 else if (channel >= 100 && channel <= 138) 4036 cal = rt2x00_eeprom_byte(rt2x00dev, 4037 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 4038 else if (channel >= 140 && channel <= 165) 4039 cal = rt2x00_eeprom_byte(rt2x00dev, 4040 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 4041 else 4042 cal = 0; 4043 rt2800_bbp_write(rt2x00dev, 159, cal); 4044 4045 /* FIXME: possible RX0, RX1 callibration ? */ 4046 4047 /* RF IQ compensation control */ 4048 rt2800_bbp_write(rt2x00dev, 158, 0x04); 4049 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 4050 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4051 4052 /* RF IQ imbalance compensation control */ 4053 rt2800_bbp_write(rt2x00dev, 158, 0x03); 4054 cal = rt2x00_eeprom_byte(rt2x00dev, 4055 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 4056 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4057 } 4058 4059 static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 4060 unsigned int channel, 4061 s8 txpower) 4062 { 4063 if (rt2x00_rt(rt2x00dev, RT3593) || 4064 rt2x00_rt(rt2x00dev, RT3883)) 4065 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 4066 4067 if (channel <= 14) 4068 return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 4069 4070 if (rt2x00_rt(rt2x00dev, RT3593) || 4071 rt2x00_rt(rt2x00dev, RT3883)) 4072 return clamp_t(s8, txpower, MIN_A_TXPOWER_3593, 4073 MAX_A_TXPOWER_3593); 4074 else 4075 return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 4076 } 4077 4078 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev, 4079 struct rf_channel *rf) 4080 { 4081 u8 bbp; 4082 4083 bbp = (rf->channel > 14) ? 0x48 : 0x38; 4084 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 4085 4086 rt2800_bbp_write(rt2x00dev, 69, 0x12); 4087 4088 if (rf->channel <= 14) { 4089 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4090 } else { 4091 /* Disable CCK packet detection */ 4092 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4093 } 4094 4095 rt2800_bbp_write(rt2x00dev, 73, 0x10); 4096 4097 if (rf->channel > 14) { 4098 rt2800_bbp_write(rt2x00dev, 62, 0x1d); 4099 rt2800_bbp_write(rt2x00dev, 63, 0x1d); 4100 rt2800_bbp_write(rt2x00dev, 64, 0x1d); 4101 } else { 4102 rt2800_bbp_write(rt2x00dev, 62, 0x2d); 4103 rt2800_bbp_write(rt2x00dev, 63, 0x2d); 4104 rt2800_bbp_write(rt2x00dev, 64, 0x2d); 4105 } 4106 } 4107 4108 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 4109 struct ieee80211_conf *conf, 4110 struct rf_channel *rf, 4111 struct channel_info *info) 4112 { 4113 u32 reg; 4114 u32 tx_pin; 4115 u8 bbp, rfcsr; 4116 4117 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4118 info->default_power1); 4119 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4120 info->default_power2); 4121 if (rt2x00dev->default_ant.tx_chain_num > 2) 4122 info->default_power3 = 4123 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4124 info->default_power3); 4125 4126 switch (rt2x00dev->chip.rt) { 4127 case RT3883: 4128 rt3883_bbp_adjust(rt2x00dev, rf); 4129 break; 4130 } 4131 4132 switch (rt2x00dev->chip.rf) { 4133 case RF2020: 4134 case RF3020: 4135 case RF3021: 4136 case RF3022: 4137 case RF3320: 4138 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 4139 break; 4140 case RF3052: 4141 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 4142 break; 4143 case RF3053: 4144 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 4145 break; 4146 case RF3290: 4147 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 4148 break; 4149 case RF3322: 4150 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 4151 break; 4152 case RF3853: 4153 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info); 4154 break; 4155 case RF3070: 4156 case RF5350: 4157 case RF5360: 4158 case RF5362: 4159 case RF5370: 4160 case RF5372: 4161 case RF5390: 4162 case RF5392: 4163 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 4164 break; 4165 case RF5592: 4166 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 4167 break; 4168 case RF7620: 4169 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 4170 break; 4171 default: 4172 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 4173 } 4174 4175 if (rt2x00_rf(rt2x00dev, RF3070) || 4176 rt2x00_rf(rt2x00dev, RF3290) || 4177 rt2x00_rf(rt2x00dev, RF3322) || 4178 rt2x00_rf(rt2x00dev, RF5350) || 4179 rt2x00_rf(rt2x00dev, RF5360) || 4180 rt2x00_rf(rt2x00dev, RF5362) || 4181 rt2x00_rf(rt2x00dev, RF5370) || 4182 rt2x00_rf(rt2x00dev, RF5372) || 4183 rt2x00_rf(rt2x00dev, RF5390) || 4184 rt2x00_rf(rt2x00dev, RF5392)) { 4185 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 4186 if (rt2x00_rf(rt2x00dev, RF3322)) { 4187 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 4188 conf_is_ht40(conf)); 4189 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 4190 conf_is_ht40(conf)); 4191 } else { 4192 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 4193 conf_is_ht40(conf)); 4194 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 4195 conf_is_ht40(conf)); 4196 } 4197 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 4198 4199 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4200 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4201 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4202 } 4203 4204 /* 4205 * Change BBP settings 4206 */ 4207 4208 if (rt2x00_rt(rt2x00dev, RT3352)) { 4209 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4210 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4211 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4212 4213 rt2800_bbp_write(rt2x00dev, 27, 0x0); 4214 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4215 rt2800_bbp_write(rt2x00dev, 27, 0x20); 4216 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4217 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4218 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 4219 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4220 if (rf->channel > 14) { 4221 /* Disable CCK Packet detection on 5GHz */ 4222 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4223 } else { 4224 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4225 } 4226 4227 if (conf_is_ht40(conf)) 4228 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4229 else 4230 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4231 4232 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4233 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4234 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4235 rt2800_bbp_write(rt2x00dev, 77, 0x98); 4236 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 4237 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4238 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4239 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4240 4241 if (rt2x00dev->default_ant.rx_chain_num > 1) 4242 rt2800_bbp_write(rt2x00dev, 86, 0x46); 4243 else 4244 rt2800_bbp_write(rt2x00dev, 86, 0); 4245 } else { 4246 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4247 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4248 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4249 if (rt2x00_rt(rt2x00dev, RT6352)) 4250 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4251 else 4252 rt2800_bbp_write(rt2x00dev, 86, 0); 4253 } 4254 4255 if (rf->channel <= 14) { 4256 if (!rt2x00_rt(rt2x00dev, RT5390) && 4257 !rt2x00_rt(rt2x00dev, RT5392) && 4258 !rt2x00_rt(rt2x00dev, RT6352)) { 4259 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4260 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4261 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4262 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4263 } else { 4264 if (rt2x00_rt(rt2x00dev, RT3593)) 4265 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4266 else 4267 rt2800_bbp_write(rt2x00dev, 82, 0x84); 4268 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4269 } 4270 if (rt2x00_rt(rt2x00dev, RT3593) || 4271 rt2x00_rt(rt2x00dev, RT3883)) 4272 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 4273 } 4274 4275 } else { 4276 if (rt2x00_rt(rt2x00dev, RT3572)) 4277 rt2800_bbp_write(rt2x00dev, 82, 0x94); 4278 else if (rt2x00_rt(rt2x00dev, RT3593) || 4279 rt2x00_rt(rt2x00dev, RT3883)) 4280 rt2800_bbp_write(rt2x00dev, 82, 0x82); 4281 else if (!rt2x00_rt(rt2x00dev, RT6352)) 4282 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 4283 4284 if (rt2x00_rt(rt2x00dev, RT3593) || 4285 rt2x00_rt(rt2x00dev, RT3883)) 4286 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 4287 4288 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 4289 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4290 else 4291 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4292 } 4293 4294 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 4295 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 4296 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 4297 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 4298 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 4299 4300 if (rt2x00_rt(rt2x00dev, RT3572)) 4301 rt2800_rfcsr_write(rt2x00dev, 8, 0); 4302 4303 if (rt2x00_rt(rt2x00dev, RT6352)) { 4304 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4305 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 4306 } else { 4307 tx_pin = 0; 4308 } 4309 4310 switch (rt2x00dev->default_ant.tx_chain_num) { 4311 case 3: 4312 /* Turn on tertiary PAs */ 4313 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 4314 rf->channel > 14); 4315 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 4316 rf->channel <= 14); 4317 fallthrough; 4318 case 2: 4319 /* Turn on secondary PAs */ 4320 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 4321 rf->channel > 14); 4322 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 4323 rf->channel <= 14); 4324 fallthrough; 4325 case 1: 4326 /* Turn on primary PAs */ 4327 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 4328 rf->channel > 14); 4329 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 4330 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4331 else 4332 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 4333 rf->channel <= 14); 4334 break; 4335 } 4336 4337 switch (rt2x00dev->default_ant.rx_chain_num) { 4338 case 3: 4339 /* Turn on tertiary LNAs */ 4340 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 4341 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 4342 fallthrough; 4343 case 2: 4344 /* Turn on secondary LNAs */ 4345 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 4346 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 4347 fallthrough; 4348 case 1: 4349 /* Turn on primary LNAs */ 4350 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 4351 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 4352 break; 4353 } 4354 4355 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 4356 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 4357 4358 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4359 4360 if (rt2x00_rt(rt2x00dev, RT3572)) { 4361 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 4362 4363 /* AGC init */ 4364 if (rf->channel <= 14) 4365 reg = 0x1c + (2 * rt2x00dev->lna_gain); 4366 else 4367 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4368 4369 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4370 } 4371 4372 if (rt2x00_rt(rt2x00dev, RT3593)) { 4373 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 4374 4375 /* Band selection */ 4376 if (rt2x00_is_usb(rt2x00dev) || 4377 rt2x00_is_pcie(rt2x00dev)) { 4378 /* GPIO #8 controls all paths */ 4379 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 4380 if (rf->channel <= 14) 4381 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 4382 else 4383 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 4384 } 4385 4386 /* LNA PE control. */ 4387 if (rt2x00_is_usb(rt2x00dev)) { 4388 /* GPIO #4 controls PE0 and PE1, 4389 * GPIO #7 controls PE2 4390 */ 4391 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4392 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 4393 4394 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4395 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 4396 } else if (rt2x00_is_pcie(rt2x00dev)) { 4397 /* GPIO #4 controls PE0, PE1 and PE2 */ 4398 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4399 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4400 } 4401 4402 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 4403 4404 /* AGC init */ 4405 if (rf->channel <= 14) 4406 reg = 0x1c + 2 * rt2x00dev->lna_gain; 4407 else 4408 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4409 4410 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4411 4412 usleep_range(1000, 1500); 4413 } 4414 4415 if (rt2x00_rt(rt2x00dev, RT3883)) { 4416 if (!conf_is_ht40(conf)) 4417 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4418 else 4419 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4420 4421 /* AGC init */ 4422 if (rf->channel <= 14) 4423 reg = 0x2e + rt2x00dev->lna_gain; 4424 else 4425 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); 4426 4427 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4428 4429 usleep_range(1000, 1500); 4430 } 4431 4432 if (rt2x00_rt(rt2x00dev, RT5592)) { 4433 bbp = conf_is_ht40(conf) ? 0x10 : 0x1a; 4434 rt2800_bbp_glrt_write(rt2x00dev, 141, bbp); 4435 4436 bbp = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; 4437 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 4438 4439 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4440 } 4441 4442 if (rt2x00_rt(rt2x00dev, RT6352)) { 4443 /* BBP for GLRT BW */ 4444 bbp = conf_is_ht40(conf) ? 4445 0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ? 4446 0x15 : 0x1a; 4447 rt2800_bbp_glrt_write(rt2x00dev, 141, bbp); 4448 4449 bbp = conf_is_ht40(conf) ? 0x2f : 0x40; 4450 rt2800_bbp_glrt_write(rt2x00dev, 157, bbp); 4451 4452 if (rt2x00dev->default_ant.rx_chain_num == 1) { 4453 rt2800_bbp_write(rt2x00dev, 91, 0x07); 4454 rt2800_bbp_write(rt2x00dev, 95, 0x1a); 4455 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xa0); 4456 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x12); 4457 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x10); 4458 } else { 4459 rt2800_bbp_write(rt2x00dev, 91, 0x06); 4460 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 4461 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xe0); 4462 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 4463 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 4464 } 4465 4466 /* AGC init */ 4467 bbp = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0; 4468 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 4469 4470 usleep_range(1000, 1500); 4471 } 4472 4473 bbp = rt2800_bbp_read(rt2x00dev, 4); 4474 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4475 rt2800_bbp_write(rt2x00dev, 4, bbp); 4476 4477 bbp = rt2800_bbp_read(rt2x00dev, 3); 4478 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4479 rt2800_bbp_write(rt2x00dev, 3, bbp); 4480 4481 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4482 if (conf_is_ht40(conf)) { 4483 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4484 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4485 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4486 } else { 4487 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4488 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4489 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4490 } 4491 } 4492 4493 usleep_range(1000, 1500); 4494 4495 /* 4496 * Clear channel statistic counters 4497 */ 4498 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4499 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4500 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4501 4502 /* 4503 * Clear update flag 4504 */ 4505 if (rt2x00_rt(rt2x00dev, RT3352) || 4506 rt2x00_rt(rt2x00dev, RT5350)) { 4507 bbp = rt2800_bbp_read(rt2x00dev, 49); 4508 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4509 rt2800_bbp_write(rt2x00dev, 49, bbp); 4510 } 4511 } 4512 4513 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4514 { 4515 u8 tssi_bounds[9]; 4516 u8 current_tssi; 4517 u16 eeprom; 4518 u8 step; 4519 int i; 4520 4521 /* 4522 * First check if temperature compensation is supported. 4523 */ 4524 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4525 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4526 return 0; 4527 4528 /* 4529 * Read TSSI boundaries for temperature compensation from 4530 * the EEPROM. 4531 * 4532 * Array idx 0 1 2 3 4 5 6 7 8 4533 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4534 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4535 */ 4536 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4537 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4538 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4539 EEPROM_TSSI_BOUND_BG1_MINUS4); 4540 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4541 EEPROM_TSSI_BOUND_BG1_MINUS3); 4542 4543 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4544 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4545 EEPROM_TSSI_BOUND_BG2_MINUS2); 4546 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4547 EEPROM_TSSI_BOUND_BG2_MINUS1); 4548 4549 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4550 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4551 EEPROM_TSSI_BOUND_BG3_REF); 4552 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4553 EEPROM_TSSI_BOUND_BG3_PLUS1); 4554 4555 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4556 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4557 EEPROM_TSSI_BOUND_BG4_PLUS2); 4558 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4559 EEPROM_TSSI_BOUND_BG4_PLUS3); 4560 4561 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4562 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4563 EEPROM_TSSI_BOUND_BG5_PLUS4); 4564 4565 step = rt2x00_get_field16(eeprom, 4566 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4567 } else { 4568 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4569 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4570 EEPROM_TSSI_BOUND_A1_MINUS4); 4571 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4572 EEPROM_TSSI_BOUND_A1_MINUS3); 4573 4574 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4575 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4576 EEPROM_TSSI_BOUND_A2_MINUS2); 4577 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4578 EEPROM_TSSI_BOUND_A2_MINUS1); 4579 4580 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4581 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4582 EEPROM_TSSI_BOUND_A3_REF); 4583 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4584 EEPROM_TSSI_BOUND_A3_PLUS1); 4585 4586 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4587 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4588 EEPROM_TSSI_BOUND_A4_PLUS2); 4589 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4590 EEPROM_TSSI_BOUND_A4_PLUS3); 4591 4592 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4593 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4594 EEPROM_TSSI_BOUND_A5_PLUS4); 4595 4596 step = rt2x00_get_field16(eeprom, 4597 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4598 } 4599 4600 /* 4601 * Check if temperature compensation is supported. 4602 */ 4603 if (tssi_bounds[4] == 0xff || step == 0xff) 4604 return 0; 4605 4606 /* 4607 * Read current TSSI (BBP 49). 4608 */ 4609 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4610 4611 /* 4612 * Compare TSSI value (BBP49) with the compensation boundaries 4613 * from the EEPROM and increase or decrease tx power. 4614 */ 4615 for (i = 0; i <= 3; i++) { 4616 if (current_tssi > tssi_bounds[i]) 4617 break; 4618 } 4619 4620 if (i == 4) { 4621 for (i = 8; i >= 5; i--) { 4622 if (current_tssi < tssi_bounds[i]) 4623 break; 4624 } 4625 } 4626 4627 return (i - 4) * step; 4628 } 4629 4630 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4631 enum nl80211_band band) 4632 { 4633 u16 eeprom; 4634 u8 comp_en; 4635 u8 comp_type; 4636 int comp_value = 0; 4637 4638 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4639 4640 /* 4641 * HT40 compensation not required. 4642 */ 4643 if (eeprom == 0xffff || 4644 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4645 return 0; 4646 4647 if (band == NL80211_BAND_2GHZ) { 4648 comp_en = rt2x00_get_field16(eeprom, 4649 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4650 if (comp_en) { 4651 comp_type = rt2x00_get_field16(eeprom, 4652 EEPROM_TXPOWER_DELTA_TYPE_2G); 4653 comp_value = rt2x00_get_field16(eeprom, 4654 EEPROM_TXPOWER_DELTA_VALUE_2G); 4655 if (!comp_type) 4656 comp_value = -comp_value; 4657 } 4658 } else { 4659 comp_en = rt2x00_get_field16(eeprom, 4660 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4661 if (comp_en) { 4662 comp_type = rt2x00_get_field16(eeprom, 4663 EEPROM_TXPOWER_DELTA_TYPE_5G); 4664 comp_value = rt2x00_get_field16(eeprom, 4665 EEPROM_TXPOWER_DELTA_VALUE_5G); 4666 if (!comp_type) 4667 comp_value = -comp_value; 4668 } 4669 } 4670 4671 return comp_value; 4672 } 4673 4674 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4675 int power_level, int max_power) 4676 { 4677 int delta; 4678 4679 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4680 return 0; 4681 4682 /* 4683 * XXX: We don't know the maximum transmit power of our hardware since 4684 * the EEPROM doesn't expose it. We only know that we are calibrated 4685 * to 100% tx power. 4686 * 4687 * Hence, we assume the regulatory limit that cfg80211 calulated for 4688 * the current channel is our maximum and if we are requested to lower 4689 * the value we just reduce our tx power accordingly. 4690 */ 4691 delta = power_level - max_power; 4692 return min(delta, 0); 4693 } 4694 4695 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4696 enum nl80211_band band, int power_level, 4697 u8 txpower, int delta) 4698 { 4699 u16 eeprom; 4700 u8 criterion; 4701 u8 eirp_txpower; 4702 u8 eirp_txpower_criterion; 4703 u8 reg_limit; 4704 4705 if (rt2x00_rt(rt2x00dev, RT3593)) 4706 return min_t(u8, txpower, 0xc); 4707 4708 if (rt2x00_rt(rt2x00dev, RT3883)) 4709 return min_t(u8, txpower, 0xf); 4710 4711 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4712 /* 4713 * Check if eirp txpower exceed txpower_limit. 4714 * We use OFDM 6M as criterion and its eirp txpower 4715 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4716 * .11b data rate need add additional 4dbm 4717 * when calculating eirp txpower. 4718 */ 4719 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4720 EEPROM_TXPOWER_BYRATE, 4721 1); 4722 criterion = rt2x00_get_field16(eeprom, 4723 EEPROM_TXPOWER_BYRATE_RATE0); 4724 4725 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4726 4727 if (band == NL80211_BAND_2GHZ) 4728 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4729 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4730 else 4731 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4732 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4733 4734 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4735 (is_rate_b ? 4 : 0) + delta; 4736 4737 reg_limit = (eirp_txpower > power_level) ? 4738 (eirp_txpower - power_level) : 0; 4739 } else 4740 reg_limit = 0; 4741 4742 txpower = max(0, txpower + delta - reg_limit); 4743 return min_t(u8, txpower, 0xc); 4744 } 4745 4746 4747 enum { 4748 TX_PWR_CFG_0_IDX, 4749 TX_PWR_CFG_1_IDX, 4750 TX_PWR_CFG_2_IDX, 4751 TX_PWR_CFG_3_IDX, 4752 TX_PWR_CFG_4_IDX, 4753 TX_PWR_CFG_5_IDX, 4754 TX_PWR_CFG_6_IDX, 4755 TX_PWR_CFG_7_IDX, 4756 TX_PWR_CFG_8_IDX, 4757 TX_PWR_CFG_9_IDX, 4758 TX_PWR_CFG_0_EXT_IDX, 4759 TX_PWR_CFG_1_EXT_IDX, 4760 TX_PWR_CFG_2_EXT_IDX, 4761 TX_PWR_CFG_3_EXT_IDX, 4762 TX_PWR_CFG_4_EXT_IDX, 4763 TX_PWR_CFG_IDX_COUNT, 4764 }; 4765 4766 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4767 struct ieee80211_channel *chan, 4768 int power_level) 4769 { 4770 u8 txpower; 4771 u16 eeprom; 4772 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4773 unsigned int offset; 4774 enum nl80211_band band = chan->band; 4775 int delta; 4776 int i; 4777 4778 memset(regs, '\0', sizeof(regs)); 4779 4780 /* TODO: adapt TX power reduction from the rt28xx code */ 4781 4782 /* calculate temperature compensation delta */ 4783 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4784 4785 if (band == NL80211_BAND_5GHZ) 4786 offset = 16; 4787 else 4788 offset = 0; 4789 4790 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4791 offset += 8; 4792 4793 /* read the next four txpower values */ 4794 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4795 offset); 4796 4797 /* CCK 1MBS,2MBS */ 4798 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4799 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4800 txpower, delta); 4801 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4802 TX_PWR_CFG_0_CCK1_CH0, txpower); 4803 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4804 TX_PWR_CFG_0_CCK1_CH1, txpower); 4805 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4806 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4807 4808 /* CCK 5.5MBS,11MBS */ 4809 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4810 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4811 txpower, delta); 4812 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4813 TX_PWR_CFG_0_CCK5_CH0, txpower); 4814 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4815 TX_PWR_CFG_0_CCK5_CH1, txpower); 4816 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4817 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4818 4819 /* OFDM 6MBS,9MBS */ 4820 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4821 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4822 txpower, delta); 4823 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4824 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4825 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4826 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4827 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4828 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4829 4830 /* OFDM 12MBS,18MBS */ 4831 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4832 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4833 txpower, delta); 4834 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4835 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4836 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4837 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4838 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4839 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4840 4841 /* read the next four txpower values */ 4842 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4843 offset + 1); 4844 4845 /* OFDM 24MBS,36MBS */ 4846 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4847 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4848 txpower, delta); 4849 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4850 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4851 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4852 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4853 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4854 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4855 4856 /* OFDM 48MBS */ 4857 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4858 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4859 txpower, delta); 4860 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4861 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4862 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4863 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4864 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4865 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4866 4867 /* OFDM 54MBS */ 4868 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4869 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4870 txpower, delta); 4871 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4872 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4873 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4874 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4875 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4876 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4877 4878 /* read the next four txpower values */ 4879 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4880 offset + 2); 4881 4882 /* MCS 0,1 */ 4883 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4884 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4885 txpower, delta); 4886 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4887 TX_PWR_CFG_1_MCS0_CH0, txpower); 4888 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4889 TX_PWR_CFG_1_MCS0_CH1, txpower); 4890 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4891 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4892 4893 /* MCS 2,3 */ 4894 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4895 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4896 txpower, delta); 4897 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4898 TX_PWR_CFG_1_MCS2_CH0, txpower); 4899 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4900 TX_PWR_CFG_1_MCS2_CH1, txpower); 4901 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4902 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4903 4904 /* MCS 4,5 */ 4905 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4906 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4907 txpower, delta); 4908 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4909 TX_PWR_CFG_2_MCS4_CH0, txpower); 4910 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4911 TX_PWR_CFG_2_MCS4_CH1, txpower); 4912 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4913 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4914 4915 /* MCS 6 */ 4916 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4917 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4918 txpower, delta); 4919 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4920 TX_PWR_CFG_2_MCS6_CH0, txpower); 4921 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4922 TX_PWR_CFG_2_MCS6_CH1, txpower); 4923 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4924 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4925 4926 /* read the next four txpower values */ 4927 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4928 offset + 3); 4929 4930 /* MCS 7 */ 4931 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4932 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4933 txpower, delta); 4934 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4935 TX_PWR_CFG_7_MCS7_CH0, txpower); 4936 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4937 TX_PWR_CFG_7_MCS7_CH1, txpower); 4938 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4939 TX_PWR_CFG_7_MCS7_CH2, txpower); 4940 4941 /* MCS 8,9 */ 4942 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4943 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4944 txpower, delta); 4945 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4946 TX_PWR_CFG_2_MCS8_CH0, txpower); 4947 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4948 TX_PWR_CFG_2_MCS8_CH1, txpower); 4949 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4950 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4951 4952 /* MCS 10,11 */ 4953 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4954 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4955 txpower, delta); 4956 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4957 TX_PWR_CFG_2_MCS10_CH0, txpower); 4958 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4959 TX_PWR_CFG_2_MCS10_CH1, txpower); 4960 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4961 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4962 4963 /* MCS 12,13 */ 4964 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4965 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4966 txpower, delta); 4967 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4968 TX_PWR_CFG_3_MCS12_CH0, txpower); 4969 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4970 TX_PWR_CFG_3_MCS12_CH1, txpower); 4971 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4972 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4973 4974 /* read the next four txpower values */ 4975 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4976 offset + 4); 4977 4978 /* MCS 14 */ 4979 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4980 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4981 txpower, delta); 4982 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4983 TX_PWR_CFG_3_MCS14_CH0, txpower); 4984 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4985 TX_PWR_CFG_3_MCS14_CH1, txpower); 4986 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4987 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4988 4989 /* MCS 15 */ 4990 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4991 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4992 txpower, delta); 4993 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4994 TX_PWR_CFG_8_MCS15_CH0, txpower); 4995 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4996 TX_PWR_CFG_8_MCS15_CH1, txpower); 4997 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4998 TX_PWR_CFG_8_MCS15_CH2, txpower); 4999 5000 /* MCS 16,17 */ 5001 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5002 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5003 txpower, delta); 5004 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5005 TX_PWR_CFG_5_MCS16_CH0, txpower); 5006 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5007 TX_PWR_CFG_5_MCS16_CH1, txpower); 5008 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5009 TX_PWR_CFG_5_MCS16_CH2, txpower); 5010 5011 /* MCS 18,19 */ 5012 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5013 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5014 txpower, delta); 5015 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5016 TX_PWR_CFG_5_MCS18_CH0, txpower); 5017 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5018 TX_PWR_CFG_5_MCS18_CH1, txpower); 5019 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5020 TX_PWR_CFG_5_MCS18_CH2, txpower); 5021 5022 /* read the next four txpower values */ 5023 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5024 offset + 5); 5025 5026 /* MCS 20,21 */ 5027 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5028 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5029 txpower, delta); 5030 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5031 TX_PWR_CFG_6_MCS20_CH0, txpower); 5032 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5033 TX_PWR_CFG_6_MCS20_CH1, txpower); 5034 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5035 TX_PWR_CFG_6_MCS20_CH2, txpower); 5036 5037 /* MCS 22 */ 5038 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5039 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5040 txpower, delta); 5041 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5042 TX_PWR_CFG_6_MCS22_CH0, txpower); 5043 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5044 TX_PWR_CFG_6_MCS22_CH1, txpower); 5045 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5046 TX_PWR_CFG_6_MCS22_CH2, txpower); 5047 5048 /* MCS 23 */ 5049 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5050 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5051 txpower, delta); 5052 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5053 TX_PWR_CFG_8_MCS23_CH0, txpower); 5054 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5055 TX_PWR_CFG_8_MCS23_CH1, txpower); 5056 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5057 TX_PWR_CFG_8_MCS23_CH2, txpower); 5058 5059 /* read the next four txpower values */ 5060 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5061 offset + 6); 5062 5063 /* STBC, MCS 0,1 */ 5064 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5065 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5066 txpower, delta); 5067 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5068 TX_PWR_CFG_3_STBC0_CH0, txpower); 5069 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5070 TX_PWR_CFG_3_STBC0_CH1, txpower); 5071 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5072 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 5073 5074 /* STBC, MCS 2,3 */ 5075 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5076 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5077 txpower, delta); 5078 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5079 TX_PWR_CFG_3_STBC2_CH0, txpower); 5080 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5081 TX_PWR_CFG_3_STBC2_CH1, txpower); 5082 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5083 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 5084 5085 /* STBC, MCS 4,5 */ 5086 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5087 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5088 txpower, delta); 5089 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 5090 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 5091 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 5092 txpower); 5093 5094 /* STBC, MCS 6 */ 5095 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5096 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5097 txpower, delta); 5098 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 5099 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 5100 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 5101 txpower); 5102 5103 /* read the next four txpower values */ 5104 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5105 offset + 7); 5106 5107 /* STBC, MCS 7 */ 5108 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5109 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5110 txpower, delta); 5111 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5112 TX_PWR_CFG_9_STBC7_CH0, txpower); 5113 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5114 TX_PWR_CFG_9_STBC7_CH1, txpower); 5115 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5116 TX_PWR_CFG_9_STBC7_CH2, txpower); 5117 5118 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 5119 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 5120 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 5121 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 5122 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 5123 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 5124 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 5125 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 5126 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 5127 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 5128 5129 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 5130 regs[TX_PWR_CFG_0_EXT_IDX]); 5131 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 5132 regs[TX_PWR_CFG_1_EXT_IDX]); 5133 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 5134 regs[TX_PWR_CFG_2_EXT_IDX]); 5135 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 5136 regs[TX_PWR_CFG_3_EXT_IDX]); 5137 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 5138 regs[TX_PWR_CFG_4_EXT_IDX]); 5139 5140 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 5141 rt2x00_dbg(rt2x00dev, 5142 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 5143 (band == NL80211_BAND_5GHZ) ? '5' : '2', 5144 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 5145 '4' : '2', 5146 (i > TX_PWR_CFG_9_IDX) ? 5147 (i - TX_PWR_CFG_9_IDX - 1) : i, 5148 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 5149 (unsigned long) regs[i]); 5150 } 5151 5152 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 5153 struct ieee80211_channel *chan, 5154 int power_level) 5155 { 5156 u32 reg, pwreg; 5157 u16 eeprom; 5158 u32 data, gdata; 5159 u8 t, i; 5160 enum nl80211_band band = chan->band; 5161 int delta; 5162 5163 /* Warn user if bw_comp is set in EEPROM */ 5164 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5165 5166 if (delta) 5167 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 5168 delta); 5169 5170 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 5171 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 5172 * driver does as well, though it looks kinda wrong. 5173 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 5174 * the hardware has a problem handling 0x20, and as the code initially 5175 * used a fixed offset between HT20 and HT40 rates they had to work- 5176 * around that issue and most likely just forgot about it later on. 5177 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 5178 * however, the corresponding EEPROM value is not respected by the 5179 * vendor driver, so maybe this is rather being taken care of the 5180 * TXALC and the driver doesn't need to handle it...? 5181 * Though this is all very awkward, just do as they did, as that's what 5182 * board vendors expected when they populated the EEPROM... 5183 */ 5184 for (i = 0; i < 5; i++) { 5185 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5186 EEPROM_TXPOWER_BYRATE, 5187 i * 2); 5188 5189 data = eeprom; 5190 5191 t = eeprom & 0x3f; 5192 if (t == 32) 5193 t++; 5194 5195 gdata = t; 5196 5197 t = (eeprom & 0x3f00) >> 8; 5198 if (t == 32) 5199 t++; 5200 5201 gdata |= (t << 8); 5202 5203 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5204 EEPROM_TXPOWER_BYRATE, 5205 (i * 2) + 1); 5206 5207 t = eeprom & 0x3f; 5208 if (t == 32) 5209 t++; 5210 5211 gdata |= (t << 16); 5212 5213 t = (eeprom & 0x3f00) >> 8; 5214 if (t == 32) 5215 t++; 5216 5217 gdata |= (t << 24); 5218 data |= (eeprom << 16); 5219 5220 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 5221 /* HT20 */ 5222 if (data != 0xffffffff) 5223 rt2800_register_write(rt2x00dev, 5224 TX_PWR_CFG_0 + (i * 4), 5225 data); 5226 } else { 5227 /* HT40 */ 5228 if (gdata != 0xffffffff) 5229 rt2800_register_write(rt2x00dev, 5230 TX_PWR_CFG_0 + (i * 4), 5231 gdata); 5232 } 5233 } 5234 5235 /* Aparently Ralink ran out of space in the BYRATE calibration section 5236 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 5237 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 5238 * power-offsets more space would be needed. Ralink decided to keep the 5239 * EEPROM layout untouched and rather have some shared values covering 5240 * multiple bitrates. 5241 * Populate the registers not covered by the EEPROM in the same way the 5242 * vendor driver does. 5243 */ 5244 5245 /* For OFDM 54MBS use value from OFDM 48MBS */ 5246 pwreg = 0; 5247 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 5248 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 5249 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 5250 5251 /* For MCS 7 use value from MCS 6 */ 5252 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 5253 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 5254 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 5255 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 5256 5257 /* For MCS 15 use value from MCS 14 */ 5258 pwreg = 0; 5259 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 5260 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 5261 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 5262 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 5263 5264 /* For STBC MCS 7 use value from STBC MCS 6 */ 5265 pwreg = 0; 5266 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 5267 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 5268 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 5269 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 5270 5271 rt2800_config_alc_rt6352(rt2x00dev, chan, power_level); 5272 5273 /* TODO: temperature compensation code! */ 5274 } 5275 5276 /* 5277 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 5278 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 5279 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 5280 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 5281 * Reference per rate transmit power values are located in the EEPROM at 5282 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 5283 * current conditions (i.e. band, bandwidth, temperature, user settings). 5284 */ 5285 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 5286 struct ieee80211_channel *chan, 5287 int power_level) 5288 { 5289 u8 txpower, r1; 5290 u16 eeprom; 5291 u32 reg, offset; 5292 int i, is_rate_b, delta, power_ctrl; 5293 enum nl80211_band band = chan->band; 5294 5295 /* 5296 * Calculate HT40 compensation. For 40MHz we need to add or subtract 5297 * value read from EEPROM (different for 2GHz and for 5GHz). 5298 */ 5299 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5300 5301 /* 5302 * Calculate temperature compensation. Depends on measurement of current 5303 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 5304 * to temperature or maybe other factors) is smaller or bigger than 5305 * expected. We adjust it, based on TSSI reference and boundaries values 5306 * provided in EEPROM. 5307 */ 5308 switch (rt2x00dev->chip.rt) { 5309 case RT2860: 5310 case RT2872: 5311 case RT2883: 5312 case RT3070: 5313 case RT3071: 5314 case RT3090: 5315 case RT3572: 5316 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 5317 break; 5318 default: 5319 /* TODO: temperature compensation code for other chips. */ 5320 break; 5321 } 5322 5323 /* 5324 * Decrease power according to user settings, on devices with unknown 5325 * maximum tx power. For other devices we take user power_level into 5326 * consideration on rt2800_compensate_txpower(). 5327 */ 5328 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 5329 chan->max_power); 5330 5331 /* 5332 * BBP_R1 controls TX power for all rates, it allow to set the following 5333 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 5334 * 5335 * TODO: we do not use +6 dBm option to do not increase power beyond 5336 * regulatory limit, however this could be utilized for devices with 5337 * CAPABILITY_POWER_LIMIT. 5338 */ 5339 if (delta <= -12) { 5340 power_ctrl = 2; 5341 delta += 12; 5342 } else if (delta <= -6) { 5343 power_ctrl = 1; 5344 delta += 6; 5345 } else { 5346 power_ctrl = 0; 5347 } 5348 r1 = rt2800_bbp_read(rt2x00dev, 1); 5349 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 5350 rt2800_bbp_write(rt2x00dev, 1, r1); 5351 5352 offset = TX_PWR_CFG_0; 5353 5354 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 5355 /* just to be safe */ 5356 if (offset > TX_PWR_CFG_4) 5357 break; 5358 5359 reg = rt2800_register_read(rt2x00dev, offset); 5360 5361 /* read the next four txpower values */ 5362 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5363 EEPROM_TXPOWER_BYRATE, 5364 i); 5365 5366 is_rate_b = i ? 0 : 1; 5367 /* 5368 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 5369 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 5370 * TX_PWR_CFG_4: unknown 5371 */ 5372 txpower = rt2x00_get_field16(eeprom, 5373 EEPROM_TXPOWER_BYRATE_RATE0); 5374 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5375 power_level, txpower, delta); 5376 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 5377 5378 /* 5379 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 5380 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 5381 * TX_PWR_CFG_4: unknown 5382 */ 5383 txpower = rt2x00_get_field16(eeprom, 5384 EEPROM_TXPOWER_BYRATE_RATE1); 5385 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5386 power_level, txpower, delta); 5387 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 5388 5389 /* 5390 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 5391 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 5392 * TX_PWR_CFG_4: unknown 5393 */ 5394 txpower = rt2x00_get_field16(eeprom, 5395 EEPROM_TXPOWER_BYRATE_RATE2); 5396 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5397 power_level, txpower, delta); 5398 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 5399 5400 /* 5401 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 5402 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 5403 * TX_PWR_CFG_4: unknown 5404 */ 5405 txpower = rt2x00_get_field16(eeprom, 5406 EEPROM_TXPOWER_BYRATE_RATE3); 5407 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5408 power_level, txpower, delta); 5409 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 5410 5411 /* read the next four txpower values */ 5412 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5413 EEPROM_TXPOWER_BYRATE, 5414 i + 1); 5415 5416 is_rate_b = 0; 5417 /* 5418 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 5419 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 5420 * TX_PWR_CFG_4: unknown 5421 */ 5422 txpower = rt2x00_get_field16(eeprom, 5423 EEPROM_TXPOWER_BYRATE_RATE0); 5424 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5425 power_level, txpower, delta); 5426 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 5427 5428 /* 5429 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 5430 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 5431 * TX_PWR_CFG_4: unknown 5432 */ 5433 txpower = rt2x00_get_field16(eeprom, 5434 EEPROM_TXPOWER_BYRATE_RATE1); 5435 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5436 power_level, txpower, delta); 5437 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 5438 5439 /* 5440 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 5441 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 5442 * TX_PWR_CFG_4: unknown 5443 */ 5444 txpower = rt2x00_get_field16(eeprom, 5445 EEPROM_TXPOWER_BYRATE_RATE2); 5446 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5447 power_level, txpower, delta); 5448 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 5449 5450 /* 5451 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 5452 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 5453 * TX_PWR_CFG_4: unknown 5454 */ 5455 txpower = rt2x00_get_field16(eeprom, 5456 EEPROM_TXPOWER_BYRATE_RATE3); 5457 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5458 power_level, txpower, delta); 5459 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 5460 5461 rt2800_register_write(rt2x00dev, offset, reg); 5462 5463 /* next TX_PWR_CFG register */ 5464 offset += 4; 5465 } 5466 } 5467 5468 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5469 struct ieee80211_channel *chan, 5470 int power_level) 5471 { 5472 if (rt2x00_rt(rt2x00dev, RT3593) || 5473 rt2x00_rt(rt2x00dev, RT3883)) 5474 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5475 else if (rt2x00_rt(rt2x00dev, RT6352)) 5476 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5477 else 5478 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5479 } 5480 5481 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5482 { 5483 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5484 rt2x00dev->tx_power); 5485 } 5486 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5487 5488 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5489 { 5490 u32 tx_pin; 5491 u8 rfcsr; 5492 unsigned long min_sleep = 0; 5493 5494 /* 5495 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5496 * designed to be controlled in oscillation frequency by a voltage 5497 * input. Maybe the temperature will affect the frequency of 5498 * oscillation to be shifted. The VCO calibration will be called 5499 * periodically to adjust the frequency to be precision. 5500 */ 5501 5502 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5503 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5504 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5505 5506 switch (rt2x00dev->chip.rf) { 5507 case RF2020: 5508 case RF3020: 5509 case RF3021: 5510 case RF3022: 5511 case RF3320: 5512 case RF3052: 5513 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5514 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5515 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5516 break; 5517 case RF3053: 5518 case RF3070: 5519 case RF3290: 5520 case RF3853: 5521 case RF5350: 5522 case RF5360: 5523 case RF5362: 5524 case RF5370: 5525 case RF5372: 5526 case RF5390: 5527 case RF5392: 5528 case RF5592: 5529 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5530 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5531 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5532 min_sleep = 1000; 5533 break; 5534 case RF7620: 5535 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5536 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5537 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5538 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5539 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5540 min_sleep = 2000; 5541 break; 5542 default: 5543 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5544 rt2x00dev->chip.rf); 5545 return; 5546 } 5547 5548 if (min_sleep > 0) 5549 usleep_range(min_sleep, min_sleep * 2); 5550 5551 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5552 if (rt2x00dev->rf_channel <= 14) { 5553 switch (rt2x00dev->default_ant.tx_chain_num) { 5554 case 3: 5555 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5556 fallthrough; 5557 case 2: 5558 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5559 fallthrough; 5560 case 1: 5561 default: 5562 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5563 break; 5564 } 5565 } else { 5566 switch (rt2x00dev->default_ant.tx_chain_num) { 5567 case 3: 5568 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5569 fallthrough; 5570 case 2: 5571 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5572 fallthrough; 5573 case 1: 5574 default: 5575 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5576 break; 5577 } 5578 } 5579 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5580 } 5581 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5582 5583 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5584 struct rt2x00lib_conf *libconf) 5585 { 5586 u32 reg; 5587 5588 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5589 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5590 libconf->conf->short_frame_max_tx_count); 5591 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5592 libconf->conf->long_frame_max_tx_count); 5593 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5594 } 5595 5596 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5597 struct rt2x00lib_conf *libconf) 5598 { 5599 enum dev_state state = 5600 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5601 STATE_SLEEP : STATE_AWAKE; 5602 u32 reg; 5603 5604 if (state == STATE_SLEEP) { 5605 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5606 5607 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5608 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5609 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5610 libconf->conf->listen_interval - 1); 5611 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5612 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5613 5614 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5615 } else { 5616 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5617 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5618 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5619 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5620 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5621 5622 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5623 } 5624 } 5625 5626 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5627 struct rt2x00lib_conf *libconf, 5628 const unsigned int flags) 5629 { 5630 /* Always recalculate LNA gain before changing configuration */ 5631 rt2800_config_lna_gain(rt2x00dev, libconf); 5632 5633 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5634 /* 5635 * To provide correct survey data for survey-based ACS algorithm 5636 * we have to save survey data for current channel before switching. 5637 */ 5638 rt2800_update_survey(rt2x00dev); 5639 5640 rt2800_config_channel(rt2x00dev, libconf->conf, 5641 &libconf->rf, &libconf->channel); 5642 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5643 libconf->conf->power_level); 5644 } 5645 if (flags & IEEE80211_CONF_CHANGE_POWER) 5646 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5647 libconf->conf->power_level); 5648 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5649 rt2800_config_retry_limit(rt2x00dev, libconf); 5650 if (flags & IEEE80211_CONF_CHANGE_PS) 5651 rt2800_config_ps(rt2x00dev, libconf); 5652 } 5653 EXPORT_SYMBOL_GPL(rt2800_config); 5654 5655 /* 5656 * Link tuning 5657 */ 5658 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5659 { 5660 u32 reg; 5661 5662 /* 5663 * Update FCS error count from register. 5664 */ 5665 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5666 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5667 } 5668 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5669 5670 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5671 { 5672 u8 vgc; 5673 5674 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5675 if (rt2x00_rt(rt2x00dev, RT3070) || 5676 rt2x00_rt(rt2x00dev, RT3071) || 5677 rt2x00_rt(rt2x00dev, RT3090) || 5678 rt2x00_rt(rt2x00dev, RT3290) || 5679 rt2x00_rt(rt2x00dev, RT3390) || 5680 rt2x00_rt(rt2x00dev, RT3572) || 5681 rt2x00_rt(rt2x00dev, RT3593) || 5682 rt2x00_rt(rt2x00dev, RT5390) || 5683 rt2x00_rt(rt2x00dev, RT5392) || 5684 rt2x00_rt(rt2x00dev, RT5592) || 5685 rt2x00_rt(rt2x00dev, RT6352)) 5686 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5687 else 5688 vgc = 0x2e + rt2x00dev->lna_gain; 5689 } else { /* 5GHZ band */ 5690 if (rt2x00_rt(rt2x00dev, RT3593) || 5691 rt2x00_rt(rt2x00dev, RT3883)) 5692 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5693 else if (rt2x00_rt(rt2x00dev, RT5592)) 5694 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5695 else { 5696 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5697 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5698 else 5699 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5700 } 5701 } 5702 5703 return vgc; 5704 } 5705 5706 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5707 struct link_qual *qual, u8 vgc_level) 5708 { 5709 if (qual->vgc_level != vgc_level) { 5710 if (rt2x00_rt(rt2x00dev, RT3572) || 5711 rt2x00_rt(rt2x00dev, RT3593) || 5712 rt2x00_rt(rt2x00dev, RT3883) || 5713 rt2x00_rt(rt2x00dev, RT6352)) { 5714 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5715 vgc_level); 5716 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5717 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5718 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5719 } else { 5720 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5721 } 5722 5723 qual->vgc_level = vgc_level; 5724 qual->vgc_level_reg = vgc_level; 5725 } 5726 } 5727 5728 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5729 { 5730 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5731 } 5732 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5733 5734 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5735 const u32 count) 5736 { 5737 u8 vgc; 5738 5739 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5740 return; 5741 5742 /* When RSSI is better than a certain threshold, increase VGC 5743 * with a chip specific value in order to improve the balance 5744 * between sensibility and noise isolation. 5745 */ 5746 5747 vgc = rt2800_get_default_vgc(rt2x00dev); 5748 5749 switch (rt2x00dev->chip.rt) { 5750 case RT3572: 5751 case RT3593: 5752 if (qual->rssi > -65) { 5753 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5754 vgc += 0x20; 5755 else 5756 vgc += 0x10; 5757 } 5758 break; 5759 5760 case RT3883: 5761 if (qual->rssi > -65) 5762 vgc += 0x10; 5763 break; 5764 5765 case RT5592: 5766 if (qual->rssi > -65) 5767 vgc += 0x20; 5768 break; 5769 5770 default: 5771 if (qual->rssi > -80) 5772 vgc += 0x10; 5773 break; 5774 } 5775 5776 rt2800_set_vgc(rt2x00dev, qual, vgc); 5777 } 5778 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5779 5780 /* 5781 * Initialization functions. 5782 */ 5783 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5784 { 5785 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5786 u32 reg; 5787 u16 eeprom; 5788 u8 bbp; 5789 unsigned int i; 5790 int ret; 5791 5792 rt2800_disable_wpdma(rt2x00dev); 5793 5794 ret = rt2800_drv_init_registers(rt2x00dev); 5795 if (ret) 5796 return ret; 5797 5798 if (rt2x00_rt(rt2x00dev, RT6352)) { 5799 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01); 5800 5801 bbp = rt2800_bbp_read(rt2x00dev, 21); 5802 bbp |= 0x01; 5803 rt2800_bbp_write(rt2x00dev, 21, bbp); 5804 bbp = rt2800_bbp_read(rt2x00dev, 21); 5805 bbp &= (~0x01); 5806 rt2800_bbp_write(rt2x00dev, 21, bbp); 5807 5808 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00); 5809 } 5810 5811 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5812 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5813 5814 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5815 5816 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5817 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5818 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5819 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5820 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5821 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5822 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5823 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5824 5825 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5826 5827 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5828 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5829 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5830 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5831 5832 if (rt2x00_rt(rt2x00dev, RT3290)) { 5833 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5834 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5835 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5836 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5837 } 5838 5839 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5840 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5841 rt2x00_set_field32(®, LDO0_EN, 1); 5842 rt2x00_set_field32(®, LDO_BGSEL, 3); 5843 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5844 } 5845 5846 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5847 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5848 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5849 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5850 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5851 5852 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5853 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5854 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5855 5856 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5857 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5858 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5859 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5860 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5861 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5862 5863 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5864 rt2x00_set_field32(®, PLL_CONTROL, 1); 5865 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5866 } 5867 5868 if (rt2x00_rt(rt2x00dev, RT3071) || 5869 rt2x00_rt(rt2x00dev, RT3090) || 5870 rt2x00_rt(rt2x00dev, RT3290) || 5871 rt2x00_rt(rt2x00dev, RT3390)) { 5872 5873 if (rt2x00_rt(rt2x00dev, RT3290)) 5874 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5875 0x00000404); 5876 else 5877 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5878 0x00000400); 5879 5880 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5881 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5882 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5883 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5884 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5885 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5886 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5887 0x0000002c); 5888 else 5889 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5890 0x0000000f); 5891 } else { 5892 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5893 } 5894 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5895 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5896 5897 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5898 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5899 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5900 } else { 5901 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5902 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5903 } 5904 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5905 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5906 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5907 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5908 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5909 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5910 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5911 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5912 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5913 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5914 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5915 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5916 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5917 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5918 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5919 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5920 if (rt2x00_get_field16(eeprom, 5921 EEPROM_NIC_CONF1_DAC_TEST)) 5922 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5923 0x0000001f); 5924 else 5925 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5926 0x0000000f); 5927 } else { 5928 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5929 0x00000000); 5930 } 5931 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5932 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5933 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5934 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); 5935 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); 5936 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); 5937 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5938 rt2x00_rt(rt2x00dev, RT5392)) { 5939 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5940 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5941 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5942 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5943 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5944 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5945 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5946 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5947 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5948 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5949 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5950 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001); 5951 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5952 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 5953 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5954 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5955 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5956 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5957 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5958 0x3630363A); 5959 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5960 0x3630363A); 5961 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5962 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5963 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5964 5965 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433); 5966 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543); 5967 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544); 5968 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544); 5969 5970 rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010); 5971 5972 } else { 5973 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5974 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5975 } 5976 5977 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5978 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5979 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5980 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5981 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5982 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5983 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5984 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5985 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5986 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5987 5988 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5989 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5990 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5991 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5992 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5993 5994 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5995 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5996 if (rt2x00_is_usb(rt2x00dev)) { 5997 drv_data->max_psdu = 3; 5998 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5999 rt2x00_rt(rt2x00dev, RT2883) || 6000 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 6001 drv_data->max_psdu = 2; 6002 } else { 6003 drv_data->max_psdu = 1; 6004 } 6005 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 6006 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 6007 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 6008 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 6009 6010 reg = rt2800_register_read(rt2x00dev, LED_CFG); 6011 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 6012 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 6013 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 6014 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 6015 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 6016 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 6017 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 6018 rt2800_register_write(rt2x00dev, LED_CFG, reg); 6019 6020 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 6021 6022 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 6023 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 6024 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 6025 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 6026 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 6027 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 6028 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 6029 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 6030 6031 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 6032 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 6033 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 6034 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 6035 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 6036 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 6037 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 6038 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 6039 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 6040 6041 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 6042 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 6043 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 6044 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 6045 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6046 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6047 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6048 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6049 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6050 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6051 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 6052 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 6053 6054 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 6055 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 6056 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 6057 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 6058 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6059 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6060 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6061 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6062 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6063 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6064 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 6065 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 6066 6067 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 6068 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 6069 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 6070 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6071 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6072 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6073 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6074 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6075 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6076 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6077 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 6078 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 6079 6080 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 6081 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 6082 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 6083 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6084 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6085 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6086 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6087 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6088 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6089 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6090 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 6091 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 6092 6093 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 6094 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 6095 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 6096 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6097 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6098 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6099 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6100 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6101 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6102 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6103 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 6104 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 6105 6106 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 6107 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 6108 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 6109 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6110 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6111 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6112 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6113 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6114 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6115 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6116 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 6117 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 6118 6119 if (rt2x00_is_usb(rt2x00dev)) { 6120 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 6121 6122 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 6123 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 6124 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 6125 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 6126 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 6127 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 6128 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 6129 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 6130 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 6131 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 6132 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6133 } 6134 6135 /* 6136 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 6137 * although it is reserved. 6138 */ 6139 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 6140 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 6141 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 6142 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 6143 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 6144 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 6145 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 6146 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 6147 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 6148 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 6149 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 6150 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 6151 6152 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 6153 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 6154 6155 if (rt2x00_rt(rt2x00dev, RT3883)) { 6156 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); 6157 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); 6158 } 6159 6160 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 6161 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 6162 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 6163 IEEE80211_MAX_RTS_THRESHOLD); 6164 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 6165 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 6166 6167 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 6168 6169 /* 6170 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 6171 * time should be set to 16. However, the original Ralink driver uses 6172 * 16 for both and indeed using a value of 10 for CCK SIFS results in 6173 * connection problems with 11g + CTS protection. Hence, use the same 6174 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 6175 */ 6176 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 6177 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 6178 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 6179 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 6180 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 6181 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 6182 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 6183 6184 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 6185 6186 /* 6187 * ASIC will keep garbage value after boot, clear encryption keys. 6188 */ 6189 for (i = 0; i < 4; i++) 6190 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0); 6191 6192 for (i = 0; i < 256; i++) { 6193 rt2800_config_wcid(rt2x00dev, NULL, i); 6194 rt2800_delete_wcid_attr(rt2x00dev, i); 6195 } 6196 6197 /* 6198 * Clear encryption initialization vectors on start, but keep them 6199 * for watchdog reset. Otherwise we will have wrong IVs and not be 6200 * able to keep connections after reset. 6201 */ 6202 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 6203 for (i = 0; i < 256; i++) 6204 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 6205 6206 /* 6207 * Clear all beacons 6208 */ 6209 for (i = 0; i < 8; i++) 6210 rt2800_clear_beacon_register(rt2x00dev, i); 6211 6212 if (rt2x00_is_usb(rt2x00dev)) { 6213 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6214 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 6215 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6216 } else if (rt2x00_is_pcie(rt2x00dev)) { 6217 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6218 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 6219 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6220 } else if (rt2x00_is_soc(rt2x00dev)) { 6221 struct clk *clk = clk_get_sys("bus", NULL); 6222 int rate; 6223 6224 if (IS_ERR(clk)) { 6225 clk = clk_get_sys("cpu", NULL); 6226 6227 if (IS_ERR(clk)) { 6228 rate = 125; 6229 } else { 6230 rate = clk_get_rate(clk) / 3000000; 6231 clk_put(clk); 6232 } 6233 } else { 6234 rate = clk_get_rate(clk) / 1000000; 6235 clk_put(clk); 6236 } 6237 6238 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6239 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate); 6240 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6241 } 6242 6243 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 6244 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 6245 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 6246 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 6247 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 6248 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 6249 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 6250 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 6251 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 6252 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 6253 6254 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 6255 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 6256 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 6257 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 6258 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 6259 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 6260 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 6261 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 6262 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 6263 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 6264 6265 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 6266 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 6267 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 6268 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 6269 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 6270 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 6271 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 6272 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 6273 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 6274 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 6275 6276 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 6277 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 6278 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 6279 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 6280 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 6281 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 6282 6283 /* 6284 * Do not force the BA window size, we use the TXWI to set it 6285 */ 6286 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 6287 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 6288 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 6289 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 6290 6291 /* 6292 * We must clear the error counters. 6293 * These registers are cleared on read, 6294 * so we may pass a useless variable to store the value. 6295 */ 6296 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 6297 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 6298 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 6299 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 6300 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 6301 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 6302 6303 /* 6304 * Setup leadtime for pre tbtt interrupt to 6ms 6305 */ 6306 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 6307 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 6308 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 6309 6310 /* 6311 * Set up channel statistics timer 6312 */ 6313 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 6314 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 6315 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 6316 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 6317 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 6318 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 6319 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 6320 6321 return 0; 6322 } 6323 6324 6325 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 6326 { 6327 u8 value; 6328 6329 value = rt2800_bbp_read(rt2x00dev, 4); 6330 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 6331 rt2800_bbp_write(rt2x00dev, 4, value); 6332 } 6333 6334 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 6335 { 6336 rt2800_bbp_write(rt2x00dev, 142, 1); 6337 rt2800_bbp_write(rt2x00dev, 143, 57); 6338 } 6339 6340 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 6341 { 6342 static const u8 glrt_table[] = { 6343 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 6344 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 6345 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 6346 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 6347 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 6348 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 6349 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 6350 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 6351 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 6352 }; 6353 int i; 6354 6355 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 6356 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 6357 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 6358 } 6359 }; 6360 6361 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 6362 { 6363 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6364 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6365 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 6366 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6367 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6368 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6369 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6370 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6371 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 6372 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6373 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6374 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6375 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6376 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6377 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6378 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6379 } 6380 6381 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 6382 { 6383 u16 eeprom; 6384 u8 value; 6385 6386 value = rt2800_bbp_read(rt2x00dev, 138); 6387 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6388 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6389 value |= 0x20; 6390 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6391 value &= ~0x02; 6392 rt2800_bbp_write(rt2x00dev, 138, value); 6393 } 6394 6395 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 6396 { 6397 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6398 6399 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6400 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6401 6402 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6403 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6404 6405 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6406 6407 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6408 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6409 6410 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6411 6412 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6413 6414 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6415 6416 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6417 6418 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6419 6420 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6421 6422 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6423 6424 rt2800_bbp_write(rt2x00dev, 105, 0x01); 6425 6426 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6427 } 6428 6429 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 6430 { 6431 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6432 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6433 6434 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 6435 rt2800_bbp_write(rt2x00dev, 69, 0x16); 6436 rt2800_bbp_write(rt2x00dev, 73, 0x12); 6437 } else { 6438 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6439 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6440 } 6441 6442 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6443 6444 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6445 6446 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6447 6448 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6449 6450 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 6451 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6452 else 6453 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6454 6455 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6456 6457 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6458 6459 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6460 6461 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6462 6463 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6464 6465 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6466 } 6467 6468 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6469 { 6470 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6471 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6472 6473 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6474 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6475 6476 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6477 6478 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6479 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6480 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6481 6482 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6483 6484 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6485 6486 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6487 6488 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6489 6490 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6491 6492 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6493 6494 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6495 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6496 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6497 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6498 else 6499 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6500 6501 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6502 6503 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6504 6505 if (rt2x00_rt(rt2x00dev, RT3071) || 6506 rt2x00_rt(rt2x00dev, RT3090)) 6507 rt2800_disable_unused_dac_adc(rt2x00dev); 6508 } 6509 6510 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6511 { 6512 u8 value; 6513 6514 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6515 6516 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6517 6518 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6519 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6520 6521 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6522 6523 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6524 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6525 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6526 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6527 6528 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6529 6530 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6531 6532 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6533 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6534 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6535 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6536 6537 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6538 6539 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6540 6541 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6542 6543 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6544 6545 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6546 6547 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6548 6549 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6550 6551 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6552 6553 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6554 6555 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6556 6557 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6558 6559 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6560 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6561 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6562 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6563 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6564 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6565 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6566 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6567 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6568 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6569 6570 value = rt2800_bbp_read(rt2x00dev, 47); 6571 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6572 rt2800_bbp_write(rt2x00dev, 47, value); 6573 6574 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6575 value = rt2800_bbp_read(rt2x00dev, 3); 6576 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6577 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6578 rt2800_bbp_write(rt2x00dev, 3, value); 6579 } 6580 6581 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6582 { 6583 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6584 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6585 6586 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6587 6588 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6589 6590 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6591 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6592 6593 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6594 6595 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6596 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6597 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6598 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6599 6600 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6601 6602 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6603 6604 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6605 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6606 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6607 6608 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6609 6610 if (rt2x00_rt(rt2x00dev, RT5350)) { 6611 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6612 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6613 } else { 6614 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6615 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6616 } 6617 6618 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6619 6620 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6621 6622 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6623 6624 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6625 6626 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6627 6628 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6629 6630 if (rt2x00_rt(rt2x00dev, RT5350)) { 6631 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6632 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6633 } else { 6634 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6635 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6636 } 6637 6638 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6639 6640 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6641 6642 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6643 /* Set ITxBF timeout to 0x9c40=1000msec */ 6644 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6645 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6646 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6647 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6648 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6649 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6650 /* Reprogram the inband interface to put right values in RXWI */ 6651 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6652 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6653 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6654 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6655 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6656 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6657 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6658 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6659 6660 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6661 6662 if (rt2x00_rt(rt2x00dev, RT5350)) { 6663 /* Antenna Software OFDM */ 6664 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6665 /* Antenna Software CCK */ 6666 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6667 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6668 /* Clear previously selected antenna */ 6669 rt2800_bbp_write(rt2x00dev, 154, 0); 6670 } 6671 } 6672 6673 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6674 { 6675 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6676 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6677 6678 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6679 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6680 6681 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6682 6683 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6684 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6685 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6686 6687 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6688 6689 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6690 6691 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6692 6693 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6694 6695 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6696 6697 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6698 6699 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6700 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6701 else 6702 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6703 6704 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6705 6706 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6707 6708 rt2800_disable_unused_dac_adc(rt2x00dev); 6709 } 6710 6711 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6712 { 6713 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6714 6715 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6716 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6717 6718 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6719 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6720 6721 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6722 6723 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6724 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6725 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6726 6727 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6728 6729 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6730 6731 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6732 6733 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6734 6735 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6736 6737 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6738 6739 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6740 6741 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6742 6743 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6744 6745 rt2800_disable_unused_dac_adc(rt2x00dev); 6746 } 6747 6748 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6749 { 6750 rt2800_init_bbp_early(rt2x00dev); 6751 6752 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6753 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6754 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6755 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6756 6757 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6758 6759 /* Enable DC filter */ 6760 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6761 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6762 } 6763 6764 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev) 6765 { 6766 rt2800_init_bbp_early(rt2x00dev); 6767 6768 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6769 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6770 6771 rt2800_bbp_write(rt2x00dev, 86, 0x46); 6772 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6773 6774 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6775 6776 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6777 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6778 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6779 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6780 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6781 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6782 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6783 6784 /* Set ITxBF timeout to 0x9C40=1000msec */ 6785 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6786 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6787 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6788 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6789 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6790 6791 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6792 6793 /* Reprogram the inband interface to put right values in RXWI */ 6794 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6795 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6796 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6797 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6798 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6799 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6800 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6801 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6802 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6803 } 6804 6805 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6806 { 6807 int ant, div_mode; 6808 u16 eeprom; 6809 u8 value; 6810 6811 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6812 6813 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6814 6815 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6816 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6817 6818 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6819 6820 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6821 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6822 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6823 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6824 6825 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6826 6827 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6828 6829 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6830 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6831 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6832 6833 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6834 6835 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6836 6837 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6838 6839 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6840 6841 if (rt2x00_rt(rt2x00dev, RT5392)) 6842 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6843 6844 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6845 6846 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6847 6848 if (rt2x00_rt(rt2x00dev, RT5392)) { 6849 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6850 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6851 } 6852 6853 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6854 6855 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6856 6857 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6858 6859 if (rt2x00_rt(rt2x00dev, RT5390)) 6860 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6861 else if (rt2x00_rt(rt2x00dev, RT5392)) 6862 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6863 else 6864 WARN_ON(1); 6865 6866 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6867 6868 if (rt2x00_rt(rt2x00dev, RT5392)) { 6869 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6870 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6871 } 6872 6873 rt2800_disable_unused_dac_adc(rt2x00dev); 6874 6875 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6876 div_mode = rt2x00_get_field16(eeprom, 6877 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6878 ant = (div_mode == 3) ? 1 : 0; 6879 6880 /* check if this is a Bluetooth combo card */ 6881 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6882 u32 reg; 6883 6884 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6885 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6886 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6887 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6888 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6889 if (ant == 0) 6890 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6891 else if (ant == 1) 6892 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6893 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6894 } 6895 6896 /* These chips have hardware RX antenna diversity */ 6897 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6898 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6899 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6900 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6901 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6902 } 6903 6904 value = rt2800_bbp_read(rt2x00dev, 152); 6905 if (ant == 0) 6906 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6907 else 6908 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6909 rt2800_bbp_write(rt2x00dev, 152, value); 6910 6911 rt2800_init_freq_calibration(rt2x00dev); 6912 } 6913 6914 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6915 { 6916 int ant, div_mode; 6917 u16 eeprom; 6918 u8 value; 6919 6920 rt2800_init_bbp_early(rt2x00dev); 6921 6922 value = rt2800_bbp_read(rt2x00dev, 105); 6923 rt2x00_set_field8(&value, BBP105_MLD, 6924 rt2x00dev->default_ant.rx_chain_num == 2); 6925 rt2800_bbp_write(rt2x00dev, 105, value); 6926 6927 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6928 6929 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6930 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6931 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6932 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6933 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6934 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6935 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6936 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6937 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6938 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6939 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6940 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6941 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6942 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6943 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6944 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6945 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6946 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6947 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6948 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6949 /* FIXME BBP105 owerwrite */ 6950 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6951 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6952 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6953 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6954 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6955 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6956 6957 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6958 rt2800_init_bbp_5592_glrt(rt2x00dev); 6959 6960 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6961 6962 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6963 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6964 ant = (div_mode == 3) ? 1 : 0; 6965 value = rt2800_bbp_read(rt2x00dev, 152); 6966 if (ant == 0) { 6967 /* Main antenna */ 6968 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6969 } else { 6970 /* Auxiliary antenna */ 6971 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6972 } 6973 rt2800_bbp_write(rt2x00dev, 152, value); 6974 6975 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6976 value = rt2800_bbp_read(rt2x00dev, 254); 6977 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6978 rt2800_bbp_write(rt2x00dev, 254, value); 6979 } 6980 6981 rt2800_init_freq_calibration(rt2x00dev); 6982 6983 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6984 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6985 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6986 } 6987 6988 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6989 { 6990 u8 bbp; 6991 6992 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6993 bbp = rt2800_bbp_read(rt2x00dev, 105); 6994 rt2x00_set_field8(&bbp, BBP105_MLD, 6995 rt2x00dev->default_ant.rx_chain_num == 2); 6996 rt2800_bbp_write(rt2x00dev, 105, bbp); 6997 6998 /* Avoid data loss and CRC errors */ 6999 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7000 7001 /* Fix I/Q swap issue */ 7002 bbp = rt2800_bbp_read(rt2x00dev, 1); 7003 bbp |= 0x04; 7004 rt2800_bbp_write(rt2x00dev, 1, bbp); 7005 7006 /* BBP for G band */ 7007 rt2800_bbp_write(rt2x00dev, 3, 0x08); 7008 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 7009 rt2800_bbp_write(rt2x00dev, 6, 0x08); 7010 rt2800_bbp_write(rt2x00dev, 14, 0x09); 7011 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 7012 rt2800_bbp_write(rt2x00dev, 16, 0x01); 7013 rt2800_bbp_write(rt2x00dev, 20, 0x06); 7014 rt2800_bbp_write(rt2x00dev, 21, 0x00); 7015 rt2800_bbp_write(rt2x00dev, 22, 0x00); 7016 rt2800_bbp_write(rt2x00dev, 27, 0x00); 7017 rt2800_bbp_write(rt2x00dev, 28, 0x00); 7018 rt2800_bbp_write(rt2x00dev, 30, 0x00); 7019 rt2800_bbp_write(rt2x00dev, 31, 0x48); 7020 rt2800_bbp_write(rt2x00dev, 47, 0x40); 7021 rt2800_bbp_write(rt2x00dev, 62, 0x00); 7022 rt2800_bbp_write(rt2x00dev, 63, 0x00); 7023 rt2800_bbp_write(rt2x00dev, 64, 0x00); 7024 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 7025 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 7026 rt2800_bbp_write(rt2x00dev, 67, 0x20); 7027 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 7028 rt2800_bbp_write(rt2x00dev, 69, 0x10); 7029 rt2800_bbp_write(rt2x00dev, 70, 0x05); 7030 rt2800_bbp_write(rt2x00dev, 73, 0x18); 7031 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 7032 rt2800_bbp_write(rt2x00dev, 75, 0x60); 7033 rt2800_bbp_write(rt2x00dev, 76, 0x44); 7034 rt2800_bbp_write(rt2x00dev, 77, 0x59); 7035 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 7036 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 7037 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 7038 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 7039 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 7040 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 7041 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 7042 rt2800_bbp_write(rt2x00dev, 86, 0x38); 7043 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7044 rt2800_bbp_write(rt2x00dev, 91, 0x04); 7045 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7046 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 7047 rt2800_bbp_write(rt2x00dev, 96, 0x00); 7048 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 7049 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7050 /* FIXME BBP105 owerwrite */ 7051 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 7052 rt2800_bbp_write(rt2x00dev, 106, 0x12); 7053 rt2800_bbp_write(rt2x00dev, 109, 0x00); 7054 rt2800_bbp_write(rt2x00dev, 134, 0x10); 7055 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 7056 rt2800_bbp_write(rt2x00dev, 137, 0x04); 7057 rt2800_bbp_write(rt2x00dev, 142, 0x30); 7058 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 7059 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 7060 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 7061 rt2800_bbp_write(rt2x00dev, 162, 0x77); 7062 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 7063 rt2800_bbp_write(rt2x00dev, 164, 0x00); 7064 rt2800_bbp_write(rt2x00dev, 165, 0x00); 7065 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7066 rt2800_bbp_write(rt2x00dev, 187, 0x00); 7067 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7068 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7069 rt2800_bbp_write(rt2x00dev, 187, 0x01); 7070 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7071 rt2800_bbp_write(rt2x00dev, 189, 0x00); 7072 7073 rt2800_bbp_write(rt2x00dev, 91, 0x06); 7074 rt2800_bbp_write(rt2x00dev, 92, 0x04); 7075 rt2800_bbp_write(rt2x00dev, 93, 0x54); 7076 rt2800_bbp_write(rt2x00dev, 99, 0x50); 7077 rt2800_bbp_write(rt2x00dev, 148, 0x84); 7078 rt2800_bbp_write(rt2x00dev, 167, 0x80); 7079 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 7080 rt2800_bbp_write(rt2x00dev, 106, 0x13); 7081 7082 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 7083 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 7084 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 7085 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 7086 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 7087 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 7088 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 7089 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 7090 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 7091 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 7092 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 7093 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 7094 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 7095 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 7096 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 7097 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 7098 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 7099 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 7100 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 7101 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 7102 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 7103 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 7104 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 7105 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 7106 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 7107 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 7108 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 7109 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 7110 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 7111 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 7112 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 7113 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 7114 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 7115 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 7116 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 7117 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 7118 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 7119 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 7120 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 7121 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 7122 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 7123 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 7124 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 7125 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 7126 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 7127 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 7128 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 7129 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 7130 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 7131 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 7132 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 7133 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 7134 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 7135 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 7136 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 7137 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 7138 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 7139 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 7140 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 7141 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 7142 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 7143 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 7144 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 7145 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 7146 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 7147 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 7148 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 7149 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 7150 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 7151 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 7152 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 7153 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 7154 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 7155 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 7156 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 7157 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 7158 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 7159 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 7160 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 7161 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 7162 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 7163 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 7164 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 7165 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 7166 7167 /* BBP for G band DCOC function */ 7168 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 7169 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 7170 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 7171 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 7172 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 7173 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 7174 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 7175 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 7176 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 7177 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 7178 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 7179 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 7180 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 7181 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 7182 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 7183 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 7184 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 7185 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 7186 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 7187 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7188 7189 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7190 7191 rt2800_bbp_write(rt2x00dev, 84, 0x19); 7192 } 7193 7194 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 7195 { 7196 unsigned int i; 7197 u16 eeprom; 7198 u8 reg_id; 7199 u8 value; 7200 7201 if (rt2800_is_305x_soc(rt2x00dev)) 7202 rt2800_init_bbp_305x_soc(rt2x00dev); 7203 7204 switch (rt2x00dev->chip.rt) { 7205 case RT2860: 7206 case RT2872: 7207 case RT2883: 7208 rt2800_init_bbp_28xx(rt2x00dev); 7209 break; 7210 case RT3070: 7211 case RT3071: 7212 case RT3090: 7213 rt2800_init_bbp_30xx(rt2x00dev); 7214 break; 7215 case RT3290: 7216 rt2800_init_bbp_3290(rt2x00dev); 7217 break; 7218 case RT3352: 7219 case RT5350: 7220 rt2800_init_bbp_3352(rt2x00dev); 7221 break; 7222 case RT3390: 7223 rt2800_init_bbp_3390(rt2x00dev); 7224 break; 7225 case RT3572: 7226 rt2800_init_bbp_3572(rt2x00dev); 7227 break; 7228 case RT3593: 7229 rt2800_init_bbp_3593(rt2x00dev); 7230 return; 7231 case RT3883: 7232 rt2800_init_bbp_3883(rt2x00dev); 7233 return; 7234 case RT5390: 7235 case RT5392: 7236 rt2800_init_bbp_53xx(rt2x00dev); 7237 break; 7238 case RT5592: 7239 rt2800_init_bbp_5592(rt2x00dev); 7240 return; 7241 case RT6352: 7242 rt2800_init_bbp_6352(rt2x00dev); 7243 break; 7244 } 7245 7246 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 7247 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 7248 EEPROM_BBP_START, i); 7249 7250 if (eeprom != 0xffff && eeprom != 0x0000) { 7251 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 7252 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 7253 rt2800_bbp_write(rt2x00dev, reg_id, value); 7254 } 7255 } 7256 } 7257 7258 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 7259 { 7260 u32 reg; 7261 7262 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 7263 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 7264 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 7265 } 7266 7267 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 7268 u8 filter_target) 7269 { 7270 unsigned int i; 7271 u8 bbp; 7272 u8 rfcsr; 7273 u8 passband; 7274 u8 stopband; 7275 u8 overtuned = 0; 7276 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 7277 7278 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7279 7280 bbp = rt2800_bbp_read(rt2x00dev, 4); 7281 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 7282 rt2800_bbp_write(rt2x00dev, 4, bbp); 7283 7284 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 7285 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 7286 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 7287 7288 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7289 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 7290 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7291 7292 /* 7293 * Set power & frequency of passband test tone 7294 */ 7295 rt2800_bbp_write(rt2x00dev, 24, 0); 7296 7297 for (i = 0; i < 100; i++) { 7298 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7299 msleep(1); 7300 7301 passband = rt2800_bbp_read(rt2x00dev, 55); 7302 if (passband) 7303 break; 7304 } 7305 7306 /* 7307 * Set power & frequency of stopband test tone 7308 */ 7309 rt2800_bbp_write(rt2x00dev, 24, 0x06); 7310 7311 for (i = 0; i < 100; i++) { 7312 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7313 msleep(1); 7314 7315 stopband = rt2800_bbp_read(rt2x00dev, 55); 7316 7317 if ((passband - stopband) <= filter_target) { 7318 rfcsr24++; 7319 overtuned += ((passband - stopband) == filter_target); 7320 } else 7321 break; 7322 7323 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7324 } 7325 7326 rfcsr24 -= !!overtuned; 7327 7328 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7329 return rfcsr24; 7330 } 7331 7332 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 7333 const unsigned int rf_reg) 7334 { 7335 u8 rfcsr; 7336 7337 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 7338 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 7339 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7340 msleep(1); 7341 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 7342 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7343 } 7344 7345 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 7346 { 7347 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7348 u8 filter_tgt_bw20; 7349 u8 filter_tgt_bw40; 7350 u8 rfcsr, bbp; 7351 7352 /* 7353 * TODO: sync filter_tgt values with vendor driver 7354 */ 7355 if (rt2x00_rt(rt2x00dev, RT3070)) { 7356 filter_tgt_bw20 = 0x16; 7357 filter_tgt_bw40 = 0x19; 7358 } else { 7359 filter_tgt_bw20 = 0x13; 7360 filter_tgt_bw40 = 0x15; 7361 } 7362 7363 drv_data->calibration_bw20 = 7364 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 7365 drv_data->calibration_bw40 = 7366 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 7367 7368 /* 7369 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 7370 */ 7371 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7372 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7373 7374 /* 7375 * Set back to initial state 7376 */ 7377 rt2800_bbp_write(rt2x00dev, 24, 0); 7378 7379 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7380 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 7381 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7382 7383 /* 7384 * Set BBP back to BW20 7385 */ 7386 bbp = rt2800_bbp_read(rt2x00dev, 4); 7387 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 7388 rt2800_bbp_write(rt2x00dev, 4, bbp); 7389 } 7390 7391 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 7392 { 7393 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7394 u8 min_gain, rfcsr, bbp; 7395 u16 eeprom; 7396 7397 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 7398 7399 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 7400 if (rt2x00_rt(rt2x00dev, RT3070) || 7401 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7402 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 7403 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 7404 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 7405 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 7406 } 7407 7408 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 7409 if (drv_data->txmixer_gain_24g >= min_gain) { 7410 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 7411 drv_data->txmixer_gain_24g); 7412 } 7413 7414 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 7415 7416 if (rt2x00_rt(rt2x00dev, RT3090)) { 7417 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7418 bbp = rt2800_bbp_read(rt2x00dev, 138); 7419 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7420 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7421 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 7422 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7423 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 7424 rt2800_bbp_write(rt2x00dev, 138, bbp); 7425 } 7426 7427 if (rt2x00_rt(rt2x00dev, RT3070)) { 7428 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 7429 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 7430 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 7431 else 7432 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 7433 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 7434 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 7435 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 7436 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 7437 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7438 rt2x00_rt(rt2x00dev, RT3090) || 7439 rt2x00_rt(rt2x00dev, RT3390)) { 7440 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7441 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7442 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 7443 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 7444 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 7445 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 7446 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7447 7448 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 7449 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 7450 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 7451 7452 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 7453 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 7454 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 7455 7456 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 7457 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 7458 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 7459 } 7460 } 7461 7462 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 7463 { 7464 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7465 u8 rfcsr; 7466 u8 tx_gain; 7467 7468 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 7469 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 7470 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7471 7472 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 7473 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 7474 RFCSR17_TXMIXER_GAIN); 7475 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 7476 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 7477 7478 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 7479 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 7480 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 7481 7482 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 7483 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 7484 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 7485 7486 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7487 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7488 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7489 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7490 7491 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7492 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7493 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7494 7495 /* TODO: enable stream mode */ 7496 } 7497 7498 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7499 { 7500 u8 reg; 7501 u16 eeprom; 7502 7503 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7504 reg = rt2800_bbp_read(rt2x00dev, 138); 7505 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7506 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7507 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7508 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7509 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7510 rt2800_bbp_write(rt2x00dev, 138, reg); 7511 7512 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7513 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7514 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7515 7516 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7517 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7518 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7519 7520 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7521 7522 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7523 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7524 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7525 } 7526 7527 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7528 { 7529 rt2800_rf_init_calibration(rt2x00dev, 30); 7530 7531 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7532 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7533 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7534 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7535 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7536 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7537 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7538 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7539 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7540 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7541 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7542 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7543 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7544 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7545 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7546 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7547 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7548 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7549 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7550 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7551 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7552 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7553 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7554 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7555 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7556 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7557 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7558 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7559 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7560 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7561 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7562 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7563 } 7564 7565 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7566 { 7567 u8 rfcsr; 7568 u16 eeprom; 7569 u32 reg; 7570 7571 /* XXX vendor driver do this only for 3070 */ 7572 rt2800_rf_init_calibration(rt2x00dev, 30); 7573 7574 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7575 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7576 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7577 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7578 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7579 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7580 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7581 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7582 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7583 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7584 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7585 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7586 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7587 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7588 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7589 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7590 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7591 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7592 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7593 7594 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7595 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7596 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7597 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7598 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7599 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7600 rt2x00_rt(rt2x00dev, RT3090)) { 7601 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7602 7603 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7604 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7605 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7606 7607 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7608 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7609 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7610 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7611 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7612 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7613 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7614 else 7615 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7616 } 7617 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7618 7619 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7620 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7621 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7622 } 7623 7624 rt2800_rx_filter_calibration(rt2x00dev); 7625 7626 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7627 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7628 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7629 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7630 7631 rt2800_led_open_drain_enable(rt2x00dev); 7632 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7633 } 7634 7635 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7636 { 7637 u8 rfcsr; 7638 7639 rt2800_rf_init_calibration(rt2x00dev, 2); 7640 7641 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7642 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7643 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7644 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7645 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7646 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7647 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7648 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7649 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7650 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7651 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7652 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7653 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7654 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7655 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7656 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7657 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7658 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7659 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7660 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7661 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7662 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7663 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7664 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7665 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7666 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7667 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7668 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7669 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7670 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7671 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7672 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7673 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7674 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7675 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7676 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7677 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7678 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7679 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7680 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7681 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7682 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7683 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7684 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7685 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7686 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7687 7688 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7689 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7690 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7691 7692 rt2800_led_open_drain_enable(rt2x00dev); 7693 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7694 } 7695 7696 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7697 { 7698 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7699 &rt2x00dev->cap_flags); 7700 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7701 &rt2x00dev->cap_flags); 7702 u8 rfcsr; 7703 7704 rt2800_rf_init_calibration(rt2x00dev, 30); 7705 7706 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7707 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7708 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7709 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7710 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7711 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7712 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7713 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7714 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7715 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7716 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7717 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7718 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7719 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7720 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7721 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7722 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7723 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7724 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7725 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7726 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7727 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7728 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7729 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7730 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7731 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7732 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7733 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7734 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7735 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7736 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7737 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7738 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7739 rfcsr = 0x01; 7740 if (tx0_ext_pa) 7741 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7742 if (tx1_ext_pa) 7743 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7744 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7745 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7746 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7747 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7748 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7749 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7750 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7751 rfcsr = 0x52; 7752 if (!tx0_ext_pa) { 7753 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7754 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7755 } 7756 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7757 rfcsr = 0x52; 7758 if (!tx1_ext_pa) { 7759 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7760 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7761 } 7762 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7763 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7764 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7765 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7766 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7767 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7768 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7769 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7770 rfcsr = 0x2d; 7771 if (tx0_ext_pa) 7772 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7773 if (tx1_ext_pa) 7774 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7775 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7776 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7777 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7778 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7779 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7780 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7781 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7782 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7783 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7784 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7785 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7786 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7787 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7788 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7789 7790 rt2800_rx_filter_calibration(rt2x00dev); 7791 rt2800_led_open_drain_enable(rt2x00dev); 7792 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7793 } 7794 7795 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7796 { 7797 u32 reg; 7798 7799 rt2800_rf_init_calibration(rt2x00dev, 30); 7800 7801 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7802 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7803 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7804 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7805 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7806 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7807 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7808 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7809 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7810 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7811 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7812 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7813 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7814 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7815 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7816 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7817 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7818 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7819 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7820 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7821 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7822 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7823 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7824 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7825 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7826 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7827 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7828 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7829 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7830 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7831 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7832 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7833 7834 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7835 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7836 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7837 7838 rt2800_rx_filter_calibration(rt2x00dev); 7839 7840 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7841 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7842 7843 rt2800_led_open_drain_enable(rt2x00dev); 7844 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7845 } 7846 7847 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7848 { 7849 u8 rfcsr; 7850 u32 reg; 7851 7852 rt2800_rf_init_calibration(rt2x00dev, 30); 7853 7854 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7855 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7856 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7857 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7858 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7859 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7860 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7861 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7862 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7863 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7864 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7865 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7866 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7867 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7868 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7869 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7870 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7871 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7872 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7873 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7874 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7875 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7876 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7877 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7878 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7879 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7880 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7881 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7882 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7883 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7884 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7885 7886 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7887 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7888 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7889 7890 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7891 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7892 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7893 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7894 msleep(1); 7895 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7896 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7897 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7898 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7899 7900 rt2800_rx_filter_calibration(rt2x00dev); 7901 rt2800_led_open_drain_enable(rt2x00dev); 7902 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7903 } 7904 7905 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7906 { 7907 u8 bbp; 7908 bool txbf_enabled = false; /* FIXME */ 7909 7910 bbp = rt2800_bbp_read(rt2x00dev, 105); 7911 if (rt2x00dev->default_ant.rx_chain_num == 1) 7912 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7913 else 7914 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7915 rt2800_bbp_write(rt2x00dev, 105, bbp); 7916 7917 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7918 7919 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7920 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7921 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7922 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7923 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7924 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7925 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7926 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7927 7928 if (txbf_enabled) 7929 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7930 else 7931 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7932 7933 /* SNR mapping */ 7934 rt2800_bbp_write(rt2x00dev, 142, 6); 7935 rt2800_bbp_write(rt2x00dev, 143, 160); 7936 rt2800_bbp_write(rt2x00dev, 142, 7); 7937 rt2800_bbp_write(rt2x00dev, 143, 161); 7938 rt2800_bbp_write(rt2x00dev, 142, 8); 7939 rt2800_bbp_write(rt2x00dev, 143, 162); 7940 7941 /* ADC/DAC control */ 7942 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7943 7944 /* RX AGC energy lower bound in log2 */ 7945 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7946 7947 /* FIXME: BBP 105 owerwrite? */ 7948 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7949 7950 } 7951 7952 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7953 { 7954 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7955 u32 reg; 7956 u8 rfcsr; 7957 7958 /* Disable GPIO #4 and #7 function for LAN PE control */ 7959 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7960 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7961 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7962 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7963 7964 /* Initialize default register values */ 7965 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7966 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7967 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7968 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7969 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7970 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7971 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7972 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7973 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7974 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7975 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7976 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7977 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7978 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7979 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7980 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7981 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7982 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7983 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7984 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7985 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7986 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7987 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7988 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7989 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7990 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7991 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7992 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7993 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7994 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7995 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7996 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7997 7998 /* Initiate calibration */ 7999 /* TODO: use rt2800_rf_init_calibration ? */ 8000 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8001 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8002 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8003 8004 rt2800_freq_cal_mode1(rt2x00dev); 8005 8006 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 8007 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 8008 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 8009 8010 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 8011 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 8012 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 8013 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8014 usleep_range(1000, 1500); 8015 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 8016 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 8017 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8018 8019 /* Set initial values for RX filter calibration */ 8020 drv_data->calibration_bw20 = 0x1f; 8021 drv_data->calibration_bw40 = 0x2f; 8022 8023 /* Save BBP 25 & 26 values for later use in channel switching */ 8024 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 8025 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 8026 8027 rt2800_led_open_drain_enable(rt2x00dev); 8028 rt2800_normal_mode_setup_3593(rt2x00dev); 8029 8030 rt3593_post_bbp_init(rt2x00dev); 8031 8032 /* TODO: enable stream mode support */ 8033 } 8034 8035 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 8036 { 8037 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 8038 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 8039 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8040 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8041 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 8042 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8043 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8044 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8045 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 8046 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 8047 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8048 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8049 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8050 if (rt2800_clk_is_20mhz(rt2x00dev)) 8051 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 8052 else 8053 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8054 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8055 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8056 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 8057 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8058 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8059 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8060 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8061 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8062 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8063 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8064 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8065 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8066 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8067 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8068 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 8069 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8070 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8071 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8072 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8073 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8074 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8075 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8076 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8077 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8078 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8079 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8080 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8081 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8082 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8083 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 8084 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 8085 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8086 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8087 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8088 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 8089 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 8090 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 8091 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8092 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8093 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8094 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8095 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 8096 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8097 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8098 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 8099 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8100 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8101 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8102 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8103 } 8104 8105 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev) 8106 { 8107 u8 rfcsr; 8108 8109 /* TODO: get the actual ECO value from the SoC */ 8110 const unsigned int eco = 5; 8111 8112 rt2800_rf_init_calibration(rt2x00dev, 2); 8113 8114 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0); 8115 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8116 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8117 rt2800_rfcsr_write(rt2x00dev, 3, 0x20); 8118 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 8119 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8120 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8121 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8122 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b); 8123 rt2800_rfcsr_write(rt2x00dev, 9, 0x08); 8124 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8125 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 8126 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 8127 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8128 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8129 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8130 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8131 8132 /* RFCSR 17 will be initialized later based on the 8133 * frequency offset stored in the EEPROM 8134 */ 8135 8136 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8137 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8138 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8139 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8140 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8141 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0); 8142 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8143 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8144 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8145 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8146 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8147 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 8148 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8149 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8150 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8151 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8152 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 8153 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8154 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8155 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8156 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8157 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8158 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8159 rt2800_rfcsr_write(rt2x00dev, 41, 0x00); 8160 rt2800_rfcsr_write(rt2x00dev, 42, 0x00); 8161 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8162 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 8163 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8164 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8165 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8166 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 8167 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8168 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8169 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 8170 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 8171 rt2800_rfcsr_write(rt2x00dev, 53, 0x76); 8172 rt2800_rfcsr_write(rt2x00dev, 54, 0x76); 8173 rt2800_rfcsr_write(rt2x00dev, 55, 0x76); 8174 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8175 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 8176 rt2800_rfcsr_write(rt2x00dev, 58, 0x00); 8177 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 8178 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 8179 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 8180 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8181 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8182 8183 /* TODO: rx filter calibration? */ 8184 8185 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 8186 8187 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 8188 8189 rt2800_bbp_write(rt2x00dev, 105, 0x05); 8190 8191 rt2800_bbp_write(rt2x00dev, 179, 0x02); 8192 rt2800_bbp_write(rt2x00dev, 180, 0x00); 8193 rt2800_bbp_write(rt2x00dev, 182, 0x40); 8194 rt2800_bbp_write(rt2x00dev, 180, 0x01); 8195 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 8196 8197 rt2800_bbp_write(rt2x00dev, 179, 0x00); 8198 8199 rt2800_bbp_write(rt2x00dev, 142, 0x04); 8200 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 8201 rt2800_bbp_write(rt2x00dev, 142, 0x06); 8202 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 8203 rt2800_bbp_write(rt2x00dev, 142, 0x07); 8204 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 8205 rt2800_bbp_write(rt2x00dev, 142, 0x08); 8206 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 8207 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 8208 8209 if (eco == 5) { 8210 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 8211 rt2800_rfcsr_write(rt2x00dev, 33, 0x32); 8212 } 8213 8214 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8215 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0); 8216 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8217 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8218 msleep(1); 8219 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 8220 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8221 8222 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 8223 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 8224 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 8225 8226 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 8227 rfcsr |= 0xc0; 8228 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 8229 8230 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 8231 rfcsr |= 0x20; 8232 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 8233 8234 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46); 8235 rfcsr |= 0x20; 8236 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr); 8237 8238 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 8239 rfcsr &= ~0xee; 8240 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 8241 } 8242 8243 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 8244 { 8245 rt2800_rf_init_calibration(rt2x00dev, 2); 8246 8247 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 8248 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8249 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8250 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8251 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8252 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8253 else 8254 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 8255 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8256 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8257 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8258 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8259 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8260 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8261 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8262 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8263 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8264 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8265 8266 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8267 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8268 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8269 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8270 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8271 if (rt2x00_is_usb(rt2x00dev) && 8272 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8273 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8274 else 8275 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 8276 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8277 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8278 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8279 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8280 8281 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8282 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8283 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8284 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8285 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8286 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8287 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8288 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8289 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8290 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8291 8292 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8293 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8294 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 8295 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 8296 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8297 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8298 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8299 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8300 else 8301 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 8302 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8303 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8304 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8305 8306 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8307 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8308 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8309 else 8310 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 8311 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 8312 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 8313 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8314 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 8315 else 8316 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 8317 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 8318 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 8319 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 8320 8321 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8322 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 8323 if (rt2x00_is_usb(rt2x00dev)) 8324 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8325 else 8326 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 8327 } else { 8328 if (rt2x00_is_usb(rt2x00dev)) 8329 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 8330 else 8331 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 8332 } 8333 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8334 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8335 8336 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8337 8338 rt2800_led_open_drain_enable(rt2x00dev); 8339 } 8340 8341 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 8342 { 8343 rt2800_rf_init_calibration(rt2x00dev, 2); 8344 8345 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 8346 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8347 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8348 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8349 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8350 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8351 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8352 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8353 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8354 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8355 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8356 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8357 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8358 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 8359 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8360 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 8361 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8362 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 8363 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 8364 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8365 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8366 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8367 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8368 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8369 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8370 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8371 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 8372 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8373 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8374 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8375 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8376 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8377 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 8378 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8379 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 8380 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8381 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8382 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8383 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8384 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8385 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8386 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 8387 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8388 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8389 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 8390 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 8391 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 8392 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 8393 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8394 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8395 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 8396 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8397 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8398 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 8399 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8400 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 8401 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 8402 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8403 8404 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8405 8406 rt2800_led_open_drain_enable(rt2x00dev); 8407 } 8408 8409 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 8410 { 8411 rt2800_rf_init_calibration(rt2x00dev, 30); 8412 8413 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 8414 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8415 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8416 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 8417 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8418 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8419 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8420 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8421 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8422 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 8423 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 8424 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 8425 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8426 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8427 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8428 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8429 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8430 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8431 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 8432 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 8433 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8434 8435 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8436 msleep(1); 8437 8438 rt2800_freq_cal_mode1(rt2x00dev); 8439 8440 /* Enable DC filter */ 8441 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 8442 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 8443 8444 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8445 8446 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 8447 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8448 8449 rt2800_led_open_drain_enable(rt2x00dev); 8450 } 8451 8452 static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev) 8453 { 8454 u8 rfb5r1_org, rfb7r1_org, rfvalue; 8455 u32 mac0518, mac051c, mac0528, mac052c; 8456 u8 i; 8457 8458 mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8459 mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8460 mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 8461 mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 8462 8463 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8464 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8465 8466 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC); 8467 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306); 8468 rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330); 8469 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff); 8470 rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8471 rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8472 8473 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4); 8474 for (i = 0; i < 100; ++i) { 8475 usleep_range(50, 100); 8476 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8477 if ((rfvalue & 0x04) != 0x4) 8478 break; 8479 } 8480 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org); 8481 8482 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4); 8483 for (i = 0; i < 100; ++i) { 8484 usleep_range(50, 100); 8485 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8486 if ((rfvalue & 0x04) != 0x4) 8487 break; 8488 } 8489 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org); 8490 8491 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8492 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8493 rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518); 8494 rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c); 8495 rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528); 8496 rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c); 8497 } 8498 8499 static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2) 8500 { 8501 int calcode = ((d2 - d1) * 1000) / 43; 8502 8503 if ((calcode % 10) >= 5) 8504 calcode += 10; 8505 calcode = (calcode / 10); 8506 8507 return calcode; 8508 } 8509 8510 static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) 8511 { 8512 u32 savemacsysctrl; 8513 u8 saverfb0r1, saverfb0r34, saverfb0r35; 8514 u8 saverfb5r4, saverfb5r17, saverfb5r18; 8515 u8 saverfb5r19, saverfb5r20; 8516 u8 savebbpr22, savebbpr47, savebbpr49; 8517 u8 bytevalue = 0; 8518 int rcalcode; 8519 u8 r_cal_code = 0; 8520 s8 d1 = 0, d2 = 0; 8521 u8 rfvalue; 8522 u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG; 8523 u32 maccfg; 8524 8525 saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8526 saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34); 8527 saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 8528 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8529 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8530 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8531 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8532 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8533 8534 savebbpr22 = rt2800_bbp_read(rt2x00dev, 22); 8535 savebbpr47 = rt2800_bbp_read(rt2x00dev, 47); 8536 savebbpr49 = rt2800_bbp_read(rt2x00dev, 49); 8537 8538 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8539 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8540 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8541 MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG); 8542 8543 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8544 maccfg &= (~0x04); 8545 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8546 8547 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8548 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n"); 8549 8550 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8551 maccfg &= (~0x08); 8552 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8553 8554 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 8555 rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n"); 8556 8557 rfvalue = (MAC_RF_BYPASS0 | 0x3004); 8558 rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue); 8559 rfvalue = (MAC_RF_CONTROL0 | (~0x3002)); 8560 rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue); 8561 8562 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27); 8563 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 8564 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83); 8565 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00); 8566 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 8567 8568 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00); 8569 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13); 8570 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 8571 8572 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1); 8573 8574 rt2800_bbp_write(rt2x00dev, 47, 0x04); 8575 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8576 usleep_range(100, 200); 8577 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8578 if (bytevalue > 128) 8579 d1 = bytevalue - 256; 8580 else 8581 d1 = (s8)bytevalue; 8582 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8583 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01); 8584 8585 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8586 usleep_range(100, 200); 8587 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8588 if (bytevalue > 128) 8589 d2 = bytevalue - 256; 8590 else 8591 d2 = (s8)bytevalue; 8592 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8593 8594 rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2); 8595 if (rcalcode < 0) 8596 r_cal_code = 256 + rcalcode; 8597 else 8598 r_cal_code = (u8)rcalcode; 8599 8600 rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code); 8601 8602 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8603 8604 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8605 bytevalue |= 0x1; 8606 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8607 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8608 bytevalue &= (~0x1); 8609 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8610 8611 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1); 8612 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34); 8613 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35); 8614 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8615 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8616 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8617 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8618 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8619 8620 rt2800_bbp_write(rt2x00dev, 22, savebbpr22); 8621 rt2800_bbp_write(rt2x00dev, 47, savebbpr47); 8622 rt2800_bbp_write(rt2x00dev, 49, savebbpr49); 8623 8624 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8625 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8626 8627 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 8628 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG); 8629 } 8630 8631 static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev) 8632 { 8633 u8 bbpreg = 0; 8634 u32 macvalue = 0; 8635 u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue; 8636 int i; 8637 8638 saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8639 rfvalue = saverfb0r2; 8640 rfvalue |= 0x03; 8641 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue); 8642 8643 rt2800_bbp_write(rt2x00dev, 158, 141); 8644 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8645 bbpreg |= 0x10; 8646 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8647 8648 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8649 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8); 8650 8651 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8652 rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n"); 8653 8654 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8655 saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8656 saverfb5r4 = saverfb5r4 & (~0x40); 8657 saverfb7r4 = saverfb7r4 & (~0x40); 8658 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64); 8659 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8660 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4); 8661 8662 rt2800_bbp_write(rt2x00dev, 158, 141); 8663 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8664 bbpreg = bbpreg & (~0x40); 8665 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8666 bbpreg |= 0x48; 8667 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8668 8669 for (i = 0; i < 10000; i++) { 8670 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8671 if ((bbpreg & 0x40) == 0) 8672 break; 8673 usleep_range(50, 100); 8674 } 8675 8676 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8677 bbpreg = bbpreg & (~0x40); 8678 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8679 8680 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 8681 8682 rt2800_bbp_write(rt2x00dev, 158, 141); 8683 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8684 bbpreg &= (~0x10); 8685 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8686 8687 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2); 8688 } 8689 8690 static u32 rt2800_do_sqrt_accumulation(u32 si) 8691 { 8692 u32 root, root_pre, bit; 8693 s8 i; 8694 8695 bit = 1 << 15; 8696 root = 0; 8697 for (i = 15; i >= 0; i = i - 1) { 8698 root_pre = root + bit; 8699 if ((root_pre * root_pre) <= si) 8700 root = root_pre; 8701 bit = bit >> 1; 8702 } 8703 8704 return root; 8705 } 8706 8707 static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev) 8708 { 8709 u8 rfb0r1, rfb0r2, rfb0r42; 8710 u8 rfb4r0, rfb4r19; 8711 u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20; 8712 u8 rfb6r0, rfb6r19; 8713 u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20; 8714 8715 u8 bbp1, bbp4; 8716 u8 bbpr241, bbpr242; 8717 u32 i; 8718 u8 ch_idx; 8719 u8 bbpval; 8720 u8 rfval, vga_idx = 0; 8721 int mi = 0, mq = 0, si = 0, sq = 0, riq = 0; 8722 int sigma_i, sigma_q, r_iq, g_rx; 8723 int g_imb; 8724 int ph_rx; 8725 u32 savemacsysctrl = 0; 8726 u32 orig_RF_CONTROL0 = 0; 8727 u32 orig_RF_BYPASS0 = 0; 8728 u32 orig_RF_CONTROL1 = 0; 8729 u32 orig_RF_BYPASS1 = 0; 8730 u32 orig_RF_CONTROL3 = 0; 8731 u32 orig_RF_BYPASS3 = 0; 8732 u32 bbpval1 = 0; 8733 static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f}; 8734 8735 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8736 orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8737 orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8738 orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1); 8739 orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1); 8740 orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 8741 orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 8742 8743 bbp1 = rt2800_bbp_read(rt2x00dev, 1); 8744 bbp4 = rt2800_bbp_read(rt2x00dev, 4); 8745 8746 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0); 8747 8748 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 8749 rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n"); 8750 8751 bbpval = bbp4 & (~0x18); 8752 bbpval = bbp4 | 0x00; 8753 rt2800_bbp_write(rt2x00dev, 4, bbpval); 8754 8755 bbpval = rt2800_bbp_read(rt2x00dev, 21); 8756 bbpval = bbpval | 1; 8757 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8758 bbpval = bbpval & 0xfe; 8759 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8760 8761 rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202); 8762 rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303); 8763 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 8764 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101); 8765 else 8766 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000); 8767 8768 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1); 8769 8770 rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8771 rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8772 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 8773 rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 8774 rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19); 8775 rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8776 rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8777 rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8778 rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8779 rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8780 rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8781 8782 rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 8783 rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19); 8784 rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 8785 rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8786 rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 8787 rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 8788 rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 8789 rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 8790 8791 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87); 8792 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27); 8793 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38); 8794 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38); 8795 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80); 8796 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1); 8797 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60); 8798 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8799 8800 rt2800_bbp_write(rt2x00dev, 23, 0x0); 8801 rt2800_bbp_write(rt2x00dev, 24, 0x0); 8802 8803 rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0); 8804 8805 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 8806 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 8807 8808 rt2800_bbp_write(rt2x00dev, 241, 0x10); 8809 rt2800_bbp_write(rt2x00dev, 242, 0x84); 8810 rt2800_bbp_write(rt2x00dev, 244, 0x31); 8811 8812 bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3); 8813 bbpval = bbpval & (~0x7); 8814 rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval); 8815 8816 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 8817 udelay(1); 8818 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 8819 usleep_range(1, 200); 8820 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376); 8821 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8822 udelay(1); 8823 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 8824 rt2800_bbp_write(rt2x00dev, 23, 0x06); 8825 rt2800_bbp_write(rt2x00dev, 24, 0x06); 8826 } else { 8827 rt2800_bbp_write(rt2x00dev, 23, 0x02); 8828 rt2800_bbp_write(rt2x00dev, 24, 0x02); 8829 } 8830 8831 for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) { 8832 if (ch_idx == 0) { 8833 rfval = rfb0r1 & (~0x3); 8834 rfval = rfb0r1 | 0x1; 8835 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8836 rfval = rfb0r2 & (~0x33); 8837 rfval = rfb0r2 | 0x11; 8838 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8839 rfval = rfb0r42 & (~0x50); 8840 rfval = rfb0r42 | 0x10; 8841 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8842 8843 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8844 udelay(1); 8845 8846 bbpval = bbp1 & (~0x18); 8847 bbpval = bbpval | 0x00; 8848 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8849 8850 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00); 8851 } else { 8852 rfval = rfb0r1 & (~0x3); 8853 rfval = rfb0r1 | 0x2; 8854 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8855 rfval = rfb0r2 & (~0x33); 8856 rfval = rfb0r2 | 0x22; 8857 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8858 rfval = rfb0r42 & (~0x50); 8859 rfval = rfb0r42 | 0x40; 8860 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8861 8862 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006); 8863 udelay(1); 8864 8865 bbpval = bbp1 & (~0x18); 8866 bbpval = bbpval | 0x08; 8867 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8868 8869 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01); 8870 } 8871 usleep_range(500, 1500); 8872 8873 vga_idx = 0; 8874 while (vga_idx < 11) { 8875 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]); 8876 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]); 8877 8878 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93); 8879 8880 for (i = 0; i < 10000; i++) { 8881 bbpval = rt2800_bbp_read(rt2x00dev, 159); 8882 if ((bbpval & 0xff) == 0x93) 8883 usleep_range(50, 100); 8884 else 8885 break; 8886 } 8887 8888 if ((bbpval & 0xff) == 0x93) { 8889 rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish"); 8890 goto restore_value; 8891 } 8892 for (i = 0; i < 5; i++) { 8893 u32 bbptemp = 0; 8894 u8 value = 0; 8895 int result = 0; 8896 8897 rt2800_bbp_write(rt2x00dev, 158, 0x1e); 8898 rt2800_bbp_write(rt2x00dev, 159, i); 8899 rt2800_bbp_write(rt2x00dev, 158, 0x22); 8900 value = rt2800_bbp_read(rt2x00dev, 159); 8901 bbptemp = bbptemp + (value << 24); 8902 rt2800_bbp_write(rt2x00dev, 158, 0x21); 8903 value = rt2800_bbp_read(rt2x00dev, 159); 8904 bbptemp = bbptemp + (value << 16); 8905 rt2800_bbp_write(rt2x00dev, 158, 0x20); 8906 value = rt2800_bbp_read(rt2x00dev, 159); 8907 bbptemp = bbptemp + (value << 8); 8908 rt2800_bbp_write(rt2x00dev, 158, 0x1f); 8909 value = rt2800_bbp_read(rt2x00dev, 159); 8910 bbptemp = bbptemp + value; 8911 8912 if (i < 2 && (bbptemp & 0x800000)) 8913 result = (bbptemp & 0xffffff) - 0x1000000; 8914 else 8915 result = bbptemp; 8916 8917 if (i == 0) 8918 mi = result / 4096; 8919 else if (i == 1) 8920 mq = result / 4096; 8921 else if (i == 2) 8922 si = bbptemp / 4096; 8923 else if (i == 3) 8924 sq = bbptemp / 4096; 8925 else 8926 riq = result / 4096; 8927 } 8928 8929 bbpval1 = si - mi * mi; 8930 rt2x00_dbg(rt2x00dev, 8931 "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d", 8932 si, sq, riq, bbpval1, vga_idx); 8933 8934 if (bbpval1 >= (100 * 100)) 8935 break; 8936 8937 if (bbpval1 <= 100) 8938 vga_idx = vga_idx + 9; 8939 else if (bbpval1 <= 158) 8940 vga_idx = vga_idx + 8; 8941 else if (bbpval1 <= 251) 8942 vga_idx = vga_idx + 7; 8943 else if (bbpval1 <= 398) 8944 vga_idx = vga_idx + 6; 8945 else if (bbpval1 <= 630) 8946 vga_idx = vga_idx + 5; 8947 else if (bbpval1 <= 1000) 8948 vga_idx = vga_idx + 4; 8949 else if (bbpval1 <= 1584) 8950 vga_idx = vga_idx + 3; 8951 else if (bbpval1 <= 2511) 8952 vga_idx = vga_idx + 2; 8953 else 8954 vga_idx = vga_idx + 1; 8955 } 8956 8957 sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi)); 8958 sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq)); 8959 r_iq = 10 * (riq - (mi * mq)); 8960 8961 rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq); 8962 8963 if (sigma_i <= 1400 && sigma_i >= 1000 && 8964 (sigma_i - sigma_q) <= 112 && 8965 (sigma_i - sigma_q) >= -112 && 8966 mi <= 32 && mi >= -32 && 8967 mq <= 32 && mq >= -32) { 8968 r_iq = 10 * (riq - (mi * mq)); 8969 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 8970 sigma_i, sigma_q, r_iq); 8971 8972 g_rx = (1000 * sigma_q) / sigma_i; 8973 g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx); 8974 ph_rx = (r_iq * 2292) / (sigma_i * sigma_q); 8975 8976 if (ph_rx > 20 || ph_rx < -20) { 8977 ph_rx = 0; 8978 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 8979 } 8980 8981 if (g_imb > 12 || g_imb < -12) { 8982 g_imb = 0; 8983 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 8984 } 8985 } else { 8986 g_imb = 0; 8987 ph_rx = 0; 8988 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 8989 sigma_i, sigma_q, r_iq); 8990 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 8991 } 8992 8993 if (ch_idx == 0) { 8994 rt2800_bbp_write(rt2x00dev, 158, 0x37); 8995 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 8996 rt2800_bbp_write(rt2x00dev, 158, 0x35); 8997 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 8998 } else { 8999 rt2800_bbp_write(rt2x00dev, 158, 0x55); 9000 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 9001 rt2800_bbp_write(rt2x00dev, 158, 0x53); 9002 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 9003 } 9004 } 9005 9006 restore_value: 9007 rt2800_bbp_write(rt2x00dev, 158, 0x3); 9008 bbpval = rt2800_bbp_read(rt2x00dev, 159); 9009 rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07)); 9010 9011 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9012 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9013 rt2800_bbp_write(rt2x00dev, 1, bbp1); 9014 rt2800_bbp_write(rt2x00dev, 4, bbp4); 9015 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9016 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9017 9018 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9019 bbpval = rt2800_bbp_read(rt2x00dev, 21); 9020 bbpval |= 0x1; 9021 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9022 usleep_range(10, 200); 9023 bbpval &= 0xfe; 9024 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9025 9026 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1); 9027 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2); 9028 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9029 9030 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0); 9031 rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19); 9032 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3); 9033 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4); 9034 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17); 9035 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18); 9036 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19); 9037 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20); 9038 9039 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0); 9040 rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19); 9041 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3); 9042 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4); 9043 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17); 9044 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18); 9045 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19); 9046 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20); 9047 9048 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 9049 udelay(1); 9050 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9051 udelay(1); 9052 rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0); 9053 udelay(1); 9054 rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0); 9055 rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1); 9056 rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1); 9057 rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3); 9058 rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3); 9059 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9060 } 9061 9062 static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, 9063 struct rf_reg_pair rf_reg_record[][13], u8 chain) 9064 { 9065 u8 rfvalue = 0; 9066 9067 if (chain == CHAIN_0) { 9068 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9069 rf_reg_record[CHAIN_0][0].bank = 0; 9070 rf_reg_record[CHAIN_0][0].reg = 1; 9071 rf_reg_record[CHAIN_0][0].value = rfvalue; 9072 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9073 rf_reg_record[CHAIN_0][1].bank = 0; 9074 rf_reg_record[CHAIN_0][1].reg = 2; 9075 rf_reg_record[CHAIN_0][1].value = rfvalue; 9076 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9077 rf_reg_record[CHAIN_0][2].bank = 0; 9078 rf_reg_record[CHAIN_0][2].reg = 35; 9079 rf_reg_record[CHAIN_0][2].value = rfvalue; 9080 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9081 rf_reg_record[CHAIN_0][3].bank = 0; 9082 rf_reg_record[CHAIN_0][3].reg = 42; 9083 rf_reg_record[CHAIN_0][3].value = rfvalue; 9084 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 9085 rf_reg_record[CHAIN_0][4].bank = 4; 9086 rf_reg_record[CHAIN_0][4].reg = 0; 9087 rf_reg_record[CHAIN_0][4].value = rfvalue; 9088 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2); 9089 rf_reg_record[CHAIN_0][5].bank = 4; 9090 rf_reg_record[CHAIN_0][5].reg = 2; 9091 rf_reg_record[CHAIN_0][5].value = rfvalue; 9092 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34); 9093 rf_reg_record[CHAIN_0][6].bank = 4; 9094 rf_reg_record[CHAIN_0][6].reg = 34; 9095 rf_reg_record[CHAIN_0][6].value = rfvalue; 9096 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 9097 rf_reg_record[CHAIN_0][7].bank = 5; 9098 rf_reg_record[CHAIN_0][7].reg = 3; 9099 rf_reg_record[CHAIN_0][7].value = rfvalue; 9100 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 9101 rf_reg_record[CHAIN_0][8].bank = 5; 9102 rf_reg_record[CHAIN_0][8].reg = 4; 9103 rf_reg_record[CHAIN_0][8].value = rfvalue; 9104 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 9105 rf_reg_record[CHAIN_0][9].bank = 5; 9106 rf_reg_record[CHAIN_0][9].reg = 17; 9107 rf_reg_record[CHAIN_0][9].value = rfvalue; 9108 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 9109 rf_reg_record[CHAIN_0][10].bank = 5; 9110 rf_reg_record[CHAIN_0][10].reg = 18; 9111 rf_reg_record[CHAIN_0][10].value = rfvalue; 9112 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 9113 rf_reg_record[CHAIN_0][11].bank = 5; 9114 rf_reg_record[CHAIN_0][11].reg = 19; 9115 rf_reg_record[CHAIN_0][11].value = rfvalue; 9116 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 9117 rf_reg_record[CHAIN_0][12].bank = 5; 9118 rf_reg_record[CHAIN_0][12].reg = 20; 9119 rf_reg_record[CHAIN_0][12].value = rfvalue; 9120 } else if (chain == CHAIN_1) { 9121 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9122 rf_reg_record[CHAIN_1][0].bank = 0; 9123 rf_reg_record[CHAIN_1][0].reg = 1; 9124 rf_reg_record[CHAIN_1][0].value = rfvalue; 9125 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9126 rf_reg_record[CHAIN_1][1].bank = 0; 9127 rf_reg_record[CHAIN_1][1].reg = 2; 9128 rf_reg_record[CHAIN_1][1].value = rfvalue; 9129 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9130 rf_reg_record[CHAIN_1][2].bank = 0; 9131 rf_reg_record[CHAIN_1][2].reg = 35; 9132 rf_reg_record[CHAIN_1][2].value = rfvalue; 9133 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9134 rf_reg_record[CHAIN_1][3].bank = 0; 9135 rf_reg_record[CHAIN_1][3].reg = 42; 9136 rf_reg_record[CHAIN_1][3].value = rfvalue; 9137 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 9138 rf_reg_record[CHAIN_1][4].bank = 6; 9139 rf_reg_record[CHAIN_1][4].reg = 0; 9140 rf_reg_record[CHAIN_1][4].value = rfvalue; 9141 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2); 9142 rf_reg_record[CHAIN_1][5].bank = 6; 9143 rf_reg_record[CHAIN_1][5].reg = 2; 9144 rf_reg_record[CHAIN_1][5].value = rfvalue; 9145 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34); 9146 rf_reg_record[CHAIN_1][6].bank = 6; 9147 rf_reg_record[CHAIN_1][6].reg = 34; 9148 rf_reg_record[CHAIN_1][6].value = rfvalue; 9149 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 9150 rf_reg_record[CHAIN_1][7].bank = 7; 9151 rf_reg_record[CHAIN_1][7].reg = 3; 9152 rf_reg_record[CHAIN_1][7].value = rfvalue; 9153 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 9154 rf_reg_record[CHAIN_1][8].bank = 7; 9155 rf_reg_record[CHAIN_1][8].reg = 4; 9156 rf_reg_record[CHAIN_1][8].value = rfvalue; 9157 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 9158 rf_reg_record[CHAIN_1][9].bank = 7; 9159 rf_reg_record[CHAIN_1][9].reg = 17; 9160 rf_reg_record[CHAIN_1][9].value = rfvalue; 9161 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 9162 rf_reg_record[CHAIN_1][10].bank = 7; 9163 rf_reg_record[CHAIN_1][10].reg = 18; 9164 rf_reg_record[CHAIN_1][10].value = rfvalue; 9165 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 9166 rf_reg_record[CHAIN_1][11].bank = 7; 9167 rf_reg_record[CHAIN_1][11].reg = 19; 9168 rf_reg_record[CHAIN_1][11].value = rfvalue; 9169 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 9170 rf_reg_record[CHAIN_1][12].bank = 7; 9171 rf_reg_record[CHAIN_1][12].reg = 20; 9172 rf_reg_record[CHAIN_1][12].value = rfvalue; 9173 } else { 9174 rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain); 9175 } 9176 } 9177 9178 static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, 9179 struct rf_reg_pair rf_record[][13]) 9180 { 9181 u8 chain_index = 0, record_index = 0; 9182 u8 bank = 0, rf_register = 0, value = 0; 9183 9184 for (chain_index = 0; chain_index < 2; chain_index++) { 9185 for (record_index = 0; record_index < 13; record_index++) { 9186 bank = rf_record[chain_index][record_index].bank; 9187 rf_register = rf_record[chain_index][record_index].reg; 9188 value = rf_record[chain_index][record_index].value; 9189 rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value); 9190 rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", 9191 bank, rf_register, value); 9192 } 9193 } 9194 } 9195 9196 static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev) 9197 { 9198 rt2800_bbp_write(rt2x00dev, 158, 0xAA); 9199 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9200 9201 rt2800_bbp_write(rt2x00dev, 158, 0xAB); 9202 rt2800_bbp_write(rt2x00dev, 159, 0x0A); 9203 9204 rt2800_bbp_write(rt2x00dev, 158, 0xAC); 9205 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9206 9207 rt2800_bbp_write(rt2x00dev, 158, 0xAD); 9208 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9209 9210 rt2800_bbp_write(rt2x00dev, 244, 0x40); 9211 } 9212 9213 static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg) 9214 { 9215 u32 macvalue = 0; 9216 int fftout_i = 0, fftout_q = 0; 9217 u32 ptmp = 0, pint = 0; 9218 u8 bbp = 0; 9219 u8 tidxi; 9220 9221 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9222 rt2800_bbp_write(rt2x00dev, 159, 0x9b); 9223 9224 bbp = 0x9b; 9225 9226 while (bbp == 0x9b) { 9227 usleep_range(10, 50); 9228 bbp = rt2800_bbp_read(rt2x00dev, 159); 9229 bbp = bbp & 0xff; 9230 } 9231 9232 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9233 rt2800_bbp_write(rt2x00dev, 159, tidx); 9234 rt2800_bbp_write(rt2x00dev, 159, tidx); 9235 rt2800_bbp_write(rt2x00dev, 159, tidx); 9236 9237 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9238 9239 fftout_i = (macvalue >> 16); 9240 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9241 fftout_q = (macvalue & 0xffff); 9242 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9243 ptmp = (fftout_i * fftout_i); 9244 ptmp = ptmp + (fftout_q * fftout_q); 9245 pint = ptmp; 9246 rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint); 9247 if (read_neg) { 9248 pint = pint >> 1; 9249 tidxi = 0x40 - tidx; 9250 tidxi = tidxi & 0x3f; 9251 9252 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9253 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9254 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9255 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9256 9257 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9258 9259 fftout_i = (macvalue >> 16); 9260 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9261 fftout_q = (macvalue & 0xffff); 9262 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9263 ptmp = (fftout_i * fftout_i); 9264 ptmp = ptmp + (fftout_q * fftout_q); 9265 ptmp = ptmp >> 1; 9266 pint = pint + ptmp; 9267 } 9268 9269 return pint; 9270 } 9271 9272 static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) 9273 { 9274 u32 macvalue = 0; 9275 int fftout_i = 0, fftout_q = 0; 9276 u32 ptmp = 0, pint = 0; 9277 9278 rt2800_bbp_write(rt2x00dev, 158, 0xBA); 9279 rt2800_bbp_write(rt2x00dev, 159, tidx); 9280 rt2800_bbp_write(rt2x00dev, 159, tidx); 9281 rt2800_bbp_write(rt2x00dev, 159, tidx); 9282 9283 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9284 9285 fftout_i = (macvalue >> 16); 9286 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9287 fftout_q = (macvalue & 0xffff); 9288 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9289 ptmp = (fftout_i * fftout_i); 9290 ptmp = ptmp + (fftout_q * fftout_q); 9291 pint = ptmp; 9292 9293 return pint; 9294 } 9295 9296 static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc) 9297 { 9298 u8 bbp = 0; 9299 9300 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9301 bbp = alc | 0x80; 9302 rt2800_bbp_write(rt2x00dev, 159, bbp); 9303 9304 if (ch_idx == 0) 9305 bbp = (iorq == 0) ? 0xb1 : 0xb2; 9306 else 9307 bbp = (iorq == 0) ? 0xb8 : 0xb9; 9308 9309 rt2800_bbp_write(rt2x00dev, 158, bbp); 9310 bbp = dc; 9311 rt2800_bbp_write(rt2x00dev, 159, bbp); 9312 } 9313 9314 static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, 9315 u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2]) 9316 { 9317 u32 p0 = 0, p1 = 0, pf = 0; 9318 s8 idx0 = 0, idx1 = 0; 9319 u8 idxf[] = {0x00, 0x00}; 9320 u8 ibit = 0x20; 9321 u8 iorq; 9322 s8 bidx; 9323 9324 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9325 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9326 9327 for (bidx = 5; bidx >= 0; bidx--) { 9328 for (iorq = 0; iorq <= 1; iorq++) { 9329 if (idxf[iorq] == 0x20) { 9330 idx0 = 0x20; 9331 p0 = pf; 9332 } else { 9333 idx0 = idxf[iorq] - ibit; 9334 idx0 = idx0 & 0x3F; 9335 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0); 9336 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9337 } 9338 9339 idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit); 9340 idx1 = idx1 & 0x3F; 9341 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1); 9342 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9343 9344 rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", 9345 alc_idx, iorq, idxf[iorq]); 9346 rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n", 9347 p0, p1, pf, idx0, idx1, ibit); 9348 9349 if (bidx != 5 && pf <= p0 && pf < p1) { 9350 idxf[iorq] = idxf[iorq]; 9351 } else if (p0 < p1) { 9352 pf = p0; 9353 idxf[iorq] = idx0 & 0x3F; 9354 } else { 9355 pf = p1; 9356 idxf[iorq] = idx1 & 0x3F; 9357 } 9358 rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", 9359 iorq, iorq, idxf[iorq], pf); 9360 9361 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]); 9362 } 9363 ibit = ibit >> 1; 9364 } 9365 dc_result[ch_idx][alc_idx][0] = idxf[0]; 9366 dc_result[ch_idx][alc_idx][1] = idxf[1]; 9367 } 9368 9369 static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes) 9370 { 9371 u32 p0 = 0, p1 = 0, pf = 0; 9372 s8 perr = 0, gerr = 0, iq_err = 0; 9373 s8 pef = 0, gef = 0; 9374 s8 psta, pend; 9375 s8 gsta, gend; 9376 9377 u8 ibit = 0x20; 9378 u8 first_search = 0x00, touch_neg_max = 0x00; 9379 s8 idx0 = 0, idx1 = 0; 9380 u8 gop; 9381 u8 bbp = 0; 9382 s8 bidx; 9383 9384 for (bidx = 5; bidx >= 1; bidx--) { 9385 for (gop = 0; gop < 2; gop++) { 9386 if (gop == 1 || bidx < 4) { 9387 if (gop == 0) 9388 iq_err = gerr; 9389 else 9390 iq_err = perr; 9391 9392 first_search = (gop == 0) ? (bidx == 3) : (bidx == 5); 9393 touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : 9394 ((iq_err & 0x3F) == 0x20); 9395 9396 if (touch_neg_max) { 9397 p0 = pf; 9398 idx0 = iq_err; 9399 } else { 9400 idx0 = iq_err - ibit; 9401 bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) : 9402 ((gop == 0) ? 0x46 : 0x47); 9403 9404 rt2800_bbp_write(rt2x00dev, 158, bbp); 9405 rt2800_bbp_write(rt2x00dev, 159, idx0); 9406 9407 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9408 } 9409 9410 idx1 = iq_err + (first_search ? 0 : ibit); 9411 idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F); 9412 9413 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9414 (gop == 0) ? 0x46 : 0x47; 9415 9416 rt2800_bbp_write(rt2x00dev, 158, bbp); 9417 rt2800_bbp_write(rt2x00dev, 159, idx1); 9418 9419 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9420 9421 rt2x00_dbg(rt2x00dev, 9422 "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n", 9423 p0, p1, pf, idx0, idx1, iq_err, gop, ibit); 9424 9425 if (!(!first_search && pf <= p0 && pf < p1)) { 9426 if (p0 < p1) { 9427 pf = p0; 9428 iq_err = idx0; 9429 } else { 9430 pf = p1; 9431 iq_err = idx1; 9432 } 9433 } 9434 9435 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9436 (gop == 0) ? 0x46 : 0x47; 9437 9438 rt2800_bbp_write(rt2x00dev, 158, bbp); 9439 rt2800_bbp_write(rt2x00dev, 159, iq_err); 9440 9441 if (gop == 0) 9442 gerr = iq_err; 9443 else 9444 perr = iq_err; 9445 9446 rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", 9447 pf, gerr & 0x0F, perr & 0x3F); 9448 } 9449 } 9450 9451 if (bidx > 0) 9452 ibit = (ibit >> 1); 9453 } 9454 gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F); 9455 perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F); 9456 9457 gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr; 9458 gsta = gerr - 1; 9459 gend = gerr + 2; 9460 9461 perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr; 9462 psta = perr - 1; 9463 pend = perr + 2; 9464 9465 for (gef = gsta; gef <= gend; gef = gef + 1) 9466 for (pef = psta; pef <= pend; pef = pef + 1) { 9467 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9468 rt2800_bbp_write(rt2x00dev, 158, bbp); 9469 rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F); 9470 9471 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9472 rt2800_bbp_write(rt2x00dev, 158, bbp); 9473 rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F); 9474 9475 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9476 if (gef == gsta && pef == psta) { 9477 pf = p1; 9478 gerr = gef; 9479 perr = pef; 9480 } else if (pf > p1) { 9481 pf = p1; 9482 gerr = gef; 9483 perr = pef; 9484 } 9485 rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", 9486 p1, pf, gef & 0x0F, pef & 0x3F); 9487 } 9488 9489 ges[ch_idx] = gerr & 0x0F; 9490 pes[ch_idx] = perr & 0x3F; 9491 } 9492 9493 static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev) 9494 { 9495 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21); 9496 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10); 9497 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9498 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b); 9499 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81); 9500 rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81); 9501 rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee); 9502 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d); 9503 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d); 9504 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 9505 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7); 9506 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2); 9507 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 9508 } 9509 9510 static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev) 9511 { 9512 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22); 9513 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20); 9514 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9515 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b); 9516 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81); 9517 rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81); 9518 rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee); 9519 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d); 9520 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d); 9521 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80); 9522 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7); 9523 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2); 9524 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20); 9525 } 9526 9527 static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev) 9528 { 9529 struct rf_reg_pair rf_store[CHAIN_NUM][13]; 9530 u32 macorg1 = 0; 9531 u32 macorg2 = 0; 9532 u32 macorg3 = 0; 9533 u32 macorg4 = 0; 9534 u32 macorg5 = 0; 9535 u32 orig528 = 0; 9536 u32 orig52c = 0; 9537 9538 u32 savemacsysctrl = 0; 9539 u32 macvalue = 0; 9540 u32 mac13b8 = 0; 9541 u32 p0 = 0, p1 = 0; 9542 u32 p0_idx10 = 0, p1_idx10 = 0; 9543 9544 u8 rfvalue; 9545 u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2]; 9546 u8 ger[CHAIN_NUM], per[CHAIN_NUM]; 9547 9548 u8 vga_gain[] = {14, 14}; 9549 u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0; 9550 u8 bbpr30, rfb0r39, rfb0r42; 9551 u8 bbpr1; 9552 u8 bbpr4; 9553 u8 bbpr241, bbpr242; 9554 u8 count_step; 9555 9556 static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c}; 9557 static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 9558 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F}; 9559 static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08}; 9560 9561 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9562 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9563 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9564 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9565 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9566 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9567 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9568 orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 9569 orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 9570 9571 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9572 macvalue &= (~0x04); 9573 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9574 9575 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9576 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9577 9578 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9579 macvalue &= (~0x08); 9580 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9581 9582 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9583 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9584 9585 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9586 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9587 9588 bbpr30 = rt2800_bbp_read(rt2x00dev, 30); 9589 rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39); 9590 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9591 9592 rt2800_bbp_write(rt2x00dev, 30, 0x1F); 9593 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80); 9594 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B); 9595 9596 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9597 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9598 9599 rt2800_setbbptonegenerator(rt2x00dev); 9600 9601 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9602 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9603 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9604 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00); 9605 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9606 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9607 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9608 rt2800_register_write(rt2x00dev, 0x13b8, 0x10); 9609 udelay(1); 9610 9611 if (ch_idx == 0) 9612 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9613 else 9614 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9615 9616 udelay(1); 9617 9618 if (ch_idx == 0) 9619 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9620 else 9621 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9622 9623 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9624 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9625 9626 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9627 if (ch_idx == 0) 9628 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9629 else 9630 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9631 9632 vga_gain[ch_idx] = 18; 9633 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9634 rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]); 9635 rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]); 9636 9637 macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9638 macvalue &= (~0x0000F1F1); 9639 macvalue |= (rf_gain[rf_alc_idx] << 4); 9640 macvalue |= (rf_gain[rf_alc_idx] << 12); 9641 rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue); 9642 macvalue = (0x0000F1F1); 9643 rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue); 9644 9645 if (rf_alc_idx == 0) { 9646 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21); 9647 for (; vga_gain[ch_idx] > 0; 9648 vga_gain[ch_idx] = vga_gain[ch_idx] - 2) { 9649 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9650 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9651 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9652 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9653 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9654 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9655 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21); 9656 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9657 rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1); 9658 if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000))) 9659 break; 9660 } 9661 9662 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9663 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9664 9665 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9666 rfvga_gain_table[vga_gain[ch_idx]]); 9667 } 9668 9669 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9670 9671 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9672 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9673 9674 rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result); 9675 } 9676 } 9677 9678 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9679 for (idx = 0; idx < 4; idx++) { 9680 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9681 bbp = (idx << 2) + rf_alc_idx; 9682 rt2800_bbp_write(rt2x00dev, 159, bbp); 9683 rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp); 9684 9685 rt2800_bbp_write(rt2x00dev, 158, 0xb1); 9686 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00]; 9687 bbp = bbp & 0x3F; 9688 rt2800_bbp_write(rt2x00dev, 159, bbp); 9689 rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp); 9690 9691 rt2800_bbp_write(rt2x00dev, 158, 0xb2); 9692 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01]; 9693 bbp = bbp & 0x3F; 9694 rt2800_bbp_write(rt2x00dev, 159, bbp); 9695 rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp); 9696 9697 rt2800_bbp_write(rt2x00dev, 158, 0xb8); 9698 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00]; 9699 bbp = bbp & 0x3F; 9700 rt2800_bbp_write(rt2x00dev, 159, bbp); 9701 rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp); 9702 9703 rt2800_bbp_write(rt2x00dev, 158, 0xb9); 9704 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01]; 9705 bbp = bbp & 0x3F; 9706 rt2800_bbp_write(rt2x00dev, 159, bbp); 9707 rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp); 9708 } 9709 } 9710 9711 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9712 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9713 9714 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9715 9716 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9717 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9718 9719 bbp = 0x00; 9720 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9721 9722 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9723 udelay(1); 9724 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9725 9726 rt2800_rf_configrecover(rt2x00dev, rf_store); 9727 9728 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9729 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9730 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9731 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9732 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9733 udelay(1); 9734 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9735 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9736 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9737 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9738 rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528); 9739 rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c); 9740 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9741 9742 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9743 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9744 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9745 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9746 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9747 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9748 9749 bbpr1 = rt2800_bbp_read(rt2x00dev, 1); 9750 bbpr4 = rt2800_bbp_read(rt2x00dev, 4); 9751 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 9752 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 9753 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9754 9755 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9756 macvalue &= (~0x04); 9757 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9758 9759 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9760 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9761 9762 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9763 macvalue &= (~0x08); 9764 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9765 9766 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9767 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9768 9769 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9770 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101); 9771 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9772 } 9773 9774 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9775 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9776 9777 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9778 rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18)); 9779 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9780 udelay(1); 9781 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9782 9783 rt2800_bbp_write(rt2x00dev, 241, 0x14); 9784 rt2800_bbp_write(rt2x00dev, 242, 0x80); 9785 rt2800_bbp_write(rt2x00dev, 244, 0x31); 9786 } else { 9787 rt2800_setbbptonegenerator(rt2x00dev); 9788 } 9789 9790 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9791 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9792 udelay(1); 9793 9794 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9795 9796 if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9797 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000); 9798 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9799 } 9800 9801 rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010); 9802 9803 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9804 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9805 9806 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B); 9807 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B); 9808 9809 rt2800_bbp_write(rt2x00dev, 158, 0x03); 9810 rt2800_bbp_write(rt2x00dev, 159, 0x60); 9811 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9812 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9813 9814 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9815 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9816 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9817 9818 if (ch_idx == 0) { 9819 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9820 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9821 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9822 bbp = bbpr1 & (~0x18); 9823 bbp = bbp | 0x00; 9824 rt2800_bbp_write(rt2x00dev, 1, bbp); 9825 } 9826 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9827 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9828 } else { 9829 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9830 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9831 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) { 9832 bbp = bbpr1 & (~0x18); 9833 bbp = bbp | 0x08; 9834 rt2800_bbp_write(rt2x00dev, 1, bbp); 9835 } 9836 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9837 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9838 } 9839 9840 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9841 rt2800_bbp_write(rt2x00dev, 159, 0x04); 9842 9843 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9844 rt2800_bbp_write(rt2x00dev, 158, bbp); 9845 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9846 9847 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9848 rt2800_bbp_write(rt2x00dev, 23, 0x06); 9849 rt2800_bbp_write(rt2x00dev, 24, 0x06); 9850 count_step = 1; 9851 } else { 9852 rt2800_bbp_write(rt2x00dev, 23, 0x1F); 9853 rt2800_bbp_write(rt2x00dev, 24, 0x1F); 9854 count_step = 2; 9855 } 9856 9857 for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) { 9858 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9859 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9860 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9861 9862 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9863 rt2800_bbp_write(rt2x00dev, 158, bbp); 9864 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9865 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9866 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9867 p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9868 9869 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9870 rt2800_bbp_write(rt2x00dev, 158, bbp); 9871 rt2800_bbp_write(rt2x00dev, 159, 0x21); 9872 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9873 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) 9874 p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9875 9876 rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1); 9877 9878 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9879 rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10); 9880 if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) { 9881 if (vga_gain[ch_idx] != 0) 9882 vga_gain[ch_idx] = vga_gain[ch_idx] - 1; 9883 break; 9884 } 9885 } 9886 9887 if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500)) 9888 break; 9889 } 9890 9891 if (vga_gain[ch_idx] > 18) 9892 vga_gain[ch_idx] = 18; 9893 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9894 rfvga_gain_table[vga_gain[ch_idx]]); 9895 9896 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9897 rt2800_bbp_write(rt2x00dev, 158, bbp); 9898 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9899 9900 rt2800_iq_search(rt2x00dev, ch_idx, ger, per); 9901 } 9902 9903 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9904 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9905 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9906 9907 rt2800_bbp_write(rt2x00dev, 158, 0x28); 9908 bbp = ger[CHAIN_0] & 0x0F; 9909 rt2800_bbp_write(rt2x00dev, 159, bbp); 9910 9911 rt2800_bbp_write(rt2x00dev, 158, 0x29); 9912 bbp = per[CHAIN_0] & 0x3F; 9913 rt2800_bbp_write(rt2x00dev, 159, bbp); 9914 9915 rt2800_bbp_write(rt2x00dev, 158, 0x46); 9916 bbp = ger[CHAIN_1] & 0x0F; 9917 rt2800_bbp_write(rt2x00dev, 159, bbp); 9918 9919 rt2800_bbp_write(rt2x00dev, 158, 0x47); 9920 bbp = per[CHAIN_1] & 0x3F; 9921 rt2800_bbp_write(rt2x00dev, 159, bbp); 9922 9923 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9924 rt2800_bbp_write(rt2x00dev, 1, bbpr1); 9925 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9926 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9927 } 9928 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9929 9930 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9931 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9932 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9933 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9934 9935 rt2800_bbp_write(rt2x00dev, 30, bbpr30); 9936 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39); 9937 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9938 9939 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9940 rt2800_bbp_write(rt2x00dev, 4, bbpr4); 9941 9942 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9943 udelay(1); 9944 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9945 9946 rt2800_rf_configrecover(rt2x00dev, rf_store); 9947 9948 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9949 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9950 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9951 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9952 udelay(1); 9953 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9954 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9955 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9956 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9957 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9958 } 9959 9960 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 9961 bool set_bw, bool is_ht40) 9962 { 9963 u8 bbp_val; 9964 9965 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 9966 bbp_val |= 0x1; 9967 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 9968 usleep_range(100, 200); 9969 9970 if (set_bw) { 9971 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 9972 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 9973 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 9974 usleep_range(100, 200); 9975 } 9976 9977 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 9978 bbp_val &= (~0x1); 9979 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 9980 usleep_range(100, 200); 9981 } 9982 9983 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 9984 { 9985 u8 rf_val; 9986 9987 if (btxcal) 9988 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9989 else 9990 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 9991 9992 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 9993 9994 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 9995 rf_val |= 0x80; 9996 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 9997 9998 if (btxcal) { 9999 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 10000 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 10001 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 10002 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10003 rf_val &= (~0x3F); 10004 rf_val |= 0x3F; 10005 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 10006 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10007 rf_val &= (~0x3F); 10008 rf_val |= 0x3F; 10009 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10010 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 10011 } else { 10012 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 10013 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 10014 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 10015 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10016 rf_val &= (~0x3F); 10017 rf_val |= 0x34; 10018 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 10019 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10020 rf_val &= (~0x3F); 10021 rf_val |= 0x34; 10022 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10023 } 10024 10025 return 0; 10026 } 10027 10028 static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 10029 { 10030 unsigned int cnt; 10031 u8 bbp_val; 10032 s8 cal_val; 10033 10034 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 10035 10036 cnt = 0; 10037 do { 10038 usleep_range(500, 2000); 10039 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 10040 if (bbp_val == 0x02 || cnt == 20) 10041 break; 10042 10043 cnt++; 10044 } while (cnt < 20); 10045 10046 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 10047 cal_val = bbp_val & 0x7F; 10048 if (cal_val >= 0x40) 10049 cal_val -= 128; 10050 10051 return cal_val; 10052 } 10053 10054 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 10055 bool btxcal) 10056 { 10057 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10058 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 10059 u8 filter_target; 10060 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 10061 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 10062 int loop = 0, is_ht40, cnt; 10063 u8 bbp_val, rf_val; 10064 s8 cal_r32_init, cal_r32_val, cal_diff; 10065 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 10066 u8 saverfb5r06, saverfb5r07; 10067 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 10068 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 10069 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 10070 u8 saverfb5r58, saverfb5r59; 10071 u8 savebbp159r0, savebbp159r2, savebbpr23; 10072 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 10073 10074 /* Save MAC registers */ 10075 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 10076 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 10077 10078 /* save BBP registers */ 10079 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 10080 10081 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 10082 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10083 10084 /* Save RF registers */ 10085 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10086 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10087 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10088 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10089 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 10090 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10091 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10092 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10093 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 10094 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 10095 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 10096 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 10097 10098 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 10099 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 10100 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 10101 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 10102 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 10103 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 10104 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 10105 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 10106 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 10107 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 10108 10109 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10110 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10111 10112 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10113 rf_val |= 0x3; 10114 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10115 10116 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10117 rf_val |= 0x1; 10118 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 10119 10120 cnt = 0; 10121 do { 10122 usleep_range(500, 2000); 10123 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10124 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 10125 break; 10126 cnt++; 10127 } while (cnt < 40); 10128 10129 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10130 rf_val &= (~0x3); 10131 rf_val |= 0x1; 10132 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10133 10134 /* I-3 */ 10135 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 10136 bbp_val &= (~0x1F); 10137 bbp_val |= 0x10; 10138 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 10139 10140 do { 10141 /* I-4,5,6,7,8,9 */ 10142 if (loop == 0) { 10143 is_ht40 = false; 10144 10145 if (btxcal) 10146 filter_target = tx_filter_target_20m; 10147 else 10148 filter_target = rx_filter_target_20m; 10149 } else { 10150 is_ht40 = true; 10151 10152 if (btxcal) 10153 filter_target = tx_filter_target_40m; 10154 else 10155 filter_target = rx_filter_target_40m; 10156 } 10157 10158 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10159 rf_val &= (~0x04); 10160 if (loop == 1) 10161 rf_val |= 0x4; 10162 10163 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 10164 10165 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 10166 10167 rt2800_rf_lp_config(rt2x00dev, btxcal); 10168 if (btxcal) { 10169 tx_agc_fc = 0; 10170 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10171 rf_val &= (~0x7F); 10172 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10173 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10174 rf_val &= (~0x7F); 10175 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10176 } else { 10177 rx_agc_fc = 0; 10178 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10179 rf_val &= (~0x7F); 10180 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10181 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10182 rf_val &= (~0x7F); 10183 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10184 } 10185 10186 usleep_range(1000, 2000); 10187 10188 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10189 bbp_val &= (~0x6); 10190 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10191 10192 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10193 10194 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10195 10196 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10197 bbp_val |= 0x6; 10198 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10199 do_cal: 10200 if (btxcal) { 10201 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10202 rf_val &= (~0x7F); 10203 rf_val |= tx_agc_fc; 10204 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10205 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10206 rf_val &= (~0x7F); 10207 rf_val |= tx_agc_fc; 10208 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10209 } else { 10210 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10211 rf_val &= (~0x7F); 10212 rf_val |= rx_agc_fc; 10213 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10214 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10215 rf_val &= (~0x7F); 10216 rf_val |= rx_agc_fc; 10217 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10218 } 10219 10220 usleep_range(500, 1000); 10221 10222 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10223 10224 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10225 10226 cal_diff = cal_r32_init - cal_r32_val; 10227 10228 if (btxcal) 10229 cmm_agc_fc = tx_agc_fc; 10230 else 10231 cmm_agc_fc = rx_agc_fc; 10232 10233 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 10234 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 10235 if (btxcal) 10236 tx_agc_fc = 0; 10237 else 10238 rx_agc_fc = 0; 10239 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 10240 if (btxcal) 10241 tx_agc_fc++; 10242 else 10243 rx_agc_fc++; 10244 goto do_cal; 10245 } 10246 10247 if (btxcal) { 10248 if (loop == 0) 10249 drv_data->tx_calibration_bw20 = tx_agc_fc; 10250 else 10251 drv_data->tx_calibration_bw40 = tx_agc_fc; 10252 } else { 10253 if (loop == 0) 10254 drv_data->rx_calibration_bw20 = rx_agc_fc; 10255 else 10256 drv_data->rx_calibration_bw40 = rx_agc_fc; 10257 } 10258 10259 loop++; 10260 } while (loop <= 1); 10261 10262 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 10263 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 10264 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 10265 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 10266 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 10267 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 10268 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 10269 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 10270 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 10271 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 10272 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 10273 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 10274 10275 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 10276 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 10277 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 10278 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 10279 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 10280 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 10281 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 10282 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 10283 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 10284 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 10285 10286 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 10287 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 10288 10289 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 10290 10291 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 10292 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 10293 10294 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 10295 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 10296 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 10297 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 10298 10299 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 10300 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 10301 } 10302 10303 static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev) 10304 { 10305 if (rt2x00_has_cap_external_pa(rt2x00dev)) { 10306 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0); 10307 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0); 10308 } 10309 10310 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 10311 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 10312 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 10313 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 10314 } 10315 10316 if (rt2x00_has_cap_external_pa(rt2x00dev)) { 10317 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xd3); 10318 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xb3); 10319 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xd5); 10320 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 10321 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6c); 10322 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xfc); 10323 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1f); 10324 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 10325 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10326 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xff); 10327 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1c); 10328 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 10329 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6b); 10330 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xf7); 10331 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 10332 } 10333 10334 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 10335 rt2800_bbp_write(rt2x00dev, 75, 0x60); 10336 rt2800_bbp_write(rt2x00dev, 76, 0x44); 10337 rt2800_bbp_write(rt2x00dev, 79, 0x1c); 10338 rt2800_bbp_write(rt2x00dev, 80, 0x0c); 10339 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 10340 } 10341 10342 if (rt2x00_has_cap_external_pa(rt2x00dev)) { 10343 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363a); 10344 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c666c); 10345 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c666c); 10346 } 10347 } 10348 10349 static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev) 10350 { 10351 u32 reg; 10352 10353 if (rt2x00_has_cap_external_pa(rt2x00dev) || 10354 rt2x00_has_cap_external_lna_bg(rt2x00dev)) 10355 rt2800_restore_rf_bbp_rt6352(rt2x00dev); 10356 10357 rt2800_r_calibration(rt2x00dev); 10358 rt2800_rf_self_txdc_cal(rt2x00dev); 10359 rt2800_rxdcoc_calibration(rt2x00dev); 10360 rt2800_bw_filter_calibration(rt2x00dev, true); 10361 rt2800_bw_filter_calibration(rt2x00dev, false); 10362 rt2800_loft_iq_calibration(rt2x00dev); 10363 10364 /* missing DPD calibration for internal PA devices */ 10365 10366 rt2800_rxdcoc_calibration(rt2x00dev); 10367 rt2800_rxiq_calibration(rt2x00dev); 10368 10369 if (!rt2x00_has_cap_external_pa(rt2x00dev) && 10370 !rt2x00_has_cap_external_lna_bg(rt2x00dev)) 10371 return; 10372 10373 if (rt2x00_has_cap_external_pa(rt2x00dev)) { 10374 reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); 10375 reg |= 0x00000101; 10376 rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); 10377 10378 reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); 10379 reg |= 0x00000101; 10380 rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); 10381 } 10382 10383 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 10384 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66); 10385 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20); 10386 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42); 10387 } 10388 10389 if (rt2x00_has_cap_external_pa(rt2x00dev)) { 10390 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73); 10391 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73); 10392 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73); 10393 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 10394 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xc8); 10395 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xa4); 10396 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05); 10397 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 10398 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xc8); 10399 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xa4); 10400 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05); 10401 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27); 10402 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xc8); 10403 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xa4); 10404 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05); 10405 } 10406 10407 if (rt2x00_has_cap_external_pa(rt2x00dev)) 10408 rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00); 10409 10410 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 10411 rt2800_bbp_write(rt2x00dev, 75, 0x68); 10412 rt2800_bbp_write(rt2x00dev, 76, 0x4c); 10413 rt2800_bbp_write(rt2x00dev, 79, 0x1c); 10414 rt2800_bbp_write(rt2x00dev, 80, 0x0c); 10415 rt2800_bbp_write(rt2x00dev, 82, 0xb6); 10416 } 10417 10418 if (rt2x00_has_cap_external_pa(rt2x00dev)) { 10419 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636); 10420 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c6b6c); 10421 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c6b6c); 10422 } 10423 } 10424 10425 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 10426 { 10427 /* Initialize RF central register to default value */ 10428 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 10429 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 10430 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 10431 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 10432 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 10433 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 10434 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 10435 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 10436 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 10437 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 10438 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 10439 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 10440 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 10441 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10442 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 10443 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 10444 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 10445 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 10446 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 10447 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 10448 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 10449 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 10450 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 10451 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 10452 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 10453 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 10454 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 10455 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10456 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 10457 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 10458 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 10459 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 10460 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 10461 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 10462 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 10463 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 10464 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 10465 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 10466 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 10467 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 10468 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 10469 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 10470 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 10471 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 10472 10473 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 10474 if (rt2800_clk_is_20mhz(rt2x00dev)) 10475 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 10476 else 10477 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10478 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 10479 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 10480 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 10481 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 10482 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 10483 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 10484 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 10485 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 10486 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 10487 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 10488 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 10489 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 10490 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10491 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 10492 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 10493 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 10494 10495 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 10496 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 10497 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 10498 10499 /* Initialize RF channel register to default value */ 10500 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 10501 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 10502 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 10503 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 10504 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 10505 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 10506 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 10507 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 10508 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 10509 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 10510 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 10511 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10512 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 10513 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 10514 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10515 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 10516 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 10517 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 10518 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 10519 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10520 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 10521 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 10522 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 10523 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 10524 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 10525 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 10526 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 10527 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 10528 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 10529 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 10530 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 10531 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 10532 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 10533 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 10534 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 10535 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 10536 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 10537 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 10538 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 10539 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 10540 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 10541 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 10542 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 10543 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 10544 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 10545 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10546 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 10547 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 10548 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 10549 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 10550 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 10551 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 10552 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 10553 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 10554 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 10555 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 10556 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 10557 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 10558 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 10559 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 10560 10561 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 10562 10563 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 10564 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 10565 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 10566 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 10567 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 10568 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 10569 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 10570 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 10571 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 10572 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 10573 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 10574 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 10575 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 10576 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 10577 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10578 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 10579 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10580 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 10581 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 10582 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 10583 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 10584 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 10585 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 10586 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10587 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 10588 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 10589 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 10590 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10591 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 10592 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 10593 10594 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 10595 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10596 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10597 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 10598 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 10599 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 10600 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 10601 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10602 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 10603 10604 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 10605 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 10606 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 10607 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 10608 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10609 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10610 10611 /* Initialize RF channel register for DRQFN */ 10612 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10613 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 10614 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 10615 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 10616 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 10617 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 10618 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 10619 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 10620 10621 /* Initialize RF DC calibration register to default value */ 10622 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 10623 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 10624 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 10625 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 10626 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 10627 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10628 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 10629 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 10630 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 10631 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 10632 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 10633 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 10634 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 10635 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 10636 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 10637 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 10638 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 10639 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 10640 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 10641 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 10642 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 10643 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 10644 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 10645 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 10646 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 10647 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 10648 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 10649 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 10650 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 10651 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 10652 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 10653 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 10654 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 10655 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 10656 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 10657 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 10658 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 10659 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 10660 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 10661 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 10662 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 10663 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 10664 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 10665 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 10666 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 10667 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 10668 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 10669 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 10670 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 10671 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 10672 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 10673 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 10674 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 10675 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 10676 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 10677 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 10678 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 10679 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 10680 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 10681 10682 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 10683 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 10684 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 10685 10686 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10687 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 10688 10689 /* Do calibration and init PA/LNA */ 10690 rt2800_calibration_rt6352(rt2x00dev); 10691 } 10692 10693 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 10694 { 10695 if (rt2800_is_305x_soc(rt2x00dev)) { 10696 rt2800_init_rfcsr_305x_soc(rt2x00dev); 10697 return; 10698 } 10699 10700 switch (rt2x00dev->chip.rt) { 10701 case RT3070: 10702 case RT3071: 10703 case RT3090: 10704 rt2800_init_rfcsr_30xx(rt2x00dev); 10705 break; 10706 case RT3290: 10707 rt2800_init_rfcsr_3290(rt2x00dev); 10708 break; 10709 case RT3352: 10710 rt2800_init_rfcsr_3352(rt2x00dev); 10711 break; 10712 case RT3390: 10713 rt2800_init_rfcsr_3390(rt2x00dev); 10714 break; 10715 case RT3883: 10716 rt2800_init_rfcsr_3883(rt2x00dev); 10717 break; 10718 case RT3572: 10719 rt2800_init_rfcsr_3572(rt2x00dev); 10720 break; 10721 case RT3593: 10722 rt2800_init_rfcsr_3593(rt2x00dev); 10723 break; 10724 case RT5350: 10725 rt2800_init_rfcsr_5350(rt2x00dev); 10726 break; 10727 case RT5390: 10728 rt2800_init_rfcsr_5390(rt2x00dev); 10729 break; 10730 case RT5392: 10731 rt2800_init_rfcsr_5392(rt2x00dev); 10732 break; 10733 case RT5592: 10734 rt2800_init_rfcsr_5592(rt2x00dev); 10735 break; 10736 case RT6352: 10737 rt2800_init_rfcsr_6352(rt2x00dev); 10738 break; 10739 } 10740 } 10741 10742 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 10743 { 10744 u32 reg; 10745 u16 word; 10746 10747 /* 10748 * Initialize MAC registers. 10749 */ 10750 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 10751 rt2800_init_registers(rt2x00dev))) 10752 return -EIO; 10753 10754 /* 10755 * Wait BBP/RF to wake up. 10756 */ 10757 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 10758 return -EIO; 10759 10760 /* 10761 * Send signal during boot time to initialize firmware. 10762 */ 10763 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 10764 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 10765 if (rt2x00_is_usb(rt2x00dev)) 10766 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 10767 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 10768 msleep(1); 10769 10770 /* 10771 * Make sure BBP is up and running. 10772 */ 10773 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 10774 return -EIO; 10775 10776 /* 10777 * Initialize BBP/RF registers. 10778 */ 10779 rt2800_init_bbp(rt2x00dev); 10780 rt2800_init_rfcsr(rt2x00dev); 10781 10782 if (rt2x00_is_usb(rt2x00dev) && 10783 (rt2x00_rt(rt2x00dev, RT3070) || 10784 rt2x00_rt(rt2x00dev, RT3071) || 10785 rt2x00_rt(rt2x00dev, RT3572))) { 10786 udelay(200); 10787 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 10788 udelay(10); 10789 } 10790 10791 /* 10792 * Enable RX. 10793 */ 10794 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10795 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10796 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10797 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10798 10799 udelay(50); 10800 10801 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 10802 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 10803 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 10804 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 10805 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 10806 10807 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10808 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10809 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 10810 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10811 10812 /* 10813 * Initialize LED control 10814 */ 10815 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 10816 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 10817 word & 0xff, (word >> 8) & 0xff); 10818 10819 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 10820 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 10821 word & 0xff, (word >> 8) & 0xff); 10822 10823 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 10824 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 10825 word & 0xff, (word >> 8) & 0xff); 10826 10827 return 0; 10828 } 10829 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 10830 10831 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 10832 { 10833 u32 reg; 10834 10835 rt2800_disable_wpdma(rt2x00dev); 10836 10837 /* Wait for DMA, ignore error */ 10838 rt2800_wait_wpdma_ready(rt2x00dev); 10839 10840 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10841 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 10842 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10843 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10844 } 10845 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 10846 10847 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 10848 { 10849 u32 reg; 10850 u16 efuse_ctrl_reg; 10851 10852 if (rt2x00_rt(rt2x00dev, RT3290)) 10853 efuse_ctrl_reg = EFUSE_CTRL_3290; 10854 else 10855 efuse_ctrl_reg = EFUSE_CTRL; 10856 10857 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 10858 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 10859 } 10860 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 10861 10862 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 10863 { 10864 u32 reg; 10865 u16 efuse_ctrl_reg; 10866 u16 efuse_data0_reg; 10867 u16 efuse_data1_reg; 10868 u16 efuse_data2_reg; 10869 u16 efuse_data3_reg; 10870 10871 if (rt2x00_rt(rt2x00dev, RT3290)) { 10872 efuse_ctrl_reg = EFUSE_CTRL_3290; 10873 efuse_data0_reg = EFUSE_DATA0_3290; 10874 efuse_data1_reg = EFUSE_DATA1_3290; 10875 efuse_data2_reg = EFUSE_DATA2_3290; 10876 efuse_data3_reg = EFUSE_DATA3_3290; 10877 } else { 10878 efuse_ctrl_reg = EFUSE_CTRL; 10879 efuse_data0_reg = EFUSE_DATA0; 10880 efuse_data1_reg = EFUSE_DATA1; 10881 efuse_data2_reg = EFUSE_DATA2; 10882 efuse_data3_reg = EFUSE_DATA3; 10883 } 10884 mutex_lock(&rt2x00dev->csr_mutex); 10885 10886 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 10887 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 10888 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 10889 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 10890 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 10891 10892 /* Wait until the EEPROM has been loaded */ 10893 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 10894 /* Apparently the data is read from end to start */ 10895 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 10896 /* The returned value is in CPU order, but eeprom is le */ 10897 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 10898 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 10899 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 10900 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 10901 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 10902 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 10903 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 10904 10905 mutex_unlock(&rt2x00dev->csr_mutex); 10906 } 10907 10908 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 10909 { 10910 unsigned int i; 10911 10912 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 10913 rt2800_efuse_read(rt2x00dev, i); 10914 10915 return 0; 10916 } 10917 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 10918 10919 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 10920 { 10921 u16 word; 10922 10923 if (rt2x00_rt(rt2x00dev, RT3593) || 10924 rt2x00_rt(rt2x00dev, RT3883)) 10925 return 0; 10926 10927 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 10928 if ((word & 0x00ff) != 0x00ff) 10929 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 10930 10931 return 0; 10932 } 10933 10934 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 10935 { 10936 u16 word; 10937 10938 if (rt2x00_rt(rt2x00dev, RT3593) || 10939 rt2x00_rt(rt2x00dev, RT3883)) 10940 return 0; 10941 10942 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 10943 if ((word & 0x00ff) != 0x00ff) 10944 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 10945 10946 return 0; 10947 } 10948 10949 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 10950 { 10951 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10952 u16 word; 10953 u8 *mac; 10954 u8 default_lna_gain; 10955 int retval; 10956 10957 /* 10958 * Read the EEPROM. 10959 */ 10960 retval = rt2800_read_eeprom(rt2x00dev); 10961 if (retval) 10962 return retval; 10963 10964 /* 10965 * Start validation of the data that has been read. 10966 */ 10967 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 10968 rt2x00lib_set_mac_address(rt2x00dev, mac); 10969 10970 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 10971 if (word == 0xffff) { 10972 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10973 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 10974 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 10975 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10976 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 10977 } else if (rt2x00_rt(rt2x00dev, RT2860) || 10978 rt2x00_rt(rt2x00dev, RT2872)) { 10979 /* 10980 * There is a max of 2 RX streams for RT28x0 series 10981 */ 10982 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 10983 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10984 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10985 } 10986 10987 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 10988 if (word == 0xffff) { 10989 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 10990 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 10991 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 10992 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 10993 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 10994 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 10995 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 10996 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 10997 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 10998 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 10999 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 11000 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 11001 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 11002 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 11003 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 11004 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 11005 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 11006 } 11007 11008 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 11009 if ((word & 0x00ff) == 0x00ff) { 11010 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 11011 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 11012 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 11013 } 11014 if ((word & 0xff00) == 0xff00) { 11015 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 11016 LED_MODE_TXRX_ACTIVITY); 11017 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 11018 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 11019 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 11020 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 11021 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 11022 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 11023 } 11024 11025 /* 11026 * During the LNA validation we are going to use 11027 * lna0 as correct value. Note that EEPROM_LNA 11028 * is never validated. 11029 */ 11030 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 11031 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 11032 11033 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 11034 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 11035 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 11036 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 11037 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 11038 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 11039 11040 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 11041 11042 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 11043 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 11044 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 11045 if (!rt2x00_rt(rt2x00dev, RT3593) && 11046 !rt2x00_rt(rt2x00dev, RT3883)) { 11047 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 11048 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 11049 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 11050 default_lna_gain); 11051 } 11052 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 11053 11054 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 11055 11056 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 11057 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 11058 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 11059 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 11060 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 11061 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 11062 11063 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 11064 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 11065 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 11066 if (!rt2x00_rt(rt2x00dev, RT3593) && 11067 !rt2x00_rt(rt2x00dev, RT3883)) { 11068 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 11069 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 11070 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 11071 default_lna_gain); 11072 } 11073 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 11074 11075 if (rt2x00_rt(rt2x00dev, RT3593) || 11076 rt2x00_rt(rt2x00dev, RT3883)) { 11077 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 11078 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 11079 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 11080 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 11081 default_lna_gain); 11082 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 11083 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 11084 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 11085 default_lna_gain); 11086 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 11087 } 11088 11089 return 0; 11090 } 11091 11092 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 11093 { 11094 u16 value; 11095 u16 eeprom; 11096 u16 rf; 11097 11098 /* 11099 * Read EEPROM word for configuration. 11100 */ 11101 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 11102 11103 /* 11104 * Identify RF chipset by EEPROM value 11105 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 11106 * RT53xx: defined in "EEPROM_CHIP_ID" field 11107 */ 11108 if (rt2x00_rt(rt2x00dev, RT3290) || 11109 rt2x00_rt(rt2x00dev, RT5390) || 11110 rt2x00_rt(rt2x00dev, RT5392) || 11111 rt2x00_rt(rt2x00dev, RT6352)) 11112 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 11113 else if (rt2x00_rt(rt2x00dev, RT3352)) 11114 rf = RF3322; 11115 else if (rt2x00_rt(rt2x00dev, RT3883)) 11116 rf = RF3853; 11117 else if (rt2x00_rt(rt2x00dev, RT5350)) 11118 rf = RF5350; 11119 else if (rt2x00_rt(rt2x00dev, RT5592)) 11120 rf = RF5592; 11121 else 11122 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 11123 11124 switch (rf) { 11125 case RF2820: 11126 case RF2850: 11127 case RF2720: 11128 case RF2750: 11129 case RF3020: 11130 case RF2020: 11131 case RF3021: 11132 case RF3022: 11133 case RF3052: 11134 case RF3053: 11135 case RF3070: 11136 case RF3290: 11137 case RF3320: 11138 case RF3322: 11139 case RF3853: 11140 case RF5350: 11141 case RF5360: 11142 case RF5362: 11143 case RF5370: 11144 case RF5372: 11145 case RF5390: 11146 case RF5392: 11147 case RF5592: 11148 case RF7620: 11149 break; 11150 default: 11151 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 11152 rf); 11153 return -ENODEV; 11154 } 11155 11156 rt2x00_set_rf(rt2x00dev, rf); 11157 11158 /* 11159 * Identify default antenna configuration. 11160 */ 11161 rt2x00dev->default_ant.tx_chain_num = 11162 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 11163 rt2x00dev->default_ant.rx_chain_num = 11164 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 11165 11166 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11167 11168 if (rt2x00_rt(rt2x00dev, RT3070) || 11169 rt2x00_rt(rt2x00dev, RT3090) || 11170 rt2x00_rt(rt2x00dev, RT3352) || 11171 rt2x00_rt(rt2x00dev, RT3390)) { 11172 value = rt2x00_get_field16(eeprom, 11173 EEPROM_NIC_CONF1_ANT_DIVERSITY); 11174 switch (value) { 11175 case 0: 11176 case 1: 11177 case 2: 11178 rt2x00dev->default_ant.tx = ANTENNA_A; 11179 rt2x00dev->default_ant.rx = ANTENNA_A; 11180 break; 11181 case 3: 11182 rt2x00dev->default_ant.tx = ANTENNA_A; 11183 rt2x00dev->default_ant.rx = ANTENNA_B; 11184 break; 11185 } 11186 } else { 11187 rt2x00dev->default_ant.tx = ANTENNA_A; 11188 rt2x00dev->default_ant.rx = ANTENNA_A; 11189 } 11190 11191 /* These chips have hardware RX antenna diversity */ 11192 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 11193 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 11194 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 11195 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 11196 } 11197 11198 /* 11199 * Determine external LNA informations. 11200 */ 11201 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 11202 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 11203 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 11204 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 11205 11206 /* 11207 * Detect if this device has an hardware controlled radio. 11208 */ 11209 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 11210 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 11211 11212 /* 11213 * Detect if this device has Bluetooth co-existence. 11214 */ 11215 if (!rt2x00_rt(rt2x00dev, RT3352) && 11216 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 11217 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 11218 11219 /* 11220 * Read frequency offset and RF programming sequence. 11221 */ 11222 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 11223 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 11224 11225 /* 11226 * Store led settings, for correct led behaviour. 11227 */ 11228 #ifdef CONFIG_RT2X00_LIB_LEDS 11229 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 11230 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 11231 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 11232 11233 rt2x00dev->led_mcu_reg = eeprom; 11234 #endif /* CONFIG_RT2X00_LIB_LEDS */ 11235 11236 /* 11237 * Check if support EIRP tx power limit feature. 11238 */ 11239 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 11240 11241 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 11242 EIRP_MAX_TX_POWER_LIMIT) 11243 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 11244 11245 /* 11246 * Detect if device uses internal or external PA 11247 */ 11248 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11249 11250 if (rt2x00_rt(rt2x00dev, RT3352) || 11251 rt2x00_rt(rt2x00dev, RT6352)) { 11252 if (rt2x00_get_field16(eeprom, 11253 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 11254 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 11255 &rt2x00dev->cap_flags); 11256 if (rt2x00_get_field16(eeprom, 11257 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 11258 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 11259 &rt2x00dev->cap_flags); 11260 } 11261 11262 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2); 11263 11264 if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) { 11265 if (!rt2x00_get_field16(eeprom, 11266 EEPROM_NIC_CONF2_EXTERNAL_PA)) { 11267 __clear_bit(CAPABILITY_EXTERNAL_PA_TX0, 11268 &rt2x00dev->cap_flags); 11269 __clear_bit(CAPABILITY_EXTERNAL_PA_TX1, 11270 &rt2x00dev->cap_flags); 11271 } 11272 } 11273 11274 return 0; 11275 } 11276 11277 /* 11278 * RF value list for rt28xx 11279 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 11280 */ 11281 static const struct rf_channel rf_vals[] = { 11282 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 11283 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 11284 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 11285 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 11286 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 11287 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 11288 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 11289 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 11290 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 11291 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 11292 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 11293 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 11294 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 11295 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 11296 11297 /* 802.11 UNI / HyperLan 2 */ 11298 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 11299 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 11300 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 11301 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 11302 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 11303 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 11304 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 11305 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 11306 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 11307 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 11308 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 11309 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 11310 11311 /* 802.11 HyperLan 2 */ 11312 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 11313 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 11314 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 11315 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 11316 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 11317 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 11318 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 11319 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 11320 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 11321 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 11322 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 11323 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 11324 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 11325 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 11326 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 11327 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 11328 11329 /* 802.11 UNII */ 11330 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 11331 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 11332 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 11333 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 11334 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 11335 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 11336 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 11337 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 11338 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 11339 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 11340 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 11341 11342 /* 802.11 Japan */ 11343 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 11344 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 11345 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 11346 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 11347 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 11348 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 11349 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 11350 }; 11351 11352 /* 11353 * RF value list for rt3xxx 11354 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 11355 */ 11356 static const struct rf_channel rf_vals_3x[] = { 11357 {1, 241, 2, 2 }, 11358 {2, 241, 2, 7 }, 11359 {3, 242, 2, 2 }, 11360 {4, 242, 2, 7 }, 11361 {5, 243, 2, 2 }, 11362 {6, 243, 2, 7 }, 11363 {7, 244, 2, 2 }, 11364 {8, 244, 2, 7 }, 11365 {9, 245, 2, 2 }, 11366 {10, 245, 2, 7 }, 11367 {11, 246, 2, 2 }, 11368 {12, 246, 2, 7 }, 11369 {13, 247, 2, 2 }, 11370 {14, 248, 2, 4 }, 11371 11372 /* 802.11 UNI / HyperLan 2 */ 11373 {36, 0x56, 0, 4}, 11374 {38, 0x56, 0, 6}, 11375 {40, 0x56, 0, 8}, 11376 {44, 0x57, 0, 0}, 11377 {46, 0x57, 0, 2}, 11378 {48, 0x57, 0, 4}, 11379 {52, 0x57, 0, 8}, 11380 {54, 0x57, 0, 10}, 11381 {56, 0x58, 0, 0}, 11382 {60, 0x58, 0, 4}, 11383 {62, 0x58, 0, 6}, 11384 {64, 0x58, 0, 8}, 11385 11386 /* 802.11 HyperLan 2 */ 11387 {100, 0x5b, 0, 8}, 11388 {102, 0x5b, 0, 10}, 11389 {104, 0x5c, 0, 0}, 11390 {108, 0x5c, 0, 4}, 11391 {110, 0x5c, 0, 6}, 11392 {112, 0x5c, 0, 8}, 11393 {116, 0x5d, 0, 0}, 11394 {118, 0x5d, 0, 2}, 11395 {120, 0x5d, 0, 4}, 11396 {124, 0x5d, 0, 8}, 11397 {126, 0x5d, 0, 10}, 11398 {128, 0x5e, 0, 0}, 11399 {132, 0x5e, 0, 4}, 11400 {134, 0x5e, 0, 6}, 11401 {136, 0x5e, 0, 8}, 11402 {140, 0x5f, 0, 0}, 11403 11404 /* 802.11 UNII */ 11405 {149, 0x5f, 0, 9}, 11406 {151, 0x5f, 0, 11}, 11407 {153, 0x60, 0, 1}, 11408 {157, 0x60, 0, 5}, 11409 {159, 0x60, 0, 7}, 11410 {161, 0x60, 0, 9}, 11411 {165, 0x61, 0, 1}, 11412 {167, 0x61, 0, 3}, 11413 {169, 0x61, 0, 5}, 11414 {171, 0x61, 0, 7}, 11415 {173, 0x61, 0, 9}, 11416 }; 11417 11418 /* 11419 * RF value list for rt3xxx with Xtal20MHz 11420 * Supports: 2.4 GHz (all) (RF3322) 11421 */ 11422 static const struct rf_channel rf_vals_3x_xtal20[] = { 11423 {1, 0xE2, 2, 0x14}, 11424 {2, 0xE3, 2, 0x14}, 11425 {3, 0xE4, 2, 0x14}, 11426 {4, 0xE5, 2, 0x14}, 11427 {5, 0xE6, 2, 0x14}, 11428 {6, 0xE7, 2, 0x14}, 11429 {7, 0xE8, 2, 0x14}, 11430 {8, 0xE9, 2, 0x14}, 11431 {9, 0xEA, 2, 0x14}, 11432 {10, 0xEB, 2, 0x14}, 11433 {11, 0xEC, 2, 0x14}, 11434 {12, 0xED, 2, 0x14}, 11435 {13, 0xEE, 2, 0x14}, 11436 {14, 0xF0, 2, 0x18}, 11437 }; 11438 11439 static const struct rf_channel rf_vals_3853[] = { 11440 {1, 241, 6, 2}, 11441 {2, 241, 6, 7}, 11442 {3, 242, 6, 2}, 11443 {4, 242, 6, 7}, 11444 {5, 243, 6, 2}, 11445 {6, 243, 6, 7}, 11446 {7, 244, 6, 2}, 11447 {8, 244, 6, 7}, 11448 {9, 245, 6, 2}, 11449 {10, 245, 6, 7}, 11450 {11, 246, 6, 2}, 11451 {12, 246, 6, 7}, 11452 {13, 247, 6, 2}, 11453 {14, 248, 6, 4}, 11454 11455 {36, 0x56, 8, 4}, 11456 {38, 0x56, 8, 6}, 11457 {40, 0x56, 8, 8}, 11458 {44, 0x57, 8, 0}, 11459 {46, 0x57, 8, 2}, 11460 {48, 0x57, 8, 4}, 11461 {52, 0x57, 8, 8}, 11462 {54, 0x57, 8, 10}, 11463 {56, 0x58, 8, 0}, 11464 {60, 0x58, 8, 4}, 11465 {62, 0x58, 8, 6}, 11466 {64, 0x58, 8, 8}, 11467 11468 {100, 0x5b, 8, 8}, 11469 {102, 0x5b, 8, 10}, 11470 {104, 0x5c, 8, 0}, 11471 {108, 0x5c, 8, 4}, 11472 {110, 0x5c, 8, 6}, 11473 {112, 0x5c, 8, 8}, 11474 {114, 0x5c, 8, 10}, 11475 {116, 0x5d, 8, 0}, 11476 {118, 0x5d, 8, 2}, 11477 {120, 0x5d, 8, 4}, 11478 {124, 0x5d, 8, 8}, 11479 {126, 0x5d, 8, 10}, 11480 {128, 0x5e, 8, 0}, 11481 {132, 0x5e, 8, 4}, 11482 {134, 0x5e, 8, 6}, 11483 {136, 0x5e, 8, 8}, 11484 {140, 0x5f, 8, 0}, 11485 11486 {149, 0x5f, 8, 9}, 11487 {151, 0x5f, 8, 11}, 11488 {153, 0x60, 8, 1}, 11489 {157, 0x60, 8, 5}, 11490 {159, 0x60, 8, 7}, 11491 {161, 0x60, 8, 9}, 11492 {165, 0x61, 8, 1}, 11493 {167, 0x61, 8, 3}, 11494 {169, 0x61, 8, 5}, 11495 {171, 0x61, 8, 7}, 11496 {173, 0x61, 8, 9}, 11497 }; 11498 11499 static const struct rf_channel rf_vals_5592_xtal20[] = { 11500 /* Channel, N, K, mod, R */ 11501 {1, 482, 4, 10, 3}, 11502 {2, 483, 4, 10, 3}, 11503 {3, 484, 4, 10, 3}, 11504 {4, 485, 4, 10, 3}, 11505 {5, 486, 4, 10, 3}, 11506 {6, 487, 4, 10, 3}, 11507 {7, 488, 4, 10, 3}, 11508 {8, 489, 4, 10, 3}, 11509 {9, 490, 4, 10, 3}, 11510 {10, 491, 4, 10, 3}, 11511 {11, 492, 4, 10, 3}, 11512 {12, 493, 4, 10, 3}, 11513 {13, 494, 4, 10, 3}, 11514 {14, 496, 8, 10, 3}, 11515 {36, 172, 8, 12, 1}, 11516 {38, 173, 0, 12, 1}, 11517 {40, 173, 4, 12, 1}, 11518 {42, 173, 8, 12, 1}, 11519 {44, 174, 0, 12, 1}, 11520 {46, 174, 4, 12, 1}, 11521 {48, 174, 8, 12, 1}, 11522 {50, 175, 0, 12, 1}, 11523 {52, 175, 4, 12, 1}, 11524 {54, 175, 8, 12, 1}, 11525 {56, 176, 0, 12, 1}, 11526 {58, 176, 4, 12, 1}, 11527 {60, 176, 8, 12, 1}, 11528 {62, 177, 0, 12, 1}, 11529 {64, 177, 4, 12, 1}, 11530 {100, 183, 4, 12, 1}, 11531 {102, 183, 8, 12, 1}, 11532 {104, 184, 0, 12, 1}, 11533 {106, 184, 4, 12, 1}, 11534 {108, 184, 8, 12, 1}, 11535 {110, 185, 0, 12, 1}, 11536 {112, 185, 4, 12, 1}, 11537 {114, 185, 8, 12, 1}, 11538 {116, 186, 0, 12, 1}, 11539 {118, 186, 4, 12, 1}, 11540 {120, 186, 8, 12, 1}, 11541 {122, 187, 0, 12, 1}, 11542 {124, 187, 4, 12, 1}, 11543 {126, 187, 8, 12, 1}, 11544 {128, 188, 0, 12, 1}, 11545 {130, 188, 4, 12, 1}, 11546 {132, 188, 8, 12, 1}, 11547 {134, 189, 0, 12, 1}, 11548 {136, 189, 4, 12, 1}, 11549 {138, 189, 8, 12, 1}, 11550 {140, 190, 0, 12, 1}, 11551 {149, 191, 6, 12, 1}, 11552 {151, 191, 10, 12, 1}, 11553 {153, 192, 2, 12, 1}, 11554 {155, 192, 6, 12, 1}, 11555 {157, 192, 10, 12, 1}, 11556 {159, 193, 2, 12, 1}, 11557 {161, 193, 6, 12, 1}, 11558 {165, 194, 2, 12, 1}, 11559 {184, 164, 0, 12, 1}, 11560 {188, 164, 4, 12, 1}, 11561 {192, 165, 8, 12, 1}, 11562 {196, 166, 0, 12, 1}, 11563 }; 11564 11565 static const struct rf_channel rf_vals_5592_xtal40[] = { 11566 /* Channel, N, K, mod, R */ 11567 {1, 241, 2, 10, 3}, 11568 {2, 241, 7, 10, 3}, 11569 {3, 242, 2, 10, 3}, 11570 {4, 242, 7, 10, 3}, 11571 {5, 243, 2, 10, 3}, 11572 {6, 243, 7, 10, 3}, 11573 {7, 244, 2, 10, 3}, 11574 {8, 244, 7, 10, 3}, 11575 {9, 245, 2, 10, 3}, 11576 {10, 245, 7, 10, 3}, 11577 {11, 246, 2, 10, 3}, 11578 {12, 246, 7, 10, 3}, 11579 {13, 247, 2, 10, 3}, 11580 {14, 248, 4, 10, 3}, 11581 {36, 86, 4, 12, 1}, 11582 {38, 86, 6, 12, 1}, 11583 {40, 86, 8, 12, 1}, 11584 {42, 86, 10, 12, 1}, 11585 {44, 87, 0, 12, 1}, 11586 {46, 87, 2, 12, 1}, 11587 {48, 87, 4, 12, 1}, 11588 {50, 87, 6, 12, 1}, 11589 {52, 87, 8, 12, 1}, 11590 {54, 87, 10, 12, 1}, 11591 {56, 88, 0, 12, 1}, 11592 {58, 88, 2, 12, 1}, 11593 {60, 88, 4, 12, 1}, 11594 {62, 88, 6, 12, 1}, 11595 {64, 88, 8, 12, 1}, 11596 {100, 91, 8, 12, 1}, 11597 {102, 91, 10, 12, 1}, 11598 {104, 92, 0, 12, 1}, 11599 {106, 92, 2, 12, 1}, 11600 {108, 92, 4, 12, 1}, 11601 {110, 92, 6, 12, 1}, 11602 {112, 92, 8, 12, 1}, 11603 {114, 92, 10, 12, 1}, 11604 {116, 93, 0, 12, 1}, 11605 {118, 93, 2, 12, 1}, 11606 {120, 93, 4, 12, 1}, 11607 {122, 93, 6, 12, 1}, 11608 {124, 93, 8, 12, 1}, 11609 {126, 93, 10, 12, 1}, 11610 {128, 94, 0, 12, 1}, 11611 {130, 94, 2, 12, 1}, 11612 {132, 94, 4, 12, 1}, 11613 {134, 94, 6, 12, 1}, 11614 {136, 94, 8, 12, 1}, 11615 {138, 94, 10, 12, 1}, 11616 {140, 95, 0, 12, 1}, 11617 {149, 95, 9, 12, 1}, 11618 {151, 95, 11, 12, 1}, 11619 {153, 96, 1, 12, 1}, 11620 {155, 96, 3, 12, 1}, 11621 {157, 96, 5, 12, 1}, 11622 {159, 96, 7, 12, 1}, 11623 {161, 96, 9, 12, 1}, 11624 {165, 97, 1, 12, 1}, 11625 {184, 82, 0, 12, 1}, 11626 {188, 82, 4, 12, 1}, 11627 {192, 82, 8, 12, 1}, 11628 {196, 83, 0, 12, 1}, 11629 }; 11630 11631 static const struct rf_channel rf_vals_7620[] = { 11632 {1, 0x50, 0x99, 0x99, 1}, 11633 {2, 0x50, 0x44, 0x44, 2}, 11634 {3, 0x50, 0xEE, 0xEE, 2}, 11635 {4, 0x50, 0x99, 0x99, 3}, 11636 {5, 0x51, 0x44, 0x44, 0}, 11637 {6, 0x51, 0xEE, 0xEE, 0}, 11638 {7, 0x51, 0x99, 0x99, 1}, 11639 {8, 0x51, 0x44, 0x44, 2}, 11640 {9, 0x51, 0xEE, 0xEE, 2}, 11641 {10, 0x51, 0x99, 0x99, 3}, 11642 {11, 0x52, 0x44, 0x44, 0}, 11643 {12, 0x52, 0xEE, 0xEE, 0}, 11644 {13, 0x52, 0x99, 0x99, 1}, 11645 {14, 0x52, 0x33, 0x33, 3}, 11646 }; 11647 11648 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 11649 { 11650 struct hw_mode_spec *spec = &rt2x00dev->spec; 11651 struct channel_info *info; 11652 s8 *default_power1; 11653 s8 *default_power2; 11654 s8 *default_power3; 11655 unsigned int i, tx_chains, rx_chains; 11656 u32 reg; 11657 11658 /* 11659 * Disable powersaving as default. 11660 */ 11661 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 11662 11663 /* 11664 * Change default retry settings to values corresponding more closely 11665 * to rate[0].count setting of minstrel rate control algorithm. 11666 */ 11667 rt2x00dev->hw->wiphy->retry_short = 2; 11668 rt2x00dev->hw->wiphy->retry_long = 2; 11669 11670 /* 11671 * Initialize all hw fields. 11672 */ 11673 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 11674 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 11675 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 11676 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 11677 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 11678 11679 /* 11680 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 11681 * unless we are capable of sending the buffered frames out after the 11682 * DTIM transmission using rt2x00lib_beacondone. This will send out 11683 * multicast and broadcast traffic immediately instead of buffering it 11684 * infinitly and thus dropping it after some time. 11685 */ 11686 if (!rt2x00_is_usb(rt2x00dev)) 11687 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 11688 11689 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 11690 11691 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 11692 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 11693 rt2800_eeprom_addr(rt2x00dev, 11694 EEPROM_MAC_ADDR_0)); 11695 11696 /* 11697 * As rt2800 has a global fallback table we cannot specify 11698 * more then one tx rate per frame but since the hw will 11699 * try several rates (based on the fallback table) we should 11700 * initialize max_report_rates to the maximum number of rates 11701 * we are going to try. Otherwise mac80211 will truncate our 11702 * reported tx rates and the rc algortihm will end up with 11703 * incorrect data. 11704 */ 11705 rt2x00dev->hw->max_rates = 1; 11706 rt2x00dev->hw->max_report_rates = 7; 11707 rt2x00dev->hw->max_rate_tries = 1; 11708 11709 /* 11710 * Initialize hw_mode information. 11711 */ 11712 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 11713 11714 switch (rt2x00dev->chip.rf) { 11715 case RF2720: 11716 case RF2820: 11717 spec->num_channels = 14; 11718 spec->channels = rf_vals; 11719 break; 11720 11721 case RF2750: 11722 case RF2850: 11723 spec->num_channels = ARRAY_SIZE(rf_vals); 11724 spec->channels = rf_vals; 11725 break; 11726 11727 case RF2020: 11728 case RF3020: 11729 case RF3021: 11730 case RF3022: 11731 case RF3070: 11732 case RF3290: 11733 case RF3320: 11734 case RF3322: 11735 case RF5350: 11736 case RF5360: 11737 case RF5362: 11738 case RF5370: 11739 case RF5372: 11740 case RF5390: 11741 case RF5392: 11742 spec->num_channels = 14; 11743 if (rt2800_clk_is_20mhz(rt2x00dev)) 11744 spec->channels = rf_vals_3x_xtal20; 11745 else 11746 spec->channels = rf_vals_3x; 11747 break; 11748 11749 case RF7620: 11750 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 11751 spec->channels = rf_vals_7620; 11752 break; 11753 11754 case RF3052: 11755 case RF3053: 11756 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 11757 spec->channels = rf_vals_3x; 11758 break; 11759 11760 case RF3853: 11761 spec->num_channels = ARRAY_SIZE(rf_vals_3853); 11762 spec->channels = rf_vals_3853; 11763 break; 11764 11765 case RF5592: 11766 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 11767 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 11768 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 11769 spec->channels = rf_vals_5592_xtal40; 11770 } else { 11771 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 11772 spec->channels = rf_vals_5592_xtal20; 11773 } 11774 break; 11775 } 11776 11777 if (WARN_ON_ONCE(!spec->channels)) 11778 return -ENODEV; 11779 11780 spec->supported_bands = SUPPORT_BAND_2GHZ; 11781 if (spec->num_channels > 14) 11782 spec->supported_bands |= SUPPORT_BAND_5GHZ; 11783 11784 /* 11785 * Initialize HT information. 11786 */ 11787 if (!rt2x00_rf(rt2x00dev, RF2020)) 11788 spec->ht.ht_supported = true; 11789 else 11790 spec->ht.ht_supported = false; 11791 11792 spec->ht.cap = 11793 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 11794 IEEE80211_HT_CAP_GRN_FLD | 11795 IEEE80211_HT_CAP_SGI_20 | 11796 IEEE80211_HT_CAP_SGI_40; 11797 11798 tx_chains = rt2x00dev->default_ant.tx_chain_num; 11799 rx_chains = rt2x00dev->default_ant.rx_chain_num; 11800 11801 if (tx_chains >= 2) 11802 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 11803 11804 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 11805 11806 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 11807 spec->ht.ampdu_density = 4; 11808 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 11809 if (tx_chains != rx_chains) { 11810 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 11811 spec->ht.mcs.tx_params |= 11812 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 11813 } 11814 11815 switch (rx_chains) { 11816 case 3: 11817 spec->ht.mcs.rx_mask[2] = 0xff; 11818 fallthrough; 11819 case 2: 11820 spec->ht.mcs.rx_mask[1] = 0xff; 11821 fallthrough; 11822 case 1: 11823 spec->ht.mcs.rx_mask[0] = 0xff; 11824 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 11825 break; 11826 } 11827 11828 /* 11829 * Create channel information and survey arrays 11830 */ 11831 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 11832 if (!info) 11833 return -ENOMEM; 11834 11835 rt2x00dev->chan_survey = 11836 kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey), 11837 GFP_KERNEL); 11838 if (!rt2x00dev->chan_survey) { 11839 kfree(info); 11840 return -ENOMEM; 11841 } 11842 11843 spec->channels_info = info; 11844 11845 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 11846 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 11847 11848 if (rt2x00dev->default_ant.tx_chain_num > 2) 11849 default_power3 = rt2800_eeprom_addr(rt2x00dev, 11850 EEPROM_EXT_TXPOWER_BG3); 11851 else 11852 default_power3 = NULL; 11853 11854 for (i = 0; i < 14; i++) { 11855 info[i].default_power1 = default_power1[i]; 11856 info[i].default_power2 = default_power2[i]; 11857 if (default_power3) 11858 info[i].default_power3 = default_power3[i]; 11859 } 11860 11861 if (spec->num_channels > 14) { 11862 default_power1 = rt2800_eeprom_addr(rt2x00dev, 11863 EEPROM_TXPOWER_A1); 11864 default_power2 = rt2800_eeprom_addr(rt2x00dev, 11865 EEPROM_TXPOWER_A2); 11866 11867 if (rt2x00dev->default_ant.tx_chain_num > 2) 11868 default_power3 = 11869 rt2800_eeprom_addr(rt2x00dev, 11870 EEPROM_EXT_TXPOWER_A3); 11871 else 11872 default_power3 = NULL; 11873 11874 for (i = 14; i < spec->num_channels; i++) { 11875 info[i].default_power1 = default_power1[i - 14]; 11876 info[i].default_power2 = default_power2[i - 14]; 11877 if (default_power3) 11878 info[i].default_power3 = default_power3[i - 14]; 11879 } 11880 } 11881 11882 switch (rt2x00dev->chip.rf) { 11883 case RF2020: 11884 case RF3020: 11885 case RF3021: 11886 case RF3022: 11887 case RF3320: 11888 case RF3052: 11889 case RF3053: 11890 case RF3070: 11891 case RF3290: 11892 case RF3853: 11893 case RF5350: 11894 case RF5360: 11895 case RF5362: 11896 case RF5370: 11897 case RF5372: 11898 case RF5390: 11899 case RF5392: 11900 case RF5592: 11901 case RF7620: 11902 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 11903 break; 11904 } 11905 11906 return 0; 11907 } 11908 11909 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 11910 { 11911 u32 reg; 11912 u32 rt; 11913 u32 rev; 11914 11915 if (rt2x00_rt(rt2x00dev, RT3290)) 11916 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 11917 else 11918 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 11919 11920 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 11921 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 11922 11923 switch (rt) { 11924 case RT2860: 11925 case RT2872: 11926 case RT2883: 11927 case RT3070: 11928 case RT3071: 11929 case RT3090: 11930 case RT3290: 11931 case RT3352: 11932 case RT3390: 11933 case RT3572: 11934 case RT3593: 11935 case RT3883: 11936 case RT5350: 11937 case RT5390: 11938 case RT5392: 11939 case RT5592: 11940 break; 11941 default: 11942 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 11943 rt, rev); 11944 return -ENODEV; 11945 } 11946 11947 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 11948 rt = RT6352; 11949 11950 rt2x00_set_rt(rt2x00dev, rt, rev); 11951 11952 return 0; 11953 } 11954 11955 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 11956 { 11957 int retval; 11958 u32 reg; 11959 11960 retval = rt2800_probe_rt(rt2x00dev); 11961 if (retval) 11962 return retval; 11963 11964 /* 11965 * Allocate eeprom data. 11966 */ 11967 retval = rt2800_validate_eeprom(rt2x00dev); 11968 if (retval) 11969 return retval; 11970 11971 retval = rt2800_init_eeprom(rt2x00dev); 11972 if (retval) 11973 return retval; 11974 11975 /* 11976 * Enable rfkill polling by setting GPIO direction of the 11977 * rfkill switch GPIO pin correctly. 11978 */ 11979 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 11980 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 11981 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 11982 11983 /* 11984 * Initialize hw specifications. 11985 */ 11986 retval = rt2800_probe_hw_mode(rt2x00dev); 11987 if (retval) 11988 return retval; 11989 11990 /* 11991 * Set device capabilities. 11992 */ 11993 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 11994 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 11995 if (!rt2x00_is_usb(rt2x00dev)) 11996 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 11997 11998 /* 11999 * Set device requirements. 12000 */ 12001 if (!rt2x00_is_soc(rt2x00dev)) 12002 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 12003 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 12004 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 12005 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 12006 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 12007 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 12008 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 12009 if (rt2x00_is_usb(rt2x00dev)) 12010 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 12011 else { 12012 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 12013 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 12014 } 12015 12016 if (modparam_watchdog) { 12017 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags); 12018 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100); 12019 } else { 12020 rt2x00dev->link.watchdog_disabled = true; 12021 } 12022 12023 /* 12024 * Set the rssi offset. 12025 */ 12026 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 12027 12028 return 0; 12029 } 12030 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 12031 12032 /* 12033 * IEEE80211 stack callback functions. 12034 */ 12035 void rt2800_get_key_seq(struct ieee80211_hw *hw, 12036 struct ieee80211_key_conf *key, 12037 struct ieee80211_key_seq *seq) 12038 { 12039 struct rt2x00_dev *rt2x00dev = hw->priv; 12040 struct mac_iveiv_entry iveiv_entry; 12041 u32 offset; 12042 12043 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 12044 return; 12045 12046 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 12047 rt2800_register_multiread(rt2x00dev, offset, 12048 &iveiv_entry, sizeof(iveiv_entry)); 12049 12050 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 12051 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 12052 } 12053 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 12054 12055 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 12056 { 12057 struct rt2x00_dev *rt2x00dev = hw->priv; 12058 u32 reg; 12059 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 12060 12061 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 12062 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 12063 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 12064 12065 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 12066 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 12067 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 12068 12069 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 12070 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 12071 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 12072 12073 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 12074 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 12075 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 12076 12077 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 12078 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 12079 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 12080 12081 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 12082 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 12083 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 12084 12085 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 12086 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 12087 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 12088 12089 return 0; 12090 } 12091 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 12092 12093 int rt2800_conf_tx(struct ieee80211_hw *hw, 12094 struct ieee80211_vif *vif, 12095 unsigned int link_id, u16 queue_idx, 12096 const struct ieee80211_tx_queue_params *params) 12097 { 12098 struct rt2x00_dev *rt2x00dev = hw->priv; 12099 struct data_queue *queue; 12100 struct rt2x00_field32 field; 12101 int retval; 12102 u32 reg; 12103 u32 offset; 12104 12105 /* 12106 * First pass the configuration through rt2x00lib, that will 12107 * update the queue settings and validate the input. After that 12108 * we are free to update the registers based on the value 12109 * in the queue parameter. 12110 */ 12111 retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params); 12112 if (retval) 12113 return retval; 12114 12115 /* 12116 * We only need to perform additional register initialization 12117 * for WMM queues/ 12118 */ 12119 if (queue_idx >= 4) 12120 return 0; 12121 12122 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 12123 12124 /* Update WMM TXOP register */ 12125 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 12126 field.bit_offset = (queue_idx & 1) * 16; 12127 field.bit_mask = 0xffff << field.bit_offset; 12128 12129 reg = rt2800_register_read(rt2x00dev, offset); 12130 rt2x00_set_field32(®, field, queue->txop); 12131 rt2800_register_write(rt2x00dev, offset, reg); 12132 12133 /* Update WMM registers */ 12134 field.bit_offset = queue_idx * 4; 12135 field.bit_mask = 0xf << field.bit_offset; 12136 12137 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 12138 rt2x00_set_field32(®, field, queue->aifs); 12139 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 12140 12141 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 12142 rt2x00_set_field32(®, field, queue->cw_min); 12143 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 12144 12145 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 12146 rt2x00_set_field32(®, field, queue->cw_max); 12147 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 12148 12149 /* Update EDCA registers */ 12150 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 12151 12152 reg = rt2800_register_read(rt2x00dev, offset); 12153 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 12154 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 12155 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 12156 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 12157 rt2800_register_write(rt2x00dev, offset, reg); 12158 12159 return 0; 12160 } 12161 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 12162 12163 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 12164 { 12165 struct rt2x00_dev *rt2x00dev = hw->priv; 12166 u64 tsf; 12167 u32 reg; 12168 12169 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 12170 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 12171 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 12172 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 12173 12174 return tsf; 12175 } 12176 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 12177 12178 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 12179 struct ieee80211_ampdu_params *params) 12180 { 12181 struct ieee80211_sta *sta = params->sta; 12182 enum ieee80211_ampdu_mlme_action action = params->action; 12183 u16 tid = params->tid; 12184 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 12185 int ret = 0; 12186 12187 /* 12188 * Don't allow aggregation for stations the hardware isn't aware 12189 * of because tx status reports for frames to an unknown station 12190 * always contain wcid=WCID_END+1 and thus we can't distinguish 12191 * between multiple stations which leads to unwanted situations 12192 * when the hw reorders frames due to aggregation. 12193 */ 12194 if (sta_priv->wcid > WCID_END) 12195 return -ENOSPC; 12196 12197 switch (action) { 12198 case IEEE80211_AMPDU_RX_START: 12199 case IEEE80211_AMPDU_RX_STOP: 12200 /* 12201 * The hw itself takes care of setting up BlockAck mechanisms. 12202 * So, we only have to allow mac80211 to nagotiate a BlockAck 12203 * agreement. Once that is done, the hw will BlockAck incoming 12204 * AMPDUs without further setup. 12205 */ 12206 break; 12207 case IEEE80211_AMPDU_TX_START: 12208 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 12209 break; 12210 case IEEE80211_AMPDU_TX_STOP_CONT: 12211 case IEEE80211_AMPDU_TX_STOP_FLUSH: 12212 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 12213 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 12214 break; 12215 case IEEE80211_AMPDU_TX_OPERATIONAL: 12216 break; 12217 default: 12218 rt2x00_warn((struct rt2x00_dev *)hw->priv, 12219 "Unknown AMPDU action\n"); 12220 } 12221 12222 return ret; 12223 } 12224 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 12225 12226 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 12227 struct survey_info *survey) 12228 { 12229 struct rt2x00_dev *rt2x00dev = hw->priv; 12230 struct rt2x00_chan_survey *chan_survey = 12231 &rt2x00dev->chan_survey[idx]; 12232 enum nl80211_band band = NL80211_BAND_2GHZ; 12233 12234 if (idx >= rt2x00dev->bands[band].n_channels) { 12235 idx -= rt2x00dev->bands[band].n_channels; 12236 band = NL80211_BAND_5GHZ; 12237 } 12238 12239 if (idx >= rt2x00dev->bands[band].n_channels) 12240 return -ENOENT; 12241 12242 if (idx == 0) 12243 rt2800_update_survey(rt2x00dev); 12244 12245 survey->channel = &rt2x00dev->bands[band].channels[idx]; 12246 12247 survey->filled = SURVEY_INFO_TIME | 12248 SURVEY_INFO_TIME_BUSY | 12249 SURVEY_INFO_TIME_EXT_BUSY; 12250 12251 survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000); 12252 survey->time_busy = div_u64(chan_survey->time_busy, 1000); 12253 survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000); 12254 12255 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 12256 survey->filled |= SURVEY_INFO_IN_USE; 12257 12258 return 0; 12259 12260 } 12261 EXPORT_SYMBOL_GPL(rt2800_get_survey); 12262 12263 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 12264 MODULE_VERSION(DRV_VERSION); 12265 MODULE_DESCRIPTION("Ralink RT2800 library"); 12266 MODULE_LICENSE("GPL"); 12267