1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 7 8 Based on the original rt2800pci.c and rt2800usb.c. 9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 15 <http://rt2x00.serialmonkey.com> 16 17 */ 18 19 /* 20 Module: rt2800lib 21 Abstract: rt2800 generic device routines. 22 */ 23 24 #include <linux/crc-ccitt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "rt2x00.h" 30 #include "rt2800lib.h" 31 #include "rt2800.h" 32 33 static bool modparam_watchdog; 34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO); 35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected"); 36 37 /* 38 * Register access. 39 * All access to the CSR registers will go through the methods 40 * rt2800_register_read and rt2800_register_write. 41 * BBP and RF register require indirect register access, 42 * and use the CSR registers BBPCSR and RFCSR to achieve this. 43 * These indirect registers work with busy bits, 44 * and we will try maximal REGISTER_BUSY_COUNT times to access 45 * the register while taking a REGISTER_BUSY_DELAY us delay 46 * between each attampt. When the busy bit is still set at that time, 47 * the access attempt is considered to have failed, 48 * and we will print an error. 49 * The _lock versions must be used if you already hold the csr_mutex 50 */ 51 #define WAIT_FOR_BBP(__dev, __reg) \ 52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 53 #define WAIT_FOR_RFCSR(__dev, __reg) \ 54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 56 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 57 (__reg)) 58 #define WAIT_FOR_RF(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 60 #define WAIT_FOR_MCU(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 62 H2M_MAILBOX_CSR_OWNER, (__reg)) 63 64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 65 { 66 /* check for rt2872 on SoC */ 67 if (!rt2x00_is_soc(rt2x00dev) || 68 !rt2x00_rt(rt2x00dev, RT2872)) 69 return false; 70 71 /* we know for sure that these rf chipsets are used on rt305x boards */ 72 if (rt2x00_rf(rt2x00dev, RF3020) || 73 rt2x00_rf(rt2x00dev, RF3021) || 74 rt2x00_rf(rt2x00dev, RF3022)) 75 return true; 76 77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 78 return false; 79 } 80 81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 82 const unsigned int word, const u8 value) 83 { 84 u32 reg; 85 86 mutex_lock(&rt2x00dev->csr_mutex); 87 88 /* 89 * Wait until the BBP becomes available, afterwards we 90 * can safely write the new data into the register. 91 */ 92 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 93 reg = 0; 94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 99 100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 101 } 102 103 mutex_unlock(&rt2x00dev->csr_mutex); 104 } 105 106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 107 { 108 u32 reg; 109 u8 value; 110 111 mutex_lock(&rt2x00dev->csr_mutex); 112 113 /* 114 * Wait until the BBP becomes available, afterwards we 115 * can safely write the read request into the register. 116 * After the data has been written, we wait until hardware 117 * returns the correct value, if at any time the register 118 * doesn't become available in time, reg will be 0xffffffff 119 * which means we return 0xff to the caller. 120 */ 121 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 122 reg = 0; 123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 127 128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 129 130 WAIT_FOR_BBP(rt2x00dev, ®); 131 } 132 133 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 134 135 mutex_unlock(&rt2x00dev->csr_mutex); 136 137 return value; 138 } 139 140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 141 const unsigned int word, const u8 value) 142 { 143 u32 reg; 144 145 mutex_lock(&rt2x00dev->csr_mutex); 146 147 /* 148 * Wait until the RFCSR becomes available, afterwards we 149 * can safely write the new data into the register. 150 */ 151 switch (rt2x00dev->chip.rt) { 152 case RT6352: 153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 157 word); 158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 160 161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 162 } 163 break; 164 165 default: 166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 167 reg = 0; 168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 172 173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 174 } 175 break; 176 } 177 178 mutex_unlock(&rt2x00dev->csr_mutex); 179 } 180 181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 182 const unsigned int reg, const u8 value) 183 { 184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 185 } 186 187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 188 const unsigned int reg, const u8 value) 189 { 190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 192 } 193 194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 199 } 200 201 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 202 const u8 reg, const u8 value) 203 { 204 rt2800_bbp_write(rt2x00dev, 158, reg); 205 rt2800_bbp_write(rt2x00dev, 159, value); 206 } 207 208 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 209 { 210 rt2800_bbp_write(rt2x00dev, 158, reg); 211 return rt2800_bbp_read(rt2x00dev, 159); 212 } 213 214 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 215 const u8 reg, const u8 value) 216 { 217 rt2800_bbp_write(rt2x00dev, 195, reg); 218 rt2800_bbp_write(rt2x00dev, 196, value); 219 } 220 221 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 222 const unsigned int word) 223 { 224 u32 reg; 225 u8 value; 226 227 mutex_lock(&rt2x00dev->csr_mutex); 228 229 /* 230 * Wait until the RFCSR becomes available, afterwards we 231 * can safely write the read request into the register. 232 * After the data has been written, we wait until hardware 233 * returns the correct value, if at any time the register 234 * doesn't become available in time, reg will be 0xffffffff 235 * which means we return 0xff to the caller. 236 */ 237 switch (rt2x00dev->chip.rt) { 238 case RT6352: 239 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 240 reg = 0; 241 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 242 word); 243 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 244 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 245 246 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 247 248 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 249 } 250 251 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 252 break; 253 254 default: 255 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 256 reg = 0; 257 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 258 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 259 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 260 261 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 262 263 WAIT_FOR_RFCSR(rt2x00dev, ®); 264 } 265 266 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 267 break; 268 } 269 270 mutex_unlock(&rt2x00dev->csr_mutex); 271 272 return value; 273 } 274 275 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 276 const unsigned int reg) 277 { 278 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 279 } 280 281 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 282 const unsigned int word, const u32 value) 283 { 284 u32 reg; 285 286 mutex_lock(&rt2x00dev->csr_mutex); 287 288 /* 289 * Wait until the RF becomes available, afterwards we 290 * can safely write the new data into the register. 291 */ 292 if (WAIT_FOR_RF(rt2x00dev, ®)) { 293 reg = 0; 294 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 295 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 296 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 297 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 298 299 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 300 rt2x00_rf_write(rt2x00dev, word, value); 301 } 302 303 mutex_unlock(&rt2x00dev->csr_mutex); 304 } 305 306 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 307 [EEPROM_CHIP_ID] = 0x0000, 308 [EEPROM_VERSION] = 0x0001, 309 [EEPROM_MAC_ADDR_0] = 0x0002, 310 [EEPROM_MAC_ADDR_1] = 0x0003, 311 [EEPROM_MAC_ADDR_2] = 0x0004, 312 [EEPROM_NIC_CONF0] = 0x001a, 313 [EEPROM_NIC_CONF1] = 0x001b, 314 [EEPROM_FREQ] = 0x001d, 315 [EEPROM_LED_AG_CONF] = 0x001e, 316 [EEPROM_LED_ACT_CONF] = 0x001f, 317 [EEPROM_LED_POLARITY] = 0x0020, 318 [EEPROM_NIC_CONF2] = 0x0021, 319 [EEPROM_LNA] = 0x0022, 320 [EEPROM_RSSI_BG] = 0x0023, 321 [EEPROM_RSSI_BG2] = 0x0024, 322 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 323 [EEPROM_RSSI_A] = 0x0025, 324 [EEPROM_RSSI_A2] = 0x0026, 325 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 326 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 327 [EEPROM_TXPOWER_DELTA] = 0x0028, 328 [EEPROM_TXPOWER_BG1] = 0x0029, 329 [EEPROM_TXPOWER_BG2] = 0x0030, 330 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 331 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 332 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 333 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 334 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 335 [EEPROM_TXPOWER_A1] = 0x003c, 336 [EEPROM_TXPOWER_A2] = 0x0053, 337 [EEPROM_TXPOWER_INIT] = 0x0068, 338 [EEPROM_TSSI_BOUND_A1] = 0x006a, 339 [EEPROM_TSSI_BOUND_A2] = 0x006b, 340 [EEPROM_TSSI_BOUND_A3] = 0x006c, 341 [EEPROM_TSSI_BOUND_A4] = 0x006d, 342 [EEPROM_TSSI_BOUND_A5] = 0x006e, 343 [EEPROM_TXPOWER_BYRATE] = 0x006f, 344 [EEPROM_BBP_START] = 0x0078, 345 }; 346 347 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 348 [EEPROM_CHIP_ID] = 0x0000, 349 [EEPROM_VERSION] = 0x0001, 350 [EEPROM_MAC_ADDR_0] = 0x0002, 351 [EEPROM_MAC_ADDR_1] = 0x0003, 352 [EEPROM_MAC_ADDR_2] = 0x0004, 353 [EEPROM_NIC_CONF0] = 0x001a, 354 [EEPROM_NIC_CONF1] = 0x001b, 355 [EEPROM_NIC_CONF2] = 0x001c, 356 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 357 [EEPROM_FREQ] = 0x0022, 358 [EEPROM_LED_AG_CONF] = 0x0023, 359 [EEPROM_LED_ACT_CONF] = 0x0024, 360 [EEPROM_LED_POLARITY] = 0x0025, 361 [EEPROM_LNA] = 0x0026, 362 [EEPROM_EXT_LNA2] = 0x0027, 363 [EEPROM_RSSI_BG] = 0x0028, 364 [EEPROM_RSSI_BG2] = 0x0029, 365 [EEPROM_RSSI_A] = 0x002a, 366 [EEPROM_RSSI_A2] = 0x002b, 367 [EEPROM_TXPOWER_BG1] = 0x0030, 368 [EEPROM_TXPOWER_BG2] = 0x0037, 369 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 370 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 371 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 372 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 373 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 374 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 375 [EEPROM_TXPOWER_A1] = 0x004b, 376 [EEPROM_TXPOWER_A2] = 0x0065, 377 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 378 [EEPROM_TSSI_BOUND_A1] = 0x009a, 379 [EEPROM_TSSI_BOUND_A2] = 0x009b, 380 [EEPROM_TSSI_BOUND_A3] = 0x009c, 381 [EEPROM_TSSI_BOUND_A4] = 0x009d, 382 [EEPROM_TSSI_BOUND_A5] = 0x009e, 383 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 384 }; 385 386 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 387 const enum rt2800_eeprom_word word) 388 { 389 const unsigned int *map; 390 unsigned int index; 391 392 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 393 "%s: invalid EEPROM word %d\n", 394 wiphy_name(rt2x00dev->hw->wiphy), word)) 395 return 0; 396 397 if (rt2x00_rt(rt2x00dev, RT3593) || 398 rt2x00_rt(rt2x00dev, RT3883)) 399 map = rt2800_eeprom_map_ext; 400 else 401 map = rt2800_eeprom_map; 402 403 index = map[word]; 404 405 /* Index 0 is valid only for EEPROM_CHIP_ID. 406 * Otherwise it means that the offset of the 407 * given word is not initialized in the map, 408 * or that the field is not usable on the 409 * actual chipset. 410 */ 411 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 412 "%s: invalid access of EEPROM word %d\n", 413 wiphy_name(rt2x00dev->hw->wiphy), word); 414 415 return index; 416 } 417 418 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 419 const enum rt2800_eeprom_word word) 420 { 421 unsigned int index; 422 423 index = rt2800_eeprom_word_index(rt2x00dev, word); 424 return rt2x00_eeprom_addr(rt2x00dev, index); 425 } 426 427 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 428 const enum rt2800_eeprom_word word) 429 { 430 unsigned int index; 431 432 index = rt2800_eeprom_word_index(rt2x00dev, word); 433 return rt2x00_eeprom_read(rt2x00dev, index); 434 } 435 436 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 437 const enum rt2800_eeprom_word word, u16 data) 438 { 439 unsigned int index; 440 441 index = rt2800_eeprom_word_index(rt2x00dev, word); 442 rt2x00_eeprom_write(rt2x00dev, index, data); 443 } 444 445 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 446 const enum rt2800_eeprom_word array, 447 unsigned int offset) 448 { 449 unsigned int index; 450 451 index = rt2800_eeprom_word_index(rt2x00dev, array); 452 return rt2x00_eeprom_read(rt2x00dev, index + offset); 453 } 454 455 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 456 { 457 u32 reg; 458 int i, count; 459 460 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 461 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 462 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 463 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 464 rt2x00_set_field32(®, WLAN_EN, 1); 465 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 466 467 udelay(REGISTER_BUSY_DELAY); 468 469 count = 0; 470 do { 471 /* 472 * Check PLL_LD & XTAL_RDY. 473 */ 474 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 475 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 476 if (rt2x00_get_field32(reg, PLL_LD) && 477 rt2x00_get_field32(reg, XTAL_RDY)) 478 break; 479 udelay(REGISTER_BUSY_DELAY); 480 } 481 482 if (i >= REGISTER_BUSY_COUNT) { 483 484 if (count >= 10) 485 return -EIO; 486 487 rt2800_register_write(rt2x00dev, 0x58, 0x018); 488 udelay(REGISTER_BUSY_DELAY); 489 rt2800_register_write(rt2x00dev, 0x58, 0x418); 490 udelay(REGISTER_BUSY_DELAY); 491 rt2800_register_write(rt2x00dev, 0x58, 0x618); 492 udelay(REGISTER_BUSY_DELAY); 493 count++; 494 } else { 495 count = 0; 496 } 497 498 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 499 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 500 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 501 rt2x00_set_field32(®, WLAN_RESET, 1); 502 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 503 udelay(10); 504 rt2x00_set_field32(®, WLAN_RESET, 0); 505 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 506 udelay(10); 507 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 508 } while (count != 0); 509 510 return 0; 511 } 512 513 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 514 const u8 command, const u8 token, 515 const u8 arg0, const u8 arg1) 516 { 517 u32 reg; 518 519 /* 520 * SOC devices don't support MCU requests. 521 */ 522 if (rt2x00_is_soc(rt2x00dev)) 523 return; 524 525 mutex_lock(&rt2x00dev->csr_mutex); 526 527 /* 528 * Wait until the MCU becomes available, afterwards we 529 * can safely write the new data into the register. 530 */ 531 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 532 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 533 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 534 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 535 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 536 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 537 538 reg = 0; 539 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 540 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 541 } 542 543 mutex_unlock(&rt2x00dev->csr_mutex); 544 } 545 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 546 547 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 548 { 549 unsigned int i = 0; 550 u32 reg; 551 552 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 553 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 554 if (reg && reg != ~0) 555 return 0; 556 msleep(1); 557 } 558 559 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 560 return -EBUSY; 561 } 562 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 563 564 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 565 { 566 unsigned int i; 567 u32 reg; 568 569 /* 570 * Some devices are really slow to respond here. Wait a whole second 571 * before timing out. 572 */ 573 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 574 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 575 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 576 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 577 return 0; 578 579 msleep(10); 580 } 581 582 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 583 return -EACCES; 584 } 585 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 586 587 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 588 { 589 u32 reg; 590 591 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 592 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 593 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 594 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 595 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 596 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 597 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 598 } 599 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 600 601 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 602 unsigned short *txwi_size, 603 unsigned short *rxwi_size) 604 { 605 switch (rt2x00dev->chip.rt) { 606 case RT3593: 607 case RT3883: 608 *txwi_size = TXWI_DESC_SIZE_4WORDS; 609 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 610 break; 611 612 case RT5592: 613 case RT6352: 614 *txwi_size = TXWI_DESC_SIZE_5WORDS; 615 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 616 break; 617 618 default: 619 *txwi_size = TXWI_DESC_SIZE_4WORDS; 620 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 621 break; 622 } 623 } 624 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 625 626 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 627 { 628 u16 fw_crc; 629 u16 crc; 630 631 /* 632 * The last 2 bytes in the firmware array are the crc checksum itself, 633 * this means that we should never pass those 2 bytes to the crc 634 * algorithm. 635 */ 636 fw_crc = (data[len - 2] << 8 | data[len - 1]); 637 638 /* 639 * Use the crc ccitt algorithm. 640 * This will return the same value as the legacy driver which 641 * used bit ordering reversion on the both the firmware bytes 642 * before input input as well as on the final output. 643 * Obviously using crc ccitt directly is much more efficient. 644 */ 645 crc = crc_ccitt(~0, data, len - 2); 646 647 /* 648 * There is a small difference between the crc-itu-t + bitrev and 649 * the crc-ccitt crc calculation. In the latter method the 2 bytes 650 * will be swapped, use swab16 to convert the crc to the correct 651 * value. 652 */ 653 crc = swab16(crc); 654 655 return fw_crc == crc; 656 } 657 658 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 659 const u8 *data, const size_t len) 660 { 661 size_t offset = 0; 662 size_t fw_len; 663 bool multiple; 664 665 /* 666 * PCI(e) & SOC devices require firmware with a length 667 * of 8kb. USB devices require firmware files with a length 668 * of 4kb. Certain USB chipsets however require different firmware, 669 * which Ralink only provides attached to the original firmware 670 * file. Thus for USB devices, firmware files have a length 671 * which is a multiple of 4kb. The firmware for rt3290 chip also 672 * have a length which is a multiple of 4kb. 673 */ 674 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 675 fw_len = 4096; 676 else 677 fw_len = 8192; 678 679 multiple = true; 680 /* 681 * Validate the firmware length 682 */ 683 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 684 return FW_BAD_LENGTH; 685 686 /* 687 * Check if the chipset requires one of the upper parts 688 * of the firmware. 689 */ 690 if (rt2x00_is_usb(rt2x00dev) && 691 !rt2x00_rt(rt2x00dev, RT2860) && 692 !rt2x00_rt(rt2x00dev, RT2872) && 693 !rt2x00_rt(rt2x00dev, RT3070) && 694 ((len / fw_len) == 1)) 695 return FW_BAD_VERSION; 696 697 /* 698 * 8kb firmware files must be checked as if it were 699 * 2 separate firmware files. 700 */ 701 while (offset < len) { 702 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 703 return FW_BAD_CRC; 704 705 offset += fw_len; 706 } 707 708 return FW_OK; 709 } 710 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 711 712 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 713 const u8 *data, const size_t len) 714 { 715 unsigned int i; 716 u32 reg; 717 int retval; 718 719 if (rt2x00_rt(rt2x00dev, RT3290)) { 720 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 721 if (retval) 722 return -EBUSY; 723 } 724 725 /* 726 * If driver doesn't wake up firmware here, 727 * rt2800_load_firmware will hang forever when interface is up again. 728 */ 729 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 730 731 /* 732 * Wait for stable hardware. 733 */ 734 if (rt2800_wait_csr_ready(rt2x00dev)) 735 return -EBUSY; 736 737 if (rt2x00_is_pci(rt2x00dev)) { 738 if (rt2x00_rt(rt2x00dev, RT3290) || 739 rt2x00_rt(rt2x00dev, RT3572) || 740 rt2x00_rt(rt2x00dev, RT5390) || 741 rt2x00_rt(rt2x00dev, RT5392)) { 742 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 743 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 744 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 745 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 746 } 747 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 748 } 749 750 rt2800_disable_wpdma(rt2x00dev); 751 752 /* 753 * Write firmware to the device. 754 */ 755 rt2800_drv_write_firmware(rt2x00dev, data, len); 756 757 /* 758 * Wait for device to stabilize. 759 */ 760 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 761 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 762 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 763 break; 764 msleep(1); 765 } 766 767 if (i == REGISTER_BUSY_COUNT) { 768 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 769 return -EBUSY; 770 } 771 772 /* 773 * Disable DMA, will be reenabled later when enabling 774 * the radio. 775 */ 776 rt2800_disable_wpdma(rt2x00dev); 777 778 /* 779 * Initialize firmware. 780 */ 781 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 782 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 783 if (rt2x00_is_usb(rt2x00dev)) { 784 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 785 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 786 } 787 msleep(1); 788 789 return 0; 790 } 791 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 792 793 void rt2800_write_tx_data(struct queue_entry *entry, 794 struct txentry_desc *txdesc) 795 { 796 __le32 *txwi = rt2800_drv_get_txwi(entry); 797 u32 word; 798 int i; 799 800 /* 801 * Initialize TX Info descriptor 802 */ 803 word = rt2x00_desc_read(txwi, 0); 804 rt2x00_set_field32(&word, TXWI_W0_FRAG, 805 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 807 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 808 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 809 rt2x00_set_field32(&word, TXWI_W0_TS, 810 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 811 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 812 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 814 txdesc->u.ht.mpdu_density); 815 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 816 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 817 rt2x00_set_field32(&word, TXWI_W0_BW, 818 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 819 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 820 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 821 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 822 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 823 rt2x00_desc_write(txwi, 0, word); 824 825 word = rt2x00_desc_read(txwi, 1); 826 rt2x00_set_field32(&word, TXWI_W1_ACK, 827 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 828 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 829 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 830 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 831 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 832 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 833 txdesc->key_idx : txdesc->u.ht.wcid); 834 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 835 txdesc->length); 836 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 837 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 838 rt2x00_desc_write(txwi, 1, word); 839 840 /* 841 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 842 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 843 * When TXD_W3_WIV is set to 1 it will use the IV data 844 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 845 * crypto entry in the registers should be used to encrypt the frame. 846 * 847 * Nulify all remaining words as well, we don't know how to program them. 848 */ 849 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 850 _rt2x00_desc_write(txwi, i, 0); 851 } 852 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 853 854 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 855 { 856 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 857 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 858 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 859 s8 base_val = rt2x00_rt(rt2x00dev, RT6352) ? -2 : -12; 860 u16 eeprom; 861 u8 offset0; 862 u8 offset1; 863 u8 offset2; 864 865 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 866 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 867 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 868 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 869 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 870 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 871 } else { 872 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 873 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 874 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 875 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 876 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 877 } 878 879 /* 880 * Convert the value from the descriptor into the RSSI value 881 * If the value in the descriptor is 0, it is considered invalid 882 * and the default (extremely low) rssi value is assumed 883 */ 884 rssi0 = (rssi0) ? (base_val - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 885 rssi1 = (rssi1) ? (base_val - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 886 rssi2 = (rssi2) ? (base_val - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 887 888 /* 889 * mac80211 only accepts a single RSSI value. Calculating the 890 * average doesn't deliver a fair answer either since -60:-60 would 891 * be considered equally good as -50:-70 while the second is the one 892 * which gives less energy... 893 */ 894 rssi0 = max(rssi0, rssi1); 895 return (int)max(rssi0, rssi2); 896 } 897 898 void rt2800_process_rxwi(struct queue_entry *entry, 899 struct rxdone_entry_desc *rxdesc) 900 { 901 __le32 *rxwi = (__le32 *) entry->skb->data; 902 u32 word; 903 904 word = rt2x00_desc_read(rxwi, 0); 905 906 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 907 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 908 909 word = rt2x00_desc_read(rxwi, 1); 910 911 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 912 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 913 914 if (rt2x00_get_field32(word, RXWI_W1_BW)) 915 rxdesc->bw = RATE_INFO_BW_40; 916 917 /* 918 * Detect RX rate, always use MCS as signal type. 919 */ 920 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 921 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 922 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 923 924 /* 925 * Mask of 0x8 bit to remove the short preamble flag. 926 */ 927 if (rxdesc->rate_mode == RATE_MODE_CCK) 928 rxdesc->signal &= ~0x8; 929 930 word = rt2x00_desc_read(rxwi, 2); 931 932 /* 933 * Convert descriptor AGC value to RSSI value. 934 */ 935 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 936 /* 937 * Remove RXWI descriptor from start of the buffer. 938 */ 939 skb_pull(entry->skb, entry->queue->winfo_size); 940 } 941 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 942 943 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 944 u32 status, enum nl80211_band band) 945 { 946 u8 flags = 0; 947 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 948 949 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 950 case RATE_MODE_HT_GREENFIELD: 951 flags |= IEEE80211_TX_RC_GREEN_FIELD; 952 fallthrough; 953 case RATE_MODE_HT_MIX: 954 flags |= IEEE80211_TX_RC_MCS; 955 break; 956 case RATE_MODE_OFDM: 957 if (band == NL80211_BAND_2GHZ) 958 idx += 4; 959 break; 960 case RATE_MODE_CCK: 961 if (idx >= 8) 962 idx -= 8; 963 break; 964 } 965 966 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 967 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 968 969 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 970 flags |= IEEE80211_TX_RC_SHORT_GI; 971 972 skbdesc->tx_rate_idx = idx; 973 skbdesc->tx_rate_flags = flags; 974 } 975 976 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 977 { 978 __le32 *txwi; 979 u32 word; 980 int wcid, ack, pid; 981 int tx_wcid, tx_ack, tx_pid, is_agg; 982 983 /* 984 * This frames has returned with an IO error, 985 * so the status report is not intended for this 986 * frame. 987 */ 988 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 989 return false; 990 991 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 992 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 993 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 994 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 995 996 /* 997 * Validate if this TX status report is intended for 998 * this entry by comparing the WCID/ACK/PID fields. 999 */ 1000 txwi = rt2800_drv_get_txwi(entry); 1001 1002 word = rt2x00_desc_read(txwi, 1); 1003 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 1004 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 1005 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 1006 1007 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 1008 rt2x00_dbg(entry->queue->rt2x00dev, 1009 "TX status report missed for queue %d entry %d\n", 1010 entry->queue->qid, entry->entry_idx); 1011 return false; 1012 } 1013 1014 return true; 1015 } 1016 1017 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 1018 bool match) 1019 { 1020 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1021 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1022 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1023 struct txdone_entry_desc txdesc; 1024 u32 word; 1025 u16 mcs, real_mcs; 1026 int aggr, ampdu, wcid, ack_req; 1027 1028 /* 1029 * Obtain the status about this packet. 1030 */ 1031 txdesc.flags = 0; 1032 word = rt2x00_desc_read(txwi, 0); 1033 1034 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1035 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1036 1037 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1038 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1039 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1040 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1041 1042 /* 1043 * If a frame was meant to be sent as a single non-aggregated MPDU 1044 * but ended up in an aggregate the used tx rate doesn't correlate 1045 * with the one specified in the TXWI as the whole aggregate is sent 1046 * with the same rate. 1047 * 1048 * For example: two frames are sent to rt2x00, the first one sets 1049 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1050 * and requests MCS15. If the hw aggregates both frames into one 1051 * AMDPU the tx status for both frames will contain MCS7 although 1052 * the frame was sent successfully. 1053 * 1054 * Hence, replace the requested rate with the real tx rate to not 1055 * confuse the rate control algortihm by providing clearly wrong 1056 * data. 1057 * 1058 * FIXME: if we do not find matching entry, we tell that frame was 1059 * posted without any retries. We need to find a way to fix that 1060 * and provide retry count. 1061 */ 1062 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1063 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1064 mcs = real_mcs; 1065 } 1066 1067 if (aggr == 1 || ampdu == 1) 1068 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1069 1070 if (!ack_req) 1071 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1072 1073 /* 1074 * Ralink has a retry mechanism using a global fallback 1075 * table. We setup this fallback table to try the immediate 1076 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1077 * always contains the MCS used for the last transmission, be 1078 * it successful or not. 1079 */ 1080 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1081 /* 1082 * Transmission succeeded. The number of retries is 1083 * mcs - real_mcs 1084 */ 1085 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1086 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1087 } else { 1088 /* 1089 * Transmission failed. The number of retries is 1090 * always 7 in this case (for a total number of 8 1091 * frames sent). 1092 */ 1093 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1094 txdesc.retry = rt2x00dev->long_retry; 1095 } 1096 1097 /* 1098 * the frame was retried at least once 1099 * -> hw used fallback rates 1100 */ 1101 if (txdesc.retry) 1102 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1103 1104 if (!match) { 1105 /* RCU assures non-null sta will not be freed by mac80211. */ 1106 rcu_read_lock(); 1107 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1108 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1109 else 1110 skbdesc->sta = NULL; 1111 rt2x00lib_txdone_nomatch(entry, &txdesc); 1112 rcu_read_unlock(); 1113 } else { 1114 rt2x00lib_txdone(entry, &txdesc); 1115 } 1116 } 1117 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1118 1119 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1120 { 1121 struct data_queue *queue; 1122 struct queue_entry *entry; 1123 u32 reg; 1124 u8 qid; 1125 bool match; 1126 1127 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1128 /* 1129 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1130 * guaranteed to be one of the TX QIDs . 1131 */ 1132 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1133 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1134 1135 if (unlikely(rt2x00queue_empty(queue))) { 1136 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1137 qid); 1138 break; 1139 } 1140 1141 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1142 1143 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1144 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1145 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1146 entry->entry_idx, qid); 1147 break; 1148 } 1149 1150 match = rt2800_txdone_entry_check(entry, reg); 1151 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1152 } 1153 } 1154 EXPORT_SYMBOL_GPL(rt2800_txdone); 1155 1156 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1157 struct queue_entry *entry) 1158 { 1159 bool ret; 1160 unsigned long tout; 1161 1162 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1163 return false; 1164 1165 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1166 tout = msecs_to_jiffies(50); 1167 else 1168 tout = msecs_to_jiffies(2000); 1169 1170 ret = time_after(jiffies, entry->last_action + tout); 1171 if (unlikely(ret)) 1172 rt2x00_dbg(entry->queue->rt2x00dev, 1173 "TX status timeout for entry %d in queue %d\n", 1174 entry->entry_idx, entry->queue->qid); 1175 return ret; 1176 } 1177 1178 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1179 { 1180 struct data_queue *queue; 1181 struct queue_entry *entry; 1182 1183 tx_queue_for_each(rt2x00dev, queue) { 1184 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1185 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1186 return true; 1187 } 1188 1189 return false; 1190 } 1191 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1192 1193 /* 1194 * test if there is an entry in any TX queue for which DMA is done 1195 * but the TX status has not been returned yet 1196 */ 1197 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1198 { 1199 struct data_queue *queue; 1200 1201 tx_queue_for_each(rt2x00dev, queue) { 1202 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1203 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1204 return true; 1205 } 1206 return false; 1207 } 1208 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1209 1210 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1211 { 1212 struct data_queue *queue; 1213 struct queue_entry *entry; 1214 1215 /* 1216 * Process any trailing TX status reports for IO failures, 1217 * we loop until we find the first non-IO error entry. This 1218 * can either be a frame which is free, is being uploaded, 1219 * or has completed the upload but didn't have an entry 1220 * in the TX_STAT_FIFO register yet. 1221 */ 1222 tx_queue_for_each(rt2x00dev, queue) { 1223 while (!rt2x00queue_empty(queue)) { 1224 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1225 1226 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1227 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1228 break; 1229 1230 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1231 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1232 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1233 else 1234 break; 1235 } 1236 } 1237 } 1238 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1239 1240 static int rt2800_check_hung(struct data_queue *queue) 1241 { 1242 unsigned int cur_idx = rt2800_drv_get_dma_done(queue); 1243 1244 if (queue->wd_idx != cur_idx) 1245 queue->wd_count = 0; 1246 else 1247 queue->wd_count++; 1248 1249 return queue->wd_count > 16; 1250 } 1251 1252 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev) 1253 { 1254 struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan; 1255 struct rt2x00_chan_survey *chan_survey = 1256 &rt2x00dev->chan_survey[chan->hw_value]; 1257 1258 chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA); 1259 chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA); 1260 chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 1261 } 1262 1263 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev) 1264 { 1265 struct data_queue *queue; 1266 bool hung_tx = false; 1267 bool hung_rx = false; 1268 1269 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) 1270 return; 1271 1272 rt2800_update_survey(rt2x00dev); 1273 1274 queue_for_each(rt2x00dev, queue) { 1275 switch (queue->qid) { 1276 case QID_AC_VO: 1277 case QID_AC_VI: 1278 case QID_AC_BE: 1279 case QID_AC_BK: 1280 case QID_MGMT: 1281 if (rt2x00queue_empty(queue)) 1282 continue; 1283 hung_tx = rt2800_check_hung(queue); 1284 break; 1285 case QID_RX: 1286 /* For station mode we should reactive at least 1287 * beacons. TODO: need to find good way detect 1288 * RX hung for AP mode. 1289 */ 1290 if (rt2x00dev->intf_sta_count == 0) 1291 continue; 1292 hung_rx = rt2800_check_hung(queue); 1293 break; 1294 default: 1295 break; 1296 } 1297 } 1298 1299 if (hung_tx) 1300 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n"); 1301 1302 if (hung_rx) 1303 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n"); 1304 1305 if (hung_tx || hung_rx) 1306 ieee80211_restart_hw(rt2x00dev->hw); 1307 } 1308 EXPORT_SYMBOL_GPL(rt2800_watchdog); 1309 1310 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1311 unsigned int index) 1312 { 1313 return HW_BEACON_BASE(index); 1314 } 1315 1316 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1317 unsigned int index) 1318 { 1319 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1320 } 1321 1322 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1323 { 1324 struct data_queue *queue = rt2x00dev->bcn; 1325 struct queue_entry *entry; 1326 int i, bcn_num = 0; 1327 u64 off, reg = 0; 1328 u32 bssid_dw1; 1329 1330 /* 1331 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1332 */ 1333 for (i = 0; i < queue->limit; i++) { 1334 entry = &queue->entries[i]; 1335 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1336 continue; 1337 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1338 reg |= off << (8 * bcn_num); 1339 bcn_num++; 1340 } 1341 1342 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1343 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1344 1345 /* 1346 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1347 */ 1348 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1349 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1350 bcn_num > 0 ? bcn_num - 1 : 0); 1351 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1352 } 1353 1354 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1355 { 1356 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1357 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1358 unsigned int beacon_base; 1359 unsigned int padding_len; 1360 u32 orig_reg, reg; 1361 const int txwi_desc_size = entry->queue->winfo_size; 1362 1363 /* 1364 * Disable beaconing while we are reloading the beacon data, 1365 * otherwise we might be sending out invalid data. 1366 */ 1367 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1368 orig_reg = reg; 1369 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1370 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1371 1372 /* 1373 * Add space for the TXWI in front of the skb. 1374 */ 1375 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1376 1377 /* 1378 * Register descriptor details in skb frame descriptor. 1379 */ 1380 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1381 skbdesc->desc = entry->skb->data; 1382 skbdesc->desc_len = txwi_desc_size; 1383 1384 /* 1385 * Add the TXWI for the beacon to the skb. 1386 */ 1387 rt2800_write_tx_data(entry, txdesc); 1388 1389 /* 1390 * Dump beacon to userspace through debugfs. 1391 */ 1392 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1393 1394 /* 1395 * Write entire beacon with TXWI and padding to register. 1396 */ 1397 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1398 if (padding_len && skb_pad(entry->skb, padding_len)) { 1399 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1400 /* skb freed by skb_pad() on failure */ 1401 entry->skb = NULL; 1402 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1403 return; 1404 } 1405 1406 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1407 1408 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1409 entry->skb->len + padding_len); 1410 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1411 1412 /* 1413 * Change global beacons settings. 1414 */ 1415 rt2800_update_beacons_setup(rt2x00dev); 1416 1417 /* 1418 * Restore beaconing state. 1419 */ 1420 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1421 1422 /* 1423 * Clean up beacon skb. 1424 */ 1425 dev_kfree_skb_any(entry->skb); 1426 entry->skb = NULL; 1427 } 1428 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1429 1430 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1431 unsigned int index) 1432 { 1433 int i; 1434 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1435 unsigned int beacon_base; 1436 1437 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1438 1439 /* 1440 * For the Beacon base registers we only need to clear 1441 * the whole TXWI which (when set to 0) will invalidate 1442 * the entire beacon. 1443 */ 1444 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1445 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1446 } 1447 1448 void rt2800_clear_beacon(struct queue_entry *entry) 1449 { 1450 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1451 u32 orig_reg, reg; 1452 1453 /* 1454 * Disable beaconing while we are reloading the beacon data, 1455 * otherwise we might be sending out invalid data. 1456 */ 1457 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1458 reg = orig_reg; 1459 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1460 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1461 1462 /* 1463 * Clear beacon. 1464 */ 1465 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1466 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1467 1468 /* 1469 * Change global beacons settings. 1470 */ 1471 rt2800_update_beacons_setup(rt2x00dev); 1472 /* 1473 * Restore beaconing state. 1474 */ 1475 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1476 } 1477 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1478 1479 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1480 const struct rt2x00debug rt2800_rt2x00debug = { 1481 .owner = THIS_MODULE, 1482 .csr = { 1483 .read = rt2800_register_read, 1484 .write = rt2800_register_write, 1485 .flags = RT2X00DEBUGFS_OFFSET, 1486 .word_base = CSR_REG_BASE, 1487 .word_size = sizeof(u32), 1488 .word_count = CSR_REG_SIZE / sizeof(u32), 1489 }, 1490 .eeprom = { 1491 /* NOTE: The local EEPROM access functions can't 1492 * be used here, use the generic versions instead. 1493 */ 1494 .read = rt2x00_eeprom_read, 1495 .write = rt2x00_eeprom_write, 1496 .word_base = EEPROM_BASE, 1497 .word_size = sizeof(u16), 1498 .word_count = EEPROM_SIZE / sizeof(u16), 1499 }, 1500 .bbp = { 1501 .read = rt2800_bbp_read, 1502 .write = rt2800_bbp_write, 1503 .word_base = BBP_BASE, 1504 .word_size = sizeof(u8), 1505 .word_count = BBP_SIZE / sizeof(u8), 1506 }, 1507 .rf = { 1508 .read = rt2x00_rf_read, 1509 .write = rt2800_rf_write, 1510 .word_base = RF_BASE, 1511 .word_size = sizeof(u32), 1512 .word_count = RF_SIZE / sizeof(u32), 1513 }, 1514 .rfcsr = { 1515 .read = rt2800_rfcsr_read, 1516 .write = rt2800_rfcsr_write, 1517 .word_base = RFCSR_BASE, 1518 .word_size = sizeof(u8), 1519 .word_count = RFCSR_SIZE / sizeof(u8), 1520 }, 1521 }; 1522 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1523 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1524 1525 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1526 { 1527 u32 reg; 1528 1529 if (rt2x00_rt(rt2x00dev, RT3290)) { 1530 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1531 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1532 } else { 1533 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1534 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1535 } 1536 } 1537 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1538 1539 #ifdef CONFIG_RT2X00_LIB_LEDS 1540 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1541 enum led_brightness brightness) 1542 { 1543 struct rt2x00_led *led = 1544 container_of(led_cdev, struct rt2x00_led, led_dev); 1545 unsigned int enabled = brightness != LED_OFF; 1546 unsigned int bg_mode = 1547 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1548 unsigned int polarity = 1549 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1550 EEPROM_FREQ_LED_POLARITY); 1551 unsigned int ledmode = 1552 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1553 EEPROM_FREQ_LED_MODE); 1554 u32 reg; 1555 1556 /* Check for SoC (SOC devices don't support MCU requests) */ 1557 if (rt2x00_is_soc(led->rt2x00dev)) { 1558 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1559 1560 /* Set LED Polarity */ 1561 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1562 1563 /* Set LED Mode */ 1564 if (led->type == LED_TYPE_RADIO) { 1565 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1566 enabled ? 3 : 0); 1567 } else if (led->type == LED_TYPE_ASSOC) { 1568 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1569 enabled ? 3 : 0); 1570 } else if (led->type == LED_TYPE_QUALITY) { 1571 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1572 enabled ? 3 : 0); 1573 } 1574 1575 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1576 1577 } else { 1578 if (led->type == LED_TYPE_RADIO) { 1579 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1580 enabled ? 0x20 : 0); 1581 } else if (led->type == LED_TYPE_ASSOC) { 1582 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1583 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1584 } else if (led->type == LED_TYPE_QUALITY) { 1585 /* 1586 * The brightness is divided into 6 levels (0 - 5), 1587 * The specs tell us the following levels: 1588 * 0, 1 ,3, 7, 15, 31 1589 * to determine the level in a simple way we can simply 1590 * work with bitshifting: 1591 * (1 << level) - 1 1592 */ 1593 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1594 (1 << brightness / (LED_FULL / 6)) - 1, 1595 polarity); 1596 } 1597 } 1598 } 1599 1600 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1601 struct rt2x00_led *led, enum led_type type) 1602 { 1603 led->rt2x00dev = rt2x00dev; 1604 led->type = type; 1605 led->led_dev.brightness_set = rt2800_brightness_set; 1606 led->flags = LED_INITIALIZED; 1607 } 1608 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1609 1610 /* 1611 * Configuration handlers. 1612 */ 1613 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1614 const u8 *address, 1615 int wcid) 1616 { 1617 struct mac_wcid_entry wcid_entry; 1618 u32 offset; 1619 1620 offset = MAC_WCID_ENTRY(wcid); 1621 1622 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1623 if (address) 1624 memcpy(wcid_entry.mac, address, ETH_ALEN); 1625 1626 rt2800_register_multiwrite(rt2x00dev, offset, 1627 &wcid_entry, sizeof(wcid_entry)); 1628 } 1629 1630 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1631 { 1632 u32 offset; 1633 offset = MAC_WCID_ATTR_ENTRY(wcid); 1634 rt2800_register_write(rt2x00dev, offset, 0); 1635 } 1636 1637 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1638 int wcid, u32 bssidx) 1639 { 1640 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1641 u32 reg; 1642 1643 /* 1644 * The BSS Idx numbers is split in a main value of 3 bits, 1645 * and a extended field for adding one additional bit to the value. 1646 */ 1647 reg = rt2800_register_read(rt2x00dev, offset); 1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1649 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1650 (bssidx & 0x8) >> 3); 1651 rt2800_register_write(rt2x00dev, offset, reg); 1652 } 1653 1654 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1655 struct rt2x00lib_crypto *crypto, 1656 struct ieee80211_key_conf *key) 1657 { 1658 struct mac_iveiv_entry iveiv_entry; 1659 u32 offset; 1660 u32 reg; 1661 1662 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1663 1664 if (crypto->cmd == SET_KEY) { 1665 reg = rt2800_register_read(rt2x00dev, offset); 1666 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1667 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1668 /* 1669 * Both the cipher as the BSS Idx numbers are split in a main 1670 * value of 3 bits, and a extended field for adding one additional 1671 * bit to the value. 1672 */ 1673 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1674 (crypto->cipher & 0x7)); 1675 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1676 (crypto->cipher & 0x8) >> 3); 1677 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1678 rt2800_register_write(rt2x00dev, offset, reg); 1679 } else { 1680 /* Delete the cipher without touching the bssidx */ 1681 reg = rt2800_register_read(rt2x00dev, offset); 1682 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1683 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1684 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1685 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1686 rt2800_register_write(rt2x00dev, offset, reg); 1687 } 1688 1689 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 1690 return; 1691 1692 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1693 1694 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1695 if ((crypto->cipher == CIPHER_TKIP) || 1696 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1697 (crypto->cipher == CIPHER_AES)) 1698 iveiv_entry.iv[3] |= 0x20; 1699 iveiv_entry.iv[3] |= key->keyidx << 6; 1700 rt2800_register_multiwrite(rt2x00dev, offset, 1701 &iveiv_entry, sizeof(iveiv_entry)); 1702 } 1703 1704 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1705 struct rt2x00lib_crypto *crypto, 1706 struct ieee80211_key_conf *key) 1707 { 1708 struct hw_key_entry key_entry; 1709 struct rt2x00_field32 field; 1710 u32 offset; 1711 u32 reg; 1712 1713 if (crypto->cmd == SET_KEY) { 1714 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1715 1716 memcpy(key_entry.key, crypto->key, 1717 sizeof(key_entry.key)); 1718 memcpy(key_entry.tx_mic, crypto->tx_mic, 1719 sizeof(key_entry.tx_mic)); 1720 memcpy(key_entry.rx_mic, crypto->rx_mic, 1721 sizeof(key_entry.rx_mic)); 1722 1723 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1724 rt2800_register_multiwrite(rt2x00dev, offset, 1725 &key_entry, sizeof(key_entry)); 1726 } 1727 1728 /* 1729 * The cipher types are stored over multiple registers 1730 * starting with SHARED_KEY_MODE_BASE each word will have 1731 * 32 bits and contains the cipher types for 2 bssidx each. 1732 * Using the correct defines correctly will cause overhead, 1733 * so just calculate the correct offset. 1734 */ 1735 field.bit_offset = 4 * (key->hw_key_idx % 8); 1736 field.bit_mask = 0x7 << field.bit_offset; 1737 1738 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1739 1740 reg = rt2800_register_read(rt2x00dev, offset); 1741 rt2x00_set_field32(®, field, 1742 (crypto->cmd == SET_KEY) * crypto->cipher); 1743 rt2800_register_write(rt2x00dev, offset, reg); 1744 1745 /* 1746 * Update WCID information 1747 */ 1748 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1749 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1750 crypto->bssidx); 1751 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1752 1753 return 0; 1754 } 1755 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1756 1757 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1758 struct rt2x00lib_crypto *crypto, 1759 struct ieee80211_key_conf *key) 1760 { 1761 struct hw_key_entry key_entry; 1762 u32 offset; 1763 1764 if (crypto->cmd == SET_KEY) { 1765 /* 1766 * Allow key configuration only for STAs that are 1767 * known by the hw. 1768 */ 1769 if (crypto->wcid > WCID_END) 1770 return -ENOSPC; 1771 key->hw_key_idx = crypto->wcid; 1772 1773 memcpy(key_entry.key, crypto->key, 1774 sizeof(key_entry.key)); 1775 memcpy(key_entry.tx_mic, crypto->tx_mic, 1776 sizeof(key_entry.tx_mic)); 1777 memcpy(key_entry.rx_mic, crypto->rx_mic, 1778 sizeof(key_entry.rx_mic)); 1779 1780 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1781 rt2800_register_multiwrite(rt2x00dev, offset, 1782 &key_entry, sizeof(key_entry)); 1783 } 1784 1785 /* 1786 * Update WCID information 1787 */ 1788 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1789 1790 return 0; 1791 } 1792 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1793 1794 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1795 { 1796 u8 i, max_psdu; 1797 u32 reg; 1798 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1799 1800 for (i = 0; i < 3; i++) 1801 if (drv_data->ampdu_factor_cnt[i] > 0) 1802 break; 1803 1804 max_psdu = min(drv_data->max_psdu, i); 1805 1806 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1807 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1808 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1809 } 1810 1811 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1812 struct ieee80211_sta *sta) 1813 { 1814 struct rt2x00_dev *rt2x00dev = hw->priv; 1815 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1816 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1817 int wcid; 1818 1819 /* 1820 * Limit global maximum TX AMPDU length to smallest value of all 1821 * connected stations. In AP mode this can be suboptimal, but we 1822 * do not have a choice if some connected STA is not capable to 1823 * receive the same amount of data like the others. 1824 */ 1825 if (sta->deflink.ht_cap.ht_supported) { 1826 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++; 1827 rt2800_set_max_psdu_len(rt2x00dev); 1828 } 1829 1830 /* 1831 * Search for the first free WCID entry and return the corresponding 1832 * index. 1833 */ 1834 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1835 1836 /* 1837 * Store selected wcid even if it is invalid so that we can 1838 * later decide if the STA is uploaded into the hw. 1839 */ 1840 sta_priv->wcid = wcid; 1841 1842 /* 1843 * No space left in the device, however, we can still communicate 1844 * with the STA -> No error. 1845 */ 1846 if (wcid > WCID_END) 1847 return 0; 1848 1849 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1850 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1851 1852 /* 1853 * Clean up WCID attributes and write STA address to the device. 1854 */ 1855 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1856 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1857 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1858 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1859 return 0; 1860 } 1861 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1862 1863 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1864 struct ieee80211_sta *sta) 1865 { 1866 struct rt2x00_dev *rt2x00dev = hw->priv; 1867 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1868 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1869 int wcid = sta_priv->wcid; 1870 1871 if (sta->deflink.ht_cap.ht_supported) { 1872 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--; 1873 rt2800_set_max_psdu_len(rt2x00dev); 1874 } 1875 1876 if (wcid > WCID_END) 1877 return 0; 1878 /* 1879 * Remove WCID entry, no need to clean the attributes as they will 1880 * get renewed when the WCID is reused. 1881 */ 1882 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1883 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1884 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1885 1886 return 0; 1887 } 1888 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1889 1890 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev) 1891 { 1892 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1893 struct data_queue *queue = rt2x00dev->bcn; 1894 struct queue_entry *entry; 1895 int i, wcid; 1896 1897 for (wcid = WCID_START; wcid < WCID_END; wcid++) { 1898 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1899 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1900 } 1901 1902 for (i = 0; i < queue->limit; i++) { 1903 entry = &queue->entries[i]; 1904 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags); 1905 } 1906 } 1907 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw); 1908 1909 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1910 const unsigned int filter_flags) 1911 { 1912 u32 reg; 1913 1914 /* 1915 * Start configuration steps. 1916 * Note that the version error will always be dropped 1917 * and broadcast frames will always be accepted since 1918 * there is no filter for it at this time. 1919 */ 1920 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1921 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1922 !(filter_flags & FIF_FCSFAIL)); 1923 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1924 !(filter_flags & FIF_PLCPFAIL)); 1925 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1926 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1927 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1928 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1929 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1930 !(filter_flags & FIF_ALLMULTI)); 1931 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1932 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1933 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1934 !(filter_flags & FIF_CONTROL)); 1935 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1936 !(filter_flags & FIF_CONTROL)); 1937 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1938 !(filter_flags & FIF_CONTROL)); 1939 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1940 !(filter_flags & FIF_CONTROL)); 1941 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1942 !(filter_flags & FIF_CONTROL)); 1943 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1944 !(filter_flags & FIF_PSPOLL)); 1945 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1946 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1947 !(filter_flags & FIF_CONTROL)); 1948 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1949 !(filter_flags & FIF_CONTROL)); 1950 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1951 } 1952 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1953 1954 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1955 struct rt2x00intf_conf *conf, const unsigned int flags) 1956 { 1957 u32 reg; 1958 bool update_bssid = false; 1959 1960 if (flags & CONFIG_UPDATE_TYPE) { 1961 /* 1962 * Enable synchronisation. 1963 */ 1964 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1965 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1966 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1967 1968 if (conf->sync == TSF_SYNC_AP_NONE) { 1969 /* 1970 * Tune beacon queue transmit parameters for AP mode 1971 */ 1972 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1973 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1974 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1975 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1976 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1977 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1978 } else { 1979 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1980 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1981 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1982 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1983 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1984 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1985 } 1986 } 1987 1988 if (flags & CONFIG_UPDATE_MAC) { 1989 if (flags & CONFIG_UPDATE_TYPE && 1990 conf->sync == TSF_SYNC_AP_NONE) { 1991 /* 1992 * The BSSID register has to be set to our own mac 1993 * address in AP mode. 1994 */ 1995 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1996 update_bssid = true; 1997 } 1998 1999 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 2000 reg = le32_to_cpu(conf->mac[1]); 2001 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 2002 conf->mac[1] = cpu_to_le32(reg); 2003 } 2004 2005 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 2006 conf->mac, sizeof(conf->mac)); 2007 } 2008 2009 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 2010 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 2011 reg = le32_to_cpu(conf->bssid[1]); 2012 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 2013 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 2014 conf->bssid[1] = cpu_to_le32(reg); 2015 } 2016 2017 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 2018 conf->bssid, sizeof(conf->bssid)); 2019 } 2020 } 2021 EXPORT_SYMBOL_GPL(rt2800_config_intf); 2022 2023 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 2024 struct rt2x00lib_erp *erp) 2025 { 2026 bool any_sta_nongf = !!(erp->ht_opmode & 2027 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 2028 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 2029 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 2030 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 2031 u32 reg; 2032 2033 /* default protection rate for HT20: OFDM 24M */ 2034 mm20_rate = gf20_rate = 0x4004; 2035 2036 /* default protection rate for HT40: duplicate OFDM 24M */ 2037 mm40_rate = gf40_rate = 0x4084; 2038 2039 switch (protection) { 2040 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 2041 /* 2042 * All STAs in this BSS are HT20/40 but there might be 2043 * STAs not supporting greenfield mode. 2044 * => Disable protection for HT transmissions. 2045 */ 2046 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 2047 2048 break; 2049 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2050 /* 2051 * All STAs in this BSS are HT20 or HT20/40 but there 2052 * might be STAs not supporting greenfield mode. 2053 * => Protect all HT40 transmissions. 2054 */ 2055 mm20_mode = gf20_mode = 0; 2056 mm40_mode = gf40_mode = 1; 2057 2058 break; 2059 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 2060 /* 2061 * Nonmember protection: 2062 * According to 802.11n we _should_ protect all 2063 * HT transmissions (but we don't have to). 2064 * 2065 * But if cts_protection is enabled we _shall_ protect 2066 * all HT transmissions using a CCK rate. 2067 * 2068 * And if any station is non GF we _shall_ protect 2069 * GF transmissions. 2070 * 2071 * We decide to protect everything 2072 * -> fall through to mixed mode. 2073 */ 2074 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2075 /* 2076 * Legacy STAs are present 2077 * => Protect all HT transmissions. 2078 */ 2079 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 2080 2081 /* 2082 * If erp protection is needed we have to protect HT 2083 * transmissions with CCK 11M long preamble. 2084 */ 2085 if (erp->cts_protection) { 2086 /* don't duplicate RTS/CTS in CCK mode */ 2087 mm20_rate = mm40_rate = 0x0003; 2088 gf20_rate = gf40_rate = 0x0003; 2089 } 2090 break; 2091 } 2092 2093 /* check for STAs not supporting greenfield mode */ 2094 if (any_sta_nongf) 2095 gf20_mode = gf40_mode = 1; 2096 2097 /* Update HT protection config */ 2098 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 2099 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 2100 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 2101 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 2102 2103 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 2104 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 2105 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 2106 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 2107 2108 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 2109 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 2110 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 2111 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2112 2113 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 2114 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 2115 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2116 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2117 } 2118 2119 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2120 u32 changed) 2121 { 2122 u32 reg; 2123 2124 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2125 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2126 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2127 !!erp->short_preamble); 2128 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2129 } 2130 2131 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2132 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2133 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2134 erp->cts_protection ? 2 : 0); 2135 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2136 } 2137 2138 if (changed & BSS_CHANGED_BASIC_RATES) { 2139 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2140 0xff0 | erp->basic_rates); 2141 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2142 } 2143 2144 if (changed & BSS_CHANGED_ERP_SLOT) { 2145 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2146 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2147 erp->slot_time); 2148 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2149 2150 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2151 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2152 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2153 } 2154 2155 if (changed & BSS_CHANGED_BEACON_INT) { 2156 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2157 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2158 erp->beacon_int * 16); 2159 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2160 } 2161 2162 if (changed & BSS_CHANGED_HT) 2163 rt2800_config_ht_opmode(rt2x00dev, erp); 2164 } 2165 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2166 2167 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev, 2168 const struct rt2x00_field32 mask) 2169 { 2170 unsigned int i; 2171 u32 reg; 2172 2173 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2174 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 2175 if (!rt2x00_get_field32(reg, mask)) 2176 return 0; 2177 2178 udelay(REGISTER_BUSY_DELAY); 2179 } 2180 2181 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 2182 return -EACCES; 2183 } 2184 2185 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 2186 { 2187 unsigned int i; 2188 u8 value; 2189 2190 /* 2191 * BBP was enabled after firmware was loaded, 2192 * but we need to reactivate it now. 2193 */ 2194 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 2195 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 2196 msleep(1); 2197 2198 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2199 value = rt2800_bbp_read(rt2x00dev, 0); 2200 if ((value != 0xff) && (value != 0x00)) 2201 return 0; 2202 udelay(REGISTER_BUSY_DELAY); 2203 } 2204 2205 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 2206 return -EACCES; 2207 } 2208 2209 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2210 { 2211 u32 reg; 2212 u16 eeprom; 2213 u8 led_ctrl, led_g_mode, led_r_mode; 2214 2215 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2216 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2217 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2218 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2219 } else { 2220 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2221 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2222 } 2223 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2224 2225 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2226 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2227 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2228 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2229 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2230 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2231 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2232 if (led_ctrl == 0 || led_ctrl > 0x40) { 2233 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2234 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2235 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2236 } else { 2237 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2238 (led_g_mode << 2) | led_r_mode, 1); 2239 } 2240 } 2241 } 2242 2243 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2244 enum antenna ant) 2245 { 2246 u32 reg; 2247 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2248 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2249 2250 if (rt2x00_is_pci(rt2x00dev)) { 2251 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2252 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2253 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2254 } else if (rt2x00_is_usb(rt2x00dev)) 2255 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2256 eesk_pin, 0); 2257 2258 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2259 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2260 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2261 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2262 } 2263 2264 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2265 { 2266 u8 r1; 2267 u8 r3; 2268 u16 eeprom; 2269 2270 r1 = rt2800_bbp_read(rt2x00dev, 1); 2271 r3 = rt2800_bbp_read(rt2x00dev, 3); 2272 2273 if (rt2x00_rt(rt2x00dev, RT3572) && 2274 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2275 rt2800_config_3572bt_ant(rt2x00dev); 2276 2277 /* 2278 * Configure the TX antenna. 2279 */ 2280 switch (ant->tx_chain_num) { 2281 case 1: 2282 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2283 break; 2284 case 2: 2285 if (rt2x00_rt(rt2x00dev, RT3572) && 2286 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2287 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2288 else 2289 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2290 break; 2291 case 3: 2292 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2293 break; 2294 } 2295 2296 /* 2297 * Configure the RX antenna. 2298 */ 2299 switch (ant->rx_chain_num) { 2300 case 1: 2301 if (rt2x00_rt(rt2x00dev, RT3070) || 2302 rt2x00_rt(rt2x00dev, RT3090) || 2303 rt2x00_rt(rt2x00dev, RT3352) || 2304 rt2x00_rt(rt2x00dev, RT3390)) { 2305 eeprom = rt2800_eeprom_read(rt2x00dev, 2306 EEPROM_NIC_CONF1); 2307 if (rt2x00_get_field16(eeprom, 2308 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2309 rt2800_set_ant_diversity(rt2x00dev, 2310 rt2x00dev->default_ant.rx); 2311 } 2312 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2313 break; 2314 case 2: 2315 if (rt2x00_rt(rt2x00dev, RT3572) && 2316 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2317 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2318 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2319 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2320 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2321 } else { 2322 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2323 } 2324 break; 2325 case 3: 2326 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2327 break; 2328 } 2329 2330 rt2800_bbp_write(rt2x00dev, 3, r3); 2331 rt2800_bbp_write(rt2x00dev, 1, r1); 2332 2333 if (rt2x00_rt(rt2x00dev, RT3593) || 2334 rt2x00_rt(rt2x00dev, RT3883)) { 2335 if (ant->rx_chain_num == 1) 2336 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2337 else 2338 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2339 } 2340 } 2341 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2342 2343 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2344 struct rt2x00lib_conf *libconf) 2345 { 2346 u16 eeprom; 2347 short lna_gain; 2348 2349 if (libconf->rf.channel <= 14) { 2350 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2351 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2352 } else if (libconf->rf.channel <= 64) { 2353 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2354 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2355 } else if (libconf->rf.channel <= 128) { 2356 if (rt2x00_rt(rt2x00dev, RT3593) || 2357 rt2x00_rt(rt2x00dev, RT3883)) { 2358 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2359 lna_gain = rt2x00_get_field16(eeprom, 2360 EEPROM_EXT_LNA2_A1); 2361 } else { 2362 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2363 lna_gain = rt2x00_get_field16(eeprom, 2364 EEPROM_RSSI_BG2_LNA_A1); 2365 } 2366 } else { 2367 if (rt2x00_rt(rt2x00dev, RT3593) || 2368 rt2x00_rt(rt2x00dev, RT3883)) { 2369 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2370 lna_gain = rt2x00_get_field16(eeprom, 2371 EEPROM_EXT_LNA2_A2); 2372 } else { 2373 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2374 lna_gain = rt2x00_get_field16(eeprom, 2375 EEPROM_RSSI_A2_LNA_A2); 2376 } 2377 } 2378 2379 rt2x00dev->lna_gain = lna_gain; 2380 } 2381 2382 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2383 { 2384 return clk_get_rate(rt2x00dev->clk) == 20000000; 2385 } 2386 2387 #define FREQ_OFFSET_BOUND 0x5f 2388 2389 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2390 { 2391 u8 freq_offset, prev_freq_offset; 2392 u8 rfcsr, prev_rfcsr; 2393 2394 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2395 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2396 2397 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2398 prev_rfcsr = rfcsr; 2399 2400 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2401 if (rfcsr == prev_rfcsr) 2402 return; 2403 2404 if (rt2x00_is_usb(rt2x00dev)) { 2405 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2406 freq_offset, prev_rfcsr); 2407 return; 2408 } 2409 2410 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2411 while (prev_freq_offset != freq_offset) { 2412 if (prev_freq_offset < freq_offset) 2413 prev_freq_offset++; 2414 else 2415 prev_freq_offset--; 2416 2417 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2418 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2419 2420 usleep_range(1000, 1500); 2421 } 2422 } 2423 2424 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2425 struct ieee80211_conf *conf, 2426 struct rf_channel *rf, 2427 struct channel_info *info) 2428 { 2429 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2430 2431 if (rt2x00dev->default_ant.tx_chain_num == 1) 2432 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2433 2434 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2435 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2436 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2437 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2438 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2439 2440 if (rf->channel > 14) { 2441 /* 2442 * When TX power is below 0, we should increase it by 7 to 2443 * make it a positive value (Minimum value is -7). 2444 * However this means that values between 0 and 7 have 2445 * double meaning, and we should set a 7DBm boost flag. 2446 */ 2447 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2448 (info->default_power1 >= 0)); 2449 2450 if (info->default_power1 < 0) 2451 info->default_power1 += 7; 2452 2453 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2454 2455 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2456 (info->default_power2 >= 0)); 2457 2458 if (info->default_power2 < 0) 2459 info->default_power2 += 7; 2460 2461 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2462 } else { 2463 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2464 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2465 } 2466 2467 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2468 2469 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2470 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2471 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2472 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2473 2474 udelay(200); 2475 2476 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2477 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2478 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2479 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2480 2481 udelay(200); 2482 2483 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2484 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2485 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2486 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2487 } 2488 2489 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2490 struct ieee80211_conf *conf, 2491 struct rf_channel *rf, 2492 struct channel_info *info) 2493 { 2494 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2495 u8 rfcsr, calib_tx, calib_rx; 2496 2497 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2498 2499 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2500 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2501 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2502 2503 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2504 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2505 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2506 2507 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2508 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2509 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2510 2511 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2512 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2513 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2514 2515 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2516 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2517 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2518 rt2x00dev->default_ant.rx_chain_num <= 1); 2519 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2520 rt2x00dev->default_ant.rx_chain_num <= 2); 2521 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2522 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2523 rt2x00dev->default_ant.tx_chain_num <= 1); 2524 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2525 rt2x00dev->default_ant.tx_chain_num <= 2); 2526 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2527 2528 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2529 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2530 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2531 2532 if (rt2x00_rt(rt2x00dev, RT3390)) { 2533 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2534 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2535 } else { 2536 if (conf_is_ht40(conf)) { 2537 calib_tx = drv_data->calibration_bw40; 2538 calib_rx = drv_data->calibration_bw40; 2539 } else { 2540 calib_tx = drv_data->calibration_bw20; 2541 calib_rx = drv_data->calibration_bw20; 2542 } 2543 } 2544 2545 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2546 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2547 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2548 2549 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2550 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2551 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2552 2553 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2554 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2555 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2556 2557 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2558 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2559 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2560 2561 usleep_range(1000, 1500); 2562 2563 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2564 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2565 } 2566 2567 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2568 struct ieee80211_conf *conf, 2569 struct rf_channel *rf, 2570 struct channel_info *info) 2571 { 2572 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2573 u8 rfcsr; 2574 u32 reg; 2575 2576 if (rf->channel <= 14) { 2577 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2578 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2579 } else { 2580 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2581 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2582 } 2583 2584 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2585 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2586 2587 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2588 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2589 if (rf->channel <= 14) 2590 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2591 else 2592 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2593 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2594 2595 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2596 if (rf->channel <= 14) 2597 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2598 else 2599 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2600 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2601 2602 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2603 if (rf->channel <= 14) { 2604 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2605 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2606 info->default_power1); 2607 } else { 2608 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2609 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2610 (info->default_power1 & 0x3) | 2611 ((info->default_power1 & 0xC) << 1)); 2612 } 2613 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2614 2615 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2616 if (rf->channel <= 14) { 2617 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2618 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2619 info->default_power2); 2620 } else { 2621 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2622 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2623 (info->default_power2 & 0x3) | 2624 ((info->default_power2 & 0xC) << 1)); 2625 } 2626 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2627 2628 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2629 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2630 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2631 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2632 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2633 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2634 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2635 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2636 if (rf->channel <= 14) { 2637 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2638 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2639 } 2640 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2641 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2642 } else { 2643 switch (rt2x00dev->default_ant.tx_chain_num) { 2644 case 1: 2645 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2646 fallthrough; 2647 case 2: 2648 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2649 break; 2650 } 2651 2652 switch (rt2x00dev->default_ant.rx_chain_num) { 2653 case 1: 2654 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2655 fallthrough; 2656 case 2: 2657 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2658 break; 2659 } 2660 } 2661 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2662 2663 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2664 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2665 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2666 2667 if (conf_is_ht40(conf)) { 2668 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2669 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2670 } else { 2671 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2672 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2673 } 2674 2675 if (rf->channel <= 14) { 2676 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2677 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2678 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2679 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2680 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2681 rfcsr = 0x4c; 2682 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2683 drv_data->txmixer_gain_24g); 2684 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2685 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2686 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2687 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2688 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2689 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2690 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2691 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2692 } else { 2693 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2694 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2695 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2696 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2697 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2698 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2699 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2700 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2701 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2702 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2703 rfcsr = 0x7a; 2704 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2705 drv_data->txmixer_gain_5g); 2706 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2707 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2708 if (rf->channel <= 64) { 2709 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2710 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2711 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2712 } else if (rf->channel <= 128) { 2713 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2714 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2715 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2716 } else { 2717 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2718 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2719 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2720 } 2721 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2722 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2723 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2724 } 2725 2726 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2727 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2728 if (rf->channel <= 14) 2729 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2730 else 2731 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2732 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2733 2734 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2735 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2736 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2737 } 2738 2739 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2740 struct ieee80211_conf *conf, 2741 struct rf_channel *rf, 2742 struct channel_info *info) 2743 { 2744 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2745 u8 txrx_agc_fc; 2746 u8 txrx_h20m; 2747 u8 rfcsr; 2748 u8 bbp; 2749 const bool txbf_enabled = false; /* TODO */ 2750 2751 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2752 bbp = rt2800_bbp_read(rt2x00dev, 109); 2753 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2754 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2755 rt2800_bbp_write(rt2x00dev, 109, bbp); 2756 2757 bbp = rt2800_bbp_read(rt2x00dev, 110); 2758 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2759 rt2800_bbp_write(rt2x00dev, 110, bbp); 2760 2761 if (rf->channel <= 14) { 2762 /* Restore BBP 25 & 26 for 2.4 GHz */ 2763 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2764 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2765 } else { 2766 /* Hard code BBP 25 & 26 for 5GHz */ 2767 2768 /* Enable IQ Phase correction */ 2769 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2770 /* Setup IQ Phase correction value */ 2771 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2772 } 2773 2774 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2775 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2776 2777 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2778 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2779 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2780 2781 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2782 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2783 if (rf->channel <= 14) 2784 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2785 else 2786 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2787 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2788 2789 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2790 if (rf->channel <= 14) { 2791 rfcsr = 0; 2792 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2793 info->default_power1 & 0x1f); 2794 } else { 2795 if (rt2x00_is_usb(rt2x00dev)) 2796 rfcsr = 0x40; 2797 2798 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2799 ((info->default_power1 & 0x18) << 1) | 2800 (info->default_power1 & 7)); 2801 } 2802 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2803 2804 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2805 if (rf->channel <= 14) { 2806 rfcsr = 0; 2807 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2808 info->default_power2 & 0x1f); 2809 } else { 2810 if (rt2x00_is_usb(rt2x00dev)) 2811 rfcsr = 0x40; 2812 2813 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2814 ((info->default_power2 & 0x18) << 1) | 2815 (info->default_power2 & 7)); 2816 } 2817 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2818 2819 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2820 if (rf->channel <= 14) { 2821 rfcsr = 0; 2822 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2823 info->default_power3 & 0x1f); 2824 } else { 2825 if (rt2x00_is_usb(rt2x00dev)) 2826 rfcsr = 0x40; 2827 2828 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2829 ((info->default_power3 & 0x18) << 1) | 2830 (info->default_power3 & 7)); 2831 } 2832 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2833 2834 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2835 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2836 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2837 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2838 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2839 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2840 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2841 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2842 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2843 2844 switch (rt2x00dev->default_ant.tx_chain_num) { 2845 case 3: 2846 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2847 fallthrough; 2848 case 2: 2849 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2850 fallthrough; 2851 case 1: 2852 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2853 break; 2854 } 2855 2856 switch (rt2x00dev->default_ant.rx_chain_num) { 2857 case 3: 2858 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2859 fallthrough; 2860 case 2: 2861 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2862 fallthrough; 2863 case 1: 2864 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2865 break; 2866 } 2867 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2868 2869 rt2800_freq_cal_mode1(rt2x00dev); 2870 2871 if (conf_is_ht40(conf)) { 2872 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2873 RFCSR24_TX_AGC_FC); 2874 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2875 RFCSR24_TX_H20M); 2876 } else { 2877 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2878 RFCSR24_TX_AGC_FC); 2879 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2880 RFCSR24_TX_H20M); 2881 } 2882 2883 /* NOTE: the reference driver does not writes the new value 2884 * back to RFCSR 32 2885 */ 2886 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2887 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2888 2889 if (rf->channel <= 14) 2890 rfcsr = 0xa0; 2891 else 2892 rfcsr = 0x80; 2893 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2894 2895 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2896 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2897 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2898 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2899 2900 /* Band selection */ 2901 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2902 if (rf->channel <= 14) 2903 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2904 else 2905 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2906 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2907 2908 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2909 if (rf->channel <= 14) 2910 rfcsr = 0x3c; 2911 else 2912 rfcsr = 0x20; 2913 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2914 2915 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2916 if (rf->channel <= 14) 2917 rfcsr = 0x1a; 2918 else 2919 rfcsr = 0x12; 2920 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2921 2922 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2923 if (rf->channel >= 1 && rf->channel <= 14) 2924 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2925 else if (rf->channel >= 36 && rf->channel <= 64) 2926 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2927 else if (rf->channel >= 100 && rf->channel <= 128) 2928 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2929 else 2930 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2931 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2932 2933 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2934 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2935 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2936 2937 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2938 2939 if (rf->channel <= 14) { 2940 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2941 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2942 } else { 2943 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2944 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2945 } 2946 2947 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2948 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2949 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2950 2951 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2952 if (rf->channel <= 14) { 2953 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2954 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2955 } else { 2956 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2957 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2958 } 2959 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2960 2961 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2962 if (rf->channel <= 14) 2963 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2964 else 2965 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2966 2967 if (txbf_enabled) 2968 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2969 2970 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2971 2972 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2973 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2974 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2975 2976 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2977 if (rf->channel <= 14) 2978 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2979 else 2980 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2981 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2982 2983 if (rf->channel <= 14) { 2984 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2985 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2986 } else { 2987 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2988 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2989 } 2990 2991 /* Initiate VCO calibration */ 2992 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2993 if (rf->channel <= 14) { 2994 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2995 } else { 2996 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2997 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2998 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2999 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 3000 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 3001 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3002 } 3003 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3004 3005 if (rf->channel >= 1 && rf->channel <= 14) { 3006 rfcsr = 0x23; 3007 if (txbf_enabled) 3008 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3009 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3010 3011 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 3012 } else if (rf->channel >= 36 && rf->channel <= 64) { 3013 rfcsr = 0x36; 3014 if (txbf_enabled) 3015 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3016 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 3017 3018 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 3019 } else if (rf->channel >= 100 && rf->channel <= 128) { 3020 rfcsr = 0x32; 3021 if (txbf_enabled) 3022 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3023 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3024 3025 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 3026 } else { 3027 rfcsr = 0x30; 3028 if (txbf_enabled) 3029 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3030 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3031 3032 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 3033 } 3034 } 3035 3036 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev, 3037 struct ieee80211_conf *conf, 3038 struct rf_channel *rf, 3039 struct channel_info *info) 3040 { 3041 u8 rfcsr; 3042 u8 bbp; 3043 u8 pwr1, pwr2, pwr3; 3044 3045 const bool txbf_enabled = false; /* TODO */ 3046 3047 /* TODO: add band selection */ 3048 3049 if (rf->channel <= 14) 3050 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3051 else if (rf->channel < 132) 3052 rt2800_rfcsr_write(rt2x00dev, 6, 0x80); 3053 else 3054 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3055 3056 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3057 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3058 3059 if (rf->channel <= 14) 3060 rt2800_rfcsr_write(rt2x00dev, 11, 0x46); 3061 else 3062 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 3063 3064 if (rf->channel <= 14) 3065 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 3066 else 3067 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3068 3069 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 3070 3071 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3072 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 3073 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 3074 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3075 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3076 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3077 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3078 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3079 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3080 3081 switch (rt2x00dev->default_ant.tx_chain_num) { 3082 case 3: 3083 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 3084 fallthrough; 3085 case 2: 3086 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3087 fallthrough; 3088 case 1: 3089 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3090 break; 3091 } 3092 3093 switch (rt2x00dev->default_ant.rx_chain_num) { 3094 case 3: 3095 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 3096 fallthrough; 3097 case 2: 3098 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3099 fallthrough; 3100 case 1: 3101 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3102 break; 3103 } 3104 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3105 3106 rt2800_freq_cal_mode1(rt2x00dev); 3107 3108 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3109 if (!conf_is_ht40(conf)) 3110 rfcsr &= ~(0x06); 3111 else 3112 rfcsr |= 0x06; 3113 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3114 3115 if (rf->channel <= 14) 3116 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0); 3117 else 3118 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3119 3120 if (conf_is_ht40(conf)) 3121 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3122 else 3123 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 3124 3125 if (rf->channel <= 14) 3126 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 3127 else 3128 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 3129 3130 /* loopback RF_BS */ 3131 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 3132 if (rf->channel <= 14) 3133 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 3134 else 3135 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 3136 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 3137 3138 if (rf->channel <= 14) 3139 rfcsr = 0x23; 3140 else if (rf->channel < 100) 3141 rfcsr = 0x36; 3142 else if (rf->channel < 132) 3143 rfcsr = 0x32; 3144 else 3145 rfcsr = 0x30; 3146 3147 if (txbf_enabled) 3148 rfcsr |= 0x40; 3149 3150 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3151 3152 if (rf->channel <= 14) 3153 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 3154 else 3155 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 3156 3157 if (rf->channel <= 14) 3158 rfcsr = 0xbb; 3159 else if (rf->channel < 100) 3160 rfcsr = 0xeb; 3161 else if (rf->channel < 132) 3162 rfcsr = 0xb3; 3163 else 3164 rfcsr = 0x9b; 3165 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr); 3166 3167 if (rf->channel <= 14) 3168 rfcsr = 0x8e; 3169 else 3170 rfcsr = 0x8a; 3171 3172 if (txbf_enabled) 3173 rfcsr |= 0x20; 3174 3175 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3176 3177 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 3178 3179 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 3180 if (rf->channel <= 14) 3181 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 3182 else 3183 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 3184 3185 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52); 3186 if (rf->channel <= 14) 3187 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 3188 else 3189 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 3190 3191 if (rf->channel <= 14) { 3192 pwr1 = info->default_power1 & 0x1f; 3193 pwr2 = info->default_power2 & 0x1f; 3194 pwr3 = info->default_power3 & 0x1f; 3195 } else { 3196 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) | 3197 (info->default_power1 & 0x7); 3198 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) | 3199 (info->default_power2 & 0x7); 3200 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) | 3201 (info->default_power3 & 0x7); 3202 } 3203 3204 rt2800_rfcsr_write(rt2x00dev, 53, pwr1); 3205 rt2800_rfcsr_write(rt2x00dev, 54, pwr2); 3206 rt2800_rfcsr_write(rt2x00dev, 55, pwr3); 3207 3208 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n", 3209 rf->channel, pwr1, pwr2, pwr3); 3210 3211 bbp = (info->default_power1 >> 5) | 3212 ((info->default_power2 & 0xe0) >> 1); 3213 rt2800_bbp_write(rt2x00dev, 109, bbp); 3214 3215 bbp = rt2800_bbp_read(rt2x00dev, 110); 3216 bbp &= 0x0f; 3217 bbp |= (info->default_power3 & 0xe0) >> 1; 3218 rt2800_bbp_write(rt2x00dev, 110, bbp); 3219 3220 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 3221 if (rf->channel <= 14) 3222 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 3223 else 3224 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 3225 3226 /* Enable RF tuning */ 3227 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3228 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3229 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3230 3231 udelay(2000); 3232 3233 bbp = rt2800_bbp_read(rt2x00dev, 49); 3234 /* clear update flag */ 3235 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe); 3236 rt2800_bbp_write(rt2x00dev, 49, bbp); 3237 3238 /* TODO: add calibration for TxBF */ 3239 } 3240 3241 #define POWER_BOUND 0x27 3242 #define POWER_BOUND_5G 0x2b 3243 3244 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 3245 struct ieee80211_conf *conf, 3246 struct rf_channel *rf, 3247 struct channel_info *info) 3248 { 3249 u8 rfcsr; 3250 3251 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3252 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3253 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3254 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3255 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3256 3257 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3258 if (info->default_power1 > POWER_BOUND) 3259 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3260 else 3261 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3262 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3263 3264 rt2800_freq_cal_mode1(rt2x00dev); 3265 3266 if (rf->channel <= 14) { 3267 if (rf->channel == 6) 3268 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 3269 else 3270 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3271 3272 if (rf->channel >= 1 && rf->channel <= 6) 3273 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 3274 else if (rf->channel >= 7 && rf->channel <= 11) 3275 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 3276 else if (rf->channel >= 12 && rf->channel <= 14) 3277 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 3278 } 3279 } 3280 3281 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 3282 struct ieee80211_conf *conf, 3283 struct rf_channel *rf, 3284 struct channel_info *info) 3285 { 3286 u8 rfcsr; 3287 3288 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3289 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3290 3291 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 3292 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 3293 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 3294 3295 if (info->default_power1 > POWER_BOUND) 3296 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 3297 else 3298 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 3299 3300 if (info->default_power2 > POWER_BOUND) 3301 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 3302 else 3303 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 3304 3305 rt2800_freq_cal_mode1(rt2x00dev); 3306 3307 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3308 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3309 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3310 3311 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 3312 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3313 else 3314 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3315 3316 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 3317 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3318 else 3319 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3320 3321 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3322 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3323 3324 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3325 3326 rt2800_rfcsr_write(rt2x00dev, 31, 80); 3327 } 3328 3329 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 3330 struct ieee80211_conf *conf, 3331 struct rf_channel *rf, 3332 struct channel_info *info) 3333 { 3334 u8 rfcsr; 3335 int idx = rf->channel-1; 3336 3337 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3338 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3339 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3340 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3341 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3342 3343 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3344 if (info->default_power1 > POWER_BOUND) 3345 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3346 else 3347 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3348 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3349 3350 if (rt2x00_rt(rt2x00dev, RT5392)) { 3351 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3352 if (info->default_power2 > POWER_BOUND) 3353 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 3354 else 3355 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 3356 info->default_power2); 3357 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3358 } 3359 3360 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3361 if (rt2x00_rt(rt2x00dev, RT5392)) { 3362 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3363 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3364 } 3365 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3366 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3367 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3368 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3369 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3370 3371 rt2800_freq_cal_mode1(rt2x00dev); 3372 3373 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3374 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3375 /* r55/r59 value array of channel 1~14 */ 3376 static const u8 r55_bt_rev[] = {0x83, 0x83, 3377 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3378 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3379 static const u8 r59_bt_rev[] = {0x0e, 0x0e, 3380 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3381 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3382 3383 rt2800_rfcsr_write(rt2x00dev, 55, 3384 r55_bt_rev[idx]); 3385 rt2800_rfcsr_write(rt2x00dev, 59, 3386 r59_bt_rev[idx]); 3387 } else { 3388 static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b, 3389 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3390 0x88, 0x88, 0x86, 0x85, 0x84}; 3391 3392 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3393 } 3394 } else { 3395 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3396 static const u8 r55_nonbt_rev[] = {0x23, 0x23, 3397 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3398 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3399 static const u8 r59_nonbt_rev[] = {0x07, 0x07, 3400 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3401 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3402 3403 rt2800_rfcsr_write(rt2x00dev, 55, 3404 r55_nonbt_rev[idx]); 3405 rt2800_rfcsr_write(rt2x00dev, 59, 3406 r59_nonbt_rev[idx]); 3407 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3408 rt2x00_rt(rt2x00dev, RT5392) || 3409 rt2x00_rt(rt2x00dev, RT6352)) { 3410 static const u8 r59_non_bt[] = {0x8f, 0x8f, 3411 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3412 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3413 3414 rt2800_rfcsr_write(rt2x00dev, 59, 3415 r59_non_bt[idx]); 3416 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3417 static const u8 r59_non_bt[] = {0x0b, 0x0b, 3418 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3419 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3420 3421 rt2800_rfcsr_write(rt2x00dev, 59, 3422 r59_non_bt[idx]); 3423 } 3424 } 3425 } 3426 3427 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3428 struct ieee80211_conf *conf, 3429 struct rf_channel *rf, 3430 struct channel_info *info) 3431 { 3432 u8 rfcsr, ep_reg; 3433 u32 reg; 3434 int power_bound; 3435 3436 /* TODO */ 3437 const bool is_11b = false; 3438 const bool is_type_ep = false; 3439 3440 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3441 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3442 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3443 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3444 3445 /* Order of values on rf_channel entry: N, K, mod, R */ 3446 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3447 3448 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3449 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3450 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3451 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3452 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3453 3454 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3455 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3456 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3457 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3458 3459 if (rf->channel <= 14) { 3460 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3461 /* FIXME: RF11 owerwrite ? */ 3462 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3463 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3464 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3465 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3466 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3467 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3468 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3469 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3470 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3471 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3472 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3473 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3474 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3475 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3476 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3477 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3478 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3479 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3480 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3481 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3482 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3483 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3484 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3485 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3486 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3487 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3488 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3489 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3490 3491 /* TODO RF27 <- tssi */ 3492 3493 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3494 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3495 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3496 3497 if (is_11b) { 3498 /* CCK */ 3499 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3500 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3501 if (is_type_ep) 3502 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3503 else 3504 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3505 } else { 3506 /* OFDM */ 3507 if (is_type_ep) 3508 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3509 else 3510 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3511 } 3512 3513 power_bound = POWER_BOUND; 3514 ep_reg = 0x2; 3515 } else { 3516 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3517 /* FIMXE: RF11 overwrite */ 3518 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3519 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3520 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3521 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3522 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3523 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3524 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3525 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3526 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3527 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3528 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3529 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3530 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3531 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3532 3533 /* TODO RF27 <- tssi */ 3534 3535 if (rf->channel >= 36 && rf->channel <= 64) { 3536 3537 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3538 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3539 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3540 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3541 if (rf->channel <= 50) 3542 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3543 else if (rf->channel >= 52) 3544 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3545 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3546 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3547 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3548 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3549 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3550 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3551 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3552 if (rf->channel <= 50) { 3553 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3554 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3555 } else if (rf->channel >= 52) { 3556 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3557 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3558 } 3559 3560 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3561 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3562 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3563 3564 } else if (rf->channel >= 100 && rf->channel <= 165) { 3565 3566 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3567 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3568 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3569 if (rf->channel <= 153) { 3570 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3571 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3572 } else if (rf->channel >= 155) { 3573 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3574 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3575 } 3576 if (rf->channel <= 138) { 3577 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3578 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3579 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3580 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3581 } else if (rf->channel >= 140) { 3582 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3583 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3584 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3585 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3586 } 3587 if (rf->channel <= 124) 3588 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3589 else if (rf->channel >= 126) 3590 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3591 if (rf->channel <= 138) 3592 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3593 else if (rf->channel >= 140) 3594 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3595 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3596 if (rf->channel <= 138) 3597 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3598 else if (rf->channel >= 140) 3599 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3600 if (rf->channel <= 128) 3601 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3602 else if (rf->channel >= 130) 3603 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3604 if (rf->channel <= 116) 3605 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3606 else if (rf->channel >= 118) 3607 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3608 if (rf->channel <= 138) 3609 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3610 else if (rf->channel >= 140) 3611 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3612 if (rf->channel <= 116) 3613 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3614 else if (rf->channel >= 118) 3615 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3616 } 3617 3618 power_bound = POWER_BOUND_5G; 3619 ep_reg = 0x3; 3620 } 3621 3622 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3623 if (info->default_power1 > power_bound) 3624 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3625 else 3626 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3627 if (is_type_ep) 3628 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3629 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3630 3631 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3632 if (info->default_power2 > power_bound) 3633 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3634 else 3635 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3636 if (is_type_ep) 3637 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3638 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3639 3640 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3641 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3642 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3643 3644 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3645 rt2x00dev->default_ant.tx_chain_num >= 1); 3646 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3647 rt2x00dev->default_ant.tx_chain_num == 2); 3648 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3649 3650 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3651 rt2x00dev->default_ant.rx_chain_num >= 1); 3652 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3653 rt2x00dev->default_ant.rx_chain_num == 2); 3654 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3655 3656 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3657 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3658 3659 if (conf_is_ht40(conf)) 3660 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3661 else 3662 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3663 3664 if (!is_11b) { 3665 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3666 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3667 } 3668 3669 /* TODO proper frequency adjustment */ 3670 rt2800_freq_cal_mode1(rt2x00dev); 3671 3672 /* TODO merge with others */ 3673 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3674 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3675 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3676 3677 /* BBP settings */ 3678 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3679 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3680 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3681 3682 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3683 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3684 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3685 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3686 3687 /* GLRT band configuration */ 3688 rt2800_bbp_write(rt2x00dev, 195, 128); 3689 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3690 rt2800_bbp_write(rt2x00dev, 195, 129); 3691 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3692 rt2800_bbp_write(rt2x00dev, 195, 130); 3693 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3694 rt2800_bbp_write(rt2x00dev, 195, 131); 3695 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3696 rt2800_bbp_write(rt2x00dev, 195, 133); 3697 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3698 rt2800_bbp_write(rt2x00dev, 195, 124); 3699 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3700 } 3701 3702 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3703 struct ieee80211_conf *conf, 3704 struct rf_channel *rf, 3705 struct channel_info *info) 3706 { 3707 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3708 u8 rx_agc_fc, tx_agc_fc; 3709 u8 rfcsr; 3710 3711 /* Frequeny plan setting */ 3712 /* Rdiv setting (set 0x03 if Xtal==20) 3713 * R13[1:0] 3714 */ 3715 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3716 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3717 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3718 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3719 3720 /* N setting 3721 * R20[7:0] in rf->rf1 3722 * R21[0] always 0 3723 */ 3724 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3725 rfcsr = (rf->rf1 & 0x00ff); 3726 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3727 3728 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3729 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3730 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3731 3732 /* K setting (always 0) 3733 * R16[3:0] (RF PLL freq selection) 3734 */ 3735 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3736 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3737 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3738 3739 /* D setting (always 0) 3740 * R22[2:0] (D=15, R22[2:0]=<111>) 3741 */ 3742 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3743 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3744 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3745 3746 /* Ksd setting 3747 * Ksd: R17<7:0> in rf->rf2 3748 * R18<7:0> in rf->rf3 3749 * R19<1:0> in rf->rf4 3750 */ 3751 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3752 rfcsr = rf->rf2; 3753 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3754 3755 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3756 rfcsr = rf->rf3; 3757 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3758 3759 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3760 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3761 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3762 3763 /* Default: XO=20MHz , SDM mode */ 3764 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3765 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3766 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3767 3768 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3769 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3770 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3771 3772 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3773 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3774 rt2x00dev->default_ant.tx_chain_num != 1); 3775 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3776 3777 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3778 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3779 rt2x00dev->default_ant.tx_chain_num != 1); 3780 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3781 rt2x00dev->default_ant.rx_chain_num != 1); 3782 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3783 3784 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3785 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3786 rt2x00dev->default_ant.tx_chain_num != 1); 3787 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3788 3789 /* RF for DC Cal BW */ 3790 if (conf_is_ht40(conf)) { 3791 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3792 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3793 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3794 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3795 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3796 } else { 3797 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3798 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3799 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3800 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3801 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3802 } 3803 3804 if (conf_is_ht40(conf)) { 3805 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3806 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3807 } else { 3808 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3809 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3810 } 3811 3812 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3813 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3814 conf_is_ht40(conf) && (rf->channel == 11)); 3815 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3816 3817 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3818 if (conf_is_ht40(conf)) { 3819 rx_agc_fc = drv_data->rx_calibration_bw40; 3820 tx_agc_fc = drv_data->tx_calibration_bw40; 3821 } else { 3822 rx_agc_fc = drv_data->rx_calibration_bw20; 3823 tx_agc_fc = drv_data->tx_calibration_bw20; 3824 } 3825 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3826 rfcsr &= (~0x3F); 3827 rfcsr |= rx_agc_fc; 3828 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3829 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3830 rfcsr &= (~0x3F); 3831 rfcsr |= rx_agc_fc; 3832 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3833 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3834 rfcsr &= (~0x3F); 3835 rfcsr |= rx_agc_fc; 3836 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3837 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3838 rfcsr &= (~0x3F); 3839 rfcsr |= rx_agc_fc; 3840 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3841 3842 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3843 rfcsr &= (~0x3F); 3844 rfcsr |= tx_agc_fc; 3845 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3846 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3847 rfcsr &= (~0x3F); 3848 rfcsr |= tx_agc_fc; 3849 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3850 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3851 rfcsr &= (~0x3F); 3852 rfcsr |= tx_agc_fc; 3853 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3854 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3855 rfcsr &= (~0x3F); 3856 rfcsr |= tx_agc_fc; 3857 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3858 } 3859 3860 if (conf_is_ht40(conf)) { 3861 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10); 3862 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f); 3863 } else { 3864 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a); 3865 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40); 3866 } 3867 } 3868 3869 static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev, 3870 struct ieee80211_channel *chan, 3871 int power_level) 3872 { 3873 int cur_channel = rt2x00dev->rf_channel; 3874 u16 eeprom, chan_power, rate_power, target_power; 3875 u16 tx_power[2]; 3876 s8 *power_group[2]; 3877 u32 mac_sys_ctrl; 3878 u32 cnt, reg; 3879 u8 bbp; 3880 3881 if (WARN_ON(cur_channel < 1 || cur_channel > 14)) 3882 return; 3883 3884 /* get per chain power, 2 chains in total, unit is 0.5dBm */ 3885 power_level = (power_level - 3) * 2; 3886 3887 /* We can't get the accurate TX power. Based on some tests, the real 3888 * TX power is approximately equal to channel_power + (max)rate_power. 3889 * Usually max rate_power is the gain of the OFDM 6M rate. The antenna 3890 * gain and externel PA gain are not included as we are unable to 3891 * obtain these values. 3892 */ 3893 rate_power = rt2800_eeprom_read_from_array(rt2x00dev, 3894 EEPROM_TXPOWER_BYRATE, 1); 3895 rate_power &= 0x3f; 3896 power_level -= rate_power; 3897 if (power_level < 1) 3898 power_level = 1; 3899 3900 power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 3901 power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 3902 for (cnt = 0; cnt < 2; cnt++) { 3903 chan_power = power_group[cnt][cur_channel - 1]; 3904 if (chan_power >= 0x20 || chan_power == 0) 3905 chan_power = 0x10; 3906 tx_power[cnt] = power_level < chan_power ? power_level : chan_power; 3907 } 3908 3909 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3910 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]); 3911 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]); 3912 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, 0x2f); 3913 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, 0x2f); 3914 3915 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3916 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3917 /* init base power by eeprom target power */ 3918 target_power = rt2800_eeprom_read(rt2x00dev, 3919 EEPROM_TXPOWER_INIT); 3920 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3921 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3922 } 3923 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3924 3925 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3926 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3927 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3928 3929 /* Save MAC SYS CTRL registers */ 3930 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3931 /* Disable Tx/Rx */ 3932 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3933 /* Check MAC Tx/Rx idle */ 3934 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 3935 rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n"); 3936 3937 if (chan->center_freq > 2457) { 3938 bbp = rt2800_bbp_read(rt2x00dev, 30); 3939 bbp = 0x40; 3940 rt2800_bbp_write(rt2x00dev, 30, bbp); 3941 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3942 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3943 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3944 else 3945 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3946 } else { 3947 bbp = rt2800_bbp_read(rt2x00dev, 30); 3948 bbp = 0x1f; 3949 rt2800_bbp_write(rt2x00dev, 30, bbp); 3950 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3951 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3952 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3953 else 3954 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3955 } 3956 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3957 3958 rt2800_vco_calibration(rt2x00dev); 3959 } 3960 3961 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3962 const unsigned int word, 3963 const u8 value) 3964 { 3965 u8 chain, reg; 3966 3967 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3968 reg = rt2800_bbp_read(rt2x00dev, 27); 3969 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3970 rt2800_bbp_write(rt2x00dev, 27, reg); 3971 3972 rt2800_bbp_write(rt2x00dev, word, value); 3973 } 3974 } 3975 3976 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3977 { 3978 u8 cal; 3979 3980 /* TX0 IQ Gain */ 3981 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3982 if (channel <= 14) 3983 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3984 else if (channel >= 36 && channel <= 64) 3985 cal = rt2x00_eeprom_byte(rt2x00dev, 3986 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3987 else if (channel >= 100 && channel <= 138) 3988 cal = rt2x00_eeprom_byte(rt2x00dev, 3989 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3990 else if (channel >= 140 && channel <= 165) 3991 cal = rt2x00_eeprom_byte(rt2x00dev, 3992 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3993 else 3994 cal = 0; 3995 rt2800_bbp_write(rt2x00dev, 159, cal); 3996 3997 /* TX0 IQ Phase */ 3998 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3999 if (channel <= 14) 4000 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 4001 else if (channel >= 36 && channel <= 64) 4002 cal = rt2x00_eeprom_byte(rt2x00dev, 4003 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 4004 else if (channel >= 100 && channel <= 138) 4005 cal = rt2x00_eeprom_byte(rt2x00dev, 4006 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 4007 else if (channel >= 140 && channel <= 165) 4008 cal = rt2x00_eeprom_byte(rt2x00dev, 4009 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 4010 else 4011 cal = 0; 4012 rt2800_bbp_write(rt2x00dev, 159, cal); 4013 4014 /* TX1 IQ Gain */ 4015 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 4016 if (channel <= 14) 4017 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 4018 else if (channel >= 36 && channel <= 64) 4019 cal = rt2x00_eeprom_byte(rt2x00dev, 4020 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 4021 else if (channel >= 100 && channel <= 138) 4022 cal = rt2x00_eeprom_byte(rt2x00dev, 4023 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 4024 else if (channel >= 140 && channel <= 165) 4025 cal = rt2x00_eeprom_byte(rt2x00dev, 4026 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 4027 else 4028 cal = 0; 4029 rt2800_bbp_write(rt2x00dev, 159, cal); 4030 4031 /* TX1 IQ Phase */ 4032 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 4033 if (channel <= 14) 4034 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 4035 else if (channel >= 36 && channel <= 64) 4036 cal = rt2x00_eeprom_byte(rt2x00dev, 4037 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 4038 else if (channel >= 100 && channel <= 138) 4039 cal = rt2x00_eeprom_byte(rt2x00dev, 4040 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 4041 else if (channel >= 140 && channel <= 165) 4042 cal = rt2x00_eeprom_byte(rt2x00dev, 4043 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 4044 else 4045 cal = 0; 4046 rt2800_bbp_write(rt2x00dev, 159, cal); 4047 4048 /* FIXME: possible RX0, RX1 callibration ? */ 4049 4050 /* RF IQ compensation control */ 4051 rt2800_bbp_write(rt2x00dev, 158, 0x04); 4052 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 4053 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4054 4055 /* RF IQ imbalance compensation control */ 4056 rt2800_bbp_write(rt2x00dev, 158, 0x03); 4057 cal = rt2x00_eeprom_byte(rt2x00dev, 4058 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 4059 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4060 } 4061 4062 static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 4063 unsigned int channel, 4064 s8 txpower) 4065 { 4066 if (rt2x00_rt(rt2x00dev, RT3593) || 4067 rt2x00_rt(rt2x00dev, RT3883)) 4068 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 4069 4070 if (channel <= 14) 4071 return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 4072 4073 if (rt2x00_rt(rt2x00dev, RT3593) || 4074 rt2x00_rt(rt2x00dev, RT3883)) 4075 return clamp_t(s8, txpower, MIN_A_TXPOWER_3593, 4076 MAX_A_TXPOWER_3593); 4077 else 4078 return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 4079 } 4080 4081 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev, 4082 struct rf_channel *rf) 4083 { 4084 u8 bbp; 4085 4086 bbp = (rf->channel > 14) ? 0x48 : 0x38; 4087 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 4088 4089 rt2800_bbp_write(rt2x00dev, 69, 0x12); 4090 4091 if (rf->channel <= 14) { 4092 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4093 } else { 4094 /* Disable CCK packet detection */ 4095 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4096 } 4097 4098 rt2800_bbp_write(rt2x00dev, 73, 0x10); 4099 4100 if (rf->channel > 14) { 4101 rt2800_bbp_write(rt2x00dev, 62, 0x1d); 4102 rt2800_bbp_write(rt2x00dev, 63, 0x1d); 4103 rt2800_bbp_write(rt2x00dev, 64, 0x1d); 4104 } else { 4105 rt2800_bbp_write(rt2x00dev, 62, 0x2d); 4106 rt2800_bbp_write(rt2x00dev, 63, 0x2d); 4107 rt2800_bbp_write(rt2x00dev, 64, 0x2d); 4108 } 4109 } 4110 4111 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 4112 struct ieee80211_conf *conf, 4113 struct rf_channel *rf, 4114 struct channel_info *info) 4115 { 4116 u32 reg; 4117 u32 tx_pin; 4118 u8 bbp, rfcsr; 4119 4120 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4121 info->default_power1); 4122 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4123 info->default_power2); 4124 if (rt2x00dev->default_ant.tx_chain_num > 2) 4125 info->default_power3 = 4126 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4127 info->default_power3); 4128 4129 switch (rt2x00dev->chip.rt) { 4130 case RT3883: 4131 rt3883_bbp_adjust(rt2x00dev, rf); 4132 break; 4133 } 4134 4135 switch (rt2x00dev->chip.rf) { 4136 case RF2020: 4137 case RF3020: 4138 case RF3021: 4139 case RF3022: 4140 case RF3320: 4141 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 4142 break; 4143 case RF3052: 4144 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 4145 break; 4146 case RF3053: 4147 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 4148 break; 4149 case RF3290: 4150 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 4151 break; 4152 case RF3322: 4153 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 4154 break; 4155 case RF3853: 4156 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info); 4157 break; 4158 case RF3070: 4159 case RF5350: 4160 case RF5360: 4161 case RF5362: 4162 case RF5370: 4163 case RF5372: 4164 case RF5390: 4165 case RF5392: 4166 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 4167 break; 4168 case RF5592: 4169 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 4170 break; 4171 case RF7620: 4172 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 4173 break; 4174 default: 4175 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 4176 } 4177 4178 if (rt2x00_rf(rt2x00dev, RF3070) || 4179 rt2x00_rf(rt2x00dev, RF3290) || 4180 rt2x00_rf(rt2x00dev, RF3322) || 4181 rt2x00_rf(rt2x00dev, RF5350) || 4182 rt2x00_rf(rt2x00dev, RF5360) || 4183 rt2x00_rf(rt2x00dev, RF5362) || 4184 rt2x00_rf(rt2x00dev, RF5370) || 4185 rt2x00_rf(rt2x00dev, RF5372) || 4186 rt2x00_rf(rt2x00dev, RF5390) || 4187 rt2x00_rf(rt2x00dev, RF5392)) { 4188 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 4189 if (rt2x00_rf(rt2x00dev, RF3322)) { 4190 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 4191 conf_is_ht40(conf)); 4192 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 4193 conf_is_ht40(conf)); 4194 } else { 4195 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 4196 conf_is_ht40(conf)); 4197 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 4198 conf_is_ht40(conf)); 4199 } 4200 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 4201 4202 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4203 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4204 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4205 } 4206 4207 /* 4208 * Change BBP settings 4209 */ 4210 4211 if (rt2x00_rt(rt2x00dev, RT3352)) { 4212 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4213 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4214 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4215 4216 rt2800_bbp_write(rt2x00dev, 27, 0x0); 4217 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4218 rt2800_bbp_write(rt2x00dev, 27, 0x20); 4219 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4220 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4221 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 4222 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4223 if (rf->channel > 14) { 4224 /* Disable CCK Packet detection on 5GHz */ 4225 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4226 } else { 4227 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4228 } 4229 4230 if (conf_is_ht40(conf)) 4231 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4232 else 4233 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4234 4235 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4236 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4237 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4238 rt2800_bbp_write(rt2x00dev, 77, 0x98); 4239 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 4240 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4241 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4242 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4243 4244 if (rt2x00dev->default_ant.rx_chain_num > 1) 4245 rt2800_bbp_write(rt2x00dev, 86, 0x46); 4246 else 4247 rt2800_bbp_write(rt2x00dev, 86, 0); 4248 } else { 4249 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4250 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4251 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4252 if (rt2x00_rt(rt2x00dev, RT6352)) 4253 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4254 else 4255 rt2800_bbp_write(rt2x00dev, 86, 0); 4256 } 4257 4258 if (rf->channel <= 14) { 4259 if (!rt2x00_rt(rt2x00dev, RT5390) && 4260 !rt2x00_rt(rt2x00dev, RT5392) && 4261 !rt2x00_rt(rt2x00dev, RT6352)) { 4262 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4263 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4264 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4265 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4266 } else { 4267 if (rt2x00_rt(rt2x00dev, RT3593)) 4268 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4269 else 4270 rt2800_bbp_write(rt2x00dev, 82, 0x84); 4271 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4272 } 4273 if (rt2x00_rt(rt2x00dev, RT3593) || 4274 rt2x00_rt(rt2x00dev, RT3883)) 4275 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 4276 } 4277 4278 } else { 4279 if (rt2x00_rt(rt2x00dev, RT3572)) 4280 rt2800_bbp_write(rt2x00dev, 82, 0x94); 4281 else if (rt2x00_rt(rt2x00dev, RT3593) || 4282 rt2x00_rt(rt2x00dev, RT3883)) 4283 rt2800_bbp_write(rt2x00dev, 82, 0x82); 4284 else if (!rt2x00_rt(rt2x00dev, RT6352)) 4285 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 4286 4287 if (rt2x00_rt(rt2x00dev, RT3593) || 4288 rt2x00_rt(rt2x00dev, RT3883)) 4289 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 4290 4291 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 4292 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4293 else 4294 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4295 } 4296 4297 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 4298 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 4299 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 4300 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 4301 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 4302 4303 if (rt2x00_rt(rt2x00dev, RT3572)) 4304 rt2800_rfcsr_write(rt2x00dev, 8, 0); 4305 4306 if (rt2x00_rt(rt2x00dev, RT6352)) { 4307 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4308 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 4309 } else { 4310 tx_pin = 0; 4311 } 4312 4313 switch (rt2x00dev->default_ant.tx_chain_num) { 4314 case 3: 4315 /* Turn on tertiary PAs */ 4316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 4317 rf->channel > 14); 4318 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 4319 rf->channel <= 14); 4320 fallthrough; 4321 case 2: 4322 /* Turn on secondary PAs */ 4323 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 4324 rf->channel > 14); 4325 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 4326 rf->channel <= 14); 4327 fallthrough; 4328 case 1: 4329 /* Turn on primary PAs */ 4330 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 4331 rf->channel > 14); 4332 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 4333 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4334 else 4335 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 4336 rf->channel <= 14); 4337 break; 4338 } 4339 4340 switch (rt2x00dev->default_ant.rx_chain_num) { 4341 case 3: 4342 /* Turn on tertiary LNAs */ 4343 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 4344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 4345 fallthrough; 4346 case 2: 4347 /* Turn on secondary LNAs */ 4348 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 4349 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 4350 fallthrough; 4351 case 1: 4352 /* Turn on primary LNAs */ 4353 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 4354 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 4355 break; 4356 } 4357 4358 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 4359 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 4360 4361 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4362 4363 if (rt2x00_rt(rt2x00dev, RT3572)) { 4364 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 4365 4366 /* AGC init */ 4367 if (rf->channel <= 14) 4368 reg = 0x1c + (2 * rt2x00dev->lna_gain); 4369 else 4370 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4371 4372 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4373 } 4374 4375 if (rt2x00_rt(rt2x00dev, RT3593)) { 4376 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 4377 4378 /* Band selection */ 4379 if (rt2x00_is_usb(rt2x00dev) || 4380 rt2x00_is_pcie(rt2x00dev)) { 4381 /* GPIO #8 controls all paths */ 4382 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 4383 if (rf->channel <= 14) 4384 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 4385 else 4386 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 4387 } 4388 4389 /* LNA PE control. */ 4390 if (rt2x00_is_usb(rt2x00dev)) { 4391 /* GPIO #4 controls PE0 and PE1, 4392 * GPIO #7 controls PE2 4393 */ 4394 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4395 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 4396 4397 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4398 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 4399 } else if (rt2x00_is_pcie(rt2x00dev)) { 4400 /* GPIO #4 controls PE0, PE1 and PE2 */ 4401 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4402 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4403 } 4404 4405 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 4406 4407 /* AGC init */ 4408 if (rf->channel <= 14) 4409 reg = 0x1c + 2 * rt2x00dev->lna_gain; 4410 else 4411 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4412 4413 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4414 4415 usleep_range(1000, 1500); 4416 } 4417 4418 if (rt2x00_rt(rt2x00dev, RT3883)) { 4419 if (!conf_is_ht40(conf)) 4420 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4421 else 4422 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4423 4424 /* AGC init */ 4425 if (rf->channel <= 14) 4426 reg = 0x2e + rt2x00dev->lna_gain; 4427 else 4428 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); 4429 4430 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4431 4432 usleep_range(1000, 1500); 4433 } 4434 4435 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 4436 reg = 0x10; 4437 if (!conf_is_ht40(conf)) { 4438 if (rt2x00_rt(rt2x00dev, RT6352) && 4439 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4440 reg |= 0x5; 4441 } else { 4442 reg |= 0xa; 4443 } 4444 } 4445 rt2800_bbp_write(rt2x00dev, 195, 141); 4446 rt2800_bbp_write(rt2x00dev, 196, reg); 4447 4448 /* AGC init. 4449 * Despite the vendor driver using different values here for 4450 * RT6352 chip, we use 0x1c for now. This may have to be changed 4451 * once TSSI got implemented. 4452 */ 4453 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; 4454 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4455 4456 if (rt2x00_rt(rt2x00dev, RT5592)) 4457 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4458 } 4459 4460 if (rt2x00_rt(rt2x00dev, RT6352)) { 4461 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, 4462 &rt2x00dev->cap_flags)) { 4463 reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); 4464 reg |= 0x00000101; 4465 rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); 4466 4467 reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); 4468 reg |= 0x00000101; 4469 rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); 4470 4471 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73); 4472 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73); 4473 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73); 4474 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 4475 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8); 4476 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4); 4477 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05); 4478 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 4479 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8); 4480 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4); 4481 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05); 4482 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27); 4483 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8); 4484 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4); 4485 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05); 4486 rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00); 4487 4488 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 4489 0x36303636); 4490 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 4491 0x6C6C6B6C); 4492 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 4493 0x6C6C6B6C); 4494 } 4495 } 4496 4497 bbp = rt2800_bbp_read(rt2x00dev, 4); 4498 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4499 rt2800_bbp_write(rt2x00dev, 4, bbp); 4500 4501 bbp = rt2800_bbp_read(rt2x00dev, 3); 4502 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4503 rt2800_bbp_write(rt2x00dev, 3, bbp); 4504 4505 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4506 if (conf_is_ht40(conf)) { 4507 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4508 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4509 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4510 } else { 4511 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4512 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4513 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4514 } 4515 } 4516 4517 usleep_range(1000, 1500); 4518 4519 /* 4520 * Clear channel statistic counters 4521 */ 4522 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4523 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4524 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4525 4526 /* 4527 * Clear update flag 4528 */ 4529 if (rt2x00_rt(rt2x00dev, RT3352) || 4530 rt2x00_rt(rt2x00dev, RT5350)) { 4531 bbp = rt2800_bbp_read(rt2x00dev, 49); 4532 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4533 rt2800_bbp_write(rt2x00dev, 49, bbp); 4534 } 4535 } 4536 4537 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4538 { 4539 u8 tssi_bounds[9]; 4540 u8 current_tssi; 4541 u16 eeprom; 4542 u8 step; 4543 int i; 4544 4545 /* 4546 * First check if temperature compensation is supported. 4547 */ 4548 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4549 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4550 return 0; 4551 4552 /* 4553 * Read TSSI boundaries for temperature compensation from 4554 * the EEPROM. 4555 * 4556 * Array idx 0 1 2 3 4 5 6 7 8 4557 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4558 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4559 */ 4560 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4561 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4562 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4563 EEPROM_TSSI_BOUND_BG1_MINUS4); 4564 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4565 EEPROM_TSSI_BOUND_BG1_MINUS3); 4566 4567 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4568 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4569 EEPROM_TSSI_BOUND_BG2_MINUS2); 4570 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4571 EEPROM_TSSI_BOUND_BG2_MINUS1); 4572 4573 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4574 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4575 EEPROM_TSSI_BOUND_BG3_REF); 4576 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4577 EEPROM_TSSI_BOUND_BG3_PLUS1); 4578 4579 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4580 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4581 EEPROM_TSSI_BOUND_BG4_PLUS2); 4582 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4583 EEPROM_TSSI_BOUND_BG4_PLUS3); 4584 4585 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4586 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4587 EEPROM_TSSI_BOUND_BG5_PLUS4); 4588 4589 step = rt2x00_get_field16(eeprom, 4590 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4591 } else { 4592 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4593 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4594 EEPROM_TSSI_BOUND_A1_MINUS4); 4595 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4596 EEPROM_TSSI_BOUND_A1_MINUS3); 4597 4598 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4599 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4600 EEPROM_TSSI_BOUND_A2_MINUS2); 4601 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4602 EEPROM_TSSI_BOUND_A2_MINUS1); 4603 4604 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4605 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4606 EEPROM_TSSI_BOUND_A3_REF); 4607 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4608 EEPROM_TSSI_BOUND_A3_PLUS1); 4609 4610 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4611 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4612 EEPROM_TSSI_BOUND_A4_PLUS2); 4613 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4614 EEPROM_TSSI_BOUND_A4_PLUS3); 4615 4616 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4617 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4618 EEPROM_TSSI_BOUND_A5_PLUS4); 4619 4620 step = rt2x00_get_field16(eeprom, 4621 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4622 } 4623 4624 /* 4625 * Check if temperature compensation is supported. 4626 */ 4627 if (tssi_bounds[4] == 0xff || step == 0xff) 4628 return 0; 4629 4630 /* 4631 * Read current TSSI (BBP 49). 4632 */ 4633 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4634 4635 /* 4636 * Compare TSSI value (BBP49) with the compensation boundaries 4637 * from the EEPROM and increase or decrease tx power. 4638 */ 4639 for (i = 0; i <= 3; i++) { 4640 if (current_tssi > tssi_bounds[i]) 4641 break; 4642 } 4643 4644 if (i == 4) { 4645 for (i = 8; i >= 5; i--) { 4646 if (current_tssi < tssi_bounds[i]) 4647 break; 4648 } 4649 } 4650 4651 return (i - 4) * step; 4652 } 4653 4654 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4655 enum nl80211_band band) 4656 { 4657 u16 eeprom; 4658 u8 comp_en; 4659 u8 comp_type; 4660 int comp_value = 0; 4661 4662 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4663 4664 /* 4665 * HT40 compensation not required. 4666 */ 4667 if (eeprom == 0xffff || 4668 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4669 return 0; 4670 4671 if (band == NL80211_BAND_2GHZ) { 4672 comp_en = rt2x00_get_field16(eeprom, 4673 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4674 if (comp_en) { 4675 comp_type = rt2x00_get_field16(eeprom, 4676 EEPROM_TXPOWER_DELTA_TYPE_2G); 4677 comp_value = rt2x00_get_field16(eeprom, 4678 EEPROM_TXPOWER_DELTA_VALUE_2G); 4679 if (!comp_type) 4680 comp_value = -comp_value; 4681 } 4682 } else { 4683 comp_en = rt2x00_get_field16(eeprom, 4684 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4685 if (comp_en) { 4686 comp_type = rt2x00_get_field16(eeprom, 4687 EEPROM_TXPOWER_DELTA_TYPE_5G); 4688 comp_value = rt2x00_get_field16(eeprom, 4689 EEPROM_TXPOWER_DELTA_VALUE_5G); 4690 if (!comp_type) 4691 comp_value = -comp_value; 4692 } 4693 } 4694 4695 return comp_value; 4696 } 4697 4698 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4699 int power_level, int max_power) 4700 { 4701 int delta; 4702 4703 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4704 return 0; 4705 4706 /* 4707 * XXX: We don't know the maximum transmit power of our hardware since 4708 * the EEPROM doesn't expose it. We only know that we are calibrated 4709 * to 100% tx power. 4710 * 4711 * Hence, we assume the regulatory limit that cfg80211 calulated for 4712 * the current channel is our maximum and if we are requested to lower 4713 * the value we just reduce our tx power accordingly. 4714 */ 4715 delta = power_level - max_power; 4716 return min(delta, 0); 4717 } 4718 4719 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4720 enum nl80211_band band, int power_level, 4721 u8 txpower, int delta) 4722 { 4723 u16 eeprom; 4724 u8 criterion; 4725 u8 eirp_txpower; 4726 u8 eirp_txpower_criterion; 4727 u8 reg_limit; 4728 4729 if (rt2x00_rt(rt2x00dev, RT3593)) 4730 return min_t(u8, txpower, 0xc); 4731 4732 if (rt2x00_rt(rt2x00dev, RT3883)) 4733 return min_t(u8, txpower, 0xf); 4734 4735 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4736 /* 4737 * Check if eirp txpower exceed txpower_limit. 4738 * We use OFDM 6M as criterion and its eirp txpower 4739 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4740 * .11b data rate need add additional 4dbm 4741 * when calculating eirp txpower. 4742 */ 4743 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4744 EEPROM_TXPOWER_BYRATE, 4745 1); 4746 criterion = rt2x00_get_field16(eeprom, 4747 EEPROM_TXPOWER_BYRATE_RATE0); 4748 4749 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4750 4751 if (band == NL80211_BAND_2GHZ) 4752 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4753 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4754 else 4755 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4756 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4757 4758 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4759 (is_rate_b ? 4 : 0) + delta; 4760 4761 reg_limit = (eirp_txpower > power_level) ? 4762 (eirp_txpower - power_level) : 0; 4763 } else 4764 reg_limit = 0; 4765 4766 txpower = max(0, txpower + delta - reg_limit); 4767 return min_t(u8, txpower, 0xc); 4768 } 4769 4770 4771 enum { 4772 TX_PWR_CFG_0_IDX, 4773 TX_PWR_CFG_1_IDX, 4774 TX_PWR_CFG_2_IDX, 4775 TX_PWR_CFG_3_IDX, 4776 TX_PWR_CFG_4_IDX, 4777 TX_PWR_CFG_5_IDX, 4778 TX_PWR_CFG_6_IDX, 4779 TX_PWR_CFG_7_IDX, 4780 TX_PWR_CFG_8_IDX, 4781 TX_PWR_CFG_9_IDX, 4782 TX_PWR_CFG_0_EXT_IDX, 4783 TX_PWR_CFG_1_EXT_IDX, 4784 TX_PWR_CFG_2_EXT_IDX, 4785 TX_PWR_CFG_3_EXT_IDX, 4786 TX_PWR_CFG_4_EXT_IDX, 4787 TX_PWR_CFG_IDX_COUNT, 4788 }; 4789 4790 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4791 struct ieee80211_channel *chan, 4792 int power_level) 4793 { 4794 u8 txpower; 4795 u16 eeprom; 4796 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4797 unsigned int offset; 4798 enum nl80211_band band = chan->band; 4799 int delta; 4800 int i; 4801 4802 memset(regs, '\0', sizeof(regs)); 4803 4804 /* TODO: adapt TX power reduction from the rt28xx code */ 4805 4806 /* calculate temperature compensation delta */ 4807 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4808 4809 if (band == NL80211_BAND_5GHZ) 4810 offset = 16; 4811 else 4812 offset = 0; 4813 4814 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4815 offset += 8; 4816 4817 /* read the next four txpower values */ 4818 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4819 offset); 4820 4821 /* CCK 1MBS,2MBS */ 4822 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4823 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4824 txpower, delta); 4825 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4826 TX_PWR_CFG_0_CCK1_CH0, txpower); 4827 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4828 TX_PWR_CFG_0_CCK1_CH1, txpower); 4829 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4830 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4831 4832 /* CCK 5.5MBS,11MBS */ 4833 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4834 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4835 txpower, delta); 4836 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4837 TX_PWR_CFG_0_CCK5_CH0, txpower); 4838 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4839 TX_PWR_CFG_0_CCK5_CH1, txpower); 4840 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4841 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4842 4843 /* OFDM 6MBS,9MBS */ 4844 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4845 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4846 txpower, delta); 4847 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4848 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4849 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4850 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4851 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4852 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4853 4854 /* OFDM 12MBS,18MBS */ 4855 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4856 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4857 txpower, delta); 4858 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4859 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4860 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4861 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4862 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4863 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4864 4865 /* read the next four txpower values */ 4866 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4867 offset + 1); 4868 4869 /* OFDM 24MBS,36MBS */ 4870 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4871 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4872 txpower, delta); 4873 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4874 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4875 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4876 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4877 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4878 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4879 4880 /* OFDM 48MBS */ 4881 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4882 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4883 txpower, delta); 4884 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4885 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4886 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4887 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4888 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4889 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4890 4891 /* OFDM 54MBS */ 4892 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4893 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4894 txpower, delta); 4895 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4896 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4897 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4898 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4899 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4900 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4901 4902 /* read the next four txpower values */ 4903 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4904 offset + 2); 4905 4906 /* MCS 0,1 */ 4907 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4908 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4909 txpower, delta); 4910 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4911 TX_PWR_CFG_1_MCS0_CH0, txpower); 4912 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4913 TX_PWR_CFG_1_MCS0_CH1, txpower); 4914 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4915 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4916 4917 /* MCS 2,3 */ 4918 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4919 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4920 txpower, delta); 4921 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4922 TX_PWR_CFG_1_MCS2_CH0, txpower); 4923 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4924 TX_PWR_CFG_1_MCS2_CH1, txpower); 4925 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4926 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4927 4928 /* MCS 4,5 */ 4929 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4930 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4931 txpower, delta); 4932 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4933 TX_PWR_CFG_2_MCS4_CH0, txpower); 4934 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4935 TX_PWR_CFG_2_MCS4_CH1, txpower); 4936 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4937 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4938 4939 /* MCS 6 */ 4940 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4941 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4942 txpower, delta); 4943 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4944 TX_PWR_CFG_2_MCS6_CH0, txpower); 4945 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4946 TX_PWR_CFG_2_MCS6_CH1, txpower); 4947 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4948 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4949 4950 /* read the next four txpower values */ 4951 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4952 offset + 3); 4953 4954 /* MCS 7 */ 4955 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4956 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4957 txpower, delta); 4958 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4959 TX_PWR_CFG_7_MCS7_CH0, txpower); 4960 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4961 TX_PWR_CFG_7_MCS7_CH1, txpower); 4962 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4963 TX_PWR_CFG_7_MCS7_CH2, txpower); 4964 4965 /* MCS 8,9 */ 4966 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4967 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4968 txpower, delta); 4969 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4970 TX_PWR_CFG_2_MCS8_CH0, txpower); 4971 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4972 TX_PWR_CFG_2_MCS8_CH1, txpower); 4973 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4974 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4975 4976 /* MCS 10,11 */ 4977 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4978 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4979 txpower, delta); 4980 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4981 TX_PWR_CFG_2_MCS10_CH0, txpower); 4982 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4983 TX_PWR_CFG_2_MCS10_CH1, txpower); 4984 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4985 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4986 4987 /* MCS 12,13 */ 4988 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4989 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4990 txpower, delta); 4991 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4992 TX_PWR_CFG_3_MCS12_CH0, txpower); 4993 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4994 TX_PWR_CFG_3_MCS12_CH1, txpower); 4995 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4996 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4997 4998 /* read the next four txpower values */ 4999 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5000 offset + 4); 5001 5002 /* MCS 14 */ 5003 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5004 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5005 txpower, delta); 5006 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5007 TX_PWR_CFG_3_MCS14_CH0, txpower); 5008 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5009 TX_PWR_CFG_3_MCS14_CH1, txpower); 5010 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5011 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 5012 5013 /* MCS 15 */ 5014 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5015 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5016 txpower, delta); 5017 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5018 TX_PWR_CFG_8_MCS15_CH0, txpower); 5019 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5020 TX_PWR_CFG_8_MCS15_CH1, txpower); 5021 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5022 TX_PWR_CFG_8_MCS15_CH2, txpower); 5023 5024 /* MCS 16,17 */ 5025 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5026 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5027 txpower, delta); 5028 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5029 TX_PWR_CFG_5_MCS16_CH0, txpower); 5030 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5031 TX_PWR_CFG_5_MCS16_CH1, txpower); 5032 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5033 TX_PWR_CFG_5_MCS16_CH2, txpower); 5034 5035 /* MCS 18,19 */ 5036 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5037 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5038 txpower, delta); 5039 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5040 TX_PWR_CFG_5_MCS18_CH0, txpower); 5041 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5042 TX_PWR_CFG_5_MCS18_CH1, txpower); 5043 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5044 TX_PWR_CFG_5_MCS18_CH2, txpower); 5045 5046 /* read the next four txpower values */ 5047 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5048 offset + 5); 5049 5050 /* MCS 20,21 */ 5051 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5052 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5053 txpower, delta); 5054 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5055 TX_PWR_CFG_6_MCS20_CH0, txpower); 5056 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5057 TX_PWR_CFG_6_MCS20_CH1, txpower); 5058 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5059 TX_PWR_CFG_6_MCS20_CH2, txpower); 5060 5061 /* MCS 22 */ 5062 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5063 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5064 txpower, delta); 5065 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5066 TX_PWR_CFG_6_MCS22_CH0, txpower); 5067 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5068 TX_PWR_CFG_6_MCS22_CH1, txpower); 5069 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5070 TX_PWR_CFG_6_MCS22_CH2, txpower); 5071 5072 /* MCS 23 */ 5073 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5074 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5075 txpower, delta); 5076 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5077 TX_PWR_CFG_8_MCS23_CH0, txpower); 5078 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5079 TX_PWR_CFG_8_MCS23_CH1, txpower); 5080 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5081 TX_PWR_CFG_8_MCS23_CH2, txpower); 5082 5083 /* read the next four txpower values */ 5084 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5085 offset + 6); 5086 5087 /* STBC, MCS 0,1 */ 5088 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5089 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5090 txpower, delta); 5091 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5092 TX_PWR_CFG_3_STBC0_CH0, txpower); 5093 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5094 TX_PWR_CFG_3_STBC0_CH1, txpower); 5095 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5096 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 5097 5098 /* STBC, MCS 2,3 */ 5099 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5100 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5101 txpower, delta); 5102 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5103 TX_PWR_CFG_3_STBC2_CH0, txpower); 5104 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5105 TX_PWR_CFG_3_STBC2_CH1, txpower); 5106 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5107 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 5108 5109 /* STBC, MCS 4,5 */ 5110 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5111 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5112 txpower, delta); 5113 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 5114 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 5115 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 5116 txpower); 5117 5118 /* STBC, MCS 6 */ 5119 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5120 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5121 txpower, delta); 5122 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 5123 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 5124 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 5125 txpower); 5126 5127 /* read the next four txpower values */ 5128 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5129 offset + 7); 5130 5131 /* STBC, MCS 7 */ 5132 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5133 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5134 txpower, delta); 5135 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5136 TX_PWR_CFG_9_STBC7_CH0, txpower); 5137 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5138 TX_PWR_CFG_9_STBC7_CH1, txpower); 5139 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5140 TX_PWR_CFG_9_STBC7_CH2, txpower); 5141 5142 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 5143 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 5144 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 5145 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 5146 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 5147 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 5148 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 5149 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 5150 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 5151 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 5152 5153 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 5154 regs[TX_PWR_CFG_0_EXT_IDX]); 5155 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 5156 regs[TX_PWR_CFG_1_EXT_IDX]); 5157 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 5158 regs[TX_PWR_CFG_2_EXT_IDX]); 5159 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 5160 regs[TX_PWR_CFG_3_EXT_IDX]); 5161 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 5162 regs[TX_PWR_CFG_4_EXT_IDX]); 5163 5164 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 5165 rt2x00_dbg(rt2x00dev, 5166 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 5167 (band == NL80211_BAND_5GHZ) ? '5' : '2', 5168 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 5169 '4' : '2', 5170 (i > TX_PWR_CFG_9_IDX) ? 5171 (i - TX_PWR_CFG_9_IDX - 1) : i, 5172 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 5173 (unsigned long) regs[i]); 5174 } 5175 5176 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 5177 struct ieee80211_channel *chan, 5178 int power_level) 5179 { 5180 u32 reg, pwreg; 5181 u16 eeprom; 5182 u32 data, gdata; 5183 u8 t, i; 5184 enum nl80211_band band = chan->band; 5185 int delta; 5186 5187 /* Warn user if bw_comp is set in EEPROM */ 5188 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5189 5190 if (delta) 5191 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 5192 delta); 5193 5194 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 5195 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 5196 * driver does as well, though it looks kinda wrong. 5197 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 5198 * the hardware has a problem handling 0x20, and as the code initially 5199 * used a fixed offset between HT20 and HT40 rates they had to work- 5200 * around that issue and most likely just forgot about it later on. 5201 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 5202 * however, the corresponding EEPROM value is not respected by the 5203 * vendor driver, so maybe this is rather being taken care of the 5204 * TXALC and the driver doesn't need to handle it...? 5205 * Though this is all very awkward, just do as they did, as that's what 5206 * board vendors expected when they populated the EEPROM... 5207 */ 5208 for (i = 0; i < 5; i++) { 5209 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5210 EEPROM_TXPOWER_BYRATE, 5211 i * 2); 5212 5213 data = eeprom; 5214 5215 t = eeprom & 0x3f; 5216 if (t == 32) 5217 t++; 5218 5219 gdata = t; 5220 5221 t = (eeprom & 0x3f00) >> 8; 5222 if (t == 32) 5223 t++; 5224 5225 gdata |= (t << 8); 5226 5227 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5228 EEPROM_TXPOWER_BYRATE, 5229 (i * 2) + 1); 5230 5231 t = eeprom & 0x3f; 5232 if (t == 32) 5233 t++; 5234 5235 gdata |= (t << 16); 5236 5237 t = (eeprom & 0x3f00) >> 8; 5238 if (t == 32) 5239 t++; 5240 5241 gdata |= (t << 24); 5242 data |= (eeprom << 16); 5243 5244 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 5245 /* HT20 */ 5246 if (data != 0xffffffff) 5247 rt2800_register_write(rt2x00dev, 5248 TX_PWR_CFG_0 + (i * 4), 5249 data); 5250 } else { 5251 /* HT40 */ 5252 if (gdata != 0xffffffff) 5253 rt2800_register_write(rt2x00dev, 5254 TX_PWR_CFG_0 + (i * 4), 5255 gdata); 5256 } 5257 } 5258 5259 /* Aparently Ralink ran out of space in the BYRATE calibration section 5260 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 5261 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 5262 * power-offsets more space would be needed. Ralink decided to keep the 5263 * EEPROM layout untouched and rather have some shared values covering 5264 * multiple bitrates. 5265 * Populate the registers not covered by the EEPROM in the same way the 5266 * vendor driver does. 5267 */ 5268 5269 /* For OFDM 54MBS use value from OFDM 48MBS */ 5270 pwreg = 0; 5271 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 5272 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 5273 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 5274 5275 /* For MCS 7 use value from MCS 6 */ 5276 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 5277 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 5278 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 5279 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 5280 5281 /* For MCS 15 use value from MCS 14 */ 5282 pwreg = 0; 5283 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 5284 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 5285 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 5286 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 5287 5288 /* For STBC MCS 7 use value from STBC MCS 6 */ 5289 pwreg = 0; 5290 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 5291 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 5292 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 5293 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 5294 5295 rt2800_config_alc_rt6352(rt2x00dev, chan, power_level); 5296 5297 /* TODO: temperature compensation code! */ 5298 } 5299 5300 /* 5301 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 5302 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 5303 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 5304 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 5305 * Reference per rate transmit power values are located in the EEPROM at 5306 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 5307 * current conditions (i.e. band, bandwidth, temperature, user settings). 5308 */ 5309 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 5310 struct ieee80211_channel *chan, 5311 int power_level) 5312 { 5313 u8 txpower, r1; 5314 u16 eeprom; 5315 u32 reg, offset; 5316 int i, is_rate_b, delta, power_ctrl; 5317 enum nl80211_band band = chan->band; 5318 5319 /* 5320 * Calculate HT40 compensation. For 40MHz we need to add or subtract 5321 * value read from EEPROM (different for 2GHz and for 5GHz). 5322 */ 5323 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5324 5325 /* 5326 * Calculate temperature compensation. Depends on measurement of current 5327 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 5328 * to temperature or maybe other factors) is smaller or bigger than 5329 * expected. We adjust it, based on TSSI reference and boundaries values 5330 * provided in EEPROM. 5331 */ 5332 switch (rt2x00dev->chip.rt) { 5333 case RT2860: 5334 case RT2872: 5335 case RT2883: 5336 case RT3070: 5337 case RT3071: 5338 case RT3090: 5339 case RT3572: 5340 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 5341 break; 5342 default: 5343 /* TODO: temperature compensation code for other chips. */ 5344 break; 5345 } 5346 5347 /* 5348 * Decrease power according to user settings, on devices with unknown 5349 * maximum tx power. For other devices we take user power_level into 5350 * consideration on rt2800_compensate_txpower(). 5351 */ 5352 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 5353 chan->max_power); 5354 5355 /* 5356 * BBP_R1 controls TX power for all rates, it allow to set the following 5357 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 5358 * 5359 * TODO: we do not use +6 dBm option to do not increase power beyond 5360 * regulatory limit, however this could be utilized for devices with 5361 * CAPABILITY_POWER_LIMIT. 5362 */ 5363 if (delta <= -12) { 5364 power_ctrl = 2; 5365 delta += 12; 5366 } else if (delta <= -6) { 5367 power_ctrl = 1; 5368 delta += 6; 5369 } else { 5370 power_ctrl = 0; 5371 } 5372 r1 = rt2800_bbp_read(rt2x00dev, 1); 5373 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 5374 rt2800_bbp_write(rt2x00dev, 1, r1); 5375 5376 offset = TX_PWR_CFG_0; 5377 5378 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 5379 /* just to be safe */ 5380 if (offset > TX_PWR_CFG_4) 5381 break; 5382 5383 reg = rt2800_register_read(rt2x00dev, offset); 5384 5385 /* read the next four txpower values */ 5386 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5387 EEPROM_TXPOWER_BYRATE, 5388 i); 5389 5390 is_rate_b = i ? 0 : 1; 5391 /* 5392 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 5393 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 5394 * TX_PWR_CFG_4: unknown 5395 */ 5396 txpower = rt2x00_get_field16(eeprom, 5397 EEPROM_TXPOWER_BYRATE_RATE0); 5398 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5399 power_level, txpower, delta); 5400 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 5401 5402 /* 5403 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 5404 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 5405 * TX_PWR_CFG_4: unknown 5406 */ 5407 txpower = rt2x00_get_field16(eeprom, 5408 EEPROM_TXPOWER_BYRATE_RATE1); 5409 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5410 power_level, txpower, delta); 5411 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 5412 5413 /* 5414 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 5415 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 5416 * TX_PWR_CFG_4: unknown 5417 */ 5418 txpower = rt2x00_get_field16(eeprom, 5419 EEPROM_TXPOWER_BYRATE_RATE2); 5420 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5421 power_level, txpower, delta); 5422 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 5423 5424 /* 5425 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 5426 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 5427 * TX_PWR_CFG_4: unknown 5428 */ 5429 txpower = rt2x00_get_field16(eeprom, 5430 EEPROM_TXPOWER_BYRATE_RATE3); 5431 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5432 power_level, txpower, delta); 5433 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 5434 5435 /* read the next four txpower values */ 5436 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5437 EEPROM_TXPOWER_BYRATE, 5438 i + 1); 5439 5440 is_rate_b = 0; 5441 /* 5442 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 5443 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 5444 * TX_PWR_CFG_4: unknown 5445 */ 5446 txpower = rt2x00_get_field16(eeprom, 5447 EEPROM_TXPOWER_BYRATE_RATE0); 5448 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5449 power_level, txpower, delta); 5450 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 5451 5452 /* 5453 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 5454 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 5455 * TX_PWR_CFG_4: unknown 5456 */ 5457 txpower = rt2x00_get_field16(eeprom, 5458 EEPROM_TXPOWER_BYRATE_RATE1); 5459 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5460 power_level, txpower, delta); 5461 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 5462 5463 /* 5464 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 5465 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 5466 * TX_PWR_CFG_4: unknown 5467 */ 5468 txpower = rt2x00_get_field16(eeprom, 5469 EEPROM_TXPOWER_BYRATE_RATE2); 5470 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5471 power_level, txpower, delta); 5472 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 5473 5474 /* 5475 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 5476 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 5477 * TX_PWR_CFG_4: unknown 5478 */ 5479 txpower = rt2x00_get_field16(eeprom, 5480 EEPROM_TXPOWER_BYRATE_RATE3); 5481 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5482 power_level, txpower, delta); 5483 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 5484 5485 rt2800_register_write(rt2x00dev, offset, reg); 5486 5487 /* next TX_PWR_CFG register */ 5488 offset += 4; 5489 } 5490 } 5491 5492 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5493 struct ieee80211_channel *chan, 5494 int power_level) 5495 { 5496 if (rt2x00_rt(rt2x00dev, RT3593) || 5497 rt2x00_rt(rt2x00dev, RT3883)) 5498 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5499 else if (rt2x00_rt(rt2x00dev, RT6352)) 5500 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5501 else 5502 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5503 } 5504 5505 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5506 { 5507 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5508 rt2x00dev->tx_power); 5509 } 5510 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5511 5512 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5513 { 5514 u32 tx_pin; 5515 u8 rfcsr; 5516 unsigned long min_sleep = 0; 5517 5518 /* 5519 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5520 * designed to be controlled in oscillation frequency by a voltage 5521 * input. Maybe the temperature will affect the frequency of 5522 * oscillation to be shifted. The VCO calibration will be called 5523 * periodically to adjust the frequency to be precision. 5524 */ 5525 5526 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5527 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5528 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5529 5530 switch (rt2x00dev->chip.rf) { 5531 case RF2020: 5532 case RF3020: 5533 case RF3021: 5534 case RF3022: 5535 case RF3320: 5536 case RF3052: 5537 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5538 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5539 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5540 break; 5541 case RF3053: 5542 case RF3070: 5543 case RF3290: 5544 case RF3853: 5545 case RF5350: 5546 case RF5360: 5547 case RF5362: 5548 case RF5370: 5549 case RF5372: 5550 case RF5390: 5551 case RF5392: 5552 case RF5592: 5553 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5554 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5555 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5556 min_sleep = 1000; 5557 break; 5558 case RF7620: 5559 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5560 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5561 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5562 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5563 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5564 min_sleep = 2000; 5565 break; 5566 default: 5567 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5568 rt2x00dev->chip.rf); 5569 return; 5570 } 5571 5572 if (min_sleep > 0) 5573 usleep_range(min_sleep, min_sleep * 2); 5574 5575 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5576 if (rt2x00dev->rf_channel <= 14) { 5577 switch (rt2x00dev->default_ant.tx_chain_num) { 5578 case 3: 5579 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5580 fallthrough; 5581 case 2: 5582 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5583 fallthrough; 5584 case 1: 5585 default: 5586 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5587 break; 5588 } 5589 } else { 5590 switch (rt2x00dev->default_ant.tx_chain_num) { 5591 case 3: 5592 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5593 fallthrough; 5594 case 2: 5595 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5596 fallthrough; 5597 case 1: 5598 default: 5599 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5600 break; 5601 } 5602 } 5603 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5604 5605 if (rt2x00_rt(rt2x00dev, RT6352)) { 5606 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5607 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5608 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5609 rt2800_bbp_write(rt2x00dev, 195, 128); 5610 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5611 rt2800_bbp_write(rt2x00dev, 195, 170); 5612 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5613 rt2800_bbp_write(rt2x00dev, 195, 171); 5614 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5615 } else { 5616 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5617 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5618 rt2800_bbp_write(rt2x00dev, 195, 128); 5619 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5620 rt2800_bbp_write(rt2x00dev, 195, 170); 5621 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5622 rt2800_bbp_write(rt2x00dev, 195, 171); 5623 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5624 } 5625 5626 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5627 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5628 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5629 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5630 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5631 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5632 } 5633 5634 /* On 11A, We should delay and wait RF/BBP to be stable 5635 * and the appropriate time should be 1000 micro seconds 5636 * 2005/06/05 - On 11G, we also need this delay time. 5637 * Otherwise it's difficult to pass the WHQL. 5638 */ 5639 usleep_range(1000, 1500); 5640 } 5641 } 5642 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5643 5644 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5645 struct rt2x00lib_conf *libconf) 5646 { 5647 u32 reg; 5648 5649 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5650 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5651 libconf->conf->short_frame_max_tx_count); 5652 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5653 libconf->conf->long_frame_max_tx_count); 5654 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5655 } 5656 5657 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5658 struct rt2x00lib_conf *libconf) 5659 { 5660 enum dev_state state = 5661 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5662 STATE_SLEEP : STATE_AWAKE; 5663 u32 reg; 5664 5665 if (state == STATE_SLEEP) { 5666 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5667 5668 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5669 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5670 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5671 libconf->conf->listen_interval - 1); 5672 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5673 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5674 5675 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5676 } else { 5677 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5678 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5679 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5680 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5681 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5682 5683 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5684 } 5685 } 5686 5687 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5688 struct rt2x00lib_conf *libconf, 5689 const unsigned int flags) 5690 { 5691 /* Always recalculate LNA gain before changing configuration */ 5692 rt2800_config_lna_gain(rt2x00dev, libconf); 5693 5694 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5695 /* 5696 * To provide correct survey data for survey-based ACS algorithm 5697 * we have to save survey data for current channel before switching. 5698 */ 5699 rt2800_update_survey(rt2x00dev); 5700 5701 rt2800_config_channel(rt2x00dev, libconf->conf, 5702 &libconf->rf, &libconf->channel); 5703 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5704 libconf->conf->power_level); 5705 } 5706 if (flags & IEEE80211_CONF_CHANGE_POWER) 5707 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5708 libconf->conf->power_level); 5709 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5710 rt2800_config_retry_limit(rt2x00dev, libconf); 5711 if (flags & IEEE80211_CONF_CHANGE_PS) 5712 rt2800_config_ps(rt2x00dev, libconf); 5713 } 5714 EXPORT_SYMBOL_GPL(rt2800_config); 5715 5716 /* 5717 * Link tuning 5718 */ 5719 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5720 { 5721 u32 reg; 5722 5723 /* 5724 * Update FCS error count from register. 5725 */ 5726 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5727 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5728 } 5729 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5730 5731 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5732 { 5733 u8 vgc; 5734 5735 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5736 if (rt2x00_rt(rt2x00dev, RT3070) || 5737 rt2x00_rt(rt2x00dev, RT3071) || 5738 rt2x00_rt(rt2x00dev, RT3090) || 5739 rt2x00_rt(rt2x00dev, RT3290) || 5740 rt2x00_rt(rt2x00dev, RT3390) || 5741 rt2x00_rt(rt2x00dev, RT3572) || 5742 rt2x00_rt(rt2x00dev, RT3593) || 5743 rt2x00_rt(rt2x00dev, RT5390) || 5744 rt2x00_rt(rt2x00dev, RT5392) || 5745 rt2x00_rt(rt2x00dev, RT5592) || 5746 rt2x00_rt(rt2x00dev, RT6352)) 5747 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5748 else 5749 vgc = 0x2e + rt2x00dev->lna_gain; 5750 } else { /* 5GHZ band */ 5751 if (rt2x00_rt(rt2x00dev, RT3593) || 5752 rt2x00_rt(rt2x00dev, RT3883)) 5753 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5754 else if (rt2x00_rt(rt2x00dev, RT5592)) 5755 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5756 else { 5757 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5758 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5759 else 5760 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5761 } 5762 } 5763 5764 return vgc; 5765 } 5766 5767 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5768 struct link_qual *qual, u8 vgc_level) 5769 { 5770 if (qual->vgc_level != vgc_level) { 5771 if (rt2x00_rt(rt2x00dev, RT3572) || 5772 rt2x00_rt(rt2x00dev, RT3593) || 5773 rt2x00_rt(rt2x00dev, RT3883) || 5774 rt2x00_rt(rt2x00dev, RT6352)) { 5775 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5776 vgc_level); 5777 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5778 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5779 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5780 } else { 5781 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5782 } 5783 5784 qual->vgc_level = vgc_level; 5785 qual->vgc_level_reg = vgc_level; 5786 } 5787 } 5788 5789 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5790 { 5791 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5792 } 5793 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5794 5795 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5796 const u32 count) 5797 { 5798 u8 vgc; 5799 5800 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5801 return; 5802 5803 /* When RSSI is better than a certain threshold, increase VGC 5804 * with a chip specific value in order to improve the balance 5805 * between sensibility and noise isolation. 5806 */ 5807 5808 vgc = rt2800_get_default_vgc(rt2x00dev); 5809 5810 switch (rt2x00dev->chip.rt) { 5811 case RT3572: 5812 case RT3593: 5813 if (qual->rssi > -65) { 5814 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5815 vgc += 0x20; 5816 else 5817 vgc += 0x10; 5818 } 5819 break; 5820 5821 case RT3883: 5822 if (qual->rssi > -65) 5823 vgc += 0x10; 5824 break; 5825 5826 case RT5592: 5827 if (qual->rssi > -65) 5828 vgc += 0x20; 5829 break; 5830 5831 default: 5832 if (qual->rssi > -80) 5833 vgc += 0x10; 5834 break; 5835 } 5836 5837 rt2800_set_vgc(rt2x00dev, qual, vgc); 5838 } 5839 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5840 5841 /* 5842 * Initialization functions. 5843 */ 5844 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5845 { 5846 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5847 u32 reg; 5848 u16 eeprom; 5849 unsigned int i; 5850 int ret; 5851 5852 rt2800_disable_wpdma(rt2x00dev); 5853 5854 ret = rt2800_drv_init_registers(rt2x00dev); 5855 if (ret) 5856 return ret; 5857 5858 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5859 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5860 5861 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5862 5863 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5864 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5865 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5866 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5867 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5868 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5869 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5870 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5871 5872 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5873 5874 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5875 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5876 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5877 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5878 5879 if (rt2x00_rt(rt2x00dev, RT3290)) { 5880 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5881 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5882 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5883 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5884 } 5885 5886 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5887 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5888 rt2x00_set_field32(®, LDO0_EN, 1); 5889 rt2x00_set_field32(®, LDO_BGSEL, 3); 5890 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5891 } 5892 5893 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5894 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5895 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5896 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5897 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5898 5899 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5900 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5901 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5902 5903 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5904 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5905 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5906 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5907 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5908 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5909 5910 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5911 rt2x00_set_field32(®, PLL_CONTROL, 1); 5912 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5913 } 5914 5915 if (rt2x00_rt(rt2x00dev, RT3071) || 5916 rt2x00_rt(rt2x00dev, RT3090) || 5917 rt2x00_rt(rt2x00dev, RT3290) || 5918 rt2x00_rt(rt2x00dev, RT3390)) { 5919 5920 if (rt2x00_rt(rt2x00dev, RT3290)) 5921 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5922 0x00000404); 5923 else 5924 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5925 0x00000400); 5926 5927 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5928 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5929 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5930 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5931 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5932 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5933 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5934 0x0000002c); 5935 else 5936 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5937 0x0000000f); 5938 } else { 5939 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5940 } 5941 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5942 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5943 5944 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5945 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5946 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5947 } else { 5948 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5949 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5950 } 5951 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5952 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5953 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5954 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5955 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5956 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5957 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5958 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5959 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5960 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5961 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5962 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5963 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5964 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5965 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5966 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5967 if (rt2x00_get_field16(eeprom, 5968 EEPROM_NIC_CONF1_DAC_TEST)) 5969 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5970 0x0000001f); 5971 else 5972 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5973 0x0000000f); 5974 } else { 5975 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5976 0x00000000); 5977 } 5978 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5979 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5980 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5981 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); 5982 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); 5983 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); 5984 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5985 rt2x00_rt(rt2x00dev, RT5392)) { 5986 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5987 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5988 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5989 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5990 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5991 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5992 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5993 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5994 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5995 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5996 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5997 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001); 5998 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5999 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 6000 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 6001 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 6002 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 6003 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 6004 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 6005 0x3630363A); 6006 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 6007 0x3630363A); 6008 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 6009 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 6010 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 6011 } else { 6012 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 6013 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 6014 } 6015 6016 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 6017 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 6018 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 6019 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 6020 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 6021 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 6022 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 6023 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 6024 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 6025 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 6026 6027 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 6028 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 6029 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 6030 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 6031 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 6032 6033 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 6034 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 6035 if (rt2x00_is_usb(rt2x00dev)) { 6036 drv_data->max_psdu = 3; 6037 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 6038 rt2x00_rt(rt2x00dev, RT2883) || 6039 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 6040 drv_data->max_psdu = 2; 6041 } else { 6042 drv_data->max_psdu = 1; 6043 } 6044 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 6045 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 6046 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 6047 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 6048 6049 reg = rt2800_register_read(rt2x00dev, LED_CFG); 6050 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 6051 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 6052 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 6053 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 6054 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 6055 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 6056 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 6057 rt2800_register_write(rt2x00dev, LED_CFG, reg); 6058 6059 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 6060 6061 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 6062 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 6063 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 6064 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 6065 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 6066 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 6067 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 6068 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 6069 6070 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 6071 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 6072 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 6073 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 6074 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 6075 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 6076 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 6077 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 6078 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 6079 6080 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 6081 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 6082 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 6083 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 6084 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6085 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6086 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6087 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6088 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6089 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6090 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 6091 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 6092 6093 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 6094 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 6095 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 6096 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 6097 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6098 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6099 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6100 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6101 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6102 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6103 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 6104 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 6105 6106 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 6107 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 6108 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 6109 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6110 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6111 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6112 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6113 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6114 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6115 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6116 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 6117 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 6118 6119 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 6120 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 6121 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 6122 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6123 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6124 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6125 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6126 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6127 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6128 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6129 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 6130 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 6131 6132 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 6133 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 6134 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 6135 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6136 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6137 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6138 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6139 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6140 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6141 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6142 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 6143 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 6144 6145 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 6146 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 6147 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 6148 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6149 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6150 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6151 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6152 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6153 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6154 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6155 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 6156 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 6157 6158 if (rt2x00_is_usb(rt2x00dev)) { 6159 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 6160 6161 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 6162 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 6163 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 6164 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 6165 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 6166 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 6167 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 6168 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 6169 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 6170 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 6171 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6172 } 6173 6174 /* 6175 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 6176 * although it is reserved. 6177 */ 6178 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 6179 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 6180 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 6181 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 6182 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 6183 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 6184 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 6185 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 6186 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 6187 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 6188 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 6189 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 6190 6191 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 6192 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 6193 6194 if (rt2x00_rt(rt2x00dev, RT3883)) { 6195 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); 6196 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); 6197 } 6198 6199 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 6200 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 6201 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 6202 IEEE80211_MAX_RTS_THRESHOLD); 6203 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 6204 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 6205 6206 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 6207 6208 /* 6209 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 6210 * time should be set to 16. However, the original Ralink driver uses 6211 * 16 for both and indeed using a value of 10 for CCK SIFS results in 6212 * connection problems with 11g + CTS protection. Hence, use the same 6213 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 6214 */ 6215 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 6216 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 6217 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 6218 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 6219 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 6220 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 6221 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 6222 6223 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 6224 6225 /* 6226 * ASIC will keep garbage value after boot, clear encryption keys. 6227 */ 6228 for (i = 0; i < 4; i++) 6229 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0); 6230 6231 for (i = 0; i < 256; i++) { 6232 rt2800_config_wcid(rt2x00dev, NULL, i); 6233 rt2800_delete_wcid_attr(rt2x00dev, i); 6234 } 6235 6236 /* 6237 * Clear encryption initialization vectors on start, but keep them 6238 * for watchdog reset. Otherwise we will have wrong IVs and not be 6239 * able to keep connections after reset. 6240 */ 6241 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 6242 for (i = 0; i < 256; i++) 6243 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 6244 6245 /* 6246 * Clear all beacons 6247 */ 6248 for (i = 0; i < 8; i++) 6249 rt2800_clear_beacon_register(rt2x00dev, i); 6250 6251 if (rt2x00_is_usb(rt2x00dev)) { 6252 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6253 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 6254 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6255 } else if (rt2x00_is_pcie(rt2x00dev)) { 6256 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6257 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 6258 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6259 } else if (rt2x00_is_soc(rt2x00dev)) { 6260 struct clk *clk = clk_get_sys("bus", NULL); 6261 int rate; 6262 6263 if (IS_ERR(clk)) { 6264 clk = clk_get_sys("cpu", NULL); 6265 6266 if (IS_ERR(clk)) { 6267 rate = 125; 6268 } else { 6269 rate = clk_get_rate(clk) / 3000000; 6270 clk_put(clk); 6271 } 6272 } else { 6273 rate = clk_get_rate(clk) / 1000000; 6274 clk_put(clk); 6275 } 6276 6277 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6278 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate); 6279 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6280 } 6281 6282 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 6283 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 6284 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 6285 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 6286 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 6287 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 6288 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 6289 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 6290 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 6291 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 6292 6293 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 6294 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 6295 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 6296 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 6297 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 6298 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 6299 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 6300 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 6301 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 6302 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 6303 6304 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 6305 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 6306 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 6307 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 6308 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 6309 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 6310 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 6311 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 6312 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 6313 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 6314 6315 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 6316 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 6317 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 6318 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 6319 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 6320 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 6321 6322 /* 6323 * Do not force the BA window size, we use the TXWI to set it 6324 */ 6325 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 6326 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 6327 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 6328 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 6329 6330 /* 6331 * We must clear the error counters. 6332 * These registers are cleared on read, 6333 * so we may pass a useless variable to store the value. 6334 */ 6335 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 6336 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 6337 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 6338 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 6339 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 6340 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 6341 6342 /* 6343 * Setup leadtime for pre tbtt interrupt to 6ms 6344 */ 6345 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 6346 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 6347 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 6348 6349 /* 6350 * Set up channel statistics timer 6351 */ 6352 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 6353 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 6354 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 6355 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 6356 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 6357 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 6358 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 6359 6360 return 0; 6361 } 6362 6363 6364 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 6365 { 6366 u8 value; 6367 6368 value = rt2800_bbp_read(rt2x00dev, 4); 6369 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 6370 rt2800_bbp_write(rt2x00dev, 4, value); 6371 } 6372 6373 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 6374 { 6375 rt2800_bbp_write(rt2x00dev, 142, 1); 6376 rt2800_bbp_write(rt2x00dev, 143, 57); 6377 } 6378 6379 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 6380 { 6381 static const u8 glrt_table[] = { 6382 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 6383 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 6384 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 6385 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 6386 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 6387 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 6388 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 6389 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 6390 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 6391 }; 6392 int i; 6393 6394 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 6395 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 6396 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 6397 } 6398 }; 6399 6400 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 6401 { 6402 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6403 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6404 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 6405 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6406 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6407 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6408 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6409 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6410 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 6411 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6412 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6413 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6414 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6415 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6416 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6417 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6418 } 6419 6420 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 6421 { 6422 u16 eeprom; 6423 u8 value; 6424 6425 value = rt2800_bbp_read(rt2x00dev, 138); 6426 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6427 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6428 value |= 0x20; 6429 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6430 value &= ~0x02; 6431 rt2800_bbp_write(rt2x00dev, 138, value); 6432 } 6433 6434 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 6435 { 6436 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6437 6438 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6439 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6440 6441 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6442 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6443 6444 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6445 6446 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6447 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6448 6449 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6450 6451 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6452 6453 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6454 6455 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6456 6457 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6458 6459 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6460 6461 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6462 6463 rt2800_bbp_write(rt2x00dev, 105, 0x01); 6464 6465 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6466 } 6467 6468 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 6469 { 6470 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6471 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6472 6473 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 6474 rt2800_bbp_write(rt2x00dev, 69, 0x16); 6475 rt2800_bbp_write(rt2x00dev, 73, 0x12); 6476 } else { 6477 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6478 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6479 } 6480 6481 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6482 6483 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6484 6485 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6486 6487 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6488 6489 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 6490 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6491 else 6492 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6493 6494 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6495 6496 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6497 6498 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6499 6500 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6501 6502 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6503 6504 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6505 } 6506 6507 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6508 { 6509 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6510 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6511 6512 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6513 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6514 6515 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6516 6517 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6518 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6519 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6520 6521 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6522 6523 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6524 6525 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6526 6527 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6528 6529 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6530 6531 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6532 6533 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6534 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6535 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6536 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6537 else 6538 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6539 6540 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6541 6542 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6543 6544 if (rt2x00_rt(rt2x00dev, RT3071) || 6545 rt2x00_rt(rt2x00dev, RT3090)) 6546 rt2800_disable_unused_dac_adc(rt2x00dev); 6547 } 6548 6549 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6550 { 6551 u8 value; 6552 6553 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6554 6555 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6556 6557 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6558 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6559 6560 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6561 6562 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6563 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6564 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6565 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6566 6567 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6568 6569 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6570 6571 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6572 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6573 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6574 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6575 6576 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6577 6578 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6579 6580 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6581 6582 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6583 6584 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6585 6586 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6587 6588 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6589 6590 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6591 6592 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6593 6594 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6595 6596 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6597 6598 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6599 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6600 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6601 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6602 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6603 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6604 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6605 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6606 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6607 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6608 6609 value = rt2800_bbp_read(rt2x00dev, 47); 6610 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6611 rt2800_bbp_write(rt2x00dev, 47, value); 6612 6613 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6614 value = rt2800_bbp_read(rt2x00dev, 3); 6615 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6616 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6617 rt2800_bbp_write(rt2x00dev, 3, value); 6618 } 6619 6620 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6621 { 6622 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6623 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6624 6625 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6626 6627 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6628 6629 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6630 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6631 6632 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6633 6634 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6635 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6636 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6637 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6638 6639 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6640 6641 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6642 6643 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6644 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6645 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6646 6647 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6648 6649 if (rt2x00_rt(rt2x00dev, RT5350)) { 6650 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6651 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6652 } else { 6653 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6654 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6655 } 6656 6657 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6658 6659 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6660 6661 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6662 6663 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6664 6665 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6666 6667 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6668 6669 if (rt2x00_rt(rt2x00dev, RT5350)) { 6670 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6671 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6672 } else { 6673 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6674 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6675 } 6676 6677 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6678 6679 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6680 6681 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6682 /* Set ITxBF timeout to 0x9c40=1000msec */ 6683 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6684 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6685 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6686 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6687 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6688 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6689 /* Reprogram the inband interface to put right values in RXWI */ 6690 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6691 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6692 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6693 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6694 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6695 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6696 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6697 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6698 6699 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6700 6701 if (rt2x00_rt(rt2x00dev, RT5350)) { 6702 /* Antenna Software OFDM */ 6703 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6704 /* Antenna Software CCK */ 6705 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6706 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6707 /* Clear previously selected antenna */ 6708 rt2800_bbp_write(rt2x00dev, 154, 0); 6709 } 6710 } 6711 6712 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6713 { 6714 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6715 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6716 6717 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6718 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6719 6720 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6721 6722 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6723 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6724 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6725 6726 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6727 6728 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6729 6730 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6731 6732 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6733 6734 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6735 6736 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6737 6738 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6739 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6740 else 6741 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6742 6743 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6744 6745 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6746 6747 rt2800_disable_unused_dac_adc(rt2x00dev); 6748 } 6749 6750 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6751 { 6752 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6753 6754 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6755 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6756 6757 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6758 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6759 6760 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6761 6762 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6763 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6764 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6765 6766 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6767 6768 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6769 6770 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6771 6772 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6773 6774 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6775 6776 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6777 6778 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6779 6780 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6781 6782 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6783 6784 rt2800_disable_unused_dac_adc(rt2x00dev); 6785 } 6786 6787 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6788 { 6789 rt2800_init_bbp_early(rt2x00dev); 6790 6791 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6792 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6793 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6794 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6795 6796 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6797 6798 /* Enable DC filter */ 6799 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6800 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6801 } 6802 6803 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev) 6804 { 6805 rt2800_init_bbp_early(rt2x00dev); 6806 6807 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6808 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6809 6810 rt2800_bbp_write(rt2x00dev, 86, 0x46); 6811 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6812 6813 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6814 6815 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6816 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6817 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6818 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6819 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6820 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6821 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6822 6823 /* Set ITxBF timeout to 0x9C40=1000msec */ 6824 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6825 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6826 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6827 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6828 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6829 6830 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6831 6832 /* Reprogram the inband interface to put right values in RXWI */ 6833 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6834 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6835 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6836 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6837 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6838 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6839 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6840 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6841 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6842 } 6843 6844 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6845 { 6846 int ant, div_mode; 6847 u16 eeprom; 6848 u8 value; 6849 6850 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6851 6852 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6853 6854 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6855 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6856 6857 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6858 6859 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6860 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6861 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6862 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6863 6864 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6865 6866 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6867 6868 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6869 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6870 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6871 6872 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6873 6874 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6875 6876 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6877 6878 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6879 6880 if (rt2x00_rt(rt2x00dev, RT5392)) 6881 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6882 6883 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6884 6885 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6886 6887 if (rt2x00_rt(rt2x00dev, RT5392)) { 6888 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6889 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6890 } 6891 6892 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6893 6894 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6895 6896 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6897 6898 if (rt2x00_rt(rt2x00dev, RT5390)) 6899 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6900 else if (rt2x00_rt(rt2x00dev, RT5392)) 6901 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6902 else 6903 WARN_ON(1); 6904 6905 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6906 6907 if (rt2x00_rt(rt2x00dev, RT5392)) { 6908 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6909 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6910 } 6911 6912 rt2800_disable_unused_dac_adc(rt2x00dev); 6913 6914 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6915 div_mode = rt2x00_get_field16(eeprom, 6916 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6917 ant = (div_mode == 3) ? 1 : 0; 6918 6919 /* check if this is a Bluetooth combo card */ 6920 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6921 u32 reg; 6922 6923 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6924 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6925 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6926 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6927 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6928 if (ant == 0) 6929 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6930 else if (ant == 1) 6931 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6932 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6933 } 6934 6935 /* These chips have hardware RX antenna diversity */ 6936 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6937 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6938 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6939 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6940 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6941 } 6942 6943 value = rt2800_bbp_read(rt2x00dev, 152); 6944 if (ant == 0) 6945 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6946 else 6947 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6948 rt2800_bbp_write(rt2x00dev, 152, value); 6949 6950 rt2800_init_freq_calibration(rt2x00dev); 6951 } 6952 6953 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6954 { 6955 int ant, div_mode; 6956 u16 eeprom; 6957 u8 value; 6958 6959 rt2800_init_bbp_early(rt2x00dev); 6960 6961 value = rt2800_bbp_read(rt2x00dev, 105); 6962 rt2x00_set_field8(&value, BBP105_MLD, 6963 rt2x00dev->default_ant.rx_chain_num == 2); 6964 rt2800_bbp_write(rt2x00dev, 105, value); 6965 6966 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6967 6968 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6969 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6970 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6971 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6972 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6973 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6974 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6975 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6976 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6977 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6978 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6979 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6980 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6981 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6982 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6983 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6984 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6985 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6986 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6987 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6988 /* FIXME BBP105 owerwrite */ 6989 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6990 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6991 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6992 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6993 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6994 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6995 6996 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6997 rt2800_init_bbp_5592_glrt(rt2x00dev); 6998 6999 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7000 7001 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7002 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 7003 ant = (div_mode == 3) ? 1 : 0; 7004 value = rt2800_bbp_read(rt2x00dev, 152); 7005 if (ant == 0) { 7006 /* Main antenna */ 7007 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 7008 } else { 7009 /* Auxiliary antenna */ 7010 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 7011 } 7012 rt2800_bbp_write(rt2x00dev, 152, value); 7013 7014 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 7015 value = rt2800_bbp_read(rt2x00dev, 254); 7016 rt2x00_set_field8(&value, BBP254_BIT7, 1); 7017 rt2800_bbp_write(rt2x00dev, 254, value); 7018 } 7019 7020 rt2800_init_freq_calibration(rt2x00dev); 7021 7022 rt2800_bbp_write(rt2x00dev, 84, 0x19); 7023 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 7024 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 7025 } 7026 7027 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 7028 { 7029 u8 bbp; 7030 7031 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 7032 bbp = rt2800_bbp_read(rt2x00dev, 105); 7033 rt2x00_set_field8(&bbp, BBP105_MLD, 7034 rt2x00dev->default_ant.rx_chain_num == 2); 7035 rt2800_bbp_write(rt2x00dev, 105, bbp); 7036 7037 /* Avoid data loss and CRC errors */ 7038 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7039 7040 /* Fix I/Q swap issue */ 7041 bbp = rt2800_bbp_read(rt2x00dev, 1); 7042 bbp |= 0x04; 7043 rt2800_bbp_write(rt2x00dev, 1, bbp); 7044 7045 /* BBP for G band */ 7046 rt2800_bbp_write(rt2x00dev, 3, 0x08); 7047 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 7048 rt2800_bbp_write(rt2x00dev, 6, 0x08); 7049 rt2800_bbp_write(rt2x00dev, 14, 0x09); 7050 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 7051 rt2800_bbp_write(rt2x00dev, 16, 0x01); 7052 rt2800_bbp_write(rt2x00dev, 20, 0x06); 7053 rt2800_bbp_write(rt2x00dev, 21, 0x00); 7054 rt2800_bbp_write(rt2x00dev, 22, 0x00); 7055 rt2800_bbp_write(rt2x00dev, 27, 0x00); 7056 rt2800_bbp_write(rt2x00dev, 28, 0x00); 7057 rt2800_bbp_write(rt2x00dev, 30, 0x00); 7058 rt2800_bbp_write(rt2x00dev, 31, 0x48); 7059 rt2800_bbp_write(rt2x00dev, 47, 0x40); 7060 rt2800_bbp_write(rt2x00dev, 62, 0x00); 7061 rt2800_bbp_write(rt2x00dev, 63, 0x00); 7062 rt2800_bbp_write(rt2x00dev, 64, 0x00); 7063 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 7064 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 7065 rt2800_bbp_write(rt2x00dev, 67, 0x20); 7066 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 7067 rt2800_bbp_write(rt2x00dev, 69, 0x10); 7068 rt2800_bbp_write(rt2x00dev, 70, 0x05); 7069 rt2800_bbp_write(rt2x00dev, 73, 0x18); 7070 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 7071 rt2800_bbp_write(rt2x00dev, 75, 0x60); 7072 rt2800_bbp_write(rt2x00dev, 76, 0x44); 7073 rt2800_bbp_write(rt2x00dev, 77, 0x59); 7074 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 7075 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 7076 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 7077 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 7078 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 7079 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 7080 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 7081 rt2800_bbp_write(rt2x00dev, 86, 0x38); 7082 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7083 rt2800_bbp_write(rt2x00dev, 91, 0x04); 7084 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7085 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 7086 rt2800_bbp_write(rt2x00dev, 96, 0x00); 7087 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 7088 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7089 /* FIXME BBP105 owerwrite */ 7090 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 7091 rt2800_bbp_write(rt2x00dev, 106, 0x12); 7092 rt2800_bbp_write(rt2x00dev, 109, 0x00); 7093 rt2800_bbp_write(rt2x00dev, 134, 0x10); 7094 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 7095 rt2800_bbp_write(rt2x00dev, 137, 0x04); 7096 rt2800_bbp_write(rt2x00dev, 142, 0x30); 7097 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 7098 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 7099 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 7100 rt2800_bbp_write(rt2x00dev, 162, 0x77); 7101 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 7102 rt2800_bbp_write(rt2x00dev, 164, 0x00); 7103 rt2800_bbp_write(rt2x00dev, 165, 0x00); 7104 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7105 rt2800_bbp_write(rt2x00dev, 187, 0x00); 7106 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7107 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7108 rt2800_bbp_write(rt2x00dev, 187, 0x01); 7109 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7110 rt2800_bbp_write(rt2x00dev, 189, 0x00); 7111 7112 rt2800_bbp_write(rt2x00dev, 91, 0x06); 7113 rt2800_bbp_write(rt2x00dev, 92, 0x04); 7114 rt2800_bbp_write(rt2x00dev, 93, 0x54); 7115 rt2800_bbp_write(rt2x00dev, 99, 0x50); 7116 rt2800_bbp_write(rt2x00dev, 148, 0x84); 7117 rt2800_bbp_write(rt2x00dev, 167, 0x80); 7118 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 7119 rt2800_bbp_write(rt2x00dev, 106, 0x13); 7120 7121 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 7122 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 7123 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 7124 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 7125 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 7126 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 7127 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 7128 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 7129 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 7130 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 7131 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 7132 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 7133 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 7134 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 7135 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 7136 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 7137 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 7138 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 7139 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 7140 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 7141 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 7142 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 7143 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 7144 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 7145 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 7146 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 7147 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 7148 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 7149 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 7150 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 7151 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 7152 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 7153 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 7154 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 7155 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 7156 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 7157 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 7158 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 7159 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 7160 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 7161 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 7162 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 7163 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 7164 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 7165 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 7166 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 7167 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 7168 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 7169 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 7170 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 7171 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 7172 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 7173 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 7174 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 7175 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 7176 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 7177 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 7178 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 7179 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 7180 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 7181 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 7182 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 7183 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 7184 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 7185 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 7186 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 7187 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 7188 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 7189 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 7190 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 7191 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 7192 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 7193 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 7194 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 7195 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 7196 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 7197 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 7198 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 7199 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 7200 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 7201 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 7202 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 7203 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 7204 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 7205 7206 /* BBP for G band DCOC function */ 7207 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 7208 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 7209 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 7210 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 7211 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 7212 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 7213 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 7214 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 7215 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 7216 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 7217 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 7218 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 7219 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 7220 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 7221 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 7222 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 7223 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 7224 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 7225 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 7226 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7227 7228 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7229 } 7230 7231 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 7232 { 7233 unsigned int i; 7234 u16 eeprom; 7235 u8 reg_id; 7236 u8 value; 7237 7238 if (rt2800_is_305x_soc(rt2x00dev)) 7239 rt2800_init_bbp_305x_soc(rt2x00dev); 7240 7241 switch (rt2x00dev->chip.rt) { 7242 case RT2860: 7243 case RT2872: 7244 case RT2883: 7245 rt2800_init_bbp_28xx(rt2x00dev); 7246 break; 7247 case RT3070: 7248 case RT3071: 7249 case RT3090: 7250 rt2800_init_bbp_30xx(rt2x00dev); 7251 break; 7252 case RT3290: 7253 rt2800_init_bbp_3290(rt2x00dev); 7254 break; 7255 case RT3352: 7256 case RT5350: 7257 rt2800_init_bbp_3352(rt2x00dev); 7258 break; 7259 case RT3390: 7260 rt2800_init_bbp_3390(rt2x00dev); 7261 break; 7262 case RT3572: 7263 rt2800_init_bbp_3572(rt2x00dev); 7264 break; 7265 case RT3593: 7266 rt2800_init_bbp_3593(rt2x00dev); 7267 return; 7268 case RT3883: 7269 rt2800_init_bbp_3883(rt2x00dev); 7270 return; 7271 case RT5390: 7272 case RT5392: 7273 rt2800_init_bbp_53xx(rt2x00dev); 7274 break; 7275 case RT5592: 7276 rt2800_init_bbp_5592(rt2x00dev); 7277 return; 7278 case RT6352: 7279 rt2800_init_bbp_6352(rt2x00dev); 7280 break; 7281 } 7282 7283 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 7284 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 7285 EEPROM_BBP_START, i); 7286 7287 if (eeprom != 0xffff && eeprom != 0x0000) { 7288 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 7289 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 7290 rt2800_bbp_write(rt2x00dev, reg_id, value); 7291 } 7292 } 7293 } 7294 7295 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 7296 { 7297 u32 reg; 7298 7299 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 7300 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 7301 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 7302 } 7303 7304 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 7305 u8 filter_target) 7306 { 7307 unsigned int i; 7308 u8 bbp; 7309 u8 rfcsr; 7310 u8 passband; 7311 u8 stopband; 7312 u8 overtuned = 0; 7313 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 7314 7315 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7316 7317 bbp = rt2800_bbp_read(rt2x00dev, 4); 7318 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 7319 rt2800_bbp_write(rt2x00dev, 4, bbp); 7320 7321 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 7322 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 7323 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 7324 7325 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7326 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 7327 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7328 7329 /* 7330 * Set power & frequency of passband test tone 7331 */ 7332 rt2800_bbp_write(rt2x00dev, 24, 0); 7333 7334 for (i = 0; i < 100; i++) { 7335 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7336 msleep(1); 7337 7338 passband = rt2800_bbp_read(rt2x00dev, 55); 7339 if (passband) 7340 break; 7341 } 7342 7343 /* 7344 * Set power & frequency of stopband test tone 7345 */ 7346 rt2800_bbp_write(rt2x00dev, 24, 0x06); 7347 7348 for (i = 0; i < 100; i++) { 7349 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7350 msleep(1); 7351 7352 stopband = rt2800_bbp_read(rt2x00dev, 55); 7353 7354 if ((passband - stopband) <= filter_target) { 7355 rfcsr24++; 7356 overtuned += ((passband - stopband) == filter_target); 7357 } else 7358 break; 7359 7360 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7361 } 7362 7363 rfcsr24 -= !!overtuned; 7364 7365 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7366 return rfcsr24; 7367 } 7368 7369 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 7370 const unsigned int rf_reg) 7371 { 7372 u8 rfcsr; 7373 7374 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 7375 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 7376 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7377 msleep(1); 7378 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 7379 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7380 } 7381 7382 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 7383 { 7384 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7385 u8 filter_tgt_bw20; 7386 u8 filter_tgt_bw40; 7387 u8 rfcsr, bbp; 7388 7389 /* 7390 * TODO: sync filter_tgt values with vendor driver 7391 */ 7392 if (rt2x00_rt(rt2x00dev, RT3070)) { 7393 filter_tgt_bw20 = 0x16; 7394 filter_tgt_bw40 = 0x19; 7395 } else { 7396 filter_tgt_bw20 = 0x13; 7397 filter_tgt_bw40 = 0x15; 7398 } 7399 7400 drv_data->calibration_bw20 = 7401 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 7402 drv_data->calibration_bw40 = 7403 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 7404 7405 /* 7406 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 7407 */ 7408 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7409 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7410 7411 /* 7412 * Set back to initial state 7413 */ 7414 rt2800_bbp_write(rt2x00dev, 24, 0); 7415 7416 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7417 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 7418 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7419 7420 /* 7421 * Set BBP back to BW20 7422 */ 7423 bbp = rt2800_bbp_read(rt2x00dev, 4); 7424 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 7425 rt2800_bbp_write(rt2x00dev, 4, bbp); 7426 } 7427 7428 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 7429 { 7430 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7431 u8 min_gain, rfcsr, bbp; 7432 u16 eeprom; 7433 7434 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 7435 7436 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 7437 if (rt2x00_rt(rt2x00dev, RT3070) || 7438 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7439 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 7440 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 7441 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 7442 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 7443 } 7444 7445 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 7446 if (drv_data->txmixer_gain_24g >= min_gain) { 7447 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 7448 drv_data->txmixer_gain_24g); 7449 } 7450 7451 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 7452 7453 if (rt2x00_rt(rt2x00dev, RT3090)) { 7454 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7455 bbp = rt2800_bbp_read(rt2x00dev, 138); 7456 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7457 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7458 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 7459 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7460 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 7461 rt2800_bbp_write(rt2x00dev, 138, bbp); 7462 } 7463 7464 if (rt2x00_rt(rt2x00dev, RT3070)) { 7465 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 7466 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 7467 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 7468 else 7469 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 7470 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 7471 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 7472 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 7473 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 7474 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7475 rt2x00_rt(rt2x00dev, RT3090) || 7476 rt2x00_rt(rt2x00dev, RT3390)) { 7477 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7478 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7479 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 7480 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 7481 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 7482 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 7483 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7484 7485 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 7486 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 7487 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 7488 7489 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 7490 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 7491 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 7492 7493 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 7494 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 7495 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 7496 } 7497 } 7498 7499 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 7500 { 7501 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7502 u8 rfcsr; 7503 u8 tx_gain; 7504 7505 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 7506 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 7507 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7508 7509 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 7510 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 7511 RFCSR17_TXMIXER_GAIN); 7512 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 7513 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 7514 7515 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 7516 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 7517 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 7518 7519 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 7520 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 7521 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 7522 7523 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7524 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7525 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7526 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7527 7528 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7529 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7530 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7531 7532 /* TODO: enable stream mode */ 7533 } 7534 7535 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7536 { 7537 u8 reg; 7538 u16 eeprom; 7539 7540 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7541 reg = rt2800_bbp_read(rt2x00dev, 138); 7542 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7543 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7544 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7545 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7546 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7547 rt2800_bbp_write(rt2x00dev, 138, reg); 7548 7549 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7550 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7551 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7552 7553 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7554 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7555 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7556 7557 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7558 7559 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7560 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7561 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7562 } 7563 7564 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7565 { 7566 rt2800_rf_init_calibration(rt2x00dev, 30); 7567 7568 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7569 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7570 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7571 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7572 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7573 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7574 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7575 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7576 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7577 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7578 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7579 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7580 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7581 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7582 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7583 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7584 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7585 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7586 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7587 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7588 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7589 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7590 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7591 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7592 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7593 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7594 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7595 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7596 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7597 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7598 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7599 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7600 } 7601 7602 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7603 { 7604 u8 rfcsr; 7605 u16 eeprom; 7606 u32 reg; 7607 7608 /* XXX vendor driver do this only for 3070 */ 7609 rt2800_rf_init_calibration(rt2x00dev, 30); 7610 7611 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7612 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7613 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7614 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7615 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7616 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7617 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7618 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7619 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7620 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7621 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7622 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7623 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7624 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7625 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7626 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7627 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7628 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7629 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7630 7631 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7632 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7633 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7634 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7635 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7636 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7637 rt2x00_rt(rt2x00dev, RT3090)) { 7638 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7639 7640 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7641 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7642 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7643 7644 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7645 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7646 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7647 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7648 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7649 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7650 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7651 else 7652 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7653 } 7654 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7655 7656 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7657 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7658 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7659 } 7660 7661 rt2800_rx_filter_calibration(rt2x00dev); 7662 7663 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7664 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7665 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7666 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7667 7668 rt2800_led_open_drain_enable(rt2x00dev); 7669 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7670 } 7671 7672 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7673 { 7674 u8 rfcsr; 7675 7676 rt2800_rf_init_calibration(rt2x00dev, 2); 7677 7678 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7679 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7680 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7681 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7682 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7683 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7684 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7685 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7686 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7687 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7688 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7689 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7690 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7691 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7692 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7693 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7694 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7695 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7696 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7697 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7698 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7699 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7700 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7701 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7702 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7703 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7704 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7705 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7706 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7707 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7708 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7709 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7710 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7711 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7712 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7713 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7714 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7715 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7716 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7717 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7718 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7719 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7720 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7721 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7722 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7723 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7724 7725 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7726 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7727 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7728 7729 rt2800_led_open_drain_enable(rt2x00dev); 7730 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7731 } 7732 7733 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7734 { 7735 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7736 &rt2x00dev->cap_flags); 7737 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7738 &rt2x00dev->cap_flags); 7739 u8 rfcsr; 7740 7741 rt2800_rf_init_calibration(rt2x00dev, 30); 7742 7743 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7744 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7745 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7746 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7747 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7748 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7749 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7750 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7751 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7752 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7753 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7754 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7755 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7756 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7757 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7758 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7759 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7760 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7761 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7762 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7763 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7764 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7765 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7766 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7767 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7768 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7769 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7770 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7771 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7772 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7773 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7774 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7775 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7776 rfcsr = 0x01; 7777 if (tx0_ext_pa) 7778 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7779 if (tx1_ext_pa) 7780 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7781 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7782 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7783 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7784 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7785 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7786 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7787 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7788 rfcsr = 0x52; 7789 if (!tx0_ext_pa) { 7790 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7791 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7792 } 7793 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7794 rfcsr = 0x52; 7795 if (!tx1_ext_pa) { 7796 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7797 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7798 } 7799 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7800 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7801 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7802 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7803 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7804 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7805 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7806 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7807 rfcsr = 0x2d; 7808 if (tx0_ext_pa) 7809 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7810 if (tx1_ext_pa) 7811 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7812 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7813 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7814 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7815 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7816 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7817 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7818 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7819 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7820 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7821 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7822 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7823 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7824 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7825 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7826 7827 rt2800_rx_filter_calibration(rt2x00dev); 7828 rt2800_led_open_drain_enable(rt2x00dev); 7829 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7830 } 7831 7832 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7833 { 7834 u32 reg; 7835 7836 rt2800_rf_init_calibration(rt2x00dev, 30); 7837 7838 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7839 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7840 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7841 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7842 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7843 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7844 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7845 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7846 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7847 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7848 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7849 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7850 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7851 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7852 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7853 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7854 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7855 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7856 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7857 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7858 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7859 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7860 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7861 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7862 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7863 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7864 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7865 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7866 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7867 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7868 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7869 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7870 7871 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7872 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7873 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7874 7875 rt2800_rx_filter_calibration(rt2x00dev); 7876 7877 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7878 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7879 7880 rt2800_led_open_drain_enable(rt2x00dev); 7881 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7882 } 7883 7884 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7885 { 7886 u8 rfcsr; 7887 u32 reg; 7888 7889 rt2800_rf_init_calibration(rt2x00dev, 30); 7890 7891 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7892 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7893 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7894 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7895 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7896 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7897 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7898 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7899 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7900 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7901 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7902 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7903 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7904 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7905 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7906 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7907 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7908 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7909 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7910 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7911 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7912 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7913 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7914 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7915 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7916 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7917 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7918 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7919 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7920 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7921 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7922 7923 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7924 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7925 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7926 7927 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7928 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7929 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7930 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7931 msleep(1); 7932 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7933 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7934 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7935 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7936 7937 rt2800_rx_filter_calibration(rt2x00dev); 7938 rt2800_led_open_drain_enable(rt2x00dev); 7939 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7940 } 7941 7942 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7943 { 7944 u8 bbp; 7945 bool txbf_enabled = false; /* FIXME */ 7946 7947 bbp = rt2800_bbp_read(rt2x00dev, 105); 7948 if (rt2x00dev->default_ant.rx_chain_num == 1) 7949 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7950 else 7951 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7952 rt2800_bbp_write(rt2x00dev, 105, bbp); 7953 7954 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7955 7956 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7957 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7958 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7959 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7960 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7961 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7962 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7963 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7964 7965 if (txbf_enabled) 7966 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7967 else 7968 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7969 7970 /* SNR mapping */ 7971 rt2800_bbp_write(rt2x00dev, 142, 6); 7972 rt2800_bbp_write(rt2x00dev, 143, 160); 7973 rt2800_bbp_write(rt2x00dev, 142, 7); 7974 rt2800_bbp_write(rt2x00dev, 143, 161); 7975 rt2800_bbp_write(rt2x00dev, 142, 8); 7976 rt2800_bbp_write(rt2x00dev, 143, 162); 7977 7978 /* ADC/DAC control */ 7979 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7980 7981 /* RX AGC energy lower bound in log2 */ 7982 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7983 7984 /* FIXME: BBP 105 owerwrite? */ 7985 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7986 7987 } 7988 7989 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7990 { 7991 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7992 u32 reg; 7993 u8 rfcsr; 7994 7995 /* Disable GPIO #4 and #7 function for LAN PE control */ 7996 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7997 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7998 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7999 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 8000 8001 /* Initialize default register values */ 8002 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8003 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 8004 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8005 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8006 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 8007 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 8008 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8009 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 8010 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 8011 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8012 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8013 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8014 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8015 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8016 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 8017 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 8018 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 8019 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 8020 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8021 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8022 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 8023 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8024 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8025 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8026 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8027 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 8028 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 8029 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 8030 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 8031 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 8032 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8033 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 8034 8035 /* Initiate calibration */ 8036 /* TODO: use rt2800_rf_init_calibration ? */ 8037 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8038 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8039 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8040 8041 rt2800_freq_cal_mode1(rt2x00dev); 8042 8043 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 8044 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 8045 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 8046 8047 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 8048 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 8049 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 8050 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8051 usleep_range(1000, 1500); 8052 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 8053 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 8054 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8055 8056 /* Set initial values for RX filter calibration */ 8057 drv_data->calibration_bw20 = 0x1f; 8058 drv_data->calibration_bw40 = 0x2f; 8059 8060 /* Save BBP 25 & 26 values for later use in channel switching */ 8061 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 8062 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 8063 8064 rt2800_led_open_drain_enable(rt2x00dev); 8065 rt2800_normal_mode_setup_3593(rt2x00dev); 8066 8067 rt3593_post_bbp_init(rt2x00dev); 8068 8069 /* TODO: enable stream mode support */ 8070 } 8071 8072 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 8073 { 8074 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 8075 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 8076 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8077 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8078 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 8079 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8080 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8081 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8082 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 8083 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 8084 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8085 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8086 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8087 if (rt2800_clk_is_20mhz(rt2x00dev)) 8088 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 8089 else 8090 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8091 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8092 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8093 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 8094 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8095 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8096 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8097 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8098 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8099 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8100 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8101 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8102 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8103 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8104 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8105 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 8106 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8107 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8108 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8109 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8110 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8111 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8112 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8113 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8114 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8115 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8116 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8117 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8118 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8119 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8120 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 8121 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 8122 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8123 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8124 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8125 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 8126 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 8127 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 8128 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8129 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8130 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8131 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8132 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 8133 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8134 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8135 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 8136 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8137 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8138 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8139 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8140 } 8141 8142 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev) 8143 { 8144 u8 rfcsr; 8145 8146 /* TODO: get the actual ECO value from the SoC */ 8147 const unsigned int eco = 5; 8148 8149 rt2800_rf_init_calibration(rt2x00dev, 2); 8150 8151 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0); 8152 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8153 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8154 rt2800_rfcsr_write(rt2x00dev, 3, 0x20); 8155 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 8156 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8157 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8158 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8159 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b); 8160 rt2800_rfcsr_write(rt2x00dev, 9, 0x08); 8161 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8162 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 8163 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 8164 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8165 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8166 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8167 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8168 8169 /* RFCSR 17 will be initialized later based on the 8170 * frequency offset stored in the EEPROM 8171 */ 8172 8173 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8174 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8175 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8176 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8177 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8178 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0); 8179 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8180 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8181 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8182 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8183 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8184 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 8185 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8186 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8187 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8188 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8189 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 8190 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8191 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8192 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8193 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8194 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8195 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8196 rt2800_rfcsr_write(rt2x00dev, 41, 0x00); 8197 rt2800_rfcsr_write(rt2x00dev, 42, 0x00); 8198 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8199 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 8200 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8201 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8202 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8203 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 8204 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8205 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8206 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 8207 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 8208 rt2800_rfcsr_write(rt2x00dev, 53, 0x76); 8209 rt2800_rfcsr_write(rt2x00dev, 54, 0x76); 8210 rt2800_rfcsr_write(rt2x00dev, 55, 0x76); 8211 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8212 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 8213 rt2800_rfcsr_write(rt2x00dev, 58, 0x00); 8214 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 8215 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 8216 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 8217 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8218 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8219 8220 /* TODO: rx filter calibration? */ 8221 8222 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 8223 8224 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 8225 8226 rt2800_bbp_write(rt2x00dev, 105, 0x05); 8227 8228 rt2800_bbp_write(rt2x00dev, 179, 0x02); 8229 rt2800_bbp_write(rt2x00dev, 180, 0x00); 8230 rt2800_bbp_write(rt2x00dev, 182, 0x40); 8231 rt2800_bbp_write(rt2x00dev, 180, 0x01); 8232 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 8233 8234 rt2800_bbp_write(rt2x00dev, 179, 0x00); 8235 8236 rt2800_bbp_write(rt2x00dev, 142, 0x04); 8237 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 8238 rt2800_bbp_write(rt2x00dev, 142, 0x06); 8239 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 8240 rt2800_bbp_write(rt2x00dev, 142, 0x07); 8241 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 8242 rt2800_bbp_write(rt2x00dev, 142, 0x08); 8243 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 8244 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 8245 8246 if (eco == 5) { 8247 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 8248 rt2800_rfcsr_write(rt2x00dev, 33, 0x32); 8249 } 8250 8251 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8252 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0); 8253 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8254 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8255 msleep(1); 8256 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 8257 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8258 8259 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 8260 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 8261 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 8262 8263 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 8264 rfcsr |= 0xc0; 8265 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 8266 8267 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 8268 rfcsr |= 0x20; 8269 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 8270 8271 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46); 8272 rfcsr |= 0x20; 8273 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr); 8274 8275 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 8276 rfcsr &= ~0xee; 8277 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 8278 } 8279 8280 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 8281 { 8282 rt2800_rf_init_calibration(rt2x00dev, 2); 8283 8284 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 8285 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8286 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8287 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8288 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8289 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8290 else 8291 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 8292 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8293 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8294 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8295 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8296 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8297 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8298 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8299 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8300 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8301 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8302 8303 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8304 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8305 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8306 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8307 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8308 if (rt2x00_is_usb(rt2x00dev) && 8309 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8310 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8311 else 8312 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 8313 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8314 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8315 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8316 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8317 8318 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8319 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8320 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8321 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8322 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8323 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8324 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8325 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8326 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8327 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8328 8329 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8330 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8331 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 8332 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 8333 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8334 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8335 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8336 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8337 else 8338 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 8339 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8340 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8341 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8342 8343 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8344 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8345 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8346 else 8347 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 8348 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 8349 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 8350 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8351 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 8352 else 8353 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 8354 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 8355 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 8356 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 8357 8358 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8359 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 8360 if (rt2x00_is_usb(rt2x00dev)) 8361 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8362 else 8363 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 8364 } else { 8365 if (rt2x00_is_usb(rt2x00dev)) 8366 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 8367 else 8368 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 8369 } 8370 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8371 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8372 8373 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8374 8375 rt2800_led_open_drain_enable(rt2x00dev); 8376 } 8377 8378 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 8379 { 8380 rt2800_rf_init_calibration(rt2x00dev, 2); 8381 8382 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 8383 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8384 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8385 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8386 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8387 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8388 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8389 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8390 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8391 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8392 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8393 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8394 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8395 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 8396 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8397 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 8398 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8399 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 8400 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 8401 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8402 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8403 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8404 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8405 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8406 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8407 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8408 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 8409 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8410 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8411 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8412 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8413 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8414 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 8415 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8416 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 8417 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8418 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8419 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8420 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8421 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8422 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8423 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 8424 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8425 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8426 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 8427 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 8428 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 8429 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 8430 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8431 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8432 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 8433 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8434 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8435 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 8436 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8437 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 8438 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 8439 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8440 8441 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8442 8443 rt2800_led_open_drain_enable(rt2x00dev); 8444 } 8445 8446 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 8447 { 8448 rt2800_rf_init_calibration(rt2x00dev, 30); 8449 8450 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 8451 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8452 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8453 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 8454 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8455 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8456 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8457 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8458 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8459 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 8460 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 8461 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 8462 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8463 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8464 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8465 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8466 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8467 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8468 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 8469 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 8470 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8471 8472 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8473 msleep(1); 8474 8475 rt2800_freq_cal_mode1(rt2x00dev); 8476 8477 /* Enable DC filter */ 8478 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 8479 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 8480 8481 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8482 8483 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 8484 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8485 8486 rt2800_led_open_drain_enable(rt2x00dev); 8487 } 8488 8489 static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev) 8490 { 8491 u8 rfb5r1_org, rfb7r1_org, rfvalue; 8492 u32 mac0518, mac051c, mac0528, mac052c; 8493 u8 i; 8494 8495 mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8496 mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8497 mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 8498 mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 8499 8500 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8501 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8502 8503 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC); 8504 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306); 8505 rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330); 8506 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff); 8507 rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8508 rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8509 8510 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4); 8511 for (i = 0; i < 100; ++i) { 8512 usleep_range(50, 100); 8513 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8514 if ((rfvalue & 0x04) != 0x4) 8515 break; 8516 } 8517 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org); 8518 8519 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4); 8520 for (i = 0; i < 100; ++i) { 8521 usleep_range(50, 100); 8522 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8523 if ((rfvalue & 0x04) != 0x4) 8524 break; 8525 } 8526 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org); 8527 8528 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8529 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8530 rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518); 8531 rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c); 8532 rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528); 8533 rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c); 8534 } 8535 8536 static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2) 8537 { 8538 int calcode = ((d2 - d1) * 1000) / 43; 8539 8540 if ((calcode % 10) >= 5) 8541 calcode += 10; 8542 calcode = (calcode / 10); 8543 8544 return calcode; 8545 } 8546 8547 static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) 8548 { 8549 u32 savemacsysctrl; 8550 u8 saverfb0r1, saverfb0r34, saverfb0r35; 8551 u8 saverfb5r4, saverfb5r17, saverfb5r18; 8552 u8 saverfb5r19, saverfb5r20; 8553 u8 savebbpr22, savebbpr47, savebbpr49; 8554 u8 bytevalue = 0; 8555 int rcalcode; 8556 u8 r_cal_code = 0; 8557 s8 d1 = 0, d2 = 0; 8558 u8 rfvalue; 8559 u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG; 8560 u32 maccfg; 8561 8562 saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8563 saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34); 8564 saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 8565 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8566 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8567 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8568 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8569 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8570 8571 savebbpr22 = rt2800_bbp_read(rt2x00dev, 22); 8572 savebbpr47 = rt2800_bbp_read(rt2x00dev, 47); 8573 savebbpr49 = rt2800_bbp_read(rt2x00dev, 49); 8574 8575 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8576 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8577 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8578 MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG); 8579 8580 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8581 maccfg &= (~0x04); 8582 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8583 8584 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8585 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n"); 8586 8587 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8588 maccfg &= (~0x08); 8589 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8590 8591 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 8592 rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n"); 8593 8594 rfvalue = (MAC_RF_BYPASS0 | 0x3004); 8595 rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue); 8596 rfvalue = (MAC_RF_CONTROL0 | (~0x3002)); 8597 rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue); 8598 8599 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27); 8600 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 8601 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83); 8602 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00); 8603 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 8604 8605 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00); 8606 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13); 8607 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 8608 8609 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1); 8610 8611 rt2800_bbp_write(rt2x00dev, 47, 0x04); 8612 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8613 usleep_range(100, 200); 8614 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8615 if (bytevalue > 128) 8616 d1 = bytevalue - 256; 8617 else 8618 d1 = (s8)bytevalue; 8619 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8620 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01); 8621 8622 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8623 usleep_range(100, 200); 8624 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8625 if (bytevalue > 128) 8626 d2 = bytevalue - 256; 8627 else 8628 d2 = (s8)bytevalue; 8629 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8630 8631 rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2); 8632 if (rcalcode < 0) 8633 r_cal_code = 256 + rcalcode; 8634 else 8635 r_cal_code = (u8)rcalcode; 8636 8637 rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code); 8638 8639 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8640 8641 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8642 bytevalue |= 0x1; 8643 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8644 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8645 bytevalue &= (~0x1); 8646 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8647 8648 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1); 8649 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34); 8650 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35); 8651 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8652 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8653 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8654 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8655 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8656 8657 rt2800_bbp_write(rt2x00dev, 22, savebbpr22); 8658 rt2800_bbp_write(rt2x00dev, 47, savebbpr47); 8659 rt2800_bbp_write(rt2x00dev, 49, savebbpr49); 8660 8661 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8662 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8663 8664 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 8665 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG); 8666 } 8667 8668 static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev) 8669 { 8670 u8 bbpreg = 0; 8671 u32 macvalue = 0; 8672 u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue; 8673 int i; 8674 8675 saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8676 rfvalue = saverfb0r2; 8677 rfvalue |= 0x03; 8678 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue); 8679 8680 rt2800_bbp_write(rt2x00dev, 158, 141); 8681 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8682 bbpreg |= 0x10; 8683 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8684 8685 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8686 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8); 8687 8688 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8689 rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n"); 8690 8691 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8692 saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8693 saverfb5r4 = saverfb5r4 & (~0x40); 8694 saverfb7r4 = saverfb7r4 & (~0x40); 8695 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64); 8696 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8697 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4); 8698 8699 rt2800_bbp_write(rt2x00dev, 158, 141); 8700 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8701 bbpreg = bbpreg & (~0x40); 8702 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8703 bbpreg |= 0x48; 8704 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8705 8706 for (i = 0; i < 10000; i++) { 8707 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8708 if ((bbpreg & 0x40) == 0) 8709 break; 8710 usleep_range(50, 100); 8711 } 8712 8713 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8714 bbpreg = bbpreg & (~0x40); 8715 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8716 8717 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 8718 8719 rt2800_bbp_write(rt2x00dev, 158, 141); 8720 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8721 bbpreg &= (~0x10); 8722 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8723 8724 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2); 8725 } 8726 8727 static u32 rt2800_do_sqrt_accumulation(u32 si) 8728 { 8729 u32 root, root_pre, bit; 8730 s8 i; 8731 8732 bit = 1 << 15; 8733 root = 0; 8734 for (i = 15; i >= 0; i = i - 1) { 8735 root_pre = root + bit; 8736 if ((root_pre * root_pre) <= si) 8737 root = root_pre; 8738 bit = bit >> 1; 8739 } 8740 8741 return root; 8742 } 8743 8744 static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev) 8745 { 8746 u8 rfb0r1, rfb0r2, rfb0r42; 8747 u8 rfb4r0, rfb4r19; 8748 u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20; 8749 u8 rfb6r0, rfb6r19; 8750 u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20; 8751 8752 u8 bbp1, bbp4; 8753 u8 bbpr241, bbpr242; 8754 u32 i; 8755 u8 ch_idx; 8756 u8 bbpval; 8757 u8 rfval, vga_idx = 0; 8758 int mi = 0, mq = 0, si = 0, sq = 0, riq = 0; 8759 int sigma_i, sigma_q, r_iq, g_rx; 8760 int g_imb; 8761 int ph_rx; 8762 u32 savemacsysctrl = 0; 8763 u32 orig_RF_CONTROL0 = 0; 8764 u32 orig_RF_BYPASS0 = 0; 8765 u32 orig_RF_CONTROL1 = 0; 8766 u32 orig_RF_BYPASS1 = 0; 8767 u32 orig_RF_CONTROL3 = 0; 8768 u32 orig_RF_BYPASS3 = 0; 8769 u32 bbpval1 = 0; 8770 static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f}; 8771 8772 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8773 orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8774 orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8775 orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1); 8776 orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1); 8777 orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 8778 orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 8779 8780 bbp1 = rt2800_bbp_read(rt2x00dev, 1); 8781 bbp4 = rt2800_bbp_read(rt2x00dev, 4); 8782 8783 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0); 8784 8785 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 8786 rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n"); 8787 8788 bbpval = bbp4 & (~0x18); 8789 bbpval = bbp4 | 0x00; 8790 rt2800_bbp_write(rt2x00dev, 4, bbpval); 8791 8792 bbpval = rt2800_bbp_read(rt2x00dev, 21); 8793 bbpval = bbpval | 1; 8794 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8795 bbpval = bbpval & 0xfe; 8796 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8797 8798 rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202); 8799 rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303); 8800 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 8801 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101); 8802 else 8803 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000); 8804 8805 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1); 8806 8807 rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8808 rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8809 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 8810 rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 8811 rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19); 8812 rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8813 rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8814 rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8815 rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8816 rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8817 rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8818 8819 rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 8820 rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19); 8821 rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 8822 rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8823 rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 8824 rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 8825 rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 8826 rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 8827 8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87); 8829 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27); 8830 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38); 8831 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38); 8832 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80); 8833 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1); 8834 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60); 8835 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8836 8837 rt2800_bbp_write(rt2x00dev, 23, 0x0); 8838 rt2800_bbp_write(rt2x00dev, 24, 0x0); 8839 8840 rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0); 8841 8842 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 8843 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 8844 8845 rt2800_bbp_write(rt2x00dev, 241, 0x10); 8846 rt2800_bbp_write(rt2x00dev, 242, 0x84); 8847 rt2800_bbp_write(rt2x00dev, 244, 0x31); 8848 8849 bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3); 8850 bbpval = bbpval & (~0x7); 8851 rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval); 8852 8853 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 8854 udelay(1); 8855 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 8856 usleep_range(1, 200); 8857 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376); 8858 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8859 udelay(1); 8860 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 8861 rt2800_bbp_write(rt2x00dev, 23, 0x06); 8862 rt2800_bbp_write(rt2x00dev, 24, 0x06); 8863 } else { 8864 rt2800_bbp_write(rt2x00dev, 23, 0x02); 8865 rt2800_bbp_write(rt2x00dev, 24, 0x02); 8866 } 8867 8868 for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) { 8869 if (ch_idx == 0) { 8870 rfval = rfb0r1 & (~0x3); 8871 rfval = rfb0r1 | 0x1; 8872 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8873 rfval = rfb0r2 & (~0x33); 8874 rfval = rfb0r2 | 0x11; 8875 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8876 rfval = rfb0r42 & (~0x50); 8877 rfval = rfb0r42 | 0x10; 8878 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8879 8880 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8881 udelay(1); 8882 8883 bbpval = bbp1 & (~0x18); 8884 bbpval = bbpval | 0x00; 8885 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8886 8887 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00); 8888 } else { 8889 rfval = rfb0r1 & (~0x3); 8890 rfval = rfb0r1 | 0x2; 8891 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8892 rfval = rfb0r2 & (~0x33); 8893 rfval = rfb0r2 | 0x22; 8894 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8895 rfval = rfb0r42 & (~0x50); 8896 rfval = rfb0r42 | 0x40; 8897 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8898 8899 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006); 8900 udelay(1); 8901 8902 bbpval = bbp1 & (~0x18); 8903 bbpval = bbpval | 0x08; 8904 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8905 8906 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01); 8907 } 8908 usleep_range(500, 1500); 8909 8910 vga_idx = 0; 8911 while (vga_idx < 11) { 8912 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]); 8913 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]); 8914 8915 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93); 8916 8917 for (i = 0; i < 10000; i++) { 8918 bbpval = rt2800_bbp_read(rt2x00dev, 159); 8919 if ((bbpval & 0xff) == 0x93) 8920 usleep_range(50, 100); 8921 else 8922 break; 8923 } 8924 8925 if ((bbpval & 0xff) == 0x93) { 8926 rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish"); 8927 goto restore_value; 8928 } 8929 for (i = 0; i < 5; i++) { 8930 u32 bbptemp = 0; 8931 u8 value = 0; 8932 int result = 0; 8933 8934 rt2800_bbp_write(rt2x00dev, 158, 0x1e); 8935 rt2800_bbp_write(rt2x00dev, 159, i); 8936 rt2800_bbp_write(rt2x00dev, 158, 0x22); 8937 value = rt2800_bbp_read(rt2x00dev, 159); 8938 bbptemp = bbptemp + (value << 24); 8939 rt2800_bbp_write(rt2x00dev, 158, 0x21); 8940 value = rt2800_bbp_read(rt2x00dev, 159); 8941 bbptemp = bbptemp + (value << 16); 8942 rt2800_bbp_write(rt2x00dev, 158, 0x20); 8943 value = rt2800_bbp_read(rt2x00dev, 159); 8944 bbptemp = bbptemp + (value << 8); 8945 rt2800_bbp_write(rt2x00dev, 158, 0x1f); 8946 value = rt2800_bbp_read(rt2x00dev, 159); 8947 bbptemp = bbptemp + value; 8948 8949 if (i < 2 && (bbptemp & 0x800000)) 8950 result = (bbptemp & 0xffffff) - 0x1000000; 8951 else 8952 result = bbptemp; 8953 8954 if (i == 0) 8955 mi = result / 4096; 8956 else if (i == 1) 8957 mq = result / 4096; 8958 else if (i == 2) 8959 si = bbptemp / 4096; 8960 else if (i == 3) 8961 sq = bbptemp / 4096; 8962 else 8963 riq = result / 4096; 8964 } 8965 8966 bbpval1 = si - mi * mi; 8967 rt2x00_dbg(rt2x00dev, 8968 "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d", 8969 si, sq, riq, bbpval1, vga_idx); 8970 8971 if (bbpval1 >= (100 * 100)) 8972 break; 8973 8974 if (bbpval1 <= 100) 8975 vga_idx = vga_idx + 9; 8976 else if (bbpval1 <= 158) 8977 vga_idx = vga_idx + 8; 8978 else if (bbpval1 <= 251) 8979 vga_idx = vga_idx + 7; 8980 else if (bbpval1 <= 398) 8981 vga_idx = vga_idx + 6; 8982 else if (bbpval1 <= 630) 8983 vga_idx = vga_idx + 5; 8984 else if (bbpval1 <= 1000) 8985 vga_idx = vga_idx + 4; 8986 else if (bbpval1 <= 1584) 8987 vga_idx = vga_idx + 3; 8988 else if (bbpval1 <= 2511) 8989 vga_idx = vga_idx + 2; 8990 else 8991 vga_idx = vga_idx + 1; 8992 } 8993 8994 sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi)); 8995 sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq)); 8996 r_iq = 10 * (riq - (mi * mq)); 8997 8998 rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq); 8999 9000 if (sigma_i <= 1400 && sigma_i >= 1000 && 9001 (sigma_i - sigma_q) <= 112 && 9002 (sigma_i - sigma_q) >= -112 && 9003 mi <= 32 && mi >= -32 && 9004 mq <= 32 && mq >= -32) { 9005 r_iq = 10 * (riq - (mi * mq)); 9006 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 9007 sigma_i, sigma_q, r_iq); 9008 9009 g_rx = (1000 * sigma_q) / sigma_i; 9010 g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx); 9011 ph_rx = (r_iq * 2292) / (sigma_i * sigma_q); 9012 9013 if (ph_rx > 20 || ph_rx < -20) { 9014 ph_rx = 0; 9015 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 9016 } 9017 9018 if (g_imb > 12 || g_imb < -12) { 9019 g_imb = 0; 9020 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 9021 } 9022 } else { 9023 g_imb = 0; 9024 ph_rx = 0; 9025 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 9026 sigma_i, sigma_q, r_iq); 9027 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 9028 } 9029 9030 if (ch_idx == 0) { 9031 rt2800_bbp_write(rt2x00dev, 158, 0x37); 9032 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 9033 rt2800_bbp_write(rt2x00dev, 158, 0x35); 9034 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 9035 } else { 9036 rt2800_bbp_write(rt2x00dev, 158, 0x55); 9037 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 9038 rt2800_bbp_write(rt2x00dev, 158, 0x53); 9039 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 9040 } 9041 } 9042 9043 restore_value: 9044 rt2800_bbp_write(rt2x00dev, 158, 0x3); 9045 bbpval = rt2800_bbp_read(rt2x00dev, 159); 9046 rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07)); 9047 9048 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9049 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9050 rt2800_bbp_write(rt2x00dev, 1, bbp1); 9051 rt2800_bbp_write(rt2x00dev, 4, bbp4); 9052 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9053 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9054 9055 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9056 bbpval = rt2800_bbp_read(rt2x00dev, 21); 9057 bbpval |= 0x1; 9058 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9059 usleep_range(10, 200); 9060 bbpval &= 0xfe; 9061 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9062 9063 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1); 9064 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2); 9065 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9066 9067 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0); 9068 rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19); 9069 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3); 9070 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4); 9071 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17); 9072 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18); 9073 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19); 9074 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20); 9075 9076 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0); 9077 rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19); 9078 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3); 9079 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4); 9080 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17); 9081 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18); 9082 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19); 9083 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20); 9084 9085 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 9086 udelay(1); 9087 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9088 udelay(1); 9089 rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0); 9090 udelay(1); 9091 rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0); 9092 rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1); 9093 rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1); 9094 rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3); 9095 rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3); 9096 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9097 } 9098 9099 static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, 9100 struct rf_reg_pair rf_reg_record[][13], u8 chain) 9101 { 9102 u8 rfvalue = 0; 9103 9104 if (chain == CHAIN_0) { 9105 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9106 rf_reg_record[CHAIN_0][0].bank = 0; 9107 rf_reg_record[CHAIN_0][0].reg = 1; 9108 rf_reg_record[CHAIN_0][0].value = rfvalue; 9109 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9110 rf_reg_record[CHAIN_0][1].bank = 0; 9111 rf_reg_record[CHAIN_0][1].reg = 2; 9112 rf_reg_record[CHAIN_0][1].value = rfvalue; 9113 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9114 rf_reg_record[CHAIN_0][2].bank = 0; 9115 rf_reg_record[CHAIN_0][2].reg = 35; 9116 rf_reg_record[CHAIN_0][2].value = rfvalue; 9117 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9118 rf_reg_record[CHAIN_0][3].bank = 0; 9119 rf_reg_record[CHAIN_0][3].reg = 42; 9120 rf_reg_record[CHAIN_0][3].value = rfvalue; 9121 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 9122 rf_reg_record[CHAIN_0][4].bank = 4; 9123 rf_reg_record[CHAIN_0][4].reg = 0; 9124 rf_reg_record[CHAIN_0][4].value = rfvalue; 9125 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2); 9126 rf_reg_record[CHAIN_0][5].bank = 4; 9127 rf_reg_record[CHAIN_0][5].reg = 2; 9128 rf_reg_record[CHAIN_0][5].value = rfvalue; 9129 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34); 9130 rf_reg_record[CHAIN_0][6].bank = 4; 9131 rf_reg_record[CHAIN_0][6].reg = 34; 9132 rf_reg_record[CHAIN_0][6].value = rfvalue; 9133 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 9134 rf_reg_record[CHAIN_0][7].bank = 5; 9135 rf_reg_record[CHAIN_0][7].reg = 3; 9136 rf_reg_record[CHAIN_0][7].value = rfvalue; 9137 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 9138 rf_reg_record[CHAIN_0][8].bank = 5; 9139 rf_reg_record[CHAIN_0][8].reg = 4; 9140 rf_reg_record[CHAIN_0][8].value = rfvalue; 9141 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 9142 rf_reg_record[CHAIN_0][9].bank = 5; 9143 rf_reg_record[CHAIN_0][9].reg = 17; 9144 rf_reg_record[CHAIN_0][9].value = rfvalue; 9145 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 9146 rf_reg_record[CHAIN_0][10].bank = 5; 9147 rf_reg_record[CHAIN_0][10].reg = 18; 9148 rf_reg_record[CHAIN_0][10].value = rfvalue; 9149 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 9150 rf_reg_record[CHAIN_0][11].bank = 5; 9151 rf_reg_record[CHAIN_0][11].reg = 19; 9152 rf_reg_record[CHAIN_0][11].value = rfvalue; 9153 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 9154 rf_reg_record[CHAIN_0][12].bank = 5; 9155 rf_reg_record[CHAIN_0][12].reg = 20; 9156 rf_reg_record[CHAIN_0][12].value = rfvalue; 9157 } else if (chain == CHAIN_1) { 9158 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9159 rf_reg_record[CHAIN_1][0].bank = 0; 9160 rf_reg_record[CHAIN_1][0].reg = 1; 9161 rf_reg_record[CHAIN_1][0].value = rfvalue; 9162 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9163 rf_reg_record[CHAIN_1][1].bank = 0; 9164 rf_reg_record[CHAIN_1][1].reg = 2; 9165 rf_reg_record[CHAIN_1][1].value = rfvalue; 9166 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9167 rf_reg_record[CHAIN_1][2].bank = 0; 9168 rf_reg_record[CHAIN_1][2].reg = 35; 9169 rf_reg_record[CHAIN_1][2].value = rfvalue; 9170 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9171 rf_reg_record[CHAIN_1][3].bank = 0; 9172 rf_reg_record[CHAIN_1][3].reg = 42; 9173 rf_reg_record[CHAIN_1][3].value = rfvalue; 9174 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 9175 rf_reg_record[CHAIN_1][4].bank = 6; 9176 rf_reg_record[CHAIN_1][4].reg = 0; 9177 rf_reg_record[CHAIN_1][4].value = rfvalue; 9178 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2); 9179 rf_reg_record[CHAIN_1][5].bank = 6; 9180 rf_reg_record[CHAIN_1][5].reg = 2; 9181 rf_reg_record[CHAIN_1][5].value = rfvalue; 9182 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34); 9183 rf_reg_record[CHAIN_1][6].bank = 6; 9184 rf_reg_record[CHAIN_1][6].reg = 34; 9185 rf_reg_record[CHAIN_1][6].value = rfvalue; 9186 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 9187 rf_reg_record[CHAIN_1][7].bank = 7; 9188 rf_reg_record[CHAIN_1][7].reg = 3; 9189 rf_reg_record[CHAIN_1][7].value = rfvalue; 9190 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 9191 rf_reg_record[CHAIN_1][8].bank = 7; 9192 rf_reg_record[CHAIN_1][8].reg = 4; 9193 rf_reg_record[CHAIN_1][8].value = rfvalue; 9194 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 9195 rf_reg_record[CHAIN_1][9].bank = 7; 9196 rf_reg_record[CHAIN_1][9].reg = 17; 9197 rf_reg_record[CHAIN_1][9].value = rfvalue; 9198 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 9199 rf_reg_record[CHAIN_1][10].bank = 7; 9200 rf_reg_record[CHAIN_1][10].reg = 18; 9201 rf_reg_record[CHAIN_1][10].value = rfvalue; 9202 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 9203 rf_reg_record[CHAIN_1][11].bank = 7; 9204 rf_reg_record[CHAIN_1][11].reg = 19; 9205 rf_reg_record[CHAIN_1][11].value = rfvalue; 9206 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 9207 rf_reg_record[CHAIN_1][12].bank = 7; 9208 rf_reg_record[CHAIN_1][12].reg = 20; 9209 rf_reg_record[CHAIN_1][12].value = rfvalue; 9210 } else { 9211 rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain); 9212 } 9213 } 9214 9215 static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, 9216 struct rf_reg_pair rf_record[][13]) 9217 { 9218 u8 chain_index = 0, record_index = 0; 9219 u8 bank = 0, rf_register = 0, value = 0; 9220 9221 for (chain_index = 0; chain_index < 2; chain_index++) { 9222 for (record_index = 0; record_index < 13; record_index++) { 9223 bank = rf_record[chain_index][record_index].bank; 9224 rf_register = rf_record[chain_index][record_index].reg; 9225 value = rf_record[chain_index][record_index].value; 9226 rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value); 9227 rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", 9228 bank, rf_register, value); 9229 } 9230 } 9231 } 9232 9233 static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev) 9234 { 9235 rt2800_bbp_write(rt2x00dev, 158, 0xAA); 9236 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9237 9238 rt2800_bbp_write(rt2x00dev, 158, 0xAB); 9239 rt2800_bbp_write(rt2x00dev, 159, 0x0A); 9240 9241 rt2800_bbp_write(rt2x00dev, 158, 0xAC); 9242 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9243 9244 rt2800_bbp_write(rt2x00dev, 158, 0xAD); 9245 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9246 9247 rt2800_bbp_write(rt2x00dev, 244, 0x40); 9248 } 9249 9250 static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg) 9251 { 9252 u32 macvalue = 0; 9253 int fftout_i = 0, fftout_q = 0; 9254 u32 ptmp = 0, pint = 0; 9255 u8 bbp = 0; 9256 u8 tidxi; 9257 9258 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9259 rt2800_bbp_write(rt2x00dev, 159, 0x9b); 9260 9261 bbp = 0x9b; 9262 9263 while (bbp == 0x9b) { 9264 usleep_range(10, 50); 9265 bbp = rt2800_bbp_read(rt2x00dev, 159); 9266 bbp = bbp & 0xff; 9267 } 9268 9269 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9270 rt2800_bbp_write(rt2x00dev, 159, tidx); 9271 rt2800_bbp_write(rt2x00dev, 159, tidx); 9272 rt2800_bbp_write(rt2x00dev, 159, tidx); 9273 9274 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9275 9276 fftout_i = (macvalue >> 16); 9277 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9278 fftout_q = (macvalue & 0xffff); 9279 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9280 ptmp = (fftout_i * fftout_i); 9281 ptmp = ptmp + (fftout_q * fftout_q); 9282 pint = ptmp; 9283 rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint); 9284 if (read_neg) { 9285 pint = pint >> 1; 9286 tidxi = 0x40 - tidx; 9287 tidxi = tidxi & 0x3f; 9288 9289 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9290 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9291 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9292 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9293 9294 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9295 9296 fftout_i = (macvalue >> 16); 9297 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9298 fftout_q = (macvalue & 0xffff); 9299 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9300 ptmp = (fftout_i * fftout_i); 9301 ptmp = ptmp + (fftout_q * fftout_q); 9302 ptmp = ptmp >> 1; 9303 pint = pint + ptmp; 9304 } 9305 9306 return pint; 9307 } 9308 9309 static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) 9310 { 9311 u32 macvalue = 0; 9312 int fftout_i = 0, fftout_q = 0; 9313 u32 ptmp = 0, pint = 0; 9314 9315 rt2800_bbp_write(rt2x00dev, 158, 0xBA); 9316 rt2800_bbp_write(rt2x00dev, 159, tidx); 9317 rt2800_bbp_write(rt2x00dev, 159, tidx); 9318 rt2800_bbp_write(rt2x00dev, 159, tidx); 9319 9320 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9321 9322 fftout_i = (macvalue >> 16); 9323 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9324 fftout_q = (macvalue & 0xffff); 9325 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9326 ptmp = (fftout_i * fftout_i); 9327 ptmp = ptmp + (fftout_q * fftout_q); 9328 pint = ptmp; 9329 9330 return pint; 9331 } 9332 9333 static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc) 9334 { 9335 u8 bbp = 0; 9336 9337 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9338 bbp = alc | 0x80; 9339 rt2800_bbp_write(rt2x00dev, 159, bbp); 9340 9341 if (ch_idx == 0) 9342 bbp = (iorq == 0) ? 0xb1 : 0xb2; 9343 else 9344 bbp = (iorq == 0) ? 0xb8 : 0xb9; 9345 9346 rt2800_bbp_write(rt2x00dev, 158, bbp); 9347 bbp = dc; 9348 rt2800_bbp_write(rt2x00dev, 159, bbp); 9349 } 9350 9351 static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, 9352 u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2]) 9353 { 9354 u32 p0 = 0, p1 = 0, pf = 0; 9355 s8 idx0 = 0, idx1 = 0; 9356 u8 idxf[] = {0x00, 0x00}; 9357 u8 ibit = 0x20; 9358 u8 iorq; 9359 s8 bidx; 9360 9361 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9362 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9363 9364 for (bidx = 5; bidx >= 0; bidx--) { 9365 for (iorq = 0; iorq <= 1; iorq++) { 9366 if (idxf[iorq] == 0x20) { 9367 idx0 = 0x20; 9368 p0 = pf; 9369 } else { 9370 idx0 = idxf[iorq] - ibit; 9371 idx0 = idx0 & 0x3F; 9372 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0); 9373 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9374 } 9375 9376 idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit); 9377 idx1 = idx1 & 0x3F; 9378 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1); 9379 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9380 9381 rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", 9382 alc_idx, iorq, idxf[iorq]); 9383 rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n", 9384 p0, p1, pf, idx0, idx1, ibit); 9385 9386 if (bidx != 5 && pf <= p0 && pf < p1) { 9387 idxf[iorq] = idxf[iorq]; 9388 } else if (p0 < p1) { 9389 pf = p0; 9390 idxf[iorq] = idx0 & 0x3F; 9391 } else { 9392 pf = p1; 9393 idxf[iorq] = idx1 & 0x3F; 9394 } 9395 rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", 9396 iorq, iorq, idxf[iorq], pf); 9397 9398 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]); 9399 } 9400 ibit = ibit >> 1; 9401 } 9402 dc_result[ch_idx][alc_idx][0] = idxf[0]; 9403 dc_result[ch_idx][alc_idx][1] = idxf[1]; 9404 } 9405 9406 static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes) 9407 { 9408 u32 p0 = 0, p1 = 0, pf = 0; 9409 s8 perr = 0, gerr = 0, iq_err = 0; 9410 s8 pef = 0, gef = 0; 9411 s8 psta, pend; 9412 s8 gsta, gend; 9413 9414 u8 ibit = 0x20; 9415 u8 first_search = 0x00, touch_neg_max = 0x00; 9416 s8 idx0 = 0, idx1 = 0; 9417 u8 gop; 9418 u8 bbp = 0; 9419 s8 bidx; 9420 9421 for (bidx = 5; bidx >= 1; bidx--) { 9422 for (gop = 0; gop < 2; gop++) { 9423 if (gop == 1 || bidx < 4) { 9424 if (gop == 0) 9425 iq_err = gerr; 9426 else 9427 iq_err = perr; 9428 9429 first_search = (gop == 0) ? (bidx == 3) : (bidx == 5); 9430 touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : 9431 ((iq_err & 0x3F) == 0x20); 9432 9433 if (touch_neg_max) { 9434 p0 = pf; 9435 idx0 = iq_err; 9436 } else { 9437 idx0 = iq_err - ibit; 9438 bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) : 9439 ((gop == 0) ? 0x46 : 0x47); 9440 9441 rt2800_bbp_write(rt2x00dev, 158, bbp); 9442 rt2800_bbp_write(rt2x00dev, 159, idx0); 9443 9444 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9445 } 9446 9447 idx1 = iq_err + (first_search ? 0 : ibit); 9448 idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F); 9449 9450 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9451 (gop == 0) ? 0x46 : 0x47; 9452 9453 rt2800_bbp_write(rt2x00dev, 158, bbp); 9454 rt2800_bbp_write(rt2x00dev, 159, idx1); 9455 9456 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9457 9458 rt2x00_dbg(rt2x00dev, 9459 "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n", 9460 p0, p1, pf, idx0, idx1, iq_err, gop, ibit); 9461 9462 if (!(!first_search && pf <= p0 && pf < p1)) { 9463 if (p0 < p1) { 9464 pf = p0; 9465 iq_err = idx0; 9466 } else { 9467 pf = p1; 9468 iq_err = idx1; 9469 } 9470 } 9471 9472 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9473 (gop == 0) ? 0x46 : 0x47; 9474 9475 rt2800_bbp_write(rt2x00dev, 158, bbp); 9476 rt2800_bbp_write(rt2x00dev, 159, iq_err); 9477 9478 if (gop == 0) 9479 gerr = iq_err; 9480 else 9481 perr = iq_err; 9482 9483 rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", 9484 pf, gerr & 0x0F, perr & 0x3F); 9485 } 9486 } 9487 9488 if (bidx > 0) 9489 ibit = (ibit >> 1); 9490 } 9491 gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F); 9492 perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F); 9493 9494 gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr; 9495 gsta = gerr - 1; 9496 gend = gerr + 2; 9497 9498 perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr; 9499 psta = perr - 1; 9500 pend = perr + 2; 9501 9502 for (gef = gsta; gef <= gend; gef = gef + 1) 9503 for (pef = psta; pef <= pend; pef = pef + 1) { 9504 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9505 rt2800_bbp_write(rt2x00dev, 158, bbp); 9506 rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F); 9507 9508 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9509 rt2800_bbp_write(rt2x00dev, 158, bbp); 9510 rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F); 9511 9512 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9513 if (gef == gsta && pef == psta) { 9514 pf = p1; 9515 gerr = gef; 9516 perr = pef; 9517 } else if (pf > p1) { 9518 pf = p1; 9519 gerr = gef; 9520 perr = pef; 9521 } 9522 rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", 9523 p1, pf, gef & 0x0F, pef & 0x3F); 9524 } 9525 9526 ges[ch_idx] = gerr & 0x0F; 9527 pes[ch_idx] = perr & 0x3F; 9528 } 9529 9530 static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev) 9531 { 9532 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21); 9533 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10); 9534 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9535 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b); 9536 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81); 9537 rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81); 9538 rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee); 9539 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d); 9540 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d); 9541 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 9542 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7); 9543 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2); 9544 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 9545 } 9546 9547 static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev) 9548 { 9549 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22); 9550 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20); 9551 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9552 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b); 9553 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81); 9554 rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81); 9555 rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee); 9556 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d); 9557 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d); 9558 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80); 9559 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7); 9560 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2); 9561 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20); 9562 } 9563 9564 static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev) 9565 { 9566 struct rf_reg_pair rf_store[CHAIN_NUM][13]; 9567 u32 macorg1 = 0; 9568 u32 macorg2 = 0; 9569 u32 macorg3 = 0; 9570 u32 macorg4 = 0; 9571 u32 macorg5 = 0; 9572 u32 orig528 = 0; 9573 u32 orig52c = 0; 9574 9575 u32 savemacsysctrl = 0; 9576 u32 macvalue = 0; 9577 u32 mac13b8 = 0; 9578 u32 p0 = 0, p1 = 0; 9579 u32 p0_idx10 = 0, p1_idx10 = 0; 9580 9581 u8 rfvalue; 9582 u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2]; 9583 u8 ger[CHAIN_NUM], per[CHAIN_NUM]; 9584 9585 u8 vga_gain[] = {14, 14}; 9586 u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0; 9587 u8 bbpr30, rfb0r39, rfb0r42; 9588 u8 bbpr1; 9589 u8 bbpr4; 9590 u8 bbpr241, bbpr242; 9591 u8 count_step; 9592 9593 static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c}; 9594 static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 9595 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F}; 9596 static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08}; 9597 9598 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9599 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9600 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9601 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9602 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9603 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9604 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9605 orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 9606 orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 9607 9608 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9609 macvalue &= (~0x04); 9610 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9611 9612 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9613 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9614 9615 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9616 macvalue &= (~0x08); 9617 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9618 9619 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9620 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9621 9622 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9623 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9624 9625 bbpr30 = rt2800_bbp_read(rt2x00dev, 30); 9626 rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39); 9627 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9628 9629 rt2800_bbp_write(rt2x00dev, 30, 0x1F); 9630 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80); 9631 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B); 9632 9633 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9634 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9635 9636 rt2800_setbbptonegenerator(rt2x00dev); 9637 9638 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9639 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9640 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9641 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00); 9642 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9643 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9644 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9645 rt2800_register_write(rt2x00dev, 0x13b8, 0x10); 9646 udelay(1); 9647 9648 if (ch_idx == 0) 9649 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9650 else 9651 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9652 9653 udelay(1); 9654 9655 if (ch_idx == 0) 9656 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9657 else 9658 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9659 9660 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9661 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9662 9663 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9664 if (ch_idx == 0) 9665 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9666 else 9667 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9668 9669 vga_gain[ch_idx] = 18; 9670 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9671 rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]); 9672 rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]); 9673 9674 macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9675 macvalue &= (~0x0000F1F1); 9676 macvalue |= (rf_gain[rf_alc_idx] << 4); 9677 macvalue |= (rf_gain[rf_alc_idx] << 12); 9678 rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue); 9679 macvalue = (0x0000F1F1); 9680 rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue); 9681 9682 if (rf_alc_idx == 0) { 9683 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21); 9684 for (; vga_gain[ch_idx] > 0; 9685 vga_gain[ch_idx] = vga_gain[ch_idx] - 2) { 9686 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9687 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9688 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9689 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9690 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9691 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9692 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21); 9693 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9694 rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1); 9695 if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000))) 9696 break; 9697 } 9698 9699 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9700 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9701 9702 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9703 rfvga_gain_table[vga_gain[ch_idx]]); 9704 } 9705 9706 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9707 9708 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9709 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9710 9711 rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result); 9712 } 9713 } 9714 9715 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9716 for (idx = 0; idx < 4; idx++) { 9717 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9718 bbp = (idx << 2) + rf_alc_idx; 9719 rt2800_bbp_write(rt2x00dev, 159, bbp); 9720 rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp); 9721 9722 rt2800_bbp_write(rt2x00dev, 158, 0xb1); 9723 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00]; 9724 bbp = bbp & 0x3F; 9725 rt2800_bbp_write(rt2x00dev, 159, bbp); 9726 rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp); 9727 9728 rt2800_bbp_write(rt2x00dev, 158, 0xb2); 9729 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01]; 9730 bbp = bbp & 0x3F; 9731 rt2800_bbp_write(rt2x00dev, 159, bbp); 9732 rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp); 9733 9734 rt2800_bbp_write(rt2x00dev, 158, 0xb8); 9735 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00]; 9736 bbp = bbp & 0x3F; 9737 rt2800_bbp_write(rt2x00dev, 159, bbp); 9738 rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp); 9739 9740 rt2800_bbp_write(rt2x00dev, 158, 0xb9); 9741 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01]; 9742 bbp = bbp & 0x3F; 9743 rt2800_bbp_write(rt2x00dev, 159, bbp); 9744 rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp); 9745 } 9746 } 9747 9748 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9749 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9750 9751 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9752 9753 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9754 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9755 9756 bbp = 0x00; 9757 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9758 9759 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9760 udelay(1); 9761 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9762 9763 rt2800_rf_configrecover(rt2x00dev, rf_store); 9764 9765 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9766 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9767 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9768 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9769 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9770 udelay(1); 9771 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9772 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9773 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9774 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9775 rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528); 9776 rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c); 9777 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9778 9779 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9780 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9781 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9782 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9783 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9784 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9785 9786 bbpr1 = rt2800_bbp_read(rt2x00dev, 1); 9787 bbpr4 = rt2800_bbp_read(rt2x00dev, 4); 9788 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 9789 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 9790 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9791 9792 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9793 macvalue &= (~0x04); 9794 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9795 9796 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9797 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9798 9799 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9800 macvalue &= (~0x08); 9801 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9802 9803 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9804 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9805 9806 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9807 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101); 9808 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9809 } 9810 9811 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9812 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9813 9814 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9815 rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18)); 9816 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9817 udelay(1); 9818 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9819 9820 rt2800_bbp_write(rt2x00dev, 241, 0x14); 9821 rt2800_bbp_write(rt2x00dev, 242, 0x80); 9822 rt2800_bbp_write(rt2x00dev, 244, 0x31); 9823 } else { 9824 rt2800_setbbptonegenerator(rt2x00dev); 9825 } 9826 9827 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9828 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9829 udelay(1); 9830 9831 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9832 9833 if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9834 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000); 9835 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9836 } 9837 9838 rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010); 9839 9840 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9841 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9842 9843 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B); 9844 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B); 9845 9846 rt2800_bbp_write(rt2x00dev, 158, 0x03); 9847 rt2800_bbp_write(rt2x00dev, 159, 0x60); 9848 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9849 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9850 9851 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9852 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9853 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9854 9855 if (ch_idx == 0) { 9856 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9857 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9858 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9859 bbp = bbpr1 & (~0x18); 9860 bbp = bbp | 0x00; 9861 rt2800_bbp_write(rt2x00dev, 1, bbp); 9862 } 9863 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9864 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9865 } else { 9866 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9867 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9868 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) { 9869 bbp = bbpr1 & (~0x18); 9870 bbp = bbp | 0x08; 9871 rt2800_bbp_write(rt2x00dev, 1, bbp); 9872 } 9873 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9874 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9875 } 9876 9877 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9878 rt2800_bbp_write(rt2x00dev, 159, 0x04); 9879 9880 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9881 rt2800_bbp_write(rt2x00dev, 158, bbp); 9882 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9883 9884 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9885 rt2800_bbp_write(rt2x00dev, 23, 0x06); 9886 rt2800_bbp_write(rt2x00dev, 24, 0x06); 9887 count_step = 1; 9888 } else { 9889 rt2800_bbp_write(rt2x00dev, 23, 0x1F); 9890 rt2800_bbp_write(rt2x00dev, 24, 0x1F); 9891 count_step = 2; 9892 } 9893 9894 for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) { 9895 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9896 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9897 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9898 9899 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9900 rt2800_bbp_write(rt2x00dev, 158, bbp); 9901 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9902 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9903 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9904 p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9905 9906 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9907 rt2800_bbp_write(rt2x00dev, 158, bbp); 9908 rt2800_bbp_write(rt2x00dev, 159, 0x21); 9909 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9910 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) 9911 p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9912 9913 rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1); 9914 9915 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9916 rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10); 9917 if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) { 9918 if (vga_gain[ch_idx] != 0) 9919 vga_gain[ch_idx] = vga_gain[ch_idx] - 1; 9920 break; 9921 } 9922 } 9923 9924 if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500)) 9925 break; 9926 } 9927 9928 if (vga_gain[ch_idx] > 18) 9929 vga_gain[ch_idx] = 18; 9930 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9931 rfvga_gain_table[vga_gain[ch_idx]]); 9932 9933 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9934 rt2800_bbp_write(rt2x00dev, 158, bbp); 9935 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9936 9937 rt2800_iq_search(rt2x00dev, ch_idx, ger, per); 9938 } 9939 9940 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9941 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9942 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9943 9944 rt2800_bbp_write(rt2x00dev, 158, 0x28); 9945 bbp = ger[CHAIN_0] & 0x0F; 9946 rt2800_bbp_write(rt2x00dev, 159, bbp); 9947 9948 rt2800_bbp_write(rt2x00dev, 158, 0x29); 9949 bbp = per[CHAIN_0] & 0x3F; 9950 rt2800_bbp_write(rt2x00dev, 159, bbp); 9951 9952 rt2800_bbp_write(rt2x00dev, 158, 0x46); 9953 bbp = ger[CHAIN_1] & 0x0F; 9954 rt2800_bbp_write(rt2x00dev, 159, bbp); 9955 9956 rt2800_bbp_write(rt2x00dev, 158, 0x47); 9957 bbp = per[CHAIN_1] & 0x3F; 9958 rt2800_bbp_write(rt2x00dev, 159, bbp); 9959 9960 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9961 rt2800_bbp_write(rt2x00dev, 1, bbpr1); 9962 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9963 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9964 } 9965 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9966 9967 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9968 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9969 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9970 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9971 9972 rt2800_bbp_write(rt2x00dev, 30, bbpr30); 9973 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39); 9974 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9975 9976 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9977 rt2800_bbp_write(rt2x00dev, 4, bbpr4); 9978 9979 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9980 udelay(1); 9981 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9982 9983 rt2800_rf_configrecover(rt2x00dev, rf_store); 9984 9985 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9986 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9987 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9988 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9989 udelay(1); 9990 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9991 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9992 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9993 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9994 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9995 } 9996 9997 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 9998 bool set_bw, bool is_ht40) 9999 { 10000 u8 bbp_val; 10001 10002 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 10003 bbp_val |= 0x1; 10004 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 10005 usleep_range(100, 200); 10006 10007 if (set_bw) { 10008 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 10009 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 10010 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 10011 usleep_range(100, 200); 10012 } 10013 10014 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 10015 bbp_val &= (~0x1); 10016 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 10017 usleep_range(100, 200); 10018 } 10019 10020 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 10021 { 10022 u8 rf_val; 10023 10024 if (btxcal) 10025 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 10026 else 10027 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 10028 10029 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 10030 10031 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 10032 rf_val |= 0x80; 10033 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 10034 10035 if (btxcal) { 10036 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 10037 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 10038 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 10039 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10040 rf_val &= (~0x3F); 10041 rf_val |= 0x3F; 10042 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 10043 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10044 rf_val &= (~0x3F); 10045 rf_val |= 0x3F; 10046 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10047 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 10048 } else { 10049 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 10050 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 10051 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 10052 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10053 rf_val &= (~0x3F); 10054 rf_val |= 0x34; 10055 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 10056 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10057 rf_val &= (~0x3F); 10058 rf_val |= 0x34; 10059 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10060 } 10061 10062 return 0; 10063 } 10064 10065 static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 10066 { 10067 unsigned int cnt; 10068 u8 bbp_val; 10069 s8 cal_val; 10070 10071 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 10072 10073 cnt = 0; 10074 do { 10075 usleep_range(500, 2000); 10076 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 10077 if (bbp_val == 0x02 || cnt == 20) 10078 break; 10079 10080 cnt++; 10081 } while (cnt < 20); 10082 10083 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 10084 cal_val = bbp_val & 0x7F; 10085 if (cal_val >= 0x40) 10086 cal_val -= 128; 10087 10088 return cal_val; 10089 } 10090 10091 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 10092 bool btxcal) 10093 { 10094 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10095 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 10096 u8 filter_target; 10097 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 10098 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 10099 int loop = 0, is_ht40, cnt; 10100 u8 bbp_val, rf_val; 10101 s8 cal_r32_init, cal_r32_val, cal_diff; 10102 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 10103 u8 saverfb5r06, saverfb5r07; 10104 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 10105 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 10106 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 10107 u8 saverfb5r58, saverfb5r59; 10108 u8 savebbp159r0, savebbp159r2, savebbpr23; 10109 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 10110 10111 /* Save MAC registers */ 10112 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 10113 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 10114 10115 /* save BBP registers */ 10116 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 10117 10118 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 10119 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10120 10121 /* Save RF registers */ 10122 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10123 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10124 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10125 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10126 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 10127 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10128 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10129 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10130 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 10131 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 10132 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 10133 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 10134 10135 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 10136 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 10137 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 10138 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 10139 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 10140 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 10141 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 10142 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 10143 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 10144 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 10145 10146 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10147 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10148 10149 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10150 rf_val |= 0x3; 10151 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10152 10153 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10154 rf_val |= 0x1; 10155 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 10156 10157 cnt = 0; 10158 do { 10159 usleep_range(500, 2000); 10160 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10161 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 10162 break; 10163 cnt++; 10164 } while (cnt < 40); 10165 10166 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10167 rf_val &= (~0x3); 10168 rf_val |= 0x1; 10169 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10170 10171 /* I-3 */ 10172 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 10173 bbp_val &= (~0x1F); 10174 bbp_val |= 0x10; 10175 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 10176 10177 do { 10178 /* I-4,5,6,7,8,9 */ 10179 if (loop == 0) { 10180 is_ht40 = false; 10181 10182 if (btxcal) 10183 filter_target = tx_filter_target_20m; 10184 else 10185 filter_target = rx_filter_target_20m; 10186 } else { 10187 is_ht40 = true; 10188 10189 if (btxcal) 10190 filter_target = tx_filter_target_40m; 10191 else 10192 filter_target = rx_filter_target_40m; 10193 } 10194 10195 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10196 rf_val &= (~0x04); 10197 if (loop == 1) 10198 rf_val |= 0x4; 10199 10200 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 10201 10202 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 10203 10204 rt2800_rf_lp_config(rt2x00dev, btxcal); 10205 if (btxcal) { 10206 tx_agc_fc = 0; 10207 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10208 rf_val &= (~0x7F); 10209 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10210 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10211 rf_val &= (~0x7F); 10212 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10213 } else { 10214 rx_agc_fc = 0; 10215 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10216 rf_val &= (~0x7F); 10217 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10218 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10219 rf_val &= (~0x7F); 10220 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10221 } 10222 10223 usleep_range(1000, 2000); 10224 10225 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10226 bbp_val &= (~0x6); 10227 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10228 10229 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10230 10231 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10232 10233 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10234 bbp_val |= 0x6; 10235 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10236 do_cal: 10237 if (btxcal) { 10238 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10239 rf_val &= (~0x7F); 10240 rf_val |= tx_agc_fc; 10241 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10242 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10243 rf_val &= (~0x7F); 10244 rf_val |= tx_agc_fc; 10245 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10246 } else { 10247 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10248 rf_val &= (~0x7F); 10249 rf_val |= rx_agc_fc; 10250 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10251 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10252 rf_val &= (~0x7F); 10253 rf_val |= rx_agc_fc; 10254 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10255 } 10256 10257 usleep_range(500, 1000); 10258 10259 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10260 10261 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10262 10263 cal_diff = cal_r32_init - cal_r32_val; 10264 10265 if (btxcal) 10266 cmm_agc_fc = tx_agc_fc; 10267 else 10268 cmm_agc_fc = rx_agc_fc; 10269 10270 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 10271 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 10272 if (btxcal) 10273 tx_agc_fc = 0; 10274 else 10275 rx_agc_fc = 0; 10276 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 10277 if (btxcal) 10278 tx_agc_fc++; 10279 else 10280 rx_agc_fc++; 10281 goto do_cal; 10282 } 10283 10284 if (btxcal) { 10285 if (loop == 0) 10286 drv_data->tx_calibration_bw20 = tx_agc_fc; 10287 else 10288 drv_data->tx_calibration_bw40 = tx_agc_fc; 10289 } else { 10290 if (loop == 0) 10291 drv_data->rx_calibration_bw20 = rx_agc_fc; 10292 else 10293 drv_data->rx_calibration_bw40 = rx_agc_fc; 10294 } 10295 10296 loop++; 10297 } while (loop <= 1); 10298 10299 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 10300 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 10301 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 10302 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 10303 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 10304 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 10305 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 10306 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 10307 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 10308 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 10309 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 10310 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 10311 10312 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 10313 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 10314 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 10315 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 10316 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 10317 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 10318 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 10319 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 10320 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 10321 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 10322 10323 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 10324 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 10325 10326 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 10327 10328 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 10329 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 10330 10331 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 10332 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 10333 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 10334 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 10335 10336 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 10337 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 10338 } 10339 10340 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 10341 { 10342 /* Initialize RF central register to default value */ 10343 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 10344 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 10345 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 10346 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 10347 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 10348 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 10349 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 10350 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 10351 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 10352 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 10353 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 10354 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 10355 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 10356 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10357 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 10358 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 10359 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 10360 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 10361 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 10362 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 10363 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 10364 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 10365 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 10366 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 10367 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 10368 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 10369 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 10370 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10371 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 10372 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 10373 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 10374 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 10375 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 10376 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 10377 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 10378 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 10379 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 10380 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 10381 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 10382 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 10383 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 10384 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 10385 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 10386 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 10387 10388 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 10389 if (rt2800_clk_is_20mhz(rt2x00dev)) 10390 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 10391 else 10392 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10393 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 10394 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 10395 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 10396 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 10397 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 10398 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 10399 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 10400 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 10401 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 10402 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 10403 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 10404 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 10405 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10406 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 10407 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 10408 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 10409 10410 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 10411 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 10412 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 10413 10414 /* Initialize RF channel register to default value */ 10415 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 10416 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 10417 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 10418 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 10419 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 10420 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 10421 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 10422 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 10423 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 10424 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 10425 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 10426 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10427 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 10428 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 10429 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10430 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 10431 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 10432 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 10433 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 10434 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10435 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 10436 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 10437 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 10438 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 10439 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 10440 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 10441 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 10442 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 10443 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 10444 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 10445 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 10446 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 10447 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 10448 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 10449 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 10450 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 10451 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 10452 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 10453 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 10454 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 10455 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 10456 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 10457 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 10458 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 10459 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 10460 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10461 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 10462 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 10463 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 10464 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 10465 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 10466 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 10467 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 10468 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 10469 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 10470 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 10471 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 10472 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 10473 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 10474 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 10475 10476 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 10477 10478 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 10479 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 10480 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 10481 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 10482 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 10483 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 10484 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 10485 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 10486 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 10487 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 10488 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 10489 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 10490 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 10491 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 10492 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10493 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 10494 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10495 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 10496 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 10497 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 10498 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 10499 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 10500 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 10501 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10502 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 10503 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 10504 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 10505 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10506 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 10507 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 10508 10509 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 10510 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10511 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10512 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 10513 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 10514 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 10515 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 10516 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10517 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 10518 10519 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 10520 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 10521 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 10522 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 10523 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10524 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10525 10526 /* Initialize RF channel register for DRQFN */ 10527 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10528 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 10529 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 10530 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 10531 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 10532 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 10533 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 10534 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 10535 10536 /* Initialize RF DC calibration register to default value */ 10537 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 10538 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 10539 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 10540 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 10541 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 10542 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10543 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 10544 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 10545 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 10546 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 10547 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 10548 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 10549 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 10550 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 10551 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 10552 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 10553 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 10554 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 10555 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 10556 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 10557 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 10558 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 10559 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 10560 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 10561 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 10562 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 10563 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 10564 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 10565 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 10566 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 10567 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 10568 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 10569 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 10570 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 10571 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 10572 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 10573 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 10574 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 10575 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 10576 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 10577 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 10578 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 10579 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 10580 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 10581 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 10582 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 10583 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 10584 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 10585 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 10586 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 10587 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 10588 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 10589 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 10590 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 10591 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 10592 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 10593 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 10594 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 10595 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 10596 10597 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 10598 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 10599 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 10600 10601 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10602 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 10603 10604 rt2800_r_calibration(rt2x00dev); 10605 rt2800_rf_self_txdc_cal(rt2x00dev); 10606 rt2800_rxdcoc_calibration(rt2x00dev); 10607 rt2800_bw_filter_calibration(rt2x00dev, true); 10608 rt2800_bw_filter_calibration(rt2x00dev, false); 10609 rt2800_loft_iq_calibration(rt2x00dev); 10610 rt2800_rxiq_calibration(rt2x00dev); 10611 } 10612 10613 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 10614 { 10615 if (rt2800_is_305x_soc(rt2x00dev)) { 10616 rt2800_init_rfcsr_305x_soc(rt2x00dev); 10617 return; 10618 } 10619 10620 switch (rt2x00dev->chip.rt) { 10621 case RT3070: 10622 case RT3071: 10623 case RT3090: 10624 rt2800_init_rfcsr_30xx(rt2x00dev); 10625 break; 10626 case RT3290: 10627 rt2800_init_rfcsr_3290(rt2x00dev); 10628 break; 10629 case RT3352: 10630 rt2800_init_rfcsr_3352(rt2x00dev); 10631 break; 10632 case RT3390: 10633 rt2800_init_rfcsr_3390(rt2x00dev); 10634 break; 10635 case RT3883: 10636 rt2800_init_rfcsr_3883(rt2x00dev); 10637 break; 10638 case RT3572: 10639 rt2800_init_rfcsr_3572(rt2x00dev); 10640 break; 10641 case RT3593: 10642 rt2800_init_rfcsr_3593(rt2x00dev); 10643 break; 10644 case RT5350: 10645 rt2800_init_rfcsr_5350(rt2x00dev); 10646 break; 10647 case RT5390: 10648 rt2800_init_rfcsr_5390(rt2x00dev); 10649 break; 10650 case RT5392: 10651 rt2800_init_rfcsr_5392(rt2x00dev); 10652 break; 10653 case RT5592: 10654 rt2800_init_rfcsr_5592(rt2x00dev); 10655 break; 10656 case RT6352: 10657 rt2800_init_rfcsr_6352(rt2x00dev); 10658 break; 10659 } 10660 } 10661 10662 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 10663 { 10664 u32 reg; 10665 u16 word; 10666 10667 /* 10668 * Initialize MAC registers. 10669 */ 10670 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 10671 rt2800_init_registers(rt2x00dev))) 10672 return -EIO; 10673 10674 /* 10675 * Wait BBP/RF to wake up. 10676 */ 10677 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 10678 return -EIO; 10679 10680 /* 10681 * Send signal during boot time to initialize firmware. 10682 */ 10683 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 10684 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 10685 if (rt2x00_is_usb(rt2x00dev)) 10686 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 10687 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 10688 msleep(1); 10689 10690 /* 10691 * Make sure BBP is up and running. 10692 */ 10693 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 10694 return -EIO; 10695 10696 /* 10697 * Initialize BBP/RF registers. 10698 */ 10699 rt2800_init_bbp(rt2x00dev); 10700 rt2800_init_rfcsr(rt2x00dev); 10701 10702 if (rt2x00_is_usb(rt2x00dev) && 10703 (rt2x00_rt(rt2x00dev, RT3070) || 10704 rt2x00_rt(rt2x00dev, RT3071) || 10705 rt2x00_rt(rt2x00dev, RT3572))) { 10706 udelay(200); 10707 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 10708 udelay(10); 10709 } 10710 10711 /* 10712 * Enable RX. 10713 */ 10714 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10715 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10716 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10717 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10718 10719 udelay(50); 10720 10721 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 10722 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 10723 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 10724 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 10725 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 10726 10727 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10728 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10729 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 10730 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10731 10732 /* 10733 * Initialize LED control 10734 */ 10735 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 10736 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 10737 word & 0xff, (word >> 8) & 0xff); 10738 10739 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 10740 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 10741 word & 0xff, (word >> 8) & 0xff); 10742 10743 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 10744 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 10745 word & 0xff, (word >> 8) & 0xff); 10746 10747 return 0; 10748 } 10749 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 10750 10751 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 10752 { 10753 u32 reg; 10754 10755 rt2800_disable_wpdma(rt2x00dev); 10756 10757 /* Wait for DMA, ignore error */ 10758 rt2800_wait_wpdma_ready(rt2x00dev); 10759 10760 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10761 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 10762 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10763 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10764 } 10765 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 10766 10767 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 10768 { 10769 u32 reg; 10770 u16 efuse_ctrl_reg; 10771 10772 if (rt2x00_rt(rt2x00dev, RT3290)) 10773 efuse_ctrl_reg = EFUSE_CTRL_3290; 10774 else 10775 efuse_ctrl_reg = EFUSE_CTRL; 10776 10777 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 10778 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 10779 } 10780 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 10781 10782 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 10783 { 10784 u32 reg; 10785 u16 efuse_ctrl_reg; 10786 u16 efuse_data0_reg; 10787 u16 efuse_data1_reg; 10788 u16 efuse_data2_reg; 10789 u16 efuse_data3_reg; 10790 10791 if (rt2x00_rt(rt2x00dev, RT3290)) { 10792 efuse_ctrl_reg = EFUSE_CTRL_3290; 10793 efuse_data0_reg = EFUSE_DATA0_3290; 10794 efuse_data1_reg = EFUSE_DATA1_3290; 10795 efuse_data2_reg = EFUSE_DATA2_3290; 10796 efuse_data3_reg = EFUSE_DATA3_3290; 10797 } else { 10798 efuse_ctrl_reg = EFUSE_CTRL; 10799 efuse_data0_reg = EFUSE_DATA0; 10800 efuse_data1_reg = EFUSE_DATA1; 10801 efuse_data2_reg = EFUSE_DATA2; 10802 efuse_data3_reg = EFUSE_DATA3; 10803 } 10804 mutex_lock(&rt2x00dev->csr_mutex); 10805 10806 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 10807 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 10808 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 10809 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 10810 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 10811 10812 /* Wait until the EEPROM has been loaded */ 10813 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 10814 /* Apparently the data is read from end to start */ 10815 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 10816 /* The returned value is in CPU order, but eeprom is le */ 10817 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 10818 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 10819 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 10820 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 10821 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 10822 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 10823 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 10824 10825 mutex_unlock(&rt2x00dev->csr_mutex); 10826 } 10827 10828 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 10829 { 10830 unsigned int i; 10831 10832 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 10833 rt2800_efuse_read(rt2x00dev, i); 10834 10835 return 0; 10836 } 10837 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 10838 10839 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 10840 { 10841 u16 word; 10842 10843 if (rt2x00_rt(rt2x00dev, RT3593) || 10844 rt2x00_rt(rt2x00dev, RT3883)) 10845 return 0; 10846 10847 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 10848 if ((word & 0x00ff) != 0x00ff) 10849 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 10850 10851 return 0; 10852 } 10853 10854 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 10855 { 10856 u16 word; 10857 10858 if (rt2x00_rt(rt2x00dev, RT3593) || 10859 rt2x00_rt(rt2x00dev, RT3883)) 10860 return 0; 10861 10862 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 10863 if ((word & 0x00ff) != 0x00ff) 10864 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 10865 10866 return 0; 10867 } 10868 10869 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 10870 { 10871 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10872 u16 word; 10873 u8 *mac; 10874 u8 default_lna_gain; 10875 int retval; 10876 10877 /* 10878 * Read the EEPROM. 10879 */ 10880 retval = rt2800_read_eeprom(rt2x00dev); 10881 if (retval) 10882 return retval; 10883 10884 /* 10885 * Start validation of the data that has been read. 10886 */ 10887 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 10888 rt2x00lib_set_mac_address(rt2x00dev, mac); 10889 10890 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 10891 if (word == 0xffff) { 10892 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10893 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 10894 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 10895 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10896 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 10897 } else if (rt2x00_rt(rt2x00dev, RT2860) || 10898 rt2x00_rt(rt2x00dev, RT2872)) { 10899 /* 10900 * There is a max of 2 RX streams for RT28x0 series 10901 */ 10902 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 10903 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10904 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10905 } 10906 10907 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 10908 if (word == 0xffff) { 10909 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 10910 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 10911 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 10912 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 10913 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 10914 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 10915 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 10916 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 10917 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 10918 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 10919 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 10920 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 10921 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 10922 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 10923 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 10924 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 10925 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 10926 } 10927 10928 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 10929 if ((word & 0x00ff) == 0x00ff) { 10930 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 10931 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 10932 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 10933 } 10934 if ((word & 0xff00) == 0xff00) { 10935 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 10936 LED_MODE_TXRX_ACTIVITY); 10937 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 10938 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 10939 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 10940 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 10941 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 10942 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 10943 } 10944 10945 /* 10946 * During the LNA validation we are going to use 10947 * lna0 as correct value. Note that EEPROM_LNA 10948 * is never validated. 10949 */ 10950 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 10951 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 10952 10953 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 10954 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 10955 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 10956 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 10957 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 10958 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 10959 10960 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 10961 10962 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 10963 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 10964 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 10965 if (!rt2x00_rt(rt2x00dev, RT3593) && 10966 !rt2x00_rt(rt2x00dev, RT3883)) { 10967 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 10968 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 10969 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 10970 default_lna_gain); 10971 } 10972 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 10973 10974 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 10975 10976 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 10977 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 10978 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 10979 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 10980 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 10981 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 10982 10983 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 10984 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 10985 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 10986 if (!rt2x00_rt(rt2x00dev, RT3593) && 10987 !rt2x00_rt(rt2x00dev, RT3883)) { 10988 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 10989 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 10990 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 10991 default_lna_gain); 10992 } 10993 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 10994 10995 if (rt2x00_rt(rt2x00dev, RT3593) || 10996 rt2x00_rt(rt2x00dev, RT3883)) { 10997 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 10998 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 10999 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 11000 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 11001 default_lna_gain); 11002 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 11003 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 11004 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 11005 default_lna_gain); 11006 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 11007 } 11008 11009 return 0; 11010 } 11011 11012 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 11013 { 11014 u16 value; 11015 u16 eeprom; 11016 u16 rf; 11017 11018 /* 11019 * Read EEPROM word for configuration. 11020 */ 11021 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 11022 11023 /* 11024 * Identify RF chipset by EEPROM value 11025 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 11026 * RT53xx: defined in "EEPROM_CHIP_ID" field 11027 */ 11028 if (rt2x00_rt(rt2x00dev, RT3290) || 11029 rt2x00_rt(rt2x00dev, RT5390) || 11030 rt2x00_rt(rt2x00dev, RT5392) || 11031 rt2x00_rt(rt2x00dev, RT6352)) 11032 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 11033 else if (rt2x00_rt(rt2x00dev, RT3352)) 11034 rf = RF3322; 11035 else if (rt2x00_rt(rt2x00dev, RT3883)) 11036 rf = RF3853; 11037 else if (rt2x00_rt(rt2x00dev, RT5350)) 11038 rf = RF5350; 11039 else if (rt2x00_rt(rt2x00dev, RT5592)) 11040 rf = RF5592; 11041 else 11042 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 11043 11044 switch (rf) { 11045 case RF2820: 11046 case RF2850: 11047 case RF2720: 11048 case RF2750: 11049 case RF3020: 11050 case RF2020: 11051 case RF3021: 11052 case RF3022: 11053 case RF3052: 11054 case RF3053: 11055 case RF3070: 11056 case RF3290: 11057 case RF3320: 11058 case RF3322: 11059 case RF3853: 11060 case RF5350: 11061 case RF5360: 11062 case RF5362: 11063 case RF5370: 11064 case RF5372: 11065 case RF5390: 11066 case RF5392: 11067 case RF5592: 11068 case RF7620: 11069 break; 11070 default: 11071 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 11072 rf); 11073 return -ENODEV; 11074 } 11075 11076 rt2x00_set_rf(rt2x00dev, rf); 11077 11078 /* 11079 * Identify default antenna configuration. 11080 */ 11081 rt2x00dev->default_ant.tx_chain_num = 11082 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 11083 rt2x00dev->default_ant.rx_chain_num = 11084 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 11085 11086 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11087 11088 if (rt2x00_rt(rt2x00dev, RT3070) || 11089 rt2x00_rt(rt2x00dev, RT3090) || 11090 rt2x00_rt(rt2x00dev, RT3352) || 11091 rt2x00_rt(rt2x00dev, RT3390)) { 11092 value = rt2x00_get_field16(eeprom, 11093 EEPROM_NIC_CONF1_ANT_DIVERSITY); 11094 switch (value) { 11095 case 0: 11096 case 1: 11097 case 2: 11098 rt2x00dev->default_ant.tx = ANTENNA_A; 11099 rt2x00dev->default_ant.rx = ANTENNA_A; 11100 break; 11101 case 3: 11102 rt2x00dev->default_ant.tx = ANTENNA_A; 11103 rt2x00dev->default_ant.rx = ANTENNA_B; 11104 break; 11105 } 11106 } else { 11107 rt2x00dev->default_ant.tx = ANTENNA_A; 11108 rt2x00dev->default_ant.rx = ANTENNA_A; 11109 } 11110 11111 /* These chips have hardware RX antenna diversity */ 11112 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 11113 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 11114 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 11115 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 11116 } 11117 11118 /* 11119 * Determine external LNA informations. 11120 */ 11121 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 11122 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 11123 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 11124 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 11125 11126 /* 11127 * Detect if this device has an hardware controlled radio. 11128 */ 11129 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 11130 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 11131 11132 /* 11133 * Detect if this device has Bluetooth co-existence. 11134 */ 11135 if (!rt2x00_rt(rt2x00dev, RT3352) && 11136 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 11137 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 11138 11139 /* 11140 * Read frequency offset and RF programming sequence. 11141 */ 11142 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 11143 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 11144 11145 /* 11146 * Store led settings, for correct led behaviour. 11147 */ 11148 #ifdef CONFIG_RT2X00_LIB_LEDS 11149 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 11150 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 11151 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 11152 11153 rt2x00dev->led_mcu_reg = eeprom; 11154 #endif /* CONFIG_RT2X00_LIB_LEDS */ 11155 11156 /* 11157 * Check if support EIRP tx power limit feature. 11158 */ 11159 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 11160 11161 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 11162 EIRP_MAX_TX_POWER_LIMIT) 11163 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 11164 11165 /* 11166 * Detect if device uses internal or external PA 11167 */ 11168 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11169 11170 if (rt2x00_rt(rt2x00dev, RT3352) || 11171 rt2x00_rt(rt2x00dev, RT6352)) { 11172 if (rt2x00_get_field16(eeprom, 11173 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 11174 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 11175 &rt2x00dev->cap_flags); 11176 if (rt2x00_get_field16(eeprom, 11177 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 11178 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 11179 &rt2x00dev->cap_flags); 11180 } 11181 11182 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2); 11183 11184 if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) { 11185 if (!rt2x00_get_field16(eeprom, 11186 EEPROM_NIC_CONF2_EXTERNAL_PA)) { 11187 __clear_bit(CAPABILITY_EXTERNAL_PA_TX0, 11188 &rt2x00dev->cap_flags); 11189 __clear_bit(CAPABILITY_EXTERNAL_PA_TX1, 11190 &rt2x00dev->cap_flags); 11191 } 11192 } 11193 11194 return 0; 11195 } 11196 11197 /* 11198 * RF value list for rt28xx 11199 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 11200 */ 11201 static const struct rf_channel rf_vals[] = { 11202 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 11203 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 11204 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 11205 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 11206 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 11207 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 11208 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 11209 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 11210 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 11211 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 11212 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 11213 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 11214 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 11215 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 11216 11217 /* 802.11 UNI / HyperLan 2 */ 11218 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 11219 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 11220 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 11221 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 11222 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 11223 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 11224 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 11225 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 11226 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 11227 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 11228 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 11229 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 11230 11231 /* 802.11 HyperLan 2 */ 11232 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 11233 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 11234 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 11235 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 11236 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 11237 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 11238 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 11239 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 11240 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 11241 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 11242 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 11243 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 11244 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 11245 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 11246 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 11247 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 11248 11249 /* 802.11 UNII */ 11250 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 11251 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 11252 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 11253 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 11254 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 11255 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 11256 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 11257 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 11258 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 11259 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 11260 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 11261 11262 /* 802.11 Japan */ 11263 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 11264 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 11265 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 11266 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 11267 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 11268 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 11269 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 11270 }; 11271 11272 /* 11273 * RF value list for rt3xxx 11274 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 11275 */ 11276 static const struct rf_channel rf_vals_3x[] = { 11277 {1, 241, 2, 2 }, 11278 {2, 241, 2, 7 }, 11279 {3, 242, 2, 2 }, 11280 {4, 242, 2, 7 }, 11281 {5, 243, 2, 2 }, 11282 {6, 243, 2, 7 }, 11283 {7, 244, 2, 2 }, 11284 {8, 244, 2, 7 }, 11285 {9, 245, 2, 2 }, 11286 {10, 245, 2, 7 }, 11287 {11, 246, 2, 2 }, 11288 {12, 246, 2, 7 }, 11289 {13, 247, 2, 2 }, 11290 {14, 248, 2, 4 }, 11291 11292 /* 802.11 UNI / HyperLan 2 */ 11293 {36, 0x56, 0, 4}, 11294 {38, 0x56, 0, 6}, 11295 {40, 0x56, 0, 8}, 11296 {44, 0x57, 0, 0}, 11297 {46, 0x57, 0, 2}, 11298 {48, 0x57, 0, 4}, 11299 {52, 0x57, 0, 8}, 11300 {54, 0x57, 0, 10}, 11301 {56, 0x58, 0, 0}, 11302 {60, 0x58, 0, 4}, 11303 {62, 0x58, 0, 6}, 11304 {64, 0x58, 0, 8}, 11305 11306 /* 802.11 HyperLan 2 */ 11307 {100, 0x5b, 0, 8}, 11308 {102, 0x5b, 0, 10}, 11309 {104, 0x5c, 0, 0}, 11310 {108, 0x5c, 0, 4}, 11311 {110, 0x5c, 0, 6}, 11312 {112, 0x5c, 0, 8}, 11313 {116, 0x5d, 0, 0}, 11314 {118, 0x5d, 0, 2}, 11315 {120, 0x5d, 0, 4}, 11316 {124, 0x5d, 0, 8}, 11317 {126, 0x5d, 0, 10}, 11318 {128, 0x5e, 0, 0}, 11319 {132, 0x5e, 0, 4}, 11320 {134, 0x5e, 0, 6}, 11321 {136, 0x5e, 0, 8}, 11322 {140, 0x5f, 0, 0}, 11323 11324 /* 802.11 UNII */ 11325 {149, 0x5f, 0, 9}, 11326 {151, 0x5f, 0, 11}, 11327 {153, 0x60, 0, 1}, 11328 {157, 0x60, 0, 5}, 11329 {159, 0x60, 0, 7}, 11330 {161, 0x60, 0, 9}, 11331 {165, 0x61, 0, 1}, 11332 {167, 0x61, 0, 3}, 11333 {169, 0x61, 0, 5}, 11334 {171, 0x61, 0, 7}, 11335 {173, 0x61, 0, 9}, 11336 }; 11337 11338 /* 11339 * RF value list for rt3xxx with Xtal20MHz 11340 * Supports: 2.4 GHz (all) (RF3322) 11341 */ 11342 static const struct rf_channel rf_vals_3x_xtal20[] = { 11343 {1, 0xE2, 2, 0x14}, 11344 {2, 0xE3, 2, 0x14}, 11345 {3, 0xE4, 2, 0x14}, 11346 {4, 0xE5, 2, 0x14}, 11347 {5, 0xE6, 2, 0x14}, 11348 {6, 0xE7, 2, 0x14}, 11349 {7, 0xE8, 2, 0x14}, 11350 {8, 0xE9, 2, 0x14}, 11351 {9, 0xEA, 2, 0x14}, 11352 {10, 0xEB, 2, 0x14}, 11353 {11, 0xEC, 2, 0x14}, 11354 {12, 0xED, 2, 0x14}, 11355 {13, 0xEE, 2, 0x14}, 11356 {14, 0xF0, 2, 0x18}, 11357 }; 11358 11359 static const struct rf_channel rf_vals_3853[] = { 11360 {1, 241, 6, 2}, 11361 {2, 241, 6, 7}, 11362 {3, 242, 6, 2}, 11363 {4, 242, 6, 7}, 11364 {5, 243, 6, 2}, 11365 {6, 243, 6, 7}, 11366 {7, 244, 6, 2}, 11367 {8, 244, 6, 7}, 11368 {9, 245, 6, 2}, 11369 {10, 245, 6, 7}, 11370 {11, 246, 6, 2}, 11371 {12, 246, 6, 7}, 11372 {13, 247, 6, 2}, 11373 {14, 248, 6, 4}, 11374 11375 {36, 0x56, 8, 4}, 11376 {38, 0x56, 8, 6}, 11377 {40, 0x56, 8, 8}, 11378 {44, 0x57, 8, 0}, 11379 {46, 0x57, 8, 2}, 11380 {48, 0x57, 8, 4}, 11381 {52, 0x57, 8, 8}, 11382 {54, 0x57, 8, 10}, 11383 {56, 0x58, 8, 0}, 11384 {60, 0x58, 8, 4}, 11385 {62, 0x58, 8, 6}, 11386 {64, 0x58, 8, 8}, 11387 11388 {100, 0x5b, 8, 8}, 11389 {102, 0x5b, 8, 10}, 11390 {104, 0x5c, 8, 0}, 11391 {108, 0x5c, 8, 4}, 11392 {110, 0x5c, 8, 6}, 11393 {112, 0x5c, 8, 8}, 11394 {114, 0x5c, 8, 10}, 11395 {116, 0x5d, 8, 0}, 11396 {118, 0x5d, 8, 2}, 11397 {120, 0x5d, 8, 4}, 11398 {124, 0x5d, 8, 8}, 11399 {126, 0x5d, 8, 10}, 11400 {128, 0x5e, 8, 0}, 11401 {132, 0x5e, 8, 4}, 11402 {134, 0x5e, 8, 6}, 11403 {136, 0x5e, 8, 8}, 11404 {140, 0x5f, 8, 0}, 11405 11406 {149, 0x5f, 8, 9}, 11407 {151, 0x5f, 8, 11}, 11408 {153, 0x60, 8, 1}, 11409 {157, 0x60, 8, 5}, 11410 {159, 0x60, 8, 7}, 11411 {161, 0x60, 8, 9}, 11412 {165, 0x61, 8, 1}, 11413 {167, 0x61, 8, 3}, 11414 {169, 0x61, 8, 5}, 11415 {171, 0x61, 8, 7}, 11416 {173, 0x61, 8, 9}, 11417 }; 11418 11419 static const struct rf_channel rf_vals_5592_xtal20[] = { 11420 /* Channel, N, K, mod, R */ 11421 {1, 482, 4, 10, 3}, 11422 {2, 483, 4, 10, 3}, 11423 {3, 484, 4, 10, 3}, 11424 {4, 485, 4, 10, 3}, 11425 {5, 486, 4, 10, 3}, 11426 {6, 487, 4, 10, 3}, 11427 {7, 488, 4, 10, 3}, 11428 {8, 489, 4, 10, 3}, 11429 {9, 490, 4, 10, 3}, 11430 {10, 491, 4, 10, 3}, 11431 {11, 492, 4, 10, 3}, 11432 {12, 493, 4, 10, 3}, 11433 {13, 494, 4, 10, 3}, 11434 {14, 496, 8, 10, 3}, 11435 {36, 172, 8, 12, 1}, 11436 {38, 173, 0, 12, 1}, 11437 {40, 173, 4, 12, 1}, 11438 {42, 173, 8, 12, 1}, 11439 {44, 174, 0, 12, 1}, 11440 {46, 174, 4, 12, 1}, 11441 {48, 174, 8, 12, 1}, 11442 {50, 175, 0, 12, 1}, 11443 {52, 175, 4, 12, 1}, 11444 {54, 175, 8, 12, 1}, 11445 {56, 176, 0, 12, 1}, 11446 {58, 176, 4, 12, 1}, 11447 {60, 176, 8, 12, 1}, 11448 {62, 177, 0, 12, 1}, 11449 {64, 177, 4, 12, 1}, 11450 {100, 183, 4, 12, 1}, 11451 {102, 183, 8, 12, 1}, 11452 {104, 184, 0, 12, 1}, 11453 {106, 184, 4, 12, 1}, 11454 {108, 184, 8, 12, 1}, 11455 {110, 185, 0, 12, 1}, 11456 {112, 185, 4, 12, 1}, 11457 {114, 185, 8, 12, 1}, 11458 {116, 186, 0, 12, 1}, 11459 {118, 186, 4, 12, 1}, 11460 {120, 186, 8, 12, 1}, 11461 {122, 187, 0, 12, 1}, 11462 {124, 187, 4, 12, 1}, 11463 {126, 187, 8, 12, 1}, 11464 {128, 188, 0, 12, 1}, 11465 {130, 188, 4, 12, 1}, 11466 {132, 188, 8, 12, 1}, 11467 {134, 189, 0, 12, 1}, 11468 {136, 189, 4, 12, 1}, 11469 {138, 189, 8, 12, 1}, 11470 {140, 190, 0, 12, 1}, 11471 {149, 191, 6, 12, 1}, 11472 {151, 191, 10, 12, 1}, 11473 {153, 192, 2, 12, 1}, 11474 {155, 192, 6, 12, 1}, 11475 {157, 192, 10, 12, 1}, 11476 {159, 193, 2, 12, 1}, 11477 {161, 193, 6, 12, 1}, 11478 {165, 194, 2, 12, 1}, 11479 {184, 164, 0, 12, 1}, 11480 {188, 164, 4, 12, 1}, 11481 {192, 165, 8, 12, 1}, 11482 {196, 166, 0, 12, 1}, 11483 }; 11484 11485 static const struct rf_channel rf_vals_5592_xtal40[] = { 11486 /* Channel, N, K, mod, R */ 11487 {1, 241, 2, 10, 3}, 11488 {2, 241, 7, 10, 3}, 11489 {3, 242, 2, 10, 3}, 11490 {4, 242, 7, 10, 3}, 11491 {5, 243, 2, 10, 3}, 11492 {6, 243, 7, 10, 3}, 11493 {7, 244, 2, 10, 3}, 11494 {8, 244, 7, 10, 3}, 11495 {9, 245, 2, 10, 3}, 11496 {10, 245, 7, 10, 3}, 11497 {11, 246, 2, 10, 3}, 11498 {12, 246, 7, 10, 3}, 11499 {13, 247, 2, 10, 3}, 11500 {14, 248, 4, 10, 3}, 11501 {36, 86, 4, 12, 1}, 11502 {38, 86, 6, 12, 1}, 11503 {40, 86, 8, 12, 1}, 11504 {42, 86, 10, 12, 1}, 11505 {44, 87, 0, 12, 1}, 11506 {46, 87, 2, 12, 1}, 11507 {48, 87, 4, 12, 1}, 11508 {50, 87, 6, 12, 1}, 11509 {52, 87, 8, 12, 1}, 11510 {54, 87, 10, 12, 1}, 11511 {56, 88, 0, 12, 1}, 11512 {58, 88, 2, 12, 1}, 11513 {60, 88, 4, 12, 1}, 11514 {62, 88, 6, 12, 1}, 11515 {64, 88, 8, 12, 1}, 11516 {100, 91, 8, 12, 1}, 11517 {102, 91, 10, 12, 1}, 11518 {104, 92, 0, 12, 1}, 11519 {106, 92, 2, 12, 1}, 11520 {108, 92, 4, 12, 1}, 11521 {110, 92, 6, 12, 1}, 11522 {112, 92, 8, 12, 1}, 11523 {114, 92, 10, 12, 1}, 11524 {116, 93, 0, 12, 1}, 11525 {118, 93, 2, 12, 1}, 11526 {120, 93, 4, 12, 1}, 11527 {122, 93, 6, 12, 1}, 11528 {124, 93, 8, 12, 1}, 11529 {126, 93, 10, 12, 1}, 11530 {128, 94, 0, 12, 1}, 11531 {130, 94, 2, 12, 1}, 11532 {132, 94, 4, 12, 1}, 11533 {134, 94, 6, 12, 1}, 11534 {136, 94, 8, 12, 1}, 11535 {138, 94, 10, 12, 1}, 11536 {140, 95, 0, 12, 1}, 11537 {149, 95, 9, 12, 1}, 11538 {151, 95, 11, 12, 1}, 11539 {153, 96, 1, 12, 1}, 11540 {155, 96, 3, 12, 1}, 11541 {157, 96, 5, 12, 1}, 11542 {159, 96, 7, 12, 1}, 11543 {161, 96, 9, 12, 1}, 11544 {165, 97, 1, 12, 1}, 11545 {184, 82, 0, 12, 1}, 11546 {188, 82, 4, 12, 1}, 11547 {192, 82, 8, 12, 1}, 11548 {196, 83, 0, 12, 1}, 11549 }; 11550 11551 static const struct rf_channel rf_vals_7620[] = { 11552 {1, 0x50, 0x99, 0x99, 1}, 11553 {2, 0x50, 0x44, 0x44, 2}, 11554 {3, 0x50, 0xEE, 0xEE, 2}, 11555 {4, 0x50, 0x99, 0x99, 3}, 11556 {5, 0x51, 0x44, 0x44, 0}, 11557 {6, 0x51, 0xEE, 0xEE, 0}, 11558 {7, 0x51, 0x99, 0x99, 1}, 11559 {8, 0x51, 0x44, 0x44, 2}, 11560 {9, 0x51, 0xEE, 0xEE, 2}, 11561 {10, 0x51, 0x99, 0x99, 3}, 11562 {11, 0x52, 0x44, 0x44, 0}, 11563 {12, 0x52, 0xEE, 0xEE, 0}, 11564 {13, 0x52, 0x99, 0x99, 1}, 11565 {14, 0x52, 0x33, 0x33, 3}, 11566 }; 11567 11568 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 11569 { 11570 struct hw_mode_spec *spec = &rt2x00dev->spec; 11571 struct channel_info *info; 11572 s8 *default_power1; 11573 s8 *default_power2; 11574 s8 *default_power3; 11575 unsigned int i, tx_chains, rx_chains; 11576 u32 reg; 11577 11578 /* 11579 * Disable powersaving as default. 11580 */ 11581 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 11582 11583 /* 11584 * Change default retry settings to values corresponding more closely 11585 * to rate[0].count setting of minstrel rate control algorithm. 11586 */ 11587 rt2x00dev->hw->wiphy->retry_short = 2; 11588 rt2x00dev->hw->wiphy->retry_long = 2; 11589 11590 /* 11591 * Initialize all hw fields. 11592 */ 11593 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 11594 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 11595 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 11596 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 11597 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 11598 11599 /* 11600 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 11601 * unless we are capable of sending the buffered frames out after the 11602 * DTIM transmission using rt2x00lib_beacondone. This will send out 11603 * multicast and broadcast traffic immediately instead of buffering it 11604 * infinitly and thus dropping it after some time. 11605 */ 11606 if (!rt2x00_is_usb(rt2x00dev)) 11607 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 11608 11609 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 11610 11611 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 11612 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 11613 rt2800_eeprom_addr(rt2x00dev, 11614 EEPROM_MAC_ADDR_0)); 11615 11616 /* 11617 * As rt2800 has a global fallback table we cannot specify 11618 * more then one tx rate per frame but since the hw will 11619 * try several rates (based on the fallback table) we should 11620 * initialize max_report_rates to the maximum number of rates 11621 * we are going to try. Otherwise mac80211 will truncate our 11622 * reported tx rates and the rc algortihm will end up with 11623 * incorrect data. 11624 */ 11625 rt2x00dev->hw->max_rates = 1; 11626 rt2x00dev->hw->max_report_rates = 7; 11627 rt2x00dev->hw->max_rate_tries = 1; 11628 11629 /* 11630 * Initialize hw_mode information. 11631 */ 11632 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 11633 11634 switch (rt2x00dev->chip.rf) { 11635 case RF2720: 11636 case RF2820: 11637 spec->num_channels = 14; 11638 spec->channels = rf_vals; 11639 break; 11640 11641 case RF2750: 11642 case RF2850: 11643 spec->num_channels = ARRAY_SIZE(rf_vals); 11644 spec->channels = rf_vals; 11645 break; 11646 11647 case RF2020: 11648 case RF3020: 11649 case RF3021: 11650 case RF3022: 11651 case RF3070: 11652 case RF3290: 11653 case RF3320: 11654 case RF3322: 11655 case RF5350: 11656 case RF5360: 11657 case RF5362: 11658 case RF5370: 11659 case RF5372: 11660 case RF5390: 11661 case RF5392: 11662 spec->num_channels = 14; 11663 if (rt2800_clk_is_20mhz(rt2x00dev)) 11664 spec->channels = rf_vals_3x_xtal20; 11665 else 11666 spec->channels = rf_vals_3x; 11667 break; 11668 11669 case RF7620: 11670 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 11671 spec->channels = rf_vals_7620; 11672 break; 11673 11674 case RF3052: 11675 case RF3053: 11676 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 11677 spec->channels = rf_vals_3x; 11678 break; 11679 11680 case RF3853: 11681 spec->num_channels = ARRAY_SIZE(rf_vals_3853); 11682 spec->channels = rf_vals_3853; 11683 break; 11684 11685 case RF5592: 11686 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 11687 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 11688 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 11689 spec->channels = rf_vals_5592_xtal40; 11690 } else { 11691 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 11692 spec->channels = rf_vals_5592_xtal20; 11693 } 11694 break; 11695 } 11696 11697 if (WARN_ON_ONCE(!spec->channels)) 11698 return -ENODEV; 11699 11700 spec->supported_bands = SUPPORT_BAND_2GHZ; 11701 if (spec->num_channels > 14) 11702 spec->supported_bands |= SUPPORT_BAND_5GHZ; 11703 11704 /* 11705 * Initialize HT information. 11706 */ 11707 if (!rt2x00_rf(rt2x00dev, RF2020)) 11708 spec->ht.ht_supported = true; 11709 else 11710 spec->ht.ht_supported = false; 11711 11712 spec->ht.cap = 11713 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 11714 IEEE80211_HT_CAP_GRN_FLD | 11715 IEEE80211_HT_CAP_SGI_20 | 11716 IEEE80211_HT_CAP_SGI_40; 11717 11718 tx_chains = rt2x00dev->default_ant.tx_chain_num; 11719 rx_chains = rt2x00dev->default_ant.rx_chain_num; 11720 11721 if (tx_chains >= 2) 11722 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 11723 11724 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 11725 11726 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 11727 spec->ht.ampdu_density = 4; 11728 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 11729 if (tx_chains != rx_chains) { 11730 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 11731 spec->ht.mcs.tx_params |= 11732 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 11733 } 11734 11735 switch (rx_chains) { 11736 case 3: 11737 spec->ht.mcs.rx_mask[2] = 0xff; 11738 fallthrough; 11739 case 2: 11740 spec->ht.mcs.rx_mask[1] = 0xff; 11741 fallthrough; 11742 case 1: 11743 spec->ht.mcs.rx_mask[0] = 0xff; 11744 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 11745 break; 11746 } 11747 11748 /* 11749 * Create channel information and survey arrays 11750 */ 11751 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 11752 if (!info) 11753 return -ENOMEM; 11754 11755 rt2x00dev->chan_survey = 11756 kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey), 11757 GFP_KERNEL); 11758 if (!rt2x00dev->chan_survey) { 11759 kfree(info); 11760 return -ENOMEM; 11761 } 11762 11763 spec->channels_info = info; 11764 11765 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 11766 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 11767 11768 if (rt2x00dev->default_ant.tx_chain_num > 2) 11769 default_power3 = rt2800_eeprom_addr(rt2x00dev, 11770 EEPROM_EXT_TXPOWER_BG3); 11771 else 11772 default_power3 = NULL; 11773 11774 for (i = 0; i < 14; i++) { 11775 info[i].default_power1 = default_power1[i]; 11776 info[i].default_power2 = default_power2[i]; 11777 if (default_power3) 11778 info[i].default_power3 = default_power3[i]; 11779 } 11780 11781 if (spec->num_channels > 14) { 11782 default_power1 = rt2800_eeprom_addr(rt2x00dev, 11783 EEPROM_TXPOWER_A1); 11784 default_power2 = rt2800_eeprom_addr(rt2x00dev, 11785 EEPROM_TXPOWER_A2); 11786 11787 if (rt2x00dev->default_ant.tx_chain_num > 2) 11788 default_power3 = 11789 rt2800_eeprom_addr(rt2x00dev, 11790 EEPROM_EXT_TXPOWER_A3); 11791 else 11792 default_power3 = NULL; 11793 11794 for (i = 14; i < spec->num_channels; i++) { 11795 info[i].default_power1 = default_power1[i - 14]; 11796 info[i].default_power2 = default_power2[i - 14]; 11797 if (default_power3) 11798 info[i].default_power3 = default_power3[i - 14]; 11799 } 11800 } 11801 11802 switch (rt2x00dev->chip.rf) { 11803 case RF2020: 11804 case RF3020: 11805 case RF3021: 11806 case RF3022: 11807 case RF3320: 11808 case RF3052: 11809 case RF3053: 11810 case RF3070: 11811 case RF3290: 11812 case RF3853: 11813 case RF5350: 11814 case RF5360: 11815 case RF5362: 11816 case RF5370: 11817 case RF5372: 11818 case RF5390: 11819 case RF5392: 11820 case RF5592: 11821 case RF7620: 11822 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 11823 break; 11824 } 11825 11826 return 0; 11827 } 11828 11829 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 11830 { 11831 u32 reg; 11832 u32 rt; 11833 u32 rev; 11834 11835 if (rt2x00_rt(rt2x00dev, RT3290)) 11836 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 11837 else 11838 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 11839 11840 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 11841 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 11842 11843 switch (rt) { 11844 case RT2860: 11845 case RT2872: 11846 case RT2883: 11847 case RT3070: 11848 case RT3071: 11849 case RT3090: 11850 case RT3290: 11851 case RT3352: 11852 case RT3390: 11853 case RT3572: 11854 case RT3593: 11855 case RT3883: 11856 case RT5350: 11857 case RT5390: 11858 case RT5392: 11859 case RT5592: 11860 break; 11861 default: 11862 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 11863 rt, rev); 11864 return -ENODEV; 11865 } 11866 11867 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 11868 rt = RT6352; 11869 11870 rt2x00_set_rt(rt2x00dev, rt, rev); 11871 11872 return 0; 11873 } 11874 11875 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 11876 { 11877 int retval; 11878 u32 reg; 11879 11880 retval = rt2800_probe_rt(rt2x00dev); 11881 if (retval) 11882 return retval; 11883 11884 /* 11885 * Allocate eeprom data. 11886 */ 11887 retval = rt2800_validate_eeprom(rt2x00dev); 11888 if (retval) 11889 return retval; 11890 11891 retval = rt2800_init_eeprom(rt2x00dev); 11892 if (retval) 11893 return retval; 11894 11895 /* 11896 * Enable rfkill polling by setting GPIO direction of the 11897 * rfkill switch GPIO pin correctly. 11898 */ 11899 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 11900 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 11901 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 11902 11903 /* 11904 * Initialize hw specifications. 11905 */ 11906 retval = rt2800_probe_hw_mode(rt2x00dev); 11907 if (retval) 11908 return retval; 11909 11910 /* 11911 * Set device capabilities. 11912 */ 11913 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 11914 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 11915 if (!rt2x00_is_usb(rt2x00dev)) 11916 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 11917 11918 /* 11919 * Set device requirements. 11920 */ 11921 if (!rt2x00_is_soc(rt2x00dev)) 11922 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 11923 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 11924 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 11925 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 11926 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 11927 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 11928 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 11929 if (rt2x00_is_usb(rt2x00dev)) 11930 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 11931 else { 11932 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 11933 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 11934 } 11935 11936 if (modparam_watchdog) { 11937 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags); 11938 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100); 11939 } else { 11940 rt2x00dev->link.watchdog_disabled = true; 11941 } 11942 11943 /* 11944 * Set the rssi offset. 11945 */ 11946 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 11947 11948 return 0; 11949 } 11950 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 11951 11952 /* 11953 * IEEE80211 stack callback functions. 11954 */ 11955 void rt2800_get_key_seq(struct ieee80211_hw *hw, 11956 struct ieee80211_key_conf *key, 11957 struct ieee80211_key_seq *seq) 11958 { 11959 struct rt2x00_dev *rt2x00dev = hw->priv; 11960 struct mac_iveiv_entry iveiv_entry; 11961 u32 offset; 11962 11963 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 11964 return; 11965 11966 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 11967 rt2800_register_multiread(rt2x00dev, offset, 11968 &iveiv_entry, sizeof(iveiv_entry)); 11969 11970 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 11971 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 11972 } 11973 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 11974 11975 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 11976 { 11977 struct rt2x00_dev *rt2x00dev = hw->priv; 11978 u32 reg; 11979 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 11980 11981 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 11982 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 11983 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 11984 11985 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 11986 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 11987 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 11988 11989 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 11990 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 11991 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 11992 11993 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 11994 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 11995 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 11996 11997 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 11998 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 11999 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 12000 12001 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 12002 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 12003 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 12004 12005 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 12006 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 12007 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 12008 12009 return 0; 12010 } 12011 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 12012 12013 int rt2800_conf_tx(struct ieee80211_hw *hw, 12014 struct ieee80211_vif *vif, 12015 unsigned int link_id, u16 queue_idx, 12016 const struct ieee80211_tx_queue_params *params) 12017 { 12018 struct rt2x00_dev *rt2x00dev = hw->priv; 12019 struct data_queue *queue; 12020 struct rt2x00_field32 field; 12021 int retval; 12022 u32 reg; 12023 u32 offset; 12024 12025 /* 12026 * First pass the configuration through rt2x00lib, that will 12027 * update the queue settings and validate the input. After that 12028 * we are free to update the registers based on the value 12029 * in the queue parameter. 12030 */ 12031 retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params); 12032 if (retval) 12033 return retval; 12034 12035 /* 12036 * We only need to perform additional register initialization 12037 * for WMM queues/ 12038 */ 12039 if (queue_idx >= 4) 12040 return 0; 12041 12042 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 12043 12044 /* Update WMM TXOP register */ 12045 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 12046 field.bit_offset = (queue_idx & 1) * 16; 12047 field.bit_mask = 0xffff << field.bit_offset; 12048 12049 reg = rt2800_register_read(rt2x00dev, offset); 12050 rt2x00_set_field32(®, field, queue->txop); 12051 rt2800_register_write(rt2x00dev, offset, reg); 12052 12053 /* Update WMM registers */ 12054 field.bit_offset = queue_idx * 4; 12055 field.bit_mask = 0xf << field.bit_offset; 12056 12057 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 12058 rt2x00_set_field32(®, field, queue->aifs); 12059 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 12060 12061 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 12062 rt2x00_set_field32(®, field, queue->cw_min); 12063 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 12064 12065 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 12066 rt2x00_set_field32(®, field, queue->cw_max); 12067 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 12068 12069 /* Update EDCA registers */ 12070 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 12071 12072 reg = rt2800_register_read(rt2x00dev, offset); 12073 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 12074 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 12075 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 12076 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 12077 rt2800_register_write(rt2x00dev, offset, reg); 12078 12079 return 0; 12080 } 12081 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 12082 12083 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 12084 { 12085 struct rt2x00_dev *rt2x00dev = hw->priv; 12086 u64 tsf; 12087 u32 reg; 12088 12089 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 12090 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 12091 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 12092 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 12093 12094 return tsf; 12095 } 12096 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 12097 12098 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 12099 struct ieee80211_ampdu_params *params) 12100 { 12101 struct ieee80211_sta *sta = params->sta; 12102 enum ieee80211_ampdu_mlme_action action = params->action; 12103 u16 tid = params->tid; 12104 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 12105 int ret = 0; 12106 12107 /* 12108 * Don't allow aggregation for stations the hardware isn't aware 12109 * of because tx status reports for frames to an unknown station 12110 * always contain wcid=WCID_END+1 and thus we can't distinguish 12111 * between multiple stations which leads to unwanted situations 12112 * when the hw reorders frames due to aggregation. 12113 */ 12114 if (sta_priv->wcid > WCID_END) 12115 return -ENOSPC; 12116 12117 switch (action) { 12118 case IEEE80211_AMPDU_RX_START: 12119 case IEEE80211_AMPDU_RX_STOP: 12120 /* 12121 * The hw itself takes care of setting up BlockAck mechanisms. 12122 * So, we only have to allow mac80211 to nagotiate a BlockAck 12123 * agreement. Once that is done, the hw will BlockAck incoming 12124 * AMPDUs without further setup. 12125 */ 12126 break; 12127 case IEEE80211_AMPDU_TX_START: 12128 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 12129 break; 12130 case IEEE80211_AMPDU_TX_STOP_CONT: 12131 case IEEE80211_AMPDU_TX_STOP_FLUSH: 12132 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 12133 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 12134 break; 12135 case IEEE80211_AMPDU_TX_OPERATIONAL: 12136 break; 12137 default: 12138 rt2x00_warn((struct rt2x00_dev *)hw->priv, 12139 "Unknown AMPDU action\n"); 12140 } 12141 12142 return ret; 12143 } 12144 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 12145 12146 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 12147 struct survey_info *survey) 12148 { 12149 struct rt2x00_dev *rt2x00dev = hw->priv; 12150 struct rt2x00_chan_survey *chan_survey = 12151 &rt2x00dev->chan_survey[idx]; 12152 enum nl80211_band band = NL80211_BAND_2GHZ; 12153 12154 if (idx >= rt2x00dev->bands[band].n_channels) { 12155 idx -= rt2x00dev->bands[band].n_channels; 12156 band = NL80211_BAND_5GHZ; 12157 } 12158 12159 if (idx >= rt2x00dev->bands[band].n_channels) 12160 return -ENOENT; 12161 12162 if (idx == 0) 12163 rt2800_update_survey(rt2x00dev); 12164 12165 survey->channel = &rt2x00dev->bands[band].channels[idx]; 12166 12167 survey->filled = SURVEY_INFO_TIME | 12168 SURVEY_INFO_TIME_BUSY | 12169 SURVEY_INFO_TIME_EXT_BUSY; 12170 12171 survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000); 12172 survey->time_busy = div_u64(chan_survey->time_busy, 1000); 12173 survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000); 12174 12175 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 12176 survey->filled |= SURVEY_INFO_IN_USE; 12177 12178 return 0; 12179 12180 } 12181 EXPORT_SYMBOL_GPL(rt2800_get_survey); 12182 12183 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 12184 MODULE_VERSION(DRV_VERSION); 12185 MODULE_DESCRIPTION("Ralink RT2800 library"); 12186 MODULE_LICENSE("GPL"); 12187